1 /* SPDX-License-Identifier: BSD-3-Clause 2 * Copyright 2016 6WIND S.A. 3 * Copyright 2016 Mellanox Technologies, Ltd 4 */ 5 6 #include <stdalign.h> 7 #include <stdint.h> 8 #include <string.h> 9 #include <stdbool.h> 10 #include <sys/queue.h> 11 12 #include <rte_common.h> 13 #include <rte_ether.h> 14 #include <ethdev_driver.h> 15 #include <rte_eal_paging.h> 16 #include <rte_flow.h> 17 #include <rte_cycles.h> 18 #include <rte_flow_driver.h> 19 #include <rte_malloc.h> 20 #include <rte_ip.h> 21 22 #include <mlx5_glue.h> 23 #include <mlx5_devx_cmds.h> 24 #include <mlx5_prm.h> 25 #include <mlx5_malloc.h> 26 27 #include "mlx5_defs.h" 28 #include "mlx5.h" 29 #include "mlx5_flow.h" 30 #include "mlx5_flow_os.h" 31 #include "mlx5_rx.h" 32 #include "mlx5_tx.h" 33 #include "mlx5_common_os.h" 34 #include "rte_pmd_mlx5.h" 35 36 struct tunnel_default_miss_ctx { 37 uint16_t *queue; 38 __extension__ 39 union { 40 struct rte_flow_action_rss action_rss; 41 struct rte_flow_action_queue miss_queue; 42 struct rte_flow_action_jump miss_jump; 43 uint8_t raw[0]; 44 }; 45 }; 46 47 static int 48 flow_tunnel_add_default_miss(struct rte_eth_dev *dev, 49 struct rte_flow *flow, 50 const struct rte_flow_attr *attr, 51 const struct rte_flow_action *app_actions, 52 uint32_t flow_idx, 53 const struct mlx5_flow_tunnel *tunnel, 54 struct tunnel_default_miss_ctx *ctx, 55 struct rte_flow_error *error); 56 static struct mlx5_flow_tunnel * 57 mlx5_find_tunnel_id(struct rte_eth_dev *dev, uint32_t id); 58 static void 59 mlx5_flow_tunnel_free(struct rte_eth_dev *dev, struct mlx5_flow_tunnel *tunnel); 60 static uint32_t 61 tunnel_flow_group_to_flow_table(struct rte_eth_dev *dev, 62 const struct mlx5_flow_tunnel *tunnel, 63 uint32_t group, uint32_t *table, 64 struct rte_flow_error *error); 65 66 static struct mlx5_flow_workspace *mlx5_flow_push_thread_workspace(void); 67 static void mlx5_flow_pop_thread_workspace(void); 68 69 70 /** Device flow drivers. */ 71 extern const struct mlx5_flow_driver_ops mlx5_flow_verbs_drv_ops; 72 73 const struct mlx5_flow_driver_ops mlx5_flow_null_drv_ops; 74 75 const struct mlx5_flow_driver_ops *flow_drv_ops[] = { 76 [MLX5_FLOW_TYPE_MIN] = &mlx5_flow_null_drv_ops, 77 #if defined(HAVE_IBV_FLOW_DV_SUPPORT) || !defined(HAVE_INFINIBAND_VERBS_H) 78 [MLX5_FLOW_TYPE_DV] = &mlx5_flow_dv_drv_ops, 79 #endif 80 [MLX5_FLOW_TYPE_VERBS] = &mlx5_flow_verbs_drv_ops, 81 [MLX5_FLOW_TYPE_MAX] = &mlx5_flow_null_drv_ops 82 }; 83 84 /** Helper macro to build input graph for mlx5_flow_expand_rss(). */ 85 #define MLX5_FLOW_EXPAND_RSS_NEXT(...) \ 86 (const int []){ \ 87 __VA_ARGS__, 0, \ 88 } 89 90 /** Node object of input graph for mlx5_flow_expand_rss(). */ 91 struct mlx5_flow_expand_node { 92 const int *const next; 93 /**< 94 * List of next node indexes. Index 0 is interpreted as a terminator. 95 */ 96 const enum rte_flow_item_type type; 97 /**< Pattern item type of current node. */ 98 uint64_t rss_types; 99 /**< 100 * RSS types bit-field associated with this node 101 * (see RTE_ETH_RSS_* definitions). 102 */ 103 uint64_t node_flags; 104 /**< 105 * Bit-fields that define how the node is used in the expansion. 106 * (see MLX5_EXPANSION_NODE_* definitions). 107 */ 108 }; 109 110 /* Optional expand field. The expansion alg will not go deeper. */ 111 #define MLX5_EXPANSION_NODE_OPTIONAL (UINT64_C(1) << 0) 112 113 /* The node is not added implicitly as expansion to the flow pattern. 114 * If the node type does not match the flow pattern item type, the 115 * expansion alg will go deeper to its next items. 116 * In the current implementation, the list of next nodes indexes can 117 * have up to one node with this flag set and it has to be the last 118 * node index (before the list terminator). 119 */ 120 #define MLX5_EXPANSION_NODE_EXPLICIT (UINT64_C(1) << 1) 121 122 /** Object returned by mlx5_flow_expand_rss(). */ 123 struct mlx5_flow_expand_rss { 124 uint32_t entries; 125 /**< Number of entries @p patterns and @p priorities. */ 126 struct { 127 struct rte_flow_item *pattern; /**< Expanded pattern array. */ 128 uint32_t priority; /**< Priority offset for each expansion. */ 129 } entry[]; 130 }; 131 132 static void 133 mlx5_dbg__print_pattern(const struct rte_flow_item *item); 134 135 static const struct mlx5_flow_expand_node * 136 mlx5_flow_expand_rss_adjust_node(const struct rte_flow_item *pattern, 137 unsigned int item_idx, 138 const struct mlx5_flow_expand_node graph[], 139 const struct mlx5_flow_expand_node *node); 140 141 static bool 142 mlx5_flow_is_rss_expandable_item(const struct rte_flow_item *item) 143 { 144 switch (item->type) { 145 case RTE_FLOW_ITEM_TYPE_ETH: 146 case RTE_FLOW_ITEM_TYPE_VLAN: 147 case RTE_FLOW_ITEM_TYPE_IPV4: 148 case RTE_FLOW_ITEM_TYPE_IPV6: 149 case RTE_FLOW_ITEM_TYPE_UDP: 150 case RTE_FLOW_ITEM_TYPE_TCP: 151 case RTE_FLOW_ITEM_TYPE_VXLAN: 152 case RTE_FLOW_ITEM_TYPE_NVGRE: 153 case RTE_FLOW_ITEM_TYPE_GRE: 154 case RTE_FLOW_ITEM_TYPE_GENEVE: 155 case RTE_FLOW_ITEM_TYPE_MPLS: 156 case RTE_FLOW_ITEM_TYPE_VXLAN_GPE: 157 case RTE_FLOW_ITEM_TYPE_GRE_KEY: 158 case RTE_FLOW_ITEM_TYPE_IPV6_FRAG_EXT: 159 case RTE_FLOW_ITEM_TYPE_GTP: 160 return true; 161 default: 162 break; 163 } 164 return false; 165 } 166 167 static enum rte_flow_item_type 168 mlx5_flow_expand_rss_item_complete(const struct rte_flow_item *item) 169 { 170 enum rte_flow_item_type ret = RTE_FLOW_ITEM_TYPE_VOID; 171 uint16_t ether_type = 0; 172 uint16_t ether_type_m; 173 uint8_t ip_next_proto = 0; 174 uint8_t ip_next_proto_m; 175 176 if (item == NULL || item->spec == NULL) 177 return ret; 178 switch (item->type) { 179 case RTE_FLOW_ITEM_TYPE_ETH: 180 if (item->mask) 181 ether_type_m = ((const struct rte_flow_item_eth *) 182 (item->mask))->type; 183 else 184 ether_type_m = rte_flow_item_eth_mask.type; 185 if (ether_type_m != RTE_BE16(0xFFFF)) 186 break; 187 ether_type = ((const struct rte_flow_item_eth *) 188 (item->spec))->type; 189 if (rte_be_to_cpu_16(ether_type) == RTE_ETHER_TYPE_IPV4) 190 ret = RTE_FLOW_ITEM_TYPE_IPV4; 191 else if (rte_be_to_cpu_16(ether_type) == RTE_ETHER_TYPE_IPV6) 192 ret = RTE_FLOW_ITEM_TYPE_IPV6; 193 else if (rte_be_to_cpu_16(ether_type) == RTE_ETHER_TYPE_VLAN) 194 ret = RTE_FLOW_ITEM_TYPE_VLAN; 195 else 196 ret = RTE_FLOW_ITEM_TYPE_END; 197 break; 198 case RTE_FLOW_ITEM_TYPE_VLAN: 199 if (item->mask) 200 ether_type_m = ((const struct rte_flow_item_vlan *) 201 (item->mask))->inner_type; 202 else 203 ether_type_m = rte_flow_item_vlan_mask.inner_type; 204 if (ether_type_m != RTE_BE16(0xFFFF)) 205 break; 206 ether_type = ((const struct rte_flow_item_vlan *) 207 (item->spec))->inner_type; 208 if (rte_be_to_cpu_16(ether_type) == RTE_ETHER_TYPE_IPV4) 209 ret = RTE_FLOW_ITEM_TYPE_IPV4; 210 else if (rte_be_to_cpu_16(ether_type) == RTE_ETHER_TYPE_IPV6) 211 ret = RTE_FLOW_ITEM_TYPE_IPV6; 212 else if (rte_be_to_cpu_16(ether_type) == RTE_ETHER_TYPE_VLAN) 213 ret = RTE_FLOW_ITEM_TYPE_VLAN; 214 else 215 ret = RTE_FLOW_ITEM_TYPE_END; 216 break; 217 case RTE_FLOW_ITEM_TYPE_IPV4: 218 if (item->mask) 219 ip_next_proto_m = ((const struct rte_flow_item_ipv4 *) 220 (item->mask))->hdr.next_proto_id; 221 else 222 ip_next_proto_m = 223 rte_flow_item_ipv4_mask.hdr.next_proto_id; 224 if (ip_next_proto_m != 0xFF) 225 break; 226 ip_next_proto = ((const struct rte_flow_item_ipv4 *) 227 (item->spec))->hdr.next_proto_id; 228 if (ip_next_proto == IPPROTO_UDP) 229 ret = RTE_FLOW_ITEM_TYPE_UDP; 230 else if (ip_next_proto == IPPROTO_TCP) 231 ret = RTE_FLOW_ITEM_TYPE_TCP; 232 else if (ip_next_proto == IPPROTO_IP) 233 ret = RTE_FLOW_ITEM_TYPE_IPV4; 234 else if (ip_next_proto == IPPROTO_IPV6) 235 ret = RTE_FLOW_ITEM_TYPE_IPV6; 236 else 237 ret = RTE_FLOW_ITEM_TYPE_END; 238 break; 239 case RTE_FLOW_ITEM_TYPE_IPV6: 240 if (item->mask) 241 ip_next_proto_m = ((const struct rte_flow_item_ipv6 *) 242 (item->mask))->hdr.proto; 243 else 244 ip_next_proto_m = 245 rte_flow_item_ipv6_mask.hdr.proto; 246 if (ip_next_proto_m != 0xFF) 247 break; 248 ip_next_proto = ((const struct rte_flow_item_ipv6 *) 249 (item->spec))->hdr.proto; 250 if (ip_next_proto == IPPROTO_UDP) 251 ret = RTE_FLOW_ITEM_TYPE_UDP; 252 else if (ip_next_proto == IPPROTO_TCP) 253 ret = RTE_FLOW_ITEM_TYPE_TCP; 254 else if (ip_next_proto == IPPROTO_IP) 255 ret = RTE_FLOW_ITEM_TYPE_IPV4; 256 else if (ip_next_proto == IPPROTO_IPV6) 257 ret = RTE_FLOW_ITEM_TYPE_IPV6; 258 else 259 ret = RTE_FLOW_ITEM_TYPE_END; 260 break; 261 case RTE_FLOW_ITEM_TYPE_GENEVE: 262 ether_type_m = item->mask ? 263 ((const struct rte_flow_item_geneve *) 264 (item->mask))->protocol : 265 rte_flow_item_geneve_mask.protocol; 266 ether_type = ((const struct rte_flow_item_geneve *) 267 (item->spec))->protocol; 268 ether_type_m = rte_be_to_cpu_16(ether_type_m); 269 ether_type = rte_be_to_cpu_16(ether_type); 270 switch (ether_type_m & ether_type) { 271 case RTE_ETHER_TYPE_TEB: 272 ret = RTE_FLOW_ITEM_TYPE_ETH; 273 break; 274 case RTE_ETHER_TYPE_IPV4: 275 ret = RTE_FLOW_ITEM_TYPE_IPV4; 276 break; 277 case RTE_ETHER_TYPE_IPV6: 278 ret = RTE_FLOW_ITEM_TYPE_IPV6; 279 break; 280 default: 281 ret = RTE_FLOW_ITEM_TYPE_END; 282 } 283 break; 284 default: 285 ret = RTE_FLOW_ITEM_TYPE_VOID; 286 break; 287 } 288 return ret; 289 } 290 291 static const int * 292 mlx5_flow_expand_rss_skip_explicit(const struct mlx5_flow_expand_node graph[], 293 const int *next_node) 294 { 295 const struct mlx5_flow_expand_node *node = NULL; 296 const int *next = next_node; 297 298 while (next && *next) { 299 /* 300 * Skip the nodes with the MLX5_EXPANSION_NODE_EXPLICIT 301 * flag set, because they were not found in the flow pattern. 302 */ 303 node = &graph[*next]; 304 if (!(node->node_flags & MLX5_EXPANSION_NODE_EXPLICIT)) 305 break; 306 next = node->next; 307 } 308 return next; 309 } 310 311 #define MLX5_RSS_EXP_ELT_N 16 312 313 /** 314 * Expand RSS flows into several possible flows according to the RSS hash 315 * fields requested and the driver capabilities. 316 * 317 * @param[out] buf 318 * Buffer to store the result expansion. 319 * @param[in] size 320 * Buffer size in bytes. If 0, @p buf can be NULL. 321 * @param[in] pattern 322 * User flow pattern. 323 * @param[in] types 324 * RSS types to expand (see RTE_ETH_RSS_* definitions). 325 * @param[in] graph 326 * Input graph to expand @p pattern according to @p types. 327 * @param[in] graph_root_index 328 * Index of root node in @p graph, typically 0. 329 * 330 * @return 331 * A positive value representing the size of @p buf in bytes regardless of 332 * @p size on success, a negative errno value otherwise and rte_errno is 333 * set, the following errors are defined: 334 * 335 * -E2BIG: graph-depth @p graph is too deep. 336 * -EINVAL: @p size has not enough space for expanded pattern. 337 */ 338 static int 339 mlx5_flow_expand_rss(struct mlx5_flow_expand_rss *buf, size_t size, 340 const struct rte_flow_item *pattern, uint64_t types, 341 const struct mlx5_flow_expand_node graph[], 342 int graph_root_index) 343 { 344 const struct rte_flow_item *item; 345 const struct mlx5_flow_expand_node *node = &graph[graph_root_index]; 346 const int *next_node; 347 const int *stack[MLX5_RSS_EXP_ELT_N]; 348 int stack_pos = 0; 349 struct rte_flow_item flow_items[MLX5_RSS_EXP_ELT_N]; 350 unsigned int i, item_idx, last_expand_item_idx = 0; 351 size_t lsize; 352 size_t user_pattern_size = 0; 353 void *addr = NULL; 354 const struct mlx5_flow_expand_node *next = NULL; 355 struct rte_flow_item missed_item; 356 int missed = 0; 357 int elt = 0; 358 const struct rte_flow_item *last_expand_item = NULL; 359 360 memset(&missed_item, 0, sizeof(missed_item)); 361 lsize = offsetof(struct mlx5_flow_expand_rss, entry) + 362 MLX5_RSS_EXP_ELT_N * sizeof(buf->entry[0]); 363 if (lsize > size) 364 return -EINVAL; 365 buf->entry[0].priority = 0; 366 buf->entry[0].pattern = (void *)&buf->entry[MLX5_RSS_EXP_ELT_N]; 367 buf->entries = 0; 368 addr = buf->entry[0].pattern; 369 for (item = pattern, item_idx = 0; 370 item->type != RTE_FLOW_ITEM_TYPE_END; 371 item++, item_idx++) { 372 if (!mlx5_flow_is_rss_expandable_item(item)) { 373 user_pattern_size += sizeof(*item); 374 continue; 375 } 376 last_expand_item = item; 377 last_expand_item_idx = item_idx; 378 i = 0; 379 while (node->next && node->next[i]) { 380 next = &graph[node->next[i]]; 381 if (next->type == item->type) 382 break; 383 if (next->node_flags & MLX5_EXPANSION_NODE_EXPLICIT) { 384 node = next; 385 i = 0; 386 } else { 387 ++i; 388 } 389 } 390 if (next) 391 node = next; 392 user_pattern_size += sizeof(*item); 393 } 394 user_pattern_size += sizeof(*item); /* Handle END item. */ 395 lsize += user_pattern_size; 396 if (lsize > size) 397 return -EINVAL; 398 /* Copy the user pattern in the first entry of the buffer. */ 399 rte_memcpy(addr, pattern, user_pattern_size); 400 addr = (void *)(((uintptr_t)addr) + user_pattern_size); 401 buf->entries = 1; 402 /* Start expanding. */ 403 memset(flow_items, 0, sizeof(flow_items)); 404 user_pattern_size -= sizeof(*item); 405 /* 406 * Check if the last valid item has spec set, need complete pattern, 407 * and the pattern can be used for expansion. 408 */ 409 missed_item.type = mlx5_flow_expand_rss_item_complete(last_expand_item); 410 if (missed_item.type == RTE_FLOW_ITEM_TYPE_END) { 411 /* Item type END indicates expansion is not required. */ 412 return lsize; 413 } 414 if (missed_item.type != RTE_FLOW_ITEM_TYPE_VOID) { 415 next = NULL; 416 missed = 1; 417 i = 0; 418 while (node->next && node->next[i]) { 419 next = &graph[node->next[i]]; 420 if (next->type == missed_item.type) { 421 flow_items[0].type = missed_item.type; 422 flow_items[1].type = RTE_FLOW_ITEM_TYPE_END; 423 break; 424 } 425 if (next->node_flags & MLX5_EXPANSION_NODE_EXPLICIT) { 426 node = next; 427 i = 0; 428 } else { 429 ++i; 430 } 431 next = NULL; 432 } 433 } 434 if (next && missed) { 435 elt = 2; /* missed item + item end. */ 436 node = next; 437 lsize += elt * sizeof(*item) + user_pattern_size; 438 if (lsize > size) 439 return -EINVAL; 440 if (node->rss_types & types) { 441 buf->entry[buf->entries].priority = 1; 442 buf->entry[buf->entries].pattern = addr; 443 buf->entries++; 444 rte_memcpy(addr, buf->entry[0].pattern, 445 user_pattern_size); 446 addr = (void *)(((uintptr_t)addr) + user_pattern_size); 447 rte_memcpy(addr, flow_items, elt * sizeof(*item)); 448 addr = (void *)(((uintptr_t)addr) + 449 elt * sizeof(*item)); 450 } 451 } else if (last_expand_item != NULL) { 452 node = mlx5_flow_expand_rss_adjust_node(pattern, 453 last_expand_item_idx, graph, node); 454 } 455 memset(flow_items, 0, sizeof(flow_items)); 456 next_node = mlx5_flow_expand_rss_skip_explicit(graph, 457 node->next); 458 stack[stack_pos] = next_node; 459 node = next_node ? &graph[*next_node] : NULL; 460 while (node) { 461 flow_items[stack_pos].type = node->type; 462 if (node->rss_types & types) { 463 size_t n; 464 /* 465 * compute the number of items to copy from the 466 * expansion and copy it. 467 * When the stack_pos is 0, there are 1 element in it, 468 * plus the addition END item. 469 */ 470 elt = stack_pos + 2; 471 flow_items[stack_pos + 1].type = RTE_FLOW_ITEM_TYPE_END; 472 lsize += elt * sizeof(*item) + user_pattern_size; 473 if (lsize > size) 474 return -EINVAL; 475 n = elt * sizeof(*item); 476 buf->entry[buf->entries].priority = 477 stack_pos + 1 + missed; 478 buf->entry[buf->entries].pattern = addr; 479 buf->entries++; 480 rte_memcpy(addr, buf->entry[0].pattern, 481 user_pattern_size); 482 addr = (void *)(((uintptr_t)addr) + 483 user_pattern_size); 484 rte_memcpy(addr, &missed_item, 485 missed * sizeof(*item)); 486 addr = (void *)(((uintptr_t)addr) + 487 missed * sizeof(*item)); 488 rte_memcpy(addr, flow_items, n); 489 addr = (void *)(((uintptr_t)addr) + n); 490 } 491 /* Go deeper. */ 492 if (!(node->node_flags & MLX5_EXPANSION_NODE_OPTIONAL) && 493 node->next) { 494 next_node = mlx5_flow_expand_rss_skip_explicit(graph, 495 node->next); 496 if (stack_pos++ == MLX5_RSS_EXP_ELT_N) { 497 rte_errno = E2BIG; 498 return -rte_errno; 499 } 500 stack[stack_pos] = next_node; 501 } else if (*(next_node + 1)) { 502 /* Follow up with the next possibility. */ 503 next_node = mlx5_flow_expand_rss_skip_explicit(graph, 504 ++next_node); 505 } else if (!stack_pos) { 506 /* 507 * Completing the traverse over the different paths. 508 * The next_node is advanced to the terminator. 509 */ 510 ++next_node; 511 } else { 512 /* Move to the next path. */ 513 while (stack_pos) { 514 next_node = stack[--stack_pos]; 515 next_node++; 516 if (*next_node) 517 break; 518 } 519 next_node = mlx5_flow_expand_rss_skip_explicit(graph, 520 next_node); 521 stack[stack_pos] = next_node; 522 } 523 node = next_node && *next_node ? &graph[*next_node] : NULL; 524 }; 525 return lsize; 526 } 527 528 enum mlx5_expansion { 529 MLX5_EXPANSION_ROOT, 530 MLX5_EXPANSION_ROOT_OUTER, 531 MLX5_EXPANSION_OUTER_ETH, 532 MLX5_EXPANSION_OUTER_VLAN, 533 MLX5_EXPANSION_OUTER_IPV4, 534 MLX5_EXPANSION_OUTER_IPV4_UDP, 535 MLX5_EXPANSION_OUTER_IPV4_TCP, 536 MLX5_EXPANSION_OUTER_IPV6, 537 MLX5_EXPANSION_OUTER_IPV6_UDP, 538 MLX5_EXPANSION_OUTER_IPV6_TCP, 539 MLX5_EXPANSION_VXLAN, 540 MLX5_EXPANSION_STD_VXLAN, 541 MLX5_EXPANSION_L3_VXLAN, 542 MLX5_EXPANSION_VXLAN_GPE, 543 MLX5_EXPANSION_GRE, 544 MLX5_EXPANSION_NVGRE, 545 MLX5_EXPANSION_GRE_KEY, 546 MLX5_EXPANSION_MPLS, 547 MLX5_EXPANSION_ETH, 548 MLX5_EXPANSION_VLAN, 549 MLX5_EXPANSION_IPV4, 550 MLX5_EXPANSION_IPV4_UDP, 551 MLX5_EXPANSION_IPV4_TCP, 552 MLX5_EXPANSION_IPV6, 553 MLX5_EXPANSION_IPV6_UDP, 554 MLX5_EXPANSION_IPV6_TCP, 555 MLX5_EXPANSION_IPV6_FRAG_EXT, 556 MLX5_EXPANSION_GTP, 557 MLX5_EXPANSION_GENEVE, 558 }; 559 560 /** Supported expansion of items. */ 561 static const struct mlx5_flow_expand_node mlx5_support_expansion[] = { 562 [MLX5_EXPANSION_ROOT] = { 563 .next = MLX5_FLOW_EXPAND_RSS_NEXT(MLX5_EXPANSION_ETH, 564 MLX5_EXPANSION_IPV4, 565 MLX5_EXPANSION_IPV6), 566 .type = RTE_FLOW_ITEM_TYPE_END, 567 }, 568 [MLX5_EXPANSION_ROOT_OUTER] = { 569 .next = MLX5_FLOW_EXPAND_RSS_NEXT(MLX5_EXPANSION_OUTER_ETH, 570 MLX5_EXPANSION_OUTER_IPV4, 571 MLX5_EXPANSION_OUTER_IPV6), 572 .type = RTE_FLOW_ITEM_TYPE_END, 573 }, 574 [MLX5_EXPANSION_OUTER_ETH] = { 575 .next = MLX5_FLOW_EXPAND_RSS_NEXT(MLX5_EXPANSION_OUTER_VLAN), 576 .type = RTE_FLOW_ITEM_TYPE_ETH, 577 .rss_types = 0, 578 }, 579 [MLX5_EXPANSION_OUTER_VLAN] = { 580 .next = MLX5_FLOW_EXPAND_RSS_NEXT(MLX5_EXPANSION_OUTER_IPV4, 581 MLX5_EXPANSION_OUTER_IPV6), 582 .type = RTE_FLOW_ITEM_TYPE_VLAN, 583 .node_flags = MLX5_EXPANSION_NODE_EXPLICIT, 584 }, 585 [MLX5_EXPANSION_OUTER_IPV4] = { 586 .next = MLX5_FLOW_EXPAND_RSS_NEXT 587 (MLX5_EXPANSION_OUTER_IPV4_UDP, 588 MLX5_EXPANSION_OUTER_IPV4_TCP, 589 MLX5_EXPANSION_GRE, 590 MLX5_EXPANSION_NVGRE, 591 MLX5_EXPANSION_IPV4, 592 MLX5_EXPANSION_IPV6), 593 .type = RTE_FLOW_ITEM_TYPE_IPV4, 594 .rss_types = RTE_ETH_RSS_IPV4 | RTE_ETH_RSS_FRAG_IPV4 | 595 RTE_ETH_RSS_NONFRAG_IPV4_OTHER, 596 }, 597 [MLX5_EXPANSION_OUTER_IPV4_UDP] = { 598 .next = MLX5_FLOW_EXPAND_RSS_NEXT(MLX5_EXPANSION_VXLAN, 599 MLX5_EXPANSION_VXLAN_GPE, 600 MLX5_EXPANSION_MPLS, 601 MLX5_EXPANSION_GENEVE, 602 MLX5_EXPANSION_GTP), 603 .type = RTE_FLOW_ITEM_TYPE_UDP, 604 .rss_types = RTE_ETH_RSS_NONFRAG_IPV4_UDP, 605 }, 606 [MLX5_EXPANSION_OUTER_IPV4_TCP] = { 607 .type = RTE_FLOW_ITEM_TYPE_TCP, 608 .rss_types = RTE_ETH_RSS_NONFRAG_IPV4_TCP, 609 }, 610 [MLX5_EXPANSION_OUTER_IPV6] = { 611 .next = MLX5_FLOW_EXPAND_RSS_NEXT 612 (MLX5_EXPANSION_OUTER_IPV6_UDP, 613 MLX5_EXPANSION_OUTER_IPV6_TCP, 614 MLX5_EXPANSION_IPV4, 615 MLX5_EXPANSION_IPV6, 616 MLX5_EXPANSION_GRE, 617 MLX5_EXPANSION_NVGRE), 618 .type = RTE_FLOW_ITEM_TYPE_IPV6, 619 .rss_types = RTE_ETH_RSS_IPV6 | RTE_ETH_RSS_FRAG_IPV6 | 620 RTE_ETH_RSS_NONFRAG_IPV6_OTHER, 621 }, 622 [MLX5_EXPANSION_OUTER_IPV6_UDP] = { 623 .next = MLX5_FLOW_EXPAND_RSS_NEXT(MLX5_EXPANSION_VXLAN, 624 MLX5_EXPANSION_VXLAN_GPE, 625 MLX5_EXPANSION_MPLS, 626 MLX5_EXPANSION_GENEVE, 627 MLX5_EXPANSION_GTP), 628 .type = RTE_FLOW_ITEM_TYPE_UDP, 629 .rss_types = RTE_ETH_RSS_NONFRAG_IPV6_UDP, 630 }, 631 [MLX5_EXPANSION_OUTER_IPV6_TCP] = { 632 .type = RTE_FLOW_ITEM_TYPE_TCP, 633 .rss_types = RTE_ETH_RSS_NONFRAG_IPV6_TCP, 634 }, 635 [MLX5_EXPANSION_VXLAN] = { 636 .next = MLX5_FLOW_EXPAND_RSS_NEXT(MLX5_EXPANSION_ETH, 637 MLX5_EXPANSION_IPV4, 638 MLX5_EXPANSION_IPV6), 639 .type = RTE_FLOW_ITEM_TYPE_VXLAN, 640 }, 641 [MLX5_EXPANSION_STD_VXLAN] = { 642 .next = MLX5_FLOW_EXPAND_RSS_NEXT(MLX5_EXPANSION_ETH), 643 .type = RTE_FLOW_ITEM_TYPE_VXLAN, 644 }, 645 [MLX5_EXPANSION_L3_VXLAN] = { 646 .next = MLX5_FLOW_EXPAND_RSS_NEXT(MLX5_EXPANSION_IPV4, 647 MLX5_EXPANSION_IPV6), 648 .type = RTE_FLOW_ITEM_TYPE_VXLAN, 649 }, 650 [MLX5_EXPANSION_VXLAN_GPE] = { 651 .next = MLX5_FLOW_EXPAND_RSS_NEXT(MLX5_EXPANSION_ETH, 652 MLX5_EXPANSION_IPV4, 653 MLX5_EXPANSION_IPV6), 654 .type = RTE_FLOW_ITEM_TYPE_VXLAN_GPE, 655 }, 656 [MLX5_EXPANSION_GRE] = { 657 .next = MLX5_FLOW_EXPAND_RSS_NEXT(MLX5_EXPANSION_IPV4, 658 MLX5_EXPANSION_IPV6, 659 MLX5_EXPANSION_GRE_KEY, 660 MLX5_EXPANSION_MPLS), 661 .type = RTE_FLOW_ITEM_TYPE_GRE, 662 }, 663 [MLX5_EXPANSION_GRE_KEY] = { 664 .next = MLX5_FLOW_EXPAND_RSS_NEXT(MLX5_EXPANSION_IPV4, 665 MLX5_EXPANSION_IPV6, 666 MLX5_EXPANSION_MPLS), 667 .type = RTE_FLOW_ITEM_TYPE_GRE_KEY, 668 .node_flags = MLX5_EXPANSION_NODE_OPTIONAL, 669 }, 670 [MLX5_EXPANSION_NVGRE] = { 671 .next = MLX5_FLOW_EXPAND_RSS_NEXT(MLX5_EXPANSION_ETH), 672 .type = RTE_FLOW_ITEM_TYPE_NVGRE, 673 }, 674 [MLX5_EXPANSION_MPLS] = { 675 .next = MLX5_FLOW_EXPAND_RSS_NEXT(MLX5_EXPANSION_IPV4, 676 MLX5_EXPANSION_IPV6, 677 MLX5_EXPANSION_ETH), 678 .type = RTE_FLOW_ITEM_TYPE_MPLS, 679 .node_flags = MLX5_EXPANSION_NODE_OPTIONAL, 680 }, 681 [MLX5_EXPANSION_ETH] = { 682 .next = MLX5_FLOW_EXPAND_RSS_NEXT(MLX5_EXPANSION_VLAN), 683 .type = RTE_FLOW_ITEM_TYPE_ETH, 684 }, 685 [MLX5_EXPANSION_VLAN] = { 686 .next = MLX5_FLOW_EXPAND_RSS_NEXT(MLX5_EXPANSION_IPV4, 687 MLX5_EXPANSION_IPV6), 688 .type = RTE_FLOW_ITEM_TYPE_VLAN, 689 .node_flags = MLX5_EXPANSION_NODE_EXPLICIT, 690 }, 691 [MLX5_EXPANSION_IPV4] = { 692 .next = MLX5_FLOW_EXPAND_RSS_NEXT(MLX5_EXPANSION_IPV4_UDP, 693 MLX5_EXPANSION_IPV4_TCP), 694 .type = RTE_FLOW_ITEM_TYPE_IPV4, 695 .rss_types = RTE_ETH_RSS_IPV4 | RTE_ETH_RSS_FRAG_IPV4 | 696 RTE_ETH_RSS_NONFRAG_IPV4_OTHER, 697 }, 698 [MLX5_EXPANSION_IPV4_UDP] = { 699 .type = RTE_FLOW_ITEM_TYPE_UDP, 700 .rss_types = RTE_ETH_RSS_NONFRAG_IPV4_UDP, 701 }, 702 [MLX5_EXPANSION_IPV4_TCP] = { 703 .type = RTE_FLOW_ITEM_TYPE_TCP, 704 .rss_types = RTE_ETH_RSS_NONFRAG_IPV4_TCP, 705 }, 706 [MLX5_EXPANSION_IPV6] = { 707 .next = MLX5_FLOW_EXPAND_RSS_NEXT(MLX5_EXPANSION_IPV6_UDP, 708 MLX5_EXPANSION_IPV6_TCP, 709 MLX5_EXPANSION_IPV6_FRAG_EXT), 710 .type = RTE_FLOW_ITEM_TYPE_IPV6, 711 .rss_types = RTE_ETH_RSS_IPV6 | RTE_ETH_RSS_FRAG_IPV6 | 712 RTE_ETH_RSS_NONFRAG_IPV6_OTHER, 713 }, 714 [MLX5_EXPANSION_IPV6_UDP] = { 715 .type = RTE_FLOW_ITEM_TYPE_UDP, 716 .rss_types = RTE_ETH_RSS_NONFRAG_IPV6_UDP, 717 }, 718 [MLX5_EXPANSION_IPV6_TCP] = { 719 .type = RTE_FLOW_ITEM_TYPE_TCP, 720 .rss_types = RTE_ETH_RSS_NONFRAG_IPV6_TCP, 721 }, 722 [MLX5_EXPANSION_IPV6_FRAG_EXT] = { 723 .type = RTE_FLOW_ITEM_TYPE_IPV6_FRAG_EXT, 724 }, 725 [MLX5_EXPANSION_GTP] = { 726 .next = MLX5_FLOW_EXPAND_RSS_NEXT(MLX5_EXPANSION_IPV4, 727 MLX5_EXPANSION_IPV6), 728 .type = RTE_FLOW_ITEM_TYPE_GTP, 729 }, 730 [MLX5_EXPANSION_GENEVE] = { 731 .next = MLX5_FLOW_EXPAND_RSS_NEXT(MLX5_EXPANSION_ETH, 732 MLX5_EXPANSION_IPV4, 733 MLX5_EXPANSION_IPV6), 734 .type = RTE_FLOW_ITEM_TYPE_GENEVE, 735 }, 736 }; 737 738 static struct rte_flow_action_handle * 739 mlx5_action_handle_create(struct rte_eth_dev *dev, 740 const struct rte_flow_indir_action_conf *conf, 741 const struct rte_flow_action *action, 742 struct rte_flow_error *error); 743 static int mlx5_action_handle_destroy 744 (struct rte_eth_dev *dev, 745 struct rte_flow_action_handle *handle, 746 struct rte_flow_error *error); 747 static int mlx5_action_handle_update 748 (struct rte_eth_dev *dev, 749 struct rte_flow_action_handle *handle, 750 const void *update, 751 struct rte_flow_error *error); 752 static int mlx5_action_handle_query 753 (struct rte_eth_dev *dev, 754 const struct rte_flow_action_handle *handle, 755 void *data, 756 struct rte_flow_error *error); 757 static int 758 mlx5_flow_tunnel_decap_set(struct rte_eth_dev *dev, 759 struct rte_flow_tunnel *app_tunnel, 760 struct rte_flow_action **actions, 761 uint32_t *num_of_actions, 762 struct rte_flow_error *error); 763 static int 764 mlx5_flow_tunnel_match(struct rte_eth_dev *dev, 765 struct rte_flow_tunnel *app_tunnel, 766 struct rte_flow_item **items, 767 uint32_t *num_of_items, 768 struct rte_flow_error *error); 769 static int 770 mlx5_flow_tunnel_item_release(struct rte_eth_dev *dev, 771 struct rte_flow_item *pmd_items, 772 uint32_t num_items, struct rte_flow_error *err); 773 static int 774 mlx5_flow_tunnel_action_release(struct rte_eth_dev *dev, 775 struct rte_flow_action *pmd_actions, 776 uint32_t num_actions, 777 struct rte_flow_error *err); 778 static int 779 mlx5_flow_tunnel_get_restore_info(struct rte_eth_dev *dev, 780 struct rte_mbuf *m, 781 struct rte_flow_restore_info *info, 782 struct rte_flow_error *err); 783 static struct rte_flow_item_flex_handle * 784 mlx5_flow_flex_item_create(struct rte_eth_dev *dev, 785 const struct rte_flow_item_flex_conf *conf, 786 struct rte_flow_error *error); 787 static int 788 mlx5_flow_flex_item_release(struct rte_eth_dev *dev, 789 const struct rte_flow_item_flex_handle *handle, 790 struct rte_flow_error *error); 791 792 static const struct rte_flow_ops mlx5_flow_ops = { 793 .validate = mlx5_flow_validate, 794 .create = mlx5_flow_create, 795 .destroy = mlx5_flow_destroy, 796 .flush = mlx5_flow_flush, 797 .isolate = mlx5_flow_isolate, 798 .query = mlx5_flow_query, 799 .dev_dump = mlx5_flow_dev_dump, 800 .get_aged_flows = mlx5_flow_get_aged_flows, 801 .action_handle_create = mlx5_action_handle_create, 802 .action_handle_destroy = mlx5_action_handle_destroy, 803 .action_handle_update = mlx5_action_handle_update, 804 .action_handle_query = mlx5_action_handle_query, 805 .tunnel_decap_set = mlx5_flow_tunnel_decap_set, 806 .tunnel_match = mlx5_flow_tunnel_match, 807 .tunnel_action_decap_release = mlx5_flow_tunnel_action_release, 808 .tunnel_item_release = mlx5_flow_tunnel_item_release, 809 .get_restore_info = mlx5_flow_tunnel_get_restore_info, 810 .flex_item_create = mlx5_flow_flex_item_create, 811 .flex_item_release = mlx5_flow_flex_item_release, 812 }; 813 814 /* Tunnel information. */ 815 struct mlx5_flow_tunnel_info { 816 uint64_t tunnel; /**< Tunnel bit (see MLX5_FLOW_*). */ 817 uint32_t ptype; /**< Tunnel Ptype (see RTE_PTYPE_*). */ 818 }; 819 820 static struct mlx5_flow_tunnel_info tunnels_info[] = { 821 { 822 .tunnel = MLX5_FLOW_LAYER_VXLAN, 823 .ptype = RTE_PTYPE_TUNNEL_VXLAN | RTE_PTYPE_L4_UDP, 824 }, 825 { 826 .tunnel = MLX5_FLOW_LAYER_GENEVE, 827 .ptype = RTE_PTYPE_TUNNEL_GENEVE | RTE_PTYPE_L4_UDP, 828 }, 829 { 830 .tunnel = MLX5_FLOW_LAYER_VXLAN_GPE, 831 .ptype = RTE_PTYPE_TUNNEL_VXLAN_GPE | RTE_PTYPE_L4_UDP, 832 }, 833 { 834 .tunnel = MLX5_FLOW_LAYER_GRE, 835 .ptype = RTE_PTYPE_TUNNEL_GRE, 836 }, 837 { 838 .tunnel = MLX5_FLOW_LAYER_MPLS | MLX5_FLOW_LAYER_OUTER_L4_UDP, 839 .ptype = RTE_PTYPE_TUNNEL_MPLS_IN_UDP | RTE_PTYPE_L4_UDP, 840 }, 841 { 842 .tunnel = MLX5_FLOW_LAYER_MPLS, 843 .ptype = RTE_PTYPE_TUNNEL_MPLS_IN_GRE, 844 }, 845 { 846 .tunnel = MLX5_FLOW_LAYER_NVGRE, 847 .ptype = RTE_PTYPE_TUNNEL_NVGRE, 848 }, 849 { 850 .tunnel = MLX5_FLOW_LAYER_IPIP, 851 .ptype = RTE_PTYPE_TUNNEL_IP, 852 }, 853 { 854 .tunnel = MLX5_FLOW_LAYER_IPV6_ENCAP, 855 .ptype = RTE_PTYPE_TUNNEL_IP, 856 }, 857 { 858 .tunnel = MLX5_FLOW_LAYER_GTP, 859 .ptype = RTE_PTYPE_TUNNEL_GTPU, 860 }, 861 }; 862 863 864 865 /** 866 * Translate tag ID to register. 867 * 868 * @param[in] dev 869 * Pointer to the Ethernet device structure. 870 * @param[in] feature 871 * The feature that request the register. 872 * @param[in] id 873 * The request register ID. 874 * @param[out] error 875 * Error description in case of any. 876 * 877 * @return 878 * The request register on success, a negative errno 879 * value otherwise and rte_errno is set. 880 */ 881 int 882 mlx5_flow_get_reg_id(struct rte_eth_dev *dev, 883 enum mlx5_feature_name feature, 884 uint32_t id, 885 struct rte_flow_error *error) 886 { 887 struct mlx5_priv *priv = dev->data->dev_private; 888 struct mlx5_dev_config *config = &priv->config; 889 enum modify_reg start_reg; 890 bool skip_mtr_reg = false; 891 892 switch (feature) { 893 case MLX5_HAIRPIN_RX: 894 return REG_B; 895 case MLX5_HAIRPIN_TX: 896 return REG_A; 897 case MLX5_METADATA_RX: 898 switch (config->dv_xmeta_en) { 899 case MLX5_XMETA_MODE_LEGACY: 900 return REG_B; 901 case MLX5_XMETA_MODE_META16: 902 return REG_C_0; 903 case MLX5_XMETA_MODE_META32: 904 return REG_C_1; 905 } 906 break; 907 case MLX5_METADATA_TX: 908 return REG_A; 909 case MLX5_METADATA_FDB: 910 switch (config->dv_xmeta_en) { 911 case MLX5_XMETA_MODE_LEGACY: 912 return REG_NON; 913 case MLX5_XMETA_MODE_META16: 914 return REG_C_0; 915 case MLX5_XMETA_MODE_META32: 916 return REG_C_1; 917 } 918 break; 919 case MLX5_FLOW_MARK: 920 switch (config->dv_xmeta_en) { 921 case MLX5_XMETA_MODE_LEGACY: 922 return REG_NON; 923 case MLX5_XMETA_MODE_META16: 924 return REG_C_1; 925 case MLX5_XMETA_MODE_META32: 926 return REG_C_0; 927 } 928 break; 929 case MLX5_MTR_ID: 930 /* 931 * If meter color and meter id share one register, flow match 932 * should use the meter color register for match. 933 */ 934 if (priv->mtr_reg_share) 935 return priv->mtr_color_reg; 936 else 937 return priv->mtr_color_reg != REG_C_2 ? REG_C_2 : 938 REG_C_3; 939 case MLX5_MTR_COLOR: 940 case MLX5_ASO_FLOW_HIT: 941 case MLX5_ASO_CONNTRACK: 942 case MLX5_SAMPLE_ID: 943 /* All features use the same REG_C. */ 944 MLX5_ASSERT(priv->mtr_color_reg != REG_NON); 945 return priv->mtr_color_reg; 946 case MLX5_COPY_MARK: 947 /* 948 * Metadata COPY_MARK register using is in meter suffix sub 949 * flow while with meter. It's safe to share the same register. 950 */ 951 return priv->mtr_color_reg != REG_C_2 ? REG_C_2 : REG_C_3; 952 case MLX5_APP_TAG: 953 /* 954 * If meter is enable, it will engage the register for color 955 * match and flow match. If meter color match is not using the 956 * REG_C_2, need to skip the REG_C_x be used by meter color 957 * match. 958 * If meter is disable, free to use all available registers. 959 */ 960 start_reg = priv->mtr_color_reg != REG_C_2 ? REG_C_2 : 961 (priv->mtr_reg_share ? REG_C_3 : REG_C_4); 962 skip_mtr_reg = !!(priv->mtr_en && start_reg == REG_C_2); 963 if (id > (uint32_t)(REG_C_7 - start_reg)) 964 return rte_flow_error_set(error, EINVAL, 965 RTE_FLOW_ERROR_TYPE_ITEM, 966 NULL, "invalid tag id"); 967 if (priv->sh->flow_mreg_c[id + start_reg - REG_C_0] == REG_NON) 968 return rte_flow_error_set(error, ENOTSUP, 969 RTE_FLOW_ERROR_TYPE_ITEM, 970 NULL, "unsupported tag id"); 971 /* 972 * This case means meter is using the REG_C_x great than 2. 973 * Take care not to conflict with meter color REG_C_x. 974 * If the available index REG_C_y >= REG_C_x, skip the 975 * color register. 976 */ 977 if (skip_mtr_reg && priv->sh->flow_mreg_c 978 [id + start_reg - REG_C_0] >= priv->mtr_color_reg) { 979 if (id >= (uint32_t)(REG_C_7 - start_reg)) 980 return rte_flow_error_set(error, EINVAL, 981 RTE_FLOW_ERROR_TYPE_ITEM, 982 NULL, "invalid tag id"); 983 if (priv->sh->flow_mreg_c 984 [id + 1 + start_reg - REG_C_0] != REG_NON) 985 return priv->sh->flow_mreg_c 986 [id + 1 + start_reg - REG_C_0]; 987 return rte_flow_error_set(error, ENOTSUP, 988 RTE_FLOW_ERROR_TYPE_ITEM, 989 NULL, "unsupported tag id"); 990 } 991 return priv->sh->flow_mreg_c[id + start_reg - REG_C_0]; 992 } 993 MLX5_ASSERT(false); 994 return rte_flow_error_set(error, EINVAL, 995 RTE_FLOW_ERROR_TYPE_UNSPECIFIED, 996 NULL, "invalid feature name"); 997 } 998 999 /** 1000 * Check extensive flow metadata register support. 1001 * 1002 * @param dev 1003 * Pointer to rte_eth_dev structure. 1004 * 1005 * @return 1006 * True if device supports extensive flow metadata register, otherwise false. 1007 */ 1008 bool 1009 mlx5_flow_ext_mreg_supported(struct rte_eth_dev *dev) 1010 { 1011 struct mlx5_priv *priv = dev->data->dev_private; 1012 1013 /* 1014 * Having available reg_c can be regarded inclusively as supporting 1015 * extensive flow metadata register, which could mean, 1016 * - metadata register copy action by modify header. 1017 * - 16 modify header actions is supported. 1018 * - reg_c's are preserved across different domain (FDB and NIC) on 1019 * packet loopback by flow lookup miss. 1020 */ 1021 return priv->sh->flow_mreg_c[2] != REG_NON; 1022 } 1023 1024 /** 1025 * Get the lowest priority. 1026 * 1027 * @param[in] dev 1028 * Pointer to the Ethernet device structure. 1029 * @param[in] attributes 1030 * Pointer to device flow rule attributes. 1031 * 1032 * @return 1033 * The value of lowest priority of flow. 1034 */ 1035 uint32_t 1036 mlx5_get_lowest_priority(struct rte_eth_dev *dev, 1037 const struct rte_flow_attr *attr) 1038 { 1039 struct mlx5_priv *priv = dev->data->dev_private; 1040 1041 if (!attr->group && !attr->transfer) 1042 return priv->sh->flow_max_priority - 2; 1043 return MLX5_NON_ROOT_FLOW_MAX_PRIO - 1; 1044 } 1045 1046 /** 1047 * Calculate matcher priority of the flow. 1048 * 1049 * @param[in] dev 1050 * Pointer to the Ethernet device structure. 1051 * @param[in] attr 1052 * Pointer to device flow rule attributes. 1053 * @param[in] subpriority 1054 * The priority based on the items. 1055 * @param[in] external 1056 * Flow is user flow. 1057 * @return 1058 * The matcher priority of the flow. 1059 */ 1060 uint16_t 1061 mlx5_get_matcher_priority(struct rte_eth_dev *dev, 1062 const struct rte_flow_attr *attr, 1063 uint32_t subpriority, bool external) 1064 { 1065 uint16_t priority = (uint16_t)attr->priority; 1066 struct mlx5_priv *priv = dev->data->dev_private; 1067 1068 if (!attr->group && !attr->transfer) { 1069 if (attr->priority == MLX5_FLOW_LOWEST_PRIO_INDICATOR) 1070 priority = priv->sh->flow_max_priority - 1; 1071 return mlx5_os_flow_adjust_priority(dev, priority, subpriority); 1072 } else if (!external && attr->transfer && attr->group == 0 && 1073 attr->priority == MLX5_FLOW_LOWEST_PRIO_INDICATOR) { 1074 return (priv->sh->flow_max_priority - 1) * 3; 1075 } 1076 if (attr->priority == MLX5_FLOW_LOWEST_PRIO_INDICATOR) 1077 priority = MLX5_NON_ROOT_FLOW_MAX_PRIO; 1078 return priority * 3 + subpriority; 1079 } 1080 1081 /** 1082 * Verify the @p item specifications (spec, last, mask) are compatible with the 1083 * NIC capabilities. 1084 * 1085 * @param[in] item 1086 * Item specification. 1087 * @param[in] mask 1088 * @p item->mask or flow default bit-masks. 1089 * @param[in] nic_mask 1090 * Bit-masks covering supported fields by the NIC to compare with user mask. 1091 * @param[in] size 1092 * Bit-masks size in bytes. 1093 * @param[in] range_accepted 1094 * True if range of values is accepted for specific fields, false otherwise. 1095 * @param[out] error 1096 * Pointer to error structure. 1097 * 1098 * @return 1099 * 0 on success, a negative errno value otherwise and rte_errno is set. 1100 */ 1101 int 1102 mlx5_flow_item_acceptable(const struct rte_flow_item *item, 1103 const uint8_t *mask, 1104 const uint8_t *nic_mask, 1105 unsigned int size, 1106 bool range_accepted, 1107 struct rte_flow_error *error) 1108 { 1109 unsigned int i; 1110 1111 MLX5_ASSERT(nic_mask); 1112 for (i = 0; i < size; ++i) 1113 if ((nic_mask[i] | mask[i]) != nic_mask[i]) 1114 return rte_flow_error_set(error, ENOTSUP, 1115 RTE_FLOW_ERROR_TYPE_ITEM, 1116 item, 1117 "mask enables non supported" 1118 " bits"); 1119 if (!item->spec && (item->mask || item->last)) 1120 return rte_flow_error_set(error, EINVAL, 1121 RTE_FLOW_ERROR_TYPE_ITEM, item, 1122 "mask/last without a spec is not" 1123 " supported"); 1124 if (item->spec && item->last && !range_accepted) { 1125 uint8_t spec[size]; 1126 uint8_t last[size]; 1127 unsigned int i; 1128 int ret; 1129 1130 for (i = 0; i < size; ++i) { 1131 spec[i] = ((const uint8_t *)item->spec)[i] & mask[i]; 1132 last[i] = ((const uint8_t *)item->last)[i] & mask[i]; 1133 } 1134 ret = memcmp(spec, last, size); 1135 if (ret != 0) 1136 return rte_flow_error_set(error, EINVAL, 1137 RTE_FLOW_ERROR_TYPE_ITEM, 1138 item, 1139 "range is not valid"); 1140 } 1141 return 0; 1142 } 1143 1144 /** 1145 * Adjust the hash fields according to the @p flow information. 1146 * 1147 * @param[in] dev_flow. 1148 * Pointer to the mlx5_flow. 1149 * @param[in] tunnel 1150 * 1 when the hash field is for a tunnel item. 1151 * @param[in] layer_types 1152 * RTE_ETH_RSS_* types. 1153 * @param[in] hash_fields 1154 * Item hash fields. 1155 * 1156 * @return 1157 * The hash fields that should be used. 1158 */ 1159 uint64_t 1160 mlx5_flow_hashfields_adjust(struct mlx5_flow_rss_desc *rss_desc, 1161 int tunnel __rte_unused, uint64_t layer_types, 1162 uint64_t hash_fields) 1163 { 1164 #ifdef HAVE_IBV_DEVICE_TUNNEL_SUPPORT 1165 int rss_request_inner = rss_desc->level >= 2; 1166 1167 /* Check RSS hash level for tunnel. */ 1168 if (tunnel && rss_request_inner) 1169 hash_fields |= IBV_RX_HASH_INNER; 1170 else if (tunnel || rss_request_inner) 1171 return 0; 1172 #endif 1173 /* Check if requested layer matches RSS hash fields. */ 1174 if (!(rss_desc->types & layer_types)) 1175 return 0; 1176 return hash_fields; 1177 } 1178 1179 /** 1180 * Lookup and set the ptype in the data Rx part. A single Ptype can be used, 1181 * if several tunnel rules are used on this queue, the tunnel ptype will be 1182 * cleared. 1183 * 1184 * @param rxq_ctrl 1185 * Rx queue to update. 1186 */ 1187 static void 1188 flow_rxq_tunnel_ptype_update(struct mlx5_rxq_ctrl *rxq_ctrl) 1189 { 1190 unsigned int i; 1191 uint32_t tunnel_ptype = 0; 1192 1193 /* Look up for the ptype to use. */ 1194 for (i = 0; i != MLX5_FLOW_TUNNEL; ++i) { 1195 if (!rxq_ctrl->flow_tunnels_n[i]) 1196 continue; 1197 if (!tunnel_ptype) { 1198 tunnel_ptype = tunnels_info[i].ptype; 1199 } else { 1200 tunnel_ptype = 0; 1201 break; 1202 } 1203 } 1204 rxq_ctrl->rxq.tunnel = tunnel_ptype; 1205 } 1206 1207 /** 1208 * Set the Rx queue flags (Mark/Flag and Tunnel Ptypes) according to the devive 1209 * flow. 1210 * 1211 * @param[in] dev 1212 * Pointer to the Ethernet device structure. 1213 * @param[in] dev_handle 1214 * Pointer to device flow handle structure. 1215 */ 1216 void 1217 flow_drv_rxq_flags_set(struct rte_eth_dev *dev, 1218 struct mlx5_flow_handle *dev_handle) 1219 { 1220 struct mlx5_priv *priv = dev->data->dev_private; 1221 const int mark = dev_handle->mark; 1222 const int tunnel = !!(dev_handle->layers & MLX5_FLOW_LAYER_TUNNEL); 1223 struct mlx5_ind_table_obj *ind_tbl = NULL; 1224 unsigned int i; 1225 1226 if (dev_handle->fate_action == MLX5_FLOW_FATE_QUEUE) { 1227 struct mlx5_hrxq *hrxq; 1228 1229 hrxq = mlx5_ipool_get(priv->sh->ipool[MLX5_IPOOL_HRXQ], 1230 dev_handle->rix_hrxq); 1231 if (hrxq) 1232 ind_tbl = hrxq->ind_table; 1233 } else if (dev_handle->fate_action == MLX5_FLOW_FATE_SHARED_RSS) { 1234 struct mlx5_shared_action_rss *shared_rss; 1235 1236 shared_rss = mlx5_ipool_get 1237 (priv->sh->ipool[MLX5_IPOOL_RSS_SHARED_ACTIONS], 1238 dev_handle->rix_srss); 1239 if (shared_rss) 1240 ind_tbl = shared_rss->ind_tbl; 1241 } 1242 if (!ind_tbl) 1243 return; 1244 for (i = 0; i != ind_tbl->queues_n; ++i) { 1245 int idx = ind_tbl->queues[i]; 1246 struct mlx5_rxq_ctrl *rxq_ctrl = mlx5_rxq_ctrl_get(dev, idx); 1247 1248 MLX5_ASSERT(rxq_ctrl != NULL); 1249 if (rxq_ctrl == NULL) 1250 continue; 1251 /* 1252 * To support metadata register copy on Tx loopback, 1253 * this must be always enabled (metadata may arive 1254 * from other port - not from local flows only. 1255 */ 1256 if (priv->config.dv_flow_en && 1257 priv->config.dv_xmeta_en != MLX5_XMETA_MODE_LEGACY && 1258 mlx5_flow_ext_mreg_supported(dev)) { 1259 rxq_ctrl->rxq.mark = 1; 1260 rxq_ctrl->flow_mark_n = 1; 1261 } else if (mark) { 1262 rxq_ctrl->rxq.mark = 1; 1263 rxq_ctrl->flow_mark_n++; 1264 } 1265 if (tunnel) { 1266 unsigned int j; 1267 1268 /* Increase the counter matching the flow. */ 1269 for (j = 0; j != MLX5_FLOW_TUNNEL; ++j) { 1270 if ((tunnels_info[j].tunnel & 1271 dev_handle->layers) == 1272 tunnels_info[j].tunnel) { 1273 rxq_ctrl->flow_tunnels_n[j]++; 1274 break; 1275 } 1276 } 1277 flow_rxq_tunnel_ptype_update(rxq_ctrl); 1278 } 1279 } 1280 } 1281 1282 /** 1283 * Set the Rx queue flags (Mark/Flag and Tunnel Ptypes) for a flow 1284 * 1285 * @param[in] dev 1286 * Pointer to the Ethernet device structure. 1287 * @param[in] flow 1288 * Pointer to flow structure. 1289 */ 1290 static void 1291 flow_rxq_flags_set(struct rte_eth_dev *dev, struct rte_flow *flow) 1292 { 1293 struct mlx5_priv *priv = dev->data->dev_private; 1294 uint32_t handle_idx; 1295 struct mlx5_flow_handle *dev_handle; 1296 1297 SILIST_FOREACH(priv->sh->ipool[MLX5_IPOOL_MLX5_FLOW], flow->dev_handles, 1298 handle_idx, dev_handle, next) 1299 flow_drv_rxq_flags_set(dev, dev_handle); 1300 } 1301 1302 /** 1303 * Clear the Rx queue flags (Mark/Flag and Tunnel Ptype) associated with the 1304 * device flow if no other flow uses it with the same kind of request. 1305 * 1306 * @param dev 1307 * Pointer to Ethernet device. 1308 * @param[in] dev_handle 1309 * Pointer to the device flow handle structure. 1310 */ 1311 static void 1312 flow_drv_rxq_flags_trim(struct rte_eth_dev *dev, 1313 struct mlx5_flow_handle *dev_handle) 1314 { 1315 struct mlx5_priv *priv = dev->data->dev_private; 1316 const int mark = dev_handle->mark; 1317 const int tunnel = !!(dev_handle->layers & MLX5_FLOW_LAYER_TUNNEL); 1318 struct mlx5_ind_table_obj *ind_tbl = NULL; 1319 unsigned int i; 1320 1321 if (dev_handle->fate_action == MLX5_FLOW_FATE_QUEUE) { 1322 struct mlx5_hrxq *hrxq; 1323 1324 hrxq = mlx5_ipool_get(priv->sh->ipool[MLX5_IPOOL_HRXQ], 1325 dev_handle->rix_hrxq); 1326 if (hrxq) 1327 ind_tbl = hrxq->ind_table; 1328 } else if (dev_handle->fate_action == MLX5_FLOW_FATE_SHARED_RSS) { 1329 struct mlx5_shared_action_rss *shared_rss; 1330 1331 shared_rss = mlx5_ipool_get 1332 (priv->sh->ipool[MLX5_IPOOL_RSS_SHARED_ACTIONS], 1333 dev_handle->rix_srss); 1334 if (shared_rss) 1335 ind_tbl = shared_rss->ind_tbl; 1336 } 1337 if (!ind_tbl) 1338 return; 1339 MLX5_ASSERT(dev->data->dev_started); 1340 for (i = 0; i != ind_tbl->queues_n; ++i) { 1341 int idx = ind_tbl->queues[i]; 1342 struct mlx5_rxq_ctrl *rxq_ctrl = mlx5_rxq_ctrl_get(dev, idx); 1343 1344 MLX5_ASSERT(rxq_ctrl != NULL); 1345 if (rxq_ctrl == NULL) 1346 continue; 1347 if (priv->config.dv_flow_en && 1348 priv->config.dv_xmeta_en != MLX5_XMETA_MODE_LEGACY && 1349 mlx5_flow_ext_mreg_supported(dev)) { 1350 rxq_ctrl->rxq.mark = 1; 1351 rxq_ctrl->flow_mark_n = 1; 1352 } else if (mark) { 1353 rxq_ctrl->flow_mark_n--; 1354 rxq_ctrl->rxq.mark = !!rxq_ctrl->flow_mark_n; 1355 } 1356 if (tunnel) { 1357 unsigned int j; 1358 1359 /* Decrease the counter matching the flow. */ 1360 for (j = 0; j != MLX5_FLOW_TUNNEL; ++j) { 1361 if ((tunnels_info[j].tunnel & 1362 dev_handle->layers) == 1363 tunnels_info[j].tunnel) { 1364 rxq_ctrl->flow_tunnels_n[j]--; 1365 break; 1366 } 1367 } 1368 flow_rxq_tunnel_ptype_update(rxq_ctrl); 1369 } 1370 } 1371 } 1372 1373 /** 1374 * Clear the Rx queue flags (Mark/Flag and Tunnel Ptype) associated with the 1375 * @p flow if no other flow uses it with the same kind of request. 1376 * 1377 * @param dev 1378 * Pointer to Ethernet device. 1379 * @param[in] flow 1380 * Pointer to the flow. 1381 */ 1382 static void 1383 flow_rxq_flags_trim(struct rte_eth_dev *dev, struct rte_flow *flow) 1384 { 1385 struct mlx5_priv *priv = dev->data->dev_private; 1386 uint32_t handle_idx; 1387 struct mlx5_flow_handle *dev_handle; 1388 1389 SILIST_FOREACH(priv->sh->ipool[MLX5_IPOOL_MLX5_FLOW], flow->dev_handles, 1390 handle_idx, dev_handle, next) 1391 flow_drv_rxq_flags_trim(dev, dev_handle); 1392 } 1393 1394 /** 1395 * Clear the Mark/Flag and Tunnel ptype information in all Rx queues. 1396 * 1397 * @param dev 1398 * Pointer to Ethernet device. 1399 */ 1400 static void 1401 flow_rxq_flags_clear(struct rte_eth_dev *dev) 1402 { 1403 struct mlx5_priv *priv = dev->data->dev_private; 1404 unsigned int i; 1405 1406 for (i = 0; i != priv->rxqs_n; ++i) { 1407 struct mlx5_rxq_priv *rxq = mlx5_rxq_get(dev, i); 1408 unsigned int j; 1409 1410 if (rxq == NULL || rxq->ctrl == NULL) 1411 continue; 1412 rxq->ctrl->flow_mark_n = 0; 1413 rxq->ctrl->rxq.mark = 0; 1414 for (j = 0; j != MLX5_FLOW_TUNNEL; ++j) 1415 rxq->ctrl->flow_tunnels_n[j] = 0; 1416 rxq->ctrl->rxq.tunnel = 0; 1417 } 1418 } 1419 1420 /** 1421 * Set the Rx queue dynamic metadata (mask and offset) for a flow 1422 * 1423 * @param[in] dev 1424 * Pointer to the Ethernet device structure. 1425 */ 1426 void 1427 mlx5_flow_rxq_dynf_metadata_set(struct rte_eth_dev *dev) 1428 { 1429 struct mlx5_priv *priv = dev->data->dev_private; 1430 unsigned int i; 1431 1432 for (i = 0; i != priv->rxqs_n; ++i) { 1433 struct mlx5_rxq_priv *rxq = mlx5_rxq_get(dev, i); 1434 struct mlx5_rxq_data *data; 1435 1436 if (rxq == NULL || rxq->ctrl == NULL) 1437 continue; 1438 data = &rxq->ctrl->rxq; 1439 if (!rte_flow_dynf_metadata_avail()) { 1440 data->dynf_meta = 0; 1441 data->flow_meta_mask = 0; 1442 data->flow_meta_offset = -1; 1443 data->flow_meta_port_mask = 0; 1444 } else { 1445 data->dynf_meta = 1; 1446 data->flow_meta_mask = rte_flow_dynf_metadata_mask; 1447 data->flow_meta_offset = rte_flow_dynf_metadata_offs; 1448 data->flow_meta_port_mask = priv->sh->dv_meta_mask; 1449 } 1450 } 1451 } 1452 1453 /* 1454 * return a pointer to the desired action in the list of actions. 1455 * 1456 * @param[in] actions 1457 * The list of actions to search the action in. 1458 * @param[in] action 1459 * The action to find. 1460 * 1461 * @return 1462 * Pointer to the action in the list, if found. NULL otherwise. 1463 */ 1464 const struct rte_flow_action * 1465 mlx5_flow_find_action(const struct rte_flow_action *actions, 1466 enum rte_flow_action_type action) 1467 { 1468 if (actions == NULL) 1469 return NULL; 1470 for (; actions->type != RTE_FLOW_ACTION_TYPE_END; actions++) 1471 if (actions->type == action) 1472 return actions; 1473 return NULL; 1474 } 1475 1476 /* 1477 * Validate the flag action. 1478 * 1479 * @param[in] action_flags 1480 * Bit-fields that holds the actions detected until now. 1481 * @param[in] attr 1482 * Attributes of flow that includes this action. 1483 * @param[out] error 1484 * Pointer to error structure. 1485 * 1486 * @return 1487 * 0 on success, a negative errno value otherwise and rte_errno is set. 1488 */ 1489 int 1490 mlx5_flow_validate_action_flag(uint64_t action_flags, 1491 const struct rte_flow_attr *attr, 1492 struct rte_flow_error *error) 1493 { 1494 if (action_flags & MLX5_FLOW_ACTION_MARK) 1495 return rte_flow_error_set(error, EINVAL, 1496 RTE_FLOW_ERROR_TYPE_ACTION, NULL, 1497 "can't mark and flag in same flow"); 1498 if (action_flags & MLX5_FLOW_ACTION_FLAG) 1499 return rte_flow_error_set(error, EINVAL, 1500 RTE_FLOW_ERROR_TYPE_ACTION, NULL, 1501 "can't have 2 flag" 1502 " actions in same flow"); 1503 if (attr->egress) 1504 return rte_flow_error_set(error, ENOTSUP, 1505 RTE_FLOW_ERROR_TYPE_ATTR_EGRESS, NULL, 1506 "flag action not supported for " 1507 "egress"); 1508 return 0; 1509 } 1510 1511 /* 1512 * Validate the mark action. 1513 * 1514 * @param[in] action 1515 * Pointer to the queue action. 1516 * @param[in] action_flags 1517 * Bit-fields that holds the actions detected until now. 1518 * @param[in] attr 1519 * Attributes of flow that includes this action. 1520 * @param[out] error 1521 * Pointer to error structure. 1522 * 1523 * @return 1524 * 0 on success, a negative errno value otherwise and rte_errno is set. 1525 */ 1526 int 1527 mlx5_flow_validate_action_mark(const struct rte_flow_action *action, 1528 uint64_t action_flags, 1529 const struct rte_flow_attr *attr, 1530 struct rte_flow_error *error) 1531 { 1532 const struct rte_flow_action_mark *mark = action->conf; 1533 1534 if (!mark) 1535 return rte_flow_error_set(error, EINVAL, 1536 RTE_FLOW_ERROR_TYPE_ACTION, 1537 action, 1538 "configuration cannot be null"); 1539 if (mark->id >= MLX5_FLOW_MARK_MAX) 1540 return rte_flow_error_set(error, EINVAL, 1541 RTE_FLOW_ERROR_TYPE_ACTION_CONF, 1542 &mark->id, 1543 "mark id must in 0 <= id < " 1544 RTE_STR(MLX5_FLOW_MARK_MAX)); 1545 if (action_flags & MLX5_FLOW_ACTION_FLAG) 1546 return rte_flow_error_set(error, EINVAL, 1547 RTE_FLOW_ERROR_TYPE_ACTION, NULL, 1548 "can't flag and mark in same flow"); 1549 if (action_flags & MLX5_FLOW_ACTION_MARK) 1550 return rte_flow_error_set(error, EINVAL, 1551 RTE_FLOW_ERROR_TYPE_ACTION, NULL, 1552 "can't have 2 mark actions in same" 1553 " flow"); 1554 if (attr->egress) 1555 return rte_flow_error_set(error, ENOTSUP, 1556 RTE_FLOW_ERROR_TYPE_ATTR_EGRESS, NULL, 1557 "mark action not supported for " 1558 "egress"); 1559 return 0; 1560 } 1561 1562 /* 1563 * Validate the drop action. 1564 * 1565 * @param[in] action_flags 1566 * Bit-fields that holds the actions detected until now. 1567 * @param[in] attr 1568 * Attributes of flow that includes this action. 1569 * @param[out] error 1570 * Pointer to error structure. 1571 * 1572 * @return 1573 * 0 on success, a negative errno value otherwise and rte_errno is set. 1574 */ 1575 int 1576 mlx5_flow_validate_action_drop(uint64_t action_flags __rte_unused, 1577 const struct rte_flow_attr *attr, 1578 struct rte_flow_error *error) 1579 { 1580 if (attr->egress) 1581 return rte_flow_error_set(error, ENOTSUP, 1582 RTE_FLOW_ERROR_TYPE_ATTR_EGRESS, NULL, 1583 "drop action not supported for " 1584 "egress"); 1585 return 0; 1586 } 1587 1588 /* 1589 * Validate the queue action. 1590 * 1591 * @param[in] action 1592 * Pointer to the queue action. 1593 * @param[in] action_flags 1594 * Bit-fields that holds the actions detected until now. 1595 * @param[in] dev 1596 * Pointer to the Ethernet device structure. 1597 * @param[in] attr 1598 * Attributes of flow that includes this action. 1599 * @param[out] error 1600 * Pointer to error structure. 1601 * 1602 * @return 1603 * 0 on success, a negative errno value otherwise and rte_errno is set. 1604 */ 1605 int 1606 mlx5_flow_validate_action_queue(const struct rte_flow_action *action, 1607 uint64_t action_flags, 1608 struct rte_eth_dev *dev, 1609 const struct rte_flow_attr *attr, 1610 struct rte_flow_error *error) 1611 { 1612 struct mlx5_priv *priv = dev->data->dev_private; 1613 const struct rte_flow_action_queue *queue = action->conf; 1614 1615 if (action_flags & MLX5_FLOW_FATE_ACTIONS) 1616 return rte_flow_error_set(error, EINVAL, 1617 RTE_FLOW_ERROR_TYPE_ACTION, NULL, 1618 "can't have 2 fate actions in" 1619 " same flow"); 1620 if (!priv->rxqs_n) 1621 return rte_flow_error_set(error, EINVAL, 1622 RTE_FLOW_ERROR_TYPE_ACTION_CONF, 1623 NULL, "No Rx queues configured"); 1624 if (queue->index >= priv->rxqs_n) 1625 return rte_flow_error_set(error, EINVAL, 1626 RTE_FLOW_ERROR_TYPE_ACTION_CONF, 1627 &queue->index, 1628 "queue index out of range"); 1629 if (mlx5_rxq_get(dev, queue->index) == NULL) 1630 return rte_flow_error_set(error, EINVAL, 1631 RTE_FLOW_ERROR_TYPE_ACTION_CONF, 1632 &queue->index, 1633 "queue is not configured"); 1634 if (attr->egress) 1635 return rte_flow_error_set(error, ENOTSUP, 1636 RTE_FLOW_ERROR_TYPE_ATTR_EGRESS, NULL, 1637 "queue action not supported for " 1638 "egress"); 1639 return 0; 1640 } 1641 1642 /** 1643 * Validate queue numbers for device RSS. 1644 * 1645 * @param[in] dev 1646 * Configured device. 1647 * @param[in] queues 1648 * Array of queue numbers. 1649 * @param[in] queues_n 1650 * Size of the @p queues array. 1651 * @param[out] error 1652 * On error, filled with a textual error description. 1653 * @param[out] queue 1654 * On error, filled with an offending queue index in @p queues array. 1655 * 1656 * @return 1657 * 0 on success, a negative errno code on error. 1658 */ 1659 static int 1660 mlx5_validate_rss_queues(struct rte_eth_dev *dev, 1661 const uint16_t *queues, uint32_t queues_n, 1662 const char **error, uint32_t *queue_idx) 1663 { 1664 const struct mlx5_priv *priv = dev->data->dev_private; 1665 enum mlx5_rxq_type rxq_type = MLX5_RXQ_TYPE_UNDEFINED; 1666 uint32_t i; 1667 1668 for (i = 0; i != queues_n; ++i) { 1669 struct mlx5_rxq_ctrl *rxq_ctrl = mlx5_rxq_ctrl_get(dev, 1670 queues[i]); 1671 1672 if (queues[i] >= priv->rxqs_n) { 1673 *error = "queue index out of range"; 1674 *queue_idx = i; 1675 return -EINVAL; 1676 } 1677 if (rxq_ctrl == NULL) { 1678 *error = "queue is not configured"; 1679 *queue_idx = i; 1680 return -EINVAL; 1681 } 1682 if (i == 0) 1683 rxq_type = rxq_ctrl->type; 1684 if (rxq_type != rxq_ctrl->type) { 1685 *error = "combining hairpin and regular RSS queues is not supported"; 1686 *queue_idx = i; 1687 return -ENOTSUP; 1688 } 1689 } 1690 return 0; 1691 } 1692 1693 /* 1694 * Validate the rss action. 1695 * 1696 * @param[in] dev 1697 * Pointer to the Ethernet device structure. 1698 * @param[in] action 1699 * Pointer to the queue action. 1700 * @param[out] error 1701 * Pointer to error structure. 1702 * 1703 * @return 1704 * 0 on success, a negative errno value otherwise and rte_errno is set. 1705 */ 1706 int 1707 mlx5_validate_action_rss(struct rte_eth_dev *dev, 1708 const struct rte_flow_action *action, 1709 struct rte_flow_error *error) 1710 { 1711 struct mlx5_priv *priv = dev->data->dev_private; 1712 const struct rte_flow_action_rss *rss = action->conf; 1713 int ret; 1714 const char *message; 1715 uint32_t queue_idx; 1716 1717 if (rss->func != RTE_ETH_HASH_FUNCTION_DEFAULT && 1718 rss->func != RTE_ETH_HASH_FUNCTION_TOEPLITZ) 1719 return rte_flow_error_set(error, ENOTSUP, 1720 RTE_FLOW_ERROR_TYPE_ACTION_CONF, 1721 &rss->func, 1722 "RSS hash function not supported"); 1723 #ifdef HAVE_IBV_DEVICE_TUNNEL_SUPPORT 1724 if (rss->level > 2) 1725 #else 1726 if (rss->level > 1) 1727 #endif 1728 return rte_flow_error_set(error, ENOTSUP, 1729 RTE_FLOW_ERROR_TYPE_ACTION_CONF, 1730 &rss->level, 1731 "tunnel RSS is not supported"); 1732 /* allow RSS key_len 0 in case of NULL (default) RSS key. */ 1733 if (rss->key_len == 0 && rss->key != NULL) 1734 return rte_flow_error_set(error, ENOTSUP, 1735 RTE_FLOW_ERROR_TYPE_ACTION_CONF, 1736 &rss->key_len, 1737 "RSS hash key length 0"); 1738 if (rss->key_len > 0 && rss->key_len < MLX5_RSS_HASH_KEY_LEN) 1739 return rte_flow_error_set(error, ENOTSUP, 1740 RTE_FLOW_ERROR_TYPE_ACTION_CONF, 1741 &rss->key_len, 1742 "RSS hash key too small"); 1743 if (rss->key_len > MLX5_RSS_HASH_KEY_LEN) 1744 return rte_flow_error_set(error, ENOTSUP, 1745 RTE_FLOW_ERROR_TYPE_ACTION_CONF, 1746 &rss->key_len, 1747 "RSS hash key too large"); 1748 if (rss->queue_num > priv->config.ind_table_max_size) 1749 return rte_flow_error_set(error, ENOTSUP, 1750 RTE_FLOW_ERROR_TYPE_ACTION_CONF, 1751 &rss->queue_num, 1752 "number of queues too large"); 1753 if (rss->types & MLX5_RSS_HF_MASK) 1754 return rte_flow_error_set(error, ENOTSUP, 1755 RTE_FLOW_ERROR_TYPE_ACTION_CONF, 1756 &rss->types, 1757 "some RSS protocols are not" 1758 " supported"); 1759 if ((rss->types & (RTE_ETH_RSS_L3_SRC_ONLY | RTE_ETH_RSS_L3_DST_ONLY)) && 1760 !(rss->types & RTE_ETH_RSS_IP)) 1761 return rte_flow_error_set(error, EINVAL, 1762 RTE_FLOW_ERROR_TYPE_ACTION_CONF, NULL, 1763 "L3 partial RSS requested but L3 RSS" 1764 " type not specified"); 1765 if ((rss->types & (RTE_ETH_RSS_L4_SRC_ONLY | RTE_ETH_RSS_L4_DST_ONLY)) && 1766 !(rss->types & (RTE_ETH_RSS_UDP | RTE_ETH_RSS_TCP))) 1767 return rte_flow_error_set(error, EINVAL, 1768 RTE_FLOW_ERROR_TYPE_ACTION_CONF, NULL, 1769 "L4 partial RSS requested but L4 RSS" 1770 " type not specified"); 1771 if (!priv->rxqs_n) 1772 return rte_flow_error_set(error, EINVAL, 1773 RTE_FLOW_ERROR_TYPE_ACTION_CONF, 1774 NULL, "No Rx queues configured"); 1775 if (!rss->queue_num) 1776 return rte_flow_error_set(error, EINVAL, 1777 RTE_FLOW_ERROR_TYPE_ACTION_CONF, 1778 NULL, "No queues configured"); 1779 ret = mlx5_validate_rss_queues(dev, rss->queue, rss->queue_num, 1780 &message, &queue_idx); 1781 if (ret != 0) { 1782 return rte_flow_error_set(error, -ret, 1783 RTE_FLOW_ERROR_TYPE_ACTION_CONF, 1784 &rss->queue[queue_idx], message); 1785 } 1786 return 0; 1787 } 1788 1789 /* 1790 * Validate the rss action. 1791 * 1792 * @param[in] action 1793 * Pointer to the queue action. 1794 * @param[in] action_flags 1795 * Bit-fields that holds the actions detected until now. 1796 * @param[in] dev 1797 * Pointer to the Ethernet device structure. 1798 * @param[in] attr 1799 * Attributes of flow that includes this action. 1800 * @param[in] item_flags 1801 * Items that were detected. 1802 * @param[out] error 1803 * Pointer to error structure. 1804 * 1805 * @return 1806 * 0 on success, a negative errno value otherwise and rte_errno is set. 1807 */ 1808 int 1809 mlx5_flow_validate_action_rss(const struct rte_flow_action *action, 1810 uint64_t action_flags, 1811 struct rte_eth_dev *dev, 1812 const struct rte_flow_attr *attr, 1813 uint64_t item_flags, 1814 struct rte_flow_error *error) 1815 { 1816 const struct rte_flow_action_rss *rss = action->conf; 1817 int tunnel = !!(item_flags & MLX5_FLOW_LAYER_TUNNEL); 1818 int ret; 1819 1820 if (action_flags & MLX5_FLOW_FATE_ACTIONS) 1821 return rte_flow_error_set(error, EINVAL, 1822 RTE_FLOW_ERROR_TYPE_ACTION, NULL, 1823 "can't have 2 fate actions" 1824 " in same flow"); 1825 ret = mlx5_validate_action_rss(dev, action, error); 1826 if (ret) 1827 return ret; 1828 if (attr->egress) 1829 return rte_flow_error_set(error, ENOTSUP, 1830 RTE_FLOW_ERROR_TYPE_ATTR_EGRESS, NULL, 1831 "rss action not supported for " 1832 "egress"); 1833 if (rss->level > 1 && !tunnel) 1834 return rte_flow_error_set(error, EINVAL, 1835 RTE_FLOW_ERROR_TYPE_ACTION_CONF, NULL, 1836 "inner RSS is not supported for " 1837 "non-tunnel flows"); 1838 if ((item_flags & MLX5_FLOW_LAYER_ECPRI) && 1839 !(item_flags & MLX5_FLOW_LAYER_INNER_L4_UDP)) { 1840 return rte_flow_error_set(error, EINVAL, 1841 RTE_FLOW_ERROR_TYPE_ACTION_CONF, NULL, 1842 "RSS on eCPRI is not supported now"); 1843 } 1844 if ((item_flags & MLX5_FLOW_LAYER_MPLS) && 1845 !(item_flags & 1846 (MLX5_FLOW_LAYER_INNER_L2 | MLX5_FLOW_LAYER_INNER_L3)) && 1847 rss->level > 1) 1848 return rte_flow_error_set(error, EINVAL, 1849 RTE_FLOW_ERROR_TYPE_ITEM, NULL, 1850 "MPLS inner RSS needs to specify inner L2/L3 items after MPLS in pattern"); 1851 return 0; 1852 } 1853 1854 /* 1855 * Validate the default miss action. 1856 * 1857 * @param[in] action_flags 1858 * Bit-fields that holds the actions detected until now. 1859 * @param[out] error 1860 * Pointer to error structure. 1861 * 1862 * @return 1863 * 0 on success, a negative errno value otherwise and rte_errno is set. 1864 */ 1865 int 1866 mlx5_flow_validate_action_default_miss(uint64_t action_flags, 1867 const struct rte_flow_attr *attr, 1868 struct rte_flow_error *error) 1869 { 1870 if (action_flags & MLX5_FLOW_FATE_ACTIONS) 1871 return rte_flow_error_set(error, EINVAL, 1872 RTE_FLOW_ERROR_TYPE_ACTION, NULL, 1873 "can't have 2 fate actions in" 1874 " same flow"); 1875 if (attr->egress) 1876 return rte_flow_error_set(error, ENOTSUP, 1877 RTE_FLOW_ERROR_TYPE_ATTR_EGRESS, NULL, 1878 "default miss action not supported " 1879 "for egress"); 1880 if (attr->group) 1881 return rte_flow_error_set(error, ENOTSUP, 1882 RTE_FLOW_ERROR_TYPE_ATTR_GROUP, NULL, 1883 "only group 0 is supported"); 1884 if (attr->transfer) 1885 return rte_flow_error_set(error, ENOTSUP, 1886 RTE_FLOW_ERROR_TYPE_ATTR_TRANSFER, 1887 NULL, "transfer is not supported"); 1888 return 0; 1889 } 1890 1891 /* 1892 * Validate the count action. 1893 * 1894 * @param[in] dev 1895 * Pointer to the Ethernet device structure. 1896 * @param[in] attr 1897 * Attributes of flow that includes this action. 1898 * @param[out] error 1899 * Pointer to error structure. 1900 * 1901 * @return 1902 * 0 on success, a negative errno value otherwise and rte_errno is set. 1903 */ 1904 int 1905 mlx5_flow_validate_action_count(struct rte_eth_dev *dev __rte_unused, 1906 const struct rte_flow_attr *attr, 1907 struct rte_flow_error *error) 1908 { 1909 if (attr->egress) 1910 return rte_flow_error_set(error, ENOTSUP, 1911 RTE_FLOW_ERROR_TYPE_ATTR_EGRESS, NULL, 1912 "count action not supported for " 1913 "egress"); 1914 return 0; 1915 } 1916 1917 /* 1918 * Validate the ASO CT action. 1919 * 1920 * @param[in] dev 1921 * Pointer to the Ethernet device structure. 1922 * @param[in] conntrack 1923 * Pointer to the CT action profile. 1924 * @param[out] error 1925 * Pointer to error structure. 1926 * 1927 * @return 1928 * 0 on success, a negative errno value otherwise and rte_errno is set. 1929 */ 1930 int 1931 mlx5_validate_action_ct(struct rte_eth_dev *dev, 1932 const struct rte_flow_action_conntrack *conntrack, 1933 struct rte_flow_error *error) 1934 { 1935 RTE_SET_USED(dev); 1936 1937 if (conntrack->state > RTE_FLOW_CONNTRACK_STATE_TIME_WAIT) 1938 return rte_flow_error_set(error, EINVAL, 1939 RTE_FLOW_ERROR_TYPE_ACTION, NULL, 1940 "Invalid CT state"); 1941 if (conntrack->last_index > RTE_FLOW_CONNTRACK_FLAG_RST) 1942 return rte_flow_error_set(error, EINVAL, 1943 RTE_FLOW_ERROR_TYPE_ACTION, NULL, 1944 "Invalid last TCP packet flag"); 1945 return 0; 1946 } 1947 1948 /** 1949 * Verify the @p attributes will be correctly understood by the NIC and store 1950 * them in the @p flow if everything is correct. 1951 * 1952 * @param[in] dev 1953 * Pointer to the Ethernet device structure. 1954 * @param[in] attributes 1955 * Pointer to flow attributes 1956 * @param[out] error 1957 * Pointer to error structure. 1958 * 1959 * @return 1960 * 0 on success, a negative errno value otherwise and rte_errno is set. 1961 */ 1962 int 1963 mlx5_flow_validate_attributes(struct rte_eth_dev *dev, 1964 const struct rte_flow_attr *attributes, 1965 struct rte_flow_error *error) 1966 { 1967 struct mlx5_priv *priv = dev->data->dev_private; 1968 uint32_t priority_max = priv->sh->flow_max_priority - 1; 1969 1970 if (attributes->group) 1971 return rte_flow_error_set(error, ENOTSUP, 1972 RTE_FLOW_ERROR_TYPE_ATTR_GROUP, 1973 NULL, "groups is not supported"); 1974 if (attributes->priority != MLX5_FLOW_LOWEST_PRIO_INDICATOR && 1975 attributes->priority >= priority_max) 1976 return rte_flow_error_set(error, ENOTSUP, 1977 RTE_FLOW_ERROR_TYPE_ATTR_PRIORITY, 1978 NULL, "priority out of range"); 1979 if (attributes->egress) 1980 return rte_flow_error_set(error, ENOTSUP, 1981 RTE_FLOW_ERROR_TYPE_ATTR_EGRESS, NULL, 1982 "egress is not supported"); 1983 if (attributes->transfer && !priv->config.dv_esw_en) 1984 return rte_flow_error_set(error, ENOTSUP, 1985 RTE_FLOW_ERROR_TYPE_ATTR_TRANSFER, 1986 NULL, "transfer is not supported"); 1987 if (!attributes->ingress) 1988 return rte_flow_error_set(error, EINVAL, 1989 RTE_FLOW_ERROR_TYPE_ATTR_INGRESS, 1990 NULL, 1991 "ingress attribute is mandatory"); 1992 return 0; 1993 } 1994 1995 /** 1996 * Validate ICMP6 item. 1997 * 1998 * @param[in] item 1999 * Item specification. 2000 * @param[in] item_flags 2001 * Bit-fields that holds the items detected until now. 2002 * @param[in] ext_vlan_sup 2003 * Whether extended VLAN features are supported or not. 2004 * @param[out] error 2005 * Pointer to error structure. 2006 * 2007 * @return 2008 * 0 on success, a negative errno value otherwise and rte_errno is set. 2009 */ 2010 int 2011 mlx5_flow_validate_item_icmp6(const struct rte_flow_item *item, 2012 uint64_t item_flags, 2013 uint8_t target_protocol, 2014 struct rte_flow_error *error) 2015 { 2016 const struct rte_flow_item_icmp6 *mask = item->mask; 2017 const int tunnel = !!(item_flags & MLX5_FLOW_LAYER_TUNNEL); 2018 const uint64_t l3m = tunnel ? MLX5_FLOW_LAYER_INNER_L3_IPV6 : 2019 MLX5_FLOW_LAYER_OUTER_L3_IPV6; 2020 const uint64_t l4m = tunnel ? MLX5_FLOW_LAYER_INNER_L4 : 2021 MLX5_FLOW_LAYER_OUTER_L4; 2022 int ret; 2023 2024 if (target_protocol != 0xFF && target_protocol != IPPROTO_ICMPV6) 2025 return rte_flow_error_set(error, EINVAL, 2026 RTE_FLOW_ERROR_TYPE_ITEM, item, 2027 "protocol filtering not compatible" 2028 " with ICMP6 layer"); 2029 if (!(item_flags & l3m)) 2030 return rte_flow_error_set(error, EINVAL, 2031 RTE_FLOW_ERROR_TYPE_ITEM, item, 2032 "IPv6 is mandatory to filter on" 2033 " ICMP6"); 2034 if (item_flags & l4m) 2035 return rte_flow_error_set(error, EINVAL, 2036 RTE_FLOW_ERROR_TYPE_ITEM, item, 2037 "multiple L4 layers not supported"); 2038 if (!mask) 2039 mask = &rte_flow_item_icmp6_mask; 2040 ret = mlx5_flow_item_acceptable 2041 (item, (const uint8_t *)mask, 2042 (const uint8_t *)&rte_flow_item_icmp6_mask, 2043 sizeof(struct rte_flow_item_icmp6), 2044 MLX5_ITEM_RANGE_NOT_ACCEPTED, error); 2045 if (ret < 0) 2046 return ret; 2047 return 0; 2048 } 2049 2050 /** 2051 * Validate ICMP item. 2052 * 2053 * @param[in] item 2054 * Item specification. 2055 * @param[in] item_flags 2056 * Bit-fields that holds the items detected until now. 2057 * @param[out] error 2058 * Pointer to error structure. 2059 * 2060 * @return 2061 * 0 on success, a negative errno value otherwise and rte_errno is set. 2062 */ 2063 int 2064 mlx5_flow_validate_item_icmp(const struct rte_flow_item *item, 2065 uint64_t item_flags, 2066 uint8_t target_protocol, 2067 struct rte_flow_error *error) 2068 { 2069 const struct rte_flow_item_icmp *mask = item->mask; 2070 const struct rte_flow_item_icmp nic_mask = { 2071 .hdr.icmp_type = 0xff, 2072 .hdr.icmp_code = 0xff, 2073 .hdr.icmp_ident = RTE_BE16(0xffff), 2074 .hdr.icmp_seq_nb = RTE_BE16(0xffff), 2075 }; 2076 const int tunnel = !!(item_flags & MLX5_FLOW_LAYER_TUNNEL); 2077 const uint64_t l3m = tunnel ? MLX5_FLOW_LAYER_INNER_L3_IPV4 : 2078 MLX5_FLOW_LAYER_OUTER_L3_IPV4; 2079 const uint64_t l4m = tunnel ? MLX5_FLOW_LAYER_INNER_L4 : 2080 MLX5_FLOW_LAYER_OUTER_L4; 2081 int ret; 2082 2083 if (target_protocol != 0xFF && target_protocol != IPPROTO_ICMP) 2084 return rte_flow_error_set(error, EINVAL, 2085 RTE_FLOW_ERROR_TYPE_ITEM, item, 2086 "protocol filtering not compatible" 2087 " with ICMP layer"); 2088 if (!(item_flags & l3m)) 2089 return rte_flow_error_set(error, EINVAL, 2090 RTE_FLOW_ERROR_TYPE_ITEM, item, 2091 "IPv4 is mandatory to filter" 2092 " on ICMP"); 2093 if (item_flags & l4m) 2094 return rte_flow_error_set(error, EINVAL, 2095 RTE_FLOW_ERROR_TYPE_ITEM, item, 2096 "multiple L4 layers not supported"); 2097 if (!mask) 2098 mask = &nic_mask; 2099 ret = mlx5_flow_item_acceptable 2100 (item, (const uint8_t *)mask, 2101 (const uint8_t *)&nic_mask, 2102 sizeof(struct rte_flow_item_icmp), 2103 MLX5_ITEM_RANGE_NOT_ACCEPTED, error); 2104 if (ret < 0) 2105 return ret; 2106 return 0; 2107 } 2108 2109 /** 2110 * Validate Ethernet item. 2111 * 2112 * @param[in] item 2113 * Item specification. 2114 * @param[in] item_flags 2115 * Bit-fields that holds the items detected until now. 2116 * @param[out] error 2117 * Pointer to error structure. 2118 * 2119 * @return 2120 * 0 on success, a negative errno value otherwise and rte_errno is set. 2121 */ 2122 int 2123 mlx5_flow_validate_item_eth(const struct rte_flow_item *item, 2124 uint64_t item_flags, bool ext_vlan_sup, 2125 struct rte_flow_error *error) 2126 { 2127 const struct rte_flow_item_eth *mask = item->mask; 2128 const struct rte_flow_item_eth nic_mask = { 2129 .dst.addr_bytes = "\xff\xff\xff\xff\xff\xff", 2130 .src.addr_bytes = "\xff\xff\xff\xff\xff\xff", 2131 .type = RTE_BE16(0xffff), 2132 .has_vlan = ext_vlan_sup ? 1 : 0, 2133 }; 2134 int ret; 2135 int tunnel = !!(item_flags & MLX5_FLOW_LAYER_TUNNEL); 2136 const uint64_t ethm = tunnel ? MLX5_FLOW_LAYER_INNER_L2 : 2137 MLX5_FLOW_LAYER_OUTER_L2; 2138 2139 if (item_flags & ethm) 2140 return rte_flow_error_set(error, ENOTSUP, 2141 RTE_FLOW_ERROR_TYPE_ITEM, item, 2142 "multiple L2 layers not supported"); 2143 if ((!tunnel && (item_flags & MLX5_FLOW_LAYER_OUTER_L3)) || 2144 (tunnel && (item_flags & MLX5_FLOW_LAYER_INNER_L3))) 2145 return rte_flow_error_set(error, EINVAL, 2146 RTE_FLOW_ERROR_TYPE_ITEM, item, 2147 "L2 layer should not follow " 2148 "L3 layers"); 2149 if ((!tunnel && (item_flags & MLX5_FLOW_LAYER_OUTER_VLAN)) || 2150 (tunnel && (item_flags & MLX5_FLOW_LAYER_INNER_VLAN))) 2151 return rte_flow_error_set(error, EINVAL, 2152 RTE_FLOW_ERROR_TYPE_ITEM, item, 2153 "L2 layer should not follow VLAN"); 2154 if (item_flags & MLX5_FLOW_LAYER_GTP) 2155 return rte_flow_error_set(error, EINVAL, 2156 RTE_FLOW_ERROR_TYPE_ITEM, item, 2157 "L2 layer should not follow GTP"); 2158 if (!mask) 2159 mask = &rte_flow_item_eth_mask; 2160 ret = mlx5_flow_item_acceptable(item, (const uint8_t *)mask, 2161 (const uint8_t *)&nic_mask, 2162 sizeof(struct rte_flow_item_eth), 2163 MLX5_ITEM_RANGE_NOT_ACCEPTED, error); 2164 return ret; 2165 } 2166 2167 /** 2168 * Validate VLAN item. 2169 * 2170 * @param[in] item 2171 * Item specification. 2172 * @param[in] item_flags 2173 * Bit-fields that holds the items detected until now. 2174 * @param[in] dev 2175 * Ethernet device flow is being created on. 2176 * @param[out] error 2177 * Pointer to error structure. 2178 * 2179 * @return 2180 * 0 on success, a negative errno value otherwise and rte_errno is set. 2181 */ 2182 int 2183 mlx5_flow_validate_item_vlan(const struct rte_flow_item *item, 2184 uint64_t item_flags, 2185 struct rte_eth_dev *dev, 2186 struct rte_flow_error *error) 2187 { 2188 const struct rte_flow_item_vlan *spec = item->spec; 2189 const struct rte_flow_item_vlan *mask = item->mask; 2190 const struct rte_flow_item_vlan nic_mask = { 2191 .tci = RTE_BE16(UINT16_MAX), 2192 .inner_type = RTE_BE16(UINT16_MAX), 2193 }; 2194 uint16_t vlan_tag = 0; 2195 const int tunnel = !!(item_flags & MLX5_FLOW_LAYER_TUNNEL); 2196 int ret; 2197 const uint64_t l34m = tunnel ? (MLX5_FLOW_LAYER_INNER_L3 | 2198 MLX5_FLOW_LAYER_INNER_L4) : 2199 (MLX5_FLOW_LAYER_OUTER_L3 | 2200 MLX5_FLOW_LAYER_OUTER_L4); 2201 const uint64_t vlanm = tunnel ? MLX5_FLOW_LAYER_INNER_VLAN : 2202 MLX5_FLOW_LAYER_OUTER_VLAN; 2203 2204 if (item_flags & vlanm) 2205 return rte_flow_error_set(error, EINVAL, 2206 RTE_FLOW_ERROR_TYPE_ITEM, item, 2207 "multiple VLAN layers not supported"); 2208 else if ((item_flags & l34m) != 0) 2209 return rte_flow_error_set(error, EINVAL, 2210 RTE_FLOW_ERROR_TYPE_ITEM, item, 2211 "VLAN cannot follow L3/L4 layer"); 2212 if (!mask) 2213 mask = &rte_flow_item_vlan_mask; 2214 ret = mlx5_flow_item_acceptable(item, (const uint8_t *)mask, 2215 (const uint8_t *)&nic_mask, 2216 sizeof(struct rte_flow_item_vlan), 2217 MLX5_ITEM_RANGE_NOT_ACCEPTED, error); 2218 if (ret) 2219 return ret; 2220 if (!tunnel && mask->tci != RTE_BE16(0x0fff)) { 2221 struct mlx5_priv *priv = dev->data->dev_private; 2222 2223 if (priv->vmwa_context) { 2224 /* 2225 * Non-NULL context means we have a virtual machine 2226 * and SR-IOV enabled, we have to create VLAN interface 2227 * to make hypervisor to setup E-Switch vport 2228 * context correctly. We avoid creating the multiple 2229 * VLAN interfaces, so we cannot support VLAN tag mask. 2230 */ 2231 return rte_flow_error_set(error, EINVAL, 2232 RTE_FLOW_ERROR_TYPE_ITEM, 2233 item, 2234 "VLAN tag mask is not" 2235 " supported in virtual" 2236 " environment"); 2237 } 2238 } 2239 if (spec) { 2240 vlan_tag = spec->tci; 2241 vlan_tag &= mask->tci; 2242 } 2243 /* 2244 * From verbs perspective an empty VLAN is equivalent 2245 * to a packet without VLAN layer. 2246 */ 2247 if (!vlan_tag) 2248 return rte_flow_error_set(error, EINVAL, 2249 RTE_FLOW_ERROR_TYPE_ITEM_SPEC, 2250 item->spec, 2251 "VLAN cannot be empty"); 2252 return 0; 2253 } 2254 2255 /** 2256 * Validate IPV4 item. 2257 * 2258 * @param[in] item 2259 * Item specification. 2260 * @param[in] item_flags 2261 * Bit-fields that holds the items detected until now. 2262 * @param[in] last_item 2263 * Previous validated item in the pattern items. 2264 * @param[in] ether_type 2265 * Type in the ethernet layer header (including dot1q). 2266 * @param[in] acc_mask 2267 * Acceptable mask, if NULL default internal default mask 2268 * will be used to check whether item fields are supported. 2269 * @param[in] range_accepted 2270 * True if range of values is accepted for specific fields, false otherwise. 2271 * @param[out] error 2272 * Pointer to error structure. 2273 * 2274 * @return 2275 * 0 on success, a negative errno value otherwise and rte_errno is set. 2276 */ 2277 int 2278 mlx5_flow_validate_item_ipv4(const struct rte_flow_item *item, 2279 uint64_t item_flags, 2280 uint64_t last_item, 2281 uint16_t ether_type, 2282 const struct rte_flow_item_ipv4 *acc_mask, 2283 bool range_accepted, 2284 struct rte_flow_error *error) 2285 { 2286 const struct rte_flow_item_ipv4 *mask = item->mask; 2287 const struct rte_flow_item_ipv4 *spec = item->spec; 2288 const struct rte_flow_item_ipv4 nic_mask = { 2289 .hdr = { 2290 .src_addr = RTE_BE32(0xffffffff), 2291 .dst_addr = RTE_BE32(0xffffffff), 2292 .type_of_service = 0xff, 2293 .next_proto_id = 0xff, 2294 }, 2295 }; 2296 const int tunnel = !!(item_flags & MLX5_FLOW_LAYER_TUNNEL); 2297 const uint64_t l3m = tunnel ? MLX5_FLOW_LAYER_INNER_L3 : 2298 MLX5_FLOW_LAYER_OUTER_L3; 2299 const uint64_t l4m = tunnel ? MLX5_FLOW_LAYER_INNER_L4 : 2300 MLX5_FLOW_LAYER_OUTER_L4; 2301 int ret; 2302 uint8_t next_proto = 0xFF; 2303 const uint64_t l2_vlan = (MLX5_FLOW_LAYER_L2 | 2304 MLX5_FLOW_LAYER_OUTER_VLAN | 2305 MLX5_FLOW_LAYER_INNER_VLAN); 2306 2307 if ((last_item & l2_vlan) && ether_type && 2308 ether_type != RTE_ETHER_TYPE_IPV4) 2309 return rte_flow_error_set(error, EINVAL, 2310 RTE_FLOW_ERROR_TYPE_ITEM, item, 2311 "IPv4 cannot follow L2/VLAN layer " 2312 "which ether type is not IPv4"); 2313 if (item_flags & MLX5_FLOW_LAYER_TUNNEL) { 2314 if (mask && spec) 2315 next_proto = mask->hdr.next_proto_id & 2316 spec->hdr.next_proto_id; 2317 if (next_proto == IPPROTO_IPIP || next_proto == IPPROTO_IPV6) 2318 return rte_flow_error_set(error, EINVAL, 2319 RTE_FLOW_ERROR_TYPE_ITEM, 2320 item, 2321 "multiple tunnel " 2322 "not supported"); 2323 } 2324 if (item_flags & MLX5_FLOW_LAYER_IPV6_ENCAP) 2325 return rte_flow_error_set(error, EINVAL, 2326 RTE_FLOW_ERROR_TYPE_ITEM, item, 2327 "wrong tunnel type - IPv6 specified " 2328 "but IPv4 item provided"); 2329 if (item_flags & l3m) 2330 return rte_flow_error_set(error, ENOTSUP, 2331 RTE_FLOW_ERROR_TYPE_ITEM, item, 2332 "multiple L3 layers not supported"); 2333 else if (item_flags & l4m) 2334 return rte_flow_error_set(error, EINVAL, 2335 RTE_FLOW_ERROR_TYPE_ITEM, item, 2336 "L3 cannot follow an L4 layer."); 2337 else if ((item_flags & MLX5_FLOW_LAYER_NVGRE) && 2338 !(item_flags & MLX5_FLOW_LAYER_INNER_L2)) 2339 return rte_flow_error_set(error, EINVAL, 2340 RTE_FLOW_ERROR_TYPE_ITEM, item, 2341 "L3 cannot follow an NVGRE layer."); 2342 if (!mask) 2343 mask = &rte_flow_item_ipv4_mask; 2344 else if (mask->hdr.next_proto_id != 0 && 2345 mask->hdr.next_proto_id != 0xff) 2346 return rte_flow_error_set(error, EINVAL, 2347 RTE_FLOW_ERROR_TYPE_ITEM_MASK, mask, 2348 "partial mask is not supported" 2349 " for protocol"); 2350 ret = mlx5_flow_item_acceptable(item, (const uint8_t *)mask, 2351 acc_mask ? (const uint8_t *)acc_mask 2352 : (const uint8_t *)&nic_mask, 2353 sizeof(struct rte_flow_item_ipv4), 2354 range_accepted, error); 2355 if (ret < 0) 2356 return ret; 2357 return 0; 2358 } 2359 2360 /** 2361 * Validate IPV6 item. 2362 * 2363 * @param[in] item 2364 * Item specification. 2365 * @param[in] item_flags 2366 * Bit-fields that holds the items detected until now. 2367 * @param[in] last_item 2368 * Previous validated item in the pattern items. 2369 * @param[in] ether_type 2370 * Type in the ethernet layer header (including dot1q). 2371 * @param[in] acc_mask 2372 * Acceptable mask, if NULL default internal default mask 2373 * will be used to check whether item fields are supported. 2374 * @param[out] error 2375 * Pointer to error structure. 2376 * 2377 * @return 2378 * 0 on success, a negative errno value otherwise and rte_errno is set. 2379 */ 2380 int 2381 mlx5_flow_validate_item_ipv6(const struct rte_flow_item *item, 2382 uint64_t item_flags, 2383 uint64_t last_item, 2384 uint16_t ether_type, 2385 const struct rte_flow_item_ipv6 *acc_mask, 2386 struct rte_flow_error *error) 2387 { 2388 const struct rte_flow_item_ipv6 *mask = item->mask; 2389 const struct rte_flow_item_ipv6 *spec = item->spec; 2390 const struct rte_flow_item_ipv6 nic_mask = { 2391 .hdr = { 2392 .src_addr = 2393 "\xff\xff\xff\xff\xff\xff\xff\xff" 2394 "\xff\xff\xff\xff\xff\xff\xff\xff", 2395 .dst_addr = 2396 "\xff\xff\xff\xff\xff\xff\xff\xff" 2397 "\xff\xff\xff\xff\xff\xff\xff\xff", 2398 .vtc_flow = RTE_BE32(0xffffffff), 2399 .proto = 0xff, 2400 }, 2401 }; 2402 const int tunnel = !!(item_flags & MLX5_FLOW_LAYER_TUNNEL); 2403 const uint64_t l3m = tunnel ? MLX5_FLOW_LAYER_INNER_L3 : 2404 MLX5_FLOW_LAYER_OUTER_L3; 2405 const uint64_t l4m = tunnel ? MLX5_FLOW_LAYER_INNER_L4 : 2406 MLX5_FLOW_LAYER_OUTER_L4; 2407 int ret; 2408 uint8_t next_proto = 0xFF; 2409 const uint64_t l2_vlan = (MLX5_FLOW_LAYER_L2 | 2410 MLX5_FLOW_LAYER_OUTER_VLAN | 2411 MLX5_FLOW_LAYER_INNER_VLAN); 2412 2413 if ((last_item & l2_vlan) && ether_type && 2414 ether_type != RTE_ETHER_TYPE_IPV6) 2415 return rte_flow_error_set(error, EINVAL, 2416 RTE_FLOW_ERROR_TYPE_ITEM, item, 2417 "IPv6 cannot follow L2/VLAN layer " 2418 "which ether type is not IPv6"); 2419 if (mask && mask->hdr.proto == UINT8_MAX && spec) 2420 next_proto = spec->hdr.proto; 2421 if (item_flags & MLX5_FLOW_LAYER_TUNNEL) { 2422 if (next_proto == IPPROTO_IPIP || next_proto == IPPROTO_IPV6) 2423 return rte_flow_error_set(error, EINVAL, 2424 RTE_FLOW_ERROR_TYPE_ITEM, 2425 item, 2426 "multiple tunnel " 2427 "not supported"); 2428 } 2429 if (next_proto == IPPROTO_HOPOPTS || 2430 next_proto == IPPROTO_ROUTING || 2431 next_proto == IPPROTO_FRAGMENT || 2432 next_proto == IPPROTO_ESP || 2433 next_proto == IPPROTO_AH || 2434 next_proto == IPPROTO_DSTOPTS) 2435 return rte_flow_error_set(error, EINVAL, 2436 RTE_FLOW_ERROR_TYPE_ITEM, item, 2437 "IPv6 proto (next header) should " 2438 "not be set as extension header"); 2439 if (item_flags & MLX5_FLOW_LAYER_IPIP) 2440 return rte_flow_error_set(error, EINVAL, 2441 RTE_FLOW_ERROR_TYPE_ITEM, item, 2442 "wrong tunnel type - IPv4 specified " 2443 "but IPv6 item provided"); 2444 if (item_flags & l3m) 2445 return rte_flow_error_set(error, ENOTSUP, 2446 RTE_FLOW_ERROR_TYPE_ITEM, item, 2447 "multiple L3 layers not supported"); 2448 else if (item_flags & l4m) 2449 return rte_flow_error_set(error, EINVAL, 2450 RTE_FLOW_ERROR_TYPE_ITEM, item, 2451 "L3 cannot follow an L4 layer."); 2452 else if ((item_flags & MLX5_FLOW_LAYER_NVGRE) && 2453 !(item_flags & MLX5_FLOW_LAYER_INNER_L2)) 2454 return rte_flow_error_set(error, EINVAL, 2455 RTE_FLOW_ERROR_TYPE_ITEM, item, 2456 "L3 cannot follow an NVGRE layer."); 2457 if (!mask) 2458 mask = &rte_flow_item_ipv6_mask; 2459 ret = mlx5_flow_item_acceptable(item, (const uint8_t *)mask, 2460 acc_mask ? (const uint8_t *)acc_mask 2461 : (const uint8_t *)&nic_mask, 2462 sizeof(struct rte_flow_item_ipv6), 2463 MLX5_ITEM_RANGE_NOT_ACCEPTED, error); 2464 if (ret < 0) 2465 return ret; 2466 return 0; 2467 } 2468 2469 /** 2470 * Validate UDP item. 2471 * 2472 * @param[in] item 2473 * Item specification. 2474 * @param[in] item_flags 2475 * Bit-fields that holds the items detected until now. 2476 * @param[in] target_protocol 2477 * The next protocol in the previous item. 2478 * @param[in] flow_mask 2479 * mlx5 flow-specific (DV, verbs, etc.) supported header fields mask. 2480 * @param[out] error 2481 * Pointer to error structure. 2482 * 2483 * @return 2484 * 0 on success, a negative errno value otherwise and rte_errno is set. 2485 */ 2486 int 2487 mlx5_flow_validate_item_udp(const struct rte_flow_item *item, 2488 uint64_t item_flags, 2489 uint8_t target_protocol, 2490 struct rte_flow_error *error) 2491 { 2492 const struct rte_flow_item_udp *mask = item->mask; 2493 const int tunnel = !!(item_flags & MLX5_FLOW_LAYER_TUNNEL); 2494 const uint64_t l3m = tunnel ? MLX5_FLOW_LAYER_INNER_L3 : 2495 MLX5_FLOW_LAYER_OUTER_L3; 2496 const uint64_t l4m = tunnel ? MLX5_FLOW_LAYER_INNER_L4 : 2497 MLX5_FLOW_LAYER_OUTER_L4; 2498 int ret; 2499 2500 if (target_protocol != 0xff && target_protocol != IPPROTO_UDP) 2501 return rte_flow_error_set(error, EINVAL, 2502 RTE_FLOW_ERROR_TYPE_ITEM, item, 2503 "protocol filtering not compatible" 2504 " with UDP layer"); 2505 if (!(item_flags & l3m)) 2506 return rte_flow_error_set(error, EINVAL, 2507 RTE_FLOW_ERROR_TYPE_ITEM, item, 2508 "L3 is mandatory to filter on L4"); 2509 if (item_flags & l4m) 2510 return rte_flow_error_set(error, EINVAL, 2511 RTE_FLOW_ERROR_TYPE_ITEM, item, 2512 "multiple L4 layers not supported"); 2513 if (!mask) 2514 mask = &rte_flow_item_udp_mask; 2515 ret = mlx5_flow_item_acceptable 2516 (item, (const uint8_t *)mask, 2517 (const uint8_t *)&rte_flow_item_udp_mask, 2518 sizeof(struct rte_flow_item_udp), MLX5_ITEM_RANGE_NOT_ACCEPTED, 2519 error); 2520 if (ret < 0) 2521 return ret; 2522 return 0; 2523 } 2524 2525 /** 2526 * Validate TCP item. 2527 * 2528 * @param[in] item 2529 * Item specification. 2530 * @param[in] item_flags 2531 * Bit-fields that holds the items detected until now. 2532 * @param[in] target_protocol 2533 * The next protocol in the previous item. 2534 * @param[out] error 2535 * Pointer to error structure. 2536 * 2537 * @return 2538 * 0 on success, a negative errno value otherwise and rte_errno is set. 2539 */ 2540 int 2541 mlx5_flow_validate_item_tcp(const struct rte_flow_item *item, 2542 uint64_t item_flags, 2543 uint8_t target_protocol, 2544 const struct rte_flow_item_tcp *flow_mask, 2545 struct rte_flow_error *error) 2546 { 2547 const struct rte_flow_item_tcp *mask = item->mask; 2548 const int tunnel = !!(item_flags & MLX5_FLOW_LAYER_TUNNEL); 2549 const uint64_t l3m = tunnel ? MLX5_FLOW_LAYER_INNER_L3 : 2550 MLX5_FLOW_LAYER_OUTER_L3; 2551 const uint64_t l4m = tunnel ? MLX5_FLOW_LAYER_INNER_L4 : 2552 MLX5_FLOW_LAYER_OUTER_L4; 2553 int ret; 2554 2555 MLX5_ASSERT(flow_mask); 2556 if (target_protocol != 0xff && target_protocol != IPPROTO_TCP) 2557 return rte_flow_error_set(error, EINVAL, 2558 RTE_FLOW_ERROR_TYPE_ITEM, item, 2559 "protocol filtering not compatible" 2560 " with TCP layer"); 2561 if (!(item_flags & l3m)) 2562 return rte_flow_error_set(error, EINVAL, 2563 RTE_FLOW_ERROR_TYPE_ITEM, item, 2564 "L3 is mandatory to filter on L4"); 2565 if (item_flags & l4m) 2566 return rte_flow_error_set(error, EINVAL, 2567 RTE_FLOW_ERROR_TYPE_ITEM, item, 2568 "multiple L4 layers not supported"); 2569 if (!mask) 2570 mask = &rte_flow_item_tcp_mask; 2571 ret = mlx5_flow_item_acceptable 2572 (item, (const uint8_t *)mask, 2573 (const uint8_t *)flow_mask, 2574 sizeof(struct rte_flow_item_tcp), MLX5_ITEM_RANGE_NOT_ACCEPTED, 2575 error); 2576 if (ret < 0) 2577 return ret; 2578 return 0; 2579 } 2580 2581 /** 2582 * Validate VXLAN item. 2583 * 2584 * @param[in] dev 2585 * Pointer to the Ethernet device structure. 2586 * @param[in] udp_dport 2587 * UDP destination port 2588 * @param[in] item 2589 * Item specification. 2590 * @param[in] item_flags 2591 * Bit-fields that holds the items detected until now. 2592 * @param[in] attr 2593 * Flow rule attributes. 2594 * @param[out] error 2595 * Pointer to error structure. 2596 * 2597 * @return 2598 * 0 on success, a negative errno value otherwise and rte_errno is set. 2599 */ 2600 int 2601 mlx5_flow_validate_item_vxlan(struct rte_eth_dev *dev, 2602 uint16_t udp_dport, 2603 const struct rte_flow_item *item, 2604 uint64_t item_flags, 2605 const struct rte_flow_attr *attr, 2606 struct rte_flow_error *error) 2607 { 2608 const struct rte_flow_item_vxlan *spec = item->spec; 2609 const struct rte_flow_item_vxlan *mask = item->mask; 2610 int ret; 2611 struct mlx5_priv *priv = dev->data->dev_private; 2612 union vni { 2613 uint32_t vlan_id; 2614 uint8_t vni[4]; 2615 } id = { .vlan_id = 0, }; 2616 const struct rte_flow_item_vxlan nic_mask = { 2617 .vni = "\xff\xff\xff", 2618 .rsvd1 = 0xff, 2619 }; 2620 const struct rte_flow_item_vxlan *valid_mask; 2621 2622 if (item_flags & MLX5_FLOW_LAYER_TUNNEL) 2623 return rte_flow_error_set(error, ENOTSUP, 2624 RTE_FLOW_ERROR_TYPE_ITEM, item, 2625 "multiple tunnel layers not" 2626 " supported"); 2627 valid_mask = &rte_flow_item_vxlan_mask; 2628 /* 2629 * Verify only UDPv4 is present as defined in 2630 * https://tools.ietf.org/html/rfc7348 2631 */ 2632 if (!(item_flags & MLX5_FLOW_LAYER_OUTER_L4_UDP)) 2633 return rte_flow_error_set(error, EINVAL, 2634 RTE_FLOW_ERROR_TYPE_ITEM, item, 2635 "no outer UDP layer found"); 2636 if (!mask) 2637 mask = &rte_flow_item_vxlan_mask; 2638 2639 if (priv->sh->steering_format_version != 2640 MLX5_STEERING_LOGIC_FORMAT_CONNECTX_5 || 2641 !udp_dport || udp_dport == MLX5_UDP_PORT_VXLAN) { 2642 /* FDB domain & NIC domain non-zero group */ 2643 if ((attr->transfer || attr->group) && priv->sh->misc5_cap) 2644 valid_mask = &nic_mask; 2645 /* Group zero in NIC domain */ 2646 if (!attr->group && !attr->transfer && 2647 priv->sh->tunnel_header_0_1) 2648 valid_mask = &nic_mask; 2649 } 2650 ret = mlx5_flow_item_acceptable 2651 (item, (const uint8_t *)mask, 2652 (const uint8_t *)valid_mask, 2653 sizeof(struct rte_flow_item_vxlan), 2654 MLX5_ITEM_RANGE_NOT_ACCEPTED, error); 2655 if (ret < 0) 2656 return ret; 2657 if (spec) { 2658 memcpy(&id.vni[1], spec->vni, 3); 2659 memcpy(&id.vni[1], mask->vni, 3); 2660 } 2661 if (!(item_flags & MLX5_FLOW_LAYER_OUTER)) 2662 return rte_flow_error_set(error, ENOTSUP, 2663 RTE_FLOW_ERROR_TYPE_ITEM, item, 2664 "VXLAN tunnel must be fully defined"); 2665 return 0; 2666 } 2667 2668 /** 2669 * Validate VXLAN_GPE item. 2670 * 2671 * @param[in] item 2672 * Item specification. 2673 * @param[in] item_flags 2674 * Bit-fields that holds the items detected until now. 2675 * @param[in] priv 2676 * Pointer to the private data structure. 2677 * @param[in] target_protocol 2678 * The next protocol in the previous item. 2679 * @param[out] error 2680 * Pointer to error structure. 2681 * 2682 * @return 2683 * 0 on success, a negative errno value otherwise and rte_errno is set. 2684 */ 2685 int 2686 mlx5_flow_validate_item_vxlan_gpe(const struct rte_flow_item *item, 2687 uint64_t item_flags, 2688 struct rte_eth_dev *dev, 2689 struct rte_flow_error *error) 2690 { 2691 struct mlx5_priv *priv = dev->data->dev_private; 2692 const struct rte_flow_item_vxlan_gpe *spec = item->spec; 2693 const struct rte_flow_item_vxlan_gpe *mask = item->mask; 2694 int ret; 2695 union vni { 2696 uint32_t vlan_id; 2697 uint8_t vni[4]; 2698 } id = { .vlan_id = 0, }; 2699 2700 if (!priv->config.l3_vxlan_en) 2701 return rte_flow_error_set(error, ENOTSUP, 2702 RTE_FLOW_ERROR_TYPE_ITEM, item, 2703 "L3 VXLAN is not enabled by device" 2704 " parameter and/or not configured in" 2705 " firmware"); 2706 if (item_flags & MLX5_FLOW_LAYER_TUNNEL) 2707 return rte_flow_error_set(error, ENOTSUP, 2708 RTE_FLOW_ERROR_TYPE_ITEM, item, 2709 "multiple tunnel layers not" 2710 " supported"); 2711 /* 2712 * Verify only UDPv4 is present as defined in 2713 * https://tools.ietf.org/html/rfc7348 2714 */ 2715 if (!(item_flags & MLX5_FLOW_LAYER_OUTER_L4_UDP)) 2716 return rte_flow_error_set(error, EINVAL, 2717 RTE_FLOW_ERROR_TYPE_ITEM, item, 2718 "no outer UDP layer found"); 2719 if (!mask) 2720 mask = &rte_flow_item_vxlan_gpe_mask; 2721 ret = mlx5_flow_item_acceptable 2722 (item, (const uint8_t *)mask, 2723 (const uint8_t *)&rte_flow_item_vxlan_gpe_mask, 2724 sizeof(struct rte_flow_item_vxlan_gpe), 2725 MLX5_ITEM_RANGE_NOT_ACCEPTED, error); 2726 if (ret < 0) 2727 return ret; 2728 if (spec) { 2729 if (spec->protocol) 2730 return rte_flow_error_set(error, ENOTSUP, 2731 RTE_FLOW_ERROR_TYPE_ITEM, 2732 item, 2733 "VxLAN-GPE protocol" 2734 " not supported"); 2735 memcpy(&id.vni[1], spec->vni, 3); 2736 memcpy(&id.vni[1], mask->vni, 3); 2737 } 2738 if (!(item_flags & MLX5_FLOW_LAYER_OUTER)) 2739 return rte_flow_error_set(error, ENOTSUP, 2740 RTE_FLOW_ERROR_TYPE_ITEM, item, 2741 "VXLAN-GPE tunnel must be fully" 2742 " defined"); 2743 return 0; 2744 } 2745 /** 2746 * Validate GRE Key item. 2747 * 2748 * @param[in] item 2749 * Item specification. 2750 * @param[in] item_flags 2751 * Bit flags to mark detected items. 2752 * @param[in] gre_item 2753 * Pointer to gre_item 2754 * @param[out] error 2755 * Pointer to error structure. 2756 * 2757 * @return 2758 * 0 on success, a negative errno value otherwise and rte_errno is set. 2759 */ 2760 int 2761 mlx5_flow_validate_item_gre_key(const struct rte_flow_item *item, 2762 uint64_t item_flags, 2763 const struct rte_flow_item *gre_item, 2764 struct rte_flow_error *error) 2765 { 2766 const rte_be32_t *mask = item->mask; 2767 int ret = 0; 2768 rte_be32_t gre_key_default_mask = RTE_BE32(UINT32_MAX); 2769 const struct rte_flow_item_gre *gre_spec; 2770 const struct rte_flow_item_gre *gre_mask; 2771 2772 if (item_flags & MLX5_FLOW_LAYER_GRE_KEY) 2773 return rte_flow_error_set(error, ENOTSUP, 2774 RTE_FLOW_ERROR_TYPE_ITEM, item, 2775 "Multiple GRE key not support"); 2776 if (!(item_flags & MLX5_FLOW_LAYER_GRE)) 2777 return rte_flow_error_set(error, ENOTSUP, 2778 RTE_FLOW_ERROR_TYPE_ITEM, item, 2779 "No preceding GRE header"); 2780 if (item_flags & MLX5_FLOW_LAYER_INNER) 2781 return rte_flow_error_set(error, ENOTSUP, 2782 RTE_FLOW_ERROR_TYPE_ITEM, item, 2783 "GRE key following a wrong item"); 2784 gre_mask = gre_item->mask; 2785 if (!gre_mask) 2786 gre_mask = &rte_flow_item_gre_mask; 2787 gre_spec = gre_item->spec; 2788 if (gre_spec && (gre_mask->c_rsvd0_ver & RTE_BE16(0x2000)) && 2789 !(gre_spec->c_rsvd0_ver & RTE_BE16(0x2000))) 2790 return rte_flow_error_set(error, EINVAL, 2791 RTE_FLOW_ERROR_TYPE_ITEM, item, 2792 "Key bit must be on"); 2793 2794 if (!mask) 2795 mask = &gre_key_default_mask; 2796 ret = mlx5_flow_item_acceptable 2797 (item, (const uint8_t *)mask, 2798 (const uint8_t *)&gre_key_default_mask, 2799 sizeof(rte_be32_t), MLX5_ITEM_RANGE_NOT_ACCEPTED, error); 2800 return ret; 2801 } 2802 2803 /** 2804 * Validate GRE item. 2805 * 2806 * @param[in] item 2807 * Item specification. 2808 * @param[in] item_flags 2809 * Bit flags to mark detected items. 2810 * @param[in] target_protocol 2811 * The next protocol in the previous item. 2812 * @param[out] error 2813 * Pointer to error structure. 2814 * 2815 * @return 2816 * 0 on success, a negative errno value otherwise and rte_errno is set. 2817 */ 2818 int 2819 mlx5_flow_validate_item_gre(const struct rte_flow_item *item, 2820 uint64_t item_flags, 2821 uint8_t target_protocol, 2822 struct rte_flow_error *error) 2823 { 2824 const struct rte_flow_item_gre *spec __rte_unused = item->spec; 2825 const struct rte_flow_item_gre *mask = item->mask; 2826 int ret; 2827 const struct rte_flow_item_gre nic_mask = { 2828 .c_rsvd0_ver = RTE_BE16(0xB000), 2829 .protocol = RTE_BE16(UINT16_MAX), 2830 }; 2831 2832 if (target_protocol != 0xff && target_protocol != IPPROTO_GRE) 2833 return rte_flow_error_set(error, EINVAL, 2834 RTE_FLOW_ERROR_TYPE_ITEM, item, 2835 "protocol filtering not compatible" 2836 " with this GRE layer"); 2837 if (item_flags & MLX5_FLOW_LAYER_TUNNEL) 2838 return rte_flow_error_set(error, ENOTSUP, 2839 RTE_FLOW_ERROR_TYPE_ITEM, item, 2840 "multiple tunnel layers not" 2841 " supported"); 2842 if (!(item_flags & MLX5_FLOW_LAYER_OUTER_L3)) 2843 return rte_flow_error_set(error, ENOTSUP, 2844 RTE_FLOW_ERROR_TYPE_ITEM, item, 2845 "L3 Layer is missing"); 2846 if (!mask) 2847 mask = &rte_flow_item_gre_mask; 2848 ret = mlx5_flow_item_acceptable 2849 (item, (const uint8_t *)mask, 2850 (const uint8_t *)&nic_mask, 2851 sizeof(struct rte_flow_item_gre), MLX5_ITEM_RANGE_NOT_ACCEPTED, 2852 error); 2853 if (ret < 0) 2854 return ret; 2855 #ifndef HAVE_MLX5DV_DR 2856 #ifndef HAVE_IBV_DEVICE_MPLS_SUPPORT 2857 if (spec && (spec->protocol & mask->protocol)) 2858 return rte_flow_error_set(error, ENOTSUP, 2859 RTE_FLOW_ERROR_TYPE_ITEM, item, 2860 "without MPLS support the" 2861 " specification cannot be used for" 2862 " filtering"); 2863 #endif 2864 #endif 2865 return 0; 2866 } 2867 2868 /** 2869 * Validate Geneve item. 2870 * 2871 * @param[in] item 2872 * Item specification. 2873 * @param[in] itemFlags 2874 * Bit-fields that holds the items detected until now. 2875 * @param[in] enPriv 2876 * Pointer to the private data structure. 2877 * @param[out] error 2878 * Pointer to error structure. 2879 * 2880 * @return 2881 * 0 on success, a negative errno value otherwise and rte_errno is set. 2882 */ 2883 2884 int 2885 mlx5_flow_validate_item_geneve(const struct rte_flow_item *item, 2886 uint64_t item_flags, 2887 struct rte_eth_dev *dev, 2888 struct rte_flow_error *error) 2889 { 2890 struct mlx5_priv *priv = dev->data->dev_private; 2891 const struct rte_flow_item_geneve *spec = item->spec; 2892 const struct rte_flow_item_geneve *mask = item->mask; 2893 int ret; 2894 uint16_t gbhdr; 2895 uint8_t opt_len = priv->config.hca_attr.geneve_max_opt_len ? 2896 MLX5_GENEVE_OPT_LEN_1 : MLX5_GENEVE_OPT_LEN_0; 2897 const struct rte_flow_item_geneve nic_mask = { 2898 .ver_opt_len_o_c_rsvd0 = RTE_BE16(0x3f80), 2899 .vni = "\xff\xff\xff", 2900 .protocol = RTE_BE16(UINT16_MAX), 2901 }; 2902 2903 if (!priv->config.hca_attr.tunnel_stateless_geneve_rx) 2904 return rte_flow_error_set(error, ENOTSUP, 2905 RTE_FLOW_ERROR_TYPE_ITEM, item, 2906 "L3 Geneve is not enabled by device" 2907 " parameter and/or not configured in" 2908 " firmware"); 2909 if (item_flags & MLX5_FLOW_LAYER_TUNNEL) 2910 return rte_flow_error_set(error, ENOTSUP, 2911 RTE_FLOW_ERROR_TYPE_ITEM, item, 2912 "multiple tunnel layers not" 2913 " supported"); 2914 /* 2915 * Verify only UDPv4 is present as defined in 2916 * https://tools.ietf.org/html/rfc7348 2917 */ 2918 if (!(item_flags & MLX5_FLOW_LAYER_OUTER_L4_UDP)) 2919 return rte_flow_error_set(error, EINVAL, 2920 RTE_FLOW_ERROR_TYPE_ITEM, item, 2921 "no outer UDP layer found"); 2922 if (!mask) 2923 mask = &rte_flow_item_geneve_mask; 2924 ret = mlx5_flow_item_acceptable 2925 (item, (const uint8_t *)mask, 2926 (const uint8_t *)&nic_mask, 2927 sizeof(struct rte_flow_item_geneve), 2928 MLX5_ITEM_RANGE_NOT_ACCEPTED, error); 2929 if (ret) 2930 return ret; 2931 if (spec) { 2932 gbhdr = rte_be_to_cpu_16(spec->ver_opt_len_o_c_rsvd0); 2933 if (MLX5_GENEVE_VER_VAL(gbhdr) || 2934 MLX5_GENEVE_CRITO_VAL(gbhdr) || 2935 MLX5_GENEVE_RSVD_VAL(gbhdr) || spec->rsvd1) 2936 return rte_flow_error_set(error, ENOTSUP, 2937 RTE_FLOW_ERROR_TYPE_ITEM, 2938 item, 2939 "Geneve protocol unsupported" 2940 " fields are being used"); 2941 if (MLX5_GENEVE_OPTLEN_VAL(gbhdr) > opt_len) 2942 return rte_flow_error_set 2943 (error, ENOTSUP, 2944 RTE_FLOW_ERROR_TYPE_ITEM, 2945 item, 2946 "Unsupported Geneve options length"); 2947 } 2948 if (!(item_flags & MLX5_FLOW_LAYER_OUTER)) 2949 return rte_flow_error_set 2950 (error, ENOTSUP, 2951 RTE_FLOW_ERROR_TYPE_ITEM, item, 2952 "Geneve tunnel must be fully defined"); 2953 return 0; 2954 } 2955 2956 /** 2957 * Validate Geneve TLV option item. 2958 * 2959 * @param[in] item 2960 * Item specification. 2961 * @param[in] last_item 2962 * Previous validated item in the pattern items. 2963 * @param[in] geneve_item 2964 * Previous GENEVE item specification. 2965 * @param[in] dev 2966 * Pointer to the rte_eth_dev structure. 2967 * @param[out] error 2968 * Pointer to error structure. 2969 * 2970 * @return 2971 * 0 on success, a negative errno value otherwise and rte_errno is set. 2972 */ 2973 int 2974 mlx5_flow_validate_item_geneve_opt(const struct rte_flow_item *item, 2975 uint64_t last_item, 2976 const struct rte_flow_item *geneve_item, 2977 struct rte_eth_dev *dev, 2978 struct rte_flow_error *error) 2979 { 2980 struct mlx5_priv *priv = dev->data->dev_private; 2981 struct mlx5_dev_ctx_shared *sh = priv->sh; 2982 struct mlx5_geneve_tlv_option_resource *geneve_opt_resource; 2983 struct mlx5_hca_attr *hca_attr = &priv->config.hca_attr; 2984 uint8_t data_max_supported = 2985 hca_attr->max_geneve_tlv_option_data_len * 4; 2986 struct mlx5_dev_config *config = &priv->config; 2987 const struct rte_flow_item_geneve *geneve_spec; 2988 const struct rte_flow_item_geneve *geneve_mask; 2989 const struct rte_flow_item_geneve_opt *spec = item->spec; 2990 const struct rte_flow_item_geneve_opt *mask = item->mask; 2991 unsigned int i; 2992 unsigned int data_len; 2993 uint8_t tlv_option_len; 2994 uint16_t optlen_m, optlen_v; 2995 const struct rte_flow_item_geneve_opt full_mask = { 2996 .option_class = RTE_BE16(0xffff), 2997 .option_type = 0xff, 2998 .option_len = 0x1f, 2999 }; 3000 3001 if (!mask) 3002 mask = &rte_flow_item_geneve_opt_mask; 3003 if (!spec) 3004 return rte_flow_error_set 3005 (error, ENOTSUP, RTE_FLOW_ERROR_TYPE_ITEM, item, 3006 "Geneve TLV opt class/type/length must be specified"); 3007 if ((uint32_t)spec->option_len > MLX5_GENEVE_OPTLEN_MASK) 3008 return rte_flow_error_set 3009 (error, ENOTSUP, RTE_FLOW_ERROR_TYPE_ITEM, item, 3010 "Geneve TLV opt length exceeeds the limit (31)"); 3011 /* Check if class type and length masks are full. */ 3012 if (full_mask.option_class != mask->option_class || 3013 full_mask.option_type != mask->option_type || 3014 full_mask.option_len != (mask->option_len & full_mask.option_len)) 3015 return rte_flow_error_set 3016 (error, ENOTSUP, RTE_FLOW_ERROR_TYPE_ITEM, item, 3017 "Geneve TLV opt class/type/length masks must be full"); 3018 /* Check if length is supported */ 3019 if ((uint32_t)spec->option_len > 3020 config->hca_attr.max_geneve_tlv_option_data_len) 3021 return rte_flow_error_set 3022 (error, ENOTSUP, RTE_FLOW_ERROR_TYPE_ITEM, item, 3023 "Geneve TLV opt length not supported"); 3024 if (config->hca_attr.max_geneve_tlv_options > 1) 3025 DRV_LOG(DEBUG, 3026 "max_geneve_tlv_options supports more than 1 option"); 3027 /* Check GENEVE item preceding. */ 3028 if (!geneve_item || !(last_item & MLX5_FLOW_LAYER_GENEVE)) 3029 return rte_flow_error_set 3030 (error, ENOTSUP, RTE_FLOW_ERROR_TYPE_ITEM, item, 3031 "Geneve opt item must be preceded with Geneve item"); 3032 geneve_spec = geneve_item->spec; 3033 geneve_mask = geneve_item->mask ? geneve_item->mask : 3034 &rte_flow_item_geneve_mask; 3035 /* Check if GENEVE TLV option size doesn't exceed option length */ 3036 if (geneve_spec && (geneve_mask->ver_opt_len_o_c_rsvd0 || 3037 geneve_spec->ver_opt_len_o_c_rsvd0)) { 3038 tlv_option_len = spec->option_len & mask->option_len; 3039 optlen_v = rte_be_to_cpu_16(geneve_spec->ver_opt_len_o_c_rsvd0); 3040 optlen_v = MLX5_GENEVE_OPTLEN_VAL(optlen_v); 3041 optlen_m = rte_be_to_cpu_16(geneve_mask->ver_opt_len_o_c_rsvd0); 3042 optlen_m = MLX5_GENEVE_OPTLEN_VAL(optlen_m); 3043 if ((optlen_v & optlen_m) <= tlv_option_len) 3044 return rte_flow_error_set 3045 (error, ENOTSUP, RTE_FLOW_ERROR_TYPE_ITEM, item, 3046 "GENEVE TLV option length exceeds optlen"); 3047 } 3048 /* Check if length is 0 or data is 0. */ 3049 if (spec->data == NULL || spec->option_len == 0) 3050 return rte_flow_error_set 3051 (error, ENOTSUP, RTE_FLOW_ERROR_TYPE_ITEM, item, 3052 "Geneve TLV opt with zero data/length not supported"); 3053 /* Check not all data & mask are 0. */ 3054 data_len = spec->option_len * 4; 3055 if (mask->data == NULL) { 3056 for (i = 0; i < data_len; i++) 3057 if (spec->data[i]) 3058 break; 3059 if (i == data_len) 3060 return rte_flow_error_set(error, ENOTSUP, 3061 RTE_FLOW_ERROR_TYPE_ITEM, item, 3062 "Can't match on Geneve option data 0"); 3063 } else { 3064 for (i = 0; i < data_len; i++) 3065 if (spec->data[i] & mask->data[i]) 3066 break; 3067 if (i == data_len) 3068 return rte_flow_error_set(error, ENOTSUP, 3069 RTE_FLOW_ERROR_TYPE_ITEM, item, 3070 "Can't match on Geneve option data and mask 0"); 3071 /* Check data mask supported. */ 3072 for (i = data_max_supported; i < data_len ; i++) 3073 if (mask->data[i]) 3074 return rte_flow_error_set(error, ENOTSUP, 3075 RTE_FLOW_ERROR_TYPE_ITEM, item, 3076 "Data mask is of unsupported size"); 3077 } 3078 /* Check GENEVE option is supported in NIC. */ 3079 if (!config->hca_attr.geneve_tlv_opt) 3080 return rte_flow_error_set 3081 (error, ENOTSUP, RTE_FLOW_ERROR_TYPE_ITEM, item, 3082 "Geneve TLV opt not supported"); 3083 /* Check if we already have geneve option with different type/class. */ 3084 rte_spinlock_lock(&sh->geneve_tlv_opt_sl); 3085 geneve_opt_resource = sh->geneve_tlv_option_resource; 3086 if (geneve_opt_resource != NULL) 3087 if (geneve_opt_resource->option_class != spec->option_class || 3088 geneve_opt_resource->option_type != spec->option_type || 3089 geneve_opt_resource->length != spec->option_len) { 3090 rte_spinlock_unlock(&sh->geneve_tlv_opt_sl); 3091 return rte_flow_error_set(error, ENOTSUP, 3092 RTE_FLOW_ERROR_TYPE_ITEM, item, 3093 "Only one Geneve TLV option supported"); 3094 } 3095 rte_spinlock_unlock(&sh->geneve_tlv_opt_sl); 3096 return 0; 3097 } 3098 3099 /** 3100 * Validate MPLS item. 3101 * 3102 * @param[in] dev 3103 * Pointer to the rte_eth_dev structure. 3104 * @param[in] item 3105 * Item specification. 3106 * @param[in] item_flags 3107 * Bit-fields that holds the items detected until now. 3108 * @param[in] prev_layer 3109 * The protocol layer indicated in previous item. 3110 * @param[out] error 3111 * Pointer to error structure. 3112 * 3113 * @return 3114 * 0 on success, a negative errno value otherwise and rte_errno is set. 3115 */ 3116 int 3117 mlx5_flow_validate_item_mpls(struct rte_eth_dev *dev __rte_unused, 3118 const struct rte_flow_item *item __rte_unused, 3119 uint64_t item_flags __rte_unused, 3120 uint64_t prev_layer __rte_unused, 3121 struct rte_flow_error *error) 3122 { 3123 #ifdef HAVE_IBV_DEVICE_MPLS_SUPPORT 3124 const struct rte_flow_item_mpls *mask = item->mask; 3125 struct mlx5_priv *priv = dev->data->dev_private; 3126 int ret; 3127 3128 if (!priv->config.mpls_en) 3129 return rte_flow_error_set(error, ENOTSUP, 3130 RTE_FLOW_ERROR_TYPE_ITEM, item, 3131 "MPLS not supported or" 3132 " disabled in firmware" 3133 " configuration."); 3134 /* MPLS over UDP, GRE is allowed */ 3135 if (!(prev_layer & (MLX5_FLOW_LAYER_OUTER_L4_UDP | 3136 MLX5_FLOW_LAYER_GRE | 3137 MLX5_FLOW_LAYER_GRE_KEY))) 3138 return rte_flow_error_set(error, EINVAL, 3139 RTE_FLOW_ERROR_TYPE_ITEM, item, 3140 "protocol filtering not compatible" 3141 " with MPLS layer"); 3142 /* Multi-tunnel isn't allowed but MPLS over GRE is an exception. */ 3143 if ((item_flags & MLX5_FLOW_LAYER_TUNNEL) && 3144 !(item_flags & MLX5_FLOW_LAYER_GRE)) 3145 return rte_flow_error_set(error, ENOTSUP, 3146 RTE_FLOW_ERROR_TYPE_ITEM, item, 3147 "multiple tunnel layers not" 3148 " supported"); 3149 if (!mask) 3150 mask = &rte_flow_item_mpls_mask; 3151 ret = mlx5_flow_item_acceptable 3152 (item, (const uint8_t *)mask, 3153 (const uint8_t *)&rte_flow_item_mpls_mask, 3154 sizeof(struct rte_flow_item_mpls), 3155 MLX5_ITEM_RANGE_NOT_ACCEPTED, error); 3156 if (ret < 0) 3157 return ret; 3158 return 0; 3159 #else 3160 return rte_flow_error_set(error, ENOTSUP, 3161 RTE_FLOW_ERROR_TYPE_ITEM, item, 3162 "MPLS is not supported by Verbs, please" 3163 " update."); 3164 #endif 3165 } 3166 3167 /** 3168 * Validate NVGRE item. 3169 * 3170 * @param[in] item 3171 * Item specification. 3172 * @param[in] item_flags 3173 * Bit flags to mark detected items. 3174 * @param[in] target_protocol 3175 * The next protocol in the previous item. 3176 * @param[out] error 3177 * Pointer to error structure. 3178 * 3179 * @return 3180 * 0 on success, a negative errno value otherwise and rte_errno is set. 3181 */ 3182 int 3183 mlx5_flow_validate_item_nvgre(const struct rte_flow_item *item, 3184 uint64_t item_flags, 3185 uint8_t target_protocol, 3186 struct rte_flow_error *error) 3187 { 3188 const struct rte_flow_item_nvgre *mask = item->mask; 3189 int ret; 3190 3191 if (target_protocol != 0xff && target_protocol != IPPROTO_GRE) 3192 return rte_flow_error_set(error, EINVAL, 3193 RTE_FLOW_ERROR_TYPE_ITEM, item, 3194 "protocol filtering not compatible" 3195 " with this GRE layer"); 3196 if (item_flags & MLX5_FLOW_LAYER_TUNNEL) 3197 return rte_flow_error_set(error, ENOTSUP, 3198 RTE_FLOW_ERROR_TYPE_ITEM, item, 3199 "multiple tunnel layers not" 3200 " supported"); 3201 if (!(item_flags & MLX5_FLOW_LAYER_OUTER_L3)) 3202 return rte_flow_error_set(error, ENOTSUP, 3203 RTE_FLOW_ERROR_TYPE_ITEM, item, 3204 "L3 Layer is missing"); 3205 if (!mask) 3206 mask = &rte_flow_item_nvgre_mask; 3207 ret = mlx5_flow_item_acceptable 3208 (item, (const uint8_t *)mask, 3209 (const uint8_t *)&rte_flow_item_nvgre_mask, 3210 sizeof(struct rte_flow_item_nvgre), 3211 MLX5_ITEM_RANGE_NOT_ACCEPTED, error); 3212 if (ret < 0) 3213 return ret; 3214 return 0; 3215 } 3216 3217 /** 3218 * Validate eCPRI item. 3219 * 3220 * @param[in] item 3221 * Item specification. 3222 * @param[in] item_flags 3223 * Bit-fields that holds the items detected until now. 3224 * @param[in] last_item 3225 * Previous validated item in the pattern items. 3226 * @param[in] ether_type 3227 * Type in the ethernet layer header (including dot1q). 3228 * @param[in] acc_mask 3229 * Acceptable mask, if NULL default internal default mask 3230 * will be used to check whether item fields are supported. 3231 * @param[out] error 3232 * Pointer to error structure. 3233 * 3234 * @return 3235 * 0 on success, a negative errno value otherwise and rte_errno is set. 3236 */ 3237 int 3238 mlx5_flow_validate_item_ecpri(const struct rte_flow_item *item, 3239 uint64_t item_flags, 3240 uint64_t last_item, 3241 uint16_t ether_type, 3242 const struct rte_flow_item_ecpri *acc_mask, 3243 struct rte_flow_error *error) 3244 { 3245 const struct rte_flow_item_ecpri *mask = item->mask; 3246 const struct rte_flow_item_ecpri nic_mask = { 3247 .hdr = { 3248 .common = { 3249 .u32 = 3250 RTE_BE32(((const struct rte_ecpri_common_hdr) { 3251 .type = 0xFF, 3252 }).u32), 3253 }, 3254 .dummy[0] = 0xFFFFFFFF, 3255 }, 3256 }; 3257 const uint64_t outer_l2_vlan = (MLX5_FLOW_LAYER_OUTER_L2 | 3258 MLX5_FLOW_LAYER_OUTER_VLAN); 3259 struct rte_flow_item_ecpri mask_lo; 3260 3261 if (!(last_item & outer_l2_vlan) && 3262 last_item != MLX5_FLOW_LAYER_OUTER_L4_UDP) 3263 return rte_flow_error_set(error, EINVAL, 3264 RTE_FLOW_ERROR_TYPE_ITEM, item, 3265 "eCPRI can only follow L2/VLAN layer or UDP layer"); 3266 if ((last_item & outer_l2_vlan) && ether_type && 3267 ether_type != RTE_ETHER_TYPE_ECPRI) 3268 return rte_flow_error_set(error, EINVAL, 3269 RTE_FLOW_ERROR_TYPE_ITEM, item, 3270 "eCPRI cannot follow L2/VLAN layer which ether type is not 0xAEFE"); 3271 if (item_flags & MLX5_FLOW_LAYER_TUNNEL) 3272 return rte_flow_error_set(error, EINVAL, 3273 RTE_FLOW_ERROR_TYPE_ITEM, item, 3274 "eCPRI with tunnel is not supported right now"); 3275 if (item_flags & MLX5_FLOW_LAYER_OUTER_L3) 3276 return rte_flow_error_set(error, ENOTSUP, 3277 RTE_FLOW_ERROR_TYPE_ITEM, item, 3278 "multiple L3 layers not supported"); 3279 else if (item_flags & MLX5_FLOW_LAYER_OUTER_L4_TCP) 3280 return rte_flow_error_set(error, EINVAL, 3281 RTE_FLOW_ERROR_TYPE_ITEM, item, 3282 "eCPRI cannot coexist with a TCP layer"); 3283 /* In specification, eCPRI could be over UDP layer. */ 3284 else if (item_flags & MLX5_FLOW_LAYER_OUTER_L4_UDP) 3285 return rte_flow_error_set(error, EINVAL, 3286 RTE_FLOW_ERROR_TYPE_ITEM, item, 3287 "eCPRI over UDP layer is not yet supported right now"); 3288 /* Mask for type field in common header could be zero. */ 3289 if (!mask) 3290 mask = &rte_flow_item_ecpri_mask; 3291 mask_lo.hdr.common.u32 = rte_be_to_cpu_32(mask->hdr.common.u32); 3292 /* Input mask is in big-endian format. */ 3293 if (mask_lo.hdr.common.type != 0 && mask_lo.hdr.common.type != 0xff) 3294 return rte_flow_error_set(error, EINVAL, 3295 RTE_FLOW_ERROR_TYPE_ITEM_MASK, mask, 3296 "partial mask is not supported for protocol"); 3297 else if (mask_lo.hdr.common.type == 0 && mask->hdr.dummy[0] != 0) 3298 return rte_flow_error_set(error, EINVAL, 3299 RTE_FLOW_ERROR_TYPE_ITEM_MASK, mask, 3300 "message header mask must be after a type mask"); 3301 return mlx5_flow_item_acceptable(item, (const uint8_t *)mask, 3302 acc_mask ? (const uint8_t *)acc_mask 3303 : (const uint8_t *)&nic_mask, 3304 sizeof(struct rte_flow_item_ecpri), 3305 MLX5_ITEM_RANGE_NOT_ACCEPTED, error); 3306 } 3307 3308 static int 3309 flow_null_validate(struct rte_eth_dev *dev __rte_unused, 3310 const struct rte_flow_attr *attr __rte_unused, 3311 const struct rte_flow_item items[] __rte_unused, 3312 const struct rte_flow_action actions[] __rte_unused, 3313 bool external __rte_unused, 3314 int hairpin __rte_unused, 3315 struct rte_flow_error *error) 3316 { 3317 return rte_flow_error_set(error, ENOTSUP, 3318 RTE_FLOW_ERROR_TYPE_UNSPECIFIED, NULL, NULL); 3319 } 3320 3321 static struct mlx5_flow * 3322 flow_null_prepare(struct rte_eth_dev *dev __rte_unused, 3323 const struct rte_flow_attr *attr __rte_unused, 3324 const struct rte_flow_item items[] __rte_unused, 3325 const struct rte_flow_action actions[] __rte_unused, 3326 struct rte_flow_error *error) 3327 { 3328 rte_flow_error_set(error, ENOTSUP, 3329 RTE_FLOW_ERROR_TYPE_UNSPECIFIED, NULL, NULL); 3330 return NULL; 3331 } 3332 3333 static int 3334 flow_null_translate(struct rte_eth_dev *dev __rte_unused, 3335 struct mlx5_flow *dev_flow __rte_unused, 3336 const struct rte_flow_attr *attr __rte_unused, 3337 const struct rte_flow_item items[] __rte_unused, 3338 const struct rte_flow_action actions[] __rte_unused, 3339 struct rte_flow_error *error) 3340 { 3341 return rte_flow_error_set(error, ENOTSUP, 3342 RTE_FLOW_ERROR_TYPE_UNSPECIFIED, NULL, NULL); 3343 } 3344 3345 static int 3346 flow_null_apply(struct rte_eth_dev *dev __rte_unused, 3347 struct rte_flow *flow __rte_unused, 3348 struct rte_flow_error *error) 3349 { 3350 return rte_flow_error_set(error, ENOTSUP, 3351 RTE_FLOW_ERROR_TYPE_UNSPECIFIED, NULL, NULL); 3352 } 3353 3354 static void 3355 flow_null_remove(struct rte_eth_dev *dev __rte_unused, 3356 struct rte_flow *flow __rte_unused) 3357 { 3358 } 3359 3360 static void 3361 flow_null_destroy(struct rte_eth_dev *dev __rte_unused, 3362 struct rte_flow *flow __rte_unused) 3363 { 3364 } 3365 3366 static int 3367 flow_null_query(struct rte_eth_dev *dev __rte_unused, 3368 struct rte_flow *flow __rte_unused, 3369 const struct rte_flow_action *actions __rte_unused, 3370 void *data __rte_unused, 3371 struct rte_flow_error *error) 3372 { 3373 return rte_flow_error_set(error, ENOTSUP, 3374 RTE_FLOW_ERROR_TYPE_UNSPECIFIED, NULL, NULL); 3375 } 3376 3377 static int 3378 flow_null_sync_domain(struct rte_eth_dev *dev __rte_unused, 3379 uint32_t domains __rte_unused, 3380 uint32_t flags __rte_unused) 3381 { 3382 return 0; 3383 } 3384 3385 /* Void driver to protect from null pointer reference. */ 3386 const struct mlx5_flow_driver_ops mlx5_flow_null_drv_ops = { 3387 .validate = flow_null_validate, 3388 .prepare = flow_null_prepare, 3389 .translate = flow_null_translate, 3390 .apply = flow_null_apply, 3391 .remove = flow_null_remove, 3392 .destroy = flow_null_destroy, 3393 .query = flow_null_query, 3394 .sync_domain = flow_null_sync_domain, 3395 }; 3396 3397 /** 3398 * Select flow driver type according to flow attributes and device 3399 * configuration. 3400 * 3401 * @param[in] dev 3402 * Pointer to the dev structure. 3403 * @param[in] attr 3404 * Pointer to the flow attributes. 3405 * 3406 * @return 3407 * flow driver type, MLX5_FLOW_TYPE_MAX otherwise. 3408 */ 3409 static enum mlx5_flow_drv_type 3410 flow_get_drv_type(struct rte_eth_dev *dev, const struct rte_flow_attr *attr) 3411 { 3412 struct mlx5_priv *priv = dev->data->dev_private; 3413 /* The OS can determine first a specific flow type (DV, VERBS) */ 3414 enum mlx5_flow_drv_type type = mlx5_flow_os_get_type(); 3415 3416 if (type != MLX5_FLOW_TYPE_MAX) 3417 return type; 3418 /* If no OS specific type - continue with DV/VERBS selection */ 3419 if (attr->transfer && priv->config.dv_esw_en) 3420 type = MLX5_FLOW_TYPE_DV; 3421 if (!attr->transfer) 3422 type = priv->config.dv_flow_en ? MLX5_FLOW_TYPE_DV : 3423 MLX5_FLOW_TYPE_VERBS; 3424 return type; 3425 } 3426 3427 #define flow_get_drv_ops(type) flow_drv_ops[type] 3428 3429 /** 3430 * Flow driver validation API. This abstracts calling driver specific functions. 3431 * The type of flow driver is determined according to flow attributes. 3432 * 3433 * @param[in] dev 3434 * Pointer to the dev structure. 3435 * @param[in] attr 3436 * Pointer to the flow attributes. 3437 * @param[in] items 3438 * Pointer to the list of items. 3439 * @param[in] actions 3440 * Pointer to the list of actions. 3441 * @param[in] external 3442 * This flow rule is created by request external to PMD. 3443 * @param[in] hairpin 3444 * Number of hairpin TX actions, 0 means classic flow. 3445 * @param[out] error 3446 * Pointer to the error structure. 3447 * 3448 * @return 3449 * 0 on success, a negative errno value otherwise and rte_errno is set. 3450 */ 3451 static inline int 3452 flow_drv_validate(struct rte_eth_dev *dev, 3453 const struct rte_flow_attr *attr, 3454 const struct rte_flow_item items[], 3455 const struct rte_flow_action actions[], 3456 bool external, int hairpin, struct rte_flow_error *error) 3457 { 3458 const struct mlx5_flow_driver_ops *fops; 3459 enum mlx5_flow_drv_type type = flow_get_drv_type(dev, attr); 3460 3461 fops = flow_get_drv_ops(type); 3462 return fops->validate(dev, attr, items, actions, external, 3463 hairpin, error); 3464 } 3465 3466 /** 3467 * Flow driver preparation API. This abstracts calling driver specific 3468 * functions. Parent flow (rte_flow) should have driver type (drv_type). It 3469 * calculates the size of memory required for device flow, allocates the memory, 3470 * initializes the device flow and returns the pointer. 3471 * 3472 * @note 3473 * This function initializes device flow structure such as dv or verbs in 3474 * struct mlx5_flow. However, it is caller's responsibility to initialize the 3475 * rest. For example, adding returning device flow to flow->dev_flow list and 3476 * setting backward reference to the flow should be done out of this function. 3477 * layers field is not filled either. 3478 * 3479 * @param[in] dev 3480 * Pointer to the dev structure. 3481 * @param[in] attr 3482 * Pointer to the flow attributes. 3483 * @param[in] items 3484 * Pointer to the list of items. 3485 * @param[in] actions 3486 * Pointer to the list of actions. 3487 * @param[in] flow_idx 3488 * This memory pool index to the flow. 3489 * @param[out] error 3490 * Pointer to the error structure. 3491 * 3492 * @return 3493 * Pointer to device flow on success, otherwise NULL and rte_errno is set. 3494 */ 3495 static inline struct mlx5_flow * 3496 flow_drv_prepare(struct rte_eth_dev *dev, 3497 const struct rte_flow *flow, 3498 const struct rte_flow_attr *attr, 3499 const struct rte_flow_item items[], 3500 const struct rte_flow_action actions[], 3501 uint32_t flow_idx, 3502 struct rte_flow_error *error) 3503 { 3504 const struct mlx5_flow_driver_ops *fops; 3505 enum mlx5_flow_drv_type type = flow->drv_type; 3506 struct mlx5_flow *mlx5_flow = NULL; 3507 3508 MLX5_ASSERT(type > MLX5_FLOW_TYPE_MIN && type < MLX5_FLOW_TYPE_MAX); 3509 fops = flow_get_drv_ops(type); 3510 mlx5_flow = fops->prepare(dev, attr, items, actions, error); 3511 if (mlx5_flow) 3512 mlx5_flow->flow_idx = flow_idx; 3513 return mlx5_flow; 3514 } 3515 3516 /** 3517 * Flow driver translation API. This abstracts calling driver specific 3518 * functions. Parent flow (rte_flow) should have driver type (drv_type). It 3519 * translates a generic flow into a driver flow. flow_drv_prepare() must 3520 * precede. 3521 * 3522 * @note 3523 * dev_flow->layers could be filled as a result of parsing during translation 3524 * if needed by flow_drv_apply(). dev_flow->flow->actions can also be filled 3525 * if necessary. As a flow can have multiple dev_flows by RSS flow expansion, 3526 * flow->actions could be overwritten even though all the expanded dev_flows 3527 * have the same actions. 3528 * 3529 * @param[in] dev 3530 * Pointer to the rte dev structure. 3531 * @param[in, out] dev_flow 3532 * Pointer to the mlx5 flow. 3533 * @param[in] attr 3534 * Pointer to the flow attributes. 3535 * @param[in] items 3536 * Pointer to the list of items. 3537 * @param[in] actions 3538 * Pointer to the list of actions. 3539 * @param[out] error 3540 * Pointer to the error structure. 3541 * 3542 * @return 3543 * 0 on success, a negative errno value otherwise and rte_errno is set. 3544 */ 3545 static inline int 3546 flow_drv_translate(struct rte_eth_dev *dev, struct mlx5_flow *dev_flow, 3547 const struct rte_flow_attr *attr, 3548 const struct rte_flow_item items[], 3549 const struct rte_flow_action actions[], 3550 struct rte_flow_error *error) 3551 { 3552 const struct mlx5_flow_driver_ops *fops; 3553 enum mlx5_flow_drv_type type = dev_flow->flow->drv_type; 3554 3555 MLX5_ASSERT(type > MLX5_FLOW_TYPE_MIN && type < MLX5_FLOW_TYPE_MAX); 3556 fops = flow_get_drv_ops(type); 3557 return fops->translate(dev, dev_flow, attr, items, actions, error); 3558 } 3559 3560 /** 3561 * Flow driver apply API. This abstracts calling driver specific functions. 3562 * Parent flow (rte_flow) should have driver type (drv_type). It applies 3563 * translated driver flows on to device. flow_drv_translate() must precede. 3564 * 3565 * @param[in] dev 3566 * Pointer to Ethernet device structure. 3567 * @param[in, out] flow 3568 * Pointer to flow structure. 3569 * @param[out] error 3570 * Pointer to error structure. 3571 * 3572 * @return 3573 * 0 on success, a negative errno value otherwise and rte_errno is set. 3574 */ 3575 static inline int 3576 flow_drv_apply(struct rte_eth_dev *dev, struct rte_flow *flow, 3577 struct rte_flow_error *error) 3578 { 3579 const struct mlx5_flow_driver_ops *fops; 3580 enum mlx5_flow_drv_type type = flow->drv_type; 3581 3582 MLX5_ASSERT(type > MLX5_FLOW_TYPE_MIN && type < MLX5_FLOW_TYPE_MAX); 3583 fops = flow_get_drv_ops(type); 3584 return fops->apply(dev, flow, error); 3585 } 3586 3587 /** 3588 * Flow driver destroy API. This abstracts calling driver specific functions. 3589 * Parent flow (rte_flow) should have driver type (drv_type). It removes a flow 3590 * on device and releases resources of the flow. 3591 * 3592 * @param[in] dev 3593 * Pointer to Ethernet device. 3594 * @param[in, out] flow 3595 * Pointer to flow structure. 3596 */ 3597 static inline void 3598 flow_drv_destroy(struct rte_eth_dev *dev, struct rte_flow *flow) 3599 { 3600 const struct mlx5_flow_driver_ops *fops; 3601 enum mlx5_flow_drv_type type = flow->drv_type; 3602 3603 MLX5_ASSERT(type > MLX5_FLOW_TYPE_MIN && type < MLX5_FLOW_TYPE_MAX); 3604 fops = flow_get_drv_ops(type); 3605 fops->destroy(dev, flow); 3606 } 3607 3608 /** 3609 * Flow driver find RSS policy tbl API. This abstracts calling driver 3610 * specific functions. Parent flow (rte_flow) should have driver 3611 * type (drv_type). It will find the RSS policy table that has the rss_desc. 3612 * 3613 * @param[in] dev 3614 * Pointer to Ethernet device. 3615 * @param[in, out] flow 3616 * Pointer to flow structure. 3617 * @param[in] policy 3618 * Pointer to meter policy table. 3619 * @param[in] rss_desc 3620 * Pointer to rss_desc 3621 */ 3622 static struct mlx5_flow_meter_sub_policy * 3623 flow_drv_meter_sub_policy_rss_prepare(struct rte_eth_dev *dev, 3624 struct rte_flow *flow, 3625 struct mlx5_flow_meter_policy *policy, 3626 struct mlx5_flow_rss_desc *rss_desc[MLX5_MTR_RTE_COLORS]) 3627 { 3628 const struct mlx5_flow_driver_ops *fops; 3629 enum mlx5_flow_drv_type type = flow->drv_type; 3630 3631 MLX5_ASSERT(type > MLX5_FLOW_TYPE_MIN && type < MLX5_FLOW_TYPE_MAX); 3632 fops = flow_get_drv_ops(type); 3633 return fops->meter_sub_policy_rss_prepare(dev, policy, rss_desc); 3634 } 3635 3636 /** 3637 * Flow driver color tag rule API. This abstracts calling driver 3638 * specific functions. Parent flow (rte_flow) should have driver 3639 * type (drv_type). It will create the color tag rules in hierarchy meter. 3640 * 3641 * @param[in] dev 3642 * Pointer to Ethernet device. 3643 * @param[in, out] flow 3644 * Pointer to flow structure. 3645 * @param[in] fm 3646 * Pointer to flow meter structure. 3647 * @param[in] src_port 3648 * The src port this extra rule should use. 3649 * @param[in] item 3650 * The src port id match item. 3651 * @param[out] error 3652 * Pointer to error structure. 3653 */ 3654 static int 3655 flow_drv_mtr_hierarchy_rule_create(struct rte_eth_dev *dev, 3656 struct rte_flow *flow, 3657 struct mlx5_flow_meter_info *fm, 3658 int32_t src_port, 3659 const struct rte_flow_item *item, 3660 struct rte_flow_error *error) 3661 { 3662 const struct mlx5_flow_driver_ops *fops; 3663 enum mlx5_flow_drv_type type = flow->drv_type; 3664 3665 MLX5_ASSERT(type > MLX5_FLOW_TYPE_MIN && type < MLX5_FLOW_TYPE_MAX); 3666 fops = flow_get_drv_ops(type); 3667 return fops->meter_hierarchy_rule_create(dev, fm, 3668 src_port, item, error); 3669 } 3670 3671 /** 3672 * Get RSS action from the action list. 3673 * 3674 * @param[in] dev 3675 * Pointer to Ethernet device. 3676 * @param[in] actions 3677 * Pointer to the list of actions. 3678 * @param[in] flow 3679 * Parent flow structure pointer. 3680 * 3681 * @return 3682 * Pointer to the RSS action if exist, else return NULL. 3683 */ 3684 static const struct rte_flow_action_rss* 3685 flow_get_rss_action(struct rte_eth_dev *dev, 3686 const struct rte_flow_action actions[]) 3687 { 3688 struct mlx5_priv *priv = dev->data->dev_private; 3689 const struct rte_flow_action_rss *rss = NULL; 3690 struct mlx5_meter_policy_action_container *acg; 3691 struct mlx5_meter_policy_action_container *acy; 3692 3693 for (; actions->type != RTE_FLOW_ACTION_TYPE_END; actions++) { 3694 switch (actions->type) { 3695 case RTE_FLOW_ACTION_TYPE_RSS: 3696 rss = actions->conf; 3697 break; 3698 case RTE_FLOW_ACTION_TYPE_SAMPLE: 3699 { 3700 const struct rte_flow_action_sample *sample = 3701 actions->conf; 3702 const struct rte_flow_action *act = sample->actions; 3703 for (; act->type != RTE_FLOW_ACTION_TYPE_END; act++) 3704 if (act->type == RTE_FLOW_ACTION_TYPE_RSS) 3705 rss = act->conf; 3706 break; 3707 } 3708 case RTE_FLOW_ACTION_TYPE_METER: 3709 { 3710 uint32_t mtr_idx; 3711 struct mlx5_flow_meter_info *fm; 3712 struct mlx5_flow_meter_policy *policy; 3713 const struct rte_flow_action_meter *mtr = actions->conf; 3714 3715 fm = mlx5_flow_meter_find(priv, mtr->mtr_id, &mtr_idx); 3716 if (fm && !fm->def_policy) { 3717 policy = mlx5_flow_meter_policy_find(dev, 3718 fm->policy_id, NULL); 3719 MLX5_ASSERT(policy); 3720 if (policy->is_hierarchy) { 3721 policy = 3722 mlx5_flow_meter_hierarchy_get_final_policy(dev, 3723 policy); 3724 if (!policy) 3725 return NULL; 3726 } 3727 if (policy->is_rss) { 3728 acg = 3729 &policy->act_cnt[RTE_COLOR_GREEN]; 3730 acy = 3731 &policy->act_cnt[RTE_COLOR_YELLOW]; 3732 if (acg->fate_action == 3733 MLX5_FLOW_FATE_SHARED_RSS) 3734 rss = acg->rss->conf; 3735 else if (acy->fate_action == 3736 MLX5_FLOW_FATE_SHARED_RSS) 3737 rss = acy->rss->conf; 3738 } 3739 } 3740 break; 3741 } 3742 default: 3743 break; 3744 } 3745 } 3746 return rss; 3747 } 3748 3749 /** 3750 * Get ASO age action by index. 3751 * 3752 * @param[in] dev 3753 * Pointer to the Ethernet device structure. 3754 * @param[in] age_idx 3755 * Index to the ASO age action. 3756 * 3757 * @return 3758 * The specified ASO age action. 3759 */ 3760 struct mlx5_aso_age_action* 3761 flow_aso_age_get_by_idx(struct rte_eth_dev *dev, uint32_t age_idx) 3762 { 3763 uint16_t pool_idx = age_idx & UINT16_MAX; 3764 uint16_t offset = (age_idx >> 16) & UINT16_MAX; 3765 struct mlx5_priv *priv = dev->data->dev_private; 3766 struct mlx5_aso_age_mng *mng = priv->sh->aso_age_mng; 3767 struct mlx5_aso_age_pool *pool; 3768 3769 rte_rwlock_read_lock(&mng->resize_rwl); 3770 pool = mng->pools[pool_idx]; 3771 rte_rwlock_read_unlock(&mng->resize_rwl); 3772 return &pool->actions[offset - 1]; 3773 } 3774 3775 /* maps indirect action to translated direct in some actions array */ 3776 struct mlx5_translated_action_handle { 3777 struct rte_flow_action_handle *action; /**< Indirect action handle. */ 3778 int index; /**< Index in related array of rte_flow_action. */ 3779 }; 3780 3781 /** 3782 * Translates actions of type RTE_FLOW_ACTION_TYPE_INDIRECT to related 3783 * direct action if translation possible. 3784 * This functionality used to run same execution path for both direct and 3785 * indirect actions on flow create. All necessary preparations for indirect 3786 * action handling should be performed on *handle* actions list returned 3787 * from this call. 3788 * 3789 * @param[in] dev 3790 * Pointer to Ethernet device. 3791 * @param[in] actions 3792 * List of actions to translate. 3793 * @param[out] handle 3794 * List to store translated indirect action object handles. 3795 * @param[in, out] indir_n 3796 * Size of *handle* array. On return should be updated with number of 3797 * indirect actions retrieved from the *actions* list. 3798 * @param[out] translated_actions 3799 * List of actions where all indirect actions were translated to direct 3800 * if possible. NULL if no translation took place. 3801 * @param[out] error 3802 * Pointer to the error structure. 3803 * 3804 * @return 3805 * 0 on success, a negative errno value otherwise and rte_errno is set. 3806 */ 3807 static int 3808 flow_action_handles_translate(struct rte_eth_dev *dev, 3809 const struct rte_flow_action actions[], 3810 struct mlx5_translated_action_handle *handle, 3811 int *indir_n, 3812 struct rte_flow_action **translated_actions, 3813 struct rte_flow_error *error) 3814 { 3815 struct mlx5_priv *priv = dev->data->dev_private; 3816 struct rte_flow_action *translated = NULL; 3817 size_t actions_size; 3818 int n; 3819 int copied_n = 0; 3820 struct mlx5_translated_action_handle *handle_end = NULL; 3821 3822 for (n = 0; actions[n].type != RTE_FLOW_ACTION_TYPE_END; n++) { 3823 if (actions[n].type != RTE_FLOW_ACTION_TYPE_INDIRECT) 3824 continue; 3825 if (copied_n == *indir_n) { 3826 return rte_flow_error_set 3827 (error, EINVAL, RTE_FLOW_ERROR_TYPE_ACTION_NUM, 3828 NULL, "too many shared actions"); 3829 } 3830 rte_memcpy(&handle[copied_n].action, &actions[n].conf, 3831 sizeof(actions[n].conf)); 3832 handle[copied_n].index = n; 3833 copied_n++; 3834 } 3835 n++; 3836 *indir_n = copied_n; 3837 if (!copied_n) 3838 return 0; 3839 actions_size = sizeof(struct rte_flow_action) * n; 3840 translated = mlx5_malloc(MLX5_MEM_ZERO, actions_size, 0, SOCKET_ID_ANY); 3841 if (!translated) { 3842 rte_errno = ENOMEM; 3843 return -ENOMEM; 3844 } 3845 memcpy(translated, actions, actions_size); 3846 for (handle_end = handle + copied_n; handle < handle_end; handle++) { 3847 struct mlx5_shared_action_rss *shared_rss; 3848 uint32_t act_idx = (uint32_t)(uintptr_t)handle->action; 3849 uint32_t type = act_idx >> MLX5_INDIRECT_ACTION_TYPE_OFFSET; 3850 uint32_t idx = act_idx & 3851 ((1u << MLX5_INDIRECT_ACTION_TYPE_OFFSET) - 1); 3852 3853 switch (type) { 3854 case MLX5_INDIRECT_ACTION_TYPE_RSS: 3855 shared_rss = mlx5_ipool_get 3856 (priv->sh->ipool[MLX5_IPOOL_RSS_SHARED_ACTIONS], idx); 3857 translated[handle->index].type = 3858 RTE_FLOW_ACTION_TYPE_RSS; 3859 translated[handle->index].conf = 3860 &shared_rss->origin; 3861 break; 3862 case MLX5_INDIRECT_ACTION_TYPE_COUNT: 3863 translated[handle->index].type = 3864 (enum rte_flow_action_type) 3865 MLX5_RTE_FLOW_ACTION_TYPE_COUNT; 3866 translated[handle->index].conf = (void *)(uintptr_t)idx; 3867 break; 3868 case MLX5_INDIRECT_ACTION_TYPE_AGE: 3869 if (priv->sh->flow_hit_aso_en) { 3870 translated[handle->index].type = 3871 (enum rte_flow_action_type) 3872 MLX5_RTE_FLOW_ACTION_TYPE_AGE; 3873 translated[handle->index].conf = 3874 (void *)(uintptr_t)idx; 3875 break; 3876 } 3877 /* Fall-through */ 3878 case MLX5_INDIRECT_ACTION_TYPE_CT: 3879 if (priv->sh->ct_aso_en) { 3880 translated[handle->index].type = 3881 RTE_FLOW_ACTION_TYPE_CONNTRACK; 3882 translated[handle->index].conf = 3883 (void *)(uintptr_t)idx; 3884 break; 3885 } 3886 /* Fall-through */ 3887 default: 3888 mlx5_free(translated); 3889 return rte_flow_error_set 3890 (error, EINVAL, RTE_FLOW_ERROR_TYPE_ACTION, 3891 NULL, "invalid indirect action type"); 3892 } 3893 } 3894 *translated_actions = translated; 3895 return 0; 3896 } 3897 3898 /** 3899 * Get Shared RSS action from the action list. 3900 * 3901 * @param[in] dev 3902 * Pointer to Ethernet device. 3903 * @param[in] shared 3904 * Pointer to the list of actions. 3905 * @param[in] shared_n 3906 * Actions list length. 3907 * 3908 * @return 3909 * The MLX5 RSS action ID if exists, otherwise return 0. 3910 */ 3911 static uint32_t 3912 flow_get_shared_rss_action(struct rte_eth_dev *dev, 3913 struct mlx5_translated_action_handle *handle, 3914 int shared_n) 3915 { 3916 struct mlx5_translated_action_handle *handle_end; 3917 struct mlx5_priv *priv = dev->data->dev_private; 3918 struct mlx5_shared_action_rss *shared_rss; 3919 3920 3921 for (handle_end = handle + shared_n; handle < handle_end; handle++) { 3922 uint32_t act_idx = (uint32_t)(uintptr_t)handle->action; 3923 uint32_t type = act_idx >> MLX5_INDIRECT_ACTION_TYPE_OFFSET; 3924 uint32_t idx = act_idx & 3925 ((1u << MLX5_INDIRECT_ACTION_TYPE_OFFSET) - 1); 3926 switch (type) { 3927 case MLX5_INDIRECT_ACTION_TYPE_RSS: 3928 shared_rss = mlx5_ipool_get 3929 (priv->sh->ipool[MLX5_IPOOL_RSS_SHARED_ACTIONS], 3930 idx); 3931 __atomic_add_fetch(&shared_rss->refcnt, 1, 3932 __ATOMIC_RELAXED); 3933 return idx; 3934 default: 3935 break; 3936 } 3937 } 3938 return 0; 3939 } 3940 3941 static unsigned int 3942 find_graph_root(uint32_t rss_level) 3943 { 3944 return rss_level < 2 ? MLX5_EXPANSION_ROOT : 3945 MLX5_EXPANSION_ROOT_OUTER; 3946 } 3947 3948 /** 3949 * Get layer flags from the prefix flow. 3950 * 3951 * Some flows may be split to several subflows, the prefix subflow gets the 3952 * match items and the suffix sub flow gets the actions. 3953 * Some actions need the user defined match item flags to get the detail for 3954 * the action. 3955 * This function helps the suffix flow to get the item layer flags from prefix 3956 * subflow. 3957 * 3958 * @param[in] dev_flow 3959 * Pointer the created preifx subflow. 3960 * 3961 * @return 3962 * The layers get from prefix subflow. 3963 */ 3964 static inline uint64_t 3965 flow_get_prefix_layer_flags(struct mlx5_flow *dev_flow) 3966 { 3967 uint64_t layers = 0; 3968 3969 /* 3970 * Layers bits could be localization, but usually the compiler will 3971 * help to do the optimization work for source code. 3972 * If no decap actions, use the layers directly. 3973 */ 3974 if (!(dev_flow->act_flags & MLX5_FLOW_ACTION_DECAP)) 3975 return dev_flow->handle->layers; 3976 /* Convert L3 layers with decap action. */ 3977 if (dev_flow->handle->layers & MLX5_FLOW_LAYER_INNER_L3_IPV4) 3978 layers |= MLX5_FLOW_LAYER_OUTER_L3_IPV4; 3979 else if (dev_flow->handle->layers & MLX5_FLOW_LAYER_INNER_L3_IPV6) 3980 layers |= MLX5_FLOW_LAYER_OUTER_L3_IPV6; 3981 /* Convert L4 layers with decap action. */ 3982 if (dev_flow->handle->layers & MLX5_FLOW_LAYER_INNER_L4_TCP) 3983 layers |= MLX5_FLOW_LAYER_OUTER_L4_TCP; 3984 else if (dev_flow->handle->layers & MLX5_FLOW_LAYER_INNER_L4_UDP) 3985 layers |= MLX5_FLOW_LAYER_OUTER_L4_UDP; 3986 return layers; 3987 } 3988 3989 /** 3990 * Get metadata split action information. 3991 * 3992 * @param[in] actions 3993 * Pointer to the list of actions. 3994 * @param[out] qrss 3995 * Pointer to the return pointer. 3996 * @param[out] qrss_type 3997 * Pointer to the action type to return. RTE_FLOW_ACTION_TYPE_END is returned 3998 * if no QUEUE/RSS is found. 3999 * @param[out] encap_idx 4000 * Pointer to the index of the encap action if exists, otherwise the last 4001 * action index. 4002 * 4003 * @return 4004 * Total number of actions. 4005 */ 4006 static int 4007 flow_parse_metadata_split_actions_info(const struct rte_flow_action actions[], 4008 const struct rte_flow_action **qrss, 4009 int *encap_idx) 4010 { 4011 const struct rte_flow_action_raw_encap *raw_encap; 4012 int actions_n = 0; 4013 int raw_decap_idx = -1; 4014 4015 *encap_idx = -1; 4016 for (; actions->type != RTE_FLOW_ACTION_TYPE_END; actions++) { 4017 switch (actions->type) { 4018 case RTE_FLOW_ACTION_TYPE_VXLAN_ENCAP: 4019 case RTE_FLOW_ACTION_TYPE_NVGRE_ENCAP: 4020 *encap_idx = actions_n; 4021 break; 4022 case RTE_FLOW_ACTION_TYPE_RAW_DECAP: 4023 raw_decap_idx = actions_n; 4024 break; 4025 case RTE_FLOW_ACTION_TYPE_RAW_ENCAP: 4026 raw_encap = actions->conf; 4027 if (raw_encap->size > MLX5_ENCAPSULATION_DECISION_SIZE) 4028 *encap_idx = raw_decap_idx != -1 ? 4029 raw_decap_idx : actions_n; 4030 break; 4031 case RTE_FLOW_ACTION_TYPE_QUEUE: 4032 case RTE_FLOW_ACTION_TYPE_RSS: 4033 *qrss = actions; 4034 break; 4035 default: 4036 break; 4037 } 4038 actions_n++; 4039 } 4040 if (*encap_idx == -1) 4041 *encap_idx = actions_n; 4042 /* Count RTE_FLOW_ACTION_TYPE_END. */ 4043 return actions_n + 1; 4044 } 4045 4046 /** 4047 * Check if the action will change packet. 4048 * 4049 * @param dev 4050 * Pointer to Ethernet device. 4051 * @param[in] type 4052 * action type. 4053 * 4054 * @return 4055 * true if action will change packet, false otherwise. 4056 */ 4057 static bool flow_check_modify_action_type(struct rte_eth_dev *dev, 4058 enum rte_flow_action_type type) 4059 { 4060 struct mlx5_priv *priv = dev->data->dev_private; 4061 4062 switch (type) { 4063 case RTE_FLOW_ACTION_TYPE_SET_MAC_SRC: 4064 case RTE_FLOW_ACTION_TYPE_SET_MAC_DST: 4065 case RTE_FLOW_ACTION_TYPE_SET_IPV4_SRC: 4066 case RTE_FLOW_ACTION_TYPE_SET_IPV4_DST: 4067 case RTE_FLOW_ACTION_TYPE_SET_IPV6_SRC: 4068 case RTE_FLOW_ACTION_TYPE_SET_IPV6_DST: 4069 case RTE_FLOW_ACTION_TYPE_SET_TP_SRC: 4070 case RTE_FLOW_ACTION_TYPE_SET_TP_DST: 4071 case RTE_FLOW_ACTION_TYPE_DEC_TTL: 4072 case RTE_FLOW_ACTION_TYPE_SET_TTL: 4073 case RTE_FLOW_ACTION_TYPE_INC_TCP_SEQ: 4074 case RTE_FLOW_ACTION_TYPE_DEC_TCP_SEQ: 4075 case RTE_FLOW_ACTION_TYPE_INC_TCP_ACK: 4076 case RTE_FLOW_ACTION_TYPE_DEC_TCP_ACK: 4077 case RTE_FLOW_ACTION_TYPE_SET_IPV4_DSCP: 4078 case RTE_FLOW_ACTION_TYPE_SET_IPV6_DSCP: 4079 case RTE_FLOW_ACTION_TYPE_SET_META: 4080 case RTE_FLOW_ACTION_TYPE_SET_TAG: 4081 case RTE_FLOW_ACTION_TYPE_OF_POP_VLAN: 4082 case RTE_FLOW_ACTION_TYPE_OF_PUSH_VLAN: 4083 case RTE_FLOW_ACTION_TYPE_OF_SET_VLAN_VID: 4084 case RTE_FLOW_ACTION_TYPE_OF_SET_VLAN_PCP: 4085 case RTE_FLOW_ACTION_TYPE_VXLAN_ENCAP: 4086 case RTE_FLOW_ACTION_TYPE_VXLAN_DECAP: 4087 case RTE_FLOW_ACTION_TYPE_NVGRE_ENCAP: 4088 case RTE_FLOW_ACTION_TYPE_NVGRE_DECAP: 4089 case RTE_FLOW_ACTION_TYPE_RAW_ENCAP: 4090 case RTE_FLOW_ACTION_TYPE_RAW_DECAP: 4091 case RTE_FLOW_ACTION_TYPE_MODIFY_FIELD: 4092 return true; 4093 case RTE_FLOW_ACTION_TYPE_FLAG: 4094 case RTE_FLOW_ACTION_TYPE_MARK: 4095 if (priv->config.dv_xmeta_en != MLX5_XMETA_MODE_LEGACY) 4096 return true; 4097 else 4098 return false; 4099 default: 4100 return false; 4101 } 4102 } 4103 4104 /** 4105 * Check meter action from the action list. 4106 * 4107 * @param dev 4108 * Pointer to Ethernet device. 4109 * @param[in] actions 4110 * Pointer to the list of actions. 4111 * @param[out] has_mtr 4112 * Pointer to the meter exist flag. 4113 * @param[out] has_modify 4114 * Pointer to the flag showing there's packet change action. 4115 * @param[out] meter_id 4116 * Pointer to the meter id. 4117 * 4118 * @return 4119 * Total number of actions. 4120 */ 4121 static int 4122 flow_check_meter_action(struct rte_eth_dev *dev, 4123 const struct rte_flow_action actions[], 4124 bool *has_mtr, bool *has_modify, uint32_t *meter_id) 4125 { 4126 const struct rte_flow_action_meter *mtr = NULL; 4127 int actions_n = 0; 4128 4129 MLX5_ASSERT(has_mtr); 4130 *has_mtr = false; 4131 for (; actions->type != RTE_FLOW_ACTION_TYPE_END; actions++) { 4132 switch (actions->type) { 4133 case RTE_FLOW_ACTION_TYPE_METER: 4134 mtr = actions->conf; 4135 *meter_id = mtr->mtr_id; 4136 *has_mtr = true; 4137 break; 4138 default: 4139 break; 4140 } 4141 if (!*has_mtr) 4142 *has_modify |= flow_check_modify_action_type(dev, 4143 actions->type); 4144 actions_n++; 4145 } 4146 /* Count RTE_FLOW_ACTION_TYPE_END. */ 4147 return actions_n + 1; 4148 } 4149 4150 /** 4151 * Check if the flow should be split due to hairpin. 4152 * The reason for the split is that in current HW we can't 4153 * support encap and push-vlan on Rx, so if a flow contains 4154 * these actions we move it to Tx. 4155 * 4156 * @param dev 4157 * Pointer to Ethernet device. 4158 * @param[in] attr 4159 * Flow rule attributes. 4160 * @param[in] actions 4161 * Associated actions (list terminated by the END action). 4162 * 4163 * @return 4164 * > 0 the number of actions and the flow should be split, 4165 * 0 when no split required. 4166 */ 4167 static int 4168 flow_check_hairpin_split(struct rte_eth_dev *dev, 4169 const struct rte_flow_attr *attr, 4170 const struct rte_flow_action actions[]) 4171 { 4172 int queue_action = 0; 4173 int action_n = 0; 4174 int split = 0; 4175 const struct rte_flow_action_queue *queue; 4176 const struct rte_flow_action_rss *rss; 4177 const struct rte_flow_action_raw_encap *raw_encap; 4178 const struct rte_eth_hairpin_conf *conf; 4179 4180 if (!attr->ingress) 4181 return 0; 4182 for (; actions->type != RTE_FLOW_ACTION_TYPE_END; actions++) { 4183 switch (actions->type) { 4184 case RTE_FLOW_ACTION_TYPE_QUEUE: 4185 queue = actions->conf; 4186 if (queue == NULL) 4187 return 0; 4188 conf = mlx5_rxq_get_hairpin_conf(dev, queue->index); 4189 if (conf == NULL || conf->tx_explicit != 0) 4190 return 0; 4191 queue_action = 1; 4192 action_n++; 4193 break; 4194 case RTE_FLOW_ACTION_TYPE_RSS: 4195 rss = actions->conf; 4196 if (rss == NULL || rss->queue_num == 0) 4197 return 0; 4198 conf = mlx5_rxq_get_hairpin_conf(dev, rss->queue[0]); 4199 if (conf == NULL || conf->tx_explicit != 0) 4200 return 0; 4201 queue_action = 1; 4202 action_n++; 4203 break; 4204 case RTE_FLOW_ACTION_TYPE_VXLAN_ENCAP: 4205 case RTE_FLOW_ACTION_TYPE_NVGRE_ENCAP: 4206 case RTE_FLOW_ACTION_TYPE_OF_PUSH_VLAN: 4207 case RTE_FLOW_ACTION_TYPE_OF_SET_VLAN_VID: 4208 case RTE_FLOW_ACTION_TYPE_OF_SET_VLAN_PCP: 4209 split++; 4210 action_n++; 4211 break; 4212 case RTE_FLOW_ACTION_TYPE_RAW_ENCAP: 4213 raw_encap = actions->conf; 4214 if (raw_encap->size > MLX5_ENCAPSULATION_DECISION_SIZE) 4215 split++; 4216 action_n++; 4217 break; 4218 default: 4219 action_n++; 4220 break; 4221 } 4222 } 4223 if (split && queue_action) 4224 return action_n; 4225 return 0; 4226 } 4227 4228 /* Declare flow create/destroy prototype in advance. */ 4229 static uint32_t 4230 flow_list_create(struct rte_eth_dev *dev, enum mlx5_flow_type type, 4231 const struct rte_flow_attr *attr, 4232 const struct rte_flow_item items[], 4233 const struct rte_flow_action actions[], 4234 bool external, struct rte_flow_error *error); 4235 4236 static void 4237 flow_list_destroy(struct rte_eth_dev *dev, enum mlx5_flow_type type, 4238 uint32_t flow_idx); 4239 4240 int 4241 flow_dv_mreg_match_cb(void *tool_ctx __rte_unused, 4242 struct mlx5_list_entry *entry, void *cb_ctx) 4243 { 4244 struct mlx5_flow_cb_ctx *ctx = cb_ctx; 4245 struct mlx5_flow_mreg_copy_resource *mcp_res = 4246 container_of(entry, typeof(*mcp_res), hlist_ent); 4247 4248 return mcp_res->mark_id != *(uint32_t *)(ctx->data); 4249 } 4250 4251 struct mlx5_list_entry * 4252 flow_dv_mreg_create_cb(void *tool_ctx, void *cb_ctx) 4253 { 4254 struct rte_eth_dev *dev = tool_ctx; 4255 struct mlx5_priv *priv = dev->data->dev_private; 4256 struct mlx5_flow_cb_ctx *ctx = cb_ctx; 4257 struct mlx5_flow_mreg_copy_resource *mcp_res; 4258 struct rte_flow_error *error = ctx->error; 4259 uint32_t idx = 0; 4260 int ret; 4261 uint32_t mark_id = *(uint32_t *)(ctx->data); 4262 struct rte_flow_attr attr = { 4263 .group = MLX5_FLOW_MREG_CP_TABLE_GROUP, 4264 .ingress = 1, 4265 }; 4266 struct mlx5_rte_flow_item_tag tag_spec = { 4267 .data = mark_id, 4268 }; 4269 struct rte_flow_item items[] = { 4270 [1] = { .type = RTE_FLOW_ITEM_TYPE_END, }, 4271 }; 4272 struct rte_flow_action_mark ftag = { 4273 .id = mark_id, 4274 }; 4275 struct mlx5_flow_action_copy_mreg cp_mreg = { 4276 .dst = REG_B, 4277 .src = REG_NON, 4278 }; 4279 struct rte_flow_action_jump jump = { 4280 .group = MLX5_FLOW_MREG_ACT_TABLE_GROUP, 4281 }; 4282 struct rte_flow_action actions[] = { 4283 [3] = { .type = RTE_FLOW_ACTION_TYPE_END, }, 4284 }; 4285 4286 /* Fill the register fileds in the flow. */ 4287 ret = mlx5_flow_get_reg_id(dev, MLX5_FLOW_MARK, 0, error); 4288 if (ret < 0) 4289 return NULL; 4290 tag_spec.id = ret; 4291 ret = mlx5_flow_get_reg_id(dev, MLX5_METADATA_RX, 0, error); 4292 if (ret < 0) 4293 return NULL; 4294 cp_mreg.src = ret; 4295 /* Provide the full width of FLAG specific value. */ 4296 if (mark_id == (priv->sh->dv_regc0_mask & MLX5_FLOW_MARK_DEFAULT)) 4297 tag_spec.data = MLX5_FLOW_MARK_DEFAULT; 4298 /* Build a new flow. */ 4299 if (mark_id != MLX5_DEFAULT_COPY_ID) { 4300 items[0] = (struct rte_flow_item){ 4301 .type = (enum rte_flow_item_type) 4302 MLX5_RTE_FLOW_ITEM_TYPE_TAG, 4303 .spec = &tag_spec, 4304 }; 4305 items[1] = (struct rte_flow_item){ 4306 .type = RTE_FLOW_ITEM_TYPE_END, 4307 }; 4308 actions[0] = (struct rte_flow_action){ 4309 .type = (enum rte_flow_action_type) 4310 MLX5_RTE_FLOW_ACTION_TYPE_MARK, 4311 .conf = &ftag, 4312 }; 4313 actions[1] = (struct rte_flow_action){ 4314 .type = (enum rte_flow_action_type) 4315 MLX5_RTE_FLOW_ACTION_TYPE_COPY_MREG, 4316 .conf = &cp_mreg, 4317 }; 4318 actions[2] = (struct rte_flow_action){ 4319 .type = RTE_FLOW_ACTION_TYPE_JUMP, 4320 .conf = &jump, 4321 }; 4322 actions[3] = (struct rte_flow_action){ 4323 .type = RTE_FLOW_ACTION_TYPE_END, 4324 }; 4325 } else { 4326 /* Default rule, wildcard match. */ 4327 attr.priority = MLX5_FLOW_LOWEST_PRIO_INDICATOR; 4328 items[0] = (struct rte_flow_item){ 4329 .type = RTE_FLOW_ITEM_TYPE_END, 4330 }; 4331 actions[0] = (struct rte_flow_action){ 4332 .type = (enum rte_flow_action_type) 4333 MLX5_RTE_FLOW_ACTION_TYPE_COPY_MREG, 4334 .conf = &cp_mreg, 4335 }; 4336 actions[1] = (struct rte_flow_action){ 4337 .type = RTE_FLOW_ACTION_TYPE_JUMP, 4338 .conf = &jump, 4339 }; 4340 actions[2] = (struct rte_flow_action){ 4341 .type = RTE_FLOW_ACTION_TYPE_END, 4342 }; 4343 } 4344 /* Build a new entry. */ 4345 mcp_res = mlx5_ipool_zmalloc(priv->sh->ipool[MLX5_IPOOL_MCP], &idx); 4346 if (!mcp_res) { 4347 rte_errno = ENOMEM; 4348 return NULL; 4349 } 4350 mcp_res->idx = idx; 4351 mcp_res->mark_id = mark_id; 4352 /* 4353 * The copy Flows are not included in any list. There 4354 * ones are referenced from other Flows and can not 4355 * be applied, removed, deleted in ardbitrary order 4356 * by list traversing. 4357 */ 4358 mcp_res->rix_flow = flow_list_create(dev, MLX5_FLOW_TYPE_MCP, 4359 &attr, items, actions, false, error); 4360 if (!mcp_res->rix_flow) { 4361 mlx5_ipool_free(priv->sh->ipool[MLX5_IPOOL_MCP], idx); 4362 return NULL; 4363 } 4364 return &mcp_res->hlist_ent; 4365 } 4366 4367 struct mlx5_list_entry * 4368 flow_dv_mreg_clone_cb(void *tool_ctx, struct mlx5_list_entry *oentry, 4369 void *cb_ctx __rte_unused) 4370 { 4371 struct rte_eth_dev *dev = tool_ctx; 4372 struct mlx5_priv *priv = dev->data->dev_private; 4373 struct mlx5_flow_mreg_copy_resource *mcp_res; 4374 uint32_t idx = 0; 4375 4376 mcp_res = mlx5_ipool_malloc(priv->sh->ipool[MLX5_IPOOL_MCP], &idx); 4377 if (!mcp_res) { 4378 rte_errno = ENOMEM; 4379 return NULL; 4380 } 4381 memcpy(mcp_res, oentry, sizeof(*mcp_res)); 4382 mcp_res->idx = idx; 4383 return &mcp_res->hlist_ent; 4384 } 4385 4386 void 4387 flow_dv_mreg_clone_free_cb(void *tool_ctx, struct mlx5_list_entry *entry) 4388 { 4389 struct mlx5_flow_mreg_copy_resource *mcp_res = 4390 container_of(entry, typeof(*mcp_res), hlist_ent); 4391 struct rte_eth_dev *dev = tool_ctx; 4392 struct mlx5_priv *priv = dev->data->dev_private; 4393 4394 mlx5_ipool_free(priv->sh->ipool[MLX5_IPOOL_MCP], mcp_res->idx); 4395 } 4396 4397 /** 4398 * Add a flow of copying flow metadata registers in RX_CP_TBL. 4399 * 4400 * As mark_id is unique, if there's already a registered flow for the mark_id, 4401 * return by increasing the reference counter of the resource. Otherwise, create 4402 * the resource (mcp_res) and flow. 4403 * 4404 * Flow looks like, 4405 * - If ingress port is ANY and reg_c[1] is mark_id, 4406 * flow_tag := mark_id, reg_b := reg_c[0] and jump to RX_ACT_TBL. 4407 * 4408 * For default flow (zero mark_id), flow is like, 4409 * - If ingress port is ANY, 4410 * reg_b := reg_c[0] and jump to RX_ACT_TBL. 4411 * 4412 * @param dev 4413 * Pointer to Ethernet device. 4414 * @param mark_id 4415 * ID of MARK action, zero means default flow for META. 4416 * @param[out] error 4417 * Perform verbose error reporting if not NULL. 4418 * 4419 * @return 4420 * Associated resource on success, NULL otherwise and rte_errno is set. 4421 */ 4422 static struct mlx5_flow_mreg_copy_resource * 4423 flow_mreg_add_copy_action(struct rte_eth_dev *dev, uint32_t mark_id, 4424 struct rte_flow_error *error) 4425 { 4426 struct mlx5_priv *priv = dev->data->dev_private; 4427 struct mlx5_list_entry *entry; 4428 struct mlx5_flow_cb_ctx ctx = { 4429 .dev = dev, 4430 .error = error, 4431 .data = &mark_id, 4432 }; 4433 4434 /* Check if already registered. */ 4435 MLX5_ASSERT(priv->mreg_cp_tbl); 4436 entry = mlx5_hlist_register(priv->mreg_cp_tbl, mark_id, &ctx); 4437 if (!entry) 4438 return NULL; 4439 return container_of(entry, struct mlx5_flow_mreg_copy_resource, 4440 hlist_ent); 4441 } 4442 4443 void 4444 flow_dv_mreg_remove_cb(void *tool_ctx, struct mlx5_list_entry *entry) 4445 { 4446 struct mlx5_flow_mreg_copy_resource *mcp_res = 4447 container_of(entry, typeof(*mcp_res), hlist_ent); 4448 struct rte_eth_dev *dev = tool_ctx; 4449 struct mlx5_priv *priv = dev->data->dev_private; 4450 4451 MLX5_ASSERT(mcp_res->rix_flow); 4452 flow_list_destroy(dev, MLX5_FLOW_TYPE_MCP, mcp_res->rix_flow); 4453 mlx5_ipool_free(priv->sh->ipool[MLX5_IPOOL_MCP], mcp_res->idx); 4454 } 4455 4456 /** 4457 * Release flow in RX_CP_TBL. 4458 * 4459 * @param dev 4460 * Pointer to Ethernet device. 4461 * @flow 4462 * Parent flow for wich copying is provided. 4463 */ 4464 static void 4465 flow_mreg_del_copy_action(struct rte_eth_dev *dev, 4466 struct rte_flow *flow) 4467 { 4468 struct mlx5_flow_mreg_copy_resource *mcp_res; 4469 struct mlx5_priv *priv = dev->data->dev_private; 4470 4471 if (!flow->rix_mreg_copy) 4472 return; 4473 mcp_res = mlx5_ipool_get(priv->sh->ipool[MLX5_IPOOL_MCP], 4474 flow->rix_mreg_copy); 4475 if (!mcp_res || !priv->mreg_cp_tbl) 4476 return; 4477 MLX5_ASSERT(mcp_res->rix_flow); 4478 mlx5_hlist_unregister(priv->mreg_cp_tbl, &mcp_res->hlist_ent); 4479 flow->rix_mreg_copy = 0; 4480 } 4481 4482 /** 4483 * Remove the default copy action from RX_CP_TBL. 4484 * 4485 * This functions is called in the mlx5_dev_start(). No thread safe 4486 * is guaranteed. 4487 * 4488 * @param dev 4489 * Pointer to Ethernet device. 4490 */ 4491 static void 4492 flow_mreg_del_default_copy_action(struct rte_eth_dev *dev) 4493 { 4494 struct mlx5_list_entry *entry; 4495 struct mlx5_priv *priv = dev->data->dev_private; 4496 struct mlx5_flow_cb_ctx ctx; 4497 uint32_t mark_id; 4498 4499 /* Check if default flow is registered. */ 4500 if (!priv->mreg_cp_tbl) 4501 return; 4502 mark_id = MLX5_DEFAULT_COPY_ID; 4503 ctx.data = &mark_id; 4504 entry = mlx5_hlist_lookup(priv->mreg_cp_tbl, mark_id, &ctx); 4505 if (!entry) 4506 return; 4507 mlx5_hlist_unregister(priv->mreg_cp_tbl, entry); 4508 } 4509 4510 /** 4511 * Add the default copy action in in RX_CP_TBL. 4512 * 4513 * This functions is called in the mlx5_dev_start(). No thread safe 4514 * is guaranteed. 4515 * 4516 * @param dev 4517 * Pointer to Ethernet device. 4518 * @param[out] error 4519 * Perform verbose error reporting if not NULL. 4520 * 4521 * @return 4522 * 0 for success, negative value otherwise and rte_errno is set. 4523 */ 4524 static int 4525 flow_mreg_add_default_copy_action(struct rte_eth_dev *dev, 4526 struct rte_flow_error *error) 4527 { 4528 struct mlx5_priv *priv = dev->data->dev_private; 4529 struct mlx5_flow_mreg_copy_resource *mcp_res; 4530 struct mlx5_flow_cb_ctx ctx; 4531 uint32_t mark_id; 4532 4533 /* Check whether extensive metadata feature is engaged. */ 4534 if (!priv->config.dv_flow_en || 4535 priv->config.dv_xmeta_en == MLX5_XMETA_MODE_LEGACY || 4536 !mlx5_flow_ext_mreg_supported(dev) || 4537 !priv->sh->dv_regc0_mask) 4538 return 0; 4539 /* 4540 * Add default mreg copy flow may be called multiple time, but 4541 * only be called once in stop. Avoid register it twice. 4542 */ 4543 mark_id = MLX5_DEFAULT_COPY_ID; 4544 ctx.data = &mark_id; 4545 if (mlx5_hlist_lookup(priv->mreg_cp_tbl, mark_id, &ctx)) 4546 return 0; 4547 mcp_res = flow_mreg_add_copy_action(dev, mark_id, error); 4548 if (!mcp_res) 4549 return -rte_errno; 4550 return 0; 4551 } 4552 4553 /** 4554 * Add a flow of copying flow metadata registers in RX_CP_TBL. 4555 * 4556 * All the flow having Q/RSS action should be split by 4557 * flow_mreg_split_qrss_prep() to pass by RX_CP_TBL. A flow in the RX_CP_TBL 4558 * performs the following, 4559 * - CQE->flow_tag := reg_c[1] (MARK) 4560 * - CQE->flow_table_metadata (reg_b) := reg_c[0] (META) 4561 * As CQE's flow_tag is not a register, it can't be simply copied from reg_c[1] 4562 * but there should be a flow per each MARK ID set by MARK action. 4563 * 4564 * For the aforementioned reason, if there's a MARK action in flow's action 4565 * list, a corresponding flow should be added to the RX_CP_TBL in order to copy 4566 * the MARK ID to CQE's flow_tag like, 4567 * - If reg_c[1] is mark_id, 4568 * flow_tag := mark_id, reg_b := reg_c[0] and jump to RX_ACT_TBL. 4569 * 4570 * For SET_META action which stores value in reg_c[0], as the destination is 4571 * also a flow metadata register (reg_b), adding a default flow is enough. Zero 4572 * MARK ID means the default flow. The default flow looks like, 4573 * - For all flow, reg_b := reg_c[0] and jump to RX_ACT_TBL. 4574 * 4575 * @param dev 4576 * Pointer to Ethernet device. 4577 * @param flow 4578 * Pointer to flow structure. 4579 * @param[in] actions 4580 * Pointer to the list of actions. 4581 * @param[out] error 4582 * Perform verbose error reporting if not NULL. 4583 * 4584 * @return 4585 * 0 on success, negative value otherwise and rte_errno is set. 4586 */ 4587 static int 4588 flow_mreg_update_copy_table(struct rte_eth_dev *dev, 4589 struct rte_flow *flow, 4590 const struct rte_flow_action *actions, 4591 struct rte_flow_error *error) 4592 { 4593 struct mlx5_priv *priv = dev->data->dev_private; 4594 struct mlx5_dev_config *config = &priv->config; 4595 struct mlx5_flow_mreg_copy_resource *mcp_res; 4596 const struct rte_flow_action_mark *mark; 4597 4598 /* Check whether extensive metadata feature is engaged. */ 4599 if (!config->dv_flow_en || 4600 config->dv_xmeta_en == MLX5_XMETA_MODE_LEGACY || 4601 !mlx5_flow_ext_mreg_supported(dev) || 4602 !priv->sh->dv_regc0_mask) 4603 return 0; 4604 /* Find MARK action. */ 4605 for (; actions->type != RTE_FLOW_ACTION_TYPE_END; actions++) { 4606 switch (actions->type) { 4607 case RTE_FLOW_ACTION_TYPE_FLAG: 4608 mcp_res = flow_mreg_add_copy_action 4609 (dev, MLX5_FLOW_MARK_DEFAULT, error); 4610 if (!mcp_res) 4611 return -rte_errno; 4612 flow->rix_mreg_copy = mcp_res->idx; 4613 return 0; 4614 case RTE_FLOW_ACTION_TYPE_MARK: 4615 mark = (const struct rte_flow_action_mark *) 4616 actions->conf; 4617 mcp_res = 4618 flow_mreg_add_copy_action(dev, mark->id, error); 4619 if (!mcp_res) 4620 return -rte_errno; 4621 flow->rix_mreg_copy = mcp_res->idx; 4622 return 0; 4623 default: 4624 break; 4625 } 4626 } 4627 return 0; 4628 } 4629 4630 #define MLX5_MAX_SPLIT_ACTIONS 24 4631 #define MLX5_MAX_SPLIT_ITEMS 24 4632 4633 /** 4634 * Split the hairpin flow. 4635 * Since HW can't support encap and push-vlan on Rx, we move these 4636 * actions to Tx. 4637 * If the count action is after the encap then we also 4638 * move the count action. in this case the count will also measure 4639 * the outer bytes. 4640 * 4641 * @param dev 4642 * Pointer to Ethernet device. 4643 * @param[in] actions 4644 * Associated actions (list terminated by the END action). 4645 * @param[out] actions_rx 4646 * Rx flow actions. 4647 * @param[out] actions_tx 4648 * Tx flow actions.. 4649 * @param[out] pattern_tx 4650 * The pattern items for the Tx flow. 4651 * @param[out] flow_id 4652 * The flow ID connected to this flow. 4653 * 4654 * @return 4655 * 0 on success. 4656 */ 4657 static int 4658 flow_hairpin_split(struct rte_eth_dev *dev, 4659 const struct rte_flow_action actions[], 4660 struct rte_flow_action actions_rx[], 4661 struct rte_flow_action actions_tx[], 4662 struct rte_flow_item pattern_tx[], 4663 uint32_t flow_id) 4664 { 4665 const struct rte_flow_action_raw_encap *raw_encap; 4666 const struct rte_flow_action_raw_decap *raw_decap; 4667 struct mlx5_rte_flow_action_set_tag *set_tag; 4668 struct rte_flow_action *tag_action; 4669 struct mlx5_rte_flow_item_tag *tag_item; 4670 struct rte_flow_item *item; 4671 char *addr; 4672 int encap = 0; 4673 4674 for (; actions->type != RTE_FLOW_ACTION_TYPE_END; actions++) { 4675 switch (actions->type) { 4676 case RTE_FLOW_ACTION_TYPE_VXLAN_ENCAP: 4677 case RTE_FLOW_ACTION_TYPE_NVGRE_ENCAP: 4678 case RTE_FLOW_ACTION_TYPE_OF_PUSH_VLAN: 4679 case RTE_FLOW_ACTION_TYPE_OF_SET_VLAN_VID: 4680 case RTE_FLOW_ACTION_TYPE_OF_SET_VLAN_PCP: 4681 rte_memcpy(actions_tx, actions, 4682 sizeof(struct rte_flow_action)); 4683 actions_tx++; 4684 break; 4685 case RTE_FLOW_ACTION_TYPE_COUNT: 4686 if (encap) { 4687 rte_memcpy(actions_tx, actions, 4688 sizeof(struct rte_flow_action)); 4689 actions_tx++; 4690 } else { 4691 rte_memcpy(actions_rx, actions, 4692 sizeof(struct rte_flow_action)); 4693 actions_rx++; 4694 } 4695 break; 4696 case RTE_FLOW_ACTION_TYPE_RAW_ENCAP: 4697 raw_encap = actions->conf; 4698 if (raw_encap->size > MLX5_ENCAPSULATION_DECISION_SIZE) { 4699 memcpy(actions_tx, actions, 4700 sizeof(struct rte_flow_action)); 4701 actions_tx++; 4702 encap = 1; 4703 } else { 4704 rte_memcpy(actions_rx, actions, 4705 sizeof(struct rte_flow_action)); 4706 actions_rx++; 4707 } 4708 break; 4709 case RTE_FLOW_ACTION_TYPE_RAW_DECAP: 4710 raw_decap = actions->conf; 4711 if (raw_decap->size < MLX5_ENCAPSULATION_DECISION_SIZE) { 4712 memcpy(actions_tx, actions, 4713 sizeof(struct rte_flow_action)); 4714 actions_tx++; 4715 } else { 4716 rte_memcpy(actions_rx, actions, 4717 sizeof(struct rte_flow_action)); 4718 actions_rx++; 4719 } 4720 break; 4721 default: 4722 rte_memcpy(actions_rx, actions, 4723 sizeof(struct rte_flow_action)); 4724 actions_rx++; 4725 break; 4726 } 4727 } 4728 /* Add set meta action and end action for the Rx flow. */ 4729 tag_action = actions_rx; 4730 tag_action->type = (enum rte_flow_action_type) 4731 MLX5_RTE_FLOW_ACTION_TYPE_TAG; 4732 actions_rx++; 4733 rte_memcpy(actions_rx, actions, sizeof(struct rte_flow_action)); 4734 actions_rx++; 4735 set_tag = (void *)actions_rx; 4736 *set_tag = (struct mlx5_rte_flow_action_set_tag) { 4737 .id = mlx5_flow_get_reg_id(dev, MLX5_HAIRPIN_RX, 0, NULL), 4738 .data = flow_id, 4739 }; 4740 MLX5_ASSERT(set_tag->id > REG_NON); 4741 tag_action->conf = set_tag; 4742 /* Create Tx item list. */ 4743 rte_memcpy(actions_tx, actions, sizeof(struct rte_flow_action)); 4744 addr = (void *)&pattern_tx[2]; 4745 item = pattern_tx; 4746 item->type = (enum rte_flow_item_type) 4747 MLX5_RTE_FLOW_ITEM_TYPE_TAG; 4748 tag_item = (void *)addr; 4749 tag_item->data = flow_id; 4750 tag_item->id = mlx5_flow_get_reg_id(dev, MLX5_HAIRPIN_TX, 0, NULL); 4751 MLX5_ASSERT(set_tag->id > REG_NON); 4752 item->spec = tag_item; 4753 addr += sizeof(struct mlx5_rte_flow_item_tag); 4754 tag_item = (void *)addr; 4755 tag_item->data = UINT32_MAX; 4756 tag_item->id = UINT16_MAX; 4757 item->mask = tag_item; 4758 item->last = NULL; 4759 item++; 4760 item->type = RTE_FLOW_ITEM_TYPE_END; 4761 return 0; 4762 } 4763 4764 /** 4765 * The last stage of splitting chain, just creates the subflow 4766 * without any modification. 4767 * 4768 * @param[in] dev 4769 * Pointer to Ethernet device. 4770 * @param[in] flow 4771 * Parent flow structure pointer. 4772 * @param[in, out] sub_flow 4773 * Pointer to return the created subflow, may be NULL. 4774 * @param[in] attr 4775 * Flow rule attributes. 4776 * @param[in] items 4777 * Pattern specification (list terminated by the END pattern item). 4778 * @param[in] actions 4779 * Associated actions (list terminated by the END action). 4780 * @param[in] flow_split_info 4781 * Pointer to flow split info structure. 4782 * @param[out] error 4783 * Perform verbose error reporting if not NULL. 4784 * @return 4785 * 0 on success, negative value otherwise 4786 */ 4787 static int 4788 flow_create_split_inner(struct rte_eth_dev *dev, 4789 struct rte_flow *flow, 4790 struct mlx5_flow **sub_flow, 4791 const struct rte_flow_attr *attr, 4792 const struct rte_flow_item items[], 4793 const struct rte_flow_action actions[], 4794 struct mlx5_flow_split_info *flow_split_info, 4795 struct rte_flow_error *error) 4796 { 4797 struct mlx5_flow *dev_flow; 4798 4799 dev_flow = flow_drv_prepare(dev, flow, attr, items, actions, 4800 flow_split_info->flow_idx, error); 4801 if (!dev_flow) 4802 return -rte_errno; 4803 dev_flow->flow = flow; 4804 dev_flow->external = flow_split_info->external; 4805 dev_flow->skip_scale = flow_split_info->skip_scale; 4806 /* Subflow object was created, we must include one in the list. */ 4807 SILIST_INSERT(&flow->dev_handles, dev_flow->handle_idx, 4808 dev_flow->handle, next); 4809 /* 4810 * If dev_flow is as one of the suffix flow, some actions in suffix 4811 * flow may need some user defined item layer flags, and pass the 4812 * Metadate rxq mark flag to suffix flow as well. 4813 */ 4814 if (flow_split_info->prefix_layers) 4815 dev_flow->handle->layers = flow_split_info->prefix_layers; 4816 if (flow_split_info->prefix_mark) 4817 dev_flow->handle->mark = 1; 4818 if (sub_flow) 4819 *sub_flow = dev_flow; 4820 #ifdef HAVE_IBV_FLOW_DV_SUPPORT 4821 dev_flow->dv.table_id = flow_split_info->table_id; 4822 #endif 4823 return flow_drv_translate(dev, dev_flow, attr, items, actions, error); 4824 } 4825 4826 /** 4827 * Get the sub policy of a meter. 4828 * 4829 * @param[in] dev 4830 * Pointer to Ethernet device. 4831 * @param[in] flow 4832 * Parent flow structure pointer. 4833 * @param wks 4834 * Pointer to thread flow work space. 4835 * @param[in] attr 4836 * Flow rule attributes. 4837 * @param[in] items 4838 * Pattern specification (list terminated by the END pattern item). 4839 * @param[out] error 4840 * Perform verbose error reporting if not NULL. 4841 * 4842 * @return 4843 * Pointer to the meter sub policy, NULL otherwise and rte_errno is set. 4844 */ 4845 static struct mlx5_flow_meter_sub_policy * 4846 get_meter_sub_policy(struct rte_eth_dev *dev, 4847 struct rte_flow *flow, 4848 struct mlx5_flow_workspace *wks, 4849 const struct rte_flow_attr *attr, 4850 const struct rte_flow_item items[], 4851 struct rte_flow_error *error) 4852 { 4853 struct mlx5_flow_meter_policy *policy; 4854 struct mlx5_flow_meter_policy *final_policy; 4855 struct mlx5_flow_meter_sub_policy *sub_policy = NULL; 4856 4857 policy = wks->policy; 4858 final_policy = policy->is_hierarchy ? wks->final_policy : policy; 4859 if (final_policy->is_rss || final_policy->is_queue) { 4860 struct mlx5_flow_rss_desc rss_desc_v[MLX5_MTR_RTE_COLORS]; 4861 struct mlx5_flow_rss_desc *rss_desc[MLX5_MTR_RTE_COLORS] = {0}; 4862 uint32_t i; 4863 4864 /* 4865 * This is a tmp dev_flow, 4866 * no need to register any matcher for it in translate. 4867 */ 4868 wks->skip_matcher_reg = 1; 4869 for (i = 0; i < MLX5_MTR_RTE_COLORS; i++) { 4870 struct mlx5_flow dev_flow = {0}; 4871 struct mlx5_flow_handle dev_handle = { {0} }; 4872 uint8_t fate = final_policy->act_cnt[i].fate_action; 4873 4874 if (fate == MLX5_FLOW_FATE_SHARED_RSS) { 4875 const struct rte_flow_action_rss *rss_act = 4876 final_policy->act_cnt[i].rss->conf; 4877 struct rte_flow_action rss_actions[2] = { 4878 [0] = { 4879 .type = RTE_FLOW_ACTION_TYPE_RSS, 4880 .conf = rss_act, 4881 }, 4882 [1] = { 4883 .type = RTE_FLOW_ACTION_TYPE_END, 4884 .conf = NULL, 4885 } 4886 }; 4887 4888 dev_flow.handle = &dev_handle; 4889 dev_flow.ingress = attr->ingress; 4890 dev_flow.flow = flow; 4891 dev_flow.external = 0; 4892 #ifdef HAVE_IBV_FLOW_DV_SUPPORT 4893 dev_flow.dv.transfer = attr->transfer; 4894 #endif 4895 /** 4896 * Translate RSS action to get rss hash fields. 4897 */ 4898 if (flow_drv_translate(dev, &dev_flow, attr, 4899 items, rss_actions, error)) 4900 goto exit; 4901 rss_desc_v[i] = wks->rss_desc; 4902 rss_desc_v[i].key_len = MLX5_RSS_HASH_KEY_LEN; 4903 rss_desc_v[i].hash_fields = 4904 dev_flow.hash_fields; 4905 rss_desc_v[i].queue_num = 4906 rss_desc_v[i].hash_fields ? 4907 rss_desc_v[i].queue_num : 1; 4908 rss_desc_v[i].tunnel = 4909 !!(dev_flow.handle->layers & 4910 MLX5_FLOW_LAYER_TUNNEL); 4911 /* Use the RSS queues in the containers. */ 4912 rss_desc_v[i].queue = 4913 (uint16_t *)(uintptr_t)rss_act->queue; 4914 rss_desc[i] = &rss_desc_v[i]; 4915 } else if (fate == MLX5_FLOW_FATE_QUEUE) { 4916 /* This is queue action. */ 4917 rss_desc_v[i] = wks->rss_desc; 4918 rss_desc_v[i].key_len = 0; 4919 rss_desc_v[i].hash_fields = 0; 4920 rss_desc_v[i].queue = 4921 &final_policy->act_cnt[i].queue; 4922 rss_desc_v[i].queue_num = 1; 4923 rss_desc[i] = &rss_desc_v[i]; 4924 } else { 4925 rss_desc[i] = NULL; 4926 } 4927 } 4928 sub_policy = flow_drv_meter_sub_policy_rss_prepare(dev, 4929 flow, policy, rss_desc); 4930 } else { 4931 enum mlx5_meter_domain mtr_domain = 4932 attr->transfer ? MLX5_MTR_DOMAIN_TRANSFER : 4933 (attr->egress ? MLX5_MTR_DOMAIN_EGRESS : 4934 MLX5_MTR_DOMAIN_INGRESS); 4935 sub_policy = policy->sub_policys[mtr_domain][0]; 4936 } 4937 if (!sub_policy) 4938 rte_flow_error_set(error, EINVAL, 4939 RTE_FLOW_ERROR_TYPE_UNSPECIFIED, NULL, 4940 "Failed to get meter sub-policy."); 4941 exit: 4942 return sub_policy; 4943 } 4944 4945 /** 4946 * Split the meter flow. 4947 * 4948 * As meter flow will split to three sub flow, other than meter 4949 * action, the other actions make sense to only meter accepts 4950 * the packet. If it need to be dropped, no other additional 4951 * actions should be take. 4952 * 4953 * One kind of special action which decapsulates the L3 tunnel 4954 * header will be in the prefix sub flow, as not to take the 4955 * L3 tunnel header into account. 4956 * 4957 * @param[in] dev 4958 * Pointer to Ethernet device. 4959 * @param[in] flow 4960 * Parent flow structure pointer. 4961 * @param wks 4962 * Pointer to thread flow work space. 4963 * @param[in] attr 4964 * Flow rule attributes. 4965 * @param[in] items 4966 * Pattern specification (list terminated by the END pattern item). 4967 * @param[out] sfx_items 4968 * Suffix flow match items (list terminated by the END pattern item). 4969 * @param[in] actions 4970 * Associated actions (list terminated by the END action). 4971 * @param[out] actions_sfx 4972 * Suffix flow actions. 4973 * @param[out] actions_pre 4974 * Prefix flow actions. 4975 * @param[out] mtr_flow_id 4976 * Pointer to meter flow id. 4977 * @param[out] error 4978 * Perform verbose error reporting if not NULL. 4979 * 4980 * @return 4981 * 0 on success, a negative errno value otherwise and rte_errno is set. 4982 */ 4983 static int 4984 flow_meter_split_prep(struct rte_eth_dev *dev, 4985 struct rte_flow *flow, 4986 struct mlx5_flow_workspace *wks, 4987 const struct rte_flow_attr *attr, 4988 const struct rte_flow_item items[], 4989 struct rte_flow_item sfx_items[], 4990 const struct rte_flow_action actions[], 4991 struct rte_flow_action actions_sfx[], 4992 struct rte_flow_action actions_pre[], 4993 uint32_t *mtr_flow_id, 4994 struct rte_flow_error *error) 4995 { 4996 struct mlx5_priv *priv = dev->data->dev_private; 4997 struct mlx5_flow_meter_info *fm = wks->fm; 4998 struct rte_flow_action *tag_action = NULL; 4999 struct rte_flow_item *tag_item; 5000 struct mlx5_rte_flow_action_set_tag *set_tag; 5001 const struct rte_flow_action_raw_encap *raw_encap; 5002 const struct rte_flow_action_raw_decap *raw_decap; 5003 struct mlx5_rte_flow_item_tag *tag_item_spec; 5004 struct mlx5_rte_flow_item_tag *tag_item_mask; 5005 uint32_t tag_id = 0; 5006 struct rte_flow_item *vlan_item_dst = NULL; 5007 const struct rte_flow_item *vlan_item_src = NULL; 5008 struct rte_flow_action *hw_mtr_action; 5009 struct rte_flow_action *action_pre_head = NULL; 5010 int32_t flow_src_port = priv->representor_id; 5011 bool mtr_first; 5012 uint8_t mtr_id_offset = priv->mtr_reg_share ? MLX5_MTR_COLOR_BITS : 0; 5013 uint8_t mtr_reg_bits = priv->mtr_reg_share ? 5014 MLX5_MTR_IDLE_BITS_IN_COLOR_REG : MLX5_REG_BITS; 5015 uint32_t flow_id = 0; 5016 uint32_t flow_id_reversed = 0; 5017 uint8_t flow_id_bits = 0; 5018 int shift; 5019 5020 /* Prepare the suffix subflow items. */ 5021 tag_item = sfx_items++; 5022 for (; items->type != RTE_FLOW_ITEM_TYPE_END; items++) { 5023 struct mlx5_priv *port_priv; 5024 const struct rte_flow_item_port_id *pid_v; 5025 int item_type = items->type; 5026 5027 switch (item_type) { 5028 case RTE_FLOW_ITEM_TYPE_PORT_ID: 5029 pid_v = items->spec; 5030 MLX5_ASSERT(pid_v); 5031 port_priv = mlx5_port_to_eswitch_info(pid_v->id, false); 5032 if (!port_priv) 5033 return rte_flow_error_set(error, 5034 rte_errno, 5035 RTE_FLOW_ERROR_TYPE_ITEM_SPEC, 5036 pid_v, 5037 "Failed to get port info."); 5038 flow_src_port = port_priv->representor_id; 5039 if (!fm->def_policy && wks->policy->is_hierarchy && 5040 flow_src_port != priv->representor_id) { 5041 if (flow_drv_mtr_hierarchy_rule_create(dev, 5042 flow, fm, 5043 flow_src_port, 5044 items, 5045 error)) 5046 return -rte_errno; 5047 } 5048 memcpy(sfx_items, items, sizeof(*sfx_items)); 5049 sfx_items++; 5050 break; 5051 case RTE_FLOW_ITEM_TYPE_VLAN: 5052 /* Determine if copy vlan item below. */ 5053 vlan_item_src = items; 5054 vlan_item_dst = sfx_items++; 5055 vlan_item_dst->type = RTE_FLOW_ITEM_TYPE_VOID; 5056 break; 5057 default: 5058 break; 5059 } 5060 } 5061 sfx_items->type = RTE_FLOW_ITEM_TYPE_END; 5062 sfx_items++; 5063 mtr_first = priv->sh->meter_aso_en && 5064 (attr->egress || (attr->transfer && flow_src_port != UINT16_MAX)); 5065 /* For ASO meter, meter must be before tag in TX direction. */ 5066 if (mtr_first) { 5067 action_pre_head = actions_pre++; 5068 /* Leave space for tag action. */ 5069 tag_action = actions_pre++; 5070 } 5071 /* Prepare the actions for prefix and suffix flow. */ 5072 for (; actions->type != RTE_FLOW_ACTION_TYPE_END; actions++) { 5073 struct rte_flow_action *action_cur = NULL; 5074 5075 switch (actions->type) { 5076 case RTE_FLOW_ACTION_TYPE_METER: 5077 if (mtr_first) { 5078 action_cur = action_pre_head; 5079 } else { 5080 /* Leave space for tag action. */ 5081 tag_action = actions_pre++; 5082 action_cur = actions_pre++; 5083 } 5084 break; 5085 case RTE_FLOW_ACTION_TYPE_VXLAN_DECAP: 5086 case RTE_FLOW_ACTION_TYPE_NVGRE_DECAP: 5087 action_cur = actions_pre++; 5088 break; 5089 case RTE_FLOW_ACTION_TYPE_RAW_ENCAP: 5090 raw_encap = actions->conf; 5091 if (raw_encap->size < MLX5_ENCAPSULATION_DECISION_SIZE) 5092 action_cur = actions_pre++; 5093 break; 5094 case RTE_FLOW_ACTION_TYPE_RAW_DECAP: 5095 raw_decap = actions->conf; 5096 if (raw_decap->size > MLX5_ENCAPSULATION_DECISION_SIZE) 5097 action_cur = actions_pre++; 5098 break; 5099 case RTE_FLOW_ACTION_TYPE_OF_PUSH_VLAN: 5100 case RTE_FLOW_ACTION_TYPE_OF_SET_VLAN_VID: 5101 if (vlan_item_dst && vlan_item_src) { 5102 memcpy(vlan_item_dst, vlan_item_src, 5103 sizeof(*vlan_item_dst)); 5104 /* 5105 * Convert to internal match item, it is used 5106 * for vlan push and set vid. 5107 */ 5108 vlan_item_dst->type = (enum rte_flow_item_type) 5109 MLX5_RTE_FLOW_ITEM_TYPE_VLAN; 5110 } 5111 break; 5112 default: 5113 break; 5114 } 5115 if (!action_cur) 5116 action_cur = (fm->def_policy) ? 5117 actions_sfx++ : actions_pre++; 5118 memcpy(action_cur, actions, sizeof(struct rte_flow_action)); 5119 } 5120 /* Add end action to the actions. */ 5121 actions_sfx->type = RTE_FLOW_ACTION_TYPE_END; 5122 if (priv->sh->meter_aso_en) { 5123 /** 5124 * For ASO meter, need to add an extra jump action explicitly, 5125 * to jump from meter to policer table. 5126 */ 5127 struct mlx5_flow_meter_sub_policy *sub_policy; 5128 struct mlx5_flow_tbl_data_entry *tbl_data; 5129 5130 if (!fm->def_policy) { 5131 sub_policy = get_meter_sub_policy(dev, flow, wks, 5132 attr, items, error); 5133 if (!sub_policy) 5134 return -rte_errno; 5135 } else { 5136 enum mlx5_meter_domain mtr_domain = 5137 attr->transfer ? MLX5_MTR_DOMAIN_TRANSFER : 5138 (attr->egress ? MLX5_MTR_DOMAIN_EGRESS : 5139 MLX5_MTR_DOMAIN_INGRESS); 5140 5141 sub_policy = 5142 &priv->sh->mtrmng->def_policy[mtr_domain]->sub_policy; 5143 } 5144 tbl_data = container_of(sub_policy->tbl_rsc, 5145 struct mlx5_flow_tbl_data_entry, tbl); 5146 hw_mtr_action = actions_pre++; 5147 hw_mtr_action->type = (enum rte_flow_action_type) 5148 MLX5_RTE_FLOW_ACTION_TYPE_JUMP; 5149 hw_mtr_action->conf = tbl_data->jump.action; 5150 } 5151 actions_pre->type = RTE_FLOW_ACTION_TYPE_END; 5152 actions_pre++; 5153 if (!tag_action) 5154 return rte_flow_error_set(error, ENOMEM, 5155 RTE_FLOW_ERROR_TYPE_UNSPECIFIED, 5156 NULL, "No tag action space."); 5157 if (!mtr_flow_id) { 5158 tag_action->type = RTE_FLOW_ACTION_TYPE_VOID; 5159 goto exit; 5160 } 5161 /* Only default-policy Meter creates mtr flow id. */ 5162 if (fm->def_policy) { 5163 mlx5_ipool_malloc(fm->flow_ipool, &tag_id); 5164 if (!tag_id) 5165 return rte_flow_error_set(error, ENOMEM, 5166 RTE_FLOW_ERROR_TYPE_UNSPECIFIED, NULL, 5167 "Failed to allocate meter flow id."); 5168 flow_id = tag_id - 1; 5169 flow_id_bits = (!flow_id) ? 1 : 5170 (MLX5_REG_BITS - __builtin_clz(flow_id)); 5171 if ((flow_id_bits + priv->sh->mtrmng->max_mtr_bits) > 5172 mtr_reg_bits) { 5173 mlx5_ipool_free(fm->flow_ipool, tag_id); 5174 return rte_flow_error_set(error, EINVAL, 5175 RTE_FLOW_ERROR_TYPE_UNSPECIFIED, NULL, 5176 "Meter flow id exceeds max limit."); 5177 } 5178 if (flow_id_bits > priv->sh->mtrmng->max_mtr_flow_bits) 5179 priv->sh->mtrmng->max_mtr_flow_bits = flow_id_bits; 5180 } 5181 /* Build tag actions and items for meter_id/meter flow_id. */ 5182 set_tag = (struct mlx5_rte_flow_action_set_tag *)actions_pre; 5183 tag_item_spec = (struct mlx5_rte_flow_item_tag *)sfx_items; 5184 tag_item_mask = tag_item_spec + 1; 5185 /* Both flow_id and meter_id share the same register. */ 5186 *set_tag = (struct mlx5_rte_flow_action_set_tag) { 5187 .id = (enum modify_reg)mlx5_flow_get_reg_id(dev, MLX5_MTR_ID, 5188 0, error), 5189 .offset = mtr_id_offset, 5190 .length = mtr_reg_bits, 5191 .data = flow->meter, 5192 }; 5193 /* 5194 * The color Reg bits used by flow_id are growing from 5195 * msb to lsb, so must do bit reverse for flow_id val in RegC. 5196 */ 5197 for (shift = 0; shift < flow_id_bits; shift++) 5198 flow_id_reversed = (flow_id_reversed << 1) | 5199 ((flow_id >> shift) & 0x1); 5200 set_tag->data |= 5201 flow_id_reversed << (mtr_reg_bits - flow_id_bits); 5202 tag_item_spec->id = set_tag->id; 5203 tag_item_spec->data = set_tag->data << mtr_id_offset; 5204 tag_item_mask->data = UINT32_MAX << mtr_id_offset; 5205 tag_action->type = (enum rte_flow_action_type) 5206 MLX5_RTE_FLOW_ACTION_TYPE_TAG; 5207 tag_action->conf = set_tag; 5208 tag_item->type = (enum rte_flow_item_type) 5209 MLX5_RTE_FLOW_ITEM_TYPE_TAG; 5210 tag_item->spec = tag_item_spec; 5211 tag_item->last = NULL; 5212 tag_item->mask = tag_item_mask; 5213 exit: 5214 if (mtr_flow_id) 5215 *mtr_flow_id = tag_id; 5216 return 0; 5217 } 5218 5219 /** 5220 * Split action list having QUEUE/RSS for metadata register copy. 5221 * 5222 * Once Q/RSS action is detected in user's action list, the flow action 5223 * should be split in order to copy metadata registers, which will happen in 5224 * RX_CP_TBL like, 5225 * - CQE->flow_tag := reg_c[1] (MARK) 5226 * - CQE->flow_table_metadata (reg_b) := reg_c[0] (META) 5227 * The Q/RSS action will be performed on RX_ACT_TBL after passing by RX_CP_TBL. 5228 * This is because the last action of each flow must be a terminal action 5229 * (QUEUE, RSS or DROP). 5230 * 5231 * Flow ID must be allocated to identify actions in the RX_ACT_TBL and it is 5232 * stored and kept in the mlx5_flow structure per each sub_flow. 5233 * 5234 * The Q/RSS action is replaced with, 5235 * - SET_TAG, setting the allocated flow ID to reg_c[2]. 5236 * And the following JUMP action is added at the end, 5237 * - JUMP, to RX_CP_TBL. 5238 * 5239 * A flow to perform remained Q/RSS action will be created in RX_ACT_TBL by 5240 * flow_create_split_metadata() routine. The flow will look like, 5241 * - If flow ID matches (reg_c[2]), perform Q/RSS. 5242 * 5243 * @param dev 5244 * Pointer to Ethernet device. 5245 * @param[out] split_actions 5246 * Pointer to store split actions to jump to CP_TBL. 5247 * @param[in] actions 5248 * Pointer to the list of original flow actions. 5249 * @param[in] qrss 5250 * Pointer to the Q/RSS action. 5251 * @param[in] actions_n 5252 * Number of original actions. 5253 * @param[out] error 5254 * Perform verbose error reporting if not NULL. 5255 * 5256 * @return 5257 * non-zero unique flow_id on success, otherwise 0 and 5258 * error/rte_error are set. 5259 */ 5260 static uint32_t 5261 flow_mreg_split_qrss_prep(struct rte_eth_dev *dev, 5262 struct rte_flow_action *split_actions, 5263 const struct rte_flow_action *actions, 5264 const struct rte_flow_action *qrss, 5265 int actions_n, struct rte_flow_error *error) 5266 { 5267 struct mlx5_priv *priv = dev->data->dev_private; 5268 struct mlx5_rte_flow_action_set_tag *set_tag; 5269 struct rte_flow_action_jump *jump; 5270 const int qrss_idx = qrss - actions; 5271 uint32_t flow_id = 0; 5272 int ret = 0; 5273 5274 /* 5275 * Given actions will be split 5276 * - Replace QUEUE/RSS action with SET_TAG to set flow ID. 5277 * - Add jump to mreg CP_TBL. 5278 * As a result, there will be one more action. 5279 */ 5280 ++actions_n; 5281 memcpy(split_actions, actions, sizeof(*split_actions) * actions_n); 5282 set_tag = (void *)(split_actions + actions_n); 5283 /* 5284 * If tag action is not set to void(it means we are not the meter 5285 * suffix flow), add the tag action. Since meter suffix flow already 5286 * has the tag added. 5287 */ 5288 if (split_actions[qrss_idx].type != RTE_FLOW_ACTION_TYPE_VOID) { 5289 /* 5290 * Allocate the new subflow ID. This one is unique within 5291 * device and not shared with representors. Otherwise, 5292 * we would have to resolve multi-thread access synch 5293 * issue. Each flow on the shared device is appended 5294 * with source vport identifier, so the resulting 5295 * flows will be unique in the shared (by master and 5296 * representors) domain even if they have coinciding 5297 * IDs. 5298 */ 5299 mlx5_ipool_malloc(priv->sh->ipool 5300 [MLX5_IPOOL_RSS_EXPANTION_FLOW_ID], &flow_id); 5301 if (!flow_id) 5302 return rte_flow_error_set(error, ENOMEM, 5303 RTE_FLOW_ERROR_TYPE_ACTION, 5304 NULL, "can't allocate id " 5305 "for split Q/RSS subflow"); 5306 /* Internal SET_TAG action to set flow ID. */ 5307 *set_tag = (struct mlx5_rte_flow_action_set_tag){ 5308 .data = flow_id, 5309 }; 5310 ret = mlx5_flow_get_reg_id(dev, MLX5_COPY_MARK, 0, error); 5311 if (ret < 0) 5312 return ret; 5313 set_tag->id = ret; 5314 /* Construct new actions array. */ 5315 /* Replace QUEUE/RSS action. */ 5316 split_actions[qrss_idx] = (struct rte_flow_action){ 5317 .type = (enum rte_flow_action_type) 5318 MLX5_RTE_FLOW_ACTION_TYPE_TAG, 5319 .conf = set_tag, 5320 }; 5321 } 5322 /* JUMP action to jump to mreg copy table (CP_TBL). */ 5323 jump = (void *)(set_tag + 1); 5324 *jump = (struct rte_flow_action_jump){ 5325 .group = MLX5_FLOW_MREG_CP_TABLE_GROUP, 5326 }; 5327 split_actions[actions_n - 2] = (struct rte_flow_action){ 5328 .type = RTE_FLOW_ACTION_TYPE_JUMP, 5329 .conf = jump, 5330 }; 5331 split_actions[actions_n - 1] = (struct rte_flow_action){ 5332 .type = RTE_FLOW_ACTION_TYPE_END, 5333 }; 5334 return flow_id; 5335 } 5336 5337 /** 5338 * Extend the given action list for Tx metadata copy. 5339 * 5340 * Copy the given action list to the ext_actions and add flow metadata register 5341 * copy action in order to copy reg_a set by WQE to reg_c[0]. 5342 * 5343 * @param[out] ext_actions 5344 * Pointer to the extended action list. 5345 * @param[in] actions 5346 * Pointer to the list of actions. 5347 * @param[in] actions_n 5348 * Number of actions in the list. 5349 * @param[out] error 5350 * Perform verbose error reporting if not NULL. 5351 * @param[in] encap_idx 5352 * The encap action inndex. 5353 * 5354 * @return 5355 * 0 on success, negative value otherwise 5356 */ 5357 static int 5358 flow_mreg_tx_copy_prep(struct rte_eth_dev *dev, 5359 struct rte_flow_action *ext_actions, 5360 const struct rte_flow_action *actions, 5361 int actions_n, struct rte_flow_error *error, 5362 int encap_idx) 5363 { 5364 struct mlx5_flow_action_copy_mreg *cp_mreg = 5365 (struct mlx5_flow_action_copy_mreg *) 5366 (ext_actions + actions_n + 1); 5367 int ret; 5368 5369 ret = mlx5_flow_get_reg_id(dev, MLX5_METADATA_RX, 0, error); 5370 if (ret < 0) 5371 return ret; 5372 cp_mreg->dst = ret; 5373 ret = mlx5_flow_get_reg_id(dev, MLX5_METADATA_TX, 0, error); 5374 if (ret < 0) 5375 return ret; 5376 cp_mreg->src = ret; 5377 if (encap_idx != 0) 5378 memcpy(ext_actions, actions, sizeof(*ext_actions) * encap_idx); 5379 if (encap_idx == actions_n - 1) { 5380 ext_actions[actions_n - 1] = (struct rte_flow_action){ 5381 .type = (enum rte_flow_action_type) 5382 MLX5_RTE_FLOW_ACTION_TYPE_COPY_MREG, 5383 .conf = cp_mreg, 5384 }; 5385 ext_actions[actions_n] = (struct rte_flow_action){ 5386 .type = RTE_FLOW_ACTION_TYPE_END, 5387 }; 5388 } else { 5389 ext_actions[encap_idx] = (struct rte_flow_action){ 5390 .type = (enum rte_flow_action_type) 5391 MLX5_RTE_FLOW_ACTION_TYPE_COPY_MREG, 5392 .conf = cp_mreg, 5393 }; 5394 memcpy(ext_actions + encap_idx + 1, actions + encap_idx, 5395 sizeof(*ext_actions) * (actions_n - encap_idx)); 5396 } 5397 return 0; 5398 } 5399 5400 /** 5401 * Check the match action from the action list. 5402 * 5403 * @param[in] actions 5404 * Pointer to the list of actions. 5405 * @param[in] attr 5406 * Flow rule attributes. 5407 * @param[in] action 5408 * The action to be check if exist. 5409 * @param[out] match_action_pos 5410 * Pointer to the position of the matched action if exists, otherwise is -1. 5411 * @param[out] qrss_action_pos 5412 * Pointer to the position of the Queue/RSS action if exists, otherwise is -1. 5413 * @param[out] modify_after_mirror 5414 * Pointer to the flag of modify action after FDB mirroring. 5415 * 5416 * @return 5417 * > 0 the total number of actions. 5418 * 0 if not found match action in action list. 5419 */ 5420 static int 5421 flow_check_match_action(const struct rte_flow_action actions[], 5422 const struct rte_flow_attr *attr, 5423 enum rte_flow_action_type action, 5424 int *match_action_pos, int *qrss_action_pos, 5425 int *modify_after_mirror) 5426 { 5427 const struct rte_flow_action_sample *sample; 5428 const struct rte_flow_action_raw_decap *decap; 5429 int actions_n = 0; 5430 uint32_t ratio = 0; 5431 int sub_type = 0; 5432 int flag = 0; 5433 int fdb_mirror = 0; 5434 5435 *match_action_pos = -1; 5436 *qrss_action_pos = -1; 5437 for (; actions->type != RTE_FLOW_ACTION_TYPE_END; actions++) { 5438 if (actions->type == action) { 5439 flag = 1; 5440 *match_action_pos = actions_n; 5441 } 5442 switch (actions->type) { 5443 case RTE_FLOW_ACTION_TYPE_QUEUE: 5444 case RTE_FLOW_ACTION_TYPE_RSS: 5445 *qrss_action_pos = actions_n; 5446 break; 5447 case RTE_FLOW_ACTION_TYPE_SAMPLE: 5448 sample = actions->conf; 5449 ratio = sample->ratio; 5450 sub_type = ((const struct rte_flow_action *) 5451 (sample->actions))->type; 5452 if (ratio == 1 && attr->transfer) 5453 fdb_mirror = 1; 5454 break; 5455 case RTE_FLOW_ACTION_TYPE_SET_MAC_SRC: 5456 case RTE_FLOW_ACTION_TYPE_SET_MAC_DST: 5457 case RTE_FLOW_ACTION_TYPE_SET_IPV4_SRC: 5458 case RTE_FLOW_ACTION_TYPE_SET_IPV4_DST: 5459 case RTE_FLOW_ACTION_TYPE_SET_IPV6_SRC: 5460 case RTE_FLOW_ACTION_TYPE_SET_IPV6_DST: 5461 case RTE_FLOW_ACTION_TYPE_SET_TP_SRC: 5462 case RTE_FLOW_ACTION_TYPE_SET_TP_DST: 5463 case RTE_FLOW_ACTION_TYPE_DEC_TTL: 5464 case RTE_FLOW_ACTION_TYPE_SET_TTL: 5465 case RTE_FLOW_ACTION_TYPE_INC_TCP_SEQ: 5466 case RTE_FLOW_ACTION_TYPE_DEC_TCP_SEQ: 5467 case RTE_FLOW_ACTION_TYPE_INC_TCP_ACK: 5468 case RTE_FLOW_ACTION_TYPE_DEC_TCP_ACK: 5469 case RTE_FLOW_ACTION_TYPE_SET_IPV4_DSCP: 5470 case RTE_FLOW_ACTION_TYPE_SET_IPV6_DSCP: 5471 case RTE_FLOW_ACTION_TYPE_FLAG: 5472 case RTE_FLOW_ACTION_TYPE_MARK: 5473 case RTE_FLOW_ACTION_TYPE_SET_META: 5474 case RTE_FLOW_ACTION_TYPE_SET_TAG: 5475 case RTE_FLOW_ACTION_TYPE_OF_POP_VLAN: 5476 case RTE_FLOW_ACTION_TYPE_OF_PUSH_VLAN: 5477 case RTE_FLOW_ACTION_TYPE_OF_SET_VLAN_VID: 5478 case RTE_FLOW_ACTION_TYPE_OF_SET_VLAN_PCP: 5479 case RTE_FLOW_ACTION_TYPE_VXLAN_DECAP: 5480 case RTE_FLOW_ACTION_TYPE_NVGRE_DECAP: 5481 case RTE_FLOW_ACTION_TYPE_MODIFY_FIELD: 5482 case RTE_FLOW_ACTION_TYPE_METER: 5483 if (fdb_mirror) 5484 *modify_after_mirror = 1; 5485 break; 5486 case RTE_FLOW_ACTION_TYPE_RAW_DECAP: 5487 decap = actions->conf; 5488 while ((++actions)->type == RTE_FLOW_ACTION_TYPE_VOID) 5489 ; 5490 actions_n++; 5491 if (actions->type == RTE_FLOW_ACTION_TYPE_RAW_ENCAP) { 5492 const struct rte_flow_action_raw_encap *encap = 5493 actions->conf; 5494 if (decap->size <= 5495 MLX5_ENCAPSULATION_DECISION_SIZE && 5496 encap->size > 5497 MLX5_ENCAPSULATION_DECISION_SIZE) 5498 /* L3 encap. */ 5499 break; 5500 } 5501 if (fdb_mirror) 5502 *modify_after_mirror = 1; 5503 break; 5504 default: 5505 break; 5506 } 5507 actions_n++; 5508 } 5509 if (flag && fdb_mirror && !*modify_after_mirror) { 5510 /* FDB mirroring uses the destination array to implement 5511 * instead of FLOW_SAMPLER object. 5512 */ 5513 if (sub_type != RTE_FLOW_ACTION_TYPE_END) 5514 flag = 0; 5515 } 5516 /* Count RTE_FLOW_ACTION_TYPE_END. */ 5517 return flag ? actions_n + 1 : 0; 5518 } 5519 5520 #define SAMPLE_SUFFIX_ITEM 2 5521 5522 /** 5523 * Split the sample flow. 5524 * 5525 * As sample flow will split to two sub flow, sample flow with 5526 * sample action, the other actions will move to new suffix flow. 5527 * 5528 * Also add unique tag id with tag action in the sample flow, 5529 * the same tag id will be as match in the suffix flow. 5530 * 5531 * @param dev 5532 * Pointer to Ethernet device. 5533 * @param[in] add_tag 5534 * Add extra tag action flag. 5535 * @param[out] sfx_items 5536 * Suffix flow match items (list terminated by the END pattern item). 5537 * @param[in] actions 5538 * Associated actions (list terminated by the END action). 5539 * @param[out] actions_sfx 5540 * Suffix flow actions. 5541 * @param[out] actions_pre 5542 * Prefix flow actions. 5543 * @param[in] actions_n 5544 * The total number of actions. 5545 * @param[in] sample_action_pos 5546 * The sample action position. 5547 * @param[in] qrss_action_pos 5548 * The Queue/RSS action position. 5549 * @param[in] jump_table 5550 * Add extra jump action flag. 5551 * @param[out] error 5552 * Perform verbose error reporting if not NULL. 5553 * 5554 * @return 5555 * 0 on success, or unique flow_id, a negative errno value 5556 * otherwise and rte_errno is set. 5557 */ 5558 static int 5559 flow_sample_split_prep(struct rte_eth_dev *dev, 5560 int add_tag, 5561 struct rte_flow_item sfx_items[], 5562 const struct rte_flow_action actions[], 5563 struct rte_flow_action actions_sfx[], 5564 struct rte_flow_action actions_pre[], 5565 int actions_n, 5566 int sample_action_pos, 5567 int qrss_action_pos, 5568 int jump_table, 5569 struct rte_flow_error *error) 5570 { 5571 struct mlx5_priv *priv = dev->data->dev_private; 5572 struct mlx5_rte_flow_action_set_tag *set_tag; 5573 struct mlx5_rte_flow_item_tag *tag_spec; 5574 struct mlx5_rte_flow_item_tag *tag_mask; 5575 struct rte_flow_action_jump *jump_action; 5576 uint32_t tag_id = 0; 5577 int index; 5578 int append_index = 0; 5579 int ret; 5580 5581 if (sample_action_pos < 0) 5582 return rte_flow_error_set(error, EINVAL, 5583 RTE_FLOW_ERROR_TYPE_ACTION, 5584 NULL, "invalid position of sample " 5585 "action in list"); 5586 /* Prepare the actions for prefix and suffix flow. */ 5587 if (qrss_action_pos >= 0 && qrss_action_pos < sample_action_pos) { 5588 index = qrss_action_pos; 5589 /* Put the preceding the Queue/RSS action into prefix flow. */ 5590 if (index != 0) 5591 memcpy(actions_pre, actions, 5592 sizeof(struct rte_flow_action) * index); 5593 /* Put others preceding the sample action into prefix flow. */ 5594 if (sample_action_pos > index + 1) 5595 memcpy(actions_pre + index, actions + index + 1, 5596 sizeof(struct rte_flow_action) * 5597 (sample_action_pos - index - 1)); 5598 index = sample_action_pos - 1; 5599 /* Put Queue/RSS action into Suffix flow. */ 5600 memcpy(actions_sfx, actions + qrss_action_pos, 5601 sizeof(struct rte_flow_action)); 5602 actions_sfx++; 5603 } else { 5604 index = sample_action_pos; 5605 if (index != 0) 5606 memcpy(actions_pre, actions, 5607 sizeof(struct rte_flow_action) * index); 5608 } 5609 /* For CX5, add an extra tag action for NIC-RX and E-Switch ingress. 5610 * For CX6DX and above, metadata registers Cx preserve their value, 5611 * add an extra tag action for NIC-RX and E-Switch Domain. 5612 */ 5613 if (add_tag) { 5614 /* Prepare the prefix tag action. */ 5615 append_index++; 5616 set_tag = (void *)(actions_pre + actions_n + append_index); 5617 ret = mlx5_flow_get_reg_id(dev, MLX5_SAMPLE_ID, 0, error); 5618 if (ret < 0) 5619 return ret; 5620 mlx5_ipool_malloc(priv->sh->ipool 5621 [MLX5_IPOOL_RSS_EXPANTION_FLOW_ID], &tag_id); 5622 *set_tag = (struct mlx5_rte_flow_action_set_tag) { 5623 .id = ret, 5624 .data = tag_id, 5625 }; 5626 /* Prepare the suffix subflow items. */ 5627 tag_spec = (void *)(sfx_items + SAMPLE_SUFFIX_ITEM); 5628 tag_spec->data = tag_id; 5629 tag_spec->id = set_tag->id; 5630 tag_mask = tag_spec + 1; 5631 tag_mask->data = UINT32_MAX; 5632 sfx_items[0] = (struct rte_flow_item){ 5633 .type = (enum rte_flow_item_type) 5634 MLX5_RTE_FLOW_ITEM_TYPE_TAG, 5635 .spec = tag_spec, 5636 .last = NULL, 5637 .mask = tag_mask, 5638 }; 5639 sfx_items[1] = (struct rte_flow_item){ 5640 .type = (enum rte_flow_item_type) 5641 RTE_FLOW_ITEM_TYPE_END, 5642 }; 5643 /* Prepare the tag action in prefix subflow. */ 5644 actions_pre[index++] = 5645 (struct rte_flow_action){ 5646 .type = (enum rte_flow_action_type) 5647 MLX5_RTE_FLOW_ACTION_TYPE_TAG, 5648 .conf = set_tag, 5649 }; 5650 } 5651 memcpy(actions_pre + index, actions + sample_action_pos, 5652 sizeof(struct rte_flow_action)); 5653 index += 1; 5654 /* For the modify action after the sample action in E-Switch mirroring, 5655 * Add the extra jump action in prefix subflow and jump into the next 5656 * table, then do the modify action in the new table. 5657 */ 5658 if (jump_table) { 5659 /* Prepare the prefix jump action. */ 5660 append_index++; 5661 jump_action = (void *)(actions_pre + actions_n + append_index); 5662 jump_action->group = jump_table; 5663 actions_pre[index++] = 5664 (struct rte_flow_action){ 5665 .type = (enum rte_flow_action_type) 5666 RTE_FLOW_ACTION_TYPE_JUMP, 5667 .conf = jump_action, 5668 }; 5669 } 5670 actions_pre[index] = (struct rte_flow_action){ 5671 .type = (enum rte_flow_action_type) 5672 RTE_FLOW_ACTION_TYPE_END, 5673 }; 5674 /* Put the actions after sample into Suffix flow. */ 5675 memcpy(actions_sfx, actions + sample_action_pos + 1, 5676 sizeof(struct rte_flow_action) * 5677 (actions_n - sample_action_pos - 1)); 5678 return tag_id; 5679 } 5680 5681 /** 5682 * The splitting for metadata feature. 5683 * 5684 * - Q/RSS action on NIC Rx should be split in order to pass by 5685 * the mreg copy table (RX_CP_TBL) and then it jumps to the 5686 * action table (RX_ACT_TBL) which has the split Q/RSS action. 5687 * 5688 * - All the actions on NIC Tx should have a mreg copy action to 5689 * copy reg_a from WQE to reg_c[0]. 5690 * 5691 * @param dev 5692 * Pointer to Ethernet device. 5693 * @param[in] flow 5694 * Parent flow structure pointer. 5695 * @param[in] attr 5696 * Flow rule attributes. 5697 * @param[in] items 5698 * Pattern specification (list terminated by the END pattern item). 5699 * @param[in] actions 5700 * Associated actions (list terminated by the END action). 5701 * @param[in] flow_split_info 5702 * Pointer to flow split info structure. 5703 * @param[out] error 5704 * Perform verbose error reporting if not NULL. 5705 * @return 5706 * 0 on success, negative value otherwise 5707 */ 5708 static int 5709 flow_create_split_metadata(struct rte_eth_dev *dev, 5710 struct rte_flow *flow, 5711 const struct rte_flow_attr *attr, 5712 const struct rte_flow_item items[], 5713 const struct rte_flow_action actions[], 5714 struct mlx5_flow_split_info *flow_split_info, 5715 struct rte_flow_error *error) 5716 { 5717 struct mlx5_priv *priv = dev->data->dev_private; 5718 struct mlx5_dev_config *config = &priv->config; 5719 const struct rte_flow_action *qrss = NULL; 5720 struct rte_flow_action *ext_actions = NULL; 5721 struct mlx5_flow *dev_flow = NULL; 5722 uint32_t qrss_id = 0; 5723 int mtr_sfx = 0; 5724 size_t act_size; 5725 int actions_n; 5726 int encap_idx; 5727 int ret; 5728 5729 /* Check whether extensive metadata feature is engaged. */ 5730 if (!config->dv_flow_en || 5731 config->dv_xmeta_en == MLX5_XMETA_MODE_LEGACY || 5732 !mlx5_flow_ext_mreg_supported(dev)) 5733 return flow_create_split_inner(dev, flow, NULL, attr, items, 5734 actions, flow_split_info, error); 5735 actions_n = flow_parse_metadata_split_actions_info(actions, &qrss, 5736 &encap_idx); 5737 if (qrss) { 5738 /* Exclude hairpin flows from splitting. */ 5739 if (qrss->type == RTE_FLOW_ACTION_TYPE_QUEUE) { 5740 const struct rte_flow_action_queue *queue; 5741 5742 queue = qrss->conf; 5743 if (mlx5_rxq_get_type(dev, queue->index) == 5744 MLX5_RXQ_TYPE_HAIRPIN) 5745 qrss = NULL; 5746 } else if (qrss->type == RTE_FLOW_ACTION_TYPE_RSS) { 5747 const struct rte_flow_action_rss *rss; 5748 5749 rss = qrss->conf; 5750 if (mlx5_rxq_get_type(dev, rss->queue[0]) == 5751 MLX5_RXQ_TYPE_HAIRPIN) 5752 qrss = NULL; 5753 } 5754 } 5755 if (qrss) { 5756 /* Check if it is in meter suffix table. */ 5757 mtr_sfx = attr->group == (attr->transfer ? 5758 (MLX5_FLOW_TABLE_LEVEL_METER - 1) : 5759 MLX5_FLOW_TABLE_LEVEL_METER); 5760 /* 5761 * Q/RSS action on NIC Rx should be split in order to pass by 5762 * the mreg copy table (RX_CP_TBL) and then it jumps to the 5763 * action table (RX_ACT_TBL) which has the split Q/RSS action. 5764 */ 5765 act_size = sizeof(struct rte_flow_action) * (actions_n + 1) + 5766 sizeof(struct rte_flow_action_set_tag) + 5767 sizeof(struct rte_flow_action_jump); 5768 ext_actions = mlx5_malloc(MLX5_MEM_ZERO, act_size, 0, 5769 SOCKET_ID_ANY); 5770 if (!ext_actions) 5771 return rte_flow_error_set(error, ENOMEM, 5772 RTE_FLOW_ERROR_TYPE_ACTION, 5773 NULL, "no memory to split " 5774 "metadata flow"); 5775 /* 5776 * If we are the suffix flow of meter, tag already exist. 5777 * Set the tag action to void. 5778 */ 5779 if (mtr_sfx) 5780 ext_actions[qrss - actions].type = 5781 RTE_FLOW_ACTION_TYPE_VOID; 5782 else 5783 ext_actions[qrss - actions].type = 5784 (enum rte_flow_action_type) 5785 MLX5_RTE_FLOW_ACTION_TYPE_TAG; 5786 /* 5787 * Create the new actions list with removed Q/RSS action 5788 * and appended set tag and jump to register copy table 5789 * (RX_CP_TBL). We should preallocate unique tag ID here 5790 * in advance, because it is needed for set tag action. 5791 */ 5792 qrss_id = flow_mreg_split_qrss_prep(dev, ext_actions, actions, 5793 qrss, actions_n, error); 5794 if (!mtr_sfx && !qrss_id) { 5795 ret = -rte_errno; 5796 goto exit; 5797 } 5798 } else if (attr->egress && !attr->transfer) { 5799 /* 5800 * All the actions on NIC Tx should have a metadata register 5801 * copy action to copy reg_a from WQE to reg_c[meta] 5802 */ 5803 act_size = sizeof(struct rte_flow_action) * (actions_n + 1) + 5804 sizeof(struct mlx5_flow_action_copy_mreg); 5805 ext_actions = mlx5_malloc(MLX5_MEM_ZERO, act_size, 0, 5806 SOCKET_ID_ANY); 5807 if (!ext_actions) 5808 return rte_flow_error_set(error, ENOMEM, 5809 RTE_FLOW_ERROR_TYPE_ACTION, 5810 NULL, "no memory to split " 5811 "metadata flow"); 5812 /* Create the action list appended with copy register. */ 5813 ret = flow_mreg_tx_copy_prep(dev, ext_actions, actions, 5814 actions_n, error, encap_idx); 5815 if (ret < 0) 5816 goto exit; 5817 } 5818 /* Add the unmodified original or prefix subflow. */ 5819 ret = flow_create_split_inner(dev, flow, &dev_flow, attr, 5820 items, ext_actions ? ext_actions : 5821 actions, flow_split_info, error); 5822 if (ret < 0) 5823 goto exit; 5824 MLX5_ASSERT(dev_flow); 5825 if (qrss) { 5826 const struct rte_flow_attr q_attr = { 5827 .group = MLX5_FLOW_MREG_ACT_TABLE_GROUP, 5828 .ingress = 1, 5829 }; 5830 /* Internal PMD action to set register. */ 5831 struct mlx5_rte_flow_item_tag q_tag_spec = { 5832 .data = qrss_id, 5833 .id = REG_NON, 5834 }; 5835 struct rte_flow_item q_items[] = { 5836 { 5837 .type = (enum rte_flow_item_type) 5838 MLX5_RTE_FLOW_ITEM_TYPE_TAG, 5839 .spec = &q_tag_spec, 5840 .last = NULL, 5841 .mask = NULL, 5842 }, 5843 { 5844 .type = RTE_FLOW_ITEM_TYPE_END, 5845 }, 5846 }; 5847 struct rte_flow_action q_actions[] = { 5848 { 5849 .type = qrss->type, 5850 .conf = qrss->conf, 5851 }, 5852 { 5853 .type = RTE_FLOW_ACTION_TYPE_END, 5854 }, 5855 }; 5856 uint64_t layers = flow_get_prefix_layer_flags(dev_flow); 5857 5858 /* 5859 * Configure the tag item only if there is no meter subflow. 5860 * Since tag is already marked in the meter suffix subflow 5861 * we can just use the meter suffix items as is. 5862 */ 5863 if (qrss_id) { 5864 /* Not meter subflow. */ 5865 MLX5_ASSERT(!mtr_sfx); 5866 /* 5867 * Put unique id in prefix flow due to it is destroyed 5868 * after suffix flow and id will be freed after there 5869 * is no actual flows with this id and identifier 5870 * reallocation becomes possible (for example, for 5871 * other flows in other threads). 5872 */ 5873 dev_flow->handle->split_flow_id = qrss_id; 5874 ret = mlx5_flow_get_reg_id(dev, MLX5_COPY_MARK, 0, 5875 error); 5876 if (ret < 0) 5877 goto exit; 5878 q_tag_spec.id = ret; 5879 } 5880 dev_flow = NULL; 5881 /* Add suffix subflow to execute Q/RSS. */ 5882 flow_split_info->prefix_layers = layers; 5883 flow_split_info->prefix_mark = 0; 5884 ret = flow_create_split_inner(dev, flow, &dev_flow, 5885 &q_attr, mtr_sfx ? items : 5886 q_items, q_actions, 5887 flow_split_info, error); 5888 if (ret < 0) 5889 goto exit; 5890 /* qrss ID should be freed if failed. */ 5891 qrss_id = 0; 5892 MLX5_ASSERT(dev_flow); 5893 } 5894 5895 exit: 5896 /* 5897 * We do not destroy the partially created sub_flows in case of error. 5898 * These ones are included into parent flow list and will be destroyed 5899 * by flow_drv_destroy. 5900 */ 5901 mlx5_ipool_free(priv->sh->ipool[MLX5_IPOOL_RSS_EXPANTION_FLOW_ID], 5902 qrss_id); 5903 mlx5_free(ext_actions); 5904 return ret; 5905 } 5906 5907 /** 5908 * Create meter internal drop flow with the original pattern. 5909 * 5910 * @param dev 5911 * Pointer to Ethernet device. 5912 * @param[in] flow 5913 * Parent flow structure pointer. 5914 * @param[in] attr 5915 * Flow rule attributes. 5916 * @param[in] items 5917 * Pattern specification (list terminated by the END pattern item). 5918 * @param[in] flow_split_info 5919 * Pointer to flow split info structure. 5920 * @param[in] fm 5921 * Pointer to flow meter structure. 5922 * @param[out] error 5923 * Perform verbose error reporting if not NULL. 5924 * @return 5925 * 0 on success, negative value otherwise 5926 */ 5927 static uint32_t 5928 flow_meter_create_drop_flow_with_org_pattern(struct rte_eth_dev *dev, 5929 struct rte_flow *flow, 5930 const struct rte_flow_attr *attr, 5931 const struct rte_flow_item items[], 5932 struct mlx5_flow_split_info *flow_split_info, 5933 struct mlx5_flow_meter_info *fm, 5934 struct rte_flow_error *error) 5935 { 5936 struct mlx5_flow *dev_flow = NULL; 5937 struct rte_flow_attr drop_attr = *attr; 5938 struct rte_flow_action drop_actions[3]; 5939 struct mlx5_flow_split_info drop_split_info = *flow_split_info; 5940 5941 MLX5_ASSERT(fm->drop_cnt); 5942 drop_actions[0].type = 5943 (enum rte_flow_action_type)MLX5_RTE_FLOW_ACTION_TYPE_COUNT; 5944 drop_actions[0].conf = (void *)(uintptr_t)fm->drop_cnt; 5945 drop_actions[1].type = RTE_FLOW_ACTION_TYPE_DROP; 5946 drop_actions[1].conf = NULL; 5947 drop_actions[2].type = RTE_FLOW_ACTION_TYPE_END; 5948 drop_actions[2].conf = NULL; 5949 drop_split_info.external = false; 5950 drop_split_info.skip_scale |= 1 << MLX5_SCALE_FLOW_GROUP_BIT; 5951 drop_split_info.table_id = MLX5_MTR_TABLE_ID_DROP; 5952 drop_attr.group = MLX5_FLOW_TABLE_LEVEL_METER; 5953 return flow_create_split_inner(dev, flow, &dev_flow, 5954 &drop_attr, items, drop_actions, 5955 &drop_split_info, error); 5956 } 5957 5958 /** 5959 * The splitting for meter feature. 5960 * 5961 * - The meter flow will be split to two flows as prefix and 5962 * suffix flow. The packets make sense only it pass the prefix 5963 * meter action. 5964 * 5965 * - Reg_C_5 is used for the packet to match betweend prefix and 5966 * suffix flow. 5967 * 5968 * @param dev 5969 * Pointer to Ethernet device. 5970 * @param[in] flow 5971 * Parent flow structure pointer. 5972 * @param[in] attr 5973 * Flow rule attributes. 5974 * @param[in] items 5975 * Pattern specification (list terminated by the END pattern item). 5976 * @param[in] actions 5977 * Associated actions (list terminated by the END action). 5978 * @param[in] flow_split_info 5979 * Pointer to flow split info structure. 5980 * @param[out] error 5981 * Perform verbose error reporting if not NULL. 5982 * @return 5983 * 0 on success, negative value otherwise 5984 */ 5985 static int 5986 flow_create_split_meter(struct rte_eth_dev *dev, 5987 struct rte_flow *flow, 5988 const struct rte_flow_attr *attr, 5989 const struct rte_flow_item items[], 5990 const struct rte_flow_action actions[], 5991 struct mlx5_flow_split_info *flow_split_info, 5992 struct rte_flow_error *error) 5993 { 5994 struct mlx5_priv *priv = dev->data->dev_private; 5995 struct mlx5_flow_workspace *wks = mlx5_flow_get_thread_workspace(); 5996 struct rte_flow_action *sfx_actions = NULL; 5997 struct rte_flow_action *pre_actions = NULL; 5998 struct rte_flow_item *sfx_items = NULL; 5999 struct mlx5_flow *dev_flow = NULL; 6000 struct rte_flow_attr sfx_attr = *attr; 6001 struct mlx5_flow_meter_info *fm = NULL; 6002 uint8_t skip_scale_restore; 6003 bool has_mtr = false; 6004 bool has_modify = false; 6005 bool set_mtr_reg = true; 6006 bool is_mtr_hierarchy = false; 6007 uint32_t meter_id = 0; 6008 uint32_t mtr_idx = 0; 6009 uint32_t mtr_flow_id = 0; 6010 size_t act_size; 6011 size_t item_size; 6012 int actions_n = 0; 6013 int ret = 0; 6014 6015 if (priv->mtr_en) 6016 actions_n = flow_check_meter_action(dev, actions, &has_mtr, 6017 &has_modify, &meter_id); 6018 if (has_mtr) { 6019 if (flow->meter) { 6020 fm = flow_dv_meter_find_by_idx(priv, flow->meter); 6021 if (!fm) 6022 return rte_flow_error_set(error, EINVAL, 6023 RTE_FLOW_ERROR_TYPE_UNSPECIFIED, 6024 NULL, "Meter not found."); 6025 } else { 6026 fm = mlx5_flow_meter_find(priv, meter_id, &mtr_idx); 6027 if (!fm) 6028 return rte_flow_error_set(error, EINVAL, 6029 RTE_FLOW_ERROR_TYPE_UNSPECIFIED, 6030 NULL, "Meter not found."); 6031 ret = mlx5_flow_meter_attach(priv, fm, 6032 &sfx_attr, error); 6033 if (ret) 6034 return -rte_errno; 6035 flow->meter = mtr_idx; 6036 } 6037 MLX5_ASSERT(wks); 6038 wks->fm = fm; 6039 if (!fm->def_policy) { 6040 wks->policy = mlx5_flow_meter_policy_find(dev, 6041 fm->policy_id, 6042 NULL); 6043 MLX5_ASSERT(wks->policy); 6044 if (wks->policy->is_hierarchy) { 6045 wks->final_policy = 6046 mlx5_flow_meter_hierarchy_get_final_policy(dev, 6047 wks->policy); 6048 if (!wks->final_policy) 6049 return rte_flow_error_set(error, 6050 EINVAL, 6051 RTE_FLOW_ERROR_TYPE_ACTION, NULL, 6052 "Failed to find terminal policy of hierarchy."); 6053 is_mtr_hierarchy = true; 6054 } 6055 } 6056 /* 6057 * If it isn't default-policy Meter, and 6058 * 1. There's no action in flow to change 6059 * packet (modify/encap/decap etc.), OR 6060 * 2. No drop count needed for this meter. 6061 * 3. It's not meter hierarchy. 6062 * Then no need to use regC to save meter id anymore. 6063 */ 6064 if (!fm->def_policy && !is_mtr_hierarchy && 6065 (!has_modify || !fm->drop_cnt)) 6066 set_mtr_reg = false; 6067 /* Prefix actions: meter, decap, encap, tag, jump, end. */ 6068 act_size = sizeof(struct rte_flow_action) * (actions_n + 6) + 6069 sizeof(struct mlx5_rte_flow_action_set_tag); 6070 /* Suffix items: tag, vlan, port id, end. */ 6071 #define METER_SUFFIX_ITEM 4 6072 item_size = sizeof(struct rte_flow_item) * METER_SUFFIX_ITEM + 6073 sizeof(struct mlx5_rte_flow_item_tag) * 2; 6074 sfx_actions = mlx5_malloc(MLX5_MEM_ZERO, (act_size + item_size), 6075 0, SOCKET_ID_ANY); 6076 if (!sfx_actions) 6077 return rte_flow_error_set(error, ENOMEM, 6078 RTE_FLOW_ERROR_TYPE_ACTION, 6079 NULL, "no memory to split " 6080 "meter flow"); 6081 sfx_items = (struct rte_flow_item *)((char *)sfx_actions + 6082 act_size); 6083 /* There's no suffix flow for meter of non-default policy. */ 6084 if (!fm->def_policy) 6085 pre_actions = sfx_actions + 1; 6086 else 6087 pre_actions = sfx_actions + actions_n; 6088 ret = flow_meter_split_prep(dev, flow, wks, &sfx_attr, 6089 items, sfx_items, actions, 6090 sfx_actions, pre_actions, 6091 (set_mtr_reg ? &mtr_flow_id : NULL), 6092 error); 6093 if (ret) { 6094 ret = -rte_errno; 6095 goto exit; 6096 } 6097 /* Add the prefix subflow. */ 6098 flow_split_info->prefix_mark = 0; 6099 skip_scale_restore = flow_split_info->skip_scale; 6100 flow_split_info->skip_scale |= 6101 1 << MLX5_SCALE_JUMP_FLOW_GROUP_BIT; 6102 ret = flow_create_split_inner(dev, flow, &dev_flow, 6103 attr, items, pre_actions, 6104 flow_split_info, error); 6105 flow_split_info->skip_scale = skip_scale_restore; 6106 if (ret) { 6107 if (mtr_flow_id) 6108 mlx5_ipool_free(fm->flow_ipool, mtr_flow_id); 6109 ret = -rte_errno; 6110 goto exit; 6111 } 6112 if (mtr_flow_id) { 6113 dev_flow->handle->split_flow_id = mtr_flow_id; 6114 dev_flow->handle->is_meter_flow_id = 1; 6115 } 6116 if (!fm->def_policy) { 6117 if (!set_mtr_reg && fm->drop_cnt) 6118 ret = 6119 flow_meter_create_drop_flow_with_org_pattern(dev, flow, 6120 &sfx_attr, items, 6121 flow_split_info, 6122 fm, error); 6123 goto exit; 6124 } 6125 /* Setting the sfx group atrr. */ 6126 sfx_attr.group = sfx_attr.transfer ? 6127 (MLX5_FLOW_TABLE_LEVEL_METER - 1) : 6128 MLX5_FLOW_TABLE_LEVEL_METER; 6129 flow_split_info->prefix_layers = 6130 flow_get_prefix_layer_flags(dev_flow); 6131 flow_split_info->prefix_mark = dev_flow->handle->mark; 6132 flow_split_info->table_id = MLX5_MTR_TABLE_ID_SUFFIX; 6133 } 6134 /* Add the prefix subflow. */ 6135 ret = flow_create_split_metadata(dev, flow, 6136 &sfx_attr, sfx_items ? 6137 sfx_items : items, 6138 sfx_actions ? sfx_actions : actions, 6139 flow_split_info, error); 6140 exit: 6141 if (sfx_actions) 6142 mlx5_free(sfx_actions); 6143 return ret; 6144 } 6145 6146 /** 6147 * The splitting for sample feature. 6148 * 6149 * Once Sample action is detected in the action list, the flow actions should 6150 * be split into prefix sub flow and suffix sub flow. 6151 * 6152 * The original items remain in the prefix sub flow, all actions preceding the 6153 * sample action and the sample action itself will be copied to the prefix 6154 * sub flow, the actions following the sample action will be copied to the 6155 * suffix sub flow, Queue action always be located in the suffix sub flow. 6156 * 6157 * In order to make the packet from prefix sub flow matches with suffix sub 6158 * flow, an extra tag action be added into prefix sub flow, and the suffix sub 6159 * flow uses tag item with the unique flow id. 6160 * 6161 * @param dev 6162 * Pointer to Ethernet device. 6163 * @param[in] flow 6164 * Parent flow structure pointer. 6165 * @param[in] attr 6166 * Flow rule attributes. 6167 * @param[in] items 6168 * Pattern specification (list terminated by the END pattern item). 6169 * @param[in] actions 6170 * Associated actions (list terminated by the END action). 6171 * @param[in] flow_split_info 6172 * Pointer to flow split info structure. 6173 * @param[out] error 6174 * Perform verbose error reporting if not NULL. 6175 * @return 6176 * 0 on success, negative value otherwise 6177 */ 6178 static int 6179 flow_create_split_sample(struct rte_eth_dev *dev, 6180 struct rte_flow *flow, 6181 const struct rte_flow_attr *attr, 6182 const struct rte_flow_item items[], 6183 const struct rte_flow_action actions[], 6184 struct mlx5_flow_split_info *flow_split_info, 6185 struct rte_flow_error *error) 6186 { 6187 struct mlx5_priv *priv = dev->data->dev_private; 6188 struct rte_flow_action *sfx_actions = NULL; 6189 struct rte_flow_action *pre_actions = NULL; 6190 struct rte_flow_item *sfx_items = NULL; 6191 struct mlx5_flow *dev_flow = NULL; 6192 struct rte_flow_attr sfx_attr = *attr; 6193 #ifdef HAVE_IBV_FLOW_DV_SUPPORT 6194 struct mlx5_flow_dv_sample_resource *sample_res; 6195 struct mlx5_flow_tbl_data_entry *sfx_tbl_data; 6196 struct mlx5_flow_tbl_resource *sfx_tbl; 6197 #endif 6198 size_t act_size; 6199 size_t item_size; 6200 uint32_t fdb_tx = 0; 6201 int32_t tag_id = 0; 6202 int actions_n = 0; 6203 int sample_action_pos; 6204 int qrss_action_pos; 6205 int add_tag = 0; 6206 int modify_after_mirror = 0; 6207 uint16_t jump_table = 0; 6208 const uint32_t next_ft_step = 1; 6209 int ret = 0; 6210 6211 if (priv->sampler_en) 6212 actions_n = flow_check_match_action(actions, attr, 6213 RTE_FLOW_ACTION_TYPE_SAMPLE, 6214 &sample_action_pos, &qrss_action_pos, 6215 &modify_after_mirror); 6216 if (actions_n) { 6217 /* The prefix actions must includes sample, tag, end. */ 6218 act_size = sizeof(struct rte_flow_action) * (actions_n * 2 + 1) 6219 + sizeof(struct mlx5_rte_flow_action_set_tag); 6220 item_size = sizeof(struct rte_flow_item) * SAMPLE_SUFFIX_ITEM + 6221 sizeof(struct mlx5_rte_flow_item_tag) * 2; 6222 sfx_actions = mlx5_malloc(MLX5_MEM_ZERO, (act_size + 6223 item_size), 0, SOCKET_ID_ANY); 6224 if (!sfx_actions) 6225 return rte_flow_error_set(error, ENOMEM, 6226 RTE_FLOW_ERROR_TYPE_ACTION, 6227 NULL, "no memory to split " 6228 "sample flow"); 6229 /* The representor_id is UINT16_MAX for uplink. */ 6230 fdb_tx = (attr->transfer && priv->representor_id != UINT16_MAX); 6231 /* 6232 * When reg_c_preserve is set, metadata registers Cx preserve 6233 * their value even through packet duplication. 6234 */ 6235 add_tag = (!fdb_tx || priv->config.hca_attr.reg_c_preserve); 6236 if (add_tag) 6237 sfx_items = (struct rte_flow_item *)((char *)sfx_actions 6238 + act_size); 6239 if (modify_after_mirror) 6240 jump_table = attr->group * MLX5_FLOW_TABLE_FACTOR + 6241 next_ft_step; 6242 pre_actions = sfx_actions + actions_n; 6243 tag_id = flow_sample_split_prep(dev, add_tag, sfx_items, 6244 actions, sfx_actions, 6245 pre_actions, actions_n, 6246 sample_action_pos, 6247 qrss_action_pos, jump_table, 6248 error); 6249 if (tag_id < 0 || (add_tag && !tag_id)) { 6250 ret = -rte_errno; 6251 goto exit; 6252 } 6253 if (modify_after_mirror) 6254 flow_split_info->skip_scale = 6255 1 << MLX5_SCALE_JUMP_FLOW_GROUP_BIT; 6256 /* Add the prefix subflow. */ 6257 ret = flow_create_split_inner(dev, flow, &dev_flow, attr, 6258 items, pre_actions, 6259 flow_split_info, error); 6260 if (ret) { 6261 ret = -rte_errno; 6262 goto exit; 6263 } 6264 dev_flow->handle->split_flow_id = tag_id; 6265 #ifdef HAVE_IBV_FLOW_DV_SUPPORT 6266 if (!modify_after_mirror) { 6267 /* Set the sfx group attr. */ 6268 sample_res = (struct mlx5_flow_dv_sample_resource *) 6269 dev_flow->dv.sample_res; 6270 sfx_tbl = (struct mlx5_flow_tbl_resource *) 6271 sample_res->normal_path_tbl; 6272 sfx_tbl_data = container_of(sfx_tbl, 6273 struct mlx5_flow_tbl_data_entry, 6274 tbl); 6275 sfx_attr.group = sfx_attr.transfer ? 6276 (sfx_tbl_data->level - 1) : sfx_tbl_data->level; 6277 } else { 6278 MLX5_ASSERT(attr->transfer); 6279 sfx_attr.group = jump_table; 6280 } 6281 flow_split_info->prefix_layers = 6282 flow_get_prefix_layer_flags(dev_flow); 6283 flow_split_info->prefix_mark = dev_flow->handle->mark; 6284 /* Suffix group level already be scaled with factor, set 6285 * MLX5_SCALE_FLOW_GROUP_BIT of skip_scale to 1 to avoid scale 6286 * again in translation. 6287 */ 6288 flow_split_info->skip_scale = 1 << MLX5_SCALE_FLOW_GROUP_BIT; 6289 #endif 6290 } 6291 /* Add the suffix subflow. */ 6292 ret = flow_create_split_meter(dev, flow, &sfx_attr, 6293 sfx_items ? sfx_items : items, 6294 sfx_actions ? sfx_actions : actions, 6295 flow_split_info, error); 6296 exit: 6297 if (sfx_actions) 6298 mlx5_free(sfx_actions); 6299 return ret; 6300 } 6301 6302 /** 6303 * Split the flow to subflow set. The splitters might be linked 6304 * in the chain, like this: 6305 * flow_create_split_outer() calls: 6306 * flow_create_split_meter() calls: 6307 * flow_create_split_metadata(meter_subflow_0) calls: 6308 * flow_create_split_inner(metadata_subflow_0) 6309 * flow_create_split_inner(metadata_subflow_1) 6310 * flow_create_split_inner(metadata_subflow_2) 6311 * flow_create_split_metadata(meter_subflow_1) calls: 6312 * flow_create_split_inner(metadata_subflow_0) 6313 * flow_create_split_inner(metadata_subflow_1) 6314 * flow_create_split_inner(metadata_subflow_2) 6315 * 6316 * This provide flexible way to add new levels of flow splitting. 6317 * The all of successfully created subflows are included to the 6318 * parent flow dev_flow list. 6319 * 6320 * @param dev 6321 * Pointer to Ethernet device. 6322 * @param[in] flow 6323 * Parent flow structure pointer. 6324 * @param[in] attr 6325 * Flow rule attributes. 6326 * @param[in] items 6327 * Pattern specification (list terminated by the END pattern item). 6328 * @param[in] actions 6329 * Associated actions (list terminated by the END action). 6330 * @param[in] flow_split_info 6331 * Pointer to flow split info structure. 6332 * @param[out] error 6333 * Perform verbose error reporting if not NULL. 6334 * @return 6335 * 0 on success, negative value otherwise 6336 */ 6337 static int 6338 flow_create_split_outer(struct rte_eth_dev *dev, 6339 struct rte_flow *flow, 6340 const struct rte_flow_attr *attr, 6341 const struct rte_flow_item items[], 6342 const struct rte_flow_action actions[], 6343 struct mlx5_flow_split_info *flow_split_info, 6344 struct rte_flow_error *error) 6345 { 6346 int ret; 6347 6348 ret = flow_create_split_sample(dev, flow, attr, items, 6349 actions, flow_split_info, error); 6350 MLX5_ASSERT(ret <= 0); 6351 return ret; 6352 } 6353 6354 static inline struct mlx5_flow_tunnel * 6355 flow_tunnel_from_rule(const struct mlx5_flow *flow) 6356 { 6357 struct mlx5_flow_tunnel *tunnel; 6358 6359 #pragma GCC diagnostic push 6360 #pragma GCC diagnostic ignored "-Wcast-qual" 6361 tunnel = (typeof(tunnel))flow->tunnel; 6362 #pragma GCC diagnostic pop 6363 6364 return tunnel; 6365 } 6366 6367 /** 6368 * Adjust flow RSS workspace if needed. 6369 * 6370 * @param wks 6371 * Pointer to thread flow work space. 6372 * @param rss_desc 6373 * Pointer to RSS descriptor. 6374 * @param[in] nrssq_num 6375 * New RSS queue number. 6376 * 6377 * @return 6378 * 0 on success, -1 otherwise and rte_errno is set. 6379 */ 6380 static int 6381 flow_rss_workspace_adjust(struct mlx5_flow_workspace *wks, 6382 struct mlx5_flow_rss_desc *rss_desc, 6383 uint32_t nrssq_num) 6384 { 6385 if (likely(nrssq_num <= wks->rssq_num)) 6386 return 0; 6387 rss_desc->queue = realloc(rss_desc->queue, 6388 sizeof(*rss_desc->queue) * RTE_ALIGN(nrssq_num, 2)); 6389 if (!rss_desc->queue) { 6390 rte_errno = ENOMEM; 6391 return -1; 6392 } 6393 wks->rssq_num = RTE_ALIGN(nrssq_num, 2); 6394 return 0; 6395 } 6396 6397 /** 6398 * Create a flow and add it to @p list. 6399 * 6400 * @param dev 6401 * Pointer to Ethernet device. 6402 * @param list 6403 * Pointer to a TAILQ flow list. If this parameter NULL, 6404 * no list insertion occurred, flow is just created, 6405 * this is caller's responsibility to track the 6406 * created flow. 6407 * @param[in] attr 6408 * Flow rule attributes. 6409 * @param[in] items 6410 * Pattern specification (list terminated by the END pattern item). 6411 * @param[in] actions 6412 * Associated actions (list terminated by the END action). 6413 * @param[in] external 6414 * This flow rule is created by request external to PMD. 6415 * @param[out] error 6416 * Perform verbose error reporting if not NULL. 6417 * 6418 * @return 6419 * A flow index on success, 0 otherwise and rte_errno is set. 6420 */ 6421 static uint32_t 6422 flow_list_create(struct rte_eth_dev *dev, enum mlx5_flow_type type, 6423 const struct rte_flow_attr *attr, 6424 const struct rte_flow_item items[], 6425 const struct rte_flow_action original_actions[], 6426 bool external, struct rte_flow_error *error) 6427 { 6428 struct mlx5_priv *priv = dev->data->dev_private; 6429 struct rte_flow *flow = NULL; 6430 struct mlx5_flow *dev_flow; 6431 const struct rte_flow_action_rss *rss = NULL; 6432 struct mlx5_translated_action_handle 6433 indir_actions[MLX5_MAX_INDIRECT_ACTIONS]; 6434 int indir_actions_n = MLX5_MAX_INDIRECT_ACTIONS; 6435 union { 6436 struct mlx5_flow_expand_rss buf; 6437 uint8_t buffer[4096]; 6438 } expand_buffer; 6439 union { 6440 struct rte_flow_action actions[MLX5_MAX_SPLIT_ACTIONS]; 6441 uint8_t buffer[2048]; 6442 } actions_rx; 6443 union { 6444 struct rte_flow_action actions[MLX5_MAX_SPLIT_ACTIONS]; 6445 uint8_t buffer[2048]; 6446 } actions_hairpin_tx; 6447 union { 6448 struct rte_flow_item items[MLX5_MAX_SPLIT_ITEMS]; 6449 uint8_t buffer[2048]; 6450 } items_tx; 6451 struct mlx5_flow_expand_rss *buf = &expand_buffer.buf; 6452 struct mlx5_flow_rss_desc *rss_desc; 6453 const struct rte_flow_action *p_actions_rx; 6454 uint32_t i; 6455 uint32_t idx = 0; 6456 int hairpin_flow; 6457 struct rte_flow_attr attr_tx = { .priority = 0 }; 6458 const struct rte_flow_action *actions; 6459 struct rte_flow_action *translated_actions = NULL; 6460 struct mlx5_flow_tunnel *tunnel; 6461 struct tunnel_default_miss_ctx default_miss_ctx = { 0, }; 6462 struct mlx5_flow_workspace *wks = mlx5_flow_push_thread_workspace(); 6463 struct mlx5_flow_split_info flow_split_info = { 6464 .external = !!external, 6465 .skip_scale = 0, 6466 .flow_idx = 0, 6467 .prefix_mark = 0, 6468 .prefix_layers = 0, 6469 .table_id = 0 6470 }; 6471 int ret; 6472 6473 MLX5_ASSERT(wks); 6474 rss_desc = &wks->rss_desc; 6475 ret = flow_action_handles_translate(dev, original_actions, 6476 indir_actions, 6477 &indir_actions_n, 6478 &translated_actions, error); 6479 if (ret < 0) { 6480 MLX5_ASSERT(translated_actions == NULL); 6481 return 0; 6482 } 6483 actions = translated_actions ? translated_actions : original_actions; 6484 p_actions_rx = actions; 6485 hairpin_flow = flow_check_hairpin_split(dev, attr, actions); 6486 ret = flow_drv_validate(dev, attr, items, p_actions_rx, 6487 external, hairpin_flow, error); 6488 if (ret < 0) 6489 goto error_before_hairpin_split; 6490 flow = mlx5_ipool_zmalloc(priv->flows[type], &idx); 6491 if (!flow) { 6492 rte_errno = ENOMEM; 6493 goto error_before_hairpin_split; 6494 } 6495 if (hairpin_flow > 0) { 6496 if (hairpin_flow > MLX5_MAX_SPLIT_ACTIONS) { 6497 rte_errno = EINVAL; 6498 goto error_before_hairpin_split; 6499 } 6500 flow_hairpin_split(dev, actions, actions_rx.actions, 6501 actions_hairpin_tx.actions, items_tx.items, 6502 idx); 6503 p_actions_rx = actions_rx.actions; 6504 } 6505 flow_split_info.flow_idx = idx; 6506 flow->drv_type = flow_get_drv_type(dev, attr); 6507 MLX5_ASSERT(flow->drv_type > MLX5_FLOW_TYPE_MIN && 6508 flow->drv_type < MLX5_FLOW_TYPE_MAX); 6509 memset(rss_desc, 0, offsetof(struct mlx5_flow_rss_desc, queue)); 6510 /* RSS Action only works on NIC RX domain */ 6511 if (attr->ingress && !attr->transfer) 6512 rss = flow_get_rss_action(dev, p_actions_rx); 6513 if (rss) { 6514 if (flow_rss_workspace_adjust(wks, rss_desc, rss->queue_num)) 6515 return 0; 6516 /* 6517 * The following information is required by 6518 * mlx5_flow_hashfields_adjust() in advance. 6519 */ 6520 rss_desc->level = rss->level; 6521 /* RSS type 0 indicates default RSS type (RTE_ETH_RSS_IP). */ 6522 rss_desc->types = !rss->types ? RTE_ETH_RSS_IP : rss->types; 6523 } 6524 flow->dev_handles = 0; 6525 if (rss && rss->types) { 6526 unsigned int graph_root; 6527 6528 graph_root = find_graph_root(rss->level); 6529 ret = mlx5_flow_expand_rss(buf, sizeof(expand_buffer.buffer), 6530 items, rss->types, 6531 mlx5_support_expansion, graph_root); 6532 MLX5_ASSERT(ret > 0 && 6533 (unsigned int)ret < sizeof(expand_buffer.buffer)); 6534 if (rte_log_can_log(mlx5_logtype, RTE_LOG_DEBUG)) { 6535 for (i = 0; i < buf->entries; ++i) 6536 mlx5_dbg__print_pattern(buf->entry[i].pattern); 6537 } 6538 } else { 6539 buf->entries = 1; 6540 buf->entry[0].pattern = (void *)(uintptr_t)items; 6541 } 6542 rss_desc->shared_rss = flow_get_shared_rss_action(dev, indir_actions, 6543 indir_actions_n); 6544 for (i = 0; i < buf->entries; ++i) { 6545 /* Initialize flow split data. */ 6546 flow_split_info.prefix_layers = 0; 6547 flow_split_info.prefix_mark = 0; 6548 flow_split_info.skip_scale = 0; 6549 /* 6550 * The splitter may create multiple dev_flows, 6551 * depending on configuration. In the simplest 6552 * case it just creates unmodified original flow. 6553 */ 6554 ret = flow_create_split_outer(dev, flow, attr, 6555 buf->entry[i].pattern, 6556 p_actions_rx, &flow_split_info, 6557 error); 6558 if (ret < 0) 6559 goto error; 6560 if (is_flow_tunnel_steer_rule(wks->flows[0].tof_type)) { 6561 ret = flow_tunnel_add_default_miss(dev, flow, attr, 6562 p_actions_rx, 6563 idx, 6564 wks->flows[0].tunnel, 6565 &default_miss_ctx, 6566 error); 6567 if (ret < 0) { 6568 mlx5_free(default_miss_ctx.queue); 6569 goto error; 6570 } 6571 } 6572 } 6573 /* Create the tx flow. */ 6574 if (hairpin_flow) { 6575 attr_tx.group = MLX5_HAIRPIN_TX_TABLE; 6576 attr_tx.ingress = 0; 6577 attr_tx.egress = 1; 6578 dev_flow = flow_drv_prepare(dev, flow, &attr_tx, items_tx.items, 6579 actions_hairpin_tx.actions, 6580 idx, error); 6581 if (!dev_flow) 6582 goto error; 6583 dev_flow->flow = flow; 6584 dev_flow->external = 0; 6585 SILIST_INSERT(&flow->dev_handles, dev_flow->handle_idx, 6586 dev_flow->handle, next); 6587 ret = flow_drv_translate(dev, dev_flow, &attr_tx, 6588 items_tx.items, 6589 actions_hairpin_tx.actions, error); 6590 if (ret < 0) 6591 goto error; 6592 } 6593 /* 6594 * Update the metadata register copy table. If extensive 6595 * metadata feature is enabled and registers are supported 6596 * we might create the extra rte_flow for each unique 6597 * MARK/FLAG action ID. 6598 * 6599 * The table is updated for ingress Flows only, because 6600 * the egress Flows belong to the different device and 6601 * copy table should be updated in peer NIC Rx domain. 6602 */ 6603 if (attr->ingress && 6604 (external || attr->group != MLX5_FLOW_MREG_CP_TABLE_GROUP)) { 6605 ret = flow_mreg_update_copy_table(dev, flow, actions, error); 6606 if (ret) 6607 goto error; 6608 } 6609 /* 6610 * If the flow is external (from application) OR device is started, 6611 * OR mreg discover, then apply immediately. 6612 */ 6613 if (external || dev->data->dev_started || 6614 (attr->group == MLX5_FLOW_MREG_CP_TABLE_GROUP && 6615 attr->priority == MLX5_FLOW_LOWEST_PRIO_INDICATOR)) { 6616 ret = flow_drv_apply(dev, flow, error); 6617 if (ret < 0) 6618 goto error; 6619 } 6620 flow->type = type; 6621 flow_rxq_flags_set(dev, flow); 6622 rte_free(translated_actions); 6623 tunnel = flow_tunnel_from_rule(wks->flows); 6624 if (tunnel) { 6625 flow->tunnel = 1; 6626 flow->tunnel_id = tunnel->tunnel_id; 6627 __atomic_add_fetch(&tunnel->refctn, 1, __ATOMIC_RELAXED); 6628 mlx5_free(default_miss_ctx.queue); 6629 } 6630 mlx5_flow_pop_thread_workspace(); 6631 return idx; 6632 error: 6633 MLX5_ASSERT(flow); 6634 ret = rte_errno; /* Save rte_errno before cleanup. */ 6635 flow_mreg_del_copy_action(dev, flow); 6636 flow_drv_destroy(dev, flow); 6637 if (rss_desc->shared_rss) 6638 __atomic_sub_fetch(&((struct mlx5_shared_action_rss *) 6639 mlx5_ipool_get 6640 (priv->sh->ipool[MLX5_IPOOL_RSS_SHARED_ACTIONS], 6641 rss_desc->shared_rss))->refcnt, 1, __ATOMIC_RELAXED); 6642 mlx5_ipool_free(priv->flows[type], idx); 6643 rte_errno = ret; /* Restore rte_errno. */ 6644 ret = rte_errno; 6645 rte_errno = ret; 6646 mlx5_flow_pop_thread_workspace(); 6647 error_before_hairpin_split: 6648 rte_free(translated_actions); 6649 return 0; 6650 } 6651 6652 /** 6653 * Create a dedicated flow rule on e-switch table 0 (root table), to direct all 6654 * incoming packets to table 1. 6655 * 6656 * Other flow rules, requested for group n, will be created in 6657 * e-switch table n+1. 6658 * Jump action to e-switch group n will be created to group n+1. 6659 * 6660 * Used when working in switchdev mode, to utilise advantages of table 1 6661 * and above. 6662 * 6663 * @param dev 6664 * Pointer to Ethernet device. 6665 * 6666 * @return 6667 * Pointer to flow on success, NULL otherwise and rte_errno is set. 6668 */ 6669 struct rte_flow * 6670 mlx5_flow_create_esw_table_zero_flow(struct rte_eth_dev *dev) 6671 { 6672 const struct rte_flow_attr attr = { 6673 .group = 0, 6674 .priority = 0, 6675 .ingress = 1, 6676 .egress = 0, 6677 .transfer = 1, 6678 }; 6679 const struct rte_flow_item pattern = { 6680 .type = RTE_FLOW_ITEM_TYPE_END, 6681 }; 6682 struct rte_flow_action_jump jump = { 6683 .group = 1, 6684 }; 6685 const struct rte_flow_action actions[] = { 6686 { 6687 .type = RTE_FLOW_ACTION_TYPE_JUMP, 6688 .conf = &jump, 6689 }, 6690 { 6691 .type = RTE_FLOW_ACTION_TYPE_END, 6692 }, 6693 }; 6694 struct rte_flow_error error; 6695 6696 return (void *)(uintptr_t)flow_list_create(dev, MLX5_FLOW_TYPE_CTL, 6697 &attr, &pattern, 6698 actions, false, &error); 6699 } 6700 6701 /** 6702 * Create a dedicated flow rule on e-switch table 1, matches ESW manager 6703 * and sq number, directs all packets to peer vport. 6704 * 6705 * @param dev 6706 * Pointer to Ethernet device. 6707 * @param txq 6708 * Txq index. 6709 * 6710 * @return 6711 * Flow ID on success, 0 otherwise and rte_errno is set. 6712 */ 6713 uint32_t 6714 mlx5_flow_create_devx_sq_miss_flow(struct rte_eth_dev *dev, uint32_t txq) 6715 { 6716 struct rte_flow_attr attr = { 6717 .group = 0, 6718 .priority = MLX5_FLOW_LOWEST_PRIO_INDICATOR, 6719 .ingress = 1, 6720 .egress = 0, 6721 .transfer = 1, 6722 }; 6723 struct rte_flow_item_port_id port_spec = { 6724 .id = MLX5_PORT_ESW_MGR, 6725 }; 6726 struct mlx5_rte_flow_item_tx_queue txq_spec = { 6727 .queue = txq, 6728 }; 6729 struct rte_flow_item pattern[] = { 6730 { 6731 .type = RTE_FLOW_ITEM_TYPE_PORT_ID, 6732 .spec = &port_spec, 6733 }, 6734 { 6735 .type = (enum rte_flow_item_type) 6736 MLX5_RTE_FLOW_ITEM_TYPE_TX_QUEUE, 6737 .spec = &txq_spec, 6738 }, 6739 { 6740 .type = RTE_FLOW_ITEM_TYPE_END, 6741 }, 6742 }; 6743 struct rte_flow_action_jump jump = { 6744 .group = 1, 6745 }; 6746 struct rte_flow_action_port_id port = { 6747 .id = dev->data->port_id, 6748 }; 6749 struct rte_flow_action actions[] = { 6750 { 6751 .type = RTE_FLOW_ACTION_TYPE_JUMP, 6752 .conf = &jump, 6753 }, 6754 { 6755 .type = RTE_FLOW_ACTION_TYPE_END, 6756 }, 6757 }; 6758 struct rte_flow_error error; 6759 6760 /* 6761 * Creates group 0, highest priority jump flow. 6762 * Matches txq to bypass kernel packets. 6763 */ 6764 if (flow_list_create(dev, MLX5_FLOW_TYPE_CTL, &attr, pattern, actions, 6765 false, &error) == 0) 6766 return 0; 6767 /* Create group 1, lowest priority redirect flow for txq. */ 6768 attr.group = 1; 6769 actions[0].conf = &port; 6770 actions[0].type = RTE_FLOW_ACTION_TYPE_PORT_ID; 6771 return flow_list_create(dev, MLX5_FLOW_TYPE_CTL, &attr, pattern, 6772 actions, false, &error); 6773 } 6774 6775 /** 6776 * Validate a flow supported by the NIC. 6777 * 6778 * @see rte_flow_validate() 6779 * @see rte_flow_ops 6780 */ 6781 int 6782 mlx5_flow_validate(struct rte_eth_dev *dev, 6783 const struct rte_flow_attr *attr, 6784 const struct rte_flow_item items[], 6785 const struct rte_flow_action original_actions[], 6786 struct rte_flow_error *error) 6787 { 6788 int hairpin_flow; 6789 struct mlx5_translated_action_handle 6790 indir_actions[MLX5_MAX_INDIRECT_ACTIONS]; 6791 int indir_actions_n = MLX5_MAX_INDIRECT_ACTIONS; 6792 const struct rte_flow_action *actions; 6793 struct rte_flow_action *translated_actions = NULL; 6794 int ret = flow_action_handles_translate(dev, original_actions, 6795 indir_actions, 6796 &indir_actions_n, 6797 &translated_actions, error); 6798 6799 if (ret) 6800 return ret; 6801 actions = translated_actions ? translated_actions : original_actions; 6802 hairpin_flow = flow_check_hairpin_split(dev, attr, actions); 6803 ret = flow_drv_validate(dev, attr, items, actions, 6804 true, hairpin_flow, error); 6805 rte_free(translated_actions); 6806 return ret; 6807 } 6808 6809 /** 6810 * Create a flow. 6811 * 6812 * @see rte_flow_create() 6813 * @see rte_flow_ops 6814 */ 6815 struct rte_flow * 6816 mlx5_flow_create(struct rte_eth_dev *dev, 6817 const struct rte_flow_attr *attr, 6818 const struct rte_flow_item items[], 6819 const struct rte_flow_action actions[], 6820 struct rte_flow_error *error) 6821 { 6822 /* 6823 * If the device is not started yet, it is not allowed to created a 6824 * flow from application. PMD default flows and traffic control flows 6825 * are not affected. 6826 */ 6827 if (unlikely(!dev->data->dev_started)) { 6828 DRV_LOG(DEBUG, "port %u is not started when " 6829 "inserting a flow", dev->data->port_id); 6830 rte_flow_error_set(error, ENODEV, 6831 RTE_FLOW_ERROR_TYPE_UNSPECIFIED, 6832 NULL, 6833 "port not started"); 6834 return NULL; 6835 } 6836 6837 return (void *)(uintptr_t)flow_list_create(dev, MLX5_FLOW_TYPE_GEN, 6838 attr, items, actions, 6839 true, error); 6840 } 6841 6842 /** 6843 * Destroy a flow in a list. 6844 * 6845 * @param dev 6846 * Pointer to Ethernet device. 6847 * @param[in] flow_idx 6848 * Index of flow to destroy. 6849 */ 6850 static void 6851 flow_list_destroy(struct rte_eth_dev *dev, enum mlx5_flow_type type, 6852 uint32_t flow_idx) 6853 { 6854 struct mlx5_priv *priv = dev->data->dev_private; 6855 struct rte_flow *flow = mlx5_ipool_get(priv->flows[type], flow_idx); 6856 6857 if (!flow) 6858 return; 6859 MLX5_ASSERT(flow->type == type); 6860 /* 6861 * Update RX queue flags only if port is started, otherwise it is 6862 * already clean. 6863 */ 6864 if (dev->data->dev_started) 6865 flow_rxq_flags_trim(dev, flow); 6866 flow_drv_destroy(dev, flow); 6867 if (flow->tunnel) { 6868 struct mlx5_flow_tunnel *tunnel; 6869 6870 tunnel = mlx5_find_tunnel_id(dev, flow->tunnel_id); 6871 RTE_VERIFY(tunnel); 6872 if (!__atomic_sub_fetch(&tunnel->refctn, 1, __ATOMIC_RELAXED)) 6873 mlx5_flow_tunnel_free(dev, tunnel); 6874 } 6875 flow_mreg_del_copy_action(dev, flow); 6876 mlx5_ipool_free(priv->flows[type], flow_idx); 6877 } 6878 6879 /** 6880 * Destroy all flows. 6881 * 6882 * @param dev 6883 * Pointer to Ethernet device. 6884 * @param type 6885 * Flow type to be flushed. 6886 * @param active 6887 * If flushing is called avtively. 6888 */ 6889 void 6890 mlx5_flow_list_flush(struct rte_eth_dev *dev, enum mlx5_flow_type type, 6891 bool active) 6892 { 6893 struct mlx5_priv *priv = dev->data->dev_private; 6894 uint32_t num_flushed = 0, fidx = 1; 6895 struct rte_flow *flow; 6896 6897 MLX5_IPOOL_FOREACH(priv->flows[type], fidx, flow) { 6898 flow_list_destroy(dev, type, fidx); 6899 num_flushed++; 6900 } 6901 if (active) { 6902 DRV_LOG(INFO, "port %u: %u flows flushed before stopping", 6903 dev->data->port_id, num_flushed); 6904 } 6905 } 6906 6907 /** 6908 * Stop all default actions for flows. 6909 * 6910 * @param dev 6911 * Pointer to Ethernet device. 6912 */ 6913 void 6914 mlx5_flow_stop_default(struct rte_eth_dev *dev) 6915 { 6916 flow_mreg_del_default_copy_action(dev); 6917 flow_rxq_flags_clear(dev); 6918 } 6919 6920 /** 6921 * Start all default actions for flows. 6922 * 6923 * @param dev 6924 * Pointer to Ethernet device. 6925 * @return 6926 * 0 on success, a negative errno value otherwise and rte_errno is set. 6927 */ 6928 int 6929 mlx5_flow_start_default(struct rte_eth_dev *dev) 6930 { 6931 struct rte_flow_error error; 6932 6933 /* Make sure default copy action (reg_c[0] -> reg_b) is created. */ 6934 return flow_mreg_add_default_copy_action(dev, &error); 6935 } 6936 6937 /** 6938 * Release key of thread specific flow workspace data. 6939 */ 6940 void 6941 flow_release_workspace(void *data) 6942 { 6943 struct mlx5_flow_workspace *wks = data; 6944 struct mlx5_flow_workspace *next; 6945 6946 while (wks) { 6947 next = wks->next; 6948 free(wks->rss_desc.queue); 6949 free(wks); 6950 wks = next; 6951 } 6952 } 6953 6954 /** 6955 * Get thread specific current flow workspace. 6956 * 6957 * @return pointer to thread specific flow workspace data, NULL on error. 6958 */ 6959 struct mlx5_flow_workspace* 6960 mlx5_flow_get_thread_workspace(void) 6961 { 6962 struct mlx5_flow_workspace *data; 6963 6964 data = mlx5_flow_os_get_specific_workspace(); 6965 MLX5_ASSERT(data && data->inuse); 6966 if (!data || !data->inuse) 6967 DRV_LOG(ERR, "flow workspace not initialized."); 6968 return data; 6969 } 6970 6971 /** 6972 * Allocate and init new flow workspace. 6973 * 6974 * @return pointer to flow workspace data, NULL on error. 6975 */ 6976 static struct mlx5_flow_workspace* 6977 flow_alloc_thread_workspace(void) 6978 { 6979 struct mlx5_flow_workspace *data = calloc(1, sizeof(*data)); 6980 6981 if (!data) { 6982 DRV_LOG(ERR, "Failed to allocate flow workspace " 6983 "memory."); 6984 return NULL; 6985 } 6986 data->rss_desc.queue = calloc(1, 6987 sizeof(uint16_t) * MLX5_RSSQ_DEFAULT_NUM); 6988 if (!data->rss_desc.queue) 6989 goto err; 6990 data->rssq_num = MLX5_RSSQ_DEFAULT_NUM; 6991 return data; 6992 err: 6993 if (data->rss_desc.queue) 6994 free(data->rss_desc.queue); 6995 free(data); 6996 return NULL; 6997 } 6998 6999 /** 7000 * Get new thread specific flow workspace. 7001 * 7002 * If current workspace inuse, create new one and set as current. 7003 * 7004 * @return pointer to thread specific flow workspace data, NULL on error. 7005 */ 7006 static struct mlx5_flow_workspace* 7007 mlx5_flow_push_thread_workspace(void) 7008 { 7009 struct mlx5_flow_workspace *curr; 7010 struct mlx5_flow_workspace *data; 7011 7012 curr = mlx5_flow_os_get_specific_workspace(); 7013 if (!curr) { 7014 data = flow_alloc_thread_workspace(); 7015 if (!data) 7016 return NULL; 7017 } else if (!curr->inuse) { 7018 data = curr; 7019 } else if (curr->next) { 7020 data = curr->next; 7021 } else { 7022 data = flow_alloc_thread_workspace(); 7023 if (!data) 7024 return NULL; 7025 curr->next = data; 7026 data->prev = curr; 7027 } 7028 data->inuse = 1; 7029 data->flow_idx = 0; 7030 /* Set as current workspace */ 7031 if (mlx5_flow_os_set_specific_workspace(data)) 7032 DRV_LOG(ERR, "Failed to set flow workspace to thread."); 7033 return data; 7034 } 7035 7036 /** 7037 * Close current thread specific flow workspace. 7038 * 7039 * If previous workspace available, set it as current. 7040 * 7041 * @return pointer to thread specific flow workspace data, NULL on error. 7042 */ 7043 static void 7044 mlx5_flow_pop_thread_workspace(void) 7045 { 7046 struct mlx5_flow_workspace *data = mlx5_flow_get_thread_workspace(); 7047 7048 if (!data) 7049 return; 7050 if (!data->inuse) { 7051 DRV_LOG(ERR, "Failed to close unused flow workspace."); 7052 return; 7053 } 7054 data->inuse = 0; 7055 if (!data->prev) 7056 return; 7057 if (mlx5_flow_os_set_specific_workspace(data->prev)) 7058 DRV_LOG(ERR, "Failed to set flow workspace to thread."); 7059 } 7060 7061 /** 7062 * Verify the flow list is empty 7063 * 7064 * @param dev 7065 * Pointer to Ethernet device. 7066 * 7067 * @return the number of flows not released. 7068 */ 7069 int 7070 mlx5_flow_verify(struct rte_eth_dev *dev __rte_unused) 7071 { 7072 struct mlx5_priv *priv = dev->data->dev_private; 7073 struct rte_flow *flow; 7074 uint32_t idx = 0; 7075 int ret = 0, i; 7076 7077 for (i = 0; i < MLX5_FLOW_TYPE_MAXI; i++) { 7078 MLX5_IPOOL_FOREACH(priv->flows[i], idx, flow) { 7079 DRV_LOG(DEBUG, "port %u flow %p still referenced", 7080 dev->data->port_id, (void *)flow); 7081 ret++; 7082 } 7083 } 7084 return ret; 7085 } 7086 7087 /** 7088 * Enable default hairpin egress flow. 7089 * 7090 * @param dev 7091 * Pointer to Ethernet device. 7092 * @param queue 7093 * The queue index. 7094 * 7095 * @return 7096 * 0 on success, a negative errno value otherwise and rte_errno is set. 7097 */ 7098 int 7099 mlx5_ctrl_flow_source_queue(struct rte_eth_dev *dev, 7100 uint32_t queue) 7101 { 7102 const struct rte_flow_attr attr = { 7103 .egress = 1, 7104 .priority = 0, 7105 }; 7106 struct mlx5_rte_flow_item_tx_queue queue_spec = { 7107 .queue = queue, 7108 }; 7109 struct mlx5_rte_flow_item_tx_queue queue_mask = { 7110 .queue = UINT32_MAX, 7111 }; 7112 struct rte_flow_item items[] = { 7113 { 7114 .type = (enum rte_flow_item_type) 7115 MLX5_RTE_FLOW_ITEM_TYPE_TX_QUEUE, 7116 .spec = &queue_spec, 7117 .last = NULL, 7118 .mask = &queue_mask, 7119 }, 7120 { 7121 .type = RTE_FLOW_ITEM_TYPE_END, 7122 }, 7123 }; 7124 struct rte_flow_action_jump jump = { 7125 .group = MLX5_HAIRPIN_TX_TABLE, 7126 }; 7127 struct rte_flow_action actions[2]; 7128 uint32_t flow_idx; 7129 struct rte_flow_error error; 7130 7131 actions[0].type = RTE_FLOW_ACTION_TYPE_JUMP; 7132 actions[0].conf = &jump; 7133 actions[1].type = RTE_FLOW_ACTION_TYPE_END; 7134 flow_idx = flow_list_create(dev, MLX5_FLOW_TYPE_CTL, 7135 &attr, items, actions, false, &error); 7136 if (!flow_idx) { 7137 DRV_LOG(DEBUG, 7138 "Failed to create ctrl flow: rte_errno(%d)," 7139 " type(%d), message(%s)", 7140 rte_errno, error.type, 7141 error.message ? error.message : " (no stated reason)"); 7142 return -rte_errno; 7143 } 7144 return 0; 7145 } 7146 7147 /** 7148 * Enable a control flow configured from the control plane. 7149 * 7150 * @param dev 7151 * Pointer to Ethernet device. 7152 * @param eth_spec 7153 * An Ethernet flow spec to apply. 7154 * @param eth_mask 7155 * An Ethernet flow mask to apply. 7156 * @param vlan_spec 7157 * A VLAN flow spec to apply. 7158 * @param vlan_mask 7159 * A VLAN flow mask to apply. 7160 * 7161 * @return 7162 * 0 on success, a negative errno value otherwise and rte_errno is set. 7163 */ 7164 int 7165 mlx5_ctrl_flow_vlan(struct rte_eth_dev *dev, 7166 struct rte_flow_item_eth *eth_spec, 7167 struct rte_flow_item_eth *eth_mask, 7168 struct rte_flow_item_vlan *vlan_spec, 7169 struct rte_flow_item_vlan *vlan_mask) 7170 { 7171 struct mlx5_priv *priv = dev->data->dev_private; 7172 const struct rte_flow_attr attr = { 7173 .ingress = 1, 7174 .priority = MLX5_FLOW_LOWEST_PRIO_INDICATOR, 7175 }; 7176 struct rte_flow_item items[] = { 7177 { 7178 .type = RTE_FLOW_ITEM_TYPE_ETH, 7179 .spec = eth_spec, 7180 .last = NULL, 7181 .mask = eth_mask, 7182 }, 7183 { 7184 .type = (vlan_spec) ? RTE_FLOW_ITEM_TYPE_VLAN : 7185 RTE_FLOW_ITEM_TYPE_END, 7186 .spec = vlan_spec, 7187 .last = NULL, 7188 .mask = vlan_mask, 7189 }, 7190 { 7191 .type = RTE_FLOW_ITEM_TYPE_END, 7192 }, 7193 }; 7194 uint16_t queue[priv->reta_idx_n]; 7195 struct rte_flow_action_rss action_rss = { 7196 .func = RTE_ETH_HASH_FUNCTION_DEFAULT, 7197 .level = 0, 7198 .types = priv->rss_conf.rss_hf, 7199 .key_len = priv->rss_conf.rss_key_len, 7200 .queue_num = priv->reta_idx_n, 7201 .key = priv->rss_conf.rss_key, 7202 .queue = queue, 7203 }; 7204 struct rte_flow_action actions[] = { 7205 { 7206 .type = RTE_FLOW_ACTION_TYPE_RSS, 7207 .conf = &action_rss, 7208 }, 7209 { 7210 .type = RTE_FLOW_ACTION_TYPE_END, 7211 }, 7212 }; 7213 uint32_t flow_idx; 7214 struct rte_flow_error error; 7215 unsigned int i; 7216 7217 if (!priv->reta_idx_n || !priv->rxqs_n) { 7218 return 0; 7219 } 7220 if (!(dev->data->dev_conf.rxmode.mq_mode & RTE_ETH_MQ_RX_RSS_FLAG)) 7221 action_rss.types = 0; 7222 for (i = 0; i != priv->reta_idx_n; ++i) 7223 queue[i] = (*priv->reta_idx)[i]; 7224 flow_idx = flow_list_create(dev, MLX5_FLOW_TYPE_CTL, 7225 &attr, items, actions, false, &error); 7226 if (!flow_idx) 7227 return -rte_errno; 7228 return 0; 7229 } 7230 7231 /** 7232 * Enable a flow control configured from the control plane. 7233 * 7234 * @param dev 7235 * Pointer to Ethernet device. 7236 * @param eth_spec 7237 * An Ethernet flow spec to apply. 7238 * @param eth_mask 7239 * An Ethernet flow mask to apply. 7240 * 7241 * @return 7242 * 0 on success, a negative errno value otherwise and rte_errno is set. 7243 */ 7244 int 7245 mlx5_ctrl_flow(struct rte_eth_dev *dev, 7246 struct rte_flow_item_eth *eth_spec, 7247 struct rte_flow_item_eth *eth_mask) 7248 { 7249 return mlx5_ctrl_flow_vlan(dev, eth_spec, eth_mask, NULL, NULL); 7250 } 7251 7252 /** 7253 * Create default miss flow rule matching lacp traffic 7254 * 7255 * @param dev 7256 * Pointer to Ethernet device. 7257 * @param eth_spec 7258 * An Ethernet flow spec to apply. 7259 * 7260 * @return 7261 * 0 on success, a negative errno value otherwise and rte_errno is set. 7262 */ 7263 int 7264 mlx5_flow_lacp_miss(struct rte_eth_dev *dev) 7265 { 7266 /* 7267 * The LACP matching is done by only using ether type since using 7268 * a multicast dst mac causes kernel to give low priority to this flow. 7269 */ 7270 static const struct rte_flow_item_eth lacp_spec = { 7271 .type = RTE_BE16(0x8809), 7272 }; 7273 static const struct rte_flow_item_eth lacp_mask = { 7274 .type = 0xffff, 7275 }; 7276 const struct rte_flow_attr attr = { 7277 .ingress = 1, 7278 }; 7279 struct rte_flow_item items[] = { 7280 { 7281 .type = RTE_FLOW_ITEM_TYPE_ETH, 7282 .spec = &lacp_spec, 7283 .mask = &lacp_mask, 7284 }, 7285 { 7286 .type = RTE_FLOW_ITEM_TYPE_END, 7287 }, 7288 }; 7289 struct rte_flow_action actions[] = { 7290 { 7291 .type = (enum rte_flow_action_type) 7292 MLX5_RTE_FLOW_ACTION_TYPE_DEFAULT_MISS, 7293 }, 7294 { 7295 .type = RTE_FLOW_ACTION_TYPE_END, 7296 }, 7297 }; 7298 struct rte_flow_error error; 7299 uint32_t flow_idx = flow_list_create(dev, MLX5_FLOW_TYPE_CTL, 7300 &attr, items, actions, 7301 false, &error); 7302 7303 if (!flow_idx) 7304 return -rte_errno; 7305 return 0; 7306 } 7307 7308 /** 7309 * Destroy a flow. 7310 * 7311 * @see rte_flow_destroy() 7312 * @see rte_flow_ops 7313 */ 7314 int 7315 mlx5_flow_destroy(struct rte_eth_dev *dev, 7316 struct rte_flow *flow, 7317 struct rte_flow_error *error __rte_unused) 7318 { 7319 flow_list_destroy(dev, MLX5_FLOW_TYPE_GEN, 7320 (uintptr_t)(void *)flow); 7321 return 0; 7322 } 7323 7324 /** 7325 * Destroy all flows. 7326 * 7327 * @see rte_flow_flush() 7328 * @see rte_flow_ops 7329 */ 7330 int 7331 mlx5_flow_flush(struct rte_eth_dev *dev, 7332 struct rte_flow_error *error __rte_unused) 7333 { 7334 mlx5_flow_list_flush(dev, MLX5_FLOW_TYPE_GEN, false); 7335 return 0; 7336 } 7337 7338 /** 7339 * Isolated mode. 7340 * 7341 * @see rte_flow_isolate() 7342 * @see rte_flow_ops 7343 */ 7344 int 7345 mlx5_flow_isolate(struct rte_eth_dev *dev, 7346 int enable, 7347 struct rte_flow_error *error) 7348 { 7349 struct mlx5_priv *priv = dev->data->dev_private; 7350 7351 if (dev->data->dev_started) { 7352 rte_flow_error_set(error, EBUSY, 7353 RTE_FLOW_ERROR_TYPE_UNSPECIFIED, 7354 NULL, 7355 "port must be stopped first"); 7356 return -rte_errno; 7357 } 7358 priv->isolated = !!enable; 7359 if (enable) 7360 dev->dev_ops = &mlx5_dev_ops_isolate; 7361 else 7362 dev->dev_ops = &mlx5_dev_ops; 7363 7364 dev->rx_descriptor_status = mlx5_rx_descriptor_status; 7365 dev->tx_descriptor_status = mlx5_tx_descriptor_status; 7366 7367 return 0; 7368 } 7369 7370 /** 7371 * Query a flow. 7372 * 7373 * @see rte_flow_query() 7374 * @see rte_flow_ops 7375 */ 7376 static int 7377 flow_drv_query(struct rte_eth_dev *dev, 7378 uint32_t flow_idx, 7379 const struct rte_flow_action *actions, 7380 void *data, 7381 struct rte_flow_error *error) 7382 { 7383 struct mlx5_priv *priv = dev->data->dev_private; 7384 const struct mlx5_flow_driver_ops *fops; 7385 struct rte_flow *flow = mlx5_ipool_get(priv->flows[MLX5_FLOW_TYPE_GEN], 7386 flow_idx); 7387 enum mlx5_flow_drv_type ftype; 7388 7389 if (!flow) { 7390 return rte_flow_error_set(error, ENOENT, 7391 RTE_FLOW_ERROR_TYPE_UNSPECIFIED, 7392 NULL, 7393 "invalid flow handle"); 7394 } 7395 ftype = flow->drv_type; 7396 MLX5_ASSERT(ftype > MLX5_FLOW_TYPE_MIN && ftype < MLX5_FLOW_TYPE_MAX); 7397 fops = flow_get_drv_ops(ftype); 7398 7399 return fops->query(dev, flow, actions, data, error); 7400 } 7401 7402 /** 7403 * Query a flow. 7404 * 7405 * @see rte_flow_query() 7406 * @see rte_flow_ops 7407 */ 7408 int 7409 mlx5_flow_query(struct rte_eth_dev *dev, 7410 struct rte_flow *flow, 7411 const struct rte_flow_action *actions, 7412 void *data, 7413 struct rte_flow_error *error) 7414 { 7415 int ret; 7416 7417 ret = flow_drv_query(dev, (uintptr_t)(void *)flow, actions, data, 7418 error); 7419 if (ret < 0) 7420 return ret; 7421 return 0; 7422 } 7423 7424 /** 7425 * Get rte_flow callbacks. 7426 * 7427 * @param dev 7428 * Pointer to Ethernet device structure. 7429 * @param ops 7430 * Pointer to operation-specific structure. 7431 * 7432 * @return 0 7433 */ 7434 int 7435 mlx5_flow_ops_get(struct rte_eth_dev *dev __rte_unused, 7436 const struct rte_flow_ops **ops) 7437 { 7438 *ops = &mlx5_flow_ops; 7439 return 0; 7440 } 7441 7442 /** 7443 * Validate meter policy actions. 7444 * Dispatcher for action type specific validation. 7445 * 7446 * @param[in] dev 7447 * Pointer to the Ethernet device structure. 7448 * @param[in] action 7449 * The meter policy action object to validate. 7450 * @param[in] attr 7451 * Attributes of flow to determine steering domain. 7452 * @param[out] is_rss 7453 * Is RSS or not. 7454 * @param[out] domain_bitmap 7455 * Domain bitmap. 7456 * @param[out] is_def_policy 7457 * Is default policy or not. 7458 * @param[out] error 7459 * Perform verbose error reporting if not NULL. Initialized in case of 7460 * error only. 7461 * 7462 * @return 7463 * 0 on success, otherwise negative errno value. 7464 */ 7465 int 7466 mlx5_flow_validate_mtr_acts(struct rte_eth_dev *dev, 7467 const struct rte_flow_action *actions[RTE_COLORS], 7468 struct rte_flow_attr *attr, 7469 bool *is_rss, 7470 uint8_t *domain_bitmap, 7471 uint8_t *policy_mode, 7472 struct rte_mtr_error *error) 7473 { 7474 const struct mlx5_flow_driver_ops *fops; 7475 7476 fops = flow_get_drv_ops(MLX5_FLOW_TYPE_DV); 7477 return fops->validate_mtr_acts(dev, actions, attr, is_rss, 7478 domain_bitmap, policy_mode, error); 7479 } 7480 7481 /** 7482 * Destroy the meter table set. 7483 * 7484 * @param[in] dev 7485 * Pointer to Ethernet device. 7486 * @param[in] mtr_policy 7487 * Meter policy struct. 7488 */ 7489 void 7490 mlx5_flow_destroy_mtr_acts(struct rte_eth_dev *dev, 7491 struct mlx5_flow_meter_policy *mtr_policy) 7492 { 7493 const struct mlx5_flow_driver_ops *fops; 7494 7495 fops = flow_get_drv_ops(MLX5_FLOW_TYPE_DV); 7496 fops->destroy_mtr_acts(dev, mtr_policy); 7497 } 7498 7499 /** 7500 * Create policy action, lock free, 7501 * (mutex should be acquired by caller). 7502 * Dispatcher for action type specific call. 7503 * 7504 * @param[in] dev 7505 * Pointer to the Ethernet device structure. 7506 * @param[in] mtr_policy 7507 * Meter policy struct. 7508 * @param[in] action 7509 * Action specification used to create meter actions. 7510 * @param[out] error 7511 * Perform verbose error reporting if not NULL. Initialized in case of 7512 * error only. 7513 * 7514 * @return 7515 * 0 on success, otherwise negative errno value. 7516 */ 7517 int 7518 mlx5_flow_create_mtr_acts(struct rte_eth_dev *dev, 7519 struct mlx5_flow_meter_policy *mtr_policy, 7520 const struct rte_flow_action *actions[RTE_COLORS], 7521 struct rte_mtr_error *error) 7522 { 7523 const struct mlx5_flow_driver_ops *fops; 7524 7525 fops = flow_get_drv_ops(MLX5_FLOW_TYPE_DV); 7526 return fops->create_mtr_acts(dev, mtr_policy, actions, error); 7527 } 7528 7529 /** 7530 * Create policy rules, lock free, 7531 * (mutex should be acquired by caller). 7532 * Dispatcher for action type specific call. 7533 * 7534 * @param[in] dev 7535 * Pointer to the Ethernet device structure. 7536 * @param[in] mtr_policy 7537 * Meter policy struct. 7538 * 7539 * @return 7540 * 0 on success, -1 otherwise. 7541 */ 7542 int 7543 mlx5_flow_create_policy_rules(struct rte_eth_dev *dev, 7544 struct mlx5_flow_meter_policy *mtr_policy) 7545 { 7546 const struct mlx5_flow_driver_ops *fops; 7547 7548 fops = flow_get_drv_ops(MLX5_FLOW_TYPE_DV); 7549 return fops->create_policy_rules(dev, mtr_policy); 7550 } 7551 7552 /** 7553 * Destroy policy rules, lock free, 7554 * (mutex should be acquired by caller). 7555 * Dispatcher for action type specific call. 7556 * 7557 * @param[in] dev 7558 * Pointer to the Ethernet device structure. 7559 * @param[in] mtr_policy 7560 * Meter policy struct. 7561 */ 7562 void 7563 mlx5_flow_destroy_policy_rules(struct rte_eth_dev *dev, 7564 struct mlx5_flow_meter_policy *mtr_policy) 7565 { 7566 const struct mlx5_flow_driver_ops *fops; 7567 7568 fops = flow_get_drv_ops(MLX5_FLOW_TYPE_DV); 7569 fops->destroy_policy_rules(dev, mtr_policy); 7570 } 7571 7572 /** 7573 * Destroy the default policy table set. 7574 * 7575 * @param[in] dev 7576 * Pointer to Ethernet device. 7577 */ 7578 void 7579 mlx5_flow_destroy_def_policy(struct rte_eth_dev *dev) 7580 { 7581 const struct mlx5_flow_driver_ops *fops; 7582 7583 fops = flow_get_drv_ops(MLX5_FLOW_TYPE_DV); 7584 fops->destroy_def_policy(dev); 7585 } 7586 7587 /** 7588 * Destroy the default policy table set. 7589 * 7590 * @param[in] dev 7591 * Pointer to Ethernet device. 7592 * 7593 * @return 7594 * 0 on success, -1 otherwise. 7595 */ 7596 int 7597 mlx5_flow_create_def_policy(struct rte_eth_dev *dev) 7598 { 7599 const struct mlx5_flow_driver_ops *fops; 7600 7601 fops = flow_get_drv_ops(MLX5_FLOW_TYPE_DV); 7602 return fops->create_def_policy(dev); 7603 } 7604 7605 /** 7606 * Create the needed meter and suffix tables. 7607 * 7608 * @param[in] dev 7609 * Pointer to Ethernet device. 7610 * 7611 * @return 7612 * 0 on success, -1 otherwise. 7613 */ 7614 int 7615 mlx5_flow_create_mtr_tbls(struct rte_eth_dev *dev, 7616 struct mlx5_flow_meter_info *fm, 7617 uint32_t mtr_idx, 7618 uint8_t domain_bitmap) 7619 { 7620 const struct mlx5_flow_driver_ops *fops; 7621 7622 fops = flow_get_drv_ops(MLX5_FLOW_TYPE_DV); 7623 return fops->create_mtr_tbls(dev, fm, mtr_idx, domain_bitmap); 7624 } 7625 7626 /** 7627 * Destroy the meter table set. 7628 * 7629 * @param[in] dev 7630 * Pointer to Ethernet device. 7631 * @param[in] tbl 7632 * Pointer to the meter table set. 7633 */ 7634 void 7635 mlx5_flow_destroy_mtr_tbls(struct rte_eth_dev *dev, 7636 struct mlx5_flow_meter_info *fm) 7637 { 7638 const struct mlx5_flow_driver_ops *fops; 7639 7640 fops = flow_get_drv_ops(MLX5_FLOW_TYPE_DV); 7641 fops->destroy_mtr_tbls(dev, fm); 7642 } 7643 7644 /** 7645 * Destroy the global meter drop table. 7646 * 7647 * @param[in] dev 7648 * Pointer to Ethernet device. 7649 */ 7650 void 7651 mlx5_flow_destroy_mtr_drop_tbls(struct rte_eth_dev *dev) 7652 { 7653 const struct mlx5_flow_driver_ops *fops; 7654 7655 fops = flow_get_drv_ops(MLX5_FLOW_TYPE_DV); 7656 fops->destroy_mtr_drop_tbls(dev); 7657 } 7658 7659 /** 7660 * Destroy the sub policy table with RX queue. 7661 * 7662 * @param[in] dev 7663 * Pointer to Ethernet device. 7664 * @param[in] mtr_policy 7665 * Pointer to meter policy table. 7666 */ 7667 void 7668 mlx5_flow_destroy_sub_policy_with_rxq(struct rte_eth_dev *dev, 7669 struct mlx5_flow_meter_policy *mtr_policy) 7670 { 7671 const struct mlx5_flow_driver_ops *fops; 7672 7673 fops = flow_get_drv_ops(MLX5_FLOW_TYPE_DV); 7674 fops->destroy_sub_policy_with_rxq(dev, mtr_policy); 7675 } 7676 7677 /** 7678 * Allocate the needed aso flow meter id. 7679 * 7680 * @param[in] dev 7681 * Pointer to Ethernet device. 7682 * 7683 * @return 7684 * Index to aso flow meter on success, NULL otherwise. 7685 */ 7686 uint32_t 7687 mlx5_flow_mtr_alloc(struct rte_eth_dev *dev) 7688 { 7689 const struct mlx5_flow_driver_ops *fops; 7690 7691 fops = flow_get_drv_ops(MLX5_FLOW_TYPE_DV); 7692 return fops->create_meter(dev); 7693 } 7694 7695 /** 7696 * Free the aso flow meter id. 7697 * 7698 * @param[in] dev 7699 * Pointer to Ethernet device. 7700 * @param[in] mtr_idx 7701 * Index to aso flow meter to be free. 7702 * 7703 * @return 7704 * 0 on success. 7705 */ 7706 void 7707 mlx5_flow_mtr_free(struct rte_eth_dev *dev, uint32_t mtr_idx) 7708 { 7709 const struct mlx5_flow_driver_ops *fops; 7710 7711 fops = flow_get_drv_ops(MLX5_FLOW_TYPE_DV); 7712 fops->free_meter(dev, mtr_idx); 7713 } 7714 7715 /** 7716 * Allocate a counter. 7717 * 7718 * @param[in] dev 7719 * Pointer to Ethernet device structure. 7720 * 7721 * @return 7722 * Index to allocated counter on success, 0 otherwise. 7723 */ 7724 uint32_t 7725 mlx5_counter_alloc(struct rte_eth_dev *dev) 7726 { 7727 const struct mlx5_flow_driver_ops *fops; 7728 struct rte_flow_attr attr = { .transfer = 0 }; 7729 7730 if (flow_get_drv_type(dev, &attr) == MLX5_FLOW_TYPE_DV) { 7731 fops = flow_get_drv_ops(MLX5_FLOW_TYPE_DV); 7732 return fops->counter_alloc(dev); 7733 } 7734 DRV_LOG(ERR, 7735 "port %u counter allocate is not supported.", 7736 dev->data->port_id); 7737 return 0; 7738 } 7739 7740 /** 7741 * Free a counter. 7742 * 7743 * @param[in] dev 7744 * Pointer to Ethernet device structure. 7745 * @param[in] cnt 7746 * Index to counter to be free. 7747 */ 7748 void 7749 mlx5_counter_free(struct rte_eth_dev *dev, uint32_t cnt) 7750 { 7751 const struct mlx5_flow_driver_ops *fops; 7752 struct rte_flow_attr attr = { .transfer = 0 }; 7753 7754 if (flow_get_drv_type(dev, &attr) == MLX5_FLOW_TYPE_DV) { 7755 fops = flow_get_drv_ops(MLX5_FLOW_TYPE_DV); 7756 fops->counter_free(dev, cnt); 7757 return; 7758 } 7759 DRV_LOG(ERR, 7760 "port %u counter free is not supported.", 7761 dev->data->port_id); 7762 } 7763 7764 /** 7765 * Query counter statistics. 7766 * 7767 * @param[in] dev 7768 * Pointer to Ethernet device structure. 7769 * @param[in] cnt 7770 * Index to counter to query. 7771 * @param[in] clear 7772 * Set to clear counter statistics. 7773 * @param[out] pkts 7774 * The counter hits packets number to save. 7775 * @param[out] bytes 7776 * The counter hits bytes number to save. 7777 * 7778 * @return 7779 * 0 on success, a negative errno value otherwise. 7780 */ 7781 int 7782 mlx5_counter_query(struct rte_eth_dev *dev, uint32_t cnt, 7783 bool clear, uint64_t *pkts, uint64_t *bytes) 7784 { 7785 const struct mlx5_flow_driver_ops *fops; 7786 struct rte_flow_attr attr = { .transfer = 0 }; 7787 7788 if (flow_get_drv_type(dev, &attr) == MLX5_FLOW_TYPE_DV) { 7789 fops = flow_get_drv_ops(MLX5_FLOW_TYPE_DV); 7790 return fops->counter_query(dev, cnt, clear, pkts, bytes); 7791 } 7792 DRV_LOG(ERR, 7793 "port %u counter query is not supported.", 7794 dev->data->port_id); 7795 return -ENOTSUP; 7796 } 7797 7798 /** 7799 * Allocate a new memory for the counter values wrapped by all the needed 7800 * management. 7801 * 7802 * @param[in] sh 7803 * Pointer to mlx5_dev_ctx_shared object. 7804 * 7805 * @return 7806 * 0 on success, a negative errno value otherwise. 7807 */ 7808 static int 7809 mlx5_flow_create_counter_stat_mem_mng(struct mlx5_dev_ctx_shared *sh) 7810 { 7811 struct mlx5_counter_stats_mem_mng *mem_mng; 7812 volatile struct flow_counter_stats *raw_data; 7813 int raws_n = MLX5_CNT_CONTAINER_RESIZE + MLX5_MAX_PENDING_QUERIES; 7814 int size = (sizeof(struct flow_counter_stats) * 7815 MLX5_COUNTERS_PER_POOL + 7816 sizeof(struct mlx5_counter_stats_raw)) * raws_n + 7817 sizeof(struct mlx5_counter_stats_mem_mng); 7818 size_t pgsize = rte_mem_page_size(); 7819 uint8_t *mem; 7820 int ret; 7821 int i; 7822 7823 if (pgsize == (size_t)-1) { 7824 DRV_LOG(ERR, "Failed to get mem page size"); 7825 rte_errno = ENOMEM; 7826 return -ENOMEM; 7827 } 7828 mem = mlx5_malloc(MLX5_MEM_ZERO, size, pgsize, SOCKET_ID_ANY); 7829 if (!mem) { 7830 rte_errno = ENOMEM; 7831 return -ENOMEM; 7832 } 7833 mem_mng = (struct mlx5_counter_stats_mem_mng *)(mem + size) - 1; 7834 size = sizeof(*raw_data) * MLX5_COUNTERS_PER_POOL * raws_n; 7835 ret = mlx5_os_wrapped_mkey_create(sh->cdev->ctx, sh->cdev->pd, 7836 sh->cdev->pdn, mem, size, 7837 &mem_mng->wm); 7838 if (ret) { 7839 rte_errno = errno; 7840 mlx5_free(mem); 7841 return -rte_errno; 7842 } 7843 mem_mng->raws = (struct mlx5_counter_stats_raw *)(mem + size); 7844 raw_data = (volatile struct flow_counter_stats *)mem; 7845 for (i = 0; i < raws_n; ++i) { 7846 mem_mng->raws[i].mem_mng = mem_mng; 7847 mem_mng->raws[i].data = raw_data + i * MLX5_COUNTERS_PER_POOL; 7848 } 7849 for (i = 0; i < MLX5_MAX_PENDING_QUERIES; ++i) 7850 LIST_INSERT_HEAD(&sh->cmng.free_stat_raws, 7851 mem_mng->raws + MLX5_CNT_CONTAINER_RESIZE + i, 7852 next); 7853 LIST_INSERT_HEAD(&sh->cmng.mem_mngs, mem_mng, next); 7854 sh->cmng.mem_mng = mem_mng; 7855 return 0; 7856 } 7857 7858 /** 7859 * Set the statistic memory to the new counter pool. 7860 * 7861 * @param[in] sh 7862 * Pointer to mlx5_dev_ctx_shared object. 7863 * @param[in] pool 7864 * Pointer to the pool to set the statistic memory. 7865 * 7866 * @return 7867 * 0 on success, a negative errno value otherwise. 7868 */ 7869 static int 7870 mlx5_flow_set_counter_stat_mem(struct mlx5_dev_ctx_shared *sh, 7871 struct mlx5_flow_counter_pool *pool) 7872 { 7873 struct mlx5_flow_counter_mng *cmng = &sh->cmng; 7874 /* Resize statistic memory once used out. */ 7875 if (!(pool->index % MLX5_CNT_CONTAINER_RESIZE) && 7876 mlx5_flow_create_counter_stat_mem_mng(sh)) { 7877 DRV_LOG(ERR, "Cannot resize counter stat mem."); 7878 return -1; 7879 } 7880 rte_spinlock_lock(&pool->sl); 7881 pool->raw = cmng->mem_mng->raws + pool->index % 7882 MLX5_CNT_CONTAINER_RESIZE; 7883 rte_spinlock_unlock(&pool->sl); 7884 pool->raw_hw = NULL; 7885 return 0; 7886 } 7887 7888 #define MLX5_POOL_QUERY_FREQ_US 1000000 7889 7890 /** 7891 * Set the periodic procedure for triggering asynchronous batch queries for all 7892 * the counter pools. 7893 * 7894 * @param[in] sh 7895 * Pointer to mlx5_dev_ctx_shared object. 7896 */ 7897 void 7898 mlx5_set_query_alarm(struct mlx5_dev_ctx_shared *sh) 7899 { 7900 uint32_t pools_n, us; 7901 7902 pools_n = __atomic_load_n(&sh->cmng.n_valid, __ATOMIC_RELAXED); 7903 us = MLX5_POOL_QUERY_FREQ_US / pools_n; 7904 DRV_LOG(DEBUG, "Set alarm for %u pools each %u us", pools_n, us); 7905 if (rte_eal_alarm_set(us, mlx5_flow_query_alarm, sh)) { 7906 sh->cmng.query_thread_on = 0; 7907 DRV_LOG(ERR, "Cannot reinitialize query alarm"); 7908 } else { 7909 sh->cmng.query_thread_on = 1; 7910 } 7911 } 7912 7913 /** 7914 * The periodic procedure for triggering asynchronous batch queries for all the 7915 * counter pools. This function is probably called by the host thread. 7916 * 7917 * @param[in] arg 7918 * The parameter for the alarm process. 7919 */ 7920 void 7921 mlx5_flow_query_alarm(void *arg) 7922 { 7923 struct mlx5_dev_ctx_shared *sh = arg; 7924 int ret; 7925 uint16_t pool_index = sh->cmng.pool_index; 7926 struct mlx5_flow_counter_mng *cmng = &sh->cmng; 7927 struct mlx5_flow_counter_pool *pool; 7928 uint16_t n_valid; 7929 7930 if (sh->cmng.pending_queries >= MLX5_MAX_PENDING_QUERIES) 7931 goto set_alarm; 7932 rte_spinlock_lock(&cmng->pool_update_sl); 7933 pool = cmng->pools[pool_index]; 7934 n_valid = cmng->n_valid; 7935 rte_spinlock_unlock(&cmng->pool_update_sl); 7936 /* Set the statistic memory to the new created pool. */ 7937 if ((!pool->raw && mlx5_flow_set_counter_stat_mem(sh, pool))) 7938 goto set_alarm; 7939 if (pool->raw_hw) 7940 /* There is a pool query in progress. */ 7941 goto set_alarm; 7942 pool->raw_hw = 7943 LIST_FIRST(&sh->cmng.free_stat_raws); 7944 if (!pool->raw_hw) 7945 /* No free counter statistics raw memory. */ 7946 goto set_alarm; 7947 /* 7948 * Identify the counters released between query trigger and query 7949 * handle more efficiently. The counter released in this gap period 7950 * should wait for a new round of query as the new arrived packets 7951 * will not be taken into account. 7952 */ 7953 pool->query_gen++; 7954 ret = mlx5_devx_cmd_flow_counter_query(pool->min_dcs, 0, 7955 MLX5_COUNTERS_PER_POOL, 7956 NULL, NULL, 7957 pool->raw_hw->mem_mng->wm.lkey, 7958 (void *)(uintptr_t) 7959 pool->raw_hw->data, 7960 sh->devx_comp, 7961 (uint64_t)(uintptr_t)pool); 7962 if (ret) { 7963 DRV_LOG(ERR, "Failed to trigger asynchronous query for dcs ID" 7964 " %d", pool->min_dcs->id); 7965 pool->raw_hw = NULL; 7966 goto set_alarm; 7967 } 7968 LIST_REMOVE(pool->raw_hw, next); 7969 sh->cmng.pending_queries++; 7970 pool_index++; 7971 if (pool_index >= n_valid) 7972 pool_index = 0; 7973 set_alarm: 7974 sh->cmng.pool_index = pool_index; 7975 mlx5_set_query_alarm(sh); 7976 } 7977 7978 /** 7979 * Check and callback event for new aged flow in the counter pool 7980 * 7981 * @param[in] sh 7982 * Pointer to mlx5_dev_ctx_shared object. 7983 * @param[in] pool 7984 * Pointer to Current counter pool. 7985 */ 7986 static void 7987 mlx5_flow_aging_check(struct mlx5_dev_ctx_shared *sh, 7988 struct mlx5_flow_counter_pool *pool) 7989 { 7990 struct mlx5_priv *priv; 7991 struct mlx5_flow_counter *cnt; 7992 struct mlx5_age_info *age_info; 7993 struct mlx5_age_param *age_param; 7994 struct mlx5_counter_stats_raw *cur = pool->raw_hw; 7995 struct mlx5_counter_stats_raw *prev = pool->raw; 7996 const uint64_t curr_time = MLX5_CURR_TIME_SEC; 7997 const uint32_t time_delta = curr_time - pool->time_of_last_age_check; 7998 uint16_t expected = AGE_CANDIDATE; 7999 uint32_t i; 8000 8001 pool->time_of_last_age_check = curr_time; 8002 for (i = 0; i < MLX5_COUNTERS_PER_POOL; ++i) { 8003 cnt = MLX5_POOL_GET_CNT(pool, i); 8004 age_param = MLX5_CNT_TO_AGE(cnt); 8005 if (__atomic_load_n(&age_param->state, 8006 __ATOMIC_RELAXED) != AGE_CANDIDATE) 8007 continue; 8008 if (cur->data[i].hits != prev->data[i].hits) { 8009 __atomic_store_n(&age_param->sec_since_last_hit, 0, 8010 __ATOMIC_RELAXED); 8011 continue; 8012 } 8013 if (__atomic_add_fetch(&age_param->sec_since_last_hit, 8014 time_delta, 8015 __ATOMIC_RELAXED) <= age_param->timeout) 8016 continue; 8017 /** 8018 * Hold the lock first, or if between the 8019 * state AGE_TMOUT and tailq operation the 8020 * release happened, the release procedure 8021 * may delete a non-existent tailq node. 8022 */ 8023 priv = rte_eth_devices[age_param->port_id].data->dev_private; 8024 age_info = GET_PORT_AGE_INFO(priv); 8025 rte_spinlock_lock(&age_info->aged_sl); 8026 if (__atomic_compare_exchange_n(&age_param->state, &expected, 8027 AGE_TMOUT, false, 8028 __ATOMIC_RELAXED, 8029 __ATOMIC_RELAXED)) { 8030 TAILQ_INSERT_TAIL(&age_info->aged_counters, cnt, next); 8031 MLX5_AGE_SET(age_info, MLX5_AGE_EVENT_NEW); 8032 } 8033 rte_spinlock_unlock(&age_info->aged_sl); 8034 } 8035 mlx5_age_event_prepare(sh); 8036 } 8037 8038 /** 8039 * Handler for the HW respond about ready values from an asynchronous batch 8040 * query. This function is probably called by the host thread. 8041 * 8042 * @param[in] sh 8043 * The pointer to the shared device context. 8044 * @param[in] async_id 8045 * The Devx async ID. 8046 * @param[in] status 8047 * The status of the completion. 8048 */ 8049 void 8050 mlx5_flow_async_pool_query_handle(struct mlx5_dev_ctx_shared *sh, 8051 uint64_t async_id, int status) 8052 { 8053 struct mlx5_flow_counter_pool *pool = 8054 (struct mlx5_flow_counter_pool *)(uintptr_t)async_id; 8055 struct mlx5_counter_stats_raw *raw_to_free; 8056 uint8_t query_gen = pool->query_gen ^ 1; 8057 struct mlx5_flow_counter_mng *cmng = &sh->cmng; 8058 enum mlx5_counter_type cnt_type = 8059 pool->is_aged ? MLX5_COUNTER_TYPE_AGE : 8060 MLX5_COUNTER_TYPE_ORIGIN; 8061 8062 if (unlikely(status)) { 8063 raw_to_free = pool->raw_hw; 8064 } else { 8065 raw_to_free = pool->raw; 8066 if (pool->is_aged) 8067 mlx5_flow_aging_check(sh, pool); 8068 rte_spinlock_lock(&pool->sl); 8069 pool->raw = pool->raw_hw; 8070 rte_spinlock_unlock(&pool->sl); 8071 /* Be sure the new raw counters data is updated in memory. */ 8072 rte_io_wmb(); 8073 if (!TAILQ_EMPTY(&pool->counters[query_gen])) { 8074 rte_spinlock_lock(&cmng->csl[cnt_type]); 8075 TAILQ_CONCAT(&cmng->counters[cnt_type], 8076 &pool->counters[query_gen], next); 8077 rte_spinlock_unlock(&cmng->csl[cnt_type]); 8078 } 8079 } 8080 LIST_INSERT_HEAD(&sh->cmng.free_stat_raws, raw_to_free, next); 8081 pool->raw_hw = NULL; 8082 sh->cmng.pending_queries--; 8083 } 8084 8085 static int 8086 flow_group_to_table(uint32_t port_id, uint32_t group, uint32_t *table, 8087 const struct flow_grp_info *grp_info, 8088 struct rte_flow_error *error) 8089 { 8090 if (grp_info->transfer && grp_info->external && 8091 grp_info->fdb_def_rule) { 8092 if (group == UINT32_MAX) 8093 return rte_flow_error_set 8094 (error, EINVAL, 8095 RTE_FLOW_ERROR_TYPE_ATTR_GROUP, 8096 NULL, 8097 "group index not supported"); 8098 *table = group + 1; 8099 } else { 8100 *table = group; 8101 } 8102 DRV_LOG(DEBUG, "port %u group=%#x table=%#x", port_id, group, *table); 8103 return 0; 8104 } 8105 8106 /** 8107 * Translate the rte_flow group index to HW table value. 8108 * 8109 * If tunnel offload is disabled, all group ids converted to flow table 8110 * id using the standard method. 8111 * If tunnel offload is enabled, group id can be converted using the 8112 * standard or tunnel conversion method. Group conversion method 8113 * selection depends on flags in `grp_info` parameter: 8114 * - Internal (grp_info.external == 0) groups conversion uses the 8115 * standard method. 8116 * - Group ids in JUMP action converted with the tunnel conversion. 8117 * - Group id in rule attribute conversion depends on a rule type and 8118 * group id value: 8119 * ** non zero group attributes converted with the tunnel method 8120 * ** zero group attribute in non-tunnel rule is converted using the 8121 * standard method - there's only one root table 8122 * ** zero group attribute in steer tunnel rule is converted with the 8123 * standard method - single root table 8124 * ** zero group attribute in match tunnel rule is a special OvS 8125 * case: that value is used for portability reasons. That group 8126 * id is converted with the tunnel conversion method. 8127 * 8128 * @param[in] dev 8129 * Port device 8130 * @param[in] tunnel 8131 * PMD tunnel offload object 8132 * @param[in] group 8133 * rte_flow group index value. 8134 * @param[out] table 8135 * HW table value. 8136 * @param[in] grp_info 8137 * flags used for conversion 8138 * @param[out] error 8139 * Pointer to error structure. 8140 * 8141 * @return 8142 * 0 on success, a negative errno value otherwise and rte_errno is set. 8143 */ 8144 int 8145 mlx5_flow_group_to_table(struct rte_eth_dev *dev, 8146 const struct mlx5_flow_tunnel *tunnel, 8147 uint32_t group, uint32_t *table, 8148 const struct flow_grp_info *grp_info, 8149 struct rte_flow_error *error) 8150 { 8151 int ret; 8152 bool standard_translation; 8153 8154 if (!grp_info->skip_scale && grp_info->external && 8155 group < MLX5_MAX_TABLES_EXTERNAL) 8156 group *= MLX5_FLOW_TABLE_FACTOR; 8157 if (is_tunnel_offload_active(dev)) { 8158 standard_translation = !grp_info->external || 8159 grp_info->std_tbl_fix; 8160 } else { 8161 standard_translation = true; 8162 } 8163 DRV_LOG(DEBUG, 8164 "port %u group=%u transfer=%d external=%d fdb_def_rule=%d translate=%s", 8165 dev->data->port_id, group, grp_info->transfer, 8166 grp_info->external, grp_info->fdb_def_rule, 8167 standard_translation ? "STANDARD" : "TUNNEL"); 8168 if (standard_translation) 8169 ret = flow_group_to_table(dev->data->port_id, group, table, 8170 grp_info, error); 8171 else 8172 ret = tunnel_flow_group_to_flow_table(dev, tunnel, group, 8173 table, error); 8174 8175 return ret; 8176 } 8177 8178 /** 8179 * Discover availability of metadata reg_c's. 8180 * 8181 * Iteratively use test flows to check availability. 8182 * 8183 * @param[in] dev 8184 * Pointer to the Ethernet device structure. 8185 * 8186 * @return 8187 * 0 on success, a negative errno value otherwise and rte_errno is set. 8188 */ 8189 int 8190 mlx5_flow_discover_mreg_c(struct rte_eth_dev *dev) 8191 { 8192 struct mlx5_priv *priv = dev->data->dev_private; 8193 enum modify_reg idx; 8194 int n = 0; 8195 8196 /* reg_c[0] and reg_c[1] are reserved. */ 8197 priv->sh->flow_mreg_c[n++] = REG_C_0; 8198 priv->sh->flow_mreg_c[n++] = REG_C_1; 8199 /* Discover availability of other reg_c's. */ 8200 for (idx = REG_C_2; idx <= REG_C_7; ++idx) { 8201 struct rte_flow_attr attr = { 8202 .group = MLX5_FLOW_MREG_CP_TABLE_GROUP, 8203 .priority = MLX5_FLOW_LOWEST_PRIO_INDICATOR, 8204 .ingress = 1, 8205 }; 8206 struct rte_flow_item items[] = { 8207 [0] = { 8208 .type = RTE_FLOW_ITEM_TYPE_END, 8209 }, 8210 }; 8211 struct rte_flow_action actions[] = { 8212 [0] = { 8213 .type = (enum rte_flow_action_type) 8214 MLX5_RTE_FLOW_ACTION_TYPE_COPY_MREG, 8215 .conf = &(struct mlx5_flow_action_copy_mreg){ 8216 .src = REG_C_1, 8217 .dst = idx, 8218 }, 8219 }, 8220 [1] = { 8221 .type = RTE_FLOW_ACTION_TYPE_JUMP, 8222 .conf = &(struct rte_flow_action_jump){ 8223 .group = MLX5_FLOW_MREG_ACT_TABLE_GROUP, 8224 }, 8225 }, 8226 [2] = { 8227 .type = RTE_FLOW_ACTION_TYPE_END, 8228 }, 8229 }; 8230 uint32_t flow_idx; 8231 struct rte_flow *flow; 8232 struct rte_flow_error error; 8233 8234 if (!priv->config.dv_flow_en) 8235 break; 8236 /* Create internal flow, validation skips copy action. */ 8237 flow_idx = flow_list_create(dev, MLX5_FLOW_TYPE_GEN, &attr, 8238 items, actions, false, &error); 8239 flow = mlx5_ipool_get(priv->flows[MLX5_FLOW_TYPE_GEN], 8240 flow_idx); 8241 if (!flow) 8242 continue; 8243 priv->sh->flow_mreg_c[n++] = idx; 8244 flow_list_destroy(dev, MLX5_FLOW_TYPE_GEN, flow_idx); 8245 } 8246 for (; n < MLX5_MREG_C_NUM; ++n) 8247 priv->sh->flow_mreg_c[n] = REG_NON; 8248 priv->sh->metadata_regc_check_flag = 1; 8249 return 0; 8250 } 8251 8252 int 8253 save_dump_file(const uint8_t *data, uint32_t size, 8254 uint32_t type, uint64_t id, void *arg, FILE *file) 8255 { 8256 char line[BUF_SIZE]; 8257 uint32_t out = 0; 8258 uint32_t k; 8259 uint32_t actions_num; 8260 struct rte_flow_query_count *count; 8261 8262 memset(line, 0, BUF_SIZE); 8263 switch (type) { 8264 case DR_DUMP_REC_TYPE_PMD_MODIFY_HDR: 8265 actions_num = *(uint32_t *)(arg); 8266 out += snprintf(line + out, BUF_SIZE - out, "%d,0x%" PRIx64 ",%d,", 8267 type, id, actions_num); 8268 break; 8269 case DR_DUMP_REC_TYPE_PMD_PKT_REFORMAT: 8270 out += snprintf(line + out, BUF_SIZE - out, "%d,0x%" PRIx64 ",", 8271 type, id); 8272 break; 8273 case DR_DUMP_REC_TYPE_PMD_COUNTER: 8274 count = (struct rte_flow_query_count *)arg; 8275 fprintf(file, 8276 "%d,0x%" PRIx64 ",%" PRIu64 ",%" PRIu64 "\n", 8277 type, id, count->hits, count->bytes); 8278 return 0; 8279 default: 8280 return -1; 8281 } 8282 8283 for (k = 0; k < size; k++) { 8284 /* Make sure we do not overrun the line buffer length. */ 8285 if (out >= BUF_SIZE - 4) { 8286 line[out] = '\0'; 8287 break; 8288 } 8289 out += snprintf(line + out, BUF_SIZE - out, "%02x", 8290 (data[k]) & 0xff); 8291 } 8292 fprintf(file, "%s\n", line); 8293 return 0; 8294 } 8295 8296 int 8297 mlx5_flow_query_counter(struct rte_eth_dev *dev, struct rte_flow *flow, 8298 struct rte_flow_query_count *count, struct rte_flow_error *error) 8299 { 8300 struct rte_flow_action action[2]; 8301 enum mlx5_flow_drv_type ftype; 8302 const struct mlx5_flow_driver_ops *fops; 8303 8304 if (!flow) { 8305 return rte_flow_error_set(error, ENOENT, 8306 RTE_FLOW_ERROR_TYPE_UNSPECIFIED, 8307 NULL, 8308 "invalid flow handle"); 8309 } 8310 action[0].type = RTE_FLOW_ACTION_TYPE_COUNT; 8311 action[1].type = RTE_FLOW_ACTION_TYPE_END; 8312 if (flow->counter) { 8313 memset(count, 0, sizeof(struct rte_flow_query_count)); 8314 ftype = (enum mlx5_flow_drv_type)(flow->drv_type); 8315 MLX5_ASSERT(ftype > MLX5_FLOW_TYPE_MIN && 8316 ftype < MLX5_FLOW_TYPE_MAX); 8317 fops = flow_get_drv_ops(ftype); 8318 return fops->query(dev, flow, action, count, error); 8319 } 8320 return -1; 8321 } 8322 8323 #ifdef HAVE_IBV_FLOW_DV_SUPPORT 8324 /** 8325 * Dump flow ipool data to file 8326 * 8327 * @param[in] dev 8328 * The pointer to Ethernet device. 8329 * @param[in] file 8330 * A pointer to a file for output. 8331 * @param[out] error 8332 * Perform verbose error reporting if not NULL. PMDs initialize this 8333 * structure in case of error only. 8334 * @return 8335 * 0 on success, a negative value otherwise. 8336 */ 8337 int 8338 mlx5_flow_dev_dump_ipool(struct rte_eth_dev *dev, 8339 struct rte_flow *flow, FILE *file, 8340 struct rte_flow_error *error) 8341 { 8342 struct mlx5_priv *priv = dev->data->dev_private; 8343 struct mlx5_flow_dv_modify_hdr_resource *modify_hdr; 8344 struct mlx5_flow_dv_encap_decap_resource *encap_decap; 8345 uint32_t handle_idx; 8346 struct mlx5_flow_handle *dh; 8347 struct rte_flow_query_count count; 8348 uint32_t actions_num; 8349 const uint8_t *data; 8350 size_t size; 8351 uint64_t id; 8352 uint32_t type; 8353 void *action = NULL; 8354 8355 if (!flow) { 8356 return rte_flow_error_set(error, ENOENT, 8357 RTE_FLOW_ERROR_TYPE_UNSPECIFIED, 8358 NULL, 8359 "invalid flow handle"); 8360 } 8361 handle_idx = flow->dev_handles; 8362 while (handle_idx) { 8363 dh = mlx5_ipool_get(priv->sh->ipool 8364 [MLX5_IPOOL_MLX5_FLOW], handle_idx); 8365 if (!dh) 8366 continue; 8367 handle_idx = dh->next.next; 8368 8369 /* query counter */ 8370 type = DR_DUMP_REC_TYPE_PMD_COUNTER; 8371 flow_dv_query_count_ptr(dev, flow->counter, 8372 &action, error); 8373 if (action) { 8374 id = (uint64_t)(uintptr_t)action; 8375 if (!mlx5_flow_query_counter(dev, flow, &count, error)) 8376 save_dump_file(NULL, 0, type, 8377 id, (void *)&count, file); 8378 } 8379 /* Get modify_hdr and encap_decap buf from ipools. */ 8380 encap_decap = NULL; 8381 modify_hdr = dh->dvh.modify_hdr; 8382 8383 if (dh->dvh.rix_encap_decap) { 8384 encap_decap = mlx5_ipool_get(priv->sh->ipool 8385 [MLX5_IPOOL_DECAP_ENCAP], 8386 dh->dvh.rix_encap_decap); 8387 } 8388 if (modify_hdr) { 8389 data = (const uint8_t *)modify_hdr->actions; 8390 size = (size_t)(modify_hdr->actions_num) * 8; 8391 id = (uint64_t)(uintptr_t)modify_hdr->action; 8392 actions_num = modify_hdr->actions_num; 8393 type = DR_DUMP_REC_TYPE_PMD_MODIFY_HDR; 8394 save_dump_file(data, size, type, id, 8395 (void *)(&actions_num), file); 8396 } 8397 if (encap_decap) { 8398 data = encap_decap->buf; 8399 size = encap_decap->size; 8400 id = (uint64_t)(uintptr_t)encap_decap->action; 8401 type = DR_DUMP_REC_TYPE_PMD_PKT_REFORMAT; 8402 save_dump_file(data, size, type, 8403 id, NULL, file); 8404 } 8405 } 8406 return 0; 8407 } 8408 8409 /** 8410 * Dump all flow's encap_decap/modify_hdr/counter data to file 8411 * 8412 * @param[in] dev 8413 * The pointer to Ethernet device. 8414 * @param[in] file 8415 * A pointer to a file for output. 8416 * @param[out] error 8417 * Perform verbose error reporting if not NULL. PMDs initialize this 8418 * structure in case of error only. 8419 * @return 8420 * 0 on success, a negative value otherwise. 8421 */ 8422 static int 8423 mlx5_flow_dev_dump_sh_all(struct rte_eth_dev *dev, 8424 FILE *file, struct rte_flow_error *error) 8425 { 8426 struct mlx5_priv *priv = dev->data->dev_private; 8427 struct mlx5_dev_ctx_shared *sh = priv->sh; 8428 struct mlx5_hlist *h; 8429 struct mlx5_flow_dv_modify_hdr_resource *modify_hdr; 8430 struct mlx5_flow_dv_encap_decap_resource *encap_decap; 8431 struct rte_flow_query_count count; 8432 uint32_t actions_num; 8433 const uint8_t *data; 8434 size_t size; 8435 uint64_t id; 8436 uint32_t type; 8437 uint32_t i; 8438 uint32_t j; 8439 struct mlx5_list_inconst *l_inconst; 8440 struct mlx5_list_entry *e; 8441 int lcore_index; 8442 struct mlx5_flow_counter_mng *cmng = &priv->sh->cmng; 8443 uint32_t max; 8444 void *action; 8445 8446 /* encap_decap hlist is lcore_share, get global core cache. */ 8447 i = MLX5_LIST_GLOBAL; 8448 h = sh->encaps_decaps; 8449 if (h) { 8450 for (j = 0; j <= h->mask; j++) { 8451 l_inconst = &h->buckets[j].l; 8452 if (!l_inconst || !l_inconst->cache[i]) 8453 continue; 8454 8455 e = LIST_FIRST(&l_inconst->cache[i]->h); 8456 while (e) { 8457 encap_decap = 8458 (struct mlx5_flow_dv_encap_decap_resource *)e; 8459 data = encap_decap->buf; 8460 size = encap_decap->size; 8461 id = (uint64_t)(uintptr_t)encap_decap->action; 8462 type = DR_DUMP_REC_TYPE_PMD_PKT_REFORMAT; 8463 save_dump_file(data, size, type, 8464 id, NULL, file); 8465 e = LIST_NEXT(e, next); 8466 } 8467 } 8468 } 8469 8470 /* get modify_hdr */ 8471 h = sh->modify_cmds; 8472 if (h) { 8473 lcore_index = rte_lcore_index(rte_lcore_id()); 8474 if (unlikely(lcore_index == -1)) { 8475 lcore_index = MLX5_LIST_NLCORE; 8476 rte_spinlock_lock(&h->l_const.lcore_lock); 8477 } 8478 i = lcore_index; 8479 8480 for (j = 0; j <= h->mask; j++) { 8481 l_inconst = &h->buckets[j].l; 8482 if (!l_inconst || !l_inconst->cache[i]) 8483 continue; 8484 8485 e = LIST_FIRST(&l_inconst->cache[i]->h); 8486 while (e) { 8487 modify_hdr = 8488 (struct mlx5_flow_dv_modify_hdr_resource *)e; 8489 data = (const uint8_t *)modify_hdr->actions; 8490 size = (size_t)(modify_hdr->actions_num) * 8; 8491 actions_num = modify_hdr->actions_num; 8492 id = (uint64_t)(uintptr_t)modify_hdr->action; 8493 type = DR_DUMP_REC_TYPE_PMD_MODIFY_HDR; 8494 save_dump_file(data, size, type, id, 8495 (void *)(&actions_num), file); 8496 e = LIST_NEXT(e, next); 8497 } 8498 } 8499 8500 if (unlikely(lcore_index == MLX5_LIST_NLCORE)) 8501 rte_spinlock_unlock(&h->l_const.lcore_lock); 8502 } 8503 8504 /* get counter */ 8505 MLX5_ASSERT(cmng->n_valid <= cmng->n); 8506 max = MLX5_COUNTERS_PER_POOL * cmng->n_valid; 8507 for (j = 1; j <= max; j++) { 8508 action = NULL; 8509 flow_dv_query_count_ptr(dev, j, &action, error); 8510 if (action) { 8511 if (!flow_dv_query_count(dev, j, &count, error)) { 8512 type = DR_DUMP_REC_TYPE_PMD_COUNTER; 8513 id = (uint64_t)(uintptr_t)action; 8514 save_dump_file(NULL, 0, type, 8515 id, (void *)&count, file); 8516 } 8517 } 8518 } 8519 return 0; 8520 } 8521 #endif 8522 8523 /** 8524 * Dump flow raw hw data to file 8525 * 8526 * @param[in] dev 8527 * The pointer to Ethernet device. 8528 * @param[in] file 8529 * A pointer to a file for output. 8530 * @param[out] error 8531 * Perform verbose error reporting if not NULL. PMDs initialize this 8532 * structure in case of error only. 8533 * @return 8534 * 0 on success, a nagative value otherwise. 8535 */ 8536 int 8537 mlx5_flow_dev_dump(struct rte_eth_dev *dev, struct rte_flow *flow_idx, 8538 FILE *file, 8539 struct rte_flow_error *error __rte_unused) 8540 { 8541 struct mlx5_priv *priv = dev->data->dev_private; 8542 struct mlx5_dev_ctx_shared *sh = priv->sh; 8543 uint32_t handle_idx; 8544 int ret; 8545 struct mlx5_flow_handle *dh; 8546 struct rte_flow *flow; 8547 8548 if (!priv->config.dv_flow_en) { 8549 if (fputs("device dv flow disabled\n", file) <= 0) 8550 return -errno; 8551 return -ENOTSUP; 8552 } 8553 8554 /* dump all */ 8555 if (!flow_idx) { 8556 #ifdef HAVE_IBV_FLOW_DV_SUPPORT 8557 if (mlx5_flow_dev_dump_sh_all(dev, file, error)) 8558 return -EINVAL; 8559 #endif 8560 return mlx5_devx_cmd_flow_dump(sh->fdb_domain, 8561 sh->rx_domain, 8562 sh->tx_domain, file); 8563 } 8564 /* dump one */ 8565 flow = mlx5_ipool_get(priv->flows[MLX5_FLOW_TYPE_GEN], 8566 (uintptr_t)(void *)flow_idx); 8567 if (!flow) 8568 return -EINVAL; 8569 8570 #ifdef HAVE_IBV_FLOW_DV_SUPPORT 8571 mlx5_flow_dev_dump_ipool(dev, flow, file, error); 8572 #endif 8573 handle_idx = flow->dev_handles; 8574 while (handle_idx) { 8575 dh = mlx5_ipool_get(priv->sh->ipool[MLX5_IPOOL_MLX5_FLOW], 8576 handle_idx); 8577 if (!dh) 8578 return -ENOENT; 8579 if (dh->drv_flow) { 8580 ret = mlx5_devx_cmd_flow_single_dump(dh->drv_flow, 8581 file); 8582 if (ret) 8583 return -ENOENT; 8584 } 8585 handle_idx = dh->next.next; 8586 } 8587 return 0; 8588 } 8589 8590 /** 8591 * Get aged-out flows. 8592 * 8593 * @param[in] dev 8594 * Pointer to the Ethernet device structure. 8595 * @param[in] context 8596 * The address of an array of pointers to the aged-out flows contexts. 8597 * @param[in] nb_countexts 8598 * The length of context array pointers. 8599 * @param[out] error 8600 * Perform verbose error reporting if not NULL. Initialized in case of 8601 * error only. 8602 * 8603 * @return 8604 * how many contexts get in success, otherwise negative errno value. 8605 * if nb_contexts is 0, return the amount of all aged contexts. 8606 * if nb_contexts is not 0 , return the amount of aged flows reported 8607 * in the context array. 8608 */ 8609 int 8610 mlx5_flow_get_aged_flows(struct rte_eth_dev *dev, void **contexts, 8611 uint32_t nb_contexts, struct rte_flow_error *error) 8612 { 8613 const struct mlx5_flow_driver_ops *fops; 8614 struct rte_flow_attr attr = { .transfer = 0 }; 8615 8616 if (flow_get_drv_type(dev, &attr) == MLX5_FLOW_TYPE_DV) { 8617 fops = flow_get_drv_ops(MLX5_FLOW_TYPE_DV); 8618 return fops->get_aged_flows(dev, contexts, nb_contexts, 8619 error); 8620 } 8621 DRV_LOG(ERR, 8622 "port %u get aged flows is not supported.", 8623 dev->data->port_id); 8624 return -ENOTSUP; 8625 } 8626 8627 /* Wrapper for driver action_validate op callback */ 8628 static int 8629 flow_drv_action_validate(struct rte_eth_dev *dev, 8630 const struct rte_flow_indir_action_conf *conf, 8631 const struct rte_flow_action *action, 8632 const struct mlx5_flow_driver_ops *fops, 8633 struct rte_flow_error *error) 8634 { 8635 static const char err_msg[] = "indirect action validation unsupported"; 8636 8637 if (!fops->action_validate) { 8638 DRV_LOG(ERR, "port %u %s.", dev->data->port_id, err_msg); 8639 rte_flow_error_set(error, ENOTSUP, RTE_FLOW_ERROR_TYPE_ACTION, 8640 NULL, err_msg); 8641 return -rte_errno; 8642 } 8643 return fops->action_validate(dev, conf, action, error); 8644 } 8645 8646 /** 8647 * Destroys the shared action by handle. 8648 * 8649 * @param dev 8650 * Pointer to Ethernet device structure. 8651 * @param[in] handle 8652 * Handle for the indirect action object to be destroyed. 8653 * @param[out] error 8654 * Perform verbose error reporting if not NULL. PMDs initialize this 8655 * structure in case of error only. 8656 * 8657 * @return 8658 * 0 on success, a negative errno value otherwise and rte_errno is set. 8659 * 8660 * @note: wrapper for driver action_create op callback. 8661 */ 8662 static int 8663 mlx5_action_handle_destroy(struct rte_eth_dev *dev, 8664 struct rte_flow_action_handle *handle, 8665 struct rte_flow_error *error) 8666 { 8667 static const char err_msg[] = "indirect action destruction unsupported"; 8668 struct rte_flow_attr attr = { .transfer = 0 }; 8669 const struct mlx5_flow_driver_ops *fops = 8670 flow_get_drv_ops(flow_get_drv_type(dev, &attr)); 8671 8672 if (!fops->action_destroy) { 8673 DRV_LOG(ERR, "port %u %s.", dev->data->port_id, err_msg); 8674 rte_flow_error_set(error, ENOTSUP, RTE_FLOW_ERROR_TYPE_ACTION, 8675 NULL, err_msg); 8676 return -rte_errno; 8677 } 8678 return fops->action_destroy(dev, handle, error); 8679 } 8680 8681 /* Wrapper for driver action_destroy op callback */ 8682 static int 8683 flow_drv_action_update(struct rte_eth_dev *dev, 8684 struct rte_flow_action_handle *handle, 8685 const void *update, 8686 const struct mlx5_flow_driver_ops *fops, 8687 struct rte_flow_error *error) 8688 { 8689 static const char err_msg[] = "indirect action update unsupported"; 8690 8691 if (!fops->action_update) { 8692 DRV_LOG(ERR, "port %u %s.", dev->data->port_id, err_msg); 8693 rte_flow_error_set(error, ENOTSUP, RTE_FLOW_ERROR_TYPE_ACTION, 8694 NULL, err_msg); 8695 return -rte_errno; 8696 } 8697 return fops->action_update(dev, handle, update, error); 8698 } 8699 8700 /* Wrapper for driver action_destroy op callback */ 8701 static int 8702 flow_drv_action_query(struct rte_eth_dev *dev, 8703 const struct rte_flow_action_handle *handle, 8704 void *data, 8705 const struct mlx5_flow_driver_ops *fops, 8706 struct rte_flow_error *error) 8707 { 8708 static const char err_msg[] = "indirect action query unsupported"; 8709 8710 if (!fops->action_query) { 8711 DRV_LOG(ERR, "port %u %s.", dev->data->port_id, err_msg); 8712 rte_flow_error_set(error, ENOTSUP, RTE_FLOW_ERROR_TYPE_ACTION, 8713 NULL, err_msg); 8714 return -rte_errno; 8715 } 8716 return fops->action_query(dev, handle, data, error); 8717 } 8718 8719 /** 8720 * Create indirect action for reuse in multiple flow rules. 8721 * 8722 * @param dev 8723 * Pointer to Ethernet device structure. 8724 * @param conf 8725 * Pointer to indirect action object configuration. 8726 * @param[in] action 8727 * Action configuration for indirect action object creation. 8728 * @param[out] error 8729 * Perform verbose error reporting if not NULL. PMDs initialize this 8730 * structure in case of error only. 8731 * @return 8732 * A valid handle in case of success, NULL otherwise and rte_errno is set. 8733 */ 8734 static struct rte_flow_action_handle * 8735 mlx5_action_handle_create(struct rte_eth_dev *dev, 8736 const struct rte_flow_indir_action_conf *conf, 8737 const struct rte_flow_action *action, 8738 struct rte_flow_error *error) 8739 { 8740 static const char err_msg[] = "indirect action creation unsupported"; 8741 struct rte_flow_attr attr = { .transfer = 0 }; 8742 const struct mlx5_flow_driver_ops *fops = 8743 flow_get_drv_ops(flow_get_drv_type(dev, &attr)); 8744 8745 if (flow_drv_action_validate(dev, conf, action, fops, error)) 8746 return NULL; 8747 if (!fops->action_create) { 8748 DRV_LOG(ERR, "port %u %s.", dev->data->port_id, err_msg); 8749 rte_flow_error_set(error, ENOTSUP, RTE_FLOW_ERROR_TYPE_ACTION, 8750 NULL, err_msg); 8751 return NULL; 8752 } 8753 return fops->action_create(dev, conf, action, error); 8754 } 8755 8756 /** 8757 * Updates inplace the indirect action configuration pointed by *handle* 8758 * with the configuration provided as *update* argument. 8759 * The update of the indirect action configuration effects all flow rules 8760 * reusing the action via handle. 8761 * 8762 * @param dev 8763 * Pointer to Ethernet device structure. 8764 * @param[in] handle 8765 * Handle for the indirect action to be updated. 8766 * @param[in] update 8767 * Action specification used to modify the action pointed by handle. 8768 * *update* could be of same type with the action pointed by the *handle* 8769 * handle argument, or some other structures like a wrapper, depending on 8770 * the indirect action type. 8771 * @param[out] error 8772 * Perform verbose error reporting if not NULL. PMDs initialize this 8773 * structure in case of error only. 8774 * 8775 * @return 8776 * 0 on success, a negative errno value otherwise and rte_errno is set. 8777 */ 8778 static int 8779 mlx5_action_handle_update(struct rte_eth_dev *dev, 8780 struct rte_flow_action_handle *handle, 8781 const void *update, 8782 struct rte_flow_error *error) 8783 { 8784 struct rte_flow_attr attr = { .transfer = 0 }; 8785 const struct mlx5_flow_driver_ops *fops = 8786 flow_get_drv_ops(flow_get_drv_type(dev, &attr)); 8787 int ret; 8788 8789 ret = flow_drv_action_validate(dev, NULL, 8790 (const struct rte_flow_action *)update, fops, error); 8791 if (ret) 8792 return ret; 8793 return flow_drv_action_update(dev, handle, update, fops, 8794 error); 8795 } 8796 8797 /** 8798 * Query the indirect action by handle. 8799 * 8800 * This function allows retrieving action-specific data such as counters. 8801 * Data is gathered by special action which may be present/referenced in 8802 * more than one flow rule definition. 8803 * 8804 * see @RTE_FLOW_ACTION_TYPE_COUNT 8805 * 8806 * @param dev 8807 * Pointer to Ethernet device structure. 8808 * @param[in] handle 8809 * Handle for the indirect action to query. 8810 * @param[in, out] data 8811 * Pointer to storage for the associated query data type. 8812 * @param[out] error 8813 * Perform verbose error reporting if not NULL. PMDs initialize this 8814 * structure in case of error only. 8815 * 8816 * @return 8817 * 0 on success, a negative errno value otherwise and rte_errno is set. 8818 */ 8819 static int 8820 mlx5_action_handle_query(struct rte_eth_dev *dev, 8821 const struct rte_flow_action_handle *handle, 8822 void *data, 8823 struct rte_flow_error *error) 8824 { 8825 struct rte_flow_attr attr = { .transfer = 0 }; 8826 const struct mlx5_flow_driver_ops *fops = 8827 flow_get_drv_ops(flow_get_drv_type(dev, &attr)); 8828 8829 return flow_drv_action_query(dev, handle, data, fops, error); 8830 } 8831 8832 /** 8833 * Destroy all indirect actions (shared RSS). 8834 * 8835 * @param dev 8836 * Pointer to Ethernet device. 8837 * 8838 * @return 8839 * 0 on success, a negative errno value otherwise and rte_errno is set. 8840 */ 8841 int 8842 mlx5_action_handle_flush(struct rte_eth_dev *dev) 8843 { 8844 struct rte_flow_error error; 8845 struct mlx5_priv *priv = dev->data->dev_private; 8846 struct mlx5_shared_action_rss *shared_rss; 8847 int ret = 0; 8848 uint32_t idx; 8849 8850 ILIST_FOREACH(priv->sh->ipool[MLX5_IPOOL_RSS_SHARED_ACTIONS], 8851 priv->rss_shared_actions, idx, shared_rss, next) { 8852 ret |= mlx5_action_handle_destroy(dev, 8853 (struct rte_flow_action_handle *)(uintptr_t)idx, &error); 8854 } 8855 return ret; 8856 } 8857 8858 /** 8859 * Validate existing indirect actions against current device configuration 8860 * and attach them to device resources. 8861 * 8862 * @param dev 8863 * Pointer to Ethernet device. 8864 * 8865 * @return 8866 * 0 on success, a negative errno value otherwise and rte_errno is set. 8867 */ 8868 int 8869 mlx5_action_handle_attach(struct rte_eth_dev *dev) 8870 { 8871 struct mlx5_priv *priv = dev->data->dev_private; 8872 struct mlx5_indexed_pool *ipool = 8873 priv->sh->ipool[MLX5_IPOOL_RSS_SHARED_ACTIONS]; 8874 struct mlx5_shared_action_rss *shared_rss, *shared_rss_last; 8875 int ret = 0; 8876 uint32_t idx; 8877 8878 ILIST_FOREACH(ipool, priv->rss_shared_actions, idx, shared_rss, next) { 8879 struct mlx5_ind_table_obj *ind_tbl = shared_rss->ind_tbl; 8880 const char *message; 8881 uint32_t queue_idx; 8882 8883 ret = mlx5_validate_rss_queues(dev, ind_tbl->queues, 8884 ind_tbl->queues_n, 8885 &message, &queue_idx); 8886 if (ret != 0) { 8887 DRV_LOG(ERR, "Port %u cannot use queue %u in RSS: %s", 8888 dev->data->port_id, ind_tbl->queues[queue_idx], 8889 message); 8890 break; 8891 } 8892 } 8893 if (ret != 0) 8894 return ret; 8895 ILIST_FOREACH(ipool, priv->rss_shared_actions, idx, shared_rss, next) { 8896 struct mlx5_ind_table_obj *ind_tbl = shared_rss->ind_tbl; 8897 8898 ret = mlx5_ind_table_obj_attach(dev, ind_tbl); 8899 if (ret != 0) { 8900 DRV_LOG(ERR, "Port %u could not attach " 8901 "indirection table obj %p", 8902 dev->data->port_id, (void *)ind_tbl); 8903 goto error; 8904 } 8905 } 8906 return 0; 8907 error: 8908 shared_rss_last = shared_rss; 8909 ILIST_FOREACH(ipool, priv->rss_shared_actions, idx, shared_rss, next) { 8910 struct mlx5_ind_table_obj *ind_tbl = shared_rss->ind_tbl; 8911 8912 if (shared_rss == shared_rss_last) 8913 break; 8914 if (mlx5_ind_table_obj_detach(dev, ind_tbl) != 0) 8915 DRV_LOG(CRIT, "Port %u could not detach " 8916 "indirection table obj %p on rollback", 8917 dev->data->port_id, (void *)ind_tbl); 8918 } 8919 return ret; 8920 } 8921 8922 /** 8923 * Detach indirect actions of the device from its resources. 8924 * 8925 * @param dev 8926 * Pointer to Ethernet device. 8927 * 8928 * @return 8929 * 0 on success, a negative errno value otherwise and rte_errno is set. 8930 */ 8931 int 8932 mlx5_action_handle_detach(struct rte_eth_dev *dev) 8933 { 8934 struct mlx5_priv *priv = dev->data->dev_private; 8935 struct mlx5_indexed_pool *ipool = 8936 priv->sh->ipool[MLX5_IPOOL_RSS_SHARED_ACTIONS]; 8937 struct mlx5_shared_action_rss *shared_rss, *shared_rss_last; 8938 int ret = 0; 8939 uint32_t idx; 8940 8941 ILIST_FOREACH(ipool, priv->rss_shared_actions, idx, shared_rss, next) { 8942 struct mlx5_ind_table_obj *ind_tbl = shared_rss->ind_tbl; 8943 8944 ret = mlx5_ind_table_obj_detach(dev, ind_tbl); 8945 if (ret != 0) { 8946 DRV_LOG(ERR, "Port %u could not detach " 8947 "indirection table obj %p", 8948 dev->data->port_id, (void *)ind_tbl); 8949 goto error; 8950 } 8951 } 8952 return 0; 8953 error: 8954 shared_rss_last = shared_rss; 8955 ILIST_FOREACH(ipool, priv->rss_shared_actions, idx, shared_rss, next) { 8956 struct mlx5_ind_table_obj *ind_tbl = shared_rss->ind_tbl; 8957 8958 if (shared_rss == shared_rss_last) 8959 break; 8960 if (mlx5_ind_table_obj_attach(dev, ind_tbl) != 0) 8961 DRV_LOG(CRIT, "Port %u could not attach " 8962 "indirection table obj %p on rollback", 8963 dev->data->port_id, (void *)ind_tbl); 8964 } 8965 return ret; 8966 } 8967 8968 #ifndef HAVE_MLX5DV_DR 8969 #define MLX5_DOMAIN_SYNC_FLOW ((1 << 0) | (1 << 1)) 8970 #else 8971 #define MLX5_DOMAIN_SYNC_FLOW \ 8972 (MLX5DV_DR_DOMAIN_SYNC_FLAGS_SW | MLX5DV_DR_DOMAIN_SYNC_FLAGS_HW) 8973 #endif 8974 8975 int rte_pmd_mlx5_sync_flow(uint16_t port_id, uint32_t domains) 8976 { 8977 struct rte_eth_dev *dev = &rte_eth_devices[port_id]; 8978 const struct mlx5_flow_driver_ops *fops; 8979 int ret; 8980 struct rte_flow_attr attr = { .transfer = 0 }; 8981 8982 fops = flow_get_drv_ops(flow_get_drv_type(dev, &attr)); 8983 ret = fops->sync_domain(dev, domains, MLX5_DOMAIN_SYNC_FLOW); 8984 if (ret > 0) 8985 ret = -ret; 8986 return ret; 8987 } 8988 8989 const struct mlx5_flow_tunnel * 8990 mlx5_get_tof(const struct rte_flow_item *item, 8991 const struct rte_flow_action *action, 8992 enum mlx5_tof_rule_type *rule_type) 8993 { 8994 for (; item->type != RTE_FLOW_ITEM_TYPE_END; item++) { 8995 if (item->type == (typeof(item->type)) 8996 MLX5_RTE_FLOW_ITEM_TYPE_TUNNEL) { 8997 *rule_type = MLX5_TUNNEL_OFFLOAD_MATCH_RULE; 8998 return flow_items_to_tunnel(item); 8999 } 9000 } 9001 for (; action->conf != RTE_FLOW_ACTION_TYPE_END; action++) { 9002 if (action->type == (typeof(action->type)) 9003 MLX5_RTE_FLOW_ACTION_TYPE_TUNNEL_SET) { 9004 *rule_type = MLX5_TUNNEL_OFFLOAD_SET_RULE; 9005 return flow_actions_to_tunnel(action); 9006 } 9007 } 9008 return NULL; 9009 } 9010 9011 /** 9012 * tunnel offload functionalilty is defined for DV environment only 9013 */ 9014 #ifdef HAVE_IBV_FLOW_DV_SUPPORT 9015 __extension__ 9016 union tunnel_offload_mark { 9017 uint32_t val; 9018 struct { 9019 uint32_t app_reserve:8; 9020 uint32_t table_id:15; 9021 uint32_t transfer:1; 9022 uint32_t _unused_:8; 9023 }; 9024 }; 9025 9026 static bool 9027 mlx5_access_tunnel_offload_db 9028 (struct rte_eth_dev *dev, 9029 bool (*match)(struct rte_eth_dev *, 9030 struct mlx5_flow_tunnel *, const void *), 9031 void (*hit)(struct rte_eth_dev *, struct mlx5_flow_tunnel *, void *), 9032 void (*miss)(struct rte_eth_dev *, void *), 9033 void *ctx, bool lock_op); 9034 9035 static int 9036 flow_tunnel_add_default_miss(struct rte_eth_dev *dev, 9037 struct rte_flow *flow, 9038 const struct rte_flow_attr *attr, 9039 const struct rte_flow_action *app_actions, 9040 uint32_t flow_idx, 9041 const struct mlx5_flow_tunnel *tunnel, 9042 struct tunnel_default_miss_ctx *ctx, 9043 struct rte_flow_error *error) 9044 { 9045 struct mlx5_priv *priv = dev->data->dev_private; 9046 struct mlx5_flow *dev_flow; 9047 struct rte_flow_attr miss_attr = *attr; 9048 const struct rte_flow_item miss_items[2] = { 9049 { 9050 .type = RTE_FLOW_ITEM_TYPE_ETH, 9051 .spec = NULL, 9052 .last = NULL, 9053 .mask = NULL 9054 }, 9055 { 9056 .type = RTE_FLOW_ITEM_TYPE_END, 9057 .spec = NULL, 9058 .last = NULL, 9059 .mask = NULL 9060 } 9061 }; 9062 union tunnel_offload_mark mark_id; 9063 struct rte_flow_action_mark miss_mark; 9064 struct rte_flow_action miss_actions[3] = { 9065 [0] = { .type = RTE_FLOW_ACTION_TYPE_MARK, .conf = &miss_mark }, 9066 [2] = { .type = RTE_FLOW_ACTION_TYPE_END, .conf = NULL } 9067 }; 9068 const struct rte_flow_action_jump *jump_data; 9069 uint32_t i, flow_table = 0; /* prevent compilation warning */ 9070 struct flow_grp_info grp_info = { 9071 .external = 1, 9072 .transfer = attr->transfer, 9073 .fdb_def_rule = !!priv->fdb_def_rule, 9074 .std_tbl_fix = 0, 9075 }; 9076 int ret; 9077 9078 if (!attr->transfer) { 9079 uint32_t q_size; 9080 9081 miss_actions[1].type = RTE_FLOW_ACTION_TYPE_RSS; 9082 q_size = priv->reta_idx_n * sizeof(ctx->queue[0]); 9083 ctx->queue = mlx5_malloc(MLX5_MEM_SYS | MLX5_MEM_ZERO, q_size, 9084 0, SOCKET_ID_ANY); 9085 if (!ctx->queue) 9086 return rte_flow_error_set 9087 (error, ENOMEM, 9088 RTE_FLOW_ERROR_TYPE_ACTION_CONF, 9089 NULL, "invalid default miss RSS"); 9090 ctx->action_rss.func = RTE_ETH_HASH_FUNCTION_DEFAULT, 9091 ctx->action_rss.level = 0, 9092 ctx->action_rss.types = priv->rss_conf.rss_hf, 9093 ctx->action_rss.key_len = priv->rss_conf.rss_key_len, 9094 ctx->action_rss.queue_num = priv->reta_idx_n, 9095 ctx->action_rss.key = priv->rss_conf.rss_key, 9096 ctx->action_rss.queue = ctx->queue; 9097 if (!priv->reta_idx_n || !priv->rxqs_n) 9098 return rte_flow_error_set 9099 (error, EINVAL, 9100 RTE_FLOW_ERROR_TYPE_ACTION_CONF, 9101 NULL, "invalid port configuration"); 9102 if (!(dev->data->dev_conf.rxmode.mq_mode & RTE_ETH_MQ_RX_RSS_FLAG)) 9103 ctx->action_rss.types = 0; 9104 for (i = 0; i != priv->reta_idx_n; ++i) 9105 ctx->queue[i] = (*priv->reta_idx)[i]; 9106 } else { 9107 miss_actions[1].type = RTE_FLOW_ACTION_TYPE_JUMP; 9108 ctx->miss_jump.group = MLX5_TNL_MISS_FDB_JUMP_GRP; 9109 } 9110 miss_actions[1].conf = (typeof(miss_actions[1].conf))ctx->raw; 9111 for (; app_actions->type != RTE_FLOW_ACTION_TYPE_JUMP; app_actions++); 9112 jump_data = app_actions->conf; 9113 miss_attr.priority = MLX5_TNL_MISS_RULE_PRIORITY; 9114 miss_attr.group = jump_data->group; 9115 ret = mlx5_flow_group_to_table(dev, tunnel, jump_data->group, 9116 &flow_table, &grp_info, error); 9117 if (ret) 9118 return rte_flow_error_set(error, EINVAL, 9119 RTE_FLOW_ERROR_TYPE_ACTION_CONF, 9120 NULL, "invalid tunnel id"); 9121 mark_id.app_reserve = 0; 9122 mark_id.table_id = tunnel_flow_tbl_to_id(flow_table); 9123 mark_id.transfer = !!attr->transfer; 9124 mark_id._unused_ = 0; 9125 miss_mark.id = mark_id.val; 9126 dev_flow = flow_drv_prepare(dev, flow, &miss_attr, 9127 miss_items, miss_actions, flow_idx, error); 9128 if (!dev_flow) 9129 return -rte_errno; 9130 dev_flow->flow = flow; 9131 dev_flow->external = true; 9132 dev_flow->tunnel = tunnel; 9133 dev_flow->tof_type = MLX5_TUNNEL_OFFLOAD_MISS_RULE; 9134 /* Subflow object was created, we must include one in the list. */ 9135 SILIST_INSERT(&flow->dev_handles, dev_flow->handle_idx, 9136 dev_flow->handle, next); 9137 DRV_LOG(DEBUG, 9138 "port %u tunnel type=%d id=%u miss rule priority=%u group=%u", 9139 dev->data->port_id, tunnel->app_tunnel.type, 9140 tunnel->tunnel_id, miss_attr.priority, miss_attr.group); 9141 ret = flow_drv_translate(dev, dev_flow, &miss_attr, miss_items, 9142 miss_actions, error); 9143 if (!ret) 9144 ret = flow_mreg_update_copy_table(dev, flow, miss_actions, 9145 error); 9146 9147 return ret; 9148 } 9149 9150 static const struct mlx5_flow_tbl_data_entry * 9151 tunnel_mark_decode(struct rte_eth_dev *dev, uint32_t mark) 9152 { 9153 struct mlx5_priv *priv = dev->data->dev_private; 9154 struct mlx5_dev_ctx_shared *sh = priv->sh; 9155 struct mlx5_list_entry *he; 9156 union tunnel_offload_mark mbits = { .val = mark }; 9157 union mlx5_flow_tbl_key table_key = { 9158 { 9159 .level = tunnel_id_to_flow_tbl(mbits.table_id), 9160 .id = 0, 9161 .reserved = 0, 9162 .dummy = 0, 9163 .is_fdb = !!mbits.transfer, 9164 .is_egress = 0, 9165 } 9166 }; 9167 struct mlx5_flow_cb_ctx ctx = { 9168 .data = &table_key.v64, 9169 }; 9170 9171 he = mlx5_hlist_lookup(sh->flow_tbls, table_key.v64, &ctx); 9172 return he ? 9173 container_of(he, struct mlx5_flow_tbl_data_entry, entry) : NULL; 9174 } 9175 9176 static void 9177 mlx5_flow_tunnel_grp2tbl_remove_cb(void *tool_ctx, 9178 struct mlx5_list_entry *entry) 9179 { 9180 struct mlx5_dev_ctx_shared *sh = tool_ctx; 9181 struct tunnel_tbl_entry *tte = container_of(entry, typeof(*tte), hash); 9182 9183 mlx5_ipool_free(sh->ipool[MLX5_IPOOL_TNL_TBL_ID], 9184 tunnel_flow_tbl_to_id(tte->flow_table)); 9185 mlx5_free(tte); 9186 } 9187 9188 static int 9189 mlx5_flow_tunnel_grp2tbl_match_cb(void *tool_ctx __rte_unused, 9190 struct mlx5_list_entry *entry, void *cb_ctx) 9191 { 9192 struct mlx5_flow_cb_ctx *ctx = cb_ctx; 9193 union tunnel_tbl_key tbl = { 9194 .val = *(uint64_t *)(ctx->data), 9195 }; 9196 struct tunnel_tbl_entry *tte = container_of(entry, typeof(*tte), hash); 9197 9198 return tbl.tunnel_id != tte->tunnel_id || tbl.group != tte->group; 9199 } 9200 9201 static struct mlx5_list_entry * 9202 mlx5_flow_tunnel_grp2tbl_create_cb(void *tool_ctx, void *cb_ctx) 9203 { 9204 struct mlx5_dev_ctx_shared *sh = tool_ctx; 9205 struct mlx5_flow_cb_ctx *ctx = cb_ctx; 9206 struct tunnel_tbl_entry *tte; 9207 union tunnel_tbl_key tbl = { 9208 .val = *(uint64_t *)(ctx->data), 9209 }; 9210 9211 tte = mlx5_malloc(MLX5_MEM_SYS | MLX5_MEM_ZERO, 9212 sizeof(*tte), 0, 9213 SOCKET_ID_ANY); 9214 if (!tte) 9215 goto err; 9216 mlx5_ipool_malloc(sh->ipool[MLX5_IPOOL_TNL_TBL_ID], 9217 &tte->flow_table); 9218 if (tte->flow_table >= MLX5_MAX_TABLES) { 9219 DRV_LOG(ERR, "Tunnel TBL ID %d exceed max limit.", 9220 tte->flow_table); 9221 mlx5_ipool_free(sh->ipool[MLX5_IPOOL_TNL_TBL_ID], 9222 tte->flow_table); 9223 goto err; 9224 } else if (!tte->flow_table) { 9225 goto err; 9226 } 9227 tte->flow_table = tunnel_id_to_flow_tbl(tte->flow_table); 9228 tte->tunnel_id = tbl.tunnel_id; 9229 tte->group = tbl.group; 9230 return &tte->hash; 9231 err: 9232 if (tte) 9233 mlx5_free(tte); 9234 return NULL; 9235 } 9236 9237 static struct mlx5_list_entry * 9238 mlx5_flow_tunnel_grp2tbl_clone_cb(void *tool_ctx __rte_unused, 9239 struct mlx5_list_entry *oentry, 9240 void *cb_ctx __rte_unused) 9241 { 9242 struct tunnel_tbl_entry *tte = mlx5_malloc(MLX5_MEM_SYS, sizeof(*tte), 9243 0, SOCKET_ID_ANY); 9244 9245 if (!tte) 9246 return NULL; 9247 memcpy(tte, oentry, sizeof(*tte)); 9248 return &tte->hash; 9249 } 9250 9251 static void 9252 mlx5_flow_tunnel_grp2tbl_clone_free_cb(void *tool_ctx __rte_unused, 9253 struct mlx5_list_entry *entry) 9254 { 9255 struct tunnel_tbl_entry *tte = container_of(entry, typeof(*tte), hash); 9256 9257 mlx5_free(tte); 9258 } 9259 9260 static uint32_t 9261 tunnel_flow_group_to_flow_table(struct rte_eth_dev *dev, 9262 const struct mlx5_flow_tunnel *tunnel, 9263 uint32_t group, uint32_t *table, 9264 struct rte_flow_error *error) 9265 { 9266 struct mlx5_list_entry *he; 9267 struct tunnel_tbl_entry *tte; 9268 union tunnel_tbl_key key = { 9269 .tunnel_id = tunnel ? tunnel->tunnel_id : 0, 9270 .group = group 9271 }; 9272 struct mlx5_flow_tunnel_hub *thub = mlx5_tunnel_hub(dev); 9273 struct mlx5_hlist *group_hash; 9274 struct mlx5_flow_cb_ctx ctx = { 9275 .data = &key.val, 9276 }; 9277 9278 group_hash = tunnel ? tunnel->groups : thub->groups; 9279 he = mlx5_hlist_register(group_hash, key.val, &ctx); 9280 if (!he) 9281 return rte_flow_error_set(error, EINVAL, 9282 RTE_FLOW_ERROR_TYPE_ATTR_GROUP, 9283 NULL, 9284 "tunnel group index not supported"); 9285 tte = container_of(he, typeof(*tte), hash); 9286 *table = tte->flow_table; 9287 DRV_LOG(DEBUG, "port %u tunnel %u group=%#x table=%#x", 9288 dev->data->port_id, key.tunnel_id, group, *table); 9289 return 0; 9290 } 9291 9292 static void 9293 mlx5_flow_tunnel_free(struct rte_eth_dev *dev, 9294 struct mlx5_flow_tunnel *tunnel) 9295 { 9296 struct mlx5_priv *priv = dev->data->dev_private; 9297 struct mlx5_indexed_pool *ipool; 9298 9299 DRV_LOG(DEBUG, "port %u release pmd tunnel id=0x%x", 9300 dev->data->port_id, tunnel->tunnel_id); 9301 LIST_REMOVE(tunnel, chain); 9302 mlx5_hlist_destroy(tunnel->groups); 9303 ipool = priv->sh->ipool[MLX5_IPOOL_TUNNEL_ID]; 9304 mlx5_ipool_free(ipool, tunnel->tunnel_id); 9305 } 9306 9307 static bool 9308 mlx5_access_tunnel_offload_db 9309 (struct rte_eth_dev *dev, 9310 bool (*match)(struct rte_eth_dev *, 9311 struct mlx5_flow_tunnel *, const void *), 9312 void (*hit)(struct rte_eth_dev *, struct mlx5_flow_tunnel *, void *), 9313 void (*miss)(struct rte_eth_dev *, void *), 9314 void *ctx, bool lock_op) 9315 { 9316 bool verdict = false; 9317 struct mlx5_flow_tunnel_hub *thub = mlx5_tunnel_hub(dev); 9318 struct mlx5_flow_tunnel *tunnel; 9319 9320 rte_spinlock_lock(&thub->sl); 9321 LIST_FOREACH(tunnel, &thub->tunnels, chain) { 9322 verdict = match(dev, tunnel, (const void *)ctx); 9323 if (verdict) 9324 break; 9325 } 9326 if (!lock_op) 9327 rte_spinlock_unlock(&thub->sl); 9328 if (verdict && hit) 9329 hit(dev, tunnel, ctx); 9330 if (!verdict && miss) 9331 miss(dev, ctx); 9332 if (lock_op) 9333 rte_spinlock_unlock(&thub->sl); 9334 9335 return verdict; 9336 } 9337 9338 struct tunnel_db_find_tunnel_id_ctx { 9339 uint32_t tunnel_id; 9340 struct mlx5_flow_tunnel *tunnel; 9341 }; 9342 9343 static bool 9344 find_tunnel_id_match(struct rte_eth_dev *dev, 9345 struct mlx5_flow_tunnel *tunnel, const void *x) 9346 { 9347 const struct tunnel_db_find_tunnel_id_ctx *ctx = x; 9348 9349 RTE_SET_USED(dev); 9350 return tunnel->tunnel_id == ctx->tunnel_id; 9351 } 9352 9353 static void 9354 find_tunnel_id_hit(struct rte_eth_dev *dev, 9355 struct mlx5_flow_tunnel *tunnel, void *x) 9356 { 9357 struct tunnel_db_find_tunnel_id_ctx *ctx = x; 9358 RTE_SET_USED(dev); 9359 ctx->tunnel = tunnel; 9360 } 9361 9362 static struct mlx5_flow_tunnel * 9363 mlx5_find_tunnel_id(struct rte_eth_dev *dev, uint32_t id) 9364 { 9365 struct tunnel_db_find_tunnel_id_ctx ctx = { 9366 .tunnel_id = id, 9367 }; 9368 9369 mlx5_access_tunnel_offload_db(dev, find_tunnel_id_match, 9370 find_tunnel_id_hit, NULL, &ctx, true); 9371 9372 return ctx.tunnel; 9373 } 9374 9375 static struct mlx5_flow_tunnel * 9376 mlx5_flow_tunnel_allocate(struct rte_eth_dev *dev, 9377 const struct rte_flow_tunnel *app_tunnel) 9378 { 9379 struct mlx5_priv *priv = dev->data->dev_private; 9380 struct mlx5_indexed_pool *ipool; 9381 struct mlx5_flow_tunnel *tunnel; 9382 uint32_t id; 9383 9384 ipool = priv->sh->ipool[MLX5_IPOOL_TUNNEL_ID]; 9385 tunnel = mlx5_ipool_zmalloc(ipool, &id); 9386 if (!tunnel) 9387 return NULL; 9388 if (id >= MLX5_MAX_TUNNELS) { 9389 mlx5_ipool_free(ipool, id); 9390 DRV_LOG(ERR, "Tunnel ID %d exceed max limit.", id); 9391 return NULL; 9392 } 9393 tunnel->groups = mlx5_hlist_create("tunnel groups", 64, false, true, 9394 priv->sh, 9395 mlx5_flow_tunnel_grp2tbl_create_cb, 9396 mlx5_flow_tunnel_grp2tbl_match_cb, 9397 mlx5_flow_tunnel_grp2tbl_remove_cb, 9398 mlx5_flow_tunnel_grp2tbl_clone_cb, 9399 mlx5_flow_tunnel_grp2tbl_clone_free_cb); 9400 if (!tunnel->groups) { 9401 mlx5_ipool_free(ipool, id); 9402 return NULL; 9403 } 9404 /* initiate new PMD tunnel */ 9405 memcpy(&tunnel->app_tunnel, app_tunnel, sizeof(*app_tunnel)); 9406 tunnel->tunnel_id = id; 9407 tunnel->action.type = (typeof(tunnel->action.type)) 9408 MLX5_RTE_FLOW_ACTION_TYPE_TUNNEL_SET; 9409 tunnel->action.conf = tunnel; 9410 tunnel->item.type = (typeof(tunnel->item.type)) 9411 MLX5_RTE_FLOW_ITEM_TYPE_TUNNEL; 9412 tunnel->item.spec = tunnel; 9413 tunnel->item.last = NULL; 9414 tunnel->item.mask = NULL; 9415 9416 DRV_LOG(DEBUG, "port %u new pmd tunnel id=0x%x", 9417 dev->data->port_id, tunnel->tunnel_id); 9418 9419 return tunnel; 9420 } 9421 9422 struct tunnel_db_get_tunnel_ctx { 9423 const struct rte_flow_tunnel *app_tunnel; 9424 struct mlx5_flow_tunnel *tunnel; 9425 }; 9426 9427 static bool get_tunnel_match(struct rte_eth_dev *dev, 9428 struct mlx5_flow_tunnel *tunnel, const void *x) 9429 { 9430 const struct tunnel_db_get_tunnel_ctx *ctx = x; 9431 9432 RTE_SET_USED(dev); 9433 return !memcmp(ctx->app_tunnel, &tunnel->app_tunnel, 9434 sizeof(*ctx->app_tunnel)); 9435 } 9436 9437 static void get_tunnel_hit(struct rte_eth_dev *dev, 9438 struct mlx5_flow_tunnel *tunnel, void *x) 9439 { 9440 /* called under tunnel spinlock protection */ 9441 struct tunnel_db_get_tunnel_ctx *ctx = x; 9442 9443 RTE_SET_USED(dev); 9444 tunnel->refctn++; 9445 ctx->tunnel = tunnel; 9446 } 9447 9448 static void get_tunnel_miss(struct rte_eth_dev *dev, void *x) 9449 { 9450 /* called under tunnel spinlock protection */ 9451 struct mlx5_flow_tunnel_hub *thub = mlx5_tunnel_hub(dev); 9452 struct tunnel_db_get_tunnel_ctx *ctx = x; 9453 9454 rte_spinlock_unlock(&thub->sl); 9455 ctx->tunnel = mlx5_flow_tunnel_allocate(dev, ctx->app_tunnel); 9456 rte_spinlock_lock(&thub->sl); 9457 if (ctx->tunnel) { 9458 ctx->tunnel->refctn = 1; 9459 LIST_INSERT_HEAD(&thub->tunnels, ctx->tunnel, chain); 9460 } 9461 } 9462 9463 9464 static int 9465 mlx5_get_flow_tunnel(struct rte_eth_dev *dev, 9466 const struct rte_flow_tunnel *app_tunnel, 9467 struct mlx5_flow_tunnel **tunnel) 9468 { 9469 struct tunnel_db_get_tunnel_ctx ctx = { 9470 .app_tunnel = app_tunnel, 9471 }; 9472 9473 mlx5_access_tunnel_offload_db(dev, get_tunnel_match, get_tunnel_hit, 9474 get_tunnel_miss, &ctx, true); 9475 *tunnel = ctx.tunnel; 9476 return ctx.tunnel ? 0 : -ENOMEM; 9477 } 9478 9479 void mlx5_release_tunnel_hub(struct mlx5_dev_ctx_shared *sh, uint16_t port_id) 9480 { 9481 struct mlx5_flow_tunnel_hub *thub = sh->tunnel_hub; 9482 9483 if (!thub) 9484 return; 9485 if (!LIST_EMPTY(&thub->tunnels)) 9486 DRV_LOG(WARNING, "port %u tunnels present", port_id); 9487 mlx5_hlist_destroy(thub->groups); 9488 mlx5_free(thub); 9489 } 9490 9491 int mlx5_alloc_tunnel_hub(struct mlx5_dev_ctx_shared *sh) 9492 { 9493 int err; 9494 struct mlx5_flow_tunnel_hub *thub; 9495 9496 thub = mlx5_malloc(MLX5_MEM_SYS | MLX5_MEM_ZERO, sizeof(*thub), 9497 0, SOCKET_ID_ANY); 9498 if (!thub) 9499 return -ENOMEM; 9500 LIST_INIT(&thub->tunnels); 9501 rte_spinlock_init(&thub->sl); 9502 thub->groups = mlx5_hlist_create("flow groups", 64, 9503 false, true, sh, 9504 mlx5_flow_tunnel_grp2tbl_create_cb, 9505 mlx5_flow_tunnel_grp2tbl_match_cb, 9506 mlx5_flow_tunnel_grp2tbl_remove_cb, 9507 mlx5_flow_tunnel_grp2tbl_clone_cb, 9508 mlx5_flow_tunnel_grp2tbl_clone_free_cb); 9509 if (!thub->groups) { 9510 err = -rte_errno; 9511 goto err; 9512 } 9513 sh->tunnel_hub = thub; 9514 9515 return 0; 9516 9517 err: 9518 if (thub->groups) 9519 mlx5_hlist_destroy(thub->groups); 9520 if (thub) 9521 mlx5_free(thub); 9522 return err; 9523 } 9524 9525 static inline int 9526 mlx5_flow_tunnel_validate(struct rte_eth_dev *dev, 9527 struct rte_flow_tunnel *tunnel, 9528 struct rte_flow_error *error) 9529 { 9530 struct mlx5_priv *priv = dev->data->dev_private; 9531 9532 if (!priv->config.dv_flow_en) 9533 return rte_flow_error_set(error, ENOTSUP, 9534 RTE_FLOW_ERROR_TYPE_ACTION_CONF, NULL, 9535 "flow DV interface is off"); 9536 if (!is_tunnel_offload_active(dev)) 9537 return rte_flow_error_set(error, ENOTSUP, 9538 RTE_FLOW_ERROR_TYPE_ACTION_CONF, NULL, 9539 "tunnel offload was not activated"); 9540 if (!tunnel) 9541 return rte_flow_error_set(error, EINVAL, 9542 RTE_FLOW_ERROR_TYPE_ACTION_CONF, NULL, 9543 "no application tunnel"); 9544 switch (tunnel->type) { 9545 default: 9546 return rte_flow_error_set(error, EINVAL, 9547 RTE_FLOW_ERROR_TYPE_ACTION_CONF, NULL, 9548 "unsupported tunnel type"); 9549 case RTE_FLOW_ITEM_TYPE_VXLAN: 9550 case RTE_FLOW_ITEM_TYPE_GRE: 9551 case RTE_FLOW_ITEM_TYPE_NVGRE: 9552 case RTE_FLOW_ITEM_TYPE_GENEVE: 9553 break; 9554 } 9555 return 0; 9556 } 9557 9558 static int 9559 mlx5_flow_tunnel_decap_set(struct rte_eth_dev *dev, 9560 struct rte_flow_tunnel *app_tunnel, 9561 struct rte_flow_action **actions, 9562 uint32_t *num_of_actions, 9563 struct rte_flow_error *error) 9564 { 9565 struct mlx5_flow_tunnel *tunnel; 9566 int ret = mlx5_flow_tunnel_validate(dev, app_tunnel, error); 9567 9568 if (ret) 9569 return ret; 9570 ret = mlx5_get_flow_tunnel(dev, app_tunnel, &tunnel); 9571 if (ret < 0) { 9572 return rte_flow_error_set(error, ret, 9573 RTE_FLOW_ERROR_TYPE_ACTION_CONF, NULL, 9574 "failed to initialize pmd tunnel"); 9575 } 9576 *actions = &tunnel->action; 9577 *num_of_actions = 1; 9578 return 0; 9579 } 9580 9581 static int 9582 mlx5_flow_tunnel_match(struct rte_eth_dev *dev, 9583 struct rte_flow_tunnel *app_tunnel, 9584 struct rte_flow_item **items, 9585 uint32_t *num_of_items, 9586 struct rte_flow_error *error) 9587 { 9588 struct mlx5_flow_tunnel *tunnel; 9589 int ret = mlx5_flow_tunnel_validate(dev, app_tunnel, error); 9590 9591 if (ret) 9592 return ret; 9593 ret = mlx5_get_flow_tunnel(dev, app_tunnel, &tunnel); 9594 if (ret < 0) { 9595 return rte_flow_error_set(error, ret, 9596 RTE_FLOW_ERROR_TYPE_HANDLE, NULL, 9597 "failed to initialize pmd tunnel"); 9598 } 9599 *items = &tunnel->item; 9600 *num_of_items = 1; 9601 return 0; 9602 } 9603 9604 struct tunnel_db_element_release_ctx { 9605 struct rte_flow_item *items; 9606 struct rte_flow_action *actions; 9607 uint32_t num_elements; 9608 struct rte_flow_error *error; 9609 int ret; 9610 }; 9611 9612 static bool 9613 tunnel_element_release_match(struct rte_eth_dev *dev, 9614 struct mlx5_flow_tunnel *tunnel, const void *x) 9615 { 9616 const struct tunnel_db_element_release_ctx *ctx = x; 9617 9618 RTE_SET_USED(dev); 9619 if (ctx->num_elements != 1) 9620 return false; 9621 else if (ctx->items) 9622 return ctx->items == &tunnel->item; 9623 else if (ctx->actions) 9624 return ctx->actions == &tunnel->action; 9625 9626 return false; 9627 } 9628 9629 static void 9630 tunnel_element_release_hit(struct rte_eth_dev *dev, 9631 struct mlx5_flow_tunnel *tunnel, void *x) 9632 { 9633 struct tunnel_db_element_release_ctx *ctx = x; 9634 ctx->ret = 0; 9635 if (!__atomic_sub_fetch(&tunnel->refctn, 1, __ATOMIC_RELAXED)) 9636 mlx5_flow_tunnel_free(dev, tunnel); 9637 } 9638 9639 static void 9640 tunnel_element_release_miss(struct rte_eth_dev *dev, void *x) 9641 { 9642 struct tunnel_db_element_release_ctx *ctx = x; 9643 RTE_SET_USED(dev); 9644 ctx->ret = rte_flow_error_set(ctx->error, EINVAL, 9645 RTE_FLOW_ERROR_TYPE_HANDLE, NULL, 9646 "invalid argument"); 9647 } 9648 9649 static int 9650 mlx5_flow_tunnel_item_release(struct rte_eth_dev *dev, 9651 struct rte_flow_item *pmd_items, 9652 uint32_t num_items, struct rte_flow_error *err) 9653 { 9654 struct tunnel_db_element_release_ctx ctx = { 9655 .items = pmd_items, 9656 .actions = NULL, 9657 .num_elements = num_items, 9658 .error = err, 9659 }; 9660 9661 mlx5_access_tunnel_offload_db(dev, tunnel_element_release_match, 9662 tunnel_element_release_hit, 9663 tunnel_element_release_miss, &ctx, false); 9664 9665 return ctx.ret; 9666 } 9667 9668 static int 9669 mlx5_flow_tunnel_action_release(struct rte_eth_dev *dev, 9670 struct rte_flow_action *pmd_actions, 9671 uint32_t num_actions, struct rte_flow_error *err) 9672 { 9673 struct tunnel_db_element_release_ctx ctx = { 9674 .items = NULL, 9675 .actions = pmd_actions, 9676 .num_elements = num_actions, 9677 .error = err, 9678 }; 9679 9680 mlx5_access_tunnel_offload_db(dev, tunnel_element_release_match, 9681 tunnel_element_release_hit, 9682 tunnel_element_release_miss, &ctx, false); 9683 9684 return ctx.ret; 9685 } 9686 9687 static int 9688 mlx5_flow_tunnel_get_restore_info(struct rte_eth_dev *dev, 9689 struct rte_mbuf *m, 9690 struct rte_flow_restore_info *info, 9691 struct rte_flow_error *err) 9692 { 9693 uint64_t ol_flags = m->ol_flags; 9694 const struct mlx5_flow_tbl_data_entry *tble; 9695 const uint64_t mask = RTE_MBUF_F_RX_FDIR | RTE_MBUF_F_RX_FDIR_ID; 9696 9697 if (!is_tunnel_offload_active(dev)) { 9698 info->flags = 0; 9699 return 0; 9700 } 9701 9702 if ((ol_flags & mask) != mask) 9703 goto err; 9704 tble = tunnel_mark_decode(dev, m->hash.fdir.hi); 9705 if (!tble) { 9706 DRV_LOG(DEBUG, "port %u invalid miss tunnel mark %#x", 9707 dev->data->port_id, m->hash.fdir.hi); 9708 goto err; 9709 } 9710 MLX5_ASSERT(tble->tunnel); 9711 memcpy(&info->tunnel, &tble->tunnel->app_tunnel, sizeof(info->tunnel)); 9712 info->group_id = tble->group_id; 9713 info->flags = RTE_FLOW_RESTORE_INFO_TUNNEL | 9714 RTE_FLOW_RESTORE_INFO_GROUP_ID | 9715 RTE_FLOW_RESTORE_INFO_ENCAPSULATED; 9716 9717 return 0; 9718 9719 err: 9720 return rte_flow_error_set(err, EINVAL, 9721 RTE_FLOW_ERROR_TYPE_UNSPECIFIED, NULL, 9722 "failed to get restore info"); 9723 } 9724 9725 #else /* HAVE_IBV_FLOW_DV_SUPPORT */ 9726 static int 9727 mlx5_flow_tunnel_decap_set(__rte_unused struct rte_eth_dev *dev, 9728 __rte_unused struct rte_flow_tunnel *app_tunnel, 9729 __rte_unused struct rte_flow_action **actions, 9730 __rte_unused uint32_t *num_of_actions, 9731 __rte_unused struct rte_flow_error *error) 9732 { 9733 return -ENOTSUP; 9734 } 9735 9736 static int 9737 mlx5_flow_tunnel_match(__rte_unused struct rte_eth_dev *dev, 9738 __rte_unused struct rte_flow_tunnel *app_tunnel, 9739 __rte_unused struct rte_flow_item **items, 9740 __rte_unused uint32_t *num_of_items, 9741 __rte_unused struct rte_flow_error *error) 9742 { 9743 return -ENOTSUP; 9744 } 9745 9746 static int 9747 mlx5_flow_tunnel_item_release(__rte_unused struct rte_eth_dev *dev, 9748 __rte_unused struct rte_flow_item *pmd_items, 9749 __rte_unused uint32_t num_items, 9750 __rte_unused struct rte_flow_error *err) 9751 { 9752 return -ENOTSUP; 9753 } 9754 9755 static int 9756 mlx5_flow_tunnel_action_release(__rte_unused struct rte_eth_dev *dev, 9757 __rte_unused struct rte_flow_action *pmd_action, 9758 __rte_unused uint32_t num_actions, 9759 __rte_unused struct rte_flow_error *err) 9760 { 9761 return -ENOTSUP; 9762 } 9763 9764 static int 9765 mlx5_flow_tunnel_get_restore_info(__rte_unused struct rte_eth_dev *dev, 9766 __rte_unused struct rte_mbuf *m, 9767 __rte_unused struct rte_flow_restore_info *i, 9768 __rte_unused struct rte_flow_error *err) 9769 { 9770 return -ENOTSUP; 9771 } 9772 9773 static int 9774 flow_tunnel_add_default_miss(__rte_unused struct rte_eth_dev *dev, 9775 __rte_unused struct rte_flow *flow, 9776 __rte_unused const struct rte_flow_attr *attr, 9777 __rte_unused const struct rte_flow_action *actions, 9778 __rte_unused uint32_t flow_idx, 9779 __rte_unused const struct mlx5_flow_tunnel *tunnel, 9780 __rte_unused struct tunnel_default_miss_ctx *ctx, 9781 __rte_unused struct rte_flow_error *error) 9782 { 9783 return -ENOTSUP; 9784 } 9785 9786 static struct mlx5_flow_tunnel * 9787 mlx5_find_tunnel_id(__rte_unused struct rte_eth_dev *dev, 9788 __rte_unused uint32_t id) 9789 { 9790 return NULL; 9791 } 9792 9793 static void 9794 mlx5_flow_tunnel_free(__rte_unused struct rte_eth_dev *dev, 9795 __rte_unused struct mlx5_flow_tunnel *tunnel) 9796 { 9797 } 9798 9799 static uint32_t 9800 tunnel_flow_group_to_flow_table(__rte_unused struct rte_eth_dev *dev, 9801 __rte_unused const struct mlx5_flow_tunnel *t, 9802 __rte_unused uint32_t group, 9803 __rte_unused uint32_t *table, 9804 struct rte_flow_error *error) 9805 { 9806 return rte_flow_error_set(error, ENOTSUP, 9807 RTE_FLOW_ERROR_TYPE_UNSPECIFIED, NULL, 9808 "tunnel offload requires DV support"); 9809 } 9810 9811 void 9812 mlx5_release_tunnel_hub(__rte_unused struct mlx5_dev_ctx_shared *sh, 9813 __rte_unused uint16_t port_id) 9814 { 9815 } 9816 #endif /* HAVE_IBV_FLOW_DV_SUPPORT */ 9817 9818 /* Flex flow item API */ 9819 static struct rte_flow_item_flex_handle * 9820 mlx5_flow_flex_item_create(struct rte_eth_dev *dev, 9821 const struct rte_flow_item_flex_conf *conf, 9822 struct rte_flow_error *error) 9823 { 9824 static const char err_msg[] = "flex item creation unsupported"; 9825 struct rte_flow_attr attr = { .transfer = 0 }; 9826 const struct mlx5_flow_driver_ops *fops = 9827 flow_get_drv_ops(flow_get_drv_type(dev, &attr)); 9828 9829 if (!fops->item_create) { 9830 DRV_LOG(ERR, "port %u %s.", dev->data->port_id, err_msg); 9831 rte_flow_error_set(error, ENOTSUP, RTE_FLOW_ERROR_TYPE_ACTION, 9832 NULL, err_msg); 9833 return NULL; 9834 } 9835 return fops->item_create(dev, conf, error); 9836 } 9837 9838 static int 9839 mlx5_flow_flex_item_release(struct rte_eth_dev *dev, 9840 const struct rte_flow_item_flex_handle *handle, 9841 struct rte_flow_error *error) 9842 { 9843 static const char err_msg[] = "flex item release unsupported"; 9844 struct rte_flow_attr attr = { .transfer = 0 }; 9845 const struct mlx5_flow_driver_ops *fops = 9846 flow_get_drv_ops(flow_get_drv_type(dev, &attr)); 9847 9848 if (!fops->item_release) { 9849 DRV_LOG(ERR, "port %u %s.", dev->data->port_id, err_msg); 9850 rte_flow_error_set(error, ENOTSUP, RTE_FLOW_ERROR_TYPE_ACTION, 9851 NULL, err_msg); 9852 return -rte_errno; 9853 } 9854 return fops->item_release(dev, handle, error); 9855 } 9856 9857 static void 9858 mlx5_dbg__print_pattern(const struct rte_flow_item *item) 9859 { 9860 int ret; 9861 struct rte_flow_error error; 9862 9863 for (; item->type != RTE_FLOW_ITEM_TYPE_END; item++) { 9864 char *item_name; 9865 ret = rte_flow_conv(RTE_FLOW_CONV_OP_ITEM_NAME_PTR, &item_name, 9866 sizeof(item_name), 9867 (void *)(uintptr_t)item->type, &error); 9868 if (ret > 0) 9869 printf("%s ", item_name); 9870 else 9871 printf("%d\n", (int)item->type); 9872 } 9873 printf("END\n"); 9874 } 9875 9876 static int 9877 mlx5_flow_is_std_vxlan_port(const struct rte_flow_item *udp_item) 9878 { 9879 const struct rte_flow_item_udp *spec = udp_item->spec; 9880 const struct rte_flow_item_udp *mask = udp_item->mask; 9881 uint16_t udp_dport = 0; 9882 9883 if (spec != NULL) { 9884 if (!mask) 9885 mask = &rte_flow_item_udp_mask; 9886 udp_dport = rte_be_to_cpu_16(spec->hdr.dst_port & 9887 mask->hdr.dst_port); 9888 } 9889 return (!udp_dport || udp_dport == MLX5_UDP_PORT_VXLAN); 9890 } 9891 9892 static const struct mlx5_flow_expand_node * 9893 mlx5_flow_expand_rss_adjust_node(const struct rte_flow_item *pattern, 9894 unsigned int item_idx, 9895 const struct mlx5_flow_expand_node graph[], 9896 const struct mlx5_flow_expand_node *node) 9897 { 9898 const struct rte_flow_item *item = pattern + item_idx, *prev_item; 9899 9900 if (item->type == RTE_FLOW_ITEM_TYPE_VXLAN && 9901 node != NULL && 9902 node->type == RTE_FLOW_ITEM_TYPE_VXLAN) { 9903 /* 9904 * The expansion node is VXLAN and it is also the last 9905 * expandable item in the pattern, so need to continue 9906 * expansion of the inner tunnel. 9907 */ 9908 MLX5_ASSERT(item_idx > 0); 9909 prev_item = pattern + item_idx - 1; 9910 MLX5_ASSERT(prev_item->type == RTE_FLOW_ITEM_TYPE_UDP); 9911 if (mlx5_flow_is_std_vxlan_port(prev_item)) 9912 return &graph[MLX5_EXPANSION_STD_VXLAN]; 9913 return &graph[MLX5_EXPANSION_L3_VXLAN]; 9914 } 9915 return node; 9916 } 9917 9918 /* Map of Verbs to Flow priority with 8 Verbs priorities. */ 9919 static const uint32_t priority_map_3[][MLX5_PRIORITY_MAP_MAX] = { 9920 { 0, 1, 2 }, { 2, 3, 4 }, { 5, 6, 7 }, 9921 }; 9922 9923 /* Map of Verbs to Flow priority with 16 Verbs priorities. */ 9924 static const uint32_t priority_map_5[][MLX5_PRIORITY_MAP_MAX] = { 9925 { 0, 1, 2 }, { 3, 4, 5 }, { 6, 7, 8 }, 9926 { 9, 10, 11 }, { 12, 13, 14 }, 9927 }; 9928 9929 /** 9930 * Discover the number of available flow priorities. 9931 * 9932 * @param dev 9933 * Ethernet device. 9934 * 9935 * @return 9936 * On success, number of available flow priorities. 9937 * On failure, a negative errno-style code and rte_errno is set. 9938 */ 9939 int 9940 mlx5_flow_discover_priorities(struct rte_eth_dev *dev) 9941 { 9942 static const uint16_t vprio[] = {8, 16}; 9943 const struct mlx5_priv *priv = dev->data->dev_private; 9944 const struct mlx5_flow_driver_ops *fops; 9945 enum mlx5_flow_drv_type type; 9946 int ret; 9947 9948 type = mlx5_flow_os_get_type(); 9949 if (type == MLX5_FLOW_TYPE_MAX) { 9950 type = MLX5_FLOW_TYPE_VERBS; 9951 if (priv->sh->devx && priv->config.dv_flow_en) 9952 type = MLX5_FLOW_TYPE_DV; 9953 } 9954 fops = flow_get_drv_ops(type); 9955 if (fops->discover_priorities == NULL) { 9956 DRV_LOG(ERR, "Priority discovery not supported"); 9957 rte_errno = ENOTSUP; 9958 return -rte_errno; 9959 } 9960 ret = fops->discover_priorities(dev, vprio, RTE_DIM(vprio)); 9961 if (ret < 0) 9962 return ret; 9963 switch (ret) { 9964 case 8: 9965 ret = RTE_DIM(priority_map_3); 9966 break; 9967 case 16: 9968 ret = RTE_DIM(priority_map_5); 9969 break; 9970 default: 9971 rte_errno = ENOTSUP; 9972 DRV_LOG(ERR, 9973 "port %u maximum priority: %d expected 8/16", 9974 dev->data->port_id, ret); 9975 return -rte_errno; 9976 } 9977 DRV_LOG(INFO, "port %u supported flow priorities:" 9978 " 0-%d for ingress or egress root table," 9979 " 0-%d for non-root table or transfer root table.", 9980 dev->data->port_id, ret - 2, 9981 MLX5_NON_ROOT_FLOW_MAX_PRIO - 1); 9982 return ret; 9983 } 9984 9985 /** 9986 * Adjust flow priority based on the highest layer and the request priority. 9987 * 9988 * @param[in] dev 9989 * Pointer to the Ethernet device structure. 9990 * @param[in] priority 9991 * The rule base priority. 9992 * @param[in] subpriority 9993 * The priority based on the items. 9994 * 9995 * @return 9996 * The new priority. 9997 */ 9998 uint32_t 9999 mlx5_flow_adjust_priority(struct rte_eth_dev *dev, int32_t priority, 10000 uint32_t subpriority) 10001 { 10002 uint32_t res = 0; 10003 struct mlx5_priv *priv = dev->data->dev_private; 10004 10005 switch (priv->sh->flow_max_priority) { 10006 case RTE_DIM(priority_map_3): 10007 res = priority_map_3[priority][subpriority]; 10008 break; 10009 case RTE_DIM(priority_map_5): 10010 res = priority_map_5[priority][subpriority]; 10011 break; 10012 } 10013 return res; 10014 } 10015