1 /* SPDX-License-Identifier: BSD-3-Clause 2 * Copyright 2016 6WIND S.A. 3 * Copyright 2016 Mellanox Technologies, Ltd 4 */ 5 6 #include <stdalign.h> 7 #include <stdint.h> 8 #include <string.h> 9 #include <stdbool.h> 10 #include <sys/queue.h> 11 12 #include <rte_common.h> 13 #include <rte_ether.h> 14 #include <ethdev_driver.h> 15 #include <rte_eal_paging.h> 16 #include <rte_flow.h> 17 #include <rte_cycles.h> 18 #include <rte_flow_driver.h> 19 #include <rte_malloc.h> 20 #include <rte_ip.h> 21 22 #include <mlx5_glue.h> 23 #include <mlx5_devx_cmds.h> 24 #include <mlx5_prm.h> 25 #include <mlx5_malloc.h> 26 27 #include "mlx5_defs.h" 28 #include "mlx5.h" 29 #include "mlx5_flow.h" 30 #include "mlx5_flow_os.h" 31 #include "mlx5_rx.h" 32 #include "mlx5_tx.h" 33 #include "mlx5_common_os.h" 34 #include "rte_pmd_mlx5.h" 35 36 struct tunnel_default_miss_ctx { 37 uint16_t *queue; 38 __extension__ 39 union { 40 struct rte_flow_action_rss action_rss; 41 struct rte_flow_action_queue miss_queue; 42 struct rte_flow_action_jump miss_jump; 43 uint8_t raw[0]; 44 }; 45 }; 46 47 static int 48 flow_tunnel_add_default_miss(struct rte_eth_dev *dev, 49 struct rte_flow *flow, 50 const struct rte_flow_attr *attr, 51 const struct rte_flow_action *app_actions, 52 uint32_t flow_idx, 53 const struct mlx5_flow_tunnel *tunnel, 54 struct tunnel_default_miss_ctx *ctx, 55 struct rte_flow_error *error); 56 static struct mlx5_flow_tunnel * 57 mlx5_find_tunnel_id(struct rte_eth_dev *dev, uint32_t id); 58 static void 59 mlx5_flow_tunnel_free(struct rte_eth_dev *dev, struct mlx5_flow_tunnel *tunnel); 60 static uint32_t 61 tunnel_flow_group_to_flow_table(struct rte_eth_dev *dev, 62 const struct mlx5_flow_tunnel *tunnel, 63 uint32_t group, uint32_t *table, 64 struct rte_flow_error *error); 65 66 static struct mlx5_flow_workspace *mlx5_flow_push_thread_workspace(void); 67 static void mlx5_flow_pop_thread_workspace(void); 68 69 70 /** Device flow drivers. */ 71 extern const struct mlx5_flow_driver_ops mlx5_flow_verbs_drv_ops; 72 73 const struct mlx5_flow_driver_ops mlx5_flow_null_drv_ops; 74 75 const struct mlx5_flow_driver_ops *flow_drv_ops[] = { 76 [MLX5_FLOW_TYPE_MIN] = &mlx5_flow_null_drv_ops, 77 #if defined(HAVE_IBV_FLOW_DV_SUPPORT) || !defined(HAVE_INFINIBAND_VERBS_H) 78 [MLX5_FLOW_TYPE_DV] = &mlx5_flow_dv_drv_ops, 79 [MLX5_FLOW_TYPE_HW] = &mlx5_flow_hw_drv_ops, 80 #endif 81 [MLX5_FLOW_TYPE_VERBS] = &mlx5_flow_verbs_drv_ops, 82 [MLX5_FLOW_TYPE_MAX] = &mlx5_flow_null_drv_ops 83 }; 84 85 /** Helper macro to build input graph for mlx5_flow_expand_rss(). */ 86 #define MLX5_FLOW_EXPAND_RSS_NEXT(...) \ 87 (const int []){ \ 88 __VA_ARGS__, 0, \ 89 } 90 91 /** Node object of input graph for mlx5_flow_expand_rss(). */ 92 struct mlx5_flow_expand_node { 93 const int *const next; 94 /**< 95 * List of next node indexes. Index 0 is interpreted as a terminator. 96 */ 97 const enum rte_flow_item_type type; 98 /**< Pattern item type of current node. */ 99 uint64_t rss_types; 100 /**< 101 * RSS types bit-field associated with this node 102 * (see RTE_ETH_RSS_* definitions). 103 */ 104 uint64_t node_flags; 105 /**< 106 * Bit-fields that define how the node is used in the expansion. 107 * (see MLX5_EXPANSION_NODE_* definitions). 108 */ 109 }; 110 111 /* Optional expand field. The expansion alg will not go deeper. */ 112 #define MLX5_EXPANSION_NODE_OPTIONAL (UINT64_C(1) << 0) 113 114 /* The node is not added implicitly as expansion to the flow pattern. 115 * If the node type does not match the flow pattern item type, the 116 * expansion alg will go deeper to its next items. 117 * In the current implementation, the list of next nodes indexes can 118 * have up to one node with this flag set and it has to be the last 119 * node index (before the list terminator). 120 */ 121 #define MLX5_EXPANSION_NODE_EXPLICIT (UINT64_C(1) << 1) 122 123 /** Object returned by mlx5_flow_expand_rss(). */ 124 struct mlx5_flow_expand_rss { 125 uint32_t entries; 126 /**< Number of entries @p patterns and @p priorities. */ 127 struct { 128 struct rte_flow_item *pattern; /**< Expanded pattern array. */ 129 uint32_t priority; /**< Priority offset for each expansion. */ 130 } entry[]; 131 }; 132 133 static void 134 mlx5_dbg__print_pattern(const struct rte_flow_item *item); 135 136 static const struct mlx5_flow_expand_node * 137 mlx5_flow_expand_rss_adjust_node(const struct rte_flow_item *pattern, 138 unsigned int item_idx, 139 const struct mlx5_flow_expand_node graph[], 140 const struct mlx5_flow_expand_node *node); 141 142 static bool 143 mlx5_flow_is_rss_expandable_item(const struct rte_flow_item *item) 144 { 145 switch (item->type) { 146 case RTE_FLOW_ITEM_TYPE_ETH: 147 case RTE_FLOW_ITEM_TYPE_VLAN: 148 case RTE_FLOW_ITEM_TYPE_IPV4: 149 case RTE_FLOW_ITEM_TYPE_IPV6: 150 case RTE_FLOW_ITEM_TYPE_UDP: 151 case RTE_FLOW_ITEM_TYPE_TCP: 152 case RTE_FLOW_ITEM_TYPE_VXLAN: 153 case RTE_FLOW_ITEM_TYPE_NVGRE: 154 case RTE_FLOW_ITEM_TYPE_GRE: 155 case RTE_FLOW_ITEM_TYPE_GENEVE: 156 case RTE_FLOW_ITEM_TYPE_MPLS: 157 case RTE_FLOW_ITEM_TYPE_VXLAN_GPE: 158 case RTE_FLOW_ITEM_TYPE_GRE_KEY: 159 case RTE_FLOW_ITEM_TYPE_IPV6_FRAG_EXT: 160 case RTE_FLOW_ITEM_TYPE_GTP: 161 return true; 162 default: 163 break; 164 } 165 return false; 166 } 167 168 /** 169 * Network Service Header (NSH) and its next protocol values 170 * are described in RFC-8393. 171 */ 172 static enum rte_flow_item_type 173 mlx5_nsh_proto_to_item_type(uint8_t proto_spec, uint8_t proto_mask) 174 { 175 enum rte_flow_item_type type; 176 177 switch (proto_mask & proto_spec) { 178 case 0: 179 type = RTE_FLOW_ITEM_TYPE_VOID; 180 break; 181 case RTE_VXLAN_GPE_TYPE_IPV4: 182 type = RTE_FLOW_ITEM_TYPE_IPV4; 183 break; 184 case RTE_VXLAN_GPE_TYPE_IPV6: 185 type = RTE_VXLAN_GPE_TYPE_IPV6; 186 break; 187 case RTE_VXLAN_GPE_TYPE_ETH: 188 type = RTE_FLOW_ITEM_TYPE_ETH; 189 break; 190 default: 191 type = RTE_FLOW_ITEM_TYPE_END; 192 } 193 return type; 194 } 195 196 static enum rte_flow_item_type 197 mlx5_inet_proto_to_item_type(uint8_t proto_spec, uint8_t proto_mask) 198 { 199 enum rte_flow_item_type type; 200 201 switch (proto_mask & proto_spec) { 202 case 0: 203 type = RTE_FLOW_ITEM_TYPE_VOID; 204 break; 205 case IPPROTO_UDP: 206 type = RTE_FLOW_ITEM_TYPE_UDP; 207 break; 208 case IPPROTO_TCP: 209 type = RTE_FLOW_ITEM_TYPE_TCP; 210 break; 211 case IPPROTO_IPIP: 212 type = RTE_FLOW_ITEM_TYPE_IPV4; 213 break; 214 case IPPROTO_IPV6: 215 type = RTE_FLOW_ITEM_TYPE_IPV6; 216 break; 217 default: 218 type = RTE_FLOW_ITEM_TYPE_END; 219 } 220 return type; 221 } 222 223 static enum rte_flow_item_type 224 mlx5_ethertype_to_item_type(rte_be16_t type_spec, 225 rte_be16_t type_mask, bool is_tunnel) 226 { 227 enum rte_flow_item_type type; 228 229 switch (rte_be_to_cpu_16(type_spec & type_mask)) { 230 case 0: 231 type = RTE_FLOW_ITEM_TYPE_VOID; 232 break; 233 case RTE_ETHER_TYPE_TEB: 234 type = is_tunnel ? 235 RTE_FLOW_ITEM_TYPE_ETH : RTE_FLOW_ITEM_TYPE_END; 236 break; 237 case RTE_ETHER_TYPE_VLAN: 238 type = !is_tunnel ? 239 RTE_FLOW_ITEM_TYPE_VLAN : RTE_FLOW_ITEM_TYPE_END; 240 break; 241 case RTE_ETHER_TYPE_IPV4: 242 type = RTE_FLOW_ITEM_TYPE_IPV4; 243 break; 244 case RTE_ETHER_TYPE_IPV6: 245 type = RTE_FLOW_ITEM_TYPE_IPV6; 246 break; 247 default: 248 type = RTE_FLOW_ITEM_TYPE_END; 249 } 250 return type; 251 } 252 253 static enum rte_flow_item_type 254 mlx5_flow_expand_rss_item_complete(const struct rte_flow_item *item) 255 { 256 #define MLX5_XSET_ITEM_MASK_SPEC(type, fld) \ 257 do { \ 258 const void *m = item->mask; \ 259 const void *s = item->spec; \ 260 mask = m ? \ 261 ((const struct rte_flow_item_##type *)m)->fld : \ 262 rte_flow_item_##type##_mask.fld; \ 263 spec = ((const struct rte_flow_item_##type *)s)->fld; \ 264 } while (0) 265 266 enum rte_flow_item_type ret; 267 uint16_t spec, mask; 268 269 if (item == NULL || item->spec == NULL) 270 return RTE_FLOW_ITEM_TYPE_VOID; 271 switch (item->type) { 272 case RTE_FLOW_ITEM_TYPE_ETH: 273 MLX5_XSET_ITEM_MASK_SPEC(eth, type); 274 if (!mask) 275 return RTE_FLOW_ITEM_TYPE_VOID; 276 ret = mlx5_ethertype_to_item_type(spec, mask, false); 277 break; 278 case RTE_FLOW_ITEM_TYPE_VLAN: 279 MLX5_XSET_ITEM_MASK_SPEC(vlan, inner_type); 280 if (!mask) 281 return RTE_FLOW_ITEM_TYPE_VOID; 282 ret = mlx5_ethertype_to_item_type(spec, mask, false); 283 break; 284 case RTE_FLOW_ITEM_TYPE_IPV4: 285 MLX5_XSET_ITEM_MASK_SPEC(ipv4, hdr.next_proto_id); 286 if (!mask) 287 return RTE_FLOW_ITEM_TYPE_VOID; 288 ret = mlx5_inet_proto_to_item_type(spec, mask); 289 break; 290 case RTE_FLOW_ITEM_TYPE_IPV6: 291 MLX5_XSET_ITEM_MASK_SPEC(ipv6, hdr.proto); 292 if (!mask) 293 return RTE_FLOW_ITEM_TYPE_VOID; 294 ret = mlx5_inet_proto_to_item_type(spec, mask); 295 break; 296 case RTE_FLOW_ITEM_TYPE_GENEVE: 297 MLX5_XSET_ITEM_MASK_SPEC(geneve, protocol); 298 ret = mlx5_ethertype_to_item_type(spec, mask, true); 299 break; 300 case RTE_FLOW_ITEM_TYPE_GRE: 301 MLX5_XSET_ITEM_MASK_SPEC(gre, protocol); 302 ret = mlx5_ethertype_to_item_type(spec, mask, true); 303 break; 304 case RTE_FLOW_ITEM_TYPE_VXLAN_GPE: 305 MLX5_XSET_ITEM_MASK_SPEC(vxlan_gpe, protocol); 306 ret = mlx5_nsh_proto_to_item_type(spec, mask); 307 break; 308 default: 309 ret = RTE_FLOW_ITEM_TYPE_VOID; 310 break; 311 } 312 return ret; 313 #undef MLX5_XSET_ITEM_MASK_SPEC 314 } 315 316 static const int * 317 mlx5_flow_expand_rss_skip_explicit(const struct mlx5_flow_expand_node graph[], 318 const int *next_node) 319 { 320 const struct mlx5_flow_expand_node *node = NULL; 321 const int *next = next_node; 322 323 while (next && *next) { 324 /* 325 * Skip the nodes with the MLX5_EXPANSION_NODE_EXPLICIT 326 * flag set, because they were not found in the flow pattern. 327 */ 328 node = &graph[*next]; 329 if (!(node->node_flags & MLX5_EXPANSION_NODE_EXPLICIT)) 330 break; 331 next = node->next; 332 } 333 return next; 334 } 335 336 #define MLX5_RSS_EXP_ELT_N 16 337 338 /** 339 * Expand RSS flows into several possible flows according to the RSS hash 340 * fields requested and the driver capabilities. 341 * 342 * @param[out] buf 343 * Buffer to store the result expansion. 344 * @param[in] size 345 * Buffer size in bytes. If 0, @p buf can be NULL. 346 * @param[in] pattern 347 * User flow pattern. 348 * @param[in] types 349 * RSS types to expand (see RTE_ETH_RSS_* definitions). 350 * @param[in] graph 351 * Input graph to expand @p pattern according to @p types. 352 * @param[in] graph_root_index 353 * Index of root node in @p graph, typically 0. 354 * 355 * @return 356 * A positive value representing the size of @p buf in bytes regardless of 357 * @p size on success, a negative errno value otherwise and rte_errno is 358 * set, the following errors are defined: 359 * 360 * -E2BIG: graph-depth @p graph is too deep. 361 * -EINVAL: @p size has not enough space for expanded pattern. 362 */ 363 static int 364 mlx5_flow_expand_rss(struct mlx5_flow_expand_rss *buf, size_t size, 365 const struct rte_flow_item *pattern, uint64_t types, 366 const struct mlx5_flow_expand_node graph[], 367 int graph_root_index) 368 { 369 const struct rte_flow_item *item; 370 const struct mlx5_flow_expand_node *node = &graph[graph_root_index]; 371 const int *next_node; 372 const int *stack[MLX5_RSS_EXP_ELT_N]; 373 int stack_pos = 0; 374 struct rte_flow_item flow_items[MLX5_RSS_EXP_ELT_N]; 375 unsigned int i, item_idx, last_expand_item_idx = 0; 376 size_t lsize; 377 size_t user_pattern_size = 0; 378 void *addr = NULL; 379 const struct mlx5_flow_expand_node *next = NULL; 380 struct rte_flow_item missed_item; 381 int missed = 0; 382 int elt = 0; 383 const struct rte_flow_item *last_expand_item = NULL; 384 385 memset(&missed_item, 0, sizeof(missed_item)); 386 lsize = offsetof(struct mlx5_flow_expand_rss, entry) + 387 MLX5_RSS_EXP_ELT_N * sizeof(buf->entry[0]); 388 if (lsize > size) 389 return -EINVAL; 390 buf->entry[0].priority = 0; 391 buf->entry[0].pattern = (void *)&buf->entry[MLX5_RSS_EXP_ELT_N]; 392 buf->entries = 0; 393 addr = buf->entry[0].pattern; 394 for (item = pattern, item_idx = 0; 395 item->type != RTE_FLOW_ITEM_TYPE_END; 396 item++, item_idx++) { 397 if (!mlx5_flow_is_rss_expandable_item(item)) { 398 user_pattern_size += sizeof(*item); 399 continue; 400 } 401 last_expand_item = item; 402 last_expand_item_idx = item_idx; 403 i = 0; 404 while (node->next && node->next[i]) { 405 next = &graph[node->next[i]]; 406 if (next->type == item->type) 407 break; 408 if (next->node_flags & MLX5_EXPANSION_NODE_EXPLICIT) { 409 node = next; 410 i = 0; 411 } else { 412 ++i; 413 } 414 } 415 if (next) 416 node = next; 417 user_pattern_size += sizeof(*item); 418 } 419 user_pattern_size += sizeof(*item); /* Handle END item. */ 420 lsize += user_pattern_size; 421 if (lsize > size) 422 return -EINVAL; 423 /* Copy the user pattern in the first entry of the buffer. */ 424 rte_memcpy(addr, pattern, user_pattern_size); 425 addr = (void *)(((uintptr_t)addr) + user_pattern_size); 426 buf->entries = 1; 427 /* Start expanding. */ 428 memset(flow_items, 0, sizeof(flow_items)); 429 user_pattern_size -= sizeof(*item); 430 /* 431 * Check if the last valid item has spec set, need complete pattern, 432 * and the pattern can be used for expansion. 433 */ 434 missed_item.type = mlx5_flow_expand_rss_item_complete(last_expand_item); 435 if (missed_item.type == RTE_FLOW_ITEM_TYPE_END) { 436 /* Item type END indicates expansion is not required. */ 437 return lsize; 438 } 439 if (missed_item.type != RTE_FLOW_ITEM_TYPE_VOID) { 440 next = NULL; 441 missed = 1; 442 i = 0; 443 while (node->next && node->next[i]) { 444 next = &graph[node->next[i]]; 445 if (next->type == missed_item.type) { 446 flow_items[0].type = missed_item.type; 447 flow_items[1].type = RTE_FLOW_ITEM_TYPE_END; 448 break; 449 } 450 if (next->node_flags & MLX5_EXPANSION_NODE_EXPLICIT) { 451 node = next; 452 i = 0; 453 } else { 454 ++i; 455 } 456 next = NULL; 457 } 458 } 459 if (next && missed) { 460 elt = 2; /* missed item + item end. */ 461 node = next; 462 lsize += elt * sizeof(*item) + user_pattern_size; 463 if (lsize > size) 464 return -EINVAL; 465 if (node->rss_types & types) { 466 buf->entry[buf->entries].priority = 1; 467 buf->entry[buf->entries].pattern = addr; 468 buf->entries++; 469 rte_memcpy(addr, buf->entry[0].pattern, 470 user_pattern_size); 471 addr = (void *)(((uintptr_t)addr) + user_pattern_size); 472 rte_memcpy(addr, flow_items, elt * sizeof(*item)); 473 addr = (void *)(((uintptr_t)addr) + 474 elt * sizeof(*item)); 475 } 476 } else if (last_expand_item != NULL) { 477 node = mlx5_flow_expand_rss_adjust_node(pattern, 478 last_expand_item_idx, graph, node); 479 } 480 memset(flow_items, 0, sizeof(flow_items)); 481 next_node = mlx5_flow_expand_rss_skip_explicit(graph, 482 node->next); 483 stack[stack_pos] = next_node; 484 node = next_node ? &graph[*next_node] : NULL; 485 while (node) { 486 flow_items[stack_pos].type = node->type; 487 if (node->rss_types & types) { 488 size_t n; 489 /* 490 * compute the number of items to copy from the 491 * expansion and copy it. 492 * When the stack_pos is 0, there are 1 element in it, 493 * plus the addition END item. 494 */ 495 elt = stack_pos + 2; 496 flow_items[stack_pos + 1].type = RTE_FLOW_ITEM_TYPE_END; 497 lsize += elt * sizeof(*item) + user_pattern_size; 498 if (lsize > size) 499 return -EINVAL; 500 n = elt * sizeof(*item); 501 buf->entry[buf->entries].priority = 502 stack_pos + 1 + missed; 503 buf->entry[buf->entries].pattern = addr; 504 buf->entries++; 505 rte_memcpy(addr, buf->entry[0].pattern, 506 user_pattern_size); 507 addr = (void *)(((uintptr_t)addr) + 508 user_pattern_size); 509 rte_memcpy(addr, &missed_item, 510 missed * sizeof(*item)); 511 addr = (void *)(((uintptr_t)addr) + 512 missed * sizeof(*item)); 513 rte_memcpy(addr, flow_items, n); 514 addr = (void *)(((uintptr_t)addr) + n); 515 } 516 /* Go deeper. */ 517 if (!(node->node_flags & MLX5_EXPANSION_NODE_OPTIONAL) && 518 node->next) { 519 next_node = mlx5_flow_expand_rss_skip_explicit(graph, 520 node->next); 521 if (stack_pos++ == MLX5_RSS_EXP_ELT_N) { 522 rte_errno = E2BIG; 523 return -rte_errno; 524 } 525 stack[stack_pos] = next_node; 526 } else if (*(next_node + 1)) { 527 /* Follow up with the next possibility. */ 528 next_node = mlx5_flow_expand_rss_skip_explicit(graph, 529 ++next_node); 530 } else if (!stack_pos) { 531 /* 532 * Completing the traverse over the different paths. 533 * The next_node is advanced to the terminator. 534 */ 535 ++next_node; 536 } else { 537 /* Move to the next path. */ 538 while (stack_pos) { 539 next_node = stack[--stack_pos]; 540 next_node++; 541 if (*next_node) 542 break; 543 } 544 next_node = mlx5_flow_expand_rss_skip_explicit(graph, 545 next_node); 546 stack[stack_pos] = next_node; 547 } 548 node = next_node && *next_node ? &graph[*next_node] : NULL; 549 }; 550 return lsize; 551 } 552 553 enum mlx5_expansion { 554 MLX5_EXPANSION_ROOT, 555 MLX5_EXPANSION_ROOT_OUTER, 556 MLX5_EXPANSION_OUTER_ETH, 557 MLX5_EXPANSION_OUTER_VLAN, 558 MLX5_EXPANSION_OUTER_IPV4, 559 MLX5_EXPANSION_OUTER_IPV4_UDP, 560 MLX5_EXPANSION_OUTER_IPV4_TCP, 561 MLX5_EXPANSION_OUTER_IPV6, 562 MLX5_EXPANSION_OUTER_IPV6_UDP, 563 MLX5_EXPANSION_OUTER_IPV6_TCP, 564 MLX5_EXPANSION_VXLAN, 565 MLX5_EXPANSION_STD_VXLAN, 566 MLX5_EXPANSION_L3_VXLAN, 567 MLX5_EXPANSION_VXLAN_GPE, 568 MLX5_EXPANSION_GRE, 569 MLX5_EXPANSION_NVGRE, 570 MLX5_EXPANSION_GRE_KEY, 571 MLX5_EXPANSION_MPLS, 572 MLX5_EXPANSION_ETH, 573 MLX5_EXPANSION_VLAN, 574 MLX5_EXPANSION_IPV4, 575 MLX5_EXPANSION_IPV4_UDP, 576 MLX5_EXPANSION_IPV4_TCP, 577 MLX5_EXPANSION_IPV6, 578 MLX5_EXPANSION_IPV6_UDP, 579 MLX5_EXPANSION_IPV6_TCP, 580 MLX5_EXPANSION_IPV6_FRAG_EXT, 581 MLX5_EXPANSION_GTP, 582 MLX5_EXPANSION_GENEVE, 583 }; 584 585 /** Supported expansion of items. */ 586 static const struct mlx5_flow_expand_node mlx5_support_expansion[] = { 587 [MLX5_EXPANSION_ROOT] = { 588 .next = MLX5_FLOW_EXPAND_RSS_NEXT(MLX5_EXPANSION_ETH, 589 MLX5_EXPANSION_IPV4, 590 MLX5_EXPANSION_IPV6), 591 .type = RTE_FLOW_ITEM_TYPE_END, 592 }, 593 [MLX5_EXPANSION_ROOT_OUTER] = { 594 .next = MLX5_FLOW_EXPAND_RSS_NEXT(MLX5_EXPANSION_OUTER_ETH, 595 MLX5_EXPANSION_OUTER_IPV4, 596 MLX5_EXPANSION_OUTER_IPV6), 597 .type = RTE_FLOW_ITEM_TYPE_END, 598 }, 599 [MLX5_EXPANSION_OUTER_ETH] = { 600 .next = MLX5_FLOW_EXPAND_RSS_NEXT(MLX5_EXPANSION_OUTER_VLAN), 601 .type = RTE_FLOW_ITEM_TYPE_ETH, 602 .rss_types = 0, 603 }, 604 [MLX5_EXPANSION_OUTER_VLAN] = { 605 .next = MLX5_FLOW_EXPAND_RSS_NEXT(MLX5_EXPANSION_OUTER_IPV4, 606 MLX5_EXPANSION_OUTER_IPV6), 607 .type = RTE_FLOW_ITEM_TYPE_VLAN, 608 .node_flags = MLX5_EXPANSION_NODE_EXPLICIT, 609 }, 610 [MLX5_EXPANSION_OUTER_IPV4] = { 611 .next = MLX5_FLOW_EXPAND_RSS_NEXT 612 (MLX5_EXPANSION_OUTER_IPV4_UDP, 613 MLX5_EXPANSION_OUTER_IPV4_TCP, 614 MLX5_EXPANSION_GRE, 615 MLX5_EXPANSION_NVGRE, 616 MLX5_EXPANSION_IPV4, 617 MLX5_EXPANSION_IPV6), 618 .type = RTE_FLOW_ITEM_TYPE_IPV4, 619 .rss_types = RTE_ETH_RSS_IPV4 | RTE_ETH_RSS_FRAG_IPV4 | 620 RTE_ETH_RSS_NONFRAG_IPV4_OTHER, 621 }, 622 [MLX5_EXPANSION_OUTER_IPV4_UDP] = { 623 .next = MLX5_FLOW_EXPAND_RSS_NEXT(MLX5_EXPANSION_VXLAN, 624 MLX5_EXPANSION_VXLAN_GPE, 625 MLX5_EXPANSION_MPLS, 626 MLX5_EXPANSION_GENEVE, 627 MLX5_EXPANSION_GTP), 628 .type = RTE_FLOW_ITEM_TYPE_UDP, 629 .rss_types = RTE_ETH_RSS_NONFRAG_IPV4_UDP, 630 }, 631 [MLX5_EXPANSION_OUTER_IPV4_TCP] = { 632 .type = RTE_FLOW_ITEM_TYPE_TCP, 633 .rss_types = RTE_ETH_RSS_NONFRAG_IPV4_TCP, 634 }, 635 [MLX5_EXPANSION_OUTER_IPV6] = { 636 .next = MLX5_FLOW_EXPAND_RSS_NEXT 637 (MLX5_EXPANSION_OUTER_IPV6_UDP, 638 MLX5_EXPANSION_OUTER_IPV6_TCP, 639 MLX5_EXPANSION_IPV4, 640 MLX5_EXPANSION_IPV6, 641 MLX5_EXPANSION_GRE, 642 MLX5_EXPANSION_NVGRE), 643 .type = RTE_FLOW_ITEM_TYPE_IPV6, 644 .rss_types = RTE_ETH_RSS_IPV6 | RTE_ETH_RSS_FRAG_IPV6 | 645 RTE_ETH_RSS_NONFRAG_IPV6_OTHER, 646 }, 647 [MLX5_EXPANSION_OUTER_IPV6_UDP] = { 648 .next = MLX5_FLOW_EXPAND_RSS_NEXT(MLX5_EXPANSION_VXLAN, 649 MLX5_EXPANSION_VXLAN_GPE, 650 MLX5_EXPANSION_MPLS, 651 MLX5_EXPANSION_GENEVE, 652 MLX5_EXPANSION_GTP), 653 .type = RTE_FLOW_ITEM_TYPE_UDP, 654 .rss_types = RTE_ETH_RSS_NONFRAG_IPV6_UDP, 655 }, 656 [MLX5_EXPANSION_OUTER_IPV6_TCP] = { 657 .type = RTE_FLOW_ITEM_TYPE_TCP, 658 .rss_types = RTE_ETH_RSS_NONFRAG_IPV6_TCP, 659 }, 660 [MLX5_EXPANSION_VXLAN] = { 661 .next = MLX5_FLOW_EXPAND_RSS_NEXT(MLX5_EXPANSION_ETH, 662 MLX5_EXPANSION_IPV4, 663 MLX5_EXPANSION_IPV6), 664 .type = RTE_FLOW_ITEM_TYPE_VXLAN, 665 }, 666 [MLX5_EXPANSION_STD_VXLAN] = { 667 .next = MLX5_FLOW_EXPAND_RSS_NEXT(MLX5_EXPANSION_ETH), 668 .type = RTE_FLOW_ITEM_TYPE_VXLAN, 669 }, 670 [MLX5_EXPANSION_L3_VXLAN] = { 671 .next = MLX5_FLOW_EXPAND_RSS_NEXT(MLX5_EXPANSION_IPV4, 672 MLX5_EXPANSION_IPV6), 673 .type = RTE_FLOW_ITEM_TYPE_VXLAN, 674 }, 675 [MLX5_EXPANSION_VXLAN_GPE] = { 676 .next = MLX5_FLOW_EXPAND_RSS_NEXT(MLX5_EXPANSION_ETH, 677 MLX5_EXPANSION_IPV4, 678 MLX5_EXPANSION_IPV6), 679 .type = RTE_FLOW_ITEM_TYPE_VXLAN_GPE, 680 }, 681 [MLX5_EXPANSION_GRE] = { 682 .next = MLX5_FLOW_EXPAND_RSS_NEXT(MLX5_EXPANSION_ETH, 683 MLX5_EXPANSION_IPV4, 684 MLX5_EXPANSION_IPV6, 685 MLX5_EXPANSION_GRE_KEY, 686 MLX5_EXPANSION_MPLS), 687 .type = RTE_FLOW_ITEM_TYPE_GRE, 688 }, 689 [MLX5_EXPANSION_GRE_KEY] = { 690 .next = MLX5_FLOW_EXPAND_RSS_NEXT(MLX5_EXPANSION_IPV4, 691 MLX5_EXPANSION_IPV6, 692 MLX5_EXPANSION_MPLS), 693 .type = RTE_FLOW_ITEM_TYPE_GRE_KEY, 694 .node_flags = MLX5_EXPANSION_NODE_OPTIONAL, 695 }, 696 [MLX5_EXPANSION_NVGRE] = { 697 .next = MLX5_FLOW_EXPAND_RSS_NEXT(MLX5_EXPANSION_ETH), 698 .type = RTE_FLOW_ITEM_TYPE_NVGRE, 699 }, 700 [MLX5_EXPANSION_MPLS] = { 701 .next = MLX5_FLOW_EXPAND_RSS_NEXT(MLX5_EXPANSION_IPV4, 702 MLX5_EXPANSION_IPV6, 703 MLX5_EXPANSION_ETH), 704 .type = RTE_FLOW_ITEM_TYPE_MPLS, 705 .node_flags = MLX5_EXPANSION_NODE_OPTIONAL, 706 }, 707 [MLX5_EXPANSION_ETH] = { 708 .next = MLX5_FLOW_EXPAND_RSS_NEXT(MLX5_EXPANSION_VLAN), 709 .type = RTE_FLOW_ITEM_TYPE_ETH, 710 }, 711 [MLX5_EXPANSION_VLAN] = { 712 .next = MLX5_FLOW_EXPAND_RSS_NEXT(MLX5_EXPANSION_IPV4, 713 MLX5_EXPANSION_IPV6), 714 .type = RTE_FLOW_ITEM_TYPE_VLAN, 715 .node_flags = MLX5_EXPANSION_NODE_EXPLICIT, 716 }, 717 [MLX5_EXPANSION_IPV4] = { 718 .next = MLX5_FLOW_EXPAND_RSS_NEXT(MLX5_EXPANSION_IPV4_UDP, 719 MLX5_EXPANSION_IPV4_TCP), 720 .type = RTE_FLOW_ITEM_TYPE_IPV4, 721 .rss_types = RTE_ETH_RSS_IPV4 | RTE_ETH_RSS_FRAG_IPV4 | 722 RTE_ETH_RSS_NONFRAG_IPV4_OTHER, 723 }, 724 [MLX5_EXPANSION_IPV4_UDP] = { 725 .type = RTE_FLOW_ITEM_TYPE_UDP, 726 .rss_types = RTE_ETH_RSS_NONFRAG_IPV4_UDP, 727 }, 728 [MLX5_EXPANSION_IPV4_TCP] = { 729 .type = RTE_FLOW_ITEM_TYPE_TCP, 730 .rss_types = RTE_ETH_RSS_NONFRAG_IPV4_TCP, 731 }, 732 [MLX5_EXPANSION_IPV6] = { 733 .next = MLX5_FLOW_EXPAND_RSS_NEXT(MLX5_EXPANSION_IPV6_UDP, 734 MLX5_EXPANSION_IPV6_TCP, 735 MLX5_EXPANSION_IPV6_FRAG_EXT), 736 .type = RTE_FLOW_ITEM_TYPE_IPV6, 737 .rss_types = RTE_ETH_RSS_IPV6 | RTE_ETH_RSS_FRAG_IPV6 | 738 RTE_ETH_RSS_NONFRAG_IPV6_OTHER, 739 }, 740 [MLX5_EXPANSION_IPV6_UDP] = { 741 .type = RTE_FLOW_ITEM_TYPE_UDP, 742 .rss_types = RTE_ETH_RSS_NONFRAG_IPV6_UDP, 743 }, 744 [MLX5_EXPANSION_IPV6_TCP] = { 745 .type = RTE_FLOW_ITEM_TYPE_TCP, 746 .rss_types = RTE_ETH_RSS_NONFRAG_IPV6_TCP, 747 }, 748 [MLX5_EXPANSION_IPV6_FRAG_EXT] = { 749 .type = RTE_FLOW_ITEM_TYPE_IPV6_FRAG_EXT, 750 }, 751 [MLX5_EXPANSION_GTP] = { 752 .next = MLX5_FLOW_EXPAND_RSS_NEXT(MLX5_EXPANSION_IPV4, 753 MLX5_EXPANSION_IPV6), 754 .type = RTE_FLOW_ITEM_TYPE_GTP, 755 }, 756 [MLX5_EXPANSION_GENEVE] = { 757 .next = MLX5_FLOW_EXPAND_RSS_NEXT(MLX5_EXPANSION_ETH, 758 MLX5_EXPANSION_IPV4, 759 MLX5_EXPANSION_IPV6), 760 .type = RTE_FLOW_ITEM_TYPE_GENEVE, 761 }, 762 }; 763 764 static struct rte_flow_action_handle * 765 mlx5_action_handle_create(struct rte_eth_dev *dev, 766 const struct rte_flow_indir_action_conf *conf, 767 const struct rte_flow_action *action, 768 struct rte_flow_error *error); 769 static int mlx5_action_handle_destroy 770 (struct rte_eth_dev *dev, 771 struct rte_flow_action_handle *handle, 772 struct rte_flow_error *error); 773 static int mlx5_action_handle_update 774 (struct rte_eth_dev *dev, 775 struct rte_flow_action_handle *handle, 776 const void *update, 777 struct rte_flow_error *error); 778 static int mlx5_action_handle_query 779 (struct rte_eth_dev *dev, 780 const struct rte_flow_action_handle *handle, 781 void *data, 782 struct rte_flow_error *error); 783 static int 784 mlx5_flow_tunnel_decap_set(struct rte_eth_dev *dev, 785 struct rte_flow_tunnel *app_tunnel, 786 struct rte_flow_action **actions, 787 uint32_t *num_of_actions, 788 struct rte_flow_error *error); 789 static int 790 mlx5_flow_tunnel_match(struct rte_eth_dev *dev, 791 struct rte_flow_tunnel *app_tunnel, 792 struct rte_flow_item **items, 793 uint32_t *num_of_items, 794 struct rte_flow_error *error); 795 static int 796 mlx5_flow_tunnel_item_release(struct rte_eth_dev *dev, 797 struct rte_flow_item *pmd_items, 798 uint32_t num_items, struct rte_flow_error *err); 799 static int 800 mlx5_flow_tunnel_action_release(struct rte_eth_dev *dev, 801 struct rte_flow_action *pmd_actions, 802 uint32_t num_actions, 803 struct rte_flow_error *err); 804 static int 805 mlx5_flow_tunnel_get_restore_info(struct rte_eth_dev *dev, 806 struct rte_mbuf *m, 807 struct rte_flow_restore_info *info, 808 struct rte_flow_error *err); 809 static struct rte_flow_item_flex_handle * 810 mlx5_flow_flex_item_create(struct rte_eth_dev *dev, 811 const struct rte_flow_item_flex_conf *conf, 812 struct rte_flow_error *error); 813 static int 814 mlx5_flow_flex_item_release(struct rte_eth_dev *dev, 815 const struct rte_flow_item_flex_handle *handle, 816 struct rte_flow_error *error); 817 static int 818 mlx5_flow_info_get(struct rte_eth_dev *dev, 819 struct rte_flow_port_info *port_info, 820 struct rte_flow_queue_info *queue_info, 821 struct rte_flow_error *error); 822 static int 823 mlx5_flow_port_configure(struct rte_eth_dev *dev, 824 const struct rte_flow_port_attr *port_attr, 825 uint16_t nb_queue, 826 const struct rte_flow_queue_attr *queue_attr[], 827 struct rte_flow_error *err); 828 829 static struct rte_flow_pattern_template * 830 mlx5_flow_pattern_template_create(struct rte_eth_dev *dev, 831 const struct rte_flow_pattern_template_attr *attr, 832 const struct rte_flow_item items[], 833 struct rte_flow_error *error); 834 835 static int 836 mlx5_flow_pattern_template_destroy(struct rte_eth_dev *dev, 837 struct rte_flow_pattern_template *template, 838 struct rte_flow_error *error); 839 static struct rte_flow_actions_template * 840 mlx5_flow_actions_template_create(struct rte_eth_dev *dev, 841 const struct rte_flow_actions_template_attr *attr, 842 const struct rte_flow_action actions[], 843 const struct rte_flow_action masks[], 844 struct rte_flow_error *error); 845 static int 846 mlx5_flow_actions_template_destroy(struct rte_eth_dev *dev, 847 struct rte_flow_actions_template *template, 848 struct rte_flow_error *error); 849 850 static struct rte_flow_template_table * 851 mlx5_flow_table_create(struct rte_eth_dev *dev, 852 const struct rte_flow_template_table_attr *attr, 853 struct rte_flow_pattern_template *item_templates[], 854 uint8_t nb_item_templates, 855 struct rte_flow_actions_template *action_templates[], 856 uint8_t nb_action_templates, 857 struct rte_flow_error *error); 858 static int 859 mlx5_flow_table_destroy(struct rte_eth_dev *dev, 860 struct rte_flow_template_table *table, 861 struct rte_flow_error *error); 862 static struct rte_flow * 863 mlx5_flow_async_flow_create(struct rte_eth_dev *dev, 864 uint32_t queue, 865 const struct rte_flow_op_attr *attr, 866 struct rte_flow_template_table *table, 867 const struct rte_flow_item items[], 868 uint8_t pattern_template_index, 869 const struct rte_flow_action actions[], 870 uint8_t action_template_index, 871 void *user_data, 872 struct rte_flow_error *error); 873 static int 874 mlx5_flow_async_flow_destroy(struct rte_eth_dev *dev, 875 uint32_t queue, 876 const struct rte_flow_op_attr *attr, 877 struct rte_flow *flow, 878 void *user_data, 879 struct rte_flow_error *error); 880 static int 881 mlx5_flow_pull(struct rte_eth_dev *dev, 882 uint32_t queue, 883 struct rte_flow_op_result res[], 884 uint16_t n_res, 885 struct rte_flow_error *error); 886 static int 887 mlx5_flow_push(struct rte_eth_dev *dev, 888 uint32_t queue, 889 struct rte_flow_error *error); 890 891 static struct rte_flow_action_handle * 892 mlx5_flow_async_action_handle_create(struct rte_eth_dev *dev, uint32_t queue, 893 const struct rte_flow_op_attr *attr, 894 const struct rte_flow_indir_action_conf *conf, 895 const struct rte_flow_action *action, 896 void *user_data, 897 struct rte_flow_error *error); 898 899 static int 900 mlx5_flow_async_action_handle_update(struct rte_eth_dev *dev, uint32_t queue, 901 const struct rte_flow_op_attr *attr, 902 struct rte_flow_action_handle *handle, 903 const void *update, 904 void *user_data, 905 struct rte_flow_error *error); 906 907 static int 908 mlx5_flow_async_action_handle_destroy(struct rte_eth_dev *dev, uint32_t queue, 909 const struct rte_flow_op_attr *attr, 910 struct rte_flow_action_handle *handle, 911 void *user_data, 912 struct rte_flow_error *error); 913 914 static const struct rte_flow_ops mlx5_flow_ops = { 915 .validate = mlx5_flow_validate, 916 .create = mlx5_flow_create, 917 .destroy = mlx5_flow_destroy, 918 .flush = mlx5_flow_flush, 919 .isolate = mlx5_flow_isolate, 920 .query = mlx5_flow_query, 921 .dev_dump = mlx5_flow_dev_dump, 922 .get_aged_flows = mlx5_flow_get_aged_flows, 923 .action_handle_create = mlx5_action_handle_create, 924 .action_handle_destroy = mlx5_action_handle_destroy, 925 .action_handle_update = mlx5_action_handle_update, 926 .action_handle_query = mlx5_action_handle_query, 927 .tunnel_decap_set = mlx5_flow_tunnel_decap_set, 928 .tunnel_match = mlx5_flow_tunnel_match, 929 .tunnel_action_decap_release = mlx5_flow_tunnel_action_release, 930 .tunnel_item_release = mlx5_flow_tunnel_item_release, 931 .get_restore_info = mlx5_flow_tunnel_get_restore_info, 932 .flex_item_create = mlx5_flow_flex_item_create, 933 .flex_item_release = mlx5_flow_flex_item_release, 934 .info_get = mlx5_flow_info_get, 935 .configure = mlx5_flow_port_configure, 936 .pattern_template_create = mlx5_flow_pattern_template_create, 937 .pattern_template_destroy = mlx5_flow_pattern_template_destroy, 938 .actions_template_create = mlx5_flow_actions_template_create, 939 .actions_template_destroy = mlx5_flow_actions_template_destroy, 940 .template_table_create = mlx5_flow_table_create, 941 .template_table_destroy = mlx5_flow_table_destroy, 942 .async_create = mlx5_flow_async_flow_create, 943 .async_destroy = mlx5_flow_async_flow_destroy, 944 .pull = mlx5_flow_pull, 945 .push = mlx5_flow_push, 946 .async_action_handle_create = mlx5_flow_async_action_handle_create, 947 .async_action_handle_update = mlx5_flow_async_action_handle_update, 948 .async_action_handle_destroy = mlx5_flow_async_action_handle_destroy, 949 }; 950 951 /* Tunnel information. */ 952 struct mlx5_flow_tunnel_info { 953 uint64_t tunnel; /**< Tunnel bit (see MLX5_FLOW_*). */ 954 uint32_t ptype; /**< Tunnel Ptype (see RTE_PTYPE_*). */ 955 }; 956 957 static struct mlx5_flow_tunnel_info tunnels_info[] = { 958 { 959 .tunnel = MLX5_FLOW_LAYER_VXLAN, 960 .ptype = RTE_PTYPE_TUNNEL_VXLAN | RTE_PTYPE_L4_UDP, 961 }, 962 { 963 .tunnel = MLX5_FLOW_LAYER_GENEVE, 964 .ptype = RTE_PTYPE_TUNNEL_GENEVE | RTE_PTYPE_L4_UDP, 965 }, 966 { 967 .tunnel = MLX5_FLOW_LAYER_VXLAN_GPE, 968 .ptype = RTE_PTYPE_TUNNEL_VXLAN_GPE | RTE_PTYPE_L4_UDP, 969 }, 970 { 971 .tunnel = MLX5_FLOW_LAYER_GRE, 972 .ptype = RTE_PTYPE_TUNNEL_GRE, 973 }, 974 { 975 .tunnel = MLX5_FLOW_LAYER_MPLS | MLX5_FLOW_LAYER_OUTER_L4_UDP, 976 .ptype = RTE_PTYPE_TUNNEL_MPLS_IN_UDP | RTE_PTYPE_L4_UDP, 977 }, 978 { 979 .tunnel = MLX5_FLOW_LAYER_MPLS, 980 .ptype = RTE_PTYPE_TUNNEL_MPLS_IN_GRE, 981 }, 982 { 983 .tunnel = MLX5_FLOW_LAYER_NVGRE, 984 .ptype = RTE_PTYPE_TUNNEL_NVGRE, 985 }, 986 { 987 .tunnel = MLX5_FLOW_LAYER_IPIP, 988 .ptype = RTE_PTYPE_TUNNEL_IP, 989 }, 990 { 991 .tunnel = MLX5_FLOW_LAYER_IPV6_ENCAP, 992 .ptype = RTE_PTYPE_TUNNEL_IP, 993 }, 994 { 995 .tunnel = MLX5_FLOW_LAYER_GTP, 996 .ptype = RTE_PTYPE_TUNNEL_GTPU, 997 }, 998 }; 999 1000 1001 1002 /** 1003 * Translate tag ID to register. 1004 * 1005 * @param[in] dev 1006 * Pointer to the Ethernet device structure. 1007 * @param[in] feature 1008 * The feature that request the register. 1009 * @param[in] id 1010 * The request register ID. 1011 * @param[out] error 1012 * Error description in case of any. 1013 * 1014 * @return 1015 * The request register on success, a negative errno 1016 * value otherwise and rte_errno is set. 1017 */ 1018 int 1019 mlx5_flow_get_reg_id(struct rte_eth_dev *dev, 1020 enum mlx5_feature_name feature, 1021 uint32_t id, 1022 struct rte_flow_error *error) 1023 { 1024 struct mlx5_priv *priv = dev->data->dev_private; 1025 struct mlx5_sh_config *config = &priv->sh->config; 1026 enum modify_reg start_reg; 1027 bool skip_mtr_reg = false; 1028 1029 switch (feature) { 1030 case MLX5_HAIRPIN_RX: 1031 return REG_B; 1032 case MLX5_HAIRPIN_TX: 1033 return REG_A; 1034 case MLX5_METADATA_RX: 1035 switch (config->dv_xmeta_en) { 1036 case MLX5_XMETA_MODE_LEGACY: 1037 return REG_B; 1038 case MLX5_XMETA_MODE_META16: 1039 return REG_C_0; 1040 case MLX5_XMETA_MODE_META32: 1041 return REG_C_1; 1042 } 1043 break; 1044 case MLX5_METADATA_TX: 1045 return REG_A; 1046 case MLX5_METADATA_FDB: 1047 switch (config->dv_xmeta_en) { 1048 case MLX5_XMETA_MODE_LEGACY: 1049 return REG_NON; 1050 case MLX5_XMETA_MODE_META16: 1051 return REG_C_0; 1052 case MLX5_XMETA_MODE_META32: 1053 return REG_C_1; 1054 } 1055 break; 1056 case MLX5_FLOW_MARK: 1057 switch (config->dv_xmeta_en) { 1058 case MLX5_XMETA_MODE_LEGACY: 1059 return REG_NON; 1060 case MLX5_XMETA_MODE_META16: 1061 return REG_C_1; 1062 case MLX5_XMETA_MODE_META32: 1063 return REG_C_0; 1064 } 1065 break; 1066 case MLX5_MTR_ID: 1067 /* 1068 * If meter color and meter id share one register, flow match 1069 * should use the meter color register for match. 1070 */ 1071 if (priv->mtr_reg_share) 1072 return priv->mtr_color_reg; 1073 else 1074 return priv->mtr_color_reg != REG_C_2 ? REG_C_2 : 1075 REG_C_3; 1076 case MLX5_MTR_COLOR: 1077 case MLX5_ASO_FLOW_HIT: 1078 case MLX5_ASO_CONNTRACK: 1079 case MLX5_SAMPLE_ID: 1080 /* All features use the same REG_C. */ 1081 MLX5_ASSERT(priv->mtr_color_reg != REG_NON); 1082 return priv->mtr_color_reg; 1083 case MLX5_COPY_MARK: 1084 /* 1085 * Metadata COPY_MARK register using is in meter suffix sub 1086 * flow while with meter. It's safe to share the same register. 1087 */ 1088 return priv->mtr_color_reg != REG_C_2 ? REG_C_2 : REG_C_3; 1089 case MLX5_APP_TAG: 1090 /* 1091 * If meter is enable, it will engage the register for color 1092 * match and flow match. If meter color match is not using the 1093 * REG_C_2, need to skip the REG_C_x be used by meter color 1094 * match. 1095 * If meter is disable, free to use all available registers. 1096 */ 1097 start_reg = priv->mtr_color_reg != REG_C_2 ? REG_C_2 : 1098 (priv->mtr_reg_share ? REG_C_3 : REG_C_4); 1099 skip_mtr_reg = !!(priv->mtr_en && start_reg == REG_C_2); 1100 if (id > (uint32_t)(REG_C_7 - start_reg)) 1101 return rte_flow_error_set(error, EINVAL, 1102 RTE_FLOW_ERROR_TYPE_ITEM, 1103 NULL, "invalid tag id"); 1104 if (priv->sh->flow_mreg_c[id + start_reg - REG_C_0] == REG_NON) 1105 return rte_flow_error_set(error, ENOTSUP, 1106 RTE_FLOW_ERROR_TYPE_ITEM, 1107 NULL, "unsupported tag id"); 1108 /* 1109 * This case means meter is using the REG_C_x great than 2. 1110 * Take care not to conflict with meter color REG_C_x. 1111 * If the available index REG_C_y >= REG_C_x, skip the 1112 * color register. 1113 */ 1114 if (skip_mtr_reg && priv->sh->flow_mreg_c 1115 [id + start_reg - REG_C_0] >= priv->mtr_color_reg) { 1116 if (id >= (uint32_t)(REG_C_7 - start_reg)) 1117 return rte_flow_error_set(error, EINVAL, 1118 RTE_FLOW_ERROR_TYPE_ITEM, 1119 NULL, "invalid tag id"); 1120 if (priv->sh->flow_mreg_c 1121 [id + 1 + start_reg - REG_C_0] != REG_NON) 1122 return priv->sh->flow_mreg_c 1123 [id + 1 + start_reg - REG_C_0]; 1124 return rte_flow_error_set(error, ENOTSUP, 1125 RTE_FLOW_ERROR_TYPE_ITEM, 1126 NULL, "unsupported tag id"); 1127 } 1128 return priv->sh->flow_mreg_c[id + start_reg - REG_C_0]; 1129 } 1130 MLX5_ASSERT(false); 1131 return rte_flow_error_set(error, EINVAL, 1132 RTE_FLOW_ERROR_TYPE_UNSPECIFIED, 1133 NULL, "invalid feature name"); 1134 } 1135 1136 /** 1137 * Check extensive flow metadata register support. 1138 * 1139 * @param dev 1140 * Pointer to rte_eth_dev structure. 1141 * 1142 * @return 1143 * True if device supports extensive flow metadata register, otherwise false. 1144 */ 1145 bool 1146 mlx5_flow_ext_mreg_supported(struct rte_eth_dev *dev) 1147 { 1148 struct mlx5_priv *priv = dev->data->dev_private; 1149 1150 /* 1151 * Having available reg_c can be regarded inclusively as supporting 1152 * extensive flow metadata register, which could mean, 1153 * - metadata register copy action by modify header. 1154 * - 16 modify header actions is supported. 1155 * - reg_c's are preserved across different domain (FDB and NIC) on 1156 * packet loopback by flow lookup miss. 1157 */ 1158 return priv->sh->flow_mreg_c[2] != REG_NON; 1159 } 1160 1161 /** 1162 * Get the lowest priority. 1163 * 1164 * @param[in] dev 1165 * Pointer to the Ethernet device structure. 1166 * @param[in] attributes 1167 * Pointer to device flow rule attributes. 1168 * 1169 * @return 1170 * The value of lowest priority of flow. 1171 */ 1172 uint32_t 1173 mlx5_get_lowest_priority(struct rte_eth_dev *dev, 1174 const struct rte_flow_attr *attr) 1175 { 1176 struct mlx5_priv *priv = dev->data->dev_private; 1177 1178 if (!attr->group && !attr->transfer) 1179 return priv->sh->flow_max_priority - 2; 1180 return MLX5_NON_ROOT_FLOW_MAX_PRIO - 1; 1181 } 1182 1183 /** 1184 * Calculate matcher priority of the flow. 1185 * 1186 * @param[in] dev 1187 * Pointer to the Ethernet device structure. 1188 * @param[in] attr 1189 * Pointer to device flow rule attributes. 1190 * @param[in] subpriority 1191 * The priority based on the items. 1192 * @param[in] external 1193 * Flow is user flow. 1194 * @return 1195 * The matcher priority of the flow. 1196 */ 1197 uint16_t 1198 mlx5_get_matcher_priority(struct rte_eth_dev *dev, 1199 const struct rte_flow_attr *attr, 1200 uint32_t subpriority, bool external) 1201 { 1202 uint16_t priority = (uint16_t)attr->priority; 1203 struct mlx5_priv *priv = dev->data->dev_private; 1204 1205 if (!attr->group && !attr->transfer) { 1206 if (attr->priority == MLX5_FLOW_LOWEST_PRIO_INDICATOR) 1207 priority = priv->sh->flow_max_priority - 1; 1208 return mlx5_os_flow_adjust_priority(dev, priority, subpriority); 1209 } else if (!external && attr->transfer && attr->group == 0 && 1210 attr->priority == MLX5_FLOW_LOWEST_PRIO_INDICATOR) { 1211 return (priv->sh->flow_max_priority - 1) * 3; 1212 } 1213 if (attr->priority == MLX5_FLOW_LOWEST_PRIO_INDICATOR) 1214 priority = MLX5_NON_ROOT_FLOW_MAX_PRIO; 1215 return priority * 3 + subpriority; 1216 } 1217 1218 /** 1219 * Verify the @p item specifications (spec, last, mask) are compatible with the 1220 * NIC capabilities. 1221 * 1222 * @param[in] item 1223 * Item specification. 1224 * @param[in] mask 1225 * @p item->mask or flow default bit-masks. 1226 * @param[in] nic_mask 1227 * Bit-masks covering supported fields by the NIC to compare with user mask. 1228 * @param[in] size 1229 * Bit-masks size in bytes. 1230 * @param[in] range_accepted 1231 * True if range of values is accepted for specific fields, false otherwise. 1232 * @param[out] error 1233 * Pointer to error structure. 1234 * 1235 * @return 1236 * 0 on success, a negative errno value otherwise and rte_errno is set. 1237 */ 1238 int 1239 mlx5_flow_item_acceptable(const struct rte_flow_item *item, 1240 const uint8_t *mask, 1241 const uint8_t *nic_mask, 1242 unsigned int size, 1243 bool range_accepted, 1244 struct rte_flow_error *error) 1245 { 1246 unsigned int i; 1247 1248 MLX5_ASSERT(nic_mask); 1249 for (i = 0; i < size; ++i) 1250 if ((nic_mask[i] | mask[i]) != nic_mask[i]) 1251 return rte_flow_error_set(error, ENOTSUP, 1252 RTE_FLOW_ERROR_TYPE_ITEM, 1253 item, 1254 "mask enables non supported" 1255 " bits"); 1256 if (!item->spec && (item->mask || item->last)) 1257 return rte_flow_error_set(error, EINVAL, 1258 RTE_FLOW_ERROR_TYPE_ITEM, item, 1259 "mask/last without a spec is not" 1260 " supported"); 1261 if (item->spec && item->last && !range_accepted) { 1262 uint8_t spec[size]; 1263 uint8_t last[size]; 1264 unsigned int i; 1265 int ret; 1266 1267 for (i = 0; i < size; ++i) { 1268 spec[i] = ((const uint8_t *)item->spec)[i] & mask[i]; 1269 last[i] = ((const uint8_t *)item->last)[i] & mask[i]; 1270 } 1271 ret = memcmp(spec, last, size); 1272 if (ret != 0) 1273 return rte_flow_error_set(error, EINVAL, 1274 RTE_FLOW_ERROR_TYPE_ITEM, 1275 item, 1276 "range is not valid"); 1277 } 1278 return 0; 1279 } 1280 1281 /** 1282 * Adjust the hash fields according to the @p flow information. 1283 * 1284 * @param[in] dev_flow. 1285 * Pointer to the mlx5_flow. 1286 * @param[in] tunnel 1287 * 1 when the hash field is for a tunnel item. 1288 * @param[in] layer_types 1289 * RTE_ETH_RSS_* types. 1290 * @param[in] hash_fields 1291 * Item hash fields. 1292 * 1293 * @return 1294 * The hash fields that should be used. 1295 */ 1296 uint64_t 1297 mlx5_flow_hashfields_adjust(struct mlx5_flow_rss_desc *rss_desc, 1298 int tunnel __rte_unused, uint64_t layer_types, 1299 uint64_t hash_fields) 1300 { 1301 #ifdef HAVE_IBV_DEVICE_TUNNEL_SUPPORT 1302 int rss_request_inner = rss_desc->level >= 2; 1303 1304 /* Check RSS hash level for tunnel. */ 1305 if (tunnel && rss_request_inner) 1306 hash_fields |= IBV_RX_HASH_INNER; 1307 else if (tunnel || rss_request_inner) 1308 return 0; 1309 #endif 1310 /* Check if requested layer matches RSS hash fields. */ 1311 if (!(rss_desc->types & layer_types)) 1312 return 0; 1313 return hash_fields; 1314 } 1315 1316 /** 1317 * Lookup and set the ptype in the data Rx part. A single Ptype can be used, 1318 * if several tunnel rules are used on this queue, the tunnel ptype will be 1319 * cleared. 1320 * 1321 * @param rxq_ctrl 1322 * Rx queue to update. 1323 */ 1324 static void 1325 flow_rxq_tunnel_ptype_update(struct mlx5_rxq_ctrl *rxq_ctrl) 1326 { 1327 unsigned int i; 1328 uint32_t tunnel_ptype = 0; 1329 1330 /* Look up for the ptype to use. */ 1331 for (i = 0; i != MLX5_FLOW_TUNNEL; ++i) { 1332 if (!rxq_ctrl->flow_tunnels_n[i]) 1333 continue; 1334 if (!tunnel_ptype) { 1335 tunnel_ptype = tunnels_info[i].ptype; 1336 } else { 1337 tunnel_ptype = 0; 1338 break; 1339 } 1340 } 1341 rxq_ctrl->rxq.tunnel = tunnel_ptype; 1342 } 1343 1344 /** 1345 * Set the Rx queue flags (Mark/Flag and Tunnel Ptypes) according to the device 1346 * flow. 1347 * 1348 * @param[in] dev 1349 * Pointer to the Ethernet device structure. 1350 * @param[in] dev_handle 1351 * Pointer to device flow handle structure. 1352 */ 1353 void 1354 flow_drv_rxq_flags_set(struct rte_eth_dev *dev, 1355 struct mlx5_flow_handle *dev_handle) 1356 { 1357 struct mlx5_priv *priv = dev->data->dev_private; 1358 const int tunnel = !!(dev_handle->layers & MLX5_FLOW_LAYER_TUNNEL); 1359 struct mlx5_ind_table_obj *ind_tbl = NULL; 1360 unsigned int i; 1361 1362 if (dev_handle->fate_action == MLX5_FLOW_FATE_QUEUE) { 1363 struct mlx5_hrxq *hrxq; 1364 1365 hrxq = mlx5_ipool_get(priv->sh->ipool[MLX5_IPOOL_HRXQ], 1366 dev_handle->rix_hrxq); 1367 if (hrxq) 1368 ind_tbl = hrxq->ind_table; 1369 } else if (dev_handle->fate_action == MLX5_FLOW_FATE_SHARED_RSS) { 1370 struct mlx5_shared_action_rss *shared_rss; 1371 1372 shared_rss = mlx5_ipool_get 1373 (priv->sh->ipool[MLX5_IPOOL_RSS_SHARED_ACTIONS], 1374 dev_handle->rix_srss); 1375 if (shared_rss) 1376 ind_tbl = shared_rss->ind_tbl; 1377 } 1378 if (!ind_tbl) 1379 return; 1380 for (i = 0; i != ind_tbl->queues_n; ++i) { 1381 int idx = ind_tbl->queues[i]; 1382 struct mlx5_rxq_ctrl *rxq_ctrl = mlx5_rxq_ctrl_get(dev, idx); 1383 1384 MLX5_ASSERT(rxq_ctrl != NULL); 1385 if (rxq_ctrl == NULL) 1386 continue; 1387 /* 1388 * To support metadata register copy on Tx loopback, 1389 * this must be always enabled (metadata may arive 1390 * from other port - not from local flows only. 1391 */ 1392 if (tunnel) { 1393 unsigned int j; 1394 1395 /* Increase the counter matching the flow. */ 1396 for (j = 0; j != MLX5_FLOW_TUNNEL; ++j) { 1397 if ((tunnels_info[j].tunnel & 1398 dev_handle->layers) == 1399 tunnels_info[j].tunnel) { 1400 rxq_ctrl->flow_tunnels_n[j]++; 1401 break; 1402 } 1403 } 1404 flow_rxq_tunnel_ptype_update(rxq_ctrl); 1405 } 1406 } 1407 } 1408 1409 static void 1410 flow_rxq_mark_flag_set(struct rte_eth_dev *dev) 1411 { 1412 struct mlx5_priv *priv = dev->data->dev_private; 1413 struct mlx5_rxq_ctrl *rxq_ctrl; 1414 1415 if (priv->mark_enabled) 1416 return; 1417 LIST_FOREACH(rxq_ctrl, &priv->rxqsctrl, next) { 1418 rxq_ctrl->rxq.mark = 1; 1419 } 1420 priv->mark_enabled = 1; 1421 } 1422 1423 /** 1424 * Set the Rx queue flags (Mark/Flag and Tunnel Ptypes) for a flow 1425 * 1426 * @param[in] dev 1427 * Pointer to the Ethernet device structure. 1428 * @param[in] flow 1429 * Pointer to flow structure. 1430 */ 1431 static void 1432 flow_rxq_flags_set(struct rte_eth_dev *dev, struct rte_flow *flow) 1433 { 1434 struct mlx5_priv *priv = dev->data->dev_private; 1435 uint32_t handle_idx; 1436 struct mlx5_flow_handle *dev_handle; 1437 struct mlx5_flow_workspace *wks = mlx5_flow_get_thread_workspace(); 1438 1439 MLX5_ASSERT(wks); 1440 if (wks->mark) 1441 flow_rxq_mark_flag_set(dev); 1442 SILIST_FOREACH(priv->sh->ipool[MLX5_IPOOL_MLX5_FLOW], flow->dev_handles, 1443 handle_idx, dev_handle, next) 1444 flow_drv_rxq_flags_set(dev, dev_handle); 1445 } 1446 1447 /** 1448 * Clear the Rx queue flags (Mark/Flag and Tunnel Ptype) associated with the 1449 * device flow if no other flow uses it with the same kind of request. 1450 * 1451 * @param dev 1452 * Pointer to Ethernet device. 1453 * @param[in] dev_handle 1454 * Pointer to the device flow handle structure. 1455 */ 1456 static void 1457 flow_drv_rxq_flags_trim(struct rte_eth_dev *dev, 1458 struct mlx5_flow_handle *dev_handle) 1459 { 1460 struct mlx5_priv *priv = dev->data->dev_private; 1461 const int tunnel = !!(dev_handle->layers & MLX5_FLOW_LAYER_TUNNEL); 1462 struct mlx5_ind_table_obj *ind_tbl = NULL; 1463 unsigned int i; 1464 1465 if (dev_handle->fate_action == MLX5_FLOW_FATE_QUEUE) { 1466 struct mlx5_hrxq *hrxq; 1467 1468 hrxq = mlx5_ipool_get(priv->sh->ipool[MLX5_IPOOL_HRXQ], 1469 dev_handle->rix_hrxq); 1470 if (hrxq) 1471 ind_tbl = hrxq->ind_table; 1472 } else if (dev_handle->fate_action == MLX5_FLOW_FATE_SHARED_RSS) { 1473 struct mlx5_shared_action_rss *shared_rss; 1474 1475 shared_rss = mlx5_ipool_get 1476 (priv->sh->ipool[MLX5_IPOOL_RSS_SHARED_ACTIONS], 1477 dev_handle->rix_srss); 1478 if (shared_rss) 1479 ind_tbl = shared_rss->ind_tbl; 1480 } 1481 if (!ind_tbl) 1482 return; 1483 MLX5_ASSERT(dev->data->dev_started); 1484 for (i = 0; i != ind_tbl->queues_n; ++i) { 1485 int idx = ind_tbl->queues[i]; 1486 struct mlx5_rxq_ctrl *rxq_ctrl = mlx5_rxq_ctrl_get(dev, idx); 1487 1488 MLX5_ASSERT(rxq_ctrl != NULL); 1489 if (rxq_ctrl == NULL) 1490 continue; 1491 if (tunnel) { 1492 unsigned int j; 1493 1494 /* Decrease the counter matching the flow. */ 1495 for (j = 0; j != MLX5_FLOW_TUNNEL; ++j) { 1496 if ((tunnels_info[j].tunnel & 1497 dev_handle->layers) == 1498 tunnels_info[j].tunnel) { 1499 rxq_ctrl->flow_tunnels_n[j]--; 1500 break; 1501 } 1502 } 1503 flow_rxq_tunnel_ptype_update(rxq_ctrl); 1504 } 1505 } 1506 } 1507 1508 /** 1509 * Clear the Rx queue flags (Mark/Flag and Tunnel Ptype) associated with the 1510 * @p flow if no other flow uses it with the same kind of request. 1511 * 1512 * @param dev 1513 * Pointer to Ethernet device. 1514 * @param[in] flow 1515 * Pointer to the flow. 1516 */ 1517 static void 1518 flow_rxq_flags_trim(struct rte_eth_dev *dev, struct rte_flow *flow) 1519 { 1520 struct mlx5_priv *priv = dev->data->dev_private; 1521 uint32_t handle_idx; 1522 struct mlx5_flow_handle *dev_handle; 1523 1524 SILIST_FOREACH(priv->sh->ipool[MLX5_IPOOL_MLX5_FLOW], flow->dev_handles, 1525 handle_idx, dev_handle, next) 1526 flow_drv_rxq_flags_trim(dev, dev_handle); 1527 } 1528 1529 /** 1530 * Clear the Mark/Flag and Tunnel ptype information in all Rx queues. 1531 * 1532 * @param dev 1533 * Pointer to Ethernet device. 1534 */ 1535 static void 1536 flow_rxq_flags_clear(struct rte_eth_dev *dev) 1537 { 1538 struct mlx5_priv *priv = dev->data->dev_private; 1539 unsigned int i; 1540 1541 for (i = 0; i != priv->rxqs_n; ++i) { 1542 struct mlx5_rxq_priv *rxq = mlx5_rxq_get(dev, i); 1543 unsigned int j; 1544 1545 if (rxq == NULL || rxq->ctrl == NULL) 1546 continue; 1547 rxq->ctrl->rxq.mark = 0; 1548 for (j = 0; j != MLX5_FLOW_TUNNEL; ++j) 1549 rxq->ctrl->flow_tunnels_n[j] = 0; 1550 rxq->ctrl->rxq.tunnel = 0; 1551 } 1552 priv->mark_enabled = 0; 1553 } 1554 1555 /** 1556 * Set the Rx queue dynamic metadata (mask and offset) for a flow 1557 * 1558 * @param[in] dev 1559 * Pointer to the Ethernet device structure. 1560 */ 1561 void 1562 mlx5_flow_rxq_dynf_metadata_set(struct rte_eth_dev *dev) 1563 { 1564 struct mlx5_priv *priv = dev->data->dev_private; 1565 unsigned int i; 1566 1567 for (i = 0; i != priv->rxqs_n; ++i) { 1568 struct mlx5_rxq_priv *rxq = mlx5_rxq_get(dev, i); 1569 struct mlx5_rxq_data *data; 1570 1571 if (rxq == NULL || rxq->ctrl == NULL) 1572 continue; 1573 data = &rxq->ctrl->rxq; 1574 if (!rte_flow_dynf_metadata_avail()) { 1575 data->dynf_meta = 0; 1576 data->flow_meta_mask = 0; 1577 data->flow_meta_offset = -1; 1578 data->flow_meta_port_mask = 0; 1579 } else { 1580 data->dynf_meta = 1; 1581 data->flow_meta_mask = rte_flow_dynf_metadata_mask; 1582 data->flow_meta_offset = rte_flow_dynf_metadata_offs; 1583 data->flow_meta_port_mask = priv->sh->dv_meta_mask; 1584 } 1585 } 1586 } 1587 1588 /* 1589 * return a pointer to the desired action in the list of actions. 1590 * 1591 * @param[in] actions 1592 * The list of actions to search the action in. 1593 * @param[in] action 1594 * The action to find. 1595 * 1596 * @return 1597 * Pointer to the action in the list, if found. NULL otherwise. 1598 */ 1599 const struct rte_flow_action * 1600 mlx5_flow_find_action(const struct rte_flow_action *actions, 1601 enum rte_flow_action_type action) 1602 { 1603 if (actions == NULL) 1604 return NULL; 1605 for (; actions->type != RTE_FLOW_ACTION_TYPE_END; actions++) 1606 if (actions->type == action) 1607 return actions; 1608 return NULL; 1609 } 1610 1611 /* 1612 * Validate the flag action. 1613 * 1614 * @param[in] action_flags 1615 * Bit-fields that holds the actions detected until now. 1616 * @param[in] attr 1617 * Attributes of flow that includes this action. 1618 * @param[out] error 1619 * Pointer to error structure. 1620 * 1621 * @return 1622 * 0 on success, a negative errno value otherwise and rte_errno is set. 1623 */ 1624 int 1625 mlx5_flow_validate_action_flag(uint64_t action_flags, 1626 const struct rte_flow_attr *attr, 1627 struct rte_flow_error *error) 1628 { 1629 if (action_flags & MLX5_FLOW_ACTION_MARK) 1630 return rte_flow_error_set(error, EINVAL, 1631 RTE_FLOW_ERROR_TYPE_ACTION, NULL, 1632 "can't mark and flag in same flow"); 1633 if (action_flags & MLX5_FLOW_ACTION_FLAG) 1634 return rte_flow_error_set(error, EINVAL, 1635 RTE_FLOW_ERROR_TYPE_ACTION, NULL, 1636 "can't have 2 flag" 1637 " actions in same flow"); 1638 if (attr->egress) 1639 return rte_flow_error_set(error, ENOTSUP, 1640 RTE_FLOW_ERROR_TYPE_ATTR_EGRESS, NULL, 1641 "flag action not supported for " 1642 "egress"); 1643 return 0; 1644 } 1645 1646 /* 1647 * Validate the mark action. 1648 * 1649 * @param[in] action 1650 * Pointer to the queue action. 1651 * @param[in] action_flags 1652 * Bit-fields that holds the actions detected until now. 1653 * @param[in] attr 1654 * Attributes of flow that includes this action. 1655 * @param[out] error 1656 * Pointer to error structure. 1657 * 1658 * @return 1659 * 0 on success, a negative errno value otherwise and rte_errno is set. 1660 */ 1661 int 1662 mlx5_flow_validate_action_mark(const struct rte_flow_action *action, 1663 uint64_t action_flags, 1664 const struct rte_flow_attr *attr, 1665 struct rte_flow_error *error) 1666 { 1667 const struct rte_flow_action_mark *mark = action->conf; 1668 1669 if (!mark) 1670 return rte_flow_error_set(error, EINVAL, 1671 RTE_FLOW_ERROR_TYPE_ACTION, 1672 action, 1673 "configuration cannot be null"); 1674 if (mark->id >= MLX5_FLOW_MARK_MAX) 1675 return rte_flow_error_set(error, EINVAL, 1676 RTE_FLOW_ERROR_TYPE_ACTION_CONF, 1677 &mark->id, 1678 "mark id must in 0 <= id < " 1679 RTE_STR(MLX5_FLOW_MARK_MAX)); 1680 if (action_flags & MLX5_FLOW_ACTION_FLAG) 1681 return rte_flow_error_set(error, EINVAL, 1682 RTE_FLOW_ERROR_TYPE_ACTION, NULL, 1683 "can't flag and mark in same flow"); 1684 if (action_flags & MLX5_FLOW_ACTION_MARK) 1685 return rte_flow_error_set(error, EINVAL, 1686 RTE_FLOW_ERROR_TYPE_ACTION, NULL, 1687 "can't have 2 mark actions in same" 1688 " flow"); 1689 if (attr->egress) 1690 return rte_flow_error_set(error, ENOTSUP, 1691 RTE_FLOW_ERROR_TYPE_ATTR_EGRESS, NULL, 1692 "mark action not supported for " 1693 "egress"); 1694 return 0; 1695 } 1696 1697 /* 1698 * Validate the drop action. 1699 * 1700 * @param[in] action_flags 1701 * Bit-fields that holds the actions detected until now. 1702 * @param[in] attr 1703 * Attributes of flow that includes this action. 1704 * @param[out] error 1705 * Pointer to error structure. 1706 * 1707 * @return 1708 * 0 on success, a negative errno value otherwise and rte_errno is set. 1709 */ 1710 int 1711 mlx5_flow_validate_action_drop(uint64_t action_flags __rte_unused, 1712 const struct rte_flow_attr *attr, 1713 struct rte_flow_error *error) 1714 { 1715 if (attr->egress) 1716 return rte_flow_error_set(error, ENOTSUP, 1717 RTE_FLOW_ERROR_TYPE_ATTR_EGRESS, NULL, 1718 "drop action not supported for " 1719 "egress"); 1720 return 0; 1721 } 1722 1723 /* 1724 * Validate the queue action. 1725 * 1726 * @param[in] action 1727 * Pointer to the queue action. 1728 * @param[in] action_flags 1729 * Bit-fields that holds the actions detected until now. 1730 * @param[in] dev 1731 * Pointer to the Ethernet device structure. 1732 * @param[in] attr 1733 * Attributes of flow that includes this action. 1734 * @param[out] error 1735 * Pointer to error structure. 1736 * 1737 * @return 1738 * 0 on success, a negative errno value otherwise and rte_errno is set. 1739 */ 1740 int 1741 mlx5_flow_validate_action_queue(const struct rte_flow_action *action, 1742 uint64_t action_flags, 1743 struct rte_eth_dev *dev, 1744 const struct rte_flow_attr *attr, 1745 struct rte_flow_error *error) 1746 { 1747 struct mlx5_priv *priv = dev->data->dev_private; 1748 const struct rte_flow_action_queue *queue = action->conf; 1749 1750 if (action_flags & MLX5_FLOW_FATE_ACTIONS) 1751 return rte_flow_error_set(error, EINVAL, 1752 RTE_FLOW_ERROR_TYPE_ACTION, NULL, 1753 "can't have 2 fate actions in" 1754 " same flow"); 1755 if (attr->egress) 1756 return rte_flow_error_set(error, ENOTSUP, 1757 RTE_FLOW_ERROR_TYPE_ATTR_EGRESS, NULL, 1758 "queue action not supported for egress."); 1759 if (mlx5_is_external_rxq(dev, queue->index)) 1760 return 0; 1761 if (!priv->rxqs_n) 1762 return rte_flow_error_set(error, EINVAL, 1763 RTE_FLOW_ERROR_TYPE_ACTION_CONF, 1764 NULL, "No Rx queues configured"); 1765 if (queue->index >= priv->rxqs_n) 1766 return rte_flow_error_set(error, EINVAL, 1767 RTE_FLOW_ERROR_TYPE_ACTION_CONF, 1768 &queue->index, 1769 "queue index out of range"); 1770 if (mlx5_rxq_get(dev, queue->index) == NULL) 1771 return rte_flow_error_set(error, EINVAL, 1772 RTE_FLOW_ERROR_TYPE_ACTION_CONF, 1773 &queue->index, 1774 "queue is not configured"); 1775 return 0; 1776 } 1777 1778 /** 1779 * Validate queue numbers for device RSS. 1780 * 1781 * @param[in] dev 1782 * Configured device. 1783 * @param[in] queues 1784 * Array of queue numbers. 1785 * @param[in] queues_n 1786 * Size of the @p queues array. 1787 * @param[out] error 1788 * On error, filled with a textual error description. 1789 * @param[out] queue_idx 1790 * On error, filled with an offending queue index in @p queues array. 1791 * 1792 * @return 1793 * 0 on success, a negative errno code on error. 1794 */ 1795 static int 1796 mlx5_validate_rss_queues(struct rte_eth_dev *dev, 1797 const uint16_t *queues, uint32_t queues_n, 1798 const char **error, uint32_t *queue_idx) 1799 { 1800 const struct mlx5_priv *priv = dev->data->dev_private; 1801 bool is_hairpin = false; 1802 bool is_ext_rss = false; 1803 uint32_t i; 1804 1805 for (i = 0; i != queues_n; ++i) { 1806 struct mlx5_rxq_ctrl *rxq_ctrl; 1807 1808 if (mlx5_is_external_rxq(dev, queues[0])) { 1809 is_ext_rss = true; 1810 continue; 1811 } 1812 if (is_ext_rss) { 1813 *error = "Combining external and regular RSS queues is not supported"; 1814 *queue_idx = i; 1815 return -ENOTSUP; 1816 } 1817 if (queues[i] >= priv->rxqs_n) { 1818 *error = "queue index out of range"; 1819 *queue_idx = i; 1820 return -EINVAL; 1821 } 1822 rxq_ctrl = mlx5_rxq_ctrl_get(dev, queues[i]); 1823 if (rxq_ctrl == NULL) { 1824 *error = "queue is not configured"; 1825 *queue_idx = i; 1826 return -EINVAL; 1827 } 1828 if (i == 0 && rxq_ctrl->is_hairpin) 1829 is_hairpin = true; 1830 if (is_hairpin != rxq_ctrl->is_hairpin) { 1831 *error = "combining hairpin and regular RSS queues is not supported"; 1832 *queue_idx = i; 1833 return -ENOTSUP; 1834 } 1835 } 1836 return 0; 1837 } 1838 1839 /* 1840 * Validate the rss action. 1841 * 1842 * @param[in] dev 1843 * Pointer to the Ethernet device structure. 1844 * @param[in] action 1845 * Pointer to the queue action. 1846 * @param[out] error 1847 * Pointer to error structure. 1848 * 1849 * @return 1850 * 0 on success, a negative errno value otherwise and rte_errno is set. 1851 */ 1852 int 1853 mlx5_validate_action_rss(struct rte_eth_dev *dev, 1854 const struct rte_flow_action *action, 1855 struct rte_flow_error *error) 1856 { 1857 struct mlx5_priv *priv = dev->data->dev_private; 1858 const struct rte_flow_action_rss *rss = action->conf; 1859 int ret; 1860 const char *message; 1861 uint32_t queue_idx; 1862 1863 if (rss->func != RTE_ETH_HASH_FUNCTION_DEFAULT && 1864 rss->func != RTE_ETH_HASH_FUNCTION_TOEPLITZ) 1865 return rte_flow_error_set(error, ENOTSUP, 1866 RTE_FLOW_ERROR_TYPE_ACTION_CONF, 1867 &rss->func, 1868 "RSS hash function not supported"); 1869 #ifdef HAVE_IBV_DEVICE_TUNNEL_SUPPORT 1870 if (rss->level > 2) 1871 #else 1872 if (rss->level > 1) 1873 #endif 1874 return rte_flow_error_set(error, ENOTSUP, 1875 RTE_FLOW_ERROR_TYPE_ACTION_CONF, 1876 &rss->level, 1877 "tunnel RSS is not supported"); 1878 /* allow RSS key_len 0 in case of NULL (default) RSS key. */ 1879 if (rss->key_len == 0 && rss->key != NULL) 1880 return rte_flow_error_set(error, ENOTSUP, 1881 RTE_FLOW_ERROR_TYPE_ACTION_CONF, 1882 &rss->key_len, 1883 "RSS hash key length 0"); 1884 if (rss->key_len > 0 && rss->key_len < MLX5_RSS_HASH_KEY_LEN) 1885 return rte_flow_error_set(error, ENOTSUP, 1886 RTE_FLOW_ERROR_TYPE_ACTION_CONF, 1887 &rss->key_len, 1888 "RSS hash key too small"); 1889 if (rss->key_len > MLX5_RSS_HASH_KEY_LEN) 1890 return rte_flow_error_set(error, ENOTSUP, 1891 RTE_FLOW_ERROR_TYPE_ACTION_CONF, 1892 &rss->key_len, 1893 "RSS hash key too large"); 1894 if (rss->queue_num > priv->sh->dev_cap.ind_table_max_size) 1895 return rte_flow_error_set(error, ENOTSUP, 1896 RTE_FLOW_ERROR_TYPE_ACTION_CONF, 1897 &rss->queue_num, 1898 "number of queues too large"); 1899 if (rss->types & MLX5_RSS_HF_MASK) 1900 return rte_flow_error_set(error, ENOTSUP, 1901 RTE_FLOW_ERROR_TYPE_ACTION_CONF, 1902 &rss->types, 1903 "some RSS protocols are not" 1904 " supported"); 1905 if ((rss->types & (RTE_ETH_RSS_L3_SRC_ONLY | RTE_ETH_RSS_L3_DST_ONLY)) && 1906 !(rss->types & RTE_ETH_RSS_IP)) 1907 return rte_flow_error_set(error, EINVAL, 1908 RTE_FLOW_ERROR_TYPE_ACTION_CONF, NULL, 1909 "L3 partial RSS requested but L3 RSS" 1910 " type not specified"); 1911 if ((rss->types & (RTE_ETH_RSS_L4_SRC_ONLY | RTE_ETH_RSS_L4_DST_ONLY)) && 1912 !(rss->types & (RTE_ETH_RSS_UDP | RTE_ETH_RSS_TCP))) 1913 return rte_flow_error_set(error, EINVAL, 1914 RTE_FLOW_ERROR_TYPE_ACTION_CONF, NULL, 1915 "L4 partial RSS requested but L4 RSS" 1916 " type not specified"); 1917 if (!priv->rxqs_n && priv->ext_rxqs == NULL) 1918 return rte_flow_error_set(error, EINVAL, 1919 RTE_FLOW_ERROR_TYPE_ACTION_CONF, 1920 NULL, "No Rx queues configured"); 1921 if (!rss->queue_num) 1922 return rte_flow_error_set(error, EINVAL, 1923 RTE_FLOW_ERROR_TYPE_ACTION_CONF, 1924 NULL, "No queues configured"); 1925 ret = mlx5_validate_rss_queues(dev, rss->queue, rss->queue_num, 1926 &message, &queue_idx); 1927 if (ret != 0) { 1928 return rte_flow_error_set(error, -ret, 1929 RTE_FLOW_ERROR_TYPE_ACTION_CONF, 1930 &rss->queue[queue_idx], message); 1931 } 1932 return 0; 1933 } 1934 1935 /* 1936 * Validate the rss action. 1937 * 1938 * @param[in] action 1939 * Pointer to the queue action. 1940 * @param[in] action_flags 1941 * Bit-fields that holds the actions detected until now. 1942 * @param[in] dev 1943 * Pointer to the Ethernet device structure. 1944 * @param[in] attr 1945 * Attributes of flow that includes this action. 1946 * @param[in] item_flags 1947 * Items that were detected. 1948 * @param[out] error 1949 * Pointer to error structure. 1950 * 1951 * @return 1952 * 0 on success, a negative errno value otherwise and rte_errno is set. 1953 */ 1954 int 1955 mlx5_flow_validate_action_rss(const struct rte_flow_action *action, 1956 uint64_t action_flags, 1957 struct rte_eth_dev *dev, 1958 const struct rte_flow_attr *attr, 1959 uint64_t item_flags, 1960 struct rte_flow_error *error) 1961 { 1962 const struct rte_flow_action_rss *rss = action->conf; 1963 int tunnel = !!(item_flags & MLX5_FLOW_LAYER_TUNNEL); 1964 int ret; 1965 1966 if (action_flags & MLX5_FLOW_FATE_ACTIONS) 1967 return rte_flow_error_set(error, EINVAL, 1968 RTE_FLOW_ERROR_TYPE_ACTION, NULL, 1969 "can't have 2 fate actions" 1970 " in same flow"); 1971 ret = mlx5_validate_action_rss(dev, action, error); 1972 if (ret) 1973 return ret; 1974 if (attr->egress) 1975 return rte_flow_error_set(error, ENOTSUP, 1976 RTE_FLOW_ERROR_TYPE_ATTR_EGRESS, NULL, 1977 "rss action not supported for " 1978 "egress"); 1979 if (rss->level > 1 && !tunnel) 1980 return rte_flow_error_set(error, EINVAL, 1981 RTE_FLOW_ERROR_TYPE_ACTION_CONF, NULL, 1982 "inner RSS is not supported for " 1983 "non-tunnel flows"); 1984 if ((item_flags & MLX5_FLOW_LAYER_ECPRI) && 1985 !(item_flags & MLX5_FLOW_LAYER_INNER_L4_UDP)) { 1986 return rte_flow_error_set(error, EINVAL, 1987 RTE_FLOW_ERROR_TYPE_ACTION_CONF, NULL, 1988 "RSS on eCPRI is not supported now"); 1989 } 1990 if ((item_flags & MLX5_FLOW_LAYER_MPLS) && 1991 !(item_flags & 1992 (MLX5_FLOW_LAYER_INNER_L2 | MLX5_FLOW_LAYER_INNER_L3)) && 1993 rss->level > 1) 1994 return rte_flow_error_set(error, EINVAL, 1995 RTE_FLOW_ERROR_TYPE_ITEM, NULL, 1996 "MPLS inner RSS needs to specify inner L2/L3 items after MPLS in pattern"); 1997 return 0; 1998 } 1999 2000 /* 2001 * Validate the default miss action. 2002 * 2003 * @param[in] action_flags 2004 * Bit-fields that holds the actions detected until now. 2005 * @param[out] error 2006 * Pointer to error structure. 2007 * 2008 * @return 2009 * 0 on success, a negative errno value otherwise and rte_errno is set. 2010 */ 2011 int 2012 mlx5_flow_validate_action_default_miss(uint64_t action_flags, 2013 const struct rte_flow_attr *attr, 2014 struct rte_flow_error *error) 2015 { 2016 if (action_flags & MLX5_FLOW_FATE_ACTIONS) 2017 return rte_flow_error_set(error, EINVAL, 2018 RTE_FLOW_ERROR_TYPE_ACTION, NULL, 2019 "can't have 2 fate actions in" 2020 " same flow"); 2021 if (attr->egress) 2022 return rte_flow_error_set(error, ENOTSUP, 2023 RTE_FLOW_ERROR_TYPE_ATTR_EGRESS, NULL, 2024 "default miss action not supported " 2025 "for egress"); 2026 if (attr->group) 2027 return rte_flow_error_set(error, ENOTSUP, 2028 RTE_FLOW_ERROR_TYPE_ATTR_GROUP, NULL, 2029 "only group 0 is supported"); 2030 if (attr->transfer) 2031 return rte_flow_error_set(error, ENOTSUP, 2032 RTE_FLOW_ERROR_TYPE_ATTR_TRANSFER, 2033 NULL, "transfer is not supported"); 2034 return 0; 2035 } 2036 2037 /* 2038 * Validate the count action. 2039 * 2040 * @param[in] dev 2041 * Pointer to the Ethernet device structure. 2042 * @param[in] attr 2043 * Attributes of flow that includes this action. 2044 * @param[out] error 2045 * Pointer to error structure. 2046 * 2047 * @return 2048 * 0 on success, a negative errno value otherwise and rte_errno is set. 2049 */ 2050 int 2051 mlx5_flow_validate_action_count(struct rte_eth_dev *dev __rte_unused, 2052 const struct rte_flow_attr *attr, 2053 struct rte_flow_error *error) 2054 { 2055 if (attr->egress) 2056 return rte_flow_error_set(error, ENOTSUP, 2057 RTE_FLOW_ERROR_TYPE_ATTR_EGRESS, NULL, 2058 "count action not supported for " 2059 "egress"); 2060 return 0; 2061 } 2062 2063 /* 2064 * Validate the ASO CT action. 2065 * 2066 * @param[in] dev 2067 * Pointer to the Ethernet device structure. 2068 * @param[in] conntrack 2069 * Pointer to the CT action profile. 2070 * @param[out] error 2071 * Pointer to error structure. 2072 * 2073 * @return 2074 * 0 on success, a negative errno value otherwise and rte_errno is set. 2075 */ 2076 int 2077 mlx5_validate_action_ct(struct rte_eth_dev *dev, 2078 const struct rte_flow_action_conntrack *conntrack, 2079 struct rte_flow_error *error) 2080 { 2081 RTE_SET_USED(dev); 2082 2083 if (conntrack->state > RTE_FLOW_CONNTRACK_STATE_TIME_WAIT) 2084 return rte_flow_error_set(error, EINVAL, 2085 RTE_FLOW_ERROR_TYPE_ACTION, NULL, 2086 "Invalid CT state"); 2087 if (conntrack->last_index > RTE_FLOW_CONNTRACK_FLAG_RST) 2088 return rte_flow_error_set(error, EINVAL, 2089 RTE_FLOW_ERROR_TYPE_ACTION, NULL, 2090 "Invalid last TCP packet flag"); 2091 return 0; 2092 } 2093 2094 /** 2095 * Verify the @p attributes will be correctly understood by the NIC and store 2096 * them in the @p flow if everything is correct. 2097 * 2098 * @param[in] dev 2099 * Pointer to the Ethernet device structure. 2100 * @param[in] attributes 2101 * Pointer to flow attributes 2102 * @param[out] error 2103 * Pointer to error structure. 2104 * 2105 * @return 2106 * 0 on success, a negative errno value otherwise and rte_errno is set. 2107 */ 2108 int 2109 mlx5_flow_validate_attributes(struct rte_eth_dev *dev, 2110 const struct rte_flow_attr *attributes, 2111 struct rte_flow_error *error) 2112 { 2113 struct mlx5_priv *priv = dev->data->dev_private; 2114 uint32_t priority_max = priv->sh->flow_max_priority - 1; 2115 2116 if (attributes->group) 2117 return rte_flow_error_set(error, ENOTSUP, 2118 RTE_FLOW_ERROR_TYPE_ATTR_GROUP, 2119 NULL, "groups is not supported"); 2120 if (attributes->priority != MLX5_FLOW_LOWEST_PRIO_INDICATOR && 2121 attributes->priority >= priority_max) 2122 return rte_flow_error_set(error, ENOTSUP, 2123 RTE_FLOW_ERROR_TYPE_ATTR_PRIORITY, 2124 NULL, "priority out of range"); 2125 if (attributes->egress) 2126 return rte_flow_error_set(error, ENOTSUP, 2127 RTE_FLOW_ERROR_TYPE_ATTR_EGRESS, NULL, 2128 "egress is not supported"); 2129 if (attributes->transfer && !priv->sh->config.dv_esw_en) 2130 return rte_flow_error_set(error, ENOTSUP, 2131 RTE_FLOW_ERROR_TYPE_ATTR_TRANSFER, 2132 NULL, "transfer is not supported"); 2133 if (!attributes->ingress) 2134 return rte_flow_error_set(error, EINVAL, 2135 RTE_FLOW_ERROR_TYPE_ATTR_INGRESS, 2136 NULL, 2137 "ingress attribute is mandatory"); 2138 return 0; 2139 } 2140 2141 /** 2142 * Validate ICMP6 item. 2143 * 2144 * @param[in] item 2145 * Item specification. 2146 * @param[in] item_flags 2147 * Bit-fields that holds the items detected until now. 2148 * @param[in] ext_vlan_sup 2149 * Whether extended VLAN features are supported or not. 2150 * @param[out] error 2151 * Pointer to error structure. 2152 * 2153 * @return 2154 * 0 on success, a negative errno value otherwise and rte_errno is set. 2155 */ 2156 int 2157 mlx5_flow_validate_item_icmp6(const struct rte_flow_item *item, 2158 uint64_t item_flags, 2159 uint8_t target_protocol, 2160 struct rte_flow_error *error) 2161 { 2162 const struct rte_flow_item_icmp6 *mask = item->mask; 2163 const int tunnel = !!(item_flags & MLX5_FLOW_LAYER_TUNNEL); 2164 const uint64_t l3m = tunnel ? MLX5_FLOW_LAYER_INNER_L3_IPV6 : 2165 MLX5_FLOW_LAYER_OUTER_L3_IPV6; 2166 const uint64_t l4m = tunnel ? MLX5_FLOW_LAYER_INNER_L4 : 2167 MLX5_FLOW_LAYER_OUTER_L4; 2168 int ret; 2169 2170 if (target_protocol != 0xFF && target_protocol != IPPROTO_ICMPV6) 2171 return rte_flow_error_set(error, EINVAL, 2172 RTE_FLOW_ERROR_TYPE_ITEM, item, 2173 "protocol filtering not compatible" 2174 " with ICMP6 layer"); 2175 if (!(item_flags & l3m)) 2176 return rte_flow_error_set(error, EINVAL, 2177 RTE_FLOW_ERROR_TYPE_ITEM, item, 2178 "IPv6 is mandatory to filter on" 2179 " ICMP6"); 2180 if (item_flags & l4m) 2181 return rte_flow_error_set(error, EINVAL, 2182 RTE_FLOW_ERROR_TYPE_ITEM, item, 2183 "multiple L4 layers not supported"); 2184 if (!mask) 2185 mask = &rte_flow_item_icmp6_mask; 2186 ret = mlx5_flow_item_acceptable 2187 (item, (const uint8_t *)mask, 2188 (const uint8_t *)&rte_flow_item_icmp6_mask, 2189 sizeof(struct rte_flow_item_icmp6), 2190 MLX5_ITEM_RANGE_NOT_ACCEPTED, error); 2191 if (ret < 0) 2192 return ret; 2193 return 0; 2194 } 2195 2196 /** 2197 * Validate ICMP item. 2198 * 2199 * @param[in] item 2200 * Item specification. 2201 * @param[in] item_flags 2202 * Bit-fields that holds the items detected until now. 2203 * @param[out] error 2204 * Pointer to error structure. 2205 * 2206 * @return 2207 * 0 on success, a negative errno value otherwise and rte_errno is set. 2208 */ 2209 int 2210 mlx5_flow_validate_item_icmp(const struct rte_flow_item *item, 2211 uint64_t item_flags, 2212 uint8_t target_protocol, 2213 struct rte_flow_error *error) 2214 { 2215 const struct rte_flow_item_icmp *mask = item->mask; 2216 const struct rte_flow_item_icmp nic_mask = { 2217 .hdr.icmp_type = 0xff, 2218 .hdr.icmp_code = 0xff, 2219 .hdr.icmp_ident = RTE_BE16(0xffff), 2220 .hdr.icmp_seq_nb = RTE_BE16(0xffff), 2221 }; 2222 const int tunnel = !!(item_flags & MLX5_FLOW_LAYER_TUNNEL); 2223 const uint64_t l3m = tunnel ? MLX5_FLOW_LAYER_INNER_L3_IPV4 : 2224 MLX5_FLOW_LAYER_OUTER_L3_IPV4; 2225 const uint64_t l4m = tunnel ? MLX5_FLOW_LAYER_INNER_L4 : 2226 MLX5_FLOW_LAYER_OUTER_L4; 2227 int ret; 2228 2229 if (target_protocol != 0xFF && target_protocol != IPPROTO_ICMP) 2230 return rte_flow_error_set(error, EINVAL, 2231 RTE_FLOW_ERROR_TYPE_ITEM, item, 2232 "protocol filtering not compatible" 2233 " with ICMP layer"); 2234 if (!(item_flags & l3m)) 2235 return rte_flow_error_set(error, EINVAL, 2236 RTE_FLOW_ERROR_TYPE_ITEM, item, 2237 "IPv4 is mandatory to filter" 2238 " on ICMP"); 2239 if (item_flags & l4m) 2240 return rte_flow_error_set(error, EINVAL, 2241 RTE_FLOW_ERROR_TYPE_ITEM, item, 2242 "multiple L4 layers not supported"); 2243 if (!mask) 2244 mask = &nic_mask; 2245 ret = mlx5_flow_item_acceptable 2246 (item, (const uint8_t *)mask, 2247 (const uint8_t *)&nic_mask, 2248 sizeof(struct rte_flow_item_icmp), 2249 MLX5_ITEM_RANGE_NOT_ACCEPTED, error); 2250 if (ret < 0) 2251 return ret; 2252 return 0; 2253 } 2254 2255 /** 2256 * Validate Ethernet item. 2257 * 2258 * @param[in] item 2259 * Item specification. 2260 * @param[in] item_flags 2261 * Bit-fields that holds the items detected until now. 2262 * @param[out] error 2263 * Pointer to error structure. 2264 * 2265 * @return 2266 * 0 on success, a negative errno value otherwise and rte_errno is set. 2267 */ 2268 int 2269 mlx5_flow_validate_item_eth(const struct rte_flow_item *item, 2270 uint64_t item_flags, bool ext_vlan_sup, 2271 struct rte_flow_error *error) 2272 { 2273 const struct rte_flow_item_eth *mask = item->mask; 2274 const struct rte_flow_item_eth nic_mask = { 2275 .dst.addr_bytes = "\xff\xff\xff\xff\xff\xff", 2276 .src.addr_bytes = "\xff\xff\xff\xff\xff\xff", 2277 .type = RTE_BE16(0xffff), 2278 .has_vlan = ext_vlan_sup ? 1 : 0, 2279 }; 2280 int ret; 2281 int tunnel = !!(item_flags & MLX5_FLOW_LAYER_TUNNEL); 2282 const uint64_t ethm = tunnel ? MLX5_FLOW_LAYER_INNER_L2 : 2283 MLX5_FLOW_LAYER_OUTER_L2; 2284 2285 if (item_flags & ethm) 2286 return rte_flow_error_set(error, ENOTSUP, 2287 RTE_FLOW_ERROR_TYPE_ITEM, item, 2288 "multiple L2 layers not supported"); 2289 if ((!tunnel && (item_flags & MLX5_FLOW_LAYER_OUTER_L3)) || 2290 (tunnel && (item_flags & MLX5_FLOW_LAYER_INNER_L3))) 2291 return rte_flow_error_set(error, EINVAL, 2292 RTE_FLOW_ERROR_TYPE_ITEM, item, 2293 "L2 layer should not follow " 2294 "L3 layers"); 2295 if ((!tunnel && (item_flags & MLX5_FLOW_LAYER_OUTER_VLAN)) || 2296 (tunnel && (item_flags & MLX5_FLOW_LAYER_INNER_VLAN))) 2297 return rte_flow_error_set(error, EINVAL, 2298 RTE_FLOW_ERROR_TYPE_ITEM, item, 2299 "L2 layer should not follow VLAN"); 2300 if (item_flags & MLX5_FLOW_LAYER_GTP) 2301 return rte_flow_error_set(error, EINVAL, 2302 RTE_FLOW_ERROR_TYPE_ITEM, item, 2303 "L2 layer should not follow GTP"); 2304 if (!mask) 2305 mask = &rte_flow_item_eth_mask; 2306 ret = mlx5_flow_item_acceptable(item, (const uint8_t *)mask, 2307 (const uint8_t *)&nic_mask, 2308 sizeof(struct rte_flow_item_eth), 2309 MLX5_ITEM_RANGE_NOT_ACCEPTED, error); 2310 return ret; 2311 } 2312 2313 /** 2314 * Validate VLAN item. 2315 * 2316 * @param[in] item 2317 * Item specification. 2318 * @param[in] item_flags 2319 * Bit-fields that holds the items detected until now. 2320 * @param[in] dev 2321 * Ethernet device flow is being created on. 2322 * @param[out] error 2323 * Pointer to error structure. 2324 * 2325 * @return 2326 * 0 on success, a negative errno value otherwise and rte_errno is set. 2327 */ 2328 int 2329 mlx5_flow_validate_item_vlan(const struct rte_flow_item *item, 2330 uint64_t item_flags, 2331 struct rte_eth_dev *dev, 2332 struct rte_flow_error *error) 2333 { 2334 const struct rte_flow_item_vlan *spec = item->spec; 2335 const struct rte_flow_item_vlan *mask = item->mask; 2336 const struct rte_flow_item_vlan nic_mask = { 2337 .tci = RTE_BE16(UINT16_MAX), 2338 .inner_type = RTE_BE16(UINT16_MAX), 2339 }; 2340 uint16_t vlan_tag = 0; 2341 const int tunnel = !!(item_flags & MLX5_FLOW_LAYER_TUNNEL); 2342 int ret; 2343 const uint64_t l34m = tunnel ? (MLX5_FLOW_LAYER_INNER_L3 | 2344 MLX5_FLOW_LAYER_INNER_L4) : 2345 (MLX5_FLOW_LAYER_OUTER_L3 | 2346 MLX5_FLOW_LAYER_OUTER_L4); 2347 const uint64_t vlanm = tunnel ? MLX5_FLOW_LAYER_INNER_VLAN : 2348 MLX5_FLOW_LAYER_OUTER_VLAN; 2349 2350 if (item_flags & vlanm) 2351 return rte_flow_error_set(error, EINVAL, 2352 RTE_FLOW_ERROR_TYPE_ITEM, item, 2353 "multiple VLAN layers not supported"); 2354 else if ((item_flags & l34m) != 0) 2355 return rte_flow_error_set(error, EINVAL, 2356 RTE_FLOW_ERROR_TYPE_ITEM, item, 2357 "VLAN cannot follow L3/L4 layer"); 2358 if (!mask) 2359 mask = &rte_flow_item_vlan_mask; 2360 ret = mlx5_flow_item_acceptable(item, (const uint8_t *)mask, 2361 (const uint8_t *)&nic_mask, 2362 sizeof(struct rte_flow_item_vlan), 2363 MLX5_ITEM_RANGE_NOT_ACCEPTED, error); 2364 if (ret) 2365 return ret; 2366 if (!tunnel && mask->tci != RTE_BE16(0x0fff)) { 2367 struct mlx5_priv *priv = dev->data->dev_private; 2368 2369 if (priv->vmwa_context) { 2370 /* 2371 * Non-NULL context means we have a virtual machine 2372 * and SR-IOV enabled, we have to create VLAN interface 2373 * to make hypervisor to setup E-Switch vport 2374 * context correctly. We avoid creating the multiple 2375 * VLAN interfaces, so we cannot support VLAN tag mask. 2376 */ 2377 return rte_flow_error_set(error, EINVAL, 2378 RTE_FLOW_ERROR_TYPE_ITEM, 2379 item, 2380 "VLAN tag mask is not" 2381 " supported in virtual" 2382 " environment"); 2383 } 2384 } 2385 if (spec) { 2386 vlan_tag = spec->tci; 2387 vlan_tag &= mask->tci; 2388 } 2389 /* 2390 * From verbs perspective an empty VLAN is equivalent 2391 * to a packet without VLAN layer. 2392 */ 2393 if (!vlan_tag) 2394 return rte_flow_error_set(error, EINVAL, 2395 RTE_FLOW_ERROR_TYPE_ITEM_SPEC, 2396 item->spec, 2397 "VLAN cannot be empty"); 2398 return 0; 2399 } 2400 2401 /** 2402 * Validate IPV4 item. 2403 * 2404 * @param[in] item 2405 * Item specification. 2406 * @param[in] item_flags 2407 * Bit-fields that holds the items detected until now. 2408 * @param[in] last_item 2409 * Previous validated item in the pattern items. 2410 * @param[in] ether_type 2411 * Type in the ethernet layer header (including dot1q). 2412 * @param[in] acc_mask 2413 * Acceptable mask, if NULL default internal default mask 2414 * will be used to check whether item fields are supported. 2415 * @param[in] range_accepted 2416 * True if range of values is accepted for specific fields, false otherwise. 2417 * @param[out] error 2418 * Pointer to error structure. 2419 * 2420 * @return 2421 * 0 on success, a negative errno value otherwise and rte_errno is set. 2422 */ 2423 int 2424 mlx5_flow_validate_item_ipv4(const struct rte_flow_item *item, 2425 uint64_t item_flags, 2426 uint64_t last_item, 2427 uint16_t ether_type, 2428 const struct rte_flow_item_ipv4 *acc_mask, 2429 bool range_accepted, 2430 struct rte_flow_error *error) 2431 { 2432 const struct rte_flow_item_ipv4 *mask = item->mask; 2433 const struct rte_flow_item_ipv4 *spec = item->spec; 2434 const struct rte_flow_item_ipv4 nic_mask = { 2435 .hdr = { 2436 .src_addr = RTE_BE32(0xffffffff), 2437 .dst_addr = RTE_BE32(0xffffffff), 2438 .type_of_service = 0xff, 2439 .next_proto_id = 0xff, 2440 }, 2441 }; 2442 const int tunnel = !!(item_flags & MLX5_FLOW_LAYER_TUNNEL); 2443 const uint64_t l3m = tunnel ? MLX5_FLOW_LAYER_INNER_L3 : 2444 MLX5_FLOW_LAYER_OUTER_L3; 2445 const uint64_t l4m = tunnel ? MLX5_FLOW_LAYER_INNER_L4 : 2446 MLX5_FLOW_LAYER_OUTER_L4; 2447 int ret; 2448 uint8_t next_proto = 0xFF; 2449 const uint64_t l2_vlan = (MLX5_FLOW_LAYER_L2 | 2450 MLX5_FLOW_LAYER_OUTER_VLAN | 2451 MLX5_FLOW_LAYER_INNER_VLAN); 2452 2453 if ((last_item & l2_vlan) && ether_type && 2454 ether_type != RTE_ETHER_TYPE_IPV4) 2455 return rte_flow_error_set(error, EINVAL, 2456 RTE_FLOW_ERROR_TYPE_ITEM, item, 2457 "IPv4 cannot follow L2/VLAN layer " 2458 "which ether type is not IPv4"); 2459 if (item_flags & MLX5_FLOW_LAYER_TUNNEL) { 2460 if (mask && spec) 2461 next_proto = mask->hdr.next_proto_id & 2462 spec->hdr.next_proto_id; 2463 if (next_proto == IPPROTO_IPIP || next_proto == IPPROTO_IPV6) 2464 return rte_flow_error_set(error, EINVAL, 2465 RTE_FLOW_ERROR_TYPE_ITEM, 2466 item, 2467 "multiple tunnel " 2468 "not supported"); 2469 } 2470 if (item_flags & MLX5_FLOW_LAYER_IPV6_ENCAP) 2471 return rte_flow_error_set(error, EINVAL, 2472 RTE_FLOW_ERROR_TYPE_ITEM, item, 2473 "wrong tunnel type - IPv6 specified " 2474 "but IPv4 item provided"); 2475 if (item_flags & l3m) 2476 return rte_flow_error_set(error, ENOTSUP, 2477 RTE_FLOW_ERROR_TYPE_ITEM, item, 2478 "multiple L3 layers not supported"); 2479 else if (item_flags & l4m) 2480 return rte_flow_error_set(error, EINVAL, 2481 RTE_FLOW_ERROR_TYPE_ITEM, item, 2482 "L3 cannot follow an L4 layer."); 2483 else if ((item_flags & MLX5_FLOW_LAYER_NVGRE) && 2484 !(item_flags & MLX5_FLOW_LAYER_INNER_L2)) 2485 return rte_flow_error_set(error, EINVAL, 2486 RTE_FLOW_ERROR_TYPE_ITEM, item, 2487 "L3 cannot follow an NVGRE layer."); 2488 if (!mask) 2489 mask = &rte_flow_item_ipv4_mask; 2490 else if (mask->hdr.next_proto_id != 0 && 2491 mask->hdr.next_proto_id != 0xff) 2492 return rte_flow_error_set(error, EINVAL, 2493 RTE_FLOW_ERROR_TYPE_ITEM_MASK, mask, 2494 "partial mask is not supported" 2495 " for protocol"); 2496 ret = mlx5_flow_item_acceptable(item, (const uint8_t *)mask, 2497 acc_mask ? (const uint8_t *)acc_mask 2498 : (const uint8_t *)&nic_mask, 2499 sizeof(struct rte_flow_item_ipv4), 2500 range_accepted, error); 2501 if (ret < 0) 2502 return ret; 2503 return 0; 2504 } 2505 2506 /** 2507 * Validate IPV6 item. 2508 * 2509 * @param[in] item 2510 * Item specification. 2511 * @param[in] item_flags 2512 * Bit-fields that holds the items detected until now. 2513 * @param[in] last_item 2514 * Previous validated item in the pattern items. 2515 * @param[in] ether_type 2516 * Type in the ethernet layer header (including dot1q). 2517 * @param[in] acc_mask 2518 * Acceptable mask, if NULL default internal default mask 2519 * will be used to check whether item fields are supported. 2520 * @param[out] error 2521 * Pointer to error structure. 2522 * 2523 * @return 2524 * 0 on success, a negative errno value otherwise and rte_errno is set. 2525 */ 2526 int 2527 mlx5_flow_validate_item_ipv6(const struct rte_flow_item *item, 2528 uint64_t item_flags, 2529 uint64_t last_item, 2530 uint16_t ether_type, 2531 const struct rte_flow_item_ipv6 *acc_mask, 2532 struct rte_flow_error *error) 2533 { 2534 const struct rte_flow_item_ipv6 *mask = item->mask; 2535 const struct rte_flow_item_ipv6 *spec = item->spec; 2536 const struct rte_flow_item_ipv6 nic_mask = { 2537 .hdr = { 2538 .src_addr = 2539 "\xff\xff\xff\xff\xff\xff\xff\xff" 2540 "\xff\xff\xff\xff\xff\xff\xff\xff", 2541 .dst_addr = 2542 "\xff\xff\xff\xff\xff\xff\xff\xff" 2543 "\xff\xff\xff\xff\xff\xff\xff\xff", 2544 .vtc_flow = RTE_BE32(0xffffffff), 2545 .proto = 0xff, 2546 }, 2547 }; 2548 const int tunnel = !!(item_flags & MLX5_FLOW_LAYER_TUNNEL); 2549 const uint64_t l3m = tunnel ? MLX5_FLOW_LAYER_INNER_L3 : 2550 MLX5_FLOW_LAYER_OUTER_L3; 2551 const uint64_t l4m = tunnel ? MLX5_FLOW_LAYER_INNER_L4 : 2552 MLX5_FLOW_LAYER_OUTER_L4; 2553 int ret; 2554 uint8_t next_proto = 0xFF; 2555 const uint64_t l2_vlan = (MLX5_FLOW_LAYER_L2 | 2556 MLX5_FLOW_LAYER_OUTER_VLAN | 2557 MLX5_FLOW_LAYER_INNER_VLAN); 2558 2559 if ((last_item & l2_vlan) && ether_type && 2560 ether_type != RTE_ETHER_TYPE_IPV6) 2561 return rte_flow_error_set(error, EINVAL, 2562 RTE_FLOW_ERROR_TYPE_ITEM, item, 2563 "IPv6 cannot follow L2/VLAN layer " 2564 "which ether type is not IPv6"); 2565 if (mask && mask->hdr.proto == UINT8_MAX && spec) 2566 next_proto = spec->hdr.proto; 2567 if (item_flags & MLX5_FLOW_LAYER_TUNNEL) { 2568 if (next_proto == IPPROTO_IPIP || next_proto == IPPROTO_IPV6) 2569 return rte_flow_error_set(error, EINVAL, 2570 RTE_FLOW_ERROR_TYPE_ITEM, 2571 item, 2572 "multiple tunnel " 2573 "not supported"); 2574 } 2575 if (next_proto == IPPROTO_HOPOPTS || 2576 next_proto == IPPROTO_ROUTING || 2577 next_proto == IPPROTO_FRAGMENT || 2578 next_proto == IPPROTO_ESP || 2579 next_proto == IPPROTO_AH || 2580 next_proto == IPPROTO_DSTOPTS) 2581 return rte_flow_error_set(error, EINVAL, 2582 RTE_FLOW_ERROR_TYPE_ITEM, item, 2583 "IPv6 proto (next header) should " 2584 "not be set as extension header"); 2585 if (item_flags & MLX5_FLOW_LAYER_IPIP) 2586 return rte_flow_error_set(error, EINVAL, 2587 RTE_FLOW_ERROR_TYPE_ITEM, item, 2588 "wrong tunnel type - IPv4 specified " 2589 "but IPv6 item provided"); 2590 if (item_flags & l3m) 2591 return rte_flow_error_set(error, ENOTSUP, 2592 RTE_FLOW_ERROR_TYPE_ITEM, item, 2593 "multiple L3 layers not supported"); 2594 else if (item_flags & l4m) 2595 return rte_flow_error_set(error, EINVAL, 2596 RTE_FLOW_ERROR_TYPE_ITEM, item, 2597 "L3 cannot follow an L4 layer."); 2598 else if ((item_flags & MLX5_FLOW_LAYER_NVGRE) && 2599 !(item_flags & MLX5_FLOW_LAYER_INNER_L2)) 2600 return rte_flow_error_set(error, EINVAL, 2601 RTE_FLOW_ERROR_TYPE_ITEM, item, 2602 "L3 cannot follow an NVGRE layer."); 2603 if (!mask) 2604 mask = &rte_flow_item_ipv6_mask; 2605 ret = mlx5_flow_item_acceptable(item, (const uint8_t *)mask, 2606 acc_mask ? (const uint8_t *)acc_mask 2607 : (const uint8_t *)&nic_mask, 2608 sizeof(struct rte_flow_item_ipv6), 2609 MLX5_ITEM_RANGE_NOT_ACCEPTED, error); 2610 if (ret < 0) 2611 return ret; 2612 return 0; 2613 } 2614 2615 /** 2616 * Validate UDP item. 2617 * 2618 * @param[in] item 2619 * Item specification. 2620 * @param[in] item_flags 2621 * Bit-fields that holds the items detected until now. 2622 * @param[in] target_protocol 2623 * The next protocol in the previous item. 2624 * @param[in] flow_mask 2625 * mlx5 flow-specific (DV, verbs, etc.) supported header fields mask. 2626 * @param[out] error 2627 * Pointer to error structure. 2628 * 2629 * @return 2630 * 0 on success, a negative errno value otherwise and rte_errno is set. 2631 */ 2632 int 2633 mlx5_flow_validate_item_udp(const struct rte_flow_item *item, 2634 uint64_t item_flags, 2635 uint8_t target_protocol, 2636 struct rte_flow_error *error) 2637 { 2638 const struct rte_flow_item_udp *mask = item->mask; 2639 const int tunnel = !!(item_flags & MLX5_FLOW_LAYER_TUNNEL); 2640 const uint64_t l3m = tunnel ? MLX5_FLOW_LAYER_INNER_L3 : 2641 MLX5_FLOW_LAYER_OUTER_L3; 2642 const uint64_t l4m = tunnel ? MLX5_FLOW_LAYER_INNER_L4 : 2643 MLX5_FLOW_LAYER_OUTER_L4; 2644 int ret; 2645 2646 if (target_protocol != 0xff && target_protocol != IPPROTO_UDP) 2647 return rte_flow_error_set(error, EINVAL, 2648 RTE_FLOW_ERROR_TYPE_ITEM, item, 2649 "protocol filtering not compatible" 2650 " with UDP layer"); 2651 if (!(item_flags & l3m)) 2652 return rte_flow_error_set(error, EINVAL, 2653 RTE_FLOW_ERROR_TYPE_ITEM, item, 2654 "L3 is mandatory to filter on L4"); 2655 if (item_flags & l4m) 2656 return rte_flow_error_set(error, EINVAL, 2657 RTE_FLOW_ERROR_TYPE_ITEM, item, 2658 "multiple L4 layers not supported"); 2659 if (!mask) 2660 mask = &rte_flow_item_udp_mask; 2661 ret = mlx5_flow_item_acceptable 2662 (item, (const uint8_t *)mask, 2663 (const uint8_t *)&rte_flow_item_udp_mask, 2664 sizeof(struct rte_flow_item_udp), MLX5_ITEM_RANGE_NOT_ACCEPTED, 2665 error); 2666 if (ret < 0) 2667 return ret; 2668 return 0; 2669 } 2670 2671 /** 2672 * Validate TCP item. 2673 * 2674 * @param[in] item 2675 * Item specification. 2676 * @param[in] item_flags 2677 * Bit-fields that holds the items detected until now. 2678 * @param[in] target_protocol 2679 * The next protocol in the previous item. 2680 * @param[out] error 2681 * Pointer to error structure. 2682 * 2683 * @return 2684 * 0 on success, a negative errno value otherwise and rte_errno is set. 2685 */ 2686 int 2687 mlx5_flow_validate_item_tcp(const struct rte_flow_item *item, 2688 uint64_t item_flags, 2689 uint8_t target_protocol, 2690 const struct rte_flow_item_tcp *flow_mask, 2691 struct rte_flow_error *error) 2692 { 2693 const struct rte_flow_item_tcp *mask = item->mask; 2694 const int tunnel = !!(item_flags & MLX5_FLOW_LAYER_TUNNEL); 2695 const uint64_t l3m = tunnel ? MLX5_FLOW_LAYER_INNER_L3 : 2696 MLX5_FLOW_LAYER_OUTER_L3; 2697 const uint64_t l4m = tunnel ? MLX5_FLOW_LAYER_INNER_L4 : 2698 MLX5_FLOW_LAYER_OUTER_L4; 2699 int ret; 2700 2701 MLX5_ASSERT(flow_mask); 2702 if (target_protocol != 0xff && target_protocol != IPPROTO_TCP) 2703 return rte_flow_error_set(error, EINVAL, 2704 RTE_FLOW_ERROR_TYPE_ITEM, item, 2705 "protocol filtering not compatible" 2706 " with TCP layer"); 2707 if (!(item_flags & l3m)) 2708 return rte_flow_error_set(error, EINVAL, 2709 RTE_FLOW_ERROR_TYPE_ITEM, item, 2710 "L3 is mandatory to filter on L4"); 2711 if (item_flags & l4m) 2712 return rte_flow_error_set(error, EINVAL, 2713 RTE_FLOW_ERROR_TYPE_ITEM, item, 2714 "multiple L4 layers not supported"); 2715 if (!mask) 2716 mask = &rte_flow_item_tcp_mask; 2717 ret = mlx5_flow_item_acceptable 2718 (item, (const uint8_t *)mask, 2719 (const uint8_t *)flow_mask, 2720 sizeof(struct rte_flow_item_tcp), MLX5_ITEM_RANGE_NOT_ACCEPTED, 2721 error); 2722 if (ret < 0) 2723 return ret; 2724 return 0; 2725 } 2726 2727 /** 2728 * Validate VXLAN item. 2729 * 2730 * @param[in] dev 2731 * Pointer to the Ethernet device structure. 2732 * @param[in] udp_dport 2733 * UDP destination port 2734 * @param[in] item 2735 * Item specification. 2736 * @param[in] item_flags 2737 * Bit-fields that holds the items detected until now. 2738 * @param[in] attr 2739 * Flow rule attributes. 2740 * @param[out] error 2741 * Pointer to error structure. 2742 * 2743 * @return 2744 * 0 on success, a negative errno value otherwise and rte_errno is set. 2745 */ 2746 int 2747 mlx5_flow_validate_item_vxlan(struct rte_eth_dev *dev, 2748 uint16_t udp_dport, 2749 const struct rte_flow_item *item, 2750 uint64_t item_flags, 2751 const struct rte_flow_attr *attr, 2752 struct rte_flow_error *error) 2753 { 2754 const struct rte_flow_item_vxlan *spec = item->spec; 2755 const struct rte_flow_item_vxlan *mask = item->mask; 2756 int ret; 2757 struct mlx5_priv *priv = dev->data->dev_private; 2758 union vni { 2759 uint32_t vlan_id; 2760 uint8_t vni[4]; 2761 } id = { .vlan_id = 0, }; 2762 const struct rte_flow_item_vxlan nic_mask = { 2763 .vni = "\xff\xff\xff", 2764 .rsvd1 = 0xff, 2765 }; 2766 const struct rte_flow_item_vxlan *valid_mask; 2767 2768 if (item_flags & MLX5_FLOW_LAYER_TUNNEL) 2769 return rte_flow_error_set(error, ENOTSUP, 2770 RTE_FLOW_ERROR_TYPE_ITEM, item, 2771 "multiple tunnel layers not" 2772 " supported"); 2773 valid_mask = &rte_flow_item_vxlan_mask; 2774 /* 2775 * Verify only UDPv4 is present as defined in 2776 * https://tools.ietf.org/html/rfc7348 2777 */ 2778 if (!(item_flags & MLX5_FLOW_LAYER_OUTER_L4_UDP)) 2779 return rte_flow_error_set(error, EINVAL, 2780 RTE_FLOW_ERROR_TYPE_ITEM, item, 2781 "no outer UDP layer found"); 2782 if (!mask) 2783 mask = &rte_flow_item_vxlan_mask; 2784 2785 if (priv->sh->steering_format_version != 2786 MLX5_STEERING_LOGIC_FORMAT_CONNECTX_5 || 2787 !udp_dport || udp_dport == MLX5_UDP_PORT_VXLAN) { 2788 /* FDB domain & NIC domain non-zero group */ 2789 if ((attr->transfer || attr->group) && priv->sh->misc5_cap) 2790 valid_mask = &nic_mask; 2791 /* Group zero in NIC domain */ 2792 if (!attr->group && !attr->transfer && 2793 priv->sh->tunnel_header_0_1) 2794 valid_mask = &nic_mask; 2795 } 2796 ret = mlx5_flow_item_acceptable 2797 (item, (const uint8_t *)mask, 2798 (const uint8_t *)valid_mask, 2799 sizeof(struct rte_flow_item_vxlan), 2800 MLX5_ITEM_RANGE_NOT_ACCEPTED, error); 2801 if (ret < 0) 2802 return ret; 2803 if (spec) { 2804 memcpy(&id.vni[1], spec->vni, 3); 2805 memcpy(&id.vni[1], mask->vni, 3); 2806 } 2807 if (!(item_flags & MLX5_FLOW_LAYER_OUTER)) 2808 return rte_flow_error_set(error, ENOTSUP, 2809 RTE_FLOW_ERROR_TYPE_ITEM, item, 2810 "VXLAN tunnel must be fully defined"); 2811 return 0; 2812 } 2813 2814 /** 2815 * Validate VXLAN_GPE item. 2816 * 2817 * @param[in] item 2818 * Item specification. 2819 * @param[in] item_flags 2820 * Bit-fields that holds the items detected until now. 2821 * @param[in] priv 2822 * Pointer to the private data structure. 2823 * @param[in] target_protocol 2824 * The next protocol in the previous item. 2825 * @param[out] error 2826 * Pointer to error structure. 2827 * 2828 * @return 2829 * 0 on success, a negative errno value otherwise and rte_errno is set. 2830 */ 2831 int 2832 mlx5_flow_validate_item_vxlan_gpe(const struct rte_flow_item *item, 2833 uint64_t item_flags, 2834 struct rte_eth_dev *dev, 2835 struct rte_flow_error *error) 2836 { 2837 struct mlx5_priv *priv = dev->data->dev_private; 2838 const struct rte_flow_item_vxlan_gpe *spec = item->spec; 2839 const struct rte_flow_item_vxlan_gpe *mask = item->mask; 2840 int ret; 2841 union vni { 2842 uint32_t vlan_id; 2843 uint8_t vni[4]; 2844 } id = { .vlan_id = 0, }; 2845 2846 if (!priv->sh->config.l3_vxlan_en) 2847 return rte_flow_error_set(error, ENOTSUP, 2848 RTE_FLOW_ERROR_TYPE_ITEM, item, 2849 "L3 VXLAN is not enabled by device" 2850 " parameter and/or not configured in" 2851 " firmware"); 2852 if (item_flags & MLX5_FLOW_LAYER_TUNNEL) 2853 return rte_flow_error_set(error, ENOTSUP, 2854 RTE_FLOW_ERROR_TYPE_ITEM, item, 2855 "multiple tunnel layers not" 2856 " supported"); 2857 /* 2858 * Verify only UDPv4 is present as defined in 2859 * https://tools.ietf.org/html/rfc7348 2860 */ 2861 if (!(item_flags & MLX5_FLOW_LAYER_OUTER_L4_UDP)) 2862 return rte_flow_error_set(error, EINVAL, 2863 RTE_FLOW_ERROR_TYPE_ITEM, item, 2864 "no outer UDP layer found"); 2865 if (!mask) 2866 mask = &rte_flow_item_vxlan_gpe_mask; 2867 ret = mlx5_flow_item_acceptable 2868 (item, (const uint8_t *)mask, 2869 (const uint8_t *)&rte_flow_item_vxlan_gpe_mask, 2870 sizeof(struct rte_flow_item_vxlan_gpe), 2871 MLX5_ITEM_RANGE_NOT_ACCEPTED, error); 2872 if (ret < 0) 2873 return ret; 2874 if (spec) { 2875 if (spec->protocol) 2876 return rte_flow_error_set(error, ENOTSUP, 2877 RTE_FLOW_ERROR_TYPE_ITEM, 2878 item, 2879 "VxLAN-GPE protocol" 2880 " not supported"); 2881 memcpy(&id.vni[1], spec->vni, 3); 2882 memcpy(&id.vni[1], mask->vni, 3); 2883 } 2884 if (!(item_flags & MLX5_FLOW_LAYER_OUTER)) 2885 return rte_flow_error_set(error, ENOTSUP, 2886 RTE_FLOW_ERROR_TYPE_ITEM, item, 2887 "VXLAN-GPE tunnel must be fully" 2888 " defined"); 2889 return 0; 2890 } 2891 /** 2892 * Validate GRE Key item. 2893 * 2894 * @param[in] item 2895 * Item specification. 2896 * @param[in] item_flags 2897 * Bit flags to mark detected items. 2898 * @param[in] gre_item 2899 * Pointer to gre_item 2900 * @param[out] error 2901 * Pointer to error structure. 2902 * 2903 * @return 2904 * 0 on success, a negative errno value otherwise and rte_errno is set. 2905 */ 2906 int 2907 mlx5_flow_validate_item_gre_key(const struct rte_flow_item *item, 2908 uint64_t item_flags, 2909 const struct rte_flow_item *gre_item, 2910 struct rte_flow_error *error) 2911 { 2912 const rte_be32_t *mask = item->mask; 2913 int ret = 0; 2914 rte_be32_t gre_key_default_mask = RTE_BE32(UINT32_MAX); 2915 const struct rte_flow_item_gre *gre_spec; 2916 const struct rte_flow_item_gre *gre_mask; 2917 2918 if (item_flags & MLX5_FLOW_LAYER_GRE_KEY) 2919 return rte_flow_error_set(error, ENOTSUP, 2920 RTE_FLOW_ERROR_TYPE_ITEM, item, 2921 "Multiple GRE key not support"); 2922 if (!(item_flags & MLX5_FLOW_LAYER_GRE)) 2923 return rte_flow_error_set(error, ENOTSUP, 2924 RTE_FLOW_ERROR_TYPE_ITEM, item, 2925 "No preceding GRE header"); 2926 if (item_flags & MLX5_FLOW_LAYER_INNER) 2927 return rte_flow_error_set(error, ENOTSUP, 2928 RTE_FLOW_ERROR_TYPE_ITEM, item, 2929 "GRE key following a wrong item"); 2930 gre_mask = gre_item->mask; 2931 if (!gre_mask) 2932 gre_mask = &rte_flow_item_gre_mask; 2933 gre_spec = gre_item->spec; 2934 if (gre_spec && (gre_mask->c_rsvd0_ver & RTE_BE16(0x2000)) && 2935 !(gre_spec->c_rsvd0_ver & RTE_BE16(0x2000))) 2936 return rte_flow_error_set(error, EINVAL, 2937 RTE_FLOW_ERROR_TYPE_ITEM, item, 2938 "Key bit must be on"); 2939 2940 if (!mask) 2941 mask = &gre_key_default_mask; 2942 ret = mlx5_flow_item_acceptable 2943 (item, (const uint8_t *)mask, 2944 (const uint8_t *)&gre_key_default_mask, 2945 sizeof(rte_be32_t), MLX5_ITEM_RANGE_NOT_ACCEPTED, error); 2946 return ret; 2947 } 2948 2949 /** 2950 * Validate GRE optional item. 2951 * 2952 * @param[in] dev 2953 * Pointer to the Ethernet device structure. 2954 * @param[in] item 2955 * Item specification. 2956 * @param[in] item_flags 2957 * Bit flags to mark detected items. 2958 * @param[in] attr 2959 * Flow rule attributes. 2960 * @param[in] gre_item 2961 * Pointer to gre_item 2962 * @param[out] error 2963 * Pointer to error structure. 2964 * 2965 * @return 2966 * 0 on success, a negative errno value otherwise and rte_errno is set. 2967 */ 2968 int 2969 mlx5_flow_validate_item_gre_option(struct rte_eth_dev *dev, 2970 const struct rte_flow_item *item, 2971 uint64_t item_flags, 2972 const struct rte_flow_attr *attr, 2973 const struct rte_flow_item *gre_item, 2974 struct rte_flow_error *error) 2975 { 2976 const struct rte_flow_item_gre *gre_spec = gre_item->spec; 2977 const struct rte_flow_item_gre *gre_mask = gre_item->mask; 2978 const struct rte_flow_item_gre_opt *spec = item->spec; 2979 const struct rte_flow_item_gre_opt *mask = item->mask; 2980 struct mlx5_priv *priv = dev->data->dev_private; 2981 int ret = 0; 2982 struct rte_flow_item_gre_opt nic_mask = { 2983 .checksum_rsvd = { 2984 .checksum = RTE_BE16(UINT16_MAX), 2985 .reserved1 = 0x0, 2986 }, 2987 .key = { 2988 .key = RTE_BE32(UINT32_MAX), 2989 }, 2990 .sequence = { 2991 .sequence = RTE_BE32(UINT32_MAX), 2992 }, 2993 }; 2994 2995 if (!(item_flags & MLX5_FLOW_LAYER_GRE)) 2996 return rte_flow_error_set(error, ENOTSUP, 2997 RTE_FLOW_ERROR_TYPE_ITEM, item, 2998 "No preceding GRE header"); 2999 if (item_flags & MLX5_FLOW_LAYER_INNER) 3000 return rte_flow_error_set(error, ENOTSUP, 3001 RTE_FLOW_ERROR_TYPE_ITEM, item, 3002 "GRE option following a wrong item"); 3003 if (!spec || !mask) 3004 return rte_flow_error_set(error, EINVAL, 3005 RTE_FLOW_ERROR_TYPE_ITEM, item, 3006 "At least one field gre_option(checksum/key/sequence) must be specified"); 3007 if (!gre_mask) 3008 gre_mask = &rte_flow_item_gre_mask; 3009 if (mask->checksum_rsvd.checksum) 3010 if (gre_spec && (gre_mask->c_rsvd0_ver & RTE_BE16(0x8000)) && 3011 !(gre_spec->c_rsvd0_ver & RTE_BE16(0x8000))) 3012 return rte_flow_error_set(error, EINVAL, 3013 RTE_FLOW_ERROR_TYPE_ITEM, 3014 item, 3015 "Checksum bit must be on"); 3016 if (mask->key.key) 3017 if (gre_spec && (gre_mask->c_rsvd0_ver & RTE_BE16(0x2000)) && 3018 !(gre_spec->c_rsvd0_ver & RTE_BE16(0x2000))) 3019 return rte_flow_error_set(error, EINVAL, 3020 RTE_FLOW_ERROR_TYPE_ITEM, 3021 item, "Key bit must be on"); 3022 if (mask->sequence.sequence) 3023 if (gre_spec && (gre_mask->c_rsvd0_ver & RTE_BE16(0x1000)) && 3024 !(gre_spec->c_rsvd0_ver & RTE_BE16(0x1000))) 3025 return rte_flow_error_set(error, EINVAL, 3026 RTE_FLOW_ERROR_TYPE_ITEM, 3027 item, 3028 "Sequence bit must be on"); 3029 if (mask->checksum_rsvd.checksum || mask->sequence.sequence) { 3030 if (priv->sh->steering_format_version == 3031 MLX5_STEERING_LOGIC_FORMAT_CONNECTX_5 || 3032 ((attr->group || attr->transfer) && 3033 !priv->sh->misc5_cap) || 3034 (!(priv->sh->tunnel_header_0_1 && 3035 priv->sh->tunnel_header_2_3) && 3036 !attr->group && !attr->transfer)) 3037 return rte_flow_error_set(error, EINVAL, 3038 RTE_FLOW_ERROR_TYPE_ITEM, 3039 item, 3040 "Checksum/Sequence not supported"); 3041 } 3042 ret = mlx5_flow_item_acceptable 3043 (item, (const uint8_t *)mask, 3044 (const uint8_t *)&nic_mask, 3045 sizeof(struct rte_flow_item_gre_opt), 3046 MLX5_ITEM_RANGE_NOT_ACCEPTED, error); 3047 return ret; 3048 } 3049 3050 /** 3051 * Validate GRE item. 3052 * 3053 * @param[in] item 3054 * Item specification. 3055 * @param[in] item_flags 3056 * Bit flags to mark detected items. 3057 * @param[in] target_protocol 3058 * The next protocol in the previous item. 3059 * @param[out] error 3060 * Pointer to error structure. 3061 * 3062 * @return 3063 * 0 on success, a negative errno value otherwise and rte_errno is set. 3064 */ 3065 int 3066 mlx5_flow_validate_item_gre(const struct rte_flow_item *item, 3067 uint64_t item_flags, 3068 uint8_t target_protocol, 3069 struct rte_flow_error *error) 3070 { 3071 const struct rte_flow_item_gre *spec __rte_unused = item->spec; 3072 const struct rte_flow_item_gre *mask = item->mask; 3073 int ret; 3074 const struct rte_flow_item_gre nic_mask = { 3075 .c_rsvd0_ver = RTE_BE16(0xB000), 3076 .protocol = RTE_BE16(UINT16_MAX), 3077 }; 3078 3079 if (target_protocol != 0xff && target_protocol != IPPROTO_GRE) 3080 return rte_flow_error_set(error, EINVAL, 3081 RTE_FLOW_ERROR_TYPE_ITEM, item, 3082 "protocol filtering not compatible" 3083 " with this GRE layer"); 3084 if (item_flags & MLX5_FLOW_LAYER_TUNNEL) 3085 return rte_flow_error_set(error, ENOTSUP, 3086 RTE_FLOW_ERROR_TYPE_ITEM, item, 3087 "multiple tunnel layers not" 3088 " supported"); 3089 if (!(item_flags & MLX5_FLOW_LAYER_OUTER_L3)) 3090 return rte_flow_error_set(error, ENOTSUP, 3091 RTE_FLOW_ERROR_TYPE_ITEM, item, 3092 "L3 Layer is missing"); 3093 if (!mask) 3094 mask = &rte_flow_item_gre_mask; 3095 ret = mlx5_flow_item_acceptable 3096 (item, (const uint8_t *)mask, 3097 (const uint8_t *)&nic_mask, 3098 sizeof(struct rte_flow_item_gre), MLX5_ITEM_RANGE_NOT_ACCEPTED, 3099 error); 3100 if (ret < 0) 3101 return ret; 3102 #ifndef HAVE_MLX5DV_DR 3103 #ifndef HAVE_IBV_DEVICE_MPLS_SUPPORT 3104 if (spec && (spec->protocol & mask->protocol)) 3105 return rte_flow_error_set(error, ENOTSUP, 3106 RTE_FLOW_ERROR_TYPE_ITEM, item, 3107 "without MPLS support the" 3108 " specification cannot be used for" 3109 " filtering"); 3110 #endif 3111 #endif 3112 return 0; 3113 } 3114 3115 /** 3116 * Validate Geneve item. 3117 * 3118 * @param[in] item 3119 * Item specification. 3120 * @param[in] itemFlags 3121 * Bit-fields that holds the items detected until now. 3122 * @param[in] enPriv 3123 * Pointer to the private data structure. 3124 * @param[out] error 3125 * Pointer to error structure. 3126 * 3127 * @return 3128 * 0 on success, a negative errno value otherwise and rte_errno is set. 3129 */ 3130 3131 int 3132 mlx5_flow_validate_item_geneve(const struct rte_flow_item *item, 3133 uint64_t item_flags, 3134 struct rte_eth_dev *dev, 3135 struct rte_flow_error *error) 3136 { 3137 struct mlx5_priv *priv = dev->data->dev_private; 3138 const struct rte_flow_item_geneve *spec = item->spec; 3139 const struct rte_flow_item_geneve *mask = item->mask; 3140 int ret; 3141 uint16_t gbhdr; 3142 uint8_t opt_len = priv->sh->cdev->config.hca_attr.geneve_max_opt_len ? 3143 MLX5_GENEVE_OPT_LEN_1 : MLX5_GENEVE_OPT_LEN_0; 3144 const struct rte_flow_item_geneve nic_mask = { 3145 .ver_opt_len_o_c_rsvd0 = RTE_BE16(0x3f80), 3146 .vni = "\xff\xff\xff", 3147 .protocol = RTE_BE16(UINT16_MAX), 3148 }; 3149 3150 if (!priv->sh->cdev->config.hca_attr.tunnel_stateless_geneve_rx) 3151 return rte_flow_error_set(error, ENOTSUP, 3152 RTE_FLOW_ERROR_TYPE_ITEM, item, 3153 "L3 Geneve is not enabled by device" 3154 " parameter and/or not configured in" 3155 " firmware"); 3156 if (item_flags & MLX5_FLOW_LAYER_TUNNEL) 3157 return rte_flow_error_set(error, ENOTSUP, 3158 RTE_FLOW_ERROR_TYPE_ITEM, item, 3159 "multiple tunnel layers not" 3160 " supported"); 3161 /* 3162 * Verify only UDPv4 is present as defined in 3163 * https://tools.ietf.org/html/rfc7348 3164 */ 3165 if (!(item_flags & MLX5_FLOW_LAYER_OUTER_L4_UDP)) 3166 return rte_flow_error_set(error, EINVAL, 3167 RTE_FLOW_ERROR_TYPE_ITEM, item, 3168 "no outer UDP layer found"); 3169 if (!mask) 3170 mask = &rte_flow_item_geneve_mask; 3171 ret = mlx5_flow_item_acceptable 3172 (item, (const uint8_t *)mask, 3173 (const uint8_t *)&nic_mask, 3174 sizeof(struct rte_flow_item_geneve), 3175 MLX5_ITEM_RANGE_NOT_ACCEPTED, error); 3176 if (ret) 3177 return ret; 3178 if (spec) { 3179 gbhdr = rte_be_to_cpu_16(spec->ver_opt_len_o_c_rsvd0); 3180 if (MLX5_GENEVE_VER_VAL(gbhdr) || 3181 MLX5_GENEVE_CRITO_VAL(gbhdr) || 3182 MLX5_GENEVE_RSVD_VAL(gbhdr) || spec->rsvd1) 3183 return rte_flow_error_set(error, ENOTSUP, 3184 RTE_FLOW_ERROR_TYPE_ITEM, 3185 item, 3186 "Geneve protocol unsupported" 3187 " fields are being used"); 3188 if (MLX5_GENEVE_OPTLEN_VAL(gbhdr) > opt_len) 3189 return rte_flow_error_set 3190 (error, ENOTSUP, 3191 RTE_FLOW_ERROR_TYPE_ITEM, 3192 item, 3193 "Unsupported Geneve options length"); 3194 } 3195 if (!(item_flags & MLX5_FLOW_LAYER_OUTER)) 3196 return rte_flow_error_set 3197 (error, ENOTSUP, 3198 RTE_FLOW_ERROR_TYPE_ITEM, item, 3199 "Geneve tunnel must be fully defined"); 3200 return 0; 3201 } 3202 3203 /** 3204 * Validate Geneve TLV option item. 3205 * 3206 * @param[in] item 3207 * Item specification. 3208 * @param[in] last_item 3209 * Previous validated item in the pattern items. 3210 * @param[in] geneve_item 3211 * Previous GENEVE item specification. 3212 * @param[in] dev 3213 * Pointer to the rte_eth_dev structure. 3214 * @param[out] error 3215 * Pointer to error structure. 3216 * 3217 * @return 3218 * 0 on success, a negative errno value otherwise and rte_errno is set. 3219 */ 3220 int 3221 mlx5_flow_validate_item_geneve_opt(const struct rte_flow_item *item, 3222 uint64_t last_item, 3223 const struct rte_flow_item *geneve_item, 3224 struct rte_eth_dev *dev, 3225 struct rte_flow_error *error) 3226 { 3227 struct mlx5_priv *priv = dev->data->dev_private; 3228 struct mlx5_dev_ctx_shared *sh = priv->sh; 3229 struct mlx5_geneve_tlv_option_resource *geneve_opt_resource; 3230 struct mlx5_hca_attr *hca_attr = &sh->cdev->config.hca_attr; 3231 uint8_t data_max_supported = 3232 hca_attr->max_geneve_tlv_option_data_len * 4; 3233 const struct rte_flow_item_geneve *geneve_spec; 3234 const struct rte_flow_item_geneve *geneve_mask; 3235 const struct rte_flow_item_geneve_opt *spec = item->spec; 3236 const struct rte_flow_item_geneve_opt *mask = item->mask; 3237 unsigned int i; 3238 unsigned int data_len; 3239 uint8_t tlv_option_len; 3240 uint16_t optlen_m, optlen_v; 3241 const struct rte_flow_item_geneve_opt full_mask = { 3242 .option_class = RTE_BE16(0xffff), 3243 .option_type = 0xff, 3244 .option_len = 0x1f, 3245 }; 3246 3247 if (!mask) 3248 mask = &rte_flow_item_geneve_opt_mask; 3249 if (!spec) 3250 return rte_flow_error_set 3251 (error, ENOTSUP, RTE_FLOW_ERROR_TYPE_ITEM, item, 3252 "Geneve TLV opt class/type/length must be specified"); 3253 if ((uint32_t)spec->option_len > MLX5_GENEVE_OPTLEN_MASK) 3254 return rte_flow_error_set 3255 (error, ENOTSUP, RTE_FLOW_ERROR_TYPE_ITEM, item, 3256 "Geneve TLV opt length exceeds the limit (31)"); 3257 /* Check if class type and length masks are full. */ 3258 if (full_mask.option_class != mask->option_class || 3259 full_mask.option_type != mask->option_type || 3260 full_mask.option_len != (mask->option_len & full_mask.option_len)) 3261 return rte_flow_error_set 3262 (error, ENOTSUP, RTE_FLOW_ERROR_TYPE_ITEM, item, 3263 "Geneve TLV opt class/type/length masks must be full"); 3264 /* Check if length is supported */ 3265 if ((uint32_t)spec->option_len > 3266 hca_attr->max_geneve_tlv_option_data_len) 3267 return rte_flow_error_set 3268 (error, ENOTSUP, RTE_FLOW_ERROR_TYPE_ITEM, item, 3269 "Geneve TLV opt length not supported"); 3270 if (hca_attr->max_geneve_tlv_options > 1) 3271 DRV_LOG(DEBUG, 3272 "max_geneve_tlv_options supports more than 1 option"); 3273 /* Check GENEVE item preceding. */ 3274 if (!geneve_item || !(last_item & MLX5_FLOW_LAYER_GENEVE)) 3275 return rte_flow_error_set 3276 (error, ENOTSUP, RTE_FLOW_ERROR_TYPE_ITEM, item, 3277 "Geneve opt item must be preceded with Geneve item"); 3278 geneve_spec = geneve_item->spec; 3279 geneve_mask = geneve_item->mask ? geneve_item->mask : 3280 &rte_flow_item_geneve_mask; 3281 /* Check if GENEVE TLV option size doesn't exceed option length */ 3282 if (geneve_spec && (geneve_mask->ver_opt_len_o_c_rsvd0 || 3283 geneve_spec->ver_opt_len_o_c_rsvd0)) { 3284 tlv_option_len = spec->option_len & mask->option_len; 3285 optlen_v = rte_be_to_cpu_16(geneve_spec->ver_opt_len_o_c_rsvd0); 3286 optlen_v = MLX5_GENEVE_OPTLEN_VAL(optlen_v); 3287 optlen_m = rte_be_to_cpu_16(geneve_mask->ver_opt_len_o_c_rsvd0); 3288 optlen_m = MLX5_GENEVE_OPTLEN_VAL(optlen_m); 3289 if ((optlen_v & optlen_m) <= tlv_option_len) 3290 return rte_flow_error_set 3291 (error, ENOTSUP, RTE_FLOW_ERROR_TYPE_ITEM, item, 3292 "GENEVE TLV option length exceeds optlen"); 3293 } 3294 /* Check if length is 0 or data is 0. */ 3295 if (spec->data == NULL || spec->option_len == 0) 3296 return rte_flow_error_set 3297 (error, ENOTSUP, RTE_FLOW_ERROR_TYPE_ITEM, item, 3298 "Geneve TLV opt with zero data/length not supported"); 3299 /* Check not all data & mask are 0. */ 3300 data_len = spec->option_len * 4; 3301 if (mask->data == NULL) { 3302 for (i = 0; i < data_len; i++) 3303 if (spec->data[i]) 3304 break; 3305 if (i == data_len) 3306 return rte_flow_error_set(error, ENOTSUP, 3307 RTE_FLOW_ERROR_TYPE_ITEM, item, 3308 "Can't match on Geneve option data 0"); 3309 } else { 3310 for (i = 0; i < data_len; i++) 3311 if (spec->data[i] & mask->data[i]) 3312 break; 3313 if (i == data_len) 3314 return rte_flow_error_set(error, ENOTSUP, 3315 RTE_FLOW_ERROR_TYPE_ITEM, item, 3316 "Can't match on Geneve option data and mask 0"); 3317 /* Check data mask supported. */ 3318 for (i = data_max_supported; i < data_len ; i++) 3319 if (mask->data[i]) 3320 return rte_flow_error_set(error, ENOTSUP, 3321 RTE_FLOW_ERROR_TYPE_ITEM, item, 3322 "Data mask is of unsupported size"); 3323 } 3324 /* Check GENEVE option is supported in NIC. */ 3325 if (!hca_attr->geneve_tlv_opt) 3326 return rte_flow_error_set 3327 (error, ENOTSUP, RTE_FLOW_ERROR_TYPE_ITEM, item, 3328 "Geneve TLV opt not supported"); 3329 /* Check if we already have geneve option with different type/class. */ 3330 rte_spinlock_lock(&sh->geneve_tlv_opt_sl); 3331 geneve_opt_resource = sh->geneve_tlv_option_resource; 3332 if (geneve_opt_resource != NULL) 3333 if (geneve_opt_resource->option_class != spec->option_class || 3334 geneve_opt_resource->option_type != spec->option_type || 3335 geneve_opt_resource->length != spec->option_len) { 3336 rte_spinlock_unlock(&sh->geneve_tlv_opt_sl); 3337 return rte_flow_error_set(error, ENOTSUP, 3338 RTE_FLOW_ERROR_TYPE_ITEM, item, 3339 "Only one Geneve TLV option supported"); 3340 } 3341 rte_spinlock_unlock(&sh->geneve_tlv_opt_sl); 3342 return 0; 3343 } 3344 3345 /** 3346 * Validate MPLS item. 3347 * 3348 * @param[in] dev 3349 * Pointer to the rte_eth_dev structure. 3350 * @param[in] item 3351 * Item specification. 3352 * @param[in] item_flags 3353 * Bit-fields that holds the items detected until now. 3354 * @param[in] prev_layer 3355 * The protocol layer indicated in previous item. 3356 * @param[out] error 3357 * Pointer to error structure. 3358 * 3359 * @return 3360 * 0 on success, a negative errno value otherwise and rte_errno is set. 3361 */ 3362 int 3363 mlx5_flow_validate_item_mpls(struct rte_eth_dev *dev __rte_unused, 3364 const struct rte_flow_item *item __rte_unused, 3365 uint64_t item_flags __rte_unused, 3366 uint64_t prev_layer __rte_unused, 3367 struct rte_flow_error *error) 3368 { 3369 #ifdef HAVE_IBV_DEVICE_MPLS_SUPPORT 3370 const struct rte_flow_item_mpls *mask = item->mask; 3371 struct mlx5_priv *priv = dev->data->dev_private; 3372 int ret; 3373 3374 if (!priv->sh->dev_cap.mpls_en) 3375 return rte_flow_error_set(error, ENOTSUP, 3376 RTE_FLOW_ERROR_TYPE_ITEM, item, 3377 "MPLS not supported or" 3378 " disabled in firmware" 3379 " configuration."); 3380 /* MPLS over UDP, GRE is allowed */ 3381 if (!(prev_layer & (MLX5_FLOW_LAYER_OUTER_L4_UDP | 3382 MLX5_FLOW_LAYER_GRE | 3383 MLX5_FLOW_LAYER_GRE_KEY))) 3384 return rte_flow_error_set(error, EINVAL, 3385 RTE_FLOW_ERROR_TYPE_ITEM, item, 3386 "protocol filtering not compatible" 3387 " with MPLS layer"); 3388 /* Multi-tunnel isn't allowed but MPLS over GRE is an exception. */ 3389 if ((item_flags & MLX5_FLOW_LAYER_TUNNEL) && 3390 !(item_flags & MLX5_FLOW_LAYER_GRE)) 3391 return rte_flow_error_set(error, ENOTSUP, 3392 RTE_FLOW_ERROR_TYPE_ITEM, item, 3393 "multiple tunnel layers not" 3394 " supported"); 3395 if (!mask) 3396 mask = &rte_flow_item_mpls_mask; 3397 ret = mlx5_flow_item_acceptable 3398 (item, (const uint8_t *)mask, 3399 (const uint8_t *)&rte_flow_item_mpls_mask, 3400 sizeof(struct rte_flow_item_mpls), 3401 MLX5_ITEM_RANGE_NOT_ACCEPTED, error); 3402 if (ret < 0) 3403 return ret; 3404 return 0; 3405 #else 3406 return rte_flow_error_set(error, ENOTSUP, 3407 RTE_FLOW_ERROR_TYPE_ITEM, item, 3408 "MPLS is not supported by Verbs, please" 3409 " update."); 3410 #endif 3411 } 3412 3413 /** 3414 * Validate NVGRE item. 3415 * 3416 * @param[in] item 3417 * Item specification. 3418 * @param[in] item_flags 3419 * Bit flags to mark detected items. 3420 * @param[in] target_protocol 3421 * The next protocol in the previous item. 3422 * @param[out] error 3423 * Pointer to error structure. 3424 * 3425 * @return 3426 * 0 on success, a negative errno value otherwise and rte_errno is set. 3427 */ 3428 int 3429 mlx5_flow_validate_item_nvgre(const struct rte_flow_item *item, 3430 uint64_t item_flags, 3431 uint8_t target_protocol, 3432 struct rte_flow_error *error) 3433 { 3434 const struct rte_flow_item_nvgre *mask = item->mask; 3435 int ret; 3436 3437 if (target_protocol != 0xff && target_protocol != IPPROTO_GRE) 3438 return rte_flow_error_set(error, EINVAL, 3439 RTE_FLOW_ERROR_TYPE_ITEM, item, 3440 "protocol filtering not compatible" 3441 " with this GRE layer"); 3442 if (item_flags & MLX5_FLOW_LAYER_TUNNEL) 3443 return rte_flow_error_set(error, ENOTSUP, 3444 RTE_FLOW_ERROR_TYPE_ITEM, item, 3445 "multiple tunnel layers not" 3446 " supported"); 3447 if (!(item_flags & MLX5_FLOW_LAYER_OUTER_L3)) 3448 return rte_flow_error_set(error, ENOTSUP, 3449 RTE_FLOW_ERROR_TYPE_ITEM, item, 3450 "L3 Layer is missing"); 3451 if (!mask) 3452 mask = &rte_flow_item_nvgre_mask; 3453 ret = mlx5_flow_item_acceptable 3454 (item, (const uint8_t *)mask, 3455 (const uint8_t *)&rte_flow_item_nvgre_mask, 3456 sizeof(struct rte_flow_item_nvgre), 3457 MLX5_ITEM_RANGE_NOT_ACCEPTED, error); 3458 if (ret < 0) 3459 return ret; 3460 return 0; 3461 } 3462 3463 /** 3464 * Validate eCPRI item. 3465 * 3466 * @param[in] item 3467 * Item specification. 3468 * @param[in] item_flags 3469 * Bit-fields that holds the items detected until now. 3470 * @param[in] last_item 3471 * Previous validated item in the pattern items. 3472 * @param[in] ether_type 3473 * Type in the ethernet layer header (including dot1q). 3474 * @param[in] acc_mask 3475 * Acceptable mask, if NULL default internal default mask 3476 * will be used to check whether item fields are supported. 3477 * @param[out] error 3478 * Pointer to error structure. 3479 * 3480 * @return 3481 * 0 on success, a negative errno value otherwise and rte_errno is set. 3482 */ 3483 int 3484 mlx5_flow_validate_item_ecpri(const struct rte_flow_item *item, 3485 uint64_t item_flags, 3486 uint64_t last_item, 3487 uint16_t ether_type, 3488 const struct rte_flow_item_ecpri *acc_mask, 3489 struct rte_flow_error *error) 3490 { 3491 const struct rte_flow_item_ecpri *mask = item->mask; 3492 const struct rte_flow_item_ecpri nic_mask = { 3493 .hdr = { 3494 .common = { 3495 .u32 = 3496 RTE_BE32(((const struct rte_ecpri_common_hdr) { 3497 .type = 0xFF, 3498 }).u32), 3499 }, 3500 .dummy[0] = 0xFFFFFFFF, 3501 }, 3502 }; 3503 const uint64_t outer_l2_vlan = (MLX5_FLOW_LAYER_OUTER_L2 | 3504 MLX5_FLOW_LAYER_OUTER_VLAN); 3505 struct rte_flow_item_ecpri mask_lo; 3506 3507 if (!(last_item & outer_l2_vlan) && 3508 last_item != MLX5_FLOW_LAYER_OUTER_L4_UDP) 3509 return rte_flow_error_set(error, EINVAL, 3510 RTE_FLOW_ERROR_TYPE_ITEM, item, 3511 "eCPRI can only follow L2/VLAN layer or UDP layer"); 3512 if ((last_item & outer_l2_vlan) && ether_type && 3513 ether_type != RTE_ETHER_TYPE_ECPRI) 3514 return rte_flow_error_set(error, EINVAL, 3515 RTE_FLOW_ERROR_TYPE_ITEM, item, 3516 "eCPRI cannot follow L2/VLAN layer which ether type is not 0xAEFE"); 3517 if (item_flags & MLX5_FLOW_LAYER_TUNNEL) 3518 return rte_flow_error_set(error, EINVAL, 3519 RTE_FLOW_ERROR_TYPE_ITEM, item, 3520 "eCPRI with tunnel is not supported right now"); 3521 if (item_flags & MLX5_FLOW_LAYER_OUTER_L3) 3522 return rte_flow_error_set(error, ENOTSUP, 3523 RTE_FLOW_ERROR_TYPE_ITEM, item, 3524 "multiple L3 layers not supported"); 3525 else if (item_flags & MLX5_FLOW_LAYER_OUTER_L4_TCP) 3526 return rte_flow_error_set(error, EINVAL, 3527 RTE_FLOW_ERROR_TYPE_ITEM, item, 3528 "eCPRI cannot coexist with a TCP layer"); 3529 /* In specification, eCPRI could be over UDP layer. */ 3530 else if (item_flags & MLX5_FLOW_LAYER_OUTER_L4_UDP) 3531 return rte_flow_error_set(error, EINVAL, 3532 RTE_FLOW_ERROR_TYPE_ITEM, item, 3533 "eCPRI over UDP layer is not yet supported right now"); 3534 /* Mask for type field in common header could be zero. */ 3535 if (!mask) 3536 mask = &rte_flow_item_ecpri_mask; 3537 mask_lo.hdr.common.u32 = rte_be_to_cpu_32(mask->hdr.common.u32); 3538 /* Input mask is in big-endian format. */ 3539 if (mask_lo.hdr.common.type != 0 && mask_lo.hdr.common.type != 0xff) 3540 return rte_flow_error_set(error, EINVAL, 3541 RTE_FLOW_ERROR_TYPE_ITEM_MASK, mask, 3542 "partial mask is not supported for protocol"); 3543 else if (mask_lo.hdr.common.type == 0 && mask->hdr.dummy[0] != 0) 3544 return rte_flow_error_set(error, EINVAL, 3545 RTE_FLOW_ERROR_TYPE_ITEM_MASK, mask, 3546 "message header mask must be after a type mask"); 3547 return mlx5_flow_item_acceptable(item, (const uint8_t *)mask, 3548 acc_mask ? (const uint8_t *)acc_mask 3549 : (const uint8_t *)&nic_mask, 3550 sizeof(struct rte_flow_item_ecpri), 3551 MLX5_ITEM_RANGE_NOT_ACCEPTED, error); 3552 } 3553 3554 static int 3555 flow_null_validate(struct rte_eth_dev *dev __rte_unused, 3556 const struct rte_flow_attr *attr __rte_unused, 3557 const struct rte_flow_item items[] __rte_unused, 3558 const struct rte_flow_action actions[] __rte_unused, 3559 bool external __rte_unused, 3560 int hairpin __rte_unused, 3561 struct rte_flow_error *error) 3562 { 3563 return rte_flow_error_set(error, ENOTSUP, 3564 RTE_FLOW_ERROR_TYPE_UNSPECIFIED, NULL, NULL); 3565 } 3566 3567 static struct mlx5_flow * 3568 flow_null_prepare(struct rte_eth_dev *dev __rte_unused, 3569 const struct rte_flow_attr *attr __rte_unused, 3570 const struct rte_flow_item items[] __rte_unused, 3571 const struct rte_flow_action actions[] __rte_unused, 3572 struct rte_flow_error *error) 3573 { 3574 rte_flow_error_set(error, ENOTSUP, 3575 RTE_FLOW_ERROR_TYPE_UNSPECIFIED, NULL, NULL); 3576 return NULL; 3577 } 3578 3579 static int 3580 flow_null_translate(struct rte_eth_dev *dev __rte_unused, 3581 struct mlx5_flow *dev_flow __rte_unused, 3582 const struct rte_flow_attr *attr __rte_unused, 3583 const struct rte_flow_item items[] __rte_unused, 3584 const struct rte_flow_action actions[] __rte_unused, 3585 struct rte_flow_error *error) 3586 { 3587 return rte_flow_error_set(error, ENOTSUP, 3588 RTE_FLOW_ERROR_TYPE_UNSPECIFIED, NULL, NULL); 3589 } 3590 3591 static int 3592 flow_null_apply(struct rte_eth_dev *dev __rte_unused, 3593 struct rte_flow *flow __rte_unused, 3594 struct rte_flow_error *error) 3595 { 3596 return rte_flow_error_set(error, ENOTSUP, 3597 RTE_FLOW_ERROR_TYPE_UNSPECIFIED, NULL, NULL); 3598 } 3599 3600 static void 3601 flow_null_remove(struct rte_eth_dev *dev __rte_unused, 3602 struct rte_flow *flow __rte_unused) 3603 { 3604 } 3605 3606 static void 3607 flow_null_destroy(struct rte_eth_dev *dev __rte_unused, 3608 struct rte_flow *flow __rte_unused) 3609 { 3610 } 3611 3612 static int 3613 flow_null_query(struct rte_eth_dev *dev __rte_unused, 3614 struct rte_flow *flow __rte_unused, 3615 const struct rte_flow_action *actions __rte_unused, 3616 void *data __rte_unused, 3617 struct rte_flow_error *error) 3618 { 3619 return rte_flow_error_set(error, ENOTSUP, 3620 RTE_FLOW_ERROR_TYPE_UNSPECIFIED, NULL, NULL); 3621 } 3622 3623 static int 3624 flow_null_sync_domain(struct rte_eth_dev *dev __rte_unused, 3625 uint32_t domains __rte_unused, 3626 uint32_t flags __rte_unused) 3627 { 3628 return 0; 3629 } 3630 3631 /* Void driver to protect from null pointer reference. */ 3632 const struct mlx5_flow_driver_ops mlx5_flow_null_drv_ops = { 3633 .validate = flow_null_validate, 3634 .prepare = flow_null_prepare, 3635 .translate = flow_null_translate, 3636 .apply = flow_null_apply, 3637 .remove = flow_null_remove, 3638 .destroy = flow_null_destroy, 3639 .query = flow_null_query, 3640 .sync_domain = flow_null_sync_domain, 3641 }; 3642 3643 /** 3644 * Select flow driver type according to flow attributes and device 3645 * configuration. 3646 * 3647 * @param[in] dev 3648 * Pointer to the dev structure. 3649 * @param[in] attr 3650 * Pointer to the flow attributes. 3651 * 3652 * @return 3653 * flow driver type, MLX5_FLOW_TYPE_MAX otherwise. 3654 */ 3655 static enum mlx5_flow_drv_type 3656 flow_get_drv_type(struct rte_eth_dev *dev, const struct rte_flow_attr *attr) 3657 { 3658 struct mlx5_priv *priv = dev->data->dev_private; 3659 /* The OS can determine first a specific flow type (DV, VERBS) */ 3660 enum mlx5_flow_drv_type type = mlx5_flow_os_get_type(); 3661 3662 if (type != MLX5_FLOW_TYPE_MAX) 3663 return type; 3664 /* 3665 * Currently when dv_flow_en == 2, only HW steering engine is 3666 * supported. New engines can also be chosen here if ready. 3667 */ 3668 if (priv->sh->config.dv_flow_en == 2) 3669 return MLX5_FLOW_TYPE_HW; 3670 /* If no OS specific type - continue with DV/VERBS selection */ 3671 if (attr->transfer && priv->sh->config.dv_esw_en) 3672 type = MLX5_FLOW_TYPE_DV; 3673 if (!attr->transfer) 3674 type = priv->sh->config.dv_flow_en ? MLX5_FLOW_TYPE_DV : 3675 MLX5_FLOW_TYPE_VERBS; 3676 return type; 3677 } 3678 3679 #define flow_get_drv_ops(type) flow_drv_ops[type] 3680 3681 /** 3682 * Flow driver validation API. This abstracts calling driver specific functions. 3683 * The type of flow driver is determined according to flow attributes. 3684 * 3685 * @param[in] dev 3686 * Pointer to the dev structure. 3687 * @param[in] attr 3688 * Pointer to the flow attributes. 3689 * @param[in] items 3690 * Pointer to the list of items. 3691 * @param[in] actions 3692 * Pointer to the list of actions. 3693 * @param[in] external 3694 * This flow rule is created by request external to PMD. 3695 * @param[in] hairpin 3696 * Number of hairpin TX actions, 0 means classic flow. 3697 * @param[out] error 3698 * Pointer to the error structure. 3699 * 3700 * @return 3701 * 0 on success, a negative errno value otherwise and rte_errno is set. 3702 */ 3703 static inline int 3704 flow_drv_validate(struct rte_eth_dev *dev, 3705 const struct rte_flow_attr *attr, 3706 const struct rte_flow_item items[], 3707 const struct rte_flow_action actions[], 3708 bool external, int hairpin, struct rte_flow_error *error) 3709 { 3710 const struct mlx5_flow_driver_ops *fops; 3711 enum mlx5_flow_drv_type type = flow_get_drv_type(dev, attr); 3712 3713 fops = flow_get_drv_ops(type); 3714 return fops->validate(dev, attr, items, actions, external, 3715 hairpin, error); 3716 } 3717 3718 /** 3719 * Flow driver preparation API. This abstracts calling driver specific 3720 * functions. Parent flow (rte_flow) should have driver type (drv_type). It 3721 * calculates the size of memory required for device flow, allocates the memory, 3722 * initializes the device flow and returns the pointer. 3723 * 3724 * @note 3725 * This function initializes device flow structure such as dv or verbs in 3726 * struct mlx5_flow. However, it is caller's responsibility to initialize the 3727 * rest. For example, adding returning device flow to flow->dev_flow list and 3728 * setting backward reference to the flow should be done out of this function. 3729 * layers field is not filled either. 3730 * 3731 * @param[in] dev 3732 * Pointer to the dev structure. 3733 * @param[in] attr 3734 * Pointer to the flow attributes. 3735 * @param[in] items 3736 * Pointer to the list of items. 3737 * @param[in] actions 3738 * Pointer to the list of actions. 3739 * @param[in] flow_idx 3740 * This memory pool index to the flow. 3741 * @param[out] error 3742 * Pointer to the error structure. 3743 * 3744 * @return 3745 * Pointer to device flow on success, otherwise NULL and rte_errno is set. 3746 */ 3747 static inline struct mlx5_flow * 3748 flow_drv_prepare(struct rte_eth_dev *dev, 3749 const struct rte_flow *flow, 3750 const struct rte_flow_attr *attr, 3751 const struct rte_flow_item items[], 3752 const struct rte_flow_action actions[], 3753 uint32_t flow_idx, 3754 struct rte_flow_error *error) 3755 { 3756 const struct mlx5_flow_driver_ops *fops; 3757 enum mlx5_flow_drv_type type = flow->drv_type; 3758 struct mlx5_flow *mlx5_flow = NULL; 3759 3760 MLX5_ASSERT(type > MLX5_FLOW_TYPE_MIN && type < MLX5_FLOW_TYPE_MAX); 3761 fops = flow_get_drv_ops(type); 3762 mlx5_flow = fops->prepare(dev, attr, items, actions, error); 3763 if (mlx5_flow) 3764 mlx5_flow->flow_idx = flow_idx; 3765 return mlx5_flow; 3766 } 3767 3768 /** 3769 * Flow driver translation API. This abstracts calling driver specific 3770 * functions. Parent flow (rte_flow) should have driver type (drv_type). It 3771 * translates a generic flow into a driver flow. flow_drv_prepare() must 3772 * precede. 3773 * 3774 * @note 3775 * dev_flow->layers could be filled as a result of parsing during translation 3776 * if needed by flow_drv_apply(). dev_flow->flow->actions can also be filled 3777 * if necessary. As a flow can have multiple dev_flows by RSS flow expansion, 3778 * flow->actions could be overwritten even though all the expanded dev_flows 3779 * have the same actions. 3780 * 3781 * @param[in] dev 3782 * Pointer to the rte dev structure. 3783 * @param[in, out] dev_flow 3784 * Pointer to the mlx5 flow. 3785 * @param[in] attr 3786 * Pointer to the flow attributes. 3787 * @param[in] items 3788 * Pointer to the list of items. 3789 * @param[in] actions 3790 * Pointer to the list of actions. 3791 * @param[out] error 3792 * Pointer to the error structure. 3793 * 3794 * @return 3795 * 0 on success, a negative errno value otherwise and rte_errno is set. 3796 */ 3797 static inline int 3798 flow_drv_translate(struct rte_eth_dev *dev, struct mlx5_flow *dev_flow, 3799 const struct rte_flow_attr *attr, 3800 const struct rte_flow_item items[], 3801 const struct rte_flow_action actions[], 3802 struct rte_flow_error *error) 3803 { 3804 const struct mlx5_flow_driver_ops *fops; 3805 enum mlx5_flow_drv_type type = dev_flow->flow->drv_type; 3806 3807 MLX5_ASSERT(type > MLX5_FLOW_TYPE_MIN && type < MLX5_FLOW_TYPE_MAX); 3808 fops = flow_get_drv_ops(type); 3809 return fops->translate(dev, dev_flow, attr, items, actions, error); 3810 } 3811 3812 /** 3813 * Flow driver apply API. This abstracts calling driver specific functions. 3814 * Parent flow (rte_flow) should have driver type (drv_type). It applies 3815 * translated driver flows on to device. flow_drv_translate() must precede. 3816 * 3817 * @param[in] dev 3818 * Pointer to Ethernet device structure. 3819 * @param[in, out] flow 3820 * Pointer to flow structure. 3821 * @param[out] error 3822 * Pointer to error structure. 3823 * 3824 * @return 3825 * 0 on success, a negative errno value otherwise and rte_errno is set. 3826 */ 3827 static inline int 3828 flow_drv_apply(struct rte_eth_dev *dev, struct rte_flow *flow, 3829 struct rte_flow_error *error) 3830 { 3831 const struct mlx5_flow_driver_ops *fops; 3832 enum mlx5_flow_drv_type type = flow->drv_type; 3833 3834 MLX5_ASSERT(type > MLX5_FLOW_TYPE_MIN && type < MLX5_FLOW_TYPE_MAX); 3835 fops = flow_get_drv_ops(type); 3836 return fops->apply(dev, flow, error); 3837 } 3838 3839 /** 3840 * Flow driver destroy API. This abstracts calling driver specific functions. 3841 * Parent flow (rte_flow) should have driver type (drv_type). It removes a flow 3842 * on device and releases resources of the flow. 3843 * 3844 * @param[in] dev 3845 * Pointer to Ethernet device. 3846 * @param[in, out] flow 3847 * Pointer to flow structure. 3848 */ 3849 static inline void 3850 flow_drv_destroy(struct rte_eth_dev *dev, struct rte_flow *flow) 3851 { 3852 const struct mlx5_flow_driver_ops *fops; 3853 enum mlx5_flow_drv_type type = flow->drv_type; 3854 3855 MLX5_ASSERT(type > MLX5_FLOW_TYPE_MIN && type < MLX5_FLOW_TYPE_MAX); 3856 fops = flow_get_drv_ops(type); 3857 fops->destroy(dev, flow); 3858 } 3859 3860 /** 3861 * Flow driver find RSS policy tbl API. This abstracts calling driver 3862 * specific functions. Parent flow (rte_flow) should have driver 3863 * type (drv_type). It will find the RSS policy table that has the rss_desc. 3864 * 3865 * @param[in] dev 3866 * Pointer to Ethernet device. 3867 * @param[in, out] flow 3868 * Pointer to flow structure. 3869 * @param[in] policy 3870 * Pointer to meter policy table. 3871 * @param[in] rss_desc 3872 * Pointer to rss_desc 3873 */ 3874 static struct mlx5_flow_meter_sub_policy * 3875 flow_drv_meter_sub_policy_rss_prepare(struct rte_eth_dev *dev, 3876 struct rte_flow *flow, 3877 struct mlx5_flow_meter_policy *policy, 3878 struct mlx5_flow_rss_desc *rss_desc[MLX5_MTR_RTE_COLORS]) 3879 { 3880 const struct mlx5_flow_driver_ops *fops; 3881 enum mlx5_flow_drv_type type = flow->drv_type; 3882 3883 MLX5_ASSERT(type > MLX5_FLOW_TYPE_MIN && type < MLX5_FLOW_TYPE_MAX); 3884 fops = flow_get_drv_ops(type); 3885 return fops->meter_sub_policy_rss_prepare(dev, policy, rss_desc); 3886 } 3887 3888 /** 3889 * Flow driver color tag rule API. This abstracts calling driver 3890 * specific functions. Parent flow (rte_flow) should have driver 3891 * type (drv_type). It will create the color tag rules in hierarchy meter. 3892 * 3893 * @param[in] dev 3894 * Pointer to Ethernet device. 3895 * @param[in, out] flow 3896 * Pointer to flow structure. 3897 * @param[in] fm 3898 * Pointer to flow meter structure. 3899 * @param[in] src_port 3900 * The src port this extra rule should use. 3901 * @param[in] item 3902 * The src port id match item. 3903 * @param[out] error 3904 * Pointer to error structure. 3905 */ 3906 static int 3907 flow_drv_mtr_hierarchy_rule_create(struct rte_eth_dev *dev, 3908 struct rte_flow *flow, 3909 struct mlx5_flow_meter_info *fm, 3910 int32_t src_port, 3911 const struct rte_flow_item *item, 3912 struct rte_flow_error *error) 3913 { 3914 const struct mlx5_flow_driver_ops *fops; 3915 enum mlx5_flow_drv_type type = flow->drv_type; 3916 3917 MLX5_ASSERT(type > MLX5_FLOW_TYPE_MIN && type < MLX5_FLOW_TYPE_MAX); 3918 fops = flow_get_drv_ops(type); 3919 return fops->meter_hierarchy_rule_create(dev, fm, 3920 src_port, item, error); 3921 } 3922 3923 /** 3924 * Get RSS action from the action list. 3925 * 3926 * @param[in] dev 3927 * Pointer to Ethernet device. 3928 * @param[in] actions 3929 * Pointer to the list of actions. 3930 * @param[in] flow 3931 * Parent flow structure pointer. 3932 * 3933 * @return 3934 * Pointer to the RSS action if exist, else return NULL. 3935 */ 3936 static const struct rte_flow_action_rss* 3937 flow_get_rss_action(struct rte_eth_dev *dev, 3938 const struct rte_flow_action actions[]) 3939 { 3940 struct mlx5_priv *priv = dev->data->dev_private; 3941 const struct rte_flow_action_rss *rss = NULL; 3942 struct mlx5_meter_policy_action_container *acg; 3943 struct mlx5_meter_policy_action_container *acy; 3944 3945 for (; actions->type != RTE_FLOW_ACTION_TYPE_END; actions++) { 3946 switch (actions->type) { 3947 case RTE_FLOW_ACTION_TYPE_RSS: 3948 rss = actions->conf; 3949 break; 3950 case RTE_FLOW_ACTION_TYPE_SAMPLE: 3951 { 3952 const struct rte_flow_action_sample *sample = 3953 actions->conf; 3954 const struct rte_flow_action *act = sample->actions; 3955 for (; act->type != RTE_FLOW_ACTION_TYPE_END; act++) 3956 if (act->type == RTE_FLOW_ACTION_TYPE_RSS) 3957 rss = act->conf; 3958 break; 3959 } 3960 case RTE_FLOW_ACTION_TYPE_METER: 3961 { 3962 uint32_t mtr_idx; 3963 struct mlx5_flow_meter_info *fm; 3964 struct mlx5_flow_meter_policy *policy; 3965 const struct rte_flow_action_meter *mtr = actions->conf; 3966 3967 fm = mlx5_flow_meter_find(priv, mtr->mtr_id, &mtr_idx); 3968 if (fm && !fm->def_policy) { 3969 policy = mlx5_flow_meter_policy_find(dev, 3970 fm->policy_id, NULL); 3971 MLX5_ASSERT(policy); 3972 if (policy->is_hierarchy) { 3973 policy = 3974 mlx5_flow_meter_hierarchy_get_final_policy(dev, 3975 policy); 3976 if (!policy) 3977 return NULL; 3978 } 3979 if (policy->is_rss) { 3980 acg = 3981 &policy->act_cnt[RTE_COLOR_GREEN]; 3982 acy = 3983 &policy->act_cnt[RTE_COLOR_YELLOW]; 3984 if (acg->fate_action == 3985 MLX5_FLOW_FATE_SHARED_RSS) 3986 rss = acg->rss->conf; 3987 else if (acy->fate_action == 3988 MLX5_FLOW_FATE_SHARED_RSS) 3989 rss = acy->rss->conf; 3990 } 3991 } 3992 break; 3993 } 3994 default: 3995 break; 3996 } 3997 } 3998 return rss; 3999 } 4000 4001 /** 4002 * Get ASO age action by index. 4003 * 4004 * @param[in] dev 4005 * Pointer to the Ethernet device structure. 4006 * @param[in] age_idx 4007 * Index to the ASO age action. 4008 * 4009 * @return 4010 * The specified ASO age action. 4011 */ 4012 struct mlx5_aso_age_action* 4013 flow_aso_age_get_by_idx(struct rte_eth_dev *dev, uint32_t age_idx) 4014 { 4015 uint16_t pool_idx = age_idx & UINT16_MAX; 4016 uint16_t offset = (age_idx >> 16) & UINT16_MAX; 4017 struct mlx5_priv *priv = dev->data->dev_private; 4018 struct mlx5_aso_age_mng *mng = priv->sh->aso_age_mng; 4019 struct mlx5_aso_age_pool *pool; 4020 4021 rte_rwlock_read_lock(&mng->resize_rwl); 4022 pool = mng->pools[pool_idx]; 4023 rte_rwlock_read_unlock(&mng->resize_rwl); 4024 return &pool->actions[offset - 1]; 4025 } 4026 4027 /* maps indirect action to translated direct in some actions array */ 4028 struct mlx5_translated_action_handle { 4029 struct rte_flow_action_handle *action; /**< Indirect action handle. */ 4030 int index; /**< Index in related array of rte_flow_action. */ 4031 }; 4032 4033 /** 4034 * Translates actions of type RTE_FLOW_ACTION_TYPE_INDIRECT to related 4035 * direct action if translation possible. 4036 * This functionality used to run same execution path for both direct and 4037 * indirect actions on flow create. All necessary preparations for indirect 4038 * action handling should be performed on *handle* actions list returned 4039 * from this call. 4040 * 4041 * @param[in] dev 4042 * Pointer to Ethernet device. 4043 * @param[in] actions 4044 * List of actions to translate. 4045 * @param[out] handle 4046 * List to store translated indirect action object handles. 4047 * @param[in, out] indir_n 4048 * Size of *handle* array. On return should be updated with number of 4049 * indirect actions retrieved from the *actions* list. 4050 * @param[out] translated_actions 4051 * List of actions where all indirect actions were translated to direct 4052 * if possible. NULL if no translation took place. 4053 * @param[out] error 4054 * Pointer to the error structure. 4055 * 4056 * @return 4057 * 0 on success, a negative errno value otherwise and rte_errno is set. 4058 */ 4059 static int 4060 flow_action_handles_translate(struct rte_eth_dev *dev, 4061 const struct rte_flow_action actions[], 4062 struct mlx5_translated_action_handle *handle, 4063 int *indir_n, 4064 struct rte_flow_action **translated_actions, 4065 struct rte_flow_error *error) 4066 { 4067 struct mlx5_priv *priv = dev->data->dev_private; 4068 struct rte_flow_action *translated = NULL; 4069 size_t actions_size; 4070 int n; 4071 int copied_n = 0; 4072 struct mlx5_translated_action_handle *handle_end = NULL; 4073 4074 for (n = 0; actions[n].type != RTE_FLOW_ACTION_TYPE_END; n++) { 4075 if (actions[n].type != RTE_FLOW_ACTION_TYPE_INDIRECT) 4076 continue; 4077 if (copied_n == *indir_n) { 4078 return rte_flow_error_set 4079 (error, EINVAL, RTE_FLOW_ERROR_TYPE_ACTION_NUM, 4080 NULL, "too many shared actions"); 4081 } 4082 rte_memcpy(&handle[copied_n].action, &actions[n].conf, 4083 sizeof(actions[n].conf)); 4084 handle[copied_n].index = n; 4085 copied_n++; 4086 } 4087 n++; 4088 *indir_n = copied_n; 4089 if (!copied_n) 4090 return 0; 4091 actions_size = sizeof(struct rte_flow_action) * n; 4092 translated = mlx5_malloc(MLX5_MEM_ZERO, actions_size, 0, SOCKET_ID_ANY); 4093 if (!translated) { 4094 rte_errno = ENOMEM; 4095 return -ENOMEM; 4096 } 4097 memcpy(translated, actions, actions_size); 4098 for (handle_end = handle + copied_n; handle < handle_end; handle++) { 4099 struct mlx5_shared_action_rss *shared_rss; 4100 uint32_t act_idx = (uint32_t)(uintptr_t)handle->action; 4101 uint32_t type = act_idx >> MLX5_INDIRECT_ACTION_TYPE_OFFSET; 4102 uint32_t idx = act_idx & 4103 ((1u << MLX5_INDIRECT_ACTION_TYPE_OFFSET) - 1); 4104 4105 switch (type) { 4106 case MLX5_INDIRECT_ACTION_TYPE_RSS: 4107 shared_rss = mlx5_ipool_get 4108 (priv->sh->ipool[MLX5_IPOOL_RSS_SHARED_ACTIONS], idx); 4109 translated[handle->index].type = 4110 RTE_FLOW_ACTION_TYPE_RSS; 4111 translated[handle->index].conf = 4112 &shared_rss->origin; 4113 break; 4114 case MLX5_INDIRECT_ACTION_TYPE_COUNT: 4115 translated[handle->index].type = 4116 (enum rte_flow_action_type) 4117 MLX5_RTE_FLOW_ACTION_TYPE_COUNT; 4118 translated[handle->index].conf = (void *)(uintptr_t)idx; 4119 break; 4120 case MLX5_INDIRECT_ACTION_TYPE_AGE: 4121 if (priv->sh->flow_hit_aso_en) { 4122 translated[handle->index].type = 4123 (enum rte_flow_action_type) 4124 MLX5_RTE_FLOW_ACTION_TYPE_AGE; 4125 translated[handle->index].conf = 4126 (void *)(uintptr_t)idx; 4127 break; 4128 } 4129 /* Fall-through */ 4130 case MLX5_INDIRECT_ACTION_TYPE_CT: 4131 if (priv->sh->ct_aso_en) { 4132 translated[handle->index].type = 4133 RTE_FLOW_ACTION_TYPE_CONNTRACK; 4134 translated[handle->index].conf = 4135 (void *)(uintptr_t)idx; 4136 break; 4137 } 4138 /* Fall-through */ 4139 default: 4140 mlx5_free(translated); 4141 return rte_flow_error_set 4142 (error, EINVAL, RTE_FLOW_ERROR_TYPE_ACTION, 4143 NULL, "invalid indirect action type"); 4144 } 4145 } 4146 *translated_actions = translated; 4147 return 0; 4148 } 4149 4150 /** 4151 * Get Shared RSS action from the action list. 4152 * 4153 * @param[in] dev 4154 * Pointer to Ethernet device. 4155 * @param[in] shared 4156 * Pointer to the list of actions. 4157 * @param[in] shared_n 4158 * Actions list length. 4159 * 4160 * @return 4161 * The MLX5 RSS action ID if exists, otherwise return 0. 4162 */ 4163 static uint32_t 4164 flow_get_shared_rss_action(struct rte_eth_dev *dev, 4165 struct mlx5_translated_action_handle *handle, 4166 int shared_n) 4167 { 4168 struct mlx5_translated_action_handle *handle_end; 4169 struct mlx5_priv *priv = dev->data->dev_private; 4170 struct mlx5_shared_action_rss *shared_rss; 4171 4172 4173 for (handle_end = handle + shared_n; handle < handle_end; handle++) { 4174 uint32_t act_idx = (uint32_t)(uintptr_t)handle->action; 4175 uint32_t type = act_idx >> MLX5_INDIRECT_ACTION_TYPE_OFFSET; 4176 uint32_t idx = act_idx & 4177 ((1u << MLX5_INDIRECT_ACTION_TYPE_OFFSET) - 1); 4178 switch (type) { 4179 case MLX5_INDIRECT_ACTION_TYPE_RSS: 4180 shared_rss = mlx5_ipool_get 4181 (priv->sh->ipool[MLX5_IPOOL_RSS_SHARED_ACTIONS], 4182 idx); 4183 __atomic_add_fetch(&shared_rss->refcnt, 1, 4184 __ATOMIC_RELAXED); 4185 return idx; 4186 default: 4187 break; 4188 } 4189 } 4190 return 0; 4191 } 4192 4193 static unsigned int 4194 find_graph_root(uint32_t rss_level) 4195 { 4196 return rss_level < 2 ? MLX5_EXPANSION_ROOT : 4197 MLX5_EXPANSION_ROOT_OUTER; 4198 } 4199 4200 /** 4201 * Get layer flags from the prefix flow. 4202 * 4203 * Some flows may be split to several subflows, the prefix subflow gets the 4204 * match items and the suffix sub flow gets the actions. 4205 * Some actions need the user defined match item flags to get the detail for 4206 * the action. 4207 * This function helps the suffix flow to get the item layer flags from prefix 4208 * subflow. 4209 * 4210 * @param[in] dev_flow 4211 * Pointer the created prefix subflow. 4212 * 4213 * @return 4214 * The layers get from prefix subflow. 4215 */ 4216 static inline uint64_t 4217 flow_get_prefix_layer_flags(struct mlx5_flow *dev_flow) 4218 { 4219 uint64_t layers = 0; 4220 4221 /* 4222 * Layers bits could be localization, but usually the compiler will 4223 * help to do the optimization work for source code. 4224 * If no decap actions, use the layers directly. 4225 */ 4226 if (!(dev_flow->act_flags & MLX5_FLOW_ACTION_DECAP)) 4227 return dev_flow->handle->layers; 4228 /* Convert L3 layers with decap action. */ 4229 if (dev_flow->handle->layers & MLX5_FLOW_LAYER_INNER_L3_IPV4) 4230 layers |= MLX5_FLOW_LAYER_OUTER_L3_IPV4; 4231 else if (dev_flow->handle->layers & MLX5_FLOW_LAYER_INNER_L3_IPV6) 4232 layers |= MLX5_FLOW_LAYER_OUTER_L3_IPV6; 4233 /* Convert L4 layers with decap action. */ 4234 if (dev_flow->handle->layers & MLX5_FLOW_LAYER_INNER_L4_TCP) 4235 layers |= MLX5_FLOW_LAYER_OUTER_L4_TCP; 4236 else if (dev_flow->handle->layers & MLX5_FLOW_LAYER_INNER_L4_UDP) 4237 layers |= MLX5_FLOW_LAYER_OUTER_L4_UDP; 4238 return layers; 4239 } 4240 4241 /** 4242 * Get metadata split action information. 4243 * 4244 * @param[in] actions 4245 * Pointer to the list of actions. 4246 * @param[out] qrss 4247 * Pointer to the return pointer. 4248 * @param[out] qrss_type 4249 * Pointer to the action type to return. RTE_FLOW_ACTION_TYPE_END is returned 4250 * if no QUEUE/RSS is found. 4251 * @param[out] encap_idx 4252 * Pointer to the index of the encap action if exists, otherwise the last 4253 * action index. 4254 * 4255 * @return 4256 * Total number of actions. 4257 */ 4258 static int 4259 flow_parse_metadata_split_actions_info(const struct rte_flow_action actions[], 4260 const struct rte_flow_action **qrss, 4261 int *encap_idx) 4262 { 4263 const struct rte_flow_action_raw_encap *raw_encap; 4264 int actions_n = 0; 4265 int raw_decap_idx = -1; 4266 4267 *encap_idx = -1; 4268 for (; actions->type != RTE_FLOW_ACTION_TYPE_END; actions++) { 4269 switch (actions->type) { 4270 case RTE_FLOW_ACTION_TYPE_VXLAN_ENCAP: 4271 case RTE_FLOW_ACTION_TYPE_NVGRE_ENCAP: 4272 *encap_idx = actions_n; 4273 break; 4274 case RTE_FLOW_ACTION_TYPE_RAW_DECAP: 4275 raw_decap_idx = actions_n; 4276 break; 4277 case RTE_FLOW_ACTION_TYPE_RAW_ENCAP: 4278 raw_encap = actions->conf; 4279 if (raw_encap->size > MLX5_ENCAPSULATION_DECISION_SIZE) 4280 *encap_idx = raw_decap_idx != -1 ? 4281 raw_decap_idx : actions_n; 4282 break; 4283 case RTE_FLOW_ACTION_TYPE_QUEUE: 4284 case RTE_FLOW_ACTION_TYPE_RSS: 4285 *qrss = actions; 4286 break; 4287 default: 4288 break; 4289 } 4290 actions_n++; 4291 } 4292 if (*encap_idx == -1) 4293 *encap_idx = actions_n; 4294 /* Count RTE_FLOW_ACTION_TYPE_END. */ 4295 return actions_n + 1; 4296 } 4297 4298 /** 4299 * Check if the action will change packet. 4300 * 4301 * @param dev 4302 * Pointer to Ethernet device. 4303 * @param[in] type 4304 * action type. 4305 * 4306 * @return 4307 * true if action will change packet, false otherwise. 4308 */ 4309 static bool flow_check_modify_action_type(struct rte_eth_dev *dev, 4310 enum rte_flow_action_type type) 4311 { 4312 struct mlx5_priv *priv = dev->data->dev_private; 4313 4314 switch (type) { 4315 case RTE_FLOW_ACTION_TYPE_SET_MAC_SRC: 4316 case RTE_FLOW_ACTION_TYPE_SET_MAC_DST: 4317 case RTE_FLOW_ACTION_TYPE_SET_IPV4_SRC: 4318 case RTE_FLOW_ACTION_TYPE_SET_IPV4_DST: 4319 case RTE_FLOW_ACTION_TYPE_SET_IPV6_SRC: 4320 case RTE_FLOW_ACTION_TYPE_SET_IPV6_DST: 4321 case RTE_FLOW_ACTION_TYPE_SET_TP_SRC: 4322 case RTE_FLOW_ACTION_TYPE_SET_TP_DST: 4323 case RTE_FLOW_ACTION_TYPE_DEC_TTL: 4324 case RTE_FLOW_ACTION_TYPE_SET_TTL: 4325 case RTE_FLOW_ACTION_TYPE_INC_TCP_SEQ: 4326 case RTE_FLOW_ACTION_TYPE_DEC_TCP_SEQ: 4327 case RTE_FLOW_ACTION_TYPE_INC_TCP_ACK: 4328 case RTE_FLOW_ACTION_TYPE_DEC_TCP_ACK: 4329 case RTE_FLOW_ACTION_TYPE_SET_IPV4_DSCP: 4330 case RTE_FLOW_ACTION_TYPE_SET_IPV6_DSCP: 4331 case RTE_FLOW_ACTION_TYPE_SET_META: 4332 case RTE_FLOW_ACTION_TYPE_SET_TAG: 4333 case RTE_FLOW_ACTION_TYPE_OF_POP_VLAN: 4334 case RTE_FLOW_ACTION_TYPE_OF_PUSH_VLAN: 4335 case RTE_FLOW_ACTION_TYPE_OF_SET_VLAN_VID: 4336 case RTE_FLOW_ACTION_TYPE_OF_SET_VLAN_PCP: 4337 case RTE_FLOW_ACTION_TYPE_VXLAN_ENCAP: 4338 case RTE_FLOW_ACTION_TYPE_VXLAN_DECAP: 4339 case RTE_FLOW_ACTION_TYPE_NVGRE_ENCAP: 4340 case RTE_FLOW_ACTION_TYPE_NVGRE_DECAP: 4341 case RTE_FLOW_ACTION_TYPE_RAW_ENCAP: 4342 case RTE_FLOW_ACTION_TYPE_RAW_DECAP: 4343 case RTE_FLOW_ACTION_TYPE_MODIFY_FIELD: 4344 return true; 4345 case RTE_FLOW_ACTION_TYPE_FLAG: 4346 case RTE_FLOW_ACTION_TYPE_MARK: 4347 if (priv->sh->config.dv_xmeta_en != MLX5_XMETA_MODE_LEGACY) 4348 return true; 4349 else 4350 return false; 4351 default: 4352 return false; 4353 } 4354 } 4355 4356 /** 4357 * Check meter action from the action list. 4358 * 4359 * @param dev 4360 * Pointer to Ethernet device. 4361 * @param[in] actions 4362 * Pointer to the list of actions. 4363 * @param[out] has_mtr 4364 * Pointer to the meter exist flag. 4365 * @param[out] has_modify 4366 * Pointer to the flag showing there's packet change action. 4367 * @param[out] meter_id 4368 * Pointer to the meter id. 4369 * 4370 * @return 4371 * Total number of actions. 4372 */ 4373 static int 4374 flow_check_meter_action(struct rte_eth_dev *dev, 4375 const struct rte_flow_action actions[], 4376 bool *has_mtr, bool *has_modify, uint32_t *meter_id) 4377 { 4378 const struct rte_flow_action_meter *mtr = NULL; 4379 int actions_n = 0; 4380 4381 MLX5_ASSERT(has_mtr); 4382 *has_mtr = false; 4383 for (; actions->type != RTE_FLOW_ACTION_TYPE_END; actions++) { 4384 switch (actions->type) { 4385 case RTE_FLOW_ACTION_TYPE_METER: 4386 mtr = actions->conf; 4387 *meter_id = mtr->mtr_id; 4388 *has_mtr = true; 4389 break; 4390 default: 4391 break; 4392 } 4393 if (!*has_mtr) 4394 *has_modify |= flow_check_modify_action_type(dev, 4395 actions->type); 4396 actions_n++; 4397 } 4398 /* Count RTE_FLOW_ACTION_TYPE_END. */ 4399 return actions_n + 1; 4400 } 4401 4402 /** 4403 * Check if the flow should be split due to hairpin. 4404 * The reason for the split is that in current HW we can't 4405 * support encap and push-vlan on Rx, so if a flow contains 4406 * these actions we move it to Tx. 4407 * 4408 * @param dev 4409 * Pointer to Ethernet device. 4410 * @param[in] attr 4411 * Flow rule attributes. 4412 * @param[in] actions 4413 * Associated actions (list terminated by the END action). 4414 * 4415 * @return 4416 * > 0 the number of actions and the flow should be split, 4417 * 0 when no split required. 4418 */ 4419 static int 4420 flow_check_hairpin_split(struct rte_eth_dev *dev, 4421 const struct rte_flow_attr *attr, 4422 const struct rte_flow_action actions[]) 4423 { 4424 int queue_action = 0; 4425 int action_n = 0; 4426 int split = 0; 4427 const struct rte_flow_action_queue *queue; 4428 const struct rte_flow_action_rss *rss; 4429 const struct rte_flow_action_raw_encap *raw_encap; 4430 const struct rte_eth_hairpin_conf *conf; 4431 4432 if (!attr->ingress) 4433 return 0; 4434 for (; actions->type != RTE_FLOW_ACTION_TYPE_END; actions++) { 4435 switch (actions->type) { 4436 case RTE_FLOW_ACTION_TYPE_QUEUE: 4437 queue = actions->conf; 4438 if (queue == NULL) 4439 return 0; 4440 conf = mlx5_rxq_get_hairpin_conf(dev, queue->index); 4441 if (conf == NULL || conf->tx_explicit != 0) 4442 return 0; 4443 queue_action = 1; 4444 action_n++; 4445 break; 4446 case RTE_FLOW_ACTION_TYPE_RSS: 4447 rss = actions->conf; 4448 if (rss == NULL || rss->queue_num == 0) 4449 return 0; 4450 conf = mlx5_rxq_get_hairpin_conf(dev, rss->queue[0]); 4451 if (conf == NULL || conf->tx_explicit != 0) 4452 return 0; 4453 queue_action = 1; 4454 action_n++; 4455 break; 4456 case RTE_FLOW_ACTION_TYPE_VXLAN_ENCAP: 4457 case RTE_FLOW_ACTION_TYPE_NVGRE_ENCAP: 4458 case RTE_FLOW_ACTION_TYPE_OF_PUSH_VLAN: 4459 case RTE_FLOW_ACTION_TYPE_OF_SET_VLAN_VID: 4460 case RTE_FLOW_ACTION_TYPE_OF_SET_VLAN_PCP: 4461 split++; 4462 action_n++; 4463 break; 4464 case RTE_FLOW_ACTION_TYPE_RAW_ENCAP: 4465 raw_encap = actions->conf; 4466 if (raw_encap->size > MLX5_ENCAPSULATION_DECISION_SIZE) 4467 split++; 4468 action_n++; 4469 break; 4470 default: 4471 action_n++; 4472 break; 4473 } 4474 } 4475 if (split && queue_action) 4476 return action_n; 4477 return 0; 4478 } 4479 4480 /* Declare flow create/destroy prototype in advance. */ 4481 static uint32_t 4482 flow_list_create(struct rte_eth_dev *dev, enum mlx5_flow_type type, 4483 const struct rte_flow_attr *attr, 4484 const struct rte_flow_item items[], 4485 const struct rte_flow_action actions[], 4486 bool external, struct rte_flow_error *error); 4487 4488 static void 4489 flow_list_destroy(struct rte_eth_dev *dev, enum mlx5_flow_type type, 4490 uint32_t flow_idx); 4491 4492 int 4493 flow_dv_mreg_match_cb(void *tool_ctx __rte_unused, 4494 struct mlx5_list_entry *entry, void *cb_ctx) 4495 { 4496 struct mlx5_flow_cb_ctx *ctx = cb_ctx; 4497 struct mlx5_flow_mreg_copy_resource *mcp_res = 4498 container_of(entry, typeof(*mcp_res), hlist_ent); 4499 4500 return mcp_res->mark_id != *(uint32_t *)(ctx->data); 4501 } 4502 4503 struct mlx5_list_entry * 4504 flow_dv_mreg_create_cb(void *tool_ctx, void *cb_ctx) 4505 { 4506 struct rte_eth_dev *dev = tool_ctx; 4507 struct mlx5_priv *priv = dev->data->dev_private; 4508 struct mlx5_flow_cb_ctx *ctx = cb_ctx; 4509 struct mlx5_flow_mreg_copy_resource *mcp_res; 4510 struct rte_flow_error *error = ctx->error; 4511 uint32_t idx = 0; 4512 int ret; 4513 uint32_t mark_id = *(uint32_t *)(ctx->data); 4514 struct rte_flow_attr attr = { 4515 .group = MLX5_FLOW_MREG_CP_TABLE_GROUP, 4516 .ingress = 1, 4517 }; 4518 struct mlx5_rte_flow_item_tag tag_spec = { 4519 .data = mark_id, 4520 }; 4521 struct rte_flow_item items[] = { 4522 [1] = { .type = RTE_FLOW_ITEM_TYPE_END, }, 4523 }; 4524 struct rte_flow_action_mark ftag = { 4525 .id = mark_id, 4526 }; 4527 struct mlx5_flow_action_copy_mreg cp_mreg = { 4528 .dst = REG_B, 4529 .src = REG_NON, 4530 }; 4531 struct rte_flow_action_jump jump = { 4532 .group = MLX5_FLOW_MREG_ACT_TABLE_GROUP, 4533 }; 4534 struct rte_flow_action actions[] = { 4535 [3] = { .type = RTE_FLOW_ACTION_TYPE_END, }, 4536 }; 4537 4538 /* Fill the register fields in the flow. */ 4539 ret = mlx5_flow_get_reg_id(dev, MLX5_FLOW_MARK, 0, error); 4540 if (ret < 0) 4541 return NULL; 4542 tag_spec.id = ret; 4543 ret = mlx5_flow_get_reg_id(dev, MLX5_METADATA_RX, 0, error); 4544 if (ret < 0) 4545 return NULL; 4546 cp_mreg.src = ret; 4547 /* Provide the full width of FLAG specific value. */ 4548 if (mark_id == (priv->sh->dv_regc0_mask & MLX5_FLOW_MARK_DEFAULT)) 4549 tag_spec.data = MLX5_FLOW_MARK_DEFAULT; 4550 /* Build a new flow. */ 4551 if (mark_id != MLX5_DEFAULT_COPY_ID) { 4552 items[0] = (struct rte_flow_item){ 4553 .type = (enum rte_flow_item_type) 4554 MLX5_RTE_FLOW_ITEM_TYPE_TAG, 4555 .spec = &tag_spec, 4556 }; 4557 items[1] = (struct rte_flow_item){ 4558 .type = RTE_FLOW_ITEM_TYPE_END, 4559 }; 4560 actions[0] = (struct rte_flow_action){ 4561 .type = (enum rte_flow_action_type) 4562 MLX5_RTE_FLOW_ACTION_TYPE_MARK, 4563 .conf = &ftag, 4564 }; 4565 actions[1] = (struct rte_flow_action){ 4566 .type = (enum rte_flow_action_type) 4567 MLX5_RTE_FLOW_ACTION_TYPE_COPY_MREG, 4568 .conf = &cp_mreg, 4569 }; 4570 actions[2] = (struct rte_flow_action){ 4571 .type = RTE_FLOW_ACTION_TYPE_JUMP, 4572 .conf = &jump, 4573 }; 4574 actions[3] = (struct rte_flow_action){ 4575 .type = RTE_FLOW_ACTION_TYPE_END, 4576 }; 4577 } else { 4578 /* Default rule, wildcard match. */ 4579 attr.priority = MLX5_FLOW_LOWEST_PRIO_INDICATOR; 4580 items[0] = (struct rte_flow_item){ 4581 .type = RTE_FLOW_ITEM_TYPE_END, 4582 }; 4583 actions[0] = (struct rte_flow_action){ 4584 .type = (enum rte_flow_action_type) 4585 MLX5_RTE_FLOW_ACTION_TYPE_COPY_MREG, 4586 .conf = &cp_mreg, 4587 }; 4588 actions[1] = (struct rte_flow_action){ 4589 .type = RTE_FLOW_ACTION_TYPE_JUMP, 4590 .conf = &jump, 4591 }; 4592 actions[2] = (struct rte_flow_action){ 4593 .type = RTE_FLOW_ACTION_TYPE_END, 4594 }; 4595 } 4596 /* Build a new entry. */ 4597 mcp_res = mlx5_ipool_zmalloc(priv->sh->ipool[MLX5_IPOOL_MCP], &idx); 4598 if (!mcp_res) { 4599 rte_errno = ENOMEM; 4600 return NULL; 4601 } 4602 mcp_res->idx = idx; 4603 mcp_res->mark_id = mark_id; 4604 /* 4605 * The copy Flows are not included in any list. There 4606 * ones are referenced from other Flows and can not 4607 * be applied, removed, deleted in arbitrary order 4608 * by list traversing. 4609 */ 4610 mcp_res->rix_flow = flow_list_create(dev, MLX5_FLOW_TYPE_MCP, 4611 &attr, items, actions, false, error); 4612 if (!mcp_res->rix_flow) { 4613 mlx5_ipool_free(priv->sh->ipool[MLX5_IPOOL_MCP], idx); 4614 return NULL; 4615 } 4616 return &mcp_res->hlist_ent; 4617 } 4618 4619 struct mlx5_list_entry * 4620 flow_dv_mreg_clone_cb(void *tool_ctx, struct mlx5_list_entry *oentry, 4621 void *cb_ctx __rte_unused) 4622 { 4623 struct rte_eth_dev *dev = tool_ctx; 4624 struct mlx5_priv *priv = dev->data->dev_private; 4625 struct mlx5_flow_mreg_copy_resource *mcp_res; 4626 uint32_t idx = 0; 4627 4628 mcp_res = mlx5_ipool_malloc(priv->sh->ipool[MLX5_IPOOL_MCP], &idx); 4629 if (!mcp_res) { 4630 rte_errno = ENOMEM; 4631 return NULL; 4632 } 4633 memcpy(mcp_res, oentry, sizeof(*mcp_res)); 4634 mcp_res->idx = idx; 4635 return &mcp_res->hlist_ent; 4636 } 4637 4638 void 4639 flow_dv_mreg_clone_free_cb(void *tool_ctx, struct mlx5_list_entry *entry) 4640 { 4641 struct mlx5_flow_mreg_copy_resource *mcp_res = 4642 container_of(entry, typeof(*mcp_res), hlist_ent); 4643 struct rte_eth_dev *dev = tool_ctx; 4644 struct mlx5_priv *priv = dev->data->dev_private; 4645 4646 mlx5_ipool_free(priv->sh->ipool[MLX5_IPOOL_MCP], mcp_res->idx); 4647 } 4648 4649 /** 4650 * Add a flow of copying flow metadata registers in RX_CP_TBL. 4651 * 4652 * As mark_id is unique, if there's already a registered flow for the mark_id, 4653 * return by increasing the reference counter of the resource. Otherwise, create 4654 * the resource (mcp_res) and flow. 4655 * 4656 * Flow looks like, 4657 * - If ingress port is ANY and reg_c[1] is mark_id, 4658 * flow_tag := mark_id, reg_b := reg_c[0] and jump to RX_ACT_TBL. 4659 * 4660 * For default flow (zero mark_id), flow is like, 4661 * - If ingress port is ANY, 4662 * reg_b := reg_c[0] and jump to RX_ACT_TBL. 4663 * 4664 * @param dev 4665 * Pointer to Ethernet device. 4666 * @param mark_id 4667 * ID of MARK action, zero means default flow for META. 4668 * @param[out] error 4669 * Perform verbose error reporting if not NULL. 4670 * 4671 * @return 4672 * Associated resource on success, NULL otherwise and rte_errno is set. 4673 */ 4674 static struct mlx5_flow_mreg_copy_resource * 4675 flow_mreg_add_copy_action(struct rte_eth_dev *dev, uint32_t mark_id, 4676 struct rte_flow_error *error) 4677 { 4678 struct mlx5_priv *priv = dev->data->dev_private; 4679 struct mlx5_list_entry *entry; 4680 struct mlx5_flow_cb_ctx ctx = { 4681 .dev = dev, 4682 .error = error, 4683 .data = &mark_id, 4684 }; 4685 4686 /* Check if already registered. */ 4687 MLX5_ASSERT(priv->mreg_cp_tbl); 4688 entry = mlx5_hlist_register(priv->mreg_cp_tbl, mark_id, &ctx); 4689 if (!entry) 4690 return NULL; 4691 return container_of(entry, struct mlx5_flow_mreg_copy_resource, 4692 hlist_ent); 4693 } 4694 4695 void 4696 flow_dv_mreg_remove_cb(void *tool_ctx, struct mlx5_list_entry *entry) 4697 { 4698 struct mlx5_flow_mreg_copy_resource *mcp_res = 4699 container_of(entry, typeof(*mcp_res), hlist_ent); 4700 struct rte_eth_dev *dev = tool_ctx; 4701 struct mlx5_priv *priv = dev->data->dev_private; 4702 4703 MLX5_ASSERT(mcp_res->rix_flow); 4704 flow_list_destroy(dev, MLX5_FLOW_TYPE_MCP, mcp_res->rix_flow); 4705 mlx5_ipool_free(priv->sh->ipool[MLX5_IPOOL_MCP], mcp_res->idx); 4706 } 4707 4708 /** 4709 * Release flow in RX_CP_TBL. 4710 * 4711 * @param dev 4712 * Pointer to Ethernet device. 4713 * @flow 4714 * Parent flow for wich copying is provided. 4715 */ 4716 static void 4717 flow_mreg_del_copy_action(struct rte_eth_dev *dev, 4718 struct rte_flow *flow) 4719 { 4720 struct mlx5_flow_mreg_copy_resource *mcp_res; 4721 struct mlx5_priv *priv = dev->data->dev_private; 4722 4723 if (!flow->rix_mreg_copy) 4724 return; 4725 mcp_res = mlx5_ipool_get(priv->sh->ipool[MLX5_IPOOL_MCP], 4726 flow->rix_mreg_copy); 4727 if (!mcp_res || !priv->mreg_cp_tbl) 4728 return; 4729 MLX5_ASSERT(mcp_res->rix_flow); 4730 mlx5_hlist_unregister(priv->mreg_cp_tbl, &mcp_res->hlist_ent); 4731 flow->rix_mreg_copy = 0; 4732 } 4733 4734 /** 4735 * Remove the default copy action from RX_CP_TBL. 4736 * 4737 * This functions is called in the mlx5_dev_start(). No thread safe 4738 * is guaranteed. 4739 * 4740 * @param dev 4741 * Pointer to Ethernet device. 4742 */ 4743 static void 4744 flow_mreg_del_default_copy_action(struct rte_eth_dev *dev) 4745 { 4746 struct mlx5_list_entry *entry; 4747 struct mlx5_priv *priv = dev->data->dev_private; 4748 struct mlx5_flow_cb_ctx ctx; 4749 uint32_t mark_id; 4750 4751 /* Check if default flow is registered. */ 4752 if (!priv->mreg_cp_tbl) 4753 return; 4754 mark_id = MLX5_DEFAULT_COPY_ID; 4755 ctx.data = &mark_id; 4756 entry = mlx5_hlist_lookup(priv->mreg_cp_tbl, mark_id, &ctx); 4757 if (!entry) 4758 return; 4759 mlx5_hlist_unregister(priv->mreg_cp_tbl, entry); 4760 } 4761 4762 /** 4763 * Add the default copy action in in RX_CP_TBL. 4764 * 4765 * This functions is called in the mlx5_dev_start(). No thread safe 4766 * is guaranteed. 4767 * 4768 * @param dev 4769 * Pointer to Ethernet device. 4770 * @param[out] error 4771 * Perform verbose error reporting if not NULL. 4772 * 4773 * @return 4774 * 0 for success, negative value otherwise and rte_errno is set. 4775 */ 4776 static int 4777 flow_mreg_add_default_copy_action(struct rte_eth_dev *dev, 4778 struct rte_flow_error *error) 4779 { 4780 struct mlx5_priv *priv = dev->data->dev_private; 4781 struct mlx5_flow_mreg_copy_resource *mcp_res; 4782 struct mlx5_flow_cb_ctx ctx; 4783 uint32_t mark_id; 4784 4785 /* Check whether extensive metadata feature is engaged. */ 4786 if (!priv->sh->config.dv_flow_en || 4787 priv->sh->config.dv_xmeta_en == MLX5_XMETA_MODE_LEGACY || 4788 !mlx5_flow_ext_mreg_supported(dev) || 4789 !priv->sh->dv_regc0_mask) 4790 return 0; 4791 /* 4792 * Add default mreg copy flow may be called multiple time, but 4793 * only be called once in stop. Avoid register it twice. 4794 */ 4795 mark_id = MLX5_DEFAULT_COPY_ID; 4796 ctx.data = &mark_id; 4797 if (mlx5_hlist_lookup(priv->mreg_cp_tbl, mark_id, &ctx)) 4798 return 0; 4799 mcp_res = flow_mreg_add_copy_action(dev, mark_id, error); 4800 if (!mcp_res) 4801 return -rte_errno; 4802 return 0; 4803 } 4804 4805 /** 4806 * Add a flow of copying flow metadata registers in RX_CP_TBL. 4807 * 4808 * All the flow having Q/RSS action should be split by 4809 * flow_mreg_split_qrss_prep() to pass by RX_CP_TBL. A flow in the RX_CP_TBL 4810 * performs the following, 4811 * - CQE->flow_tag := reg_c[1] (MARK) 4812 * - CQE->flow_table_metadata (reg_b) := reg_c[0] (META) 4813 * As CQE's flow_tag is not a register, it can't be simply copied from reg_c[1] 4814 * but there should be a flow per each MARK ID set by MARK action. 4815 * 4816 * For the aforementioned reason, if there's a MARK action in flow's action 4817 * list, a corresponding flow should be added to the RX_CP_TBL in order to copy 4818 * the MARK ID to CQE's flow_tag like, 4819 * - If reg_c[1] is mark_id, 4820 * flow_tag := mark_id, reg_b := reg_c[0] and jump to RX_ACT_TBL. 4821 * 4822 * For SET_META action which stores value in reg_c[0], as the destination is 4823 * also a flow metadata register (reg_b), adding a default flow is enough. Zero 4824 * MARK ID means the default flow. The default flow looks like, 4825 * - For all flow, reg_b := reg_c[0] and jump to RX_ACT_TBL. 4826 * 4827 * @param dev 4828 * Pointer to Ethernet device. 4829 * @param flow 4830 * Pointer to flow structure. 4831 * @param[in] actions 4832 * Pointer to the list of actions. 4833 * @param[out] error 4834 * Perform verbose error reporting if not NULL. 4835 * 4836 * @return 4837 * 0 on success, negative value otherwise and rte_errno is set. 4838 */ 4839 static int 4840 flow_mreg_update_copy_table(struct rte_eth_dev *dev, 4841 struct rte_flow *flow, 4842 const struct rte_flow_action *actions, 4843 struct rte_flow_error *error) 4844 { 4845 struct mlx5_priv *priv = dev->data->dev_private; 4846 struct mlx5_sh_config *config = &priv->sh->config; 4847 struct mlx5_flow_mreg_copy_resource *mcp_res; 4848 const struct rte_flow_action_mark *mark; 4849 4850 /* Check whether extensive metadata feature is engaged. */ 4851 if (!config->dv_flow_en || 4852 config->dv_xmeta_en == MLX5_XMETA_MODE_LEGACY || 4853 !mlx5_flow_ext_mreg_supported(dev) || 4854 !priv->sh->dv_regc0_mask) 4855 return 0; 4856 /* Find MARK action. */ 4857 for (; actions->type != RTE_FLOW_ACTION_TYPE_END; actions++) { 4858 switch (actions->type) { 4859 case RTE_FLOW_ACTION_TYPE_FLAG: 4860 mcp_res = flow_mreg_add_copy_action 4861 (dev, MLX5_FLOW_MARK_DEFAULT, error); 4862 if (!mcp_res) 4863 return -rte_errno; 4864 flow->rix_mreg_copy = mcp_res->idx; 4865 return 0; 4866 case RTE_FLOW_ACTION_TYPE_MARK: 4867 mark = (const struct rte_flow_action_mark *) 4868 actions->conf; 4869 mcp_res = 4870 flow_mreg_add_copy_action(dev, mark->id, error); 4871 if (!mcp_res) 4872 return -rte_errno; 4873 flow->rix_mreg_copy = mcp_res->idx; 4874 return 0; 4875 default: 4876 break; 4877 } 4878 } 4879 return 0; 4880 } 4881 4882 #define MLX5_MAX_SPLIT_ACTIONS 24 4883 #define MLX5_MAX_SPLIT_ITEMS 24 4884 4885 /** 4886 * Split the hairpin flow. 4887 * Since HW can't support encap and push-vlan on Rx, we move these 4888 * actions to Tx. 4889 * If the count action is after the encap then we also 4890 * move the count action. in this case the count will also measure 4891 * the outer bytes. 4892 * 4893 * @param dev 4894 * Pointer to Ethernet device. 4895 * @param[in] actions 4896 * Associated actions (list terminated by the END action). 4897 * @param[out] actions_rx 4898 * Rx flow actions. 4899 * @param[out] actions_tx 4900 * Tx flow actions.. 4901 * @param[out] pattern_tx 4902 * The pattern items for the Tx flow. 4903 * @param[out] flow_id 4904 * The flow ID connected to this flow. 4905 * 4906 * @return 4907 * 0 on success. 4908 */ 4909 static int 4910 flow_hairpin_split(struct rte_eth_dev *dev, 4911 const struct rte_flow_action actions[], 4912 struct rte_flow_action actions_rx[], 4913 struct rte_flow_action actions_tx[], 4914 struct rte_flow_item pattern_tx[], 4915 uint32_t flow_id) 4916 { 4917 const struct rte_flow_action_raw_encap *raw_encap; 4918 const struct rte_flow_action_raw_decap *raw_decap; 4919 struct mlx5_rte_flow_action_set_tag *set_tag; 4920 struct rte_flow_action *tag_action; 4921 struct mlx5_rte_flow_item_tag *tag_item; 4922 struct rte_flow_item *item; 4923 char *addr; 4924 int encap = 0; 4925 4926 for (; actions->type != RTE_FLOW_ACTION_TYPE_END; actions++) { 4927 switch (actions->type) { 4928 case RTE_FLOW_ACTION_TYPE_VXLAN_ENCAP: 4929 case RTE_FLOW_ACTION_TYPE_NVGRE_ENCAP: 4930 case RTE_FLOW_ACTION_TYPE_OF_PUSH_VLAN: 4931 case RTE_FLOW_ACTION_TYPE_OF_SET_VLAN_VID: 4932 case RTE_FLOW_ACTION_TYPE_OF_SET_VLAN_PCP: 4933 rte_memcpy(actions_tx, actions, 4934 sizeof(struct rte_flow_action)); 4935 actions_tx++; 4936 break; 4937 case RTE_FLOW_ACTION_TYPE_COUNT: 4938 if (encap) { 4939 rte_memcpy(actions_tx, actions, 4940 sizeof(struct rte_flow_action)); 4941 actions_tx++; 4942 } else { 4943 rte_memcpy(actions_rx, actions, 4944 sizeof(struct rte_flow_action)); 4945 actions_rx++; 4946 } 4947 break; 4948 case RTE_FLOW_ACTION_TYPE_RAW_ENCAP: 4949 raw_encap = actions->conf; 4950 if (raw_encap->size > MLX5_ENCAPSULATION_DECISION_SIZE) { 4951 memcpy(actions_tx, actions, 4952 sizeof(struct rte_flow_action)); 4953 actions_tx++; 4954 encap = 1; 4955 } else { 4956 rte_memcpy(actions_rx, actions, 4957 sizeof(struct rte_flow_action)); 4958 actions_rx++; 4959 } 4960 break; 4961 case RTE_FLOW_ACTION_TYPE_RAW_DECAP: 4962 raw_decap = actions->conf; 4963 if (raw_decap->size < MLX5_ENCAPSULATION_DECISION_SIZE) { 4964 memcpy(actions_tx, actions, 4965 sizeof(struct rte_flow_action)); 4966 actions_tx++; 4967 } else { 4968 rte_memcpy(actions_rx, actions, 4969 sizeof(struct rte_flow_action)); 4970 actions_rx++; 4971 } 4972 break; 4973 default: 4974 rte_memcpy(actions_rx, actions, 4975 sizeof(struct rte_flow_action)); 4976 actions_rx++; 4977 break; 4978 } 4979 } 4980 /* Add set meta action and end action for the Rx flow. */ 4981 tag_action = actions_rx; 4982 tag_action->type = (enum rte_flow_action_type) 4983 MLX5_RTE_FLOW_ACTION_TYPE_TAG; 4984 actions_rx++; 4985 rte_memcpy(actions_rx, actions, sizeof(struct rte_flow_action)); 4986 actions_rx++; 4987 set_tag = (void *)actions_rx; 4988 *set_tag = (struct mlx5_rte_flow_action_set_tag) { 4989 .id = mlx5_flow_get_reg_id(dev, MLX5_HAIRPIN_RX, 0, NULL), 4990 .data = flow_id, 4991 }; 4992 MLX5_ASSERT(set_tag->id > REG_NON); 4993 tag_action->conf = set_tag; 4994 /* Create Tx item list. */ 4995 rte_memcpy(actions_tx, actions, sizeof(struct rte_flow_action)); 4996 addr = (void *)&pattern_tx[2]; 4997 item = pattern_tx; 4998 item->type = (enum rte_flow_item_type) 4999 MLX5_RTE_FLOW_ITEM_TYPE_TAG; 5000 tag_item = (void *)addr; 5001 tag_item->data = flow_id; 5002 tag_item->id = mlx5_flow_get_reg_id(dev, MLX5_HAIRPIN_TX, 0, NULL); 5003 MLX5_ASSERT(set_tag->id > REG_NON); 5004 item->spec = tag_item; 5005 addr += sizeof(struct mlx5_rte_flow_item_tag); 5006 tag_item = (void *)addr; 5007 tag_item->data = UINT32_MAX; 5008 tag_item->id = UINT16_MAX; 5009 item->mask = tag_item; 5010 item->last = NULL; 5011 item++; 5012 item->type = RTE_FLOW_ITEM_TYPE_END; 5013 return 0; 5014 } 5015 5016 /** 5017 * The last stage of splitting chain, just creates the subflow 5018 * without any modification. 5019 * 5020 * @param[in] dev 5021 * Pointer to Ethernet device. 5022 * @param[in] flow 5023 * Parent flow structure pointer. 5024 * @param[in, out] sub_flow 5025 * Pointer to return the created subflow, may be NULL. 5026 * @param[in] attr 5027 * Flow rule attributes. 5028 * @param[in] items 5029 * Pattern specification (list terminated by the END pattern item). 5030 * @param[in] actions 5031 * Associated actions (list terminated by the END action). 5032 * @param[in] flow_split_info 5033 * Pointer to flow split info structure. 5034 * @param[out] error 5035 * Perform verbose error reporting if not NULL. 5036 * @return 5037 * 0 on success, negative value otherwise 5038 */ 5039 static int 5040 flow_create_split_inner(struct rte_eth_dev *dev, 5041 struct rte_flow *flow, 5042 struct mlx5_flow **sub_flow, 5043 const struct rte_flow_attr *attr, 5044 const struct rte_flow_item items[], 5045 const struct rte_flow_action actions[], 5046 struct mlx5_flow_split_info *flow_split_info, 5047 struct rte_flow_error *error) 5048 { 5049 struct mlx5_flow *dev_flow; 5050 struct mlx5_flow_workspace *wks = mlx5_flow_get_thread_workspace(); 5051 5052 dev_flow = flow_drv_prepare(dev, flow, attr, items, actions, 5053 flow_split_info->flow_idx, error); 5054 if (!dev_flow) 5055 return -rte_errno; 5056 dev_flow->flow = flow; 5057 dev_flow->external = flow_split_info->external; 5058 dev_flow->skip_scale = flow_split_info->skip_scale; 5059 /* Subflow object was created, we must include one in the list. */ 5060 SILIST_INSERT(&flow->dev_handles, dev_flow->handle_idx, 5061 dev_flow->handle, next); 5062 /* 5063 * If dev_flow is as one of the suffix flow, some actions in suffix 5064 * flow may need some user defined item layer flags, and pass the 5065 * Metadata rxq mark flag to suffix flow as well. 5066 */ 5067 if (flow_split_info->prefix_layers) 5068 dev_flow->handle->layers = flow_split_info->prefix_layers; 5069 if (flow_split_info->prefix_mark) { 5070 MLX5_ASSERT(wks); 5071 wks->mark = 1; 5072 } 5073 if (sub_flow) 5074 *sub_flow = dev_flow; 5075 #ifdef HAVE_IBV_FLOW_DV_SUPPORT 5076 dev_flow->dv.table_id = flow_split_info->table_id; 5077 #endif 5078 return flow_drv_translate(dev, dev_flow, attr, items, actions, error); 5079 } 5080 5081 /** 5082 * Get the sub policy of a meter. 5083 * 5084 * @param[in] dev 5085 * Pointer to Ethernet device. 5086 * @param[in] flow 5087 * Parent flow structure pointer. 5088 * @param wks 5089 * Pointer to thread flow work space. 5090 * @param[in] attr 5091 * Flow rule attributes. 5092 * @param[in] items 5093 * Pattern specification (list terminated by the END pattern item). 5094 * @param[out] error 5095 * Perform verbose error reporting if not NULL. 5096 * 5097 * @return 5098 * Pointer to the meter sub policy, NULL otherwise and rte_errno is set. 5099 */ 5100 static struct mlx5_flow_meter_sub_policy * 5101 get_meter_sub_policy(struct rte_eth_dev *dev, 5102 struct rte_flow *flow, 5103 struct mlx5_flow_workspace *wks, 5104 const struct rte_flow_attr *attr, 5105 const struct rte_flow_item items[], 5106 struct rte_flow_error *error) 5107 { 5108 struct mlx5_flow_meter_policy *policy; 5109 struct mlx5_flow_meter_policy *final_policy; 5110 struct mlx5_flow_meter_sub_policy *sub_policy = NULL; 5111 5112 policy = wks->policy; 5113 final_policy = policy->is_hierarchy ? wks->final_policy : policy; 5114 if (final_policy->is_rss || final_policy->is_queue) { 5115 struct mlx5_flow_rss_desc rss_desc_v[MLX5_MTR_RTE_COLORS]; 5116 struct mlx5_flow_rss_desc *rss_desc[MLX5_MTR_RTE_COLORS] = {0}; 5117 uint32_t i; 5118 5119 /* 5120 * This is a tmp dev_flow, 5121 * no need to register any matcher for it in translate. 5122 */ 5123 wks->skip_matcher_reg = 1; 5124 for (i = 0; i < MLX5_MTR_RTE_COLORS; i++) { 5125 struct mlx5_flow dev_flow = {0}; 5126 struct mlx5_flow_handle dev_handle = { {0} }; 5127 uint8_t fate = final_policy->act_cnt[i].fate_action; 5128 5129 if (fate == MLX5_FLOW_FATE_SHARED_RSS) { 5130 const struct rte_flow_action_rss *rss_act = 5131 final_policy->act_cnt[i].rss->conf; 5132 struct rte_flow_action rss_actions[2] = { 5133 [0] = { 5134 .type = RTE_FLOW_ACTION_TYPE_RSS, 5135 .conf = rss_act, 5136 }, 5137 [1] = { 5138 .type = RTE_FLOW_ACTION_TYPE_END, 5139 .conf = NULL, 5140 } 5141 }; 5142 5143 dev_flow.handle = &dev_handle; 5144 dev_flow.ingress = attr->ingress; 5145 dev_flow.flow = flow; 5146 dev_flow.external = 0; 5147 #ifdef HAVE_IBV_FLOW_DV_SUPPORT 5148 dev_flow.dv.transfer = attr->transfer; 5149 #endif 5150 /** 5151 * Translate RSS action to get rss hash fields. 5152 */ 5153 if (flow_drv_translate(dev, &dev_flow, attr, 5154 items, rss_actions, error)) 5155 goto exit; 5156 rss_desc_v[i] = wks->rss_desc; 5157 rss_desc_v[i].key_len = MLX5_RSS_HASH_KEY_LEN; 5158 rss_desc_v[i].hash_fields = 5159 dev_flow.hash_fields; 5160 rss_desc_v[i].queue_num = 5161 rss_desc_v[i].hash_fields ? 5162 rss_desc_v[i].queue_num : 1; 5163 rss_desc_v[i].tunnel = 5164 !!(dev_flow.handle->layers & 5165 MLX5_FLOW_LAYER_TUNNEL); 5166 /* Use the RSS queues in the containers. */ 5167 rss_desc_v[i].queue = 5168 (uint16_t *)(uintptr_t)rss_act->queue; 5169 rss_desc[i] = &rss_desc_v[i]; 5170 } else if (fate == MLX5_FLOW_FATE_QUEUE) { 5171 /* This is queue action. */ 5172 rss_desc_v[i] = wks->rss_desc; 5173 rss_desc_v[i].key_len = 0; 5174 rss_desc_v[i].hash_fields = 0; 5175 rss_desc_v[i].queue = 5176 &final_policy->act_cnt[i].queue; 5177 rss_desc_v[i].queue_num = 1; 5178 rss_desc[i] = &rss_desc_v[i]; 5179 } else { 5180 rss_desc[i] = NULL; 5181 } 5182 } 5183 sub_policy = flow_drv_meter_sub_policy_rss_prepare(dev, 5184 flow, policy, rss_desc); 5185 } else { 5186 enum mlx5_meter_domain mtr_domain = 5187 attr->transfer ? MLX5_MTR_DOMAIN_TRANSFER : 5188 (attr->egress ? MLX5_MTR_DOMAIN_EGRESS : 5189 MLX5_MTR_DOMAIN_INGRESS); 5190 sub_policy = policy->sub_policys[mtr_domain][0]; 5191 } 5192 if (!sub_policy) 5193 rte_flow_error_set(error, EINVAL, 5194 RTE_FLOW_ERROR_TYPE_UNSPECIFIED, NULL, 5195 "Failed to get meter sub-policy."); 5196 exit: 5197 return sub_policy; 5198 } 5199 5200 /** 5201 * Split the meter flow. 5202 * 5203 * As meter flow will split to three sub flow, other than meter 5204 * action, the other actions make sense to only meter accepts 5205 * the packet. If it need to be dropped, no other additional 5206 * actions should be take. 5207 * 5208 * One kind of special action which decapsulates the L3 tunnel 5209 * header will be in the prefix sub flow, as not to take the 5210 * L3 tunnel header into account. 5211 * 5212 * @param[in] dev 5213 * Pointer to Ethernet device. 5214 * @param[in] flow 5215 * Parent flow structure pointer. 5216 * @param wks 5217 * Pointer to thread flow work space. 5218 * @param[in] attr 5219 * Flow rule attributes. 5220 * @param[in] items 5221 * Pattern specification (list terminated by the END pattern item). 5222 * @param[out] sfx_items 5223 * Suffix flow match items (list terminated by the END pattern item). 5224 * @param[in] actions 5225 * Associated actions (list terminated by the END action). 5226 * @param[out] actions_sfx 5227 * Suffix flow actions. 5228 * @param[out] actions_pre 5229 * Prefix flow actions. 5230 * @param[out] mtr_flow_id 5231 * Pointer to meter flow id. 5232 * @param[out] error 5233 * Perform verbose error reporting if not NULL. 5234 * 5235 * @return 5236 * 0 on success, a negative errno value otherwise and rte_errno is set. 5237 */ 5238 static int 5239 flow_meter_split_prep(struct rte_eth_dev *dev, 5240 struct rte_flow *flow, 5241 struct mlx5_flow_workspace *wks, 5242 const struct rte_flow_attr *attr, 5243 const struct rte_flow_item items[], 5244 struct rte_flow_item sfx_items[], 5245 const struct rte_flow_action actions[], 5246 struct rte_flow_action actions_sfx[], 5247 struct rte_flow_action actions_pre[], 5248 uint32_t *mtr_flow_id, 5249 struct rte_flow_error *error) 5250 { 5251 struct mlx5_priv *priv = dev->data->dev_private; 5252 struct mlx5_flow_meter_info *fm = wks->fm; 5253 struct rte_flow_action *tag_action = NULL; 5254 struct rte_flow_item *tag_item; 5255 struct mlx5_rte_flow_action_set_tag *set_tag; 5256 const struct rte_flow_action_raw_encap *raw_encap; 5257 const struct rte_flow_action_raw_decap *raw_decap; 5258 struct mlx5_rte_flow_item_tag *tag_item_spec; 5259 struct mlx5_rte_flow_item_tag *tag_item_mask; 5260 uint32_t tag_id = 0; 5261 struct rte_flow_item *vlan_item_dst = NULL; 5262 const struct rte_flow_item *vlan_item_src = NULL; 5263 const struct rte_flow_item *orig_items = items; 5264 struct rte_flow_action *hw_mtr_action; 5265 struct rte_flow_action *action_pre_head = NULL; 5266 int32_t flow_src_port = priv->representor_id; 5267 bool mtr_first; 5268 uint8_t mtr_id_offset = priv->mtr_reg_share ? MLX5_MTR_COLOR_BITS : 0; 5269 uint8_t mtr_reg_bits = priv->mtr_reg_share ? 5270 MLX5_MTR_IDLE_BITS_IN_COLOR_REG : MLX5_REG_BITS; 5271 uint32_t flow_id = 0; 5272 uint32_t flow_id_reversed = 0; 5273 uint8_t flow_id_bits = 0; 5274 int shift; 5275 5276 /* Prepare the suffix subflow items. */ 5277 tag_item = sfx_items++; 5278 for (; items->type != RTE_FLOW_ITEM_TYPE_END; items++) { 5279 struct mlx5_priv *port_priv; 5280 const struct rte_flow_item_port_id *pid_v; 5281 int item_type = items->type; 5282 5283 switch (item_type) { 5284 case RTE_FLOW_ITEM_TYPE_PORT_ID: 5285 pid_v = items->spec; 5286 MLX5_ASSERT(pid_v); 5287 port_priv = mlx5_port_to_eswitch_info(pid_v->id, false); 5288 if (!port_priv) 5289 return rte_flow_error_set(error, 5290 rte_errno, 5291 RTE_FLOW_ERROR_TYPE_ITEM_SPEC, 5292 pid_v, 5293 "Failed to get port info."); 5294 flow_src_port = port_priv->representor_id; 5295 if (!fm->def_policy && wks->policy->is_hierarchy && 5296 flow_src_port != priv->representor_id) { 5297 if (flow_drv_mtr_hierarchy_rule_create(dev, 5298 flow, fm, 5299 flow_src_port, 5300 items, 5301 error)) 5302 return -rte_errno; 5303 } 5304 memcpy(sfx_items, items, sizeof(*sfx_items)); 5305 sfx_items++; 5306 break; 5307 case RTE_FLOW_ITEM_TYPE_VLAN: 5308 /* Determine if copy vlan item below. */ 5309 vlan_item_src = items; 5310 vlan_item_dst = sfx_items++; 5311 vlan_item_dst->type = RTE_FLOW_ITEM_TYPE_VOID; 5312 break; 5313 default: 5314 break; 5315 } 5316 } 5317 sfx_items->type = RTE_FLOW_ITEM_TYPE_END; 5318 sfx_items++; 5319 mtr_first = priv->sh->meter_aso_en && 5320 (attr->egress || (attr->transfer && flow_src_port != UINT16_MAX)); 5321 /* For ASO meter, meter must be before tag in TX direction. */ 5322 if (mtr_first) { 5323 action_pre_head = actions_pre++; 5324 /* Leave space for tag action. */ 5325 tag_action = actions_pre++; 5326 } 5327 /* Prepare the actions for prefix and suffix flow. */ 5328 for (; actions->type != RTE_FLOW_ACTION_TYPE_END; actions++) { 5329 struct rte_flow_action *action_cur = NULL; 5330 5331 switch (actions->type) { 5332 case RTE_FLOW_ACTION_TYPE_METER: 5333 if (mtr_first) { 5334 action_cur = action_pre_head; 5335 } else { 5336 /* Leave space for tag action. */ 5337 tag_action = actions_pre++; 5338 action_cur = actions_pre++; 5339 } 5340 break; 5341 case RTE_FLOW_ACTION_TYPE_VXLAN_DECAP: 5342 case RTE_FLOW_ACTION_TYPE_NVGRE_DECAP: 5343 action_cur = actions_pre++; 5344 break; 5345 case RTE_FLOW_ACTION_TYPE_RAW_ENCAP: 5346 raw_encap = actions->conf; 5347 if (raw_encap->size < MLX5_ENCAPSULATION_DECISION_SIZE) 5348 action_cur = actions_pre++; 5349 break; 5350 case RTE_FLOW_ACTION_TYPE_RAW_DECAP: 5351 raw_decap = actions->conf; 5352 if (raw_decap->size > MLX5_ENCAPSULATION_DECISION_SIZE) 5353 action_cur = actions_pre++; 5354 break; 5355 case RTE_FLOW_ACTION_TYPE_OF_PUSH_VLAN: 5356 case RTE_FLOW_ACTION_TYPE_OF_SET_VLAN_VID: 5357 if (vlan_item_dst && vlan_item_src) { 5358 memcpy(vlan_item_dst, vlan_item_src, 5359 sizeof(*vlan_item_dst)); 5360 /* 5361 * Convert to internal match item, it is used 5362 * for vlan push and set vid. 5363 */ 5364 vlan_item_dst->type = (enum rte_flow_item_type) 5365 MLX5_RTE_FLOW_ITEM_TYPE_VLAN; 5366 } 5367 break; 5368 default: 5369 break; 5370 } 5371 if (!action_cur) 5372 action_cur = (fm->def_policy) ? 5373 actions_sfx++ : actions_pre++; 5374 memcpy(action_cur, actions, sizeof(struct rte_flow_action)); 5375 } 5376 /* Add end action to the actions. */ 5377 actions_sfx->type = RTE_FLOW_ACTION_TYPE_END; 5378 if (priv->sh->meter_aso_en) { 5379 /** 5380 * For ASO meter, need to add an extra jump action explicitly, 5381 * to jump from meter to policer table. 5382 */ 5383 struct mlx5_flow_meter_sub_policy *sub_policy; 5384 struct mlx5_flow_tbl_data_entry *tbl_data; 5385 5386 if (!fm->def_policy) { 5387 sub_policy = get_meter_sub_policy(dev, flow, wks, 5388 attr, orig_items, 5389 error); 5390 if (!sub_policy) 5391 return -rte_errno; 5392 } else { 5393 enum mlx5_meter_domain mtr_domain = 5394 attr->transfer ? MLX5_MTR_DOMAIN_TRANSFER : 5395 (attr->egress ? MLX5_MTR_DOMAIN_EGRESS : 5396 MLX5_MTR_DOMAIN_INGRESS); 5397 5398 sub_policy = 5399 &priv->sh->mtrmng->def_policy[mtr_domain]->sub_policy; 5400 } 5401 tbl_data = container_of(sub_policy->tbl_rsc, 5402 struct mlx5_flow_tbl_data_entry, tbl); 5403 hw_mtr_action = actions_pre++; 5404 hw_mtr_action->type = (enum rte_flow_action_type) 5405 MLX5_RTE_FLOW_ACTION_TYPE_JUMP; 5406 hw_mtr_action->conf = tbl_data->jump.action; 5407 } 5408 actions_pre->type = RTE_FLOW_ACTION_TYPE_END; 5409 actions_pre++; 5410 if (!tag_action) 5411 return rte_flow_error_set(error, ENOMEM, 5412 RTE_FLOW_ERROR_TYPE_UNSPECIFIED, 5413 NULL, "No tag action space."); 5414 if (!mtr_flow_id) { 5415 tag_action->type = RTE_FLOW_ACTION_TYPE_VOID; 5416 goto exit; 5417 } 5418 /* Only default-policy Meter creates mtr flow id. */ 5419 if (fm->def_policy) { 5420 mlx5_ipool_malloc(fm->flow_ipool, &tag_id); 5421 if (!tag_id) 5422 return rte_flow_error_set(error, ENOMEM, 5423 RTE_FLOW_ERROR_TYPE_UNSPECIFIED, NULL, 5424 "Failed to allocate meter flow id."); 5425 flow_id = tag_id - 1; 5426 flow_id_bits = (!flow_id) ? 1 : 5427 (MLX5_REG_BITS - __builtin_clz(flow_id)); 5428 if ((flow_id_bits + priv->sh->mtrmng->max_mtr_bits) > 5429 mtr_reg_bits) { 5430 mlx5_ipool_free(fm->flow_ipool, tag_id); 5431 return rte_flow_error_set(error, EINVAL, 5432 RTE_FLOW_ERROR_TYPE_UNSPECIFIED, NULL, 5433 "Meter flow id exceeds max limit."); 5434 } 5435 if (flow_id_bits > priv->sh->mtrmng->max_mtr_flow_bits) 5436 priv->sh->mtrmng->max_mtr_flow_bits = flow_id_bits; 5437 } 5438 /* Build tag actions and items for meter_id/meter flow_id. */ 5439 set_tag = (struct mlx5_rte_flow_action_set_tag *)actions_pre; 5440 tag_item_spec = (struct mlx5_rte_flow_item_tag *)sfx_items; 5441 tag_item_mask = tag_item_spec + 1; 5442 /* Both flow_id and meter_id share the same register. */ 5443 *set_tag = (struct mlx5_rte_flow_action_set_tag) { 5444 .id = (enum modify_reg)mlx5_flow_get_reg_id(dev, MLX5_MTR_ID, 5445 0, error), 5446 .offset = mtr_id_offset, 5447 .length = mtr_reg_bits, 5448 .data = flow->meter, 5449 }; 5450 /* 5451 * The color Reg bits used by flow_id are growing from 5452 * msb to lsb, so must do bit reverse for flow_id val in RegC. 5453 */ 5454 for (shift = 0; shift < flow_id_bits; shift++) 5455 flow_id_reversed = (flow_id_reversed << 1) | 5456 ((flow_id >> shift) & 0x1); 5457 set_tag->data |= 5458 flow_id_reversed << (mtr_reg_bits - flow_id_bits); 5459 tag_item_spec->id = set_tag->id; 5460 tag_item_spec->data = set_tag->data << mtr_id_offset; 5461 tag_item_mask->data = UINT32_MAX << mtr_id_offset; 5462 tag_action->type = (enum rte_flow_action_type) 5463 MLX5_RTE_FLOW_ACTION_TYPE_TAG; 5464 tag_action->conf = set_tag; 5465 tag_item->type = (enum rte_flow_item_type) 5466 MLX5_RTE_FLOW_ITEM_TYPE_TAG; 5467 tag_item->spec = tag_item_spec; 5468 tag_item->last = NULL; 5469 tag_item->mask = tag_item_mask; 5470 exit: 5471 if (mtr_flow_id) 5472 *mtr_flow_id = tag_id; 5473 return 0; 5474 } 5475 5476 /** 5477 * Split action list having QUEUE/RSS for metadata register copy. 5478 * 5479 * Once Q/RSS action is detected in user's action list, the flow action 5480 * should be split in order to copy metadata registers, which will happen in 5481 * RX_CP_TBL like, 5482 * - CQE->flow_tag := reg_c[1] (MARK) 5483 * - CQE->flow_table_metadata (reg_b) := reg_c[0] (META) 5484 * The Q/RSS action will be performed on RX_ACT_TBL after passing by RX_CP_TBL. 5485 * This is because the last action of each flow must be a terminal action 5486 * (QUEUE, RSS or DROP). 5487 * 5488 * Flow ID must be allocated to identify actions in the RX_ACT_TBL and it is 5489 * stored and kept in the mlx5_flow structure per each sub_flow. 5490 * 5491 * The Q/RSS action is replaced with, 5492 * - SET_TAG, setting the allocated flow ID to reg_c[2]. 5493 * And the following JUMP action is added at the end, 5494 * - JUMP, to RX_CP_TBL. 5495 * 5496 * A flow to perform remained Q/RSS action will be created in RX_ACT_TBL by 5497 * flow_create_split_metadata() routine. The flow will look like, 5498 * - If flow ID matches (reg_c[2]), perform Q/RSS. 5499 * 5500 * @param dev 5501 * Pointer to Ethernet device. 5502 * @param[out] split_actions 5503 * Pointer to store split actions to jump to CP_TBL. 5504 * @param[in] actions 5505 * Pointer to the list of original flow actions. 5506 * @param[in] qrss 5507 * Pointer to the Q/RSS action. 5508 * @param[in] actions_n 5509 * Number of original actions. 5510 * @param[in] mtr_sfx 5511 * Check if it is in meter suffix table. 5512 * @param[out] error 5513 * Perform verbose error reporting if not NULL. 5514 * 5515 * @return 5516 * non-zero unique flow_id on success, otherwise 0 and 5517 * error/rte_error are set. 5518 */ 5519 static uint32_t 5520 flow_mreg_split_qrss_prep(struct rte_eth_dev *dev, 5521 struct rte_flow_action *split_actions, 5522 const struct rte_flow_action *actions, 5523 const struct rte_flow_action *qrss, 5524 int actions_n, int mtr_sfx, 5525 struct rte_flow_error *error) 5526 { 5527 struct mlx5_priv *priv = dev->data->dev_private; 5528 struct mlx5_rte_flow_action_set_tag *set_tag; 5529 struct rte_flow_action_jump *jump; 5530 const int qrss_idx = qrss - actions; 5531 uint32_t flow_id = 0; 5532 int ret = 0; 5533 5534 /* 5535 * Given actions will be split 5536 * - Replace QUEUE/RSS action with SET_TAG to set flow ID. 5537 * - Add jump to mreg CP_TBL. 5538 * As a result, there will be one more action. 5539 */ 5540 memcpy(split_actions, actions, sizeof(*split_actions) * actions_n); 5541 /* Count MLX5_RTE_FLOW_ACTION_TYPE_TAG. */ 5542 ++actions_n; 5543 set_tag = (void *)(split_actions + actions_n); 5544 /* 5545 * If we are not the meter suffix flow, add the tag action. 5546 * Since meter suffix flow already has the tag added. 5547 */ 5548 if (!mtr_sfx) { 5549 /* 5550 * Allocate the new subflow ID. This one is unique within 5551 * device and not shared with representors. Otherwise, 5552 * we would have to resolve multi-thread access synch 5553 * issue. Each flow on the shared device is appended 5554 * with source vport identifier, so the resulting 5555 * flows will be unique in the shared (by master and 5556 * representors) domain even if they have coinciding 5557 * IDs. 5558 */ 5559 mlx5_ipool_malloc(priv->sh->ipool 5560 [MLX5_IPOOL_RSS_EXPANTION_FLOW_ID], &flow_id); 5561 if (!flow_id) 5562 return rte_flow_error_set(error, ENOMEM, 5563 RTE_FLOW_ERROR_TYPE_ACTION, 5564 NULL, "can't allocate id " 5565 "for split Q/RSS subflow"); 5566 /* Internal SET_TAG action to set flow ID. */ 5567 *set_tag = (struct mlx5_rte_flow_action_set_tag){ 5568 .data = flow_id, 5569 }; 5570 ret = mlx5_flow_get_reg_id(dev, MLX5_COPY_MARK, 0, error); 5571 if (ret < 0) 5572 return ret; 5573 set_tag->id = ret; 5574 /* Construct new actions array. */ 5575 /* Replace QUEUE/RSS action. */ 5576 split_actions[qrss_idx] = (struct rte_flow_action){ 5577 .type = (enum rte_flow_action_type) 5578 MLX5_RTE_FLOW_ACTION_TYPE_TAG, 5579 .conf = set_tag, 5580 }; 5581 } else { 5582 /* 5583 * If we are the suffix flow of meter, tag already exist. 5584 * Set the QUEUE/RSS action to void. 5585 */ 5586 split_actions[qrss_idx].type = RTE_FLOW_ACTION_TYPE_VOID; 5587 } 5588 /* JUMP action to jump to mreg copy table (CP_TBL). */ 5589 jump = (void *)(set_tag + 1); 5590 *jump = (struct rte_flow_action_jump){ 5591 .group = MLX5_FLOW_MREG_CP_TABLE_GROUP, 5592 }; 5593 split_actions[actions_n - 2] = (struct rte_flow_action){ 5594 .type = RTE_FLOW_ACTION_TYPE_JUMP, 5595 .conf = jump, 5596 }; 5597 split_actions[actions_n - 1] = (struct rte_flow_action){ 5598 .type = RTE_FLOW_ACTION_TYPE_END, 5599 }; 5600 return flow_id; 5601 } 5602 5603 /** 5604 * Extend the given action list for Tx metadata copy. 5605 * 5606 * Copy the given action list to the ext_actions and add flow metadata register 5607 * copy action in order to copy reg_a set by WQE to reg_c[0]. 5608 * 5609 * @param[out] ext_actions 5610 * Pointer to the extended action list. 5611 * @param[in] actions 5612 * Pointer to the list of actions. 5613 * @param[in] actions_n 5614 * Number of actions in the list. 5615 * @param[out] error 5616 * Perform verbose error reporting if not NULL. 5617 * @param[in] encap_idx 5618 * The encap action index. 5619 * 5620 * @return 5621 * 0 on success, negative value otherwise 5622 */ 5623 static int 5624 flow_mreg_tx_copy_prep(struct rte_eth_dev *dev, 5625 struct rte_flow_action *ext_actions, 5626 const struct rte_flow_action *actions, 5627 int actions_n, struct rte_flow_error *error, 5628 int encap_idx) 5629 { 5630 struct mlx5_flow_action_copy_mreg *cp_mreg = 5631 (struct mlx5_flow_action_copy_mreg *) 5632 (ext_actions + actions_n + 1); 5633 int ret; 5634 5635 ret = mlx5_flow_get_reg_id(dev, MLX5_METADATA_RX, 0, error); 5636 if (ret < 0) 5637 return ret; 5638 cp_mreg->dst = ret; 5639 ret = mlx5_flow_get_reg_id(dev, MLX5_METADATA_TX, 0, error); 5640 if (ret < 0) 5641 return ret; 5642 cp_mreg->src = ret; 5643 if (encap_idx != 0) 5644 memcpy(ext_actions, actions, sizeof(*ext_actions) * encap_idx); 5645 if (encap_idx == actions_n - 1) { 5646 ext_actions[actions_n - 1] = (struct rte_flow_action){ 5647 .type = (enum rte_flow_action_type) 5648 MLX5_RTE_FLOW_ACTION_TYPE_COPY_MREG, 5649 .conf = cp_mreg, 5650 }; 5651 ext_actions[actions_n] = (struct rte_flow_action){ 5652 .type = RTE_FLOW_ACTION_TYPE_END, 5653 }; 5654 } else { 5655 ext_actions[encap_idx] = (struct rte_flow_action){ 5656 .type = (enum rte_flow_action_type) 5657 MLX5_RTE_FLOW_ACTION_TYPE_COPY_MREG, 5658 .conf = cp_mreg, 5659 }; 5660 memcpy(ext_actions + encap_idx + 1, actions + encap_idx, 5661 sizeof(*ext_actions) * (actions_n - encap_idx)); 5662 } 5663 return 0; 5664 } 5665 5666 /** 5667 * Check the match action from the action list. 5668 * 5669 * @param[in] actions 5670 * Pointer to the list of actions. 5671 * @param[in] attr 5672 * Flow rule attributes. 5673 * @param[in] action 5674 * The action to be check if exist. 5675 * @param[out] match_action_pos 5676 * Pointer to the position of the matched action if exists, otherwise is -1. 5677 * @param[out] qrss_action_pos 5678 * Pointer to the position of the Queue/RSS action if exists, otherwise is -1. 5679 * @param[out] modify_after_mirror 5680 * Pointer to the flag of modify action after FDB mirroring. 5681 * 5682 * @return 5683 * > 0 the total number of actions. 5684 * 0 if not found match action in action list. 5685 */ 5686 static int 5687 flow_check_match_action(const struct rte_flow_action actions[], 5688 const struct rte_flow_attr *attr, 5689 enum rte_flow_action_type action, 5690 int *match_action_pos, int *qrss_action_pos, 5691 int *modify_after_mirror) 5692 { 5693 const struct rte_flow_action_sample *sample; 5694 const struct rte_flow_action_raw_decap *decap; 5695 int actions_n = 0; 5696 uint32_t ratio = 0; 5697 int sub_type = 0; 5698 int flag = 0; 5699 int fdb_mirror = 0; 5700 5701 *match_action_pos = -1; 5702 *qrss_action_pos = -1; 5703 for (; actions->type != RTE_FLOW_ACTION_TYPE_END; actions++) { 5704 if (actions->type == action) { 5705 flag = 1; 5706 *match_action_pos = actions_n; 5707 } 5708 switch (actions->type) { 5709 case RTE_FLOW_ACTION_TYPE_QUEUE: 5710 case RTE_FLOW_ACTION_TYPE_RSS: 5711 *qrss_action_pos = actions_n; 5712 break; 5713 case RTE_FLOW_ACTION_TYPE_SAMPLE: 5714 sample = actions->conf; 5715 ratio = sample->ratio; 5716 sub_type = ((const struct rte_flow_action *) 5717 (sample->actions))->type; 5718 if (ratio == 1 && attr->transfer) 5719 fdb_mirror = 1; 5720 break; 5721 case RTE_FLOW_ACTION_TYPE_SET_MAC_SRC: 5722 case RTE_FLOW_ACTION_TYPE_SET_MAC_DST: 5723 case RTE_FLOW_ACTION_TYPE_SET_IPV4_SRC: 5724 case RTE_FLOW_ACTION_TYPE_SET_IPV4_DST: 5725 case RTE_FLOW_ACTION_TYPE_SET_IPV6_SRC: 5726 case RTE_FLOW_ACTION_TYPE_SET_IPV6_DST: 5727 case RTE_FLOW_ACTION_TYPE_SET_TP_SRC: 5728 case RTE_FLOW_ACTION_TYPE_SET_TP_DST: 5729 case RTE_FLOW_ACTION_TYPE_DEC_TTL: 5730 case RTE_FLOW_ACTION_TYPE_SET_TTL: 5731 case RTE_FLOW_ACTION_TYPE_INC_TCP_SEQ: 5732 case RTE_FLOW_ACTION_TYPE_DEC_TCP_SEQ: 5733 case RTE_FLOW_ACTION_TYPE_INC_TCP_ACK: 5734 case RTE_FLOW_ACTION_TYPE_DEC_TCP_ACK: 5735 case RTE_FLOW_ACTION_TYPE_SET_IPV4_DSCP: 5736 case RTE_FLOW_ACTION_TYPE_SET_IPV6_DSCP: 5737 case RTE_FLOW_ACTION_TYPE_FLAG: 5738 case RTE_FLOW_ACTION_TYPE_MARK: 5739 case RTE_FLOW_ACTION_TYPE_SET_META: 5740 case RTE_FLOW_ACTION_TYPE_SET_TAG: 5741 case RTE_FLOW_ACTION_TYPE_OF_POP_VLAN: 5742 case RTE_FLOW_ACTION_TYPE_OF_PUSH_VLAN: 5743 case RTE_FLOW_ACTION_TYPE_OF_SET_VLAN_VID: 5744 case RTE_FLOW_ACTION_TYPE_OF_SET_VLAN_PCP: 5745 case RTE_FLOW_ACTION_TYPE_VXLAN_DECAP: 5746 case RTE_FLOW_ACTION_TYPE_NVGRE_DECAP: 5747 case RTE_FLOW_ACTION_TYPE_MODIFY_FIELD: 5748 case RTE_FLOW_ACTION_TYPE_METER: 5749 if (fdb_mirror) 5750 *modify_after_mirror = 1; 5751 break; 5752 case RTE_FLOW_ACTION_TYPE_RAW_DECAP: 5753 decap = actions->conf; 5754 while ((++actions)->type == RTE_FLOW_ACTION_TYPE_VOID) 5755 ; 5756 actions_n++; 5757 if (actions->type == RTE_FLOW_ACTION_TYPE_RAW_ENCAP) { 5758 const struct rte_flow_action_raw_encap *encap = 5759 actions->conf; 5760 if (decap->size <= 5761 MLX5_ENCAPSULATION_DECISION_SIZE && 5762 encap->size > 5763 MLX5_ENCAPSULATION_DECISION_SIZE) 5764 /* L3 encap. */ 5765 break; 5766 } 5767 if (fdb_mirror) 5768 *modify_after_mirror = 1; 5769 break; 5770 default: 5771 break; 5772 } 5773 actions_n++; 5774 } 5775 if (flag && fdb_mirror && !*modify_after_mirror) { 5776 /* FDB mirroring uses the destination array to implement 5777 * instead of FLOW_SAMPLER object. 5778 */ 5779 if (sub_type != RTE_FLOW_ACTION_TYPE_END) 5780 flag = 0; 5781 } 5782 /* Count RTE_FLOW_ACTION_TYPE_END. */ 5783 return flag ? actions_n + 1 : 0; 5784 } 5785 5786 #define SAMPLE_SUFFIX_ITEM 2 5787 5788 /** 5789 * Split the sample flow. 5790 * 5791 * As sample flow will split to two sub flow, sample flow with 5792 * sample action, the other actions will move to new suffix flow. 5793 * 5794 * Also add unique tag id with tag action in the sample flow, 5795 * the same tag id will be as match in the suffix flow. 5796 * 5797 * @param dev 5798 * Pointer to Ethernet device. 5799 * @param[in] add_tag 5800 * Add extra tag action flag. 5801 * @param[out] sfx_items 5802 * Suffix flow match items (list terminated by the END pattern item). 5803 * @param[in] actions 5804 * Associated actions (list terminated by the END action). 5805 * @param[out] actions_sfx 5806 * Suffix flow actions. 5807 * @param[out] actions_pre 5808 * Prefix flow actions. 5809 * @param[in] actions_n 5810 * The total number of actions. 5811 * @param[in] sample_action_pos 5812 * The sample action position. 5813 * @param[in] qrss_action_pos 5814 * The Queue/RSS action position. 5815 * @param[in] jump_table 5816 * Add extra jump action flag. 5817 * @param[out] error 5818 * Perform verbose error reporting if not NULL. 5819 * 5820 * @return 5821 * 0 on success, or unique flow_id, a negative errno value 5822 * otherwise and rte_errno is set. 5823 */ 5824 static int 5825 flow_sample_split_prep(struct rte_eth_dev *dev, 5826 int add_tag, 5827 struct rte_flow_item sfx_items[], 5828 const struct rte_flow_action actions[], 5829 struct rte_flow_action actions_sfx[], 5830 struct rte_flow_action actions_pre[], 5831 int actions_n, 5832 int sample_action_pos, 5833 int qrss_action_pos, 5834 int jump_table, 5835 struct rte_flow_error *error) 5836 { 5837 struct mlx5_priv *priv = dev->data->dev_private; 5838 struct mlx5_rte_flow_action_set_tag *set_tag; 5839 struct mlx5_rte_flow_item_tag *tag_spec; 5840 struct mlx5_rte_flow_item_tag *tag_mask; 5841 struct rte_flow_action_jump *jump_action; 5842 uint32_t tag_id = 0; 5843 int index; 5844 int append_index = 0; 5845 int ret; 5846 5847 if (sample_action_pos < 0) 5848 return rte_flow_error_set(error, EINVAL, 5849 RTE_FLOW_ERROR_TYPE_ACTION, 5850 NULL, "invalid position of sample " 5851 "action in list"); 5852 /* Prepare the actions for prefix and suffix flow. */ 5853 if (qrss_action_pos >= 0 && qrss_action_pos < sample_action_pos) { 5854 index = qrss_action_pos; 5855 /* Put the preceding the Queue/RSS action into prefix flow. */ 5856 if (index != 0) 5857 memcpy(actions_pre, actions, 5858 sizeof(struct rte_flow_action) * index); 5859 /* Put others preceding the sample action into prefix flow. */ 5860 if (sample_action_pos > index + 1) 5861 memcpy(actions_pre + index, actions + index + 1, 5862 sizeof(struct rte_flow_action) * 5863 (sample_action_pos - index - 1)); 5864 index = sample_action_pos - 1; 5865 /* Put Queue/RSS action into Suffix flow. */ 5866 memcpy(actions_sfx, actions + qrss_action_pos, 5867 sizeof(struct rte_flow_action)); 5868 actions_sfx++; 5869 } else { 5870 index = sample_action_pos; 5871 if (index != 0) 5872 memcpy(actions_pre, actions, 5873 sizeof(struct rte_flow_action) * index); 5874 } 5875 /* For CX5, add an extra tag action for NIC-RX and E-Switch ingress. 5876 * For CX6DX and above, metadata registers Cx preserve their value, 5877 * add an extra tag action for NIC-RX and E-Switch Domain. 5878 */ 5879 if (add_tag) { 5880 /* Prepare the prefix tag action. */ 5881 append_index++; 5882 set_tag = (void *)(actions_pre + actions_n + append_index); 5883 ret = mlx5_flow_get_reg_id(dev, MLX5_SAMPLE_ID, 0, error); 5884 /* Trust VF/SF on CX5 not supported meter so that the reserved 5885 * metadata regC is REG_NON, back to use application tag 5886 * index 0. 5887 */ 5888 if (unlikely(ret == REG_NON)) 5889 ret = mlx5_flow_get_reg_id(dev, MLX5_APP_TAG, 0, error); 5890 if (ret < 0) 5891 return ret; 5892 mlx5_ipool_malloc(priv->sh->ipool 5893 [MLX5_IPOOL_RSS_EXPANTION_FLOW_ID], &tag_id); 5894 *set_tag = (struct mlx5_rte_flow_action_set_tag) { 5895 .id = ret, 5896 .data = tag_id, 5897 }; 5898 /* Prepare the suffix subflow items. */ 5899 tag_spec = (void *)(sfx_items + SAMPLE_SUFFIX_ITEM); 5900 tag_spec->data = tag_id; 5901 tag_spec->id = set_tag->id; 5902 tag_mask = tag_spec + 1; 5903 tag_mask->data = UINT32_MAX; 5904 sfx_items[0] = (struct rte_flow_item){ 5905 .type = (enum rte_flow_item_type) 5906 MLX5_RTE_FLOW_ITEM_TYPE_TAG, 5907 .spec = tag_spec, 5908 .last = NULL, 5909 .mask = tag_mask, 5910 }; 5911 sfx_items[1] = (struct rte_flow_item){ 5912 .type = (enum rte_flow_item_type) 5913 RTE_FLOW_ITEM_TYPE_END, 5914 }; 5915 /* Prepare the tag action in prefix subflow. */ 5916 actions_pre[index++] = 5917 (struct rte_flow_action){ 5918 .type = (enum rte_flow_action_type) 5919 MLX5_RTE_FLOW_ACTION_TYPE_TAG, 5920 .conf = set_tag, 5921 }; 5922 } 5923 memcpy(actions_pre + index, actions + sample_action_pos, 5924 sizeof(struct rte_flow_action)); 5925 index += 1; 5926 /* For the modify action after the sample action in E-Switch mirroring, 5927 * Add the extra jump action in prefix subflow and jump into the next 5928 * table, then do the modify action in the new table. 5929 */ 5930 if (jump_table) { 5931 /* Prepare the prefix jump action. */ 5932 append_index++; 5933 jump_action = (void *)(actions_pre + actions_n + append_index); 5934 jump_action->group = jump_table; 5935 actions_pre[index++] = 5936 (struct rte_flow_action){ 5937 .type = (enum rte_flow_action_type) 5938 RTE_FLOW_ACTION_TYPE_JUMP, 5939 .conf = jump_action, 5940 }; 5941 } 5942 actions_pre[index] = (struct rte_flow_action){ 5943 .type = (enum rte_flow_action_type) 5944 RTE_FLOW_ACTION_TYPE_END, 5945 }; 5946 /* Put the actions after sample into Suffix flow. */ 5947 memcpy(actions_sfx, actions + sample_action_pos + 1, 5948 sizeof(struct rte_flow_action) * 5949 (actions_n - sample_action_pos - 1)); 5950 return tag_id; 5951 } 5952 5953 /** 5954 * The splitting for metadata feature. 5955 * 5956 * - Q/RSS action on NIC Rx should be split in order to pass by 5957 * the mreg copy table (RX_CP_TBL) and then it jumps to the 5958 * action table (RX_ACT_TBL) which has the split Q/RSS action. 5959 * 5960 * - All the actions on NIC Tx should have a mreg copy action to 5961 * copy reg_a from WQE to reg_c[0]. 5962 * 5963 * @param dev 5964 * Pointer to Ethernet device. 5965 * @param[in] flow 5966 * Parent flow structure pointer. 5967 * @param[in] attr 5968 * Flow rule attributes. 5969 * @param[in] items 5970 * Pattern specification (list terminated by the END pattern item). 5971 * @param[in] actions 5972 * Associated actions (list terminated by the END action). 5973 * @param[in] flow_split_info 5974 * Pointer to flow split info structure. 5975 * @param[out] error 5976 * Perform verbose error reporting if not NULL. 5977 * @return 5978 * 0 on success, negative value otherwise 5979 */ 5980 static int 5981 flow_create_split_metadata(struct rte_eth_dev *dev, 5982 struct rte_flow *flow, 5983 const struct rte_flow_attr *attr, 5984 const struct rte_flow_item items[], 5985 const struct rte_flow_action actions[], 5986 struct mlx5_flow_split_info *flow_split_info, 5987 struct rte_flow_error *error) 5988 { 5989 struct mlx5_priv *priv = dev->data->dev_private; 5990 struct mlx5_sh_config *config = &priv->sh->config; 5991 const struct rte_flow_action *qrss = NULL; 5992 struct rte_flow_action *ext_actions = NULL; 5993 struct mlx5_flow *dev_flow = NULL; 5994 uint32_t qrss_id = 0; 5995 int mtr_sfx = 0; 5996 size_t act_size; 5997 int actions_n; 5998 int encap_idx; 5999 int ret; 6000 6001 /* Check whether extensive metadata feature is engaged. */ 6002 if (!config->dv_flow_en || 6003 config->dv_xmeta_en == MLX5_XMETA_MODE_LEGACY || 6004 !mlx5_flow_ext_mreg_supported(dev)) 6005 return flow_create_split_inner(dev, flow, NULL, attr, items, 6006 actions, flow_split_info, error); 6007 actions_n = flow_parse_metadata_split_actions_info(actions, &qrss, 6008 &encap_idx); 6009 if (qrss) { 6010 /* Exclude hairpin flows from splitting. */ 6011 if (qrss->type == RTE_FLOW_ACTION_TYPE_QUEUE) { 6012 const struct rte_flow_action_queue *queue; 6013 6014 queue = qrss->conf; 6015 if (mlx5_rxq_is_hairpin(dev, queue->index)) 6016 qrss = NULL; 6017 } else if (qrss->type == RTE_FLOW_ACTION_TYPE_RSS) { 6018 const struct rte_flow_action_rss *rss; 6019 6020 rss = qrss->conf; 6021 if (mlx5_rxq_is_hairpin(dev, rss->queue[0])) 6022 qrss = NULL; 6023 } 6024 } 6025 if (qrss) { 6026 /* Check if it is in meter suffix table. */ 6027 mtr_sfx = attr->group == (attr->transfer ? 6028 (MLX5_FLOW_TABLE_LEVEL_METER - 1) : 6029 MLX5_FLOW_TABLE_LEVEL_METER); 6030 /* 6031 * Q/RSS action on NIC Rx should be split in order to pass by 6032 * the mreg copy table (RX_CP_TBL) and then it jumps to the 6033 * action table (RX_ACT_TBL) which has the split Q/RSS action. 6034 */ 6035 act_size = sizeof(struct rte_flow_action) * (actions_n + 1) + 6036 sizeof(struct rte_flow_action_set_tag) + 6037 sizeof(struct rte_flow_action_jump); 6038 ext_actions = mlx5_malloc(MLX5_MEM_ZERO, act_size, 0, 6039 SOCKET_ID_ANY); 6040 if (!ext_actions) 6041 return rte_flow_error_set(error, ENOMEM, 6042 RTE_FLOW_ERROR_TYPE_ACTION, 6043 NULL, "no memory to split " 6044 "metadata flow"); 6045 /* 6046 * Create the new actions list with removed Q/RSS action 6047 * and appended set tag and jump to register copy table 6048 * (RX_CP_TBL). We should preallocate unique tag ID here 6049 * in advance, because it is needed for set tag action. 6050 */ 6051 qrss_id = flow_mreg_split_qrss_prep(dev, ext_actions, actions, 6052 qrss, actions_n, 6053 mtr_sfx, error); 6054 if (!mtr_sfx && !qrss_id) { 6055 ret = -rte_errno; 6056 goto exit; 6057 } 6058 } else if (attr->egress && !attr->transfer) { 6059 /* 6060 * All the actions on NIC Tx should have a metadata register 6061 * copy action to copy reg_a from WQE to reg_c[meta] 6062 */ 6063 act_size = sizeof(struct rte_flow_action) * (actions_n + 1) + 6064 sizeof(struct mlx5_flow_action_copy_mreg); 6065 ext_actions = mlx5_malloc(MLX5_MEM_ZERO, act_size, 0, 6066 SOCKET_ID_ANY); 6067 if (!ext_actions) 6068 return rte_flow_error_set(error, ENOMEM, 6069 RTE_FLOW_ERROR_TYPE_ACTION, 6070 NULL, "no memory to split " 6071 "metadata flow"); 6072 /* Create the action list appended with copy register. */ 6073 ret = flow_mreg_tx_copy_prep(dev, ext_actions, actions, 6074 actions_n, error, encap_idx); 6075 if (ret < 0) 6076 goto exit; 6077 } 6078 /* Add the unmodified original or prefix subflow. */ 6079 ret = flow_create_split_inner(dev, flow, &dev_flow, attr, 6080 items, ext_actions ? ext_actions : 6081 actions, flow_split_info, error); 6082 if (ret < 0) 6083 goto exit; 6084 MLX5_ASSERT(dev_flow); 6085 if (qrss) { 6086 const struct rte_flow_attr q_attr = { 6087 .group = MLX5_FLOW_MREG_ACT_TABLE_GROUP, 6088 .ingress = 1, 6089 }; 6090 /* Internal PMD action to set register. */ 6091 struct mlx5_rte_flow_item_tag q_tag_spec = { 6092 .data = qrss_id, 6093 .id = REG_NON, 6094 }; 6095 struct rte_flow_item q_items[] = { 6096 { 6097 .type = (enum rte_flow_item_type) 6098 MLX5_RTE_FLOW_ITEM_TYPE_TAG, 6099 .spec = &q_tag_spec, 6100 .last = NULL, 6101 .mask = NULL, 6102 }, 6103 { 6104 .type = RTE_FLOW_ITEM_TYPE_END, 6105 }, 6106 }; 6107 struct rte_flow_action q_actions[] = { 6108 { 6109 .type = qrss->type, 6110 .conf = qrss->conf, 6111 }, 6112 { 6113 .type = RTE_FLOW_ACTION_TYPE_END, 6114 }, 6115 }; 6116 uint64_t layers = flow_get_prefix_layer_flags(dev_flow); 6117 6118 /* 6119 * Configure the tag item only if there is no meter subflow. 6120 * Since tag is already marked in the meter suffix subflow 6121 * we can just use the meter suffix items as is. 6122 */ 6123 if (qrss_id) { 6124 /* Not meter subflow. */ 6125 MLX5_ASSERT(!mtr_sfx); 6126 /* 6127 * Put unique id in prefix flow due to it is destroyed 6128 * after suffix flow and id will be freed after there 6129 * is no actual flows with this id and identifier 6130 * reallocation becomes possible (for example, for 6131 * other flows in other threads). 6132 */ 6133 dev_flow->handle->split_flow_id = qrss_id; 6134 ret = mlx5_flow_get_reg_id(dev, MLX5_COPY_MARK, 0, 6135 error); 6136 if (ret < 0) 6137 goto exit; 6138 q_tag_spec.id = ret; 6139 } 6140 dev_flow = NULL; 6141 /* Add suffix subflow to execute Q/RSS. */ 6142 flow_split_info->prefix_layers = layers; 6143 flow_split_info->prefix_mark = 0; 6144 flow_split_info->table_id = 0; 6145 ret = flow_create_split_inner(dev, flow, &dev_flow, 6146 &q_attr, mtr_sfx ? items : 6147 q_items, q_actions, 6148 flow_split_info, error); 6149 if (ret < 0) 6150 goto exit; 6151 /* qrss ID should be freed if failed. */ 6152 qrss_id = 0; 6153 MLX5_ASSERT(dev_flow); 6154 } 6155 6156 exit: 6157 /* 6158 * We do not destroy the partially created sub_flows in case of error. 6159 * These ones are included into parent flow list and will be destroyed 6160 * by flow_drv_destroy. 6161 */ 6162 mlx5_ipool_free(priv->sh->ipool[MLX5_IPOOL_RSS_EXPANTION_FLOW_ID], 6163 qrss_id); 6164 mlx5_free(ext_actions); 6165 return ret; 6166 } 6167 6168 /** 6169 * Create meter internal drop flow with the original pattern. 6170 * 6171 * @param dev 6172 * Pointer to Ethernet device. 6173 * @param[in] flow 6174 * Parent flow structure pointer. 6175 * @param[in] attr 6176 * Flow rule attributes. 6177 * @param[in] items 6178 * Pattern specification (list terminated by the END pattern item). 6179 * @param[in] flow_split_info 6180 * Pointer to flow split info structure. 6181 * @param[in] fm 6182 * Pointer to flow meter structure. 6183 * @param[out] error 6184 * Perform verbose error reporting if not NULL. 6185 * @return 6186 * 0 on success, negative value otherwise 6187 */ 6188 static uint32_t 6189 flow_meter_create_drop_flow_with_org_pattern(struct rte_eth_dev *dev, 6190 struct rte_flow *flow, 6191 const struct rte_flow_attr *attr, 6192 const struct rte_flow_item items[], 6193 struct mlx5_flow_split_info *flow_split_info, 6194 struct mlx5_flow_meter_info *fm, 6195 struct rte_flow_error *error) 6196 { 6197 struct mlx5_flow *dev_flow = NULL; 6198 struct rte_flow_attr drop_attr = *attr; 6199 struct rte_flow_action drop_actions[3]; 6200 struct mlx5_flow_split_info drop_split_info = *flow_split_info; 6201 6202 MLX5_ASSERT(fm->drop_cnt); 6203 drop_actions[0].type = 6204 (enum rte_flow_action_type)MLX5_RTE_FLOW_ACTION_TYPE_COUNT; 6205 drop_actions[0].conf = (void *)(uintptr_t)fm->drop_cnt; 6206 drop_actions[1].type = RTE_FLOW_ACTION_TYPE_DROP; 6207 drop_actions[1].conf = NULL; 6208 drop_actions[2].type = RTE_FLOW_ACTION_TYPE_END; 6209 drop_actions[2].conf = NULL; 6210 drop_split_info.external = false; 6211 drop_split_info.skip_scale |= 1 << MLX5_SCALE_FLOW_GROUP_BIT; 6212 drop_split_info.table_id = MLX5_MTR_TABLE_ID_DROP; 6213 drop_attr.group = MLX5_FLOW_TABLE_LEVEL_METER; 6214 return flow_create_split_inner(dev, flow, &dev_flow, 6215 &drop_attr, items, drop_actions, 6216 &drop_split_info, error); 6217 } 6218 6219 /** 6220 * The splitting for meter feature. 6221 * 6222 * - The meter flow will be split to two flows as prefix and 6223 * suffix flow. The packets make sense only it pass the prefix 6224 * meter action. 6225 * 6226 * - Reg_C_5 is used for the packet to match betweend prefix and 6227 * suffix flow. 6228 * 6229 * @param dev 6230 * Pointer to Ethernet device. 6231 * @param[in] flow 6232 * Parent flow structure pointer. 6233 * @param[in] attr 6234 * Flow rule attributes. 6235 * @param[in] items 6236 * Pattern specification (list terminated by the END pattern item). 6237 * @param[in] actions 6238 * Associated actions (list terminated by the END action). 6239 * @param[in] flow_split_info 6240 * Pointer to flow split info structure. 6241 * @param[out] error 6242 * Perform verbose error reporting if not NULL. 6243 * @return 6244 * 0 on success, negative value otherwise 6245 */ 6246 static int 6247 flow_create_split_meter(struct rte_eth_dev *dev, 6248 struct rte_flow *flow, 6249 const struct rte_flow_attr *attr, 6250 const struct rte_flow_item items[], 6251 const struct rte_flow_action actions[], 6252 struct mlx5_flow_split_info *flow_split_info, 6253 struct rte_flow_error *error) 6254 { 6255 struct mlx5_priv *priv = dev->data->dev_private; 6256 struct mlx5_flow_workspace *wks = mlx5_flow_get_thread_workspace(); 6257 struct rte_flow_action *sfx_actions = NULL; 6258 struct rte_flow_action *pre_actions = NULL; 6259 struct rte_flow_item *sfx_items = NULL; 6260 struct mlx5_flow *dev_flow = NULL; 6261 struct rte_flow_attr sfx_attr = *attr; 6262 struct mlx5_flow_meter_info *fm = NULL; 6263 uint8_t skip_scale_restore; 6264 bool has_mtr = false; 6265 bool has_modify = false; 6266 bool set_mtr_reg = true; 6267 bool is_mtr_hierarchy = false; 6268 uint32_t meter_id = 0; 6269 uint32_t mtr_idx = 0; 6270 uint32_t mtr_flow_id = 0; 6271 size_t act_size; 6272 size_t item_size; 6273 int actions_n = 0; 6274 int ret = 0; 6275 6276 if (priv->mtr_en) 6277 actions_n = flow_check_meter_action(dev, actions, &has_mtr, 6278 &has_modify, &meter_id); 6279 if (has_mtr) { 6280 if (flow->meter) { 6281 fm = flow_dv_meter_find_by_idx(priv, flow->meter); 6282 if (!fm) 6283 return rte_flow_error_set(error, EINVAL, 6284 RTE_FLOW_ERROR_TYPE_UNSPECIFIED, 6285 NULL, "Meter not found."); 6286 } else { 6287 fm = mlx5_flow_meter_find(priv, meter_id, &mtr_idx); 6288 if (!fm) 6289 return rte_flow_error_set(error, EINVAL, 6290 RTE_FLOW_ERROR_TYPE_UNSPECIFIED, 6291 NULL, "Meter not found."); 6292 ret = mlx5_flow_meter_attach(priv, fm, 6293 &sfx_attr, error); 6294 if (ret) 6295 return -rte_errno; 6296 flow->meter = mtr_idx; 6297 } 6298 MLX5_ASSERT(wks); 6299 wks->fm = fm; 6300 if (!fm->def_policy) { 6301 wks->policy = mlx5_flow_meter_policy_find(dev, 6302 fm->policy_id, 6303 NULL); 6304 MLX5_ASSERT(wks->policy); 6305 if (wks->policy->mark) 6306 wks->mark = 1; 6307 if (wks->policy->is_hierarchy) { 6308 wks->final_policy = 6309 mlx5_flow_meter_hierarchy_get_final_policy(dev, 6310 wks->policy); 6311 if (!wks->final_policy) 6312 return rte_flow_error_set(error, 6313 EINVAL, 6314 RTE_FLOW_ERROR_TYPE_ACTION, NULL, 6315 "Failed to find terminal policy of hierarchy."); 6316 is_mtr_hierarchy = true; 6317 } 6318 } 6319 /* 6320 * If it isn't default-policy Meter, and 6321 * 1. There's no action in flow to change 6322 * packet (modify/encap/decap etc.), OR 6323 * 2. No drop count needed for this meter. 6324 * 3. It's not meter hierarchy. 6325 * Then no need to use regC to save meter id anymore. 6326 */ 6327 if (!fm->def_policy && !is_mtr_hierarchy && 6328 (!has_modify || !fm->drop_cnt)) 6329 set_mtr_reg = false; 6330 /* Prefix actions: meter, decap, encap, tag, jump, end. */ 6331 act_size = sizeof(struct rte_flow_action) * (actions_n + 6) + 6332 sizeof(struct mlx5_rte_flow_action_set_tag); 6333 /* Suffix items: tag, vlan, port id, end. */ 6334 #define METER_SUFFIX_ITEM 4 6335 item_size = sizeof(struct rte_flow_item) * METER_SUFFIX_ITEM + 6336 sizeof(struct mlx5_rte_flow_item_tag) * 2; 6337 sfx_actions = mlx5_malloc(MLX5_MEM_ZERO, (act_size + item_size), 6338 0, SOCKET_ID_ANY); 6339 if (!sfx_actions) 6340 return rte_flow_error_set(error, ENOMEM, 6341 RTE_FLOW_ERROR_TYPE_ACTION, 6342 NULL, "no memory to split " 6343 "meter flow"); 6344 sfx_items = (struct rte_flow_item *)((char *)sfx_actions + 6345 act_size); 6346 /* There's no suffix flow for meter of non-default policy. */ 6347 if (!fm->def_policy) 6348 pre_actions = sfx_actions + 1; 6349 else 6350 pre_actions = sfx_actions + actions_n; 6351 ret = flow_meter_split_prep(dev, flow, wks, &sfx_attr, 6352 items, sfx_items, actions, 6353 sfx_actions, pre_actions, 6354 (set_mtr_reg ? &mtr_flow_id : NULL), 6355 error); 6356 if (ret) { 6357 ret = -rte_errno; 6358 goto exit; 6359 } 6360 /* Add the prefix subflow. */ 6361 skip_scale_restore = flow_split_info->skip_scale; 6362 flow_split_info->skip_scale |= 6363 1 << MLX5_SCALE_JUMP_FLOW_GROUP_BIT; 6364 ret = flow_create_split_inner(dev, flow, &dev_flow, 6365 attr, items, pre_actions, 6366 flow_split_info, error); 6367 flow_split_info->skip_scale = skip_scale_restore; 6368 if (ret) { 6369 if (mtr_flow_id) 6370 mlx5_ipool_free(fm->flow_ipool, mtr_flow_id); 6371 ret = -rte_errno; 6372 goto exit; 6373 } 6374 if (mtr_flow_id) { 6375 dev_flow->handle->split_flow_id = mtr_flow_id; 6376 dev_flow->handle->is_meter_flow_id = 1; 6377 } 6378 if (!fm->def_policy) { 6379 if (!set_mtr_reg && fm->drop_cnt) 6380 ret = 6381 flow_meter_create_drop_flow_with_org_pattern(dev, flow, 6382 &sfx_attr, items, 6383 flow_split_info, 6384 fm, error); 6385 goto exit; 6386 } 6387 /* Setting the sfx group atrr. */ 6388 sfx_attr.group = sfx_attr.transfer ? 6389 (MLX5_FLOW_TABLE_LEVEL_METER - 1) : 6390 MLX5_FLOW_TABLE_LEVEL_METER; 6391 flow_split_info->prefix_layers = 6392 flow_get_prefix_layer_flags(dev_flow); 6393 flow_split_info->prefix_mark |= wks->mark; 6394 flow_split_info->table_id = MLX5_MTR_TABLE_ID_SUFFIX; 6395 } 6396 /* Add the prefix subflow. */ 6397 ret = flow_create_split_metadata(dev, flow, 6398 &sfx_attr, sfx_items ? 6399 sfx_items : items, 6400 sfx_actions ? sfx_actions : actions, 6401 flow_split_info, error); 6402 exit: 6403 if (sfx_actions) 6404 mlx5_free(sfx_actions); 6405 return ret; 6406 } 6407 6408 /** 6409 * The splitting for sample feature. 6410 * 6411 * Once Sample action is detected in the action list, the flow actions should 6412 * be split into prefix sub flow and suffix sub flow. 6413 * 6414 * The original items remain in the prefix sub flow, all actions preceding the 6415 * sample action and the sample action itself will be copied to the prefix 6416 * sub flow, the actions following the sample action will be copied to the 6417 * suffix sub flow, Queue action always be located in the suffix sub flow. 6418 * 6419 * In order to make the packet from prefix sub flow matches with suffix sub 6420 * flow, an extra tag action be added into prefix sub flow, and the suffix sub 6421 * flow uses tag item with the unique flow id. 6422 * 6423 * @param dev 6424 * Pointer to Ethernet device. 6425 * @param[in] flow 6426 * Parent flow structure pointer. 6427 * @param[in] attr 6428 * Flow rule attributes. 6429 * @param[in] items 6430 * Pattern specification (list terminated by the END pattern item). 6431 * @param[in] actions 6432 * Associated actions (list terminated by the END action). 6433 * @param[in] flow_split_info 6434 * Pointer to flow split info structure. 6435 * @param[out] error 6436 * Perform verbose error reporting if not NULL. 6437 * @return 6438 * 0 on success, negative value otherwise 6439 */ 6440 static int 6441 flow_create_split_sample(struct rte_eth_dev *dev, 6442 struct rte_flow *flow, 6443 const struct rte_flow_attr *attr, 6444 const struct rte_flow_item items[], 6445 const struct rte_flow_action actions[], 6446 struct mlx5_flow_split_info *flow_split_info, 6447 struct rte_flow_error *error) 6448 { 6449 struct mlx5_priv *priv = dev->data->dev_private; 6450 struct rte_flow_action *sfx_actions = NULL; 6451 struct rte_flow_action *pre_actions = NULL; 6452 struct rte_flow_item *sfx_items = NULL; 6453 struct mlx5_flow *dev_flow = NULL; 6454 struct rte_flow_attr sfx_attr = *attr; 6455 #ifdef HAVE_IBV_FLOW_DV_SUPPORT 6456 struct mlx5_flow_dv_sample_resource *sample_res; 6457 struct mlx5_flow_tbl_data_entry *sfx_tbl_data; 6458 struct mlx5_flow_tbl_resource *sfx_tbl; 6459 struct mlx5_flow_workspace *wks = mlx5_flow_get_thread_workspace(); 6460 #endif 6461 size_t act_size; 6462 size_t item_size; 6463 uint32_t fdb_tx = 0; 6464 int32_t tag_id = 0; 6465 int actions_n = 0; 6466 int sample_action_pos; 6467 int qrss_action_pos; 6468 int add_tag = 0; 6469 int modify_after_mirror = 0; 6470 uint16_t jump_table = 0; 6471 const uint32_t next_ft_step = 1; 6472 int ret = 0; 6473 6474 if (priv->sampler_en) 6475 actions_n = flow_check_match_action(actions, attr, 6476 RTE_FLOW_ACTION_TYPE_SAMPLE, 6477 &sample_action_pos, &qrss_action_pos, 6478 &modify_after_mirror); 6479 if (actions_n) { 6480 /* The prefix actions must includes sample, tag, end. */ 6481 act_size = sizeof(struct rte_flow_action) * (actions_n * 2 + 1) 6482 + sizeof(struct mlx5_rte_flow_action_set_tag); 6483 item_size = sizeof(struct rte_flow_item) * SAMPLE_SUFFIX_ITEM + 6484 sizeof(struct mlx5_rte_flow_item_tag) * 2; 6485 sfx_actions = mlx5_malloc(MLX5_MEM_ZERO, (act_size + 6486 item_size), 0, SOCKET_ID_ANY); 6487 if (!sfx_actions) 6488 return rte_flow_error_set(error, ENOMEM, 6489 RTE_FLOW_ERROR_TYPE_ACTION, 6490 NULL, "no memory to split " 6491 "sample flow"); 6492 /* The representor_id is UINT16_MAX for uplink. */ 6493 fdb_tx = (attr->transfer && priv->representor_id != UINT16_MAX); 6494 /* 6495 * When reg_c_preserve is set, metadata registers Cx preserve 6496 * their value even through packet duplication. 6497 */ 6498 add_tag = (!fdb_tx || 6499 priv->sh->cdev->config.hca_attr.reg_c_preserve); 6500 if (add_tag) 6501 sfx_items = (struct rte_flow_item *)((char *)sfx_actions 6502 + act_size); 6503 if (modify_after_mirror) 6504 jump_table = attr->group * MLX5_FLOW_TABLE_FACTOR + 6505 next_ft_step; 6506 pre_actions = sfx_actions + actions_n; 6507 tag_id = flow_sample_split_prep(dev, add_tag, sfx_items, 6508 actions, sfx_actions, 6509 pre_actions, actions_n, 6510 sample_action_pos, 6511 qrss_action_pos, jump_table, 6512 error); 6513 if (tag_id < 0 || (add_tag && !tag_id)) { 6514 ret = -rte_errno; 6515 goto exit; 6516 } 6517 if (modify_after_mirror) 6518 flow_split_info->skip_scale = 6519 1 << MLX5_SCALE_JUMP_FLOW_GROUP_BIT; 6520 /* Add the prefix subflow. */ 6521 ret = flow_create_split_inner(dev, flow, &dev_flow, attr, 6522 items, pre_actions, 6523 flow_split_info, error); 6524 if (ret) { 6525 ret = -rte_errno; 6526 goto exit; 6527 } 6528 dev_flow->handle->split_flow_id = tag_id; 6529 #ifdef HAVE_IBV_FLOW_DV_SUPPORT 6530 if (!modify_after_mirror) { 6531 /* Set the sfx group attr. */ 6532 sample_res = (struct mlx5_flow_dv_sample_resource *) 6533 dev_flow->dv.sample_res; 6534 sfx_tbl = (struct mlx5_flow_tbl_resource *) 6535 sample_res->normal_path_tbl; 6536 sfx_tbl_data = container_of(sfx_tbl, 6537 struct mlx5_flow_tbl_data_entry, 6538 tbl); 6539 sfx_attr.group = sfx_attr.transfer ? 6540 (sfx_tbl_data->level - 1) : sfx_tbl_data->level; 6541 } else { 6542 MLX5_ASSERT(attr->transfer); 6543 sfx_attr.group = jump_table; 6544 } 6545 flow_split_info->prefix_layers = 6546 flow_get_prefix_layer_flags(dev_flow); 6547 MLX5_ASSERT(wks); 6548 flow_split_info->prefix_mark |= wks->mark; 6549 /* Suffix group level already be scaled with factor, set 6550 * MLX5_SCALE_FLOW_GROUP_BIT of skip_scale to 1 to avoid scale 6551 * again in translation. 6552 */ 6553 flow_split_info->skip_scale = 1 << MLX5_SCALE_FLOW_GROUP_BIT; 6554 #endif 6555 } 6556 /* Add the suffix subflow. */ 6557 ret = flow_create_split_meter(dev, flow, &sfx_attr, 6558 sfx_items ? sfx_items : items, 6559 sfx_actions ? sfx_actions : actions, 6560 flow_split_info, error); 6561 exit: 6562 if (sfx_actions) 6563 mlx5_free(sfx_actions); 6564 return ret; 6565 } 6566 6567 /** 6568 * Split the flow to subflow set. The splitters might be linked 6569 * in the chain, like this: 6570 * flow_create_split_outer() calls: 6571 * flow_create_split_meter() calls: 6572 * flow_create_split_metadata(meter_subflow_0) calls: 6573 * flow_create_split_inner(metadata_subflow_0) 6574 * flow_create_split_inner(metadata_subflow_1) 6575 * flow_create_split_inner(metadata_subflow_2) 6576 * flow_create_split_metadata(meter_subflow_1) calls: 6577 * flow_create_split_inner(metadata_subflow_0) 6578 * flow_create_split_inner(metadata_subflow_1) 6579 * flow_create_split_inner(metadata_subflow_2) 6580 * 6581 * This provide flexible way to add new levels of flow splitting. 6582 * The all of successfully created subflows are included to the 6583 * parent flow dev_flow list. 6584 * 6585 * @param dev 6586 * Pointer to Ethernet device. 6587 * @param[in] flow 6588 * Parent flow structure pointer. 6589 * @param[in] attr 6590 * Flow rule attributes. 6591 * @param[in] items 6592 * Pattern specification (list terminated by the END pattern item). 6593 * @param[in] actions 6594 * Associated actions (list terminated by the END action). 6595 * @param[in] flow_split_info 6596 * Pointer to flow split info structure. 6597 * @param[out] error 6598 * Perform verbose error reporting if not NULL. 6599 * @return 6600 * 0 on success, negative value otherwise 6601 */ 6602 static int 6603 flow_create_split_outer(struct rte_eth_dev *dev, 6604 struct rte_flow *flow, 6605 const struct rte_flow_attr *attr, 6606 const struct rte_flow_item items[], 6607 const struct rte_flow_action actions[], 6608 struct mlx5_flow_split_info *flow_split_info, 6609 struct rte_flow_error *error) 6610 { 6611 int ret; 6612 6613 ret = flow_create_split_sample(dev, flow, attr, items, 6614 actions, flow_split_info, error); 6615 MLX5_ASSERT(ret <= 0); 6616 return ret; 6617 } 6618 6619 static inline struct mlx5_flow_tunnel * 6620 flow_tunnel_from_rule(const struct mlx5_flow *flow) 6621 { 6622 struct mlx5_flow_tunnel *tunnel; 6623 6624 #pragma GCC diagnostic push 6625 #pragma GCC diagnostic ignored "-Wcast-qual" 6626 tunnel = (typeof(tunnel))flow->tunnel; 6627 #pragma GCC diagnostic pop 6628 6629 return tunnel; 6630 } 6631 6632 /** 6633 * Adjust flow RSS workspace if needed. 6634 * 6635 * @param wks 6636 * Pointer to thread flow work space. 6637 * @param rss_desc 6638 * Pointer to RSS descriptor. 6639 * @param[in] nrssq_num 6640 * New RSS queue number. 6641 * 6642 * @return 6643 * 0 on success, -1 otherwise and rte_errno is set. 6644 */ 6645 static int 6646 flow_rss_workspace_adjust(struct mlx5_flow_workspace *wks, 6647 struct mlx5_flow_rss_desc *rss_desc, 6648 uint32_t nrssq_num) 6649 { 6650 if (likely(nrssq_num <= wks->rssq_num)) 6651 return 0; 6652 rss_desc->queue = realloc(rss_desc->queue, 6653 sizeof(*rss_desc->queue) * RTE_ALIGN(nrssq_num, 2)); 6654 if (!rss_desc->queue) { 6655 rte_errno = ENOMEM; 6656 return -1; 6657 } 6658 wks->rssq_num = RTE_ALIGN(nrssq_num, 2); 6659 return 0; 6660 } 6661 6662 /** 6663 * Create a flow and add it to @p list. 6664 * 6665 * @param dev 6666 * Pointer to Ethernet device. 6667 * @param list 6668 * Pointer to a TAILQ flow list. If this parameter NULL, 6669 * no list insertion occurred, flow is just created, 6670 * this is caller's responsibility to track the 6671 * created flow. 6672 * @param[in] attr 6673 * Flow rule attributes. 6674 * @param[in] items 6675 * Pattern specification (list terminated by the END pattern item). 6676 * @param[in] actions 6677 * Associated actions (list terminated by the END action). 6678 * @param[in] external 6679 * This flow rule is created by request external to PMD. 6680 * @param[out] error 6681 * Perform verbose error reporting if not NULL. 6682 * 6683 * @return 6684 * A flow index on success, 0 otherwise and rte_errno is set. 6685 */ 6686 static uint32_t 6687 flow_list_create(struct rte_eth_dev *dev, enum mlx5_flow_type type, 6688 const struct rte_flow_attr *attr, 6689 const struct rte_flow_item items[], 6690 const struct rte_flow_action original_actions[], 6691 bool external, struct rte_flow_error *error) 6692 { 6693 struct mlx5_priv *priv = dev->data->dev_private; 6694 struct rte_flow *flow = NULL; 6695 struct mlx5_flow *dev_flow; 6696 const struct rte_flow_action_rss *rss = NULL; 6697 struct mlx5_translated_action_handle 6698 indir_actions[MLX5_MAX_INDIRECT_ACTIONS]; 6699 int indir_actions_n = MLX5_MAX_INDIRECT_ACTIONS; 6700 union { 6701 struct mlx5_flow_expand_rss buf; 6702 uint8_t buffer[4096]; 6703 } expand_buffer; 6704 union { 6705 struct rte_flow_action actions[MLX5_MAX_SPLIT_ACTIONS]; 6706 uint8_t buffer[2048]; 6707 } actions_rx; 6708 union { 6709 struct rte_flow_action actions[MLX5_MAX_SPLIT_ACTIONS]; 6710 uint8_t buffer[2048]; 6711 } actions_hairpin_tx; 6712 union { 6713 struct rte_flow_item items[MLX5_MAX_SPLIT_ITEMS]; 6714 uint8_t buffer[2048]; 6715 } items_tx; 6716 struct mlx5_flow_expand_rss *buf = &expand_buffer.buf; 6717 struct mlx5_flow_rss_desc *rss_desc; 6718 const struct rte_flow_action *p_actions_rx; 6719 uint32_t i; 6720 uint32_t idx = 0; 6721 int hairpin_flow; 6722 struct rte_flow_attr attr_tx = { .priority = 0 }; 6723 const struct rte_flow_action *actions; 6724 struct rte_flow_action *translated_actions = NULL; 6725 struct mlx5_flow_tunnel *tunnel; 6726 struct tunnel_default_miss_ctx default_miss_ctx = { 0, }; 6727 struct mlx5_flow_workspace *wks = mlx5_flow_push_thread_workspace(); 6728 struct mlx5_flow_split_info flow_split_info = { 6729 .external = !!external, 6730 .skip_scale = 0, 6731 .flow_idx = 0, 6732 .prefix_mark = 0, 6733 .prefix_layers = 0, 6734 .table_id = 0 6735 }; 6736 int ret; 6737 6738 MLX5_ASSERT(wks); 6739 rss_desc = &wks->rss_desc; 6740 ret = flow_action_handles_translate(dev, original_actions, 6741 indir_actions, 6742 &indir_actions_n, 6743 &translated_actions, error); 6744 if (ret < 0) { 6745 MLX5_ASSERT(translated_actions == NULL); 6746 return 0; 6747 } 6748 actions = translated_actions ? translated_actions : original_actions; 6749 p_actions_rx = actions; 6750 hairpin_flow = flow_check_hairpin_split(dev, attr, actions); 6751 ret = flow_drv_validate(dev, attr, items, p_actions_rx, 6752 external, hairpin_flow, error); 6753 if (ret < 0) 6754 goto error_before_hairpin_split; 6755 flow = mlx5_ipool_zmalloc(priv->flows[type], &idx); 6756 if (!flow) { 6757 rte_errno = ENOMEM; 6758 goto error_before_hairpin_split; 6759 } 6760 if (hairpin_flow > 0) { 6761 if (hairpin_flow > MLX5_MAX_SPLIT_ACTIONS) { 6762 rte_errno = EINVAL; 6763 goto error_before_hairpin_split; 6764 } 6765 flow_hairpin_split(dev, actions, actions_rx.actions, 6766 actions_hairpin_tx.actions, items_tx.items, 6767 idx); 6768 p_actions_rx = actions_rx.actions; 6769 } 6770 flow_split_info.flow_idx = idx; 6771 flow->drv_type = flow_get_drv_type(dev, attr); 6772 MLX5_ASSERT(flow->drv_type > MLX5_FLOW_TYPE_MIN && 6773 flow->drv_type < MLX5_FLOW_TYPE_MAX); 6774 memset(rss_desc, 0, offsetof(struct mlx5_flow_rss_desc, queue)); 6775 /* RSS Action only works on NIC RX domain */ 6776 if (attr->ingress && !attr->transfer) 6777 rss = flow_get_rss_action(dev, p_actions_rx); 6778 if (rss) { 6779 if (flow_rss_workspace_adjust(wks, rss_desc, rss->queue_num)) 6780 return 0; 6781 /* 6782 * The following information is required by 6783 * mlx5_flow_hashfields_adjust() in advance. 6784 */ 6785 rss_desc->level = rss->level; 6786 /* RSS type 0 indicates default RSS type (RTE_ETH_RSS_IP). */ 6787 rss_desc->types = !rss->types ? RTE_ETH_RSS_IP : rss->types; 6788 } 6789 flow->dev_handles = 0; 6790 if (rss && rss->types) { 6791 unsigned int graph_root; 6792 6793 graph_root = find_graph_root(rss->level); 6794 ret = mlx5_flow_expand_rss(buf, sizeof(expand_buffer.buffer), 6795 items, rss->types, 6796 mlx5_support_expansion, graph_root); 6797 MLX5_ASSERT(ret > 0 && 6798 (unsigned int)ret < sizeof(expand_buffer.buffer)); 6799 if (rte_log_can_log(mlx5_logtype, RTE_LOG_DEBUG)) { 6800 for (i = 0; i < buf->entries; ++i) 6801 mlx5_dbg__print_pattern(buf->entry[i].pattern); 6802 } 6803 } else { 6804 buf->entries = 1; 6805 buf->entry[0].pattern = (void *)(uintptr_t)items; 6806 } 6807 rss_desc->shared_rss = flow_get_shared_rss_action(dev, indir_actions, 6808 indir_actions_n); 6809 for (i = 0; i < buf->entries; ++i) { 6810 /* Initialize flow split data. */ 6811 flow_split_info.prefix_layers = 0; 6812 flow_split_info.prefix_mark = 0; 6813 flow_split_info.skip_scale = 0; 6814 /* 6815 * The splitter may create multiple dev_flows, 6816 * depending on configuration. In the simplest 6817 * case it just creates unmodified original flow. 6818 */ 6819 ret = flow_create_split_outer(dev, flow, attr, 6820 buf->entry[i].pattern, 6821 p_actions_rx, &flow_split_info, 6822 error); 6823 if (ret < 0) 6824 goto error; 6825 if (is_flow_tunnel_steer_rule(wks->flows[0].tof_type)) { 6826 ret = flow_tunnel_add_default_miss(dev, flow, attr, 6827 p_actions_rx, 6828 idx, 6829 wks->flows[0].tunnel, 6830 &default_miss_ctx, 6831 error); 6832 if (ret < 0) { 6833 mlx5_free(default_miss_ctx.queue); 6834 goto error; 6835 } 6836 } 6837 } 6838 /* Create the tx flow. */ 6839 if (hairpin_flow) { 6840 attr_tx.group = MLX5_HAIRPIN_TX_TABLE; 6841 attr_tx.ingress = 0; 6842 attr_tx.egress = 1; 6843 dev_flow = flow_drv_prepare(dev, flow, &attr_tx, items_tx.items, 6844 actions_hairpin_tx.actions, 6845 idx, error); 6846 if (!dev_flow) 6847 goto error; 6848 dev_flow->flow = flow; 6849 dev_flow->external = 0; 6850 SILIST_INSERT(&flow->dev_handles, dev_flow->handle_idx, 6851 dev_flow->handle, next); 6852 ret = flow_drv_translate(dev, dev_flow, &attr_tx, 6853 items_tx.items, 6854 actions_hairpin_tx.actions, error); 6855 if (ret < 0) 6856 goto error; 6857 } 6858 /* 6859 * Update the metadata register copy table. If extensive 6860 * metadata feature is enabled and registers are supported 6861 * we might create the extra rte_flow for each unique 6862 * MARK/FLAG action ID. 6863 * 6864 * The table is updated for ingress Flows only, because 6865 * the egress Flows belong to the different device and 6866 * copy table should be updated in peer NIC Rx domain. 6867 */ 6868 if (attr->ingress && 6869 (external || attr->group != MLX5_FLOW_MREG_CP_TABLE_GROUP)) { 6870 ret = flow_mreg_update_copy_table(dev, flow, actions, error); 6871 if (ret) 6872 goto error; 6873 } 6874 /* 6875 * If the flow is external (from application) OR device is started, 6876 * OR mreg discover, then apply immediately. 6877 */ 6878 if (external || dev->data->dev_started || 6879 (attr->group == MLX5_FLOW_MREG_CP_TABLE_GROUP && 6880 attr->priority == MLX5_FLOW_LOWEST_PRIO_INDICATOR)) { 6881 ret = flow_drv_apply(dev, flow, error); 6882 if (ret < 0) 6883 goto error; 6884 } 6885 flow->type = type; 6886 flow_rxq_flags_set(dev, flow); 6887 rte_free(translated_actions); 6888 tunnel = flow_tunnel_from_rule(wks->flows); 6889 if (tunnel) { 6890 flow->tunnel = 1; 6891 flow->tunnel_id = tunnel->tunnel_id; 6892 __atomic_add_fetch(&tunnel->refctn, 1, __ATOMIC_RELAXED); 6893 mlx5_free(default_miss_ctx.queue); 6894 } 6895 mlx5_flow_pop_thread_workspace(); 6896 return idx; 6897 error: 6898 MLX5_ASSERT(flow); 6899 ret = rte_errno; /* Save rte_errno before cleanup. */ 6900 flow_mreg_del_copy_action(dev, flow); 6901 flow_drv_destroy(dev, flow); 6902 if (rss_desc->shared_rss) 6903 __atomic_sub_fetch(&((struct mlx5_shared_action_rss *) 6904 mlx5_ipool_get 6905 (priv->sh->ipool[MLX5_IPOOL_RSS_SHARED_ACTIONS], 6906 rss_desc->shared_rss))->refcnt, 1, __ATOMIC_RELAXED); 6907 mlx5_ipool_free(priv->flows[type], idx); 6908 rte_errno = ret; /* Restore rte_errno. */ 6909 ret = rte_errno; 6910 rte_errno = ret; 6911 mlx5_flow_pop_thread_workspace(); 6912 error_before_hairpin_split: 6913 rte_free(translated_actions); 6914 return 0; 6915 } 6916 6917 /** 6918 * Create a dedicated flow rule on e-switch table 0 (root table), to direct all 6919 * incoming packets to table 1. 6920 * 6921 * Other flow rules, requested for group n, will be created in 6922 * e-switch table n+1. 6923 * Jump action to e-switch group n will be created to group n+1. 6924 * 6925 * Used when working in switchdev mode, to utilise advantages of table 1 6926 * and above. 6927 * 6928 * @param dev 6929 * Pointer to Ethernet device. 6930 * 6931 * @return 6932 * Pointer to flow on success, NULL otherwise and rte_errno is set. 6933 */ 6934 struct rte_flow * 6935 mlx5_flow_create_esw_table_zero_flow(struct rte_eth_dev *dev) 6936 { 6937 const struct rte_flow_attr attr = { 6938 .group = 0, 6939 .priority = 0, 6940 .ingress = 1, 6941 .egress = 0, 6942 .transfer = 1, 6943 }; 6944 const struct rte_flow_item pattern = { 6945 .type = RTE_FLOW_ITEM_TYPE_END, 6946 }; 6947 struct rte_flow_action_jump jump = { 6948 .group = 1, 6949 }; 6950 const struct rte_flow_action actions[] = { 6951 { 6952 .type = RTE_FLOW_ACTION_TYPE_JUMP, 6953 .conf = &jump, 6954 }, 6955 { 6956 .type = RTE_FLOW_ACTION_TYPE_END, 6957 }, 6958 }; 6959 struct rte_flow_error error; 6960 6961 return (void *)(uintptr_t)flow_list_create(dev, MLX5_FLOW_TYPE_CTL, 6962 &attr, &pattern, 6963 actions, false, &error); 6964 } 6965 6966 /** 6967 * Create a dedicated flow rule on e-switch table 1, matches ESW manager 6968 * and sq number, directs all packets to peer vport. 6969 * 6970 * @param dev 6971 * Pointer to Ethernet device. 6972 * @param txq 6973 * Txq index. 6974 * 6975 * @return 6976 * Flow ID on success, 0 otherwise and rte_errno is set. 6977 */ 6978 uint32_t 6979 mlx5_flow_create_devx_sq_miss_flow(struct rte_eth_dev *dev, uint32_t txq) 6980 { 6981 struct rte_flow_attr attr = { 6982 .group = 0, 6983 .priority = MLX5_FLOW_LOWEST_PRIO_INDICATOR, 6984 .ingress = 1, 6985 .egress = 0, 6986 .transfer = 1, 6987 }; 6988 struct rte_flow_item_port_id port_spec = { 6989 .id = MLX5_PORT_ESW_MGR, 6990 }; 6991 struct mlx5_rte_flow_item_tx_queue txq_spec = { 6992 .queue = txq, 6993 }; 6994 struct rte_flow_item pattern[] = { 6995 { 6996 .type = RTE_FLOW_ITEM_TYPE_PORT_ID, 6997 .spec = &port_spec, 6998 }, 6999 { 7000 .type = (enum rte_flow_item_type) 7001 MLX5_RTE_FLOW_ITEM_TYPE_TX_QUEUE, 7002 .spec = &txq_spec, 7003 }, 7004 { 7005 .type = RTE_FLOW_ITEM_TYPE_END, 7006 }, 7007 }; 7008 struct rte_flow_action_jump jump = { 7009 .group = 1, 7010 }; 7011 struct rte_flow_action_port_id port = { 7012 .id = dev->data->port_id, 7013 }; 7014 struct rte_flow_action actions[] = { 7015 { 7016 .type = RTE_FLOW_ACTION_TYPE_JUMP, 7017 .conf = &jump, 7018 }, 7019 { 7020 .type = RTE_FLOW_ACTION_TYPE_END, 7021 }, 7022 }; 7023 struct rte_flow_error error; 7024 7025 /* 7026 * Creates group 0, highest priority jump flow. 7027 * Matches txq to bypass kernel packets. 7028 */ 7029 if (flow_list_create(dev, MLX5_FLOW_TYPE_CTL, &attr, pattern, actions, 7030 false, &error) == 0) 7031 return 0; 7032 /* Create group 1, lowest priority redirect flow for txq. */ 7033 attr.group = 1; 7034 actions[0].conf = &port; 7035 actions[0].type = RTE_FLOW_ACTION_TYPE_PORT_ID; 7036 return flow_list_create(dev, MLX5_FLOW_TYPE_CTL, &attr, pattern, 7037 actions, false, &error); 7038 } 7039 7040 /** 7041 * Validate a flow supported by the NIC. 7042 * 7043 * @see rte_flow_validate() 7044 * @see rte_flow_ops 7045 */ 7046 int 7047 mlx5_flow_validate(struct rte_eth_dev *dev, 7048 const struct rte_flow_attr *attr, 7049 const struct rte_flow_item items[], 7050 const struct rte_flow_action original_actions[], 7051 struct rte_flow_error *error) 7052 { 7053 int hairpin_flow; 7054 struct mlx5_translated_action_handle 7055 indir_actions[MLX5_MAX_INDIRECT_ACTIONS]; 7056 int indir_actions_n = MLX5_MAX_INDIRECT_ACTIONS; 7057 const struct rte_flow_action *actions; 7058 struct rte_flow_action *translated_actions = NULL; 7059 int ret = flow_action_handles_translate(dev, original_actions, 7060 indir_actions, 7061 &indir_actions_n, 7062 &translated_actions, error); 7063 7064 if (ret) 7065 return ret; 7066 actions = translated_actions ? translated_actions : original_actions; 7067 hairpin_flow = flow_check_hairpin_split(dev, attr, actions); 7068 ret = flow_drv_validate(dev, attr, items, actions, 7069 true, hairpin_flow, error); 7070 rte_free(translated_actions); 7071 return ret; 7072 } 7073 7074 /** 7075 * Create a flow. 7076 * 7077 * @see rte_flow_create() 7078 * @see rte_flow_ops 7079 */ 7080 struct rte_flow * 7081 mlx5_flow_create(struct rte_eth_dev *dev, 7082 const struct rte_flow_attr *attr, 7083 const struct rte_flow_item items[], 7084 const struct rte_flow_action actions[], 7085 struct rte_flow_error *error) 7086 { 7087 struct mlx5_priv *priv = dev->data->dev_private; 7088 7089 if (priv->sh->config.dv_flow_en == 2) { 7090 rte_flow_error_set(error, ENOTSUP, 7091 RTE_FLOW_ERROR_TYPE_UNSPECIFIED, 7092 NULL, 7093 "Flow non-Q creation not supported"); 7094 return NULL; 7095 } 7096 /* 7097 * If the device is not started yet, it is not allowed to created a 7098 * flow from application. PMD default flows and traffic control flows 7099 * are not affected. 7100 */ 7101 if (unlikely(!dev->data->dev_started)) { 7102 DRV_LOG(DEBUG, "port %u is not started when " 7103 "inserting a flow", dev->data->port_id); 7104 rte_flow_error_set(error, ENODEV, 7105 RTE_FLOW_ERROR_TYPE_UNSPECIFIED, 7106 NULL, 7107 "port not started"); 7108 return NULL; 7109 } 7110 7111 return (void *)(uintptr_t)flow_list_create(dev, MLX5_FLOW_TYPE_GEN, 7112 attr, items, actions, 7113 true, error); 7114 } 7115 7116 /** 7117 * Destroy a flow in a list. 7118 * 7119 * @param dev 7120 * Pointer to Ethernet device. 7121 * @param[in] flow_idx 7122 * Index of flow to destroy. 7123 */ 7124 static void 7125 flow_list_destroy(struct rte_eth_dev *dev, enum mlx5_flow_type type, 7126 uint32_t flow_idx) 7127 { 7128 struct mlx5_priv *priv = dev->data->dev_private; 7129 struct rte_flow *flow = mlx5_ipool_get(priv->flows[type], flow_idx); 7130 7131 if (!flow) 7132 return; 7133 MLX5_ASSERT(flow->type == type); 7134 /* 7135 * Update RX queue flags only if port is started, otherwise it is 7136 * already clean. 7137 */ 7138 if (dev->data->dev_started) 7139 flow_rxq_flags_trim(dev, flow); 7140 flow_drv_destroy(dev, flow); 7141 if (flow->tunnel) { 7142 struct mlx5_flow_tunnel *tunnel; 7143 7144 tunnel = mlx5_find_tunnel_id(dev, flow->tunnel_id); 7145 RTE_VERIFY(tunnel); 7146 if (!__atomic_sub_fetch(&tunnel->refctn, 1, __ATOMIC_RELAXED)) 7147 mlx5_flow_tunnel_free(dev, tunnel); 7148 } 7149 flow_mreg_del_copy_action(dev, flow); 7150 mlx5_ipool_free(priv->flows[type], flow_idx); 7151 } 7152 7153 /** 7154 * Destroy all flows. 7155 * 7156 * @param dev 7157 * Pointer to Ethernet device. 7158 * @param type 7159 * Flow type to be flushed. 7160 * @param active 7161 * If flushing is called actively. 7162 */ 7163 void 7164 mlx5_flow_list_flush(struct rte_eth_dev *dev, enum mlx5_flow_type type, 7165 bool active) 7166 { 7167 struct mlx5_priv *priv = dev->data->dev_private; 7168 uint32_t num_flushed = 0, fidx = 1; 7169 struct rte_flow *flow; 7170 7171 #ifdef HAVE_IBV_FLOW_DV_SUPPORT 7172 if (priv->sh->config.dv_flow_en == 2 && 7173 type == MLX5_FLOW_TYPE_GEN) { 7174 flow_hw_q_flow_flush(dev, NULL); 7175 return; 7176 } 7177 #endif 7178 7179 MLX5_IPOOL_FOREACH(priv->flows[type], fidx, flow) { 7180 flow_list_destroy(dev, type, fidx); 7181 num_flushed++; 7182 } 7183 if (active) { 7184 DRV_LOG(INFO, "port %u: %u flows flushed before stopping", 7185 dev->data->port_id, num_flushed); 7186 } 7187 } 7188 7189 /** 7190 * Stop all default actions for flows. 7191 * 7192 * @param dev 7193 * Pointer to Ethernet device. 7194 */ 7195 void 7196 mlx5_flow_stop_default(struct rte_eth_dev *dev) 7197 { 7198 flow_mreg_del_default_copy_action(dev); 7199 flow_rxq_flags_clear(dev); 7200 } 7201 7202 /** 7203 * Start all default actions for flows. 7204 * 7205 * @param dev 7206 * Pointer to Ethernet device. 7207 * @return 7208 * 0 on success, a negative errno value otherwise and rte_errno is set. 7209 */ 7210 int 7211 mlx5_flow_start_default(struct rte_eth_dev *dev) 7212 { 7213 struct rte_flow_error error; 7214 7215 /* Make sure default copy action (reg_c[0] -> reg_b) is created. */ 7216 return flow_mreg_add_default_copy_action(dev, &error); 7217 } 7218 7219 /** 7220 * Release key of thread specific flow workspace data. 7221 */ 7222 void 7223 flow_release_workspace(void *data) 7224 { 7225 struct mlx5_flow_workspace *wks = data; 7226 struct mlx5_flow_workspace *next; 7227 7228 while (wks) { 7229 next = wks->next; 7230 free(wks->rss_desc.queue); 7231 free(wks); 7232 wks = next; 7233 } 7234 } 7235 7236 /** 7237 * Get thread specific current flow workspace. 7238 * 7239 * @return pointer to thread specific flow workspace data, NULL on error. 7240 */ 7241 struct mlx5_flow_workspace* 7242 mlx5_flow_get_thread_workspace(void) 7243 { 7244 struct mlx5_flow_workspace *data; 7245 7246 data = mlx5_flow_os_get_specific_workspace(); 7247 MLX5_ASSERT(data && data->inuse); 7248 if (!data || !data->inuse) 7249 DRV_LOG(ERR, "flow workspace not initialized."); 7250 return data; 7251 } 7252 7253 /** 7254 * Allocate and init new flow workspace. 7255 * 7256 * @return pointer to flow workspace data, NULL on error. 7257 */ 7258 static struct mlx5_flow_workspace* 7259 flow_alloc_thread_workspace(void) 7260 { 7261 struct mlx5_flow_workspace *data = calloc(1, sizeof(*data)); 7262 7263 if (!data) { 7264 DRV_LOG(ERR, "Failed to allocate flow workspace " 7265 "memory."); 7266 return NULL; 7267 } 7268 data->rss_desc.queue = calloc(1, 7269 sizeof(uint16_t) * MLX5_RSSQ_DEFAULT_NUM); 7270 if (!data->rss_desc.queue) 7271 goto err; 7272 data->rssq_num = MLX5_RSSQ_DEFAULT_NUM; 7273 return data; 7274 err: 7275 free(data->rss_desc.queue); 7276 free(data); 7277 return NULL; 7278 } 7279 7280 /** 7281 * Get new thread specific flow workspace. 7282 * 7283 * If current workspace inuse, create new one and set as current. 7284 * 7285 * @return pointer to thread specific flow workspace data, NULL on error. 7286 */ 7287 static struct mlx5_flow_workspace* 7288 mlx5_flow_push_thread_workspace(void) 7289 { 7290 struct mlx5_flow_workspace *curr; 7291 struct mlx5_flow_workspace *data; 7292 7293 curr = mlx5_flow_os_get_specific_workspace(); 7294 if (!curr) { 7295 data = flow_alloc_thread_workspace(); 7296 if (!data) 7297 return NULL; 7298 } else if (!curr->inuse) { 7299 data = curr; 7300 } else if (curr->next) { 7301 data = curr->next; 7302 } else { 7303 data = flow_alloc_thread_workspace(); 7304 if (!data) 7305 return NULL; 7306 curr->next = data; 7307 data->prev = curr; 7308 } 7309 data->inuse = 1; 7310 data->flow_idx = 0; 7311 /* Set as current workspace */ 7312 if (mlx5_flow_os_set_specific_workspace(data)) 7313 DRV_LOG(ERR, "Failed to set flow workspace to thread."); 7314 return data; 7315 } 7316 7317 /** 7318 * Close current thread specific flow workspace. 7319 * 7320 * If previous workspace available, set it as current. 7321 * 7322 * @return pointer to thread specific flow workspace data, NULL on error. 7323 */ 7324 static void 7325 mlx5_flow_pop_thread_workspace(void) 7326 { 7327 struct mlx5_flow_workspace *data = mlx5_flow_get_thread_workspace(); 7328 7329 if (!data) 7330 return; 7331 if (!data->inuse) { 7332 DRV_LOG(ERR, "Failed to close unused flow workspace."); 7333 return; 7334 } 7335 data->inuse = 0; 7336 if (!data->prev) 7337 return; 7338 if (mlx5_flow_os_set_specific_workspace(data->prev)) 7339 DRV_LOG(ERR, "Failed to set flow workspace to thread."); 7340 } 7341 7342 /** 7343 * Verify the flow list is empty 7344 * 7345 * @param dev 7346 * Pointer to Ethernet device. 7347 * 7348 * @return the number of flows not released. 7349 */ 7350 int 7351 mlx5_flow_verify(struct rte_eth_dev *dev __rte_unused) 7352 { 7353 struct mlx5_priv *priv = dev->data->dev_private; 7354 struct rte_flow *flow; 7355 uint32_t idx = 0; 7356 int ret = 0, i; 7357 7358 for (i = 0; i < MLX5_FLOW_TYPE_MAXI; i++) { 7359 MLX5_IPOOL_FOREACH(priv->flows[i], idx, flow) { 7360 DRV_LOG(DEBUG, "port %u flow %p still referenced", 7361 dev->data->port_id, (void *)flow); 7362 ret++; 7363 } 7364 } 7365 return ret; 7366 } 7367 7368 /** 7369 * Enable default hairpin egress flow. 7370 * 7371 * @param dev 7372 * Pointer to Ethernet device. 7373 * @param queue 7374 * The queue index. 7375 * 7376 * @return 7377 * 0 on success, a negative errno value otherwise and rte_errno is set. 7378 */ 7379 int 7380 mlx5_ctrl_flow_source_queue(struct rte_eth_dev *dev, 7381 uint32_t queue) 7382 { 7383 const struct rte_flow_attr attr = { 7384 .egress = 1, 7385 .priority = 0, 7386 }; 7387 struct mlx5_rte_flow_item_tx_queue queue_spec = { 7388 .queue = queue, 7389 }; 7390 struct mlx5_rte_flow_item_tx_queue queue_mask = { 7391 .queue = UINT32_MAX, 7392 }; 7393 struct rte_flow_item items[] = { 7394 { 7395 .type = (enum rte_flow_item_type) 7396 MLX5_RTE_FLOW_ITEM_TYPE_TX_QUEUE, 7397 .spec = &queue_spec, 7398 .last = NULL, 7399 .mask = &queue_mask, 7400 }, 7401 { 7402 .type = RTE_FLOW_ITEM_TYPE_END, 7403 }, 7404 }; 7405 struct rte_flow_action_jump jump = { 7406 .group = MLX5_HAIRPIN_TX_TABLE, 7407 }; 7408 struct rte_flow_action actions[2]; 7409 uint32_t flow_idx; 7410 struct rte_flow_error error; 7411 7412 actions[0].type = RTE_FLOW_ACTION_TYPE_JUMP; 7413 actions[0].conf = &jump; 7414 actions[1].type = RTE_FLOW_ACTION_TYPE_END; 7415 flow_idx = flow_list_create(dev, MLX5_FLOW_TYPE_CTL, 7416 &attr, items, actions, false, &error); 7417 if (!flow_idx) { 7418 DRV_LOG(DEBUG, 7419 "Failed to create ctrl flow: rte_errno(%d)," 7420 " type(%d), message(%s)", 7421 rte_errno, error.type, 7422 error.message ? error.message : " (no stated reason)"); 7423 return -rte_errno; 7424 } 7425 return 0; 7426 } 7427 7428 /** 7429 * Enable a control flow configured from the control plane. 7430 * 7431 * @param dev 7432 * Pointer to Ethernet device. 7433 * @param eth_spec 7434 * An Ethernet flow spec to apply. 7435 * @param eth_mask 7436 * An Ethernet flow mask to apply. 7437 * @param vlan_spec 7438 * A VLAN flow spec to apply. 7439 * @param vlan_mask 7440 * A VLAN flow mask to apply. 7441 * 7442 * @return 7443 * 0 on success, a negative errno value otherwise and rte_errno is set. 7444 */ 7445 int 7446 mlx5_ctrl_flow_vlan(struct rte_eth_dev *dev, 7447 struct rte_flow_item_eth *eth_spec, 7448 struct rte_flow_item_eth *eth_mask, 7449 struct rte_flow_item_vlan *vlan_spec, 7450 struct rte_flow_item_vlan *vlan_mask) 7451 { 7452 struct mlx5_priv *priv = dev->data->dev_private; 7453 const struct rte_flow_attr attr = { 7454 .ingress = 1, 7455 .priority = MLX5_FLOW_LOWEST_PRIO_INDICATOR, 7456 }; 7457 struct rte_flow_item items[] = { 7458 { 7459 .type = RTE_FLOW_ITEM_TYPE_ETH, 7460 .spec = eth_spec, 7461 .last = NULL, 7462 .mask = eth_mask, 7463 }, 7464 { 7465 .type = (vlan_spec) ? RTE_FLOW_ITEM_TYPE_VLAN : 7466 RTE_FLOW_ITEM_TYPE_END, 7467 .spec = vlan_spec, 7468 .last = NULL, 7469 .mask = vlan_mask, 7470 }, 7471 { 7472 .type = RTE_FLOW_ITEM_TYPE_END, 7473 }, 7474 }; 7475 uint16_t queue[priv->reta_idx_n]; 7476 struct rte_flow_action_rss action_rss = { 7477 .func = RTE_ETH_HASH_FUNCTION_DEFAULT, 7478 .level = 0, 7479 .types = priv->rss_conf.rss_hf, 7480 .key_len = priv->rss_conf.rss_key_len, 7481 .queue_num = priv->reta_idx_n, 7482 .key = priv->rss_conf.rss_key, 7483 .queue = queue, 7484 }; 7485 struct rte_flow_action actions[] = { 7486 { 7487 .type = RTE_FLOW_ACTION_TYPE_RSS, 7488 .conf = &action_rss, 7489 }, 7490 { 7491 .type = RTE_FLOW_ACTION_TYPE_END, 7492 }, 7493 }; 7494 uint32_t flow_idx; 7495 struct rte_flow_error error; 7496 unsigned int i; 7497 7498 if (!priv->reta_idx_n || !priv->rxqs_n) { 7499 return 0; 7500 } 7501 if (!(dev->data->dev_conf.rxmode.mq_mode & RTE_ETH_MQ_RX_RSS_FLAG)) 7502 action_rss.types = 0; 7503 for (i = 0; i != priv->reta_idx_n; ++i) 7504 queue[i] = (*priv->reta_idx)[i]; 7505 flow_idx = flow_list_create(dev, MLX5_FLOW_TYPE_CTL, 7506 &attr, items, actions, false, &error); 7507 if (!flow_idx) 7508 return -rte_errno; 7509 return 0; 7510 } 7511 7512 /** 7513 * Enable a flow control configured from the control plane. 7514 * 7515 * @param dev 7516 * Pointer to Ethernet device. 7517 * @param eth_spec 7518 * An Ethernet flow spec to apply. 7519 * @param eth_mask 7520 * An Ethernet flow mask to apply. 7521 * 7522 * @return 7523 * 0 on success, a negative errno value otherwise and rte_errno is set. 7524 */ 7525 int 7526 mlx5_ctrl_flow(struct rte_eth_dev *dev, 7527 struct rte_flow_item_eth *eth_spec, 7528 struct rte_flow_item_eth *eth_mask) 7529 { 7530 return mlx5_ctrl_flow_vlan(dev, eth_spec, eth_mask, NULL, NULL); 7531 } 7532 7533 /** 7534 * Create default miss flow rule matching lacp traffic 7535 * 7536 * @param dev 7537 * Pointer to Ethernet device. 7538 * @param eth_spec 7539 * An Ethernet flow spec to apply. 7540 * 7541 * @return 7542 * 0 on success, a negative errno value otherwise and rte_errno is set. 7543 */ 7544 int 7545 mlx5_flow_lacp_miss(struct rte_eth_dev *dev) 7546 { 7547 /* 7548 * The LACP matching is done by only using ether type since using 7549 * a multicast dst mac causes kernel to give low priority to this flow. 7550 */ 7551 static const struct rte_flow_item_eth lacp_spec = { 7552 .type = RTE_BE16(0x8809), 7553 }; 7554 static const struct rte_flow_item_eth lacp_mask = { 7555 .type = 0xffff, 7556 }; 7557 const struct rte_flow_attr attr = { 7558 .ingress = 1, 7559 }; 7560 struct rte_flow_item items[] = { 7561 { 7562 .type = RTE_FLOW_ITEM_TYPE_ETH, 7563 .spec = &lacp_spec, 7564 .mask = &lacp_mask, 7565 }, 7566 { 7567 .type = RTE_FLOW_ITEM_TYPE_END, 7568 }, 7569 }; 7570 struct rte_flow_action actions[] = { 7571 { 7572 .type = (enum rte_flow_action_type) 7573 MLX5_RTE_FLOW_ACTION_TYPE_DEFAULT_MISS, 7574 }, 7575 { 7576 .type = RTE_FLOW_ACTION_TYPE_END, 7577 }, 7578 }; 7579 struct rte_flow_error error; 7580 uint32_t flow_idx = flow_list_create(dev, MLX5_FLOW_TYPE_CTL, 7581 &attr, items, actions, 7582 false, &error); 7583 7584 if (!flow_idx) 7585 return -rte_errno; 7586 return 0; 7587 } 7588 7589 /** 7590 * Destroy a flow. 7591 * 7592 * @see rte_flow_destroy() 7593 * @see rte_flow_ops 7594 */ 7595 int 7596 mlx5_flow_destroy(struct rte_eth_dev *dev, 7597 struct rte_flow *flow, 7598 struct rte_flow_error *error __rte_unused) 7599 { 7600 struct mlx5_priv *priv = dev->data->dev_private; 7601 7602 if (priv->sh->config.dv_flow_en == 2) 7603 return rte_flow_error_set(error, ENOTSUP, 7604 RTE_FLOW_ERROR_TYPE_UNSPECIFIED, 7605 NULL, 7606 "Flow non-Q destruction not supported"); 7607 flow_list_destroy(dev, MLX5_FLOW_TYPE_GEN, 7608 (uintptr_t)(void *)flow); 7609 return 0; 7610 } 7611 7612 /** 7613 * Destroy all flows. 7614 * 7615 * @see rte_flow_flush() 7616 * @see rte_flow_ops 7617 */ 7618 int 7619 mlx5_flow_flush(struct rte_eth_dev *dev, 7620 struct rte_flow_error *error __rte_unused) 7621 { 7622 mlx5_flow_list_flush(dev, MLX5_FLOW_TYPE_GEN, false); 7623 return 0; 7624 } 7625 7626 /** 7627 * Isolated mode. 7628 * 7629 * @see rte_flow_isolate() 7630 * @see rte_flow_ops 7631 */ 7632 int 7633 mlx5_flow_isolate(struct rte_eth_dev *dev, 7634 int enable, 7635 struct rte_flow_error *error) 7636 { 7637 struct mlx5_priv *priv = dev->data->dev_private; 7638 7639 if (dev->data->dev_started) { 7640 rte_flow_error_set(error, EBUSY, 7641 RTE_FLOW_ERROR_TYPE_UNSPECIFIED, 7642 NULL, 7643 "port must be stopped first"); 7644 return -rte_errno; 7645 } 7646 priv->isolated = !!enable; 7647 if (enable) 7648 dev->dev_ops = &mlx5_dev_ops_isolate; 7649 else 7650 dev->dev_ops = &mlx5_dev_ops; 7651 7652 dev->rx_descriptor_status = mlx5_rx_descriptor_status; 7653 dev->tx_descriptor_status = mlx5_tx_descriptor_status; 7654 7655 return 0; 7656 } 7657 7658 /** 7659 * Query a flow. 7660 * 7661 * @see rte_flow_query() 7662 * @see rte_flow_ops 7663 */ 7664 static int 7665 flow_drv_query(struct rte_eth_dev *dev, 7666 uint32_t flow_idx, 7667 const struct rte_flow_action *actions, 7668 void *data, 7669 struct rte_flow_error *error) 7670 { 7671 struct mlx5_priv *priv = dev->data->dev_private; 7672 const struct mlx5_flow_driver_ops *fops; 7673 struct rte_flow *flow = mlx5_ipool_get(priv->flows[MLX5_FLOW_TYPE_GEN], 7674 flow_idx); 7675 enum mlx5_flow_drv_type ftype; 7676 7677 if (!flow) { 7678 return rte_flow_error_set(error, ENOENT, 7679 RTE_FLOW_ERROR_TYPE_UNSPECIFIED, 7680 NULL, 7681 "invalid flow handle"); 7682 } 7683 ftype = flow->drv_type; 7684 MLX5_ASSERT(ftype > MLX5_FLOW_TYPE_MIN && ftype < MLX5_FLOW_TYPE_MAX); 7685 fops = flow_get_drv_ops(ftype); 7686 7687 return fops->query(dev, flow, actions, data, error); 7688 } 7689 7690 /** 7691 * Query a flow. 7692 * 7693 * @see rte_flow_query() 7694 * @see rte_flow_ops 7695 */ 7696 int 7697 mlx5_flow_query(struct rte_eth_dev *dev, 7698 struct rte_flow *flow, 7699 const struct rte_flow_action *actions, 7700 void *data, 7701 struct rte_flow_error *error) 7702 { 7703 int ret; 7704 struct mlx5_priv *priv = dev->data->dev_private; 7705 7706 if (priv->sh->config.dv_flow_en == 2) 7707 return rte_flow_error_set(error, ENOTSUP, 7708 RTE_FLOW_ERROR_TYPE_UNSPECIFIED, 7709 NULL, 7710 "Flow non-Q query not supported"); 7711 ret = flow_drv_query(dev, (uintptr_t)(void *)flow, actions, data, 7712 error); 7713 if (ret < 0) 7714 return ret; 7715 return 0; 7716 } 7717 7718 /** 7719 * Get rte_flow callbacks. 7720 * 7721 * @param dev 7722 * Pointer to Ethernet device structure. 7723 * @param ops 7724 * Pointer to operation-specific structure. 7725 * 7726 * @return 0 7727 */ 7728 int 7729 mlx5_flow_ops_get(struct rte_eth_dev *dev __rte_unused, 7730 const struct rte_flow_ops **ops) 7731 { 7732 *ops = &mlx5_flow_ops; 7733 return 0; 7734 } 7735 7736 /** 7737 * Validate meter policy actions. 7738 * Dispatcher for action type specific validation. 7739 * 7740 * @param[in] dev 7741 * Pointer to the Ethernet device structure. 7742 * @param[in] action 7743 * The meter policy action object to validate. 7744 * @param[in] attr 7745 * Attributes of flow to determine steering domain. 7746 * @param[out] is_rss 7747 * Is RSS or not. 7748 * @param[out] domain_bitmap 7749 * Domain bitmap. 7750 * @param[out] is_def_policy 7751 * Is default policy or not. 7752 * @param[out] error 7753 * Perform verbose error reporting if not NULL. Initialized in case of 7754 * error only. 7755 * 7756 * @return 7757 * 0 on success, otherwise negative errno value. 7758 */ 7759 int 7760 mlx5_flow_validate_mtr_acts(struct rte_eth_dev *dev, 7761 const struct rte_flow_action *actions[RTE_COLORS], 7762 struct rte_flow_attr *attr, 7763 bool *is_rss, 7764 uint8_t *domain_bitmap, 7765 uint8_t *policy_mode, 7766 struct rte_mtr_error *error) 7767 { 7768 const struct mlx5_flow_driver_ops *fops; 7769 7770 fops = flow_get_drv_ops(MLX5_FLOW_TYPE_DV); 7771 return fops->validate_mtr_acts(dev, actions, attr, is_rss, 7772 domain_bitmap, policy_mode, error); 7773 } 7774 7775 /** 7776 * Destroy the meter table set. 7777 * 7778 * @param[in] dev 7779 * Pointer to Ethernet device. 7780 * @param[in] mtr_policy 7781 * Meter policy struct. 7782 */ 7783 void 7784 mlx5_flow_destroy_mtr_acts(struct rte_eth_dev *dev, 7785 struct mlx5_flow_meter_policy *mtr_policy) 7786 { 7787 const struct mlx5_flow_driver_ops *fops; 7788 7789 fops = flow_get_drv_ops(MLX5_FLOW_TYPE_DV); 7790 fops->destroy_mtr_acts(dev, mtr_policy); 7791 } 7792 7793 /** 7794 * Create policy action, lock free, 7795 * (mutex should be acquired by caller). 7796 * Dispatcher for action type specific call. 7797 * 7798 * @param[in] dev 7799 * Pointer to the Ethernet device structure. 7800 * @param[in] mtr_policy 7801 * Meter policy struct. 7802 * @param[in] action 7803 * Action specification used to create meter actions. 7804 * @param[out] error 7805 * Perform verbose error reporting if not NULL. Initialized in case of 7806 * error only. 7807 * 7808 * @return 7809 * 0 on success, otherwise negative errno value. 7810 */ 7811 int 7812 mlx5_flow_create_mtr_acts(struct rte_eth_dev *dev, 7813 struct mlx5_flow_meter_policy *mtr_policy, 7814 const struct rte_flow_action *actions[RTE_COLORS], 7815 struct rte_mtr_error *error) 7816 { 7817 const struct mlx5_flow_driver_ops *fops; 7818 7819 fops = flow_get_drv_ops(MLX5_FLOW_TYPE_DV); 7820 return fops->create_mtr_acts(dev, mtr_policy, actions, error); 7821 } 7822 7823 /** 7824 * Create policy rules, lock free, 7825 * (mutex should be acquired by caller). 7826 * Dispatcher for action type specific call. 7827 * 7828 * @param[in] dev 7829 * Pointer to the Ethernet device structure. 7830 * @param[in] mtr_policy 7831 * Meter policy struct. 7832 * 7833 * @return 7834 * 0 on success, -1 otherwise. 7835 */ 7836 int 7837 mlx5_flow_create_policy_rules(struct rte_eth_dev *dev, 7838 struct mlx5_flow_meter_policy *mtr_policy) 7839 { 7840 const struct mlx5_flow_driver_ops *fops; 7841 7842 fops = flow_get_drv_ops(MLX5_FLOW_TYPE_DV); 7843 return fops->create_policy_rules(dev, mtr_policy); 7844 } 7845 7846 /** 7847 * Destroy policy rules, lock free, 7848 * (mutex should be acquired by caller). 7849 * Dispatcher for action type specific call. 7850 * 7851 * @param[in] dev 7852 * Pointer to the Ethernet device structure. 7853 * @param[in] mtr_policy 7854 * Meter policy struct. 7855 */ 7856 void 7857 mlx5_flow_destroy_policy_rules(struct rte_eth_dev *dev, 7858 struct mlx5_flow_meter_policy *mtr_policy) 7859 { 7860 const struct mlx5_flow_driver_ops *fops; 7861 7862 fops = flow_get_drv_ops(MLX5_FLOW_TYPE_DV); 7863 fops->destroy_policy_rules(dev, mtr_policy); 7864 } 7865 7866 /** 7867 * Destroy the default policy table set. 7868 * 7869 * @param[in] dev 7870 * Pointer to Ethernet device. 7871 */ 7872 void 7873 mlx5_flow_destroy_def_policy(struct rte_eth_dev *dev) 7874 { 7875 const struct mlx5_flow_driver_ops *fops; 7876 7877 fops = flow_get_drv_ops(MLX5_FLOW_TYPE_DV); 7878 fops->destroy_def_policy(dev); 7879 } 7880 7881 /** 7882 * Destroy the default policy table set. 7883 * 7884 * @param[in] dev 7885 * Pointer to Ethernet device. 7886 * 7887 * @return 7888 * 0 on success, -1 otherwise. 7889 */ 7890 int 7891 mlx5_flow_create_def_policy(struct rte_eth_dev *dev) 7892 { 7893 const struct mlx5_flow_driver_ops *fops; 7894 7895 fops = flow_get_drv_ops(MLX5_FLOW_TYPE_DV); 7896 return fops->create_def_policy(dev); 7897 } 7898 7899 /** 7900 * Create the needed meter and suffix tables. 7901 * 7902 * @param[in] dev 7903 * Pointer to Ethernet device. 7904 * 7905 * @return 7906 * 0 on success, -1 otherwise. 7907 */ 7908 int 7909 mlx5_flow_create_mtr_tbls(struct rte_eth_dev *dev, 7910 struct mlx5_flow_meter_info *fm, 7911 uint32_t mtr_idx, 7912 uint8_t domain_bitmap) 7913 { 7914 const struct mlx5_flow_driver_ops *fops; 7915 7916 fops = flow_get_drv_ops(MLX5_FLOW_TYPE_DV); 7917 return fops->create_mtr_tbls(dev, fm, mtr_idx, domain_bitmap); 7918 } 7919 7920 /** 7921 * Destroy the meter table set. 7922 * 7923 * @param[in] dev 7924 * Pointer to Ethernet device. 7925 * @param[in] tbl 7926 * Pointer to the meter table set. 7927 */ 7928 void 7929 mlx5_flow_destroy_mtr_tbls(struct rte_eth_dev *dev, 7930 struct mlx5_flow_meter_info *fm) 7931 { 7932 const struct mlx5_flow_driver_ops *fops; 7933 7934 fops = flow_get_drv_ops(MLX5_FLOW_TYPE_DV); 7935 fops->destroy_mtr_tbls(dev, fm); 7936 } 7937 7938 /** 7939 * Destroy the global meter drop table. 7940 * 7941 * @param[in] dev 7942 * Pointer to Ethernet device. 7943 */ 7944 void 7945 mlx5_flow_destroy_mtr_drop_tbls(struct rte_eth_dev *dev) 7946 { 7947 const struct mlx5_flow_driver_ops *fops; 7948 7949 fops = flow_get_drv_ops(MLX5_FLOW_TYPE_DV); 7950 fops->destroy_mtr_drop_tbls(dev); 7951 } 7952 7953 /** 7954 * Destroy the sub policy table with RX queue. 7955 * 7956 * @param[in] dev 7957 * Pointer to Ethernet device. 7958 * @param[in] mtr_policy 7959 * Pointer to meter policy table. 7960 */ 7961 void 7962 mlx5_flow_destroy_sub_policy_with_rxq(struct rte_eth_dev *dev, 7963 struct mlx5_flow_meter_policy *mtr_policy) 7964 { 7965 const struct mlx5_flow_driver_ops *fops; 7966 7967 fops = flow_get_drv_ops(MLX5_FLOW_TYPE_DV); 7968 fops->destroy_sub_policy_with_rxq(dev, mtr_policy); 7969 } 7970 7971 /** 7972 * Allocate the needed aso flow meter id. 7973 * 7974 * @param[in] dev 7975 * Pointer to Ethernet device. 7976 * 7977 * @return 7978 * Index to aso flow meter on success, NULL otherwise. 7979 */ 7980 uint32_t 7981 mlx5_flow_mtr_alloc(struct rte_eth_dev *dev) 7982 { 7983 const struct mlx5_flow_driver_ops *fops; 7984 7985 fops = flow_get_drv_ops(MLX5_FLOW_TYPE_DV); 7986 return fops->create_meter(dev); 7987 } 7988 7989 /** 7990 * Free the aso flow meter id. 7991 * 7992 * @param[in] dev 7993 * Pointer to Ethernet device. 7994 * @param[in] mtr_idx 7995 * Index to aso flow meter to be free. 7996 * 7997 * @return 7998 * 0 on success. 7999 */ 8000 void 8001 mlx5_flow_mtr_free(struct rte_eth_dev *dev, uint32_t mtr_idx) 8002 { 8003 const struct mlx5_flow_driver_ops *fops; 8004 8005 fops = flow_get_drv_ops(MLX5_FLOW_TYPE_DV); 8006 fops->free_meter(dev, mtr_idx); 8007 } 8008 8009 /** 8010 * Allocate a counter. 8011 * 8012 * @param[in] dev 8013 * Pointer to Ethernet device structure. 8014 * 8015 * @return 8016 * Index to allocated counter on success, 0 otherwise. 8017 */ 8018 uint32_t 8019 mlx5_counter_alloc(struct rte_eth_dev *dev) 8020 { 8021 const struct mlx5_flow_driver_ops *fops; 8022 struct rte_flow_attr attr = { .transfer = 0 }; 8023 8024 if (flow_get_drv_type(dev, &attr) == MLX5_FLOW_TYPE_DV) { 8025 fops = flow_get_drv_ops(MLX5_FLOW_TYPE_DV); 8026 return fops->counter_alloc(dev); 8027 } 8028 DRV_LOG(ERR, 8029 "port %u counter allocate is not supported.", 8030 dev->data->port_id); 8031 return 0; 8032 } 8033 8034 /** 8035 * Free a counter. 8036 * 8037 * @param[in] dev 8038 * Pointer to Ethernet device structure. 8039 * @param[in] cnt 8040 * Index to counter to be free. 8041 */ 8042 void 8043 mlx5_counter_free(struct rte_eth_dev *dev, uint32_t cnt) 8044 { 8045 const struct mlx5_flow_driver_ops *fops; 8046 struct rte_flow_attr attr = { .transfer = 0 }; 8047 8048 if (flow_get_drv_type(dev, &attr) == MLX5_FLOW_TYPE_DV) { 8049 fops = flow_get_drv_ops(MLX5_FLOW_TYPE_DV); 8050 fops->counter_free(dev, cnt); 8051 return; 8052 } 8053 DRV_LOG(ERR, 8054 "port %u counter free is not supported.", 8055 dev->data->port_id); 8056 } 8057 8058 /** 8059 * Query counter statistics. 8060 * 8061 * @param[in] dev 8062 * Pointer to Ethernet device structure. 8063 * @param[in] cnt 8064 * Index to counter to query. 8065 * @param[in] clear 8066 * Set to clear counter statistics. 8067 * @param[out] pkts 8068 * The counter hits packets number to save. 8069 * @param[out] bytes 8070 * The counter hits bytes number to save. 8071 * 8072 * @return 8073 * 0 on success, a negative errno value otherwise. 8074 */ 8075 int 8076 mlx5_counter_query(struct rte_eth_dev *dev, uint32_t cnt, 8077 bool clear, uint64_t *pkts, uint64_t *bytes, void **action) 8078 { 8079 const struct mlx5_flow_driver_ops *fops; 8080 struct rte_flow_attr attr = { .transfer = 0 }; 8081 8082 if (flow_get_drv_type(dev, &attr) == MLX5_FLOW_TYPE_DV) { 8083 fops = flow_get_drv_ops(MLX5_FLOW_TYPE_DV); 8084 return fops->counter_query(dev, cnt, clear, pkts, 8085 bytes, action); 8086 } 8087 DRV_LOG(ERR, 8088 "port %u counter query is not supported.", 8089 dev->data->port_id); 8090 return -ENOTSUP; 8091 } 8092 8093 /** 8094 * Get information about HWS pre-configurable resources. 8095 * 8096 * @param[in] dev 8097 * Pointer to the rte_eth_dev structure. 8098 * @param[out] port_info 8099 * Pointer to port information. 8100 * @param[out] queue_info 8101 * Pointer to queue information. 8102 * @param[out] error 8103 * Pointer to error structure. 8104 * 8105 * @return 8106 * 0 on success, a negative errno value otherwise and rte_errno is set. 8107 */ 8108 static int 8109 mlx5_flow_info_get(struct rte_eth_dev *dev, 8110 struct rte_flow_port_info *port_info, 8111 struct rte_flow_queue_info *queue_info, 8112 struct rte_flow_error *error) 8113 { 8114 const struct mlx5_flow_driver_ops *fops; 8115 8116 if (flow_get_drv_type(dev, NULL) != MLX5_FLOW_TYPE_HW) 8117 return rte_flow_error_set(error, ENOTSUP, 8118 RTE_FLOW_ERROR_TYPE_UNSPECIFIED, 8119 NULL, 8120 "info get with incorrect steering mode"); 8121 fops = flow_get_drv_ops(MLX5_FLOW_TYPE_HW); 8122 return fops->info_get(dev, port_info, queue_info, error); 8123 } 8124 8125 /** 8126 * Configure port HWS resources. 8127 * 8128 * @param[in] dev 8129 * Pointer to the rte_eth_dev structure. 8130 * @param[in] port_attr 8131 * Port configuration attributes. 8132 * @param[in] nb_queue 8133 * Number of queue. 8134 * @param[in] queue_attr 8135 * Array that holds attributes for each flow queue. 8136 * @param[out] error 8137 * Pointer to error structure. 8138 * 8139 * @return 8140 * 0 on success, a negative errno value otherwise and rte_errno is set. 8141 */ 8142 static int 8143 mlx5_flow_port_configure(struct rte_eth_dev *dev, 8144 const struct rte_flow_port_attr *port_attr, 8145 uint16_t nb_queue, 8146 const struct rte_flow_queue_attr *queue_attr[], 8147 struct rte_flow_error *error) 8148 { 8149 const struct mlx5_flow_driver_ops *fops; 8150 8151 if (flow_get_drv_type(dev, NULL) != MLX5_FLOW_TYPE_HW) 8152 return rte_flow_error_set(error, ENOTSUP, 8153 RTE_FLOW_ERROR_TYPE_UNSPECIFIED, 8154 NULL, 8155 "port configure with incorrect steering mode"); 8156 fops = flow_get_drv_ops(MLX5_FLOW_TYPE_HW); 8157 return fops->configure(dev, port_attr, nb_queue, queue_attr, error); 8158 } 8159 8160 /** 8161 * Create flow item template. 8162 * 8163 * @param[in] dev 8164 * Pointer to the rte_eth_dev structure. 8165 * @param[in] attr 8166 * Pointer to the item template attributes. 8167 * @param[in] items 8168 * The template item pattern. 8169 * @param[out] error 8170 * Pointer to error structure. 8171 * 8172 * @return 8173 * 0 on success, a negative errno value otherwise and rte_errno is set. 8174 */ 8175 static struct rte_flow_pattern_template * 8176 mlx5_flow_pattern_template_create(struct rte_eth_dev *dev, 8177 const struct rte_flow_pattern_template_attr *attr, 8178 const struct rte_flow_item items[], 8179 struct rte_flow_error *error) 8180 { 8181 const struct mlx5_flow_driver_ops *fops; 8182 8183 if (flow_get_drv_type(dev, NULL) != MLX5_FLOW_TYPE_HW) { 8184 rte_flow_error_set(error, ENOTSUP, 8185 RTE_FLOW_ERROR_TYPE_UNSPECIFIED, 8186 NULL, 8187 "pattern create with incorrect steering mode"); 8188 return NULL; 8189 } 8190 fops = flow_get_drv_ops(MLX5_FLOW_TYPE_HW); 8191 return fops->pattern_template_create(dev, attr, items, error); 8192 } 8193 8194 /** 8195 * Destroy flow item template. 8196 * 8197 * @param[in] dev 8198 * Pointer to the rte_eth_dev structure. 8199 * @param[in] template 8200 * Pointer to the item template to be destroyed. 8201 * @param[out] error 8202 * Pointer to error structure. 8203 * 8204 * @return 8205 * 0 on success, a negative errno value otherwise and rte_errno is set. 8206 */ 8207 static int 8208 mlx5_flow_pattern_template_destroy(struct rte_eth_dev *dev, 8209 struct rte_flow_pattern_template *template, 8210 struct rte_flow_error *error) 8211 { 8212 const struct mlx5_flow_driver_ops *fops; 8213 8214 if (flow_get_drv_type(dev, NULL) != MLX5_FLOW_TYPE_HW) 8215 return rte_flow_error_set(error, ENOTSUP, 8216 RTE_FLOW_ERROR_TYPE_UNSPECIFIED, 8217 NULL, 8218 "pattern destroy with incorrect steering mode"); 8219 fops = flow_get_drv_ops(MLX5_FLOW_TYPE_HW); 8220 return fops->pattern_template_destroy(dev, template, error); 8221 } 8222 8223 /** 8224 * Create flow item template. 8225 * 8226 * @param[in] dev 8227 * Pointer to the rte_eth_dev structure. 8228 * @param[in] attr 8229 * Pointer to the action template attributes. 8230 * @param[in] actions 8231 * Associated actions (list terminated by the END action). 8232 * @param[in] masks 8233 * List of actions that marks which of the action's member is constant. 8234 * @param[out] error 8235 * Pointer to error structure. 8236 * 8237 * @return 8238 * 0 on success, a negative errno value otherwise and rte_errno is set. 8239 */ 8240 static struct rte_flow_actions_template * 8241 mlx5_flow_actions_template_create(struct rte_eth_dev *dev, 8242 const struct rte_flow_actions_template_attr *attr, 8243 const struct rte_flow_action actions[], 8244 const struct rte_flow_action masks[], 8245 struct rte_flow_error *error) 8246 { 8247 const struct mlx5_flow_driver_ops *fops; 8248 8249 if (flow_get_drv_type(dev, NULL) != MLX5_FLOW_TYPE_HW) { 8250 rte_flow_error_set(error, ENOTSUP, 8251 RTE_FLOW_ERROR_TYPE_UNSPECIFIED, 8252 NULL, 8253 "action create with incorrect steering mode"); 8254 return NULL; 8255 } 8256 fops = flow_get_drv_ops(MLX5_FLOW_TYPE_HW); 8257 return fops->actions_template_create(dev, attr, actions, masks, error); 8258 } 8259 8260 /** 8261 * Destroy flow action template. 8262 * 8263 * @param[in] dev 8264 * Pointer to the rte_eth_dev structure. 8265 * @param[in] template 8266 * Pointer to the action template to be destroyed. 8267 * @param[out] error 8268 * Pointer to error structure. 8269 * 8270 * @return 8271 * 0 on success, a negative errno value otherwise and rte_errno is set. 8272 */ 8273 static int 8274 mlx5_flow_actions_template_destroy(struct rte_eth_dev *dev, 8275 struct rte_flow_actions_template *template, 8276 struct rte_flow_error *error) 8277 { 8278 const struct mlx5_flow_driver_ops *fops; 8279 8280 if (flow_get_drv_type(dev, NULL) != MLX5_FLOW_TYPE_HW) 8281 return rte_flow_error_set(error, ENOTSUP, 8282 RTE_FLOW_ERROR_TYPE_UNSPECIFIED, 8283 NULL, 8284 "action destroy with incorrect steering mode"); 8285 fops = flow_get_drv_ops(MLX5_FLOW_TYPE_HW); 8286 return fops->actions_template_destroy(dev, template, error); 8287 } 8288 8289 /** 8290 * Create flow table. 8291 * 8292 * @param[in] dev 8293 * Pointer to the rte_eth_dev structure. 8294 * @param[in] attr 8295 * Pointer to the table attributes. 8296 * @param[in] item_templates 8297 * Item template array to be binded to the table. 8298 * @param[in] nb_item_templates 8299 * Number of item template. 8300 * @param[in] action_templates 8301 * Action template array to be binded to the table. 8302 * @param[in] nb_action_templates 8303 * Number of action template. 8304 * @param[out] error 8305 * Pointer to error structure. 8306 * 8307 * @return 8308 * Table on success, NULL otherwise and rte_errno is set. 8309 */ 8310 static struct rte_flow_template_table * 8311 mlx5_flow_table_create(struct rte_eth_dev *dev, 8312 const struct rte_flow_template_table_attr *attr, 8313 struct rte_flow_pattern_template *item_templates[], 8314 uint8_t nb_item_templates, 8315 struct rte_flow_actions_template *action_templates[], 8316 uint8_t nb_action_templates, 8317 struct rte_flow_error *error) 8318 { 8319 const struct mlx5_flow_driver_ops *fops; 8320 8321 if (flow_get_drv_type(dev, NULL) != MLX5_FLOW_TYPE_HW) { 8322 rte_flow_error_set(error, ENOTSUP, 8323 RTE_FLOW_ERROR_TYPE_UNSPECIFIED, 8324 NULL, 8325 "table create with incorrect steering mode"); 8326 return NULL; 8327 } 8328 fops = flow_get_drv_ops(MLX5_FLOW_TYPE_HW); 8329 return fops->template_table_create(dev, 8330 attr, 8331 item_templates, 8332 nb_item_templates, 8333 action_templates, 8334 nb_action_templates, 8335 error); 8336 } 8337 8338 /** 8339 * PMD destroy flow table. 8340 * 8341 * @param[in] dev 8342 * Pointer to the rte_eth_dev structure. 8343 * @param[in] table 8344 * Pointer to the table to be destroyed. 8345 * @param[out] error 8346 * Pointer to error structure. 8347 * 8348 * @return 8349 * 0 on success, a negative errno value otherwise and rte_errno is set. 8350 */ 8351 static int 8352 mlx5_flow_table_destroy(struct rte_eth_dev *dev, 8353 struct rte_flow_template_table *table, 8354 struct rte_flow_error *error) 8355 { 8356 const struct mlx5_flow_driver_ops *fops; 8357 8358 if (flow_get_drv_type(dev, NULL) != MLX5_FLOW_TYPE_HW) 8359 return rte_flow_error_set(error, ENOTSUP, 8360 RTE_FLOW_ERROR_TYPE_UNSPECIFIED, 8361 NULL, 8362 "table destroy with incorrect steering mode"); 8363 fops = flow_get_drv_ops(MLX5_FLOW_TYPE_HW); 8364 return fops->template_table_destroy(dev, table, error); 8365 } 8366 8367 /** 8368 * Enqueue flow creation. 8369 * 8370 * @param[in] dev 8371 * Pointer to the rte_eth_dev structure. 8372 * @param[in] queue_id 8373 * The queue to create the flow. 8374 * @param[in] attr 8375 * Pointer to the flow operation attributes. 8376 * @param[in] items 8377 * Items with flow spec value. 8378 * @param[in] pattern_template_index 8379 * The item pattern flow follows from the table. 8380 * @param[in] actions 8381 * Action with flow spec value. 8382 * @param[in] action_template_index 8383 * The action pattern flow follows from the table. 8384 * @param[in] user_data 8385 * Pointer to the user_data. 8386 * @param[out] error 8387 * Pointer to error structure. 8388 * 8389 * @return 8390 * Flow pointer on success, NULL otherwise and rte_errno is set. 8391 */ 8392 static struct rte_flow * 8393 mlx5_flow_async_flow_create(struct rte_eth_dev *dev, 8394 uint32_t queue_id, 8395 const struct rte_flow_op_attr *attr, 8396 struct rte_flow_template_table *table, 8397 const struct rte_flow_item items[], 8398 uint8_t pattern_template_index, 8399 const struct rte_flow_action actions[], 8400 uint8_t action_template_index, 8401 void *user_data, 8402 struct rte_flow_error *error) 8403 { 8404 const struct mlx5_flow_driver_ops *fops; 8405 8406 if (flow_get_drv_type(dev, NULL) != MLX5_FLOW_TYPE_HW) { 8407 rte_flow_error_set(error, ENOTSUP, 8408 RTE_FLOW_ERROR_TYPE_UNSPECIFIED, 8409 NULL, 8410 "flow_q create with incorrect steering mode"); 8411 return NULL; 8412 } 8413 fops = flow_get_drv_ops(MLX5_FLOW_TYPE_HW); 8414 return fops->async_flow_create(dev, queue_id, attr, table, 8415 items, pattern_template_index, 8416 actions, action_template_index, 8417 user_data, error); 8418 } 8419 8420 /** 8421 * Enqueue flow destruction. 8422 * 8423 * @param[in] dev 8424 * Pointer to the rte_eth_dev structure. 8425 * @param[in] queue 8426 * The queue to destroy the flow. 8427 * @param[in] attr 8428 * Pointer to the flow operation attributes. 8429 * @param[in] flow 8430 * Pointer to the flow to be destroyed. 8431 * @param[in] user_data 8432 * Pointer to the user_data. 8433 * @param[out] error 8434 * Pointer to error structure. 8435 * 8436 * @return 8437 * 0 on success, negative value otherwise and rte_errno is set. 8438 */ 8439 static int 8440 mlx5_flow_async_flow_destroy(struct rte_eth_dev *dev, 8441 uint32_t queue, 8442 const struct rte_flow_op_attr *attr, 8443 struct rte_flow *flow, 8444 void *user_data, 8445 struct rte_flow_error *error) 8446 { 8447 const struct mlx5_flow_driver_ops *fops; 8448 8449 if (flow_get_drv_type(dev, NULL) != MLX5_FLOW_TYPE_HW) 8450 return rte_flow_error_set(error, ENOTSUP, 8451 RTE_FLOW_ERROR_TYPE_UNSPECIFIED, 8452 NULL, 8453 "flow_q destroy with incorrect steering mode"); 8454 fops = flow_get_drv_ops(MLX5_FLOW_TYPE_HW); 8455 return fops->async_flow_destroy(dev, queue, attr, flow, 8456 user_data, error); 8457 } 8458 8459 /** 8460 * Pull the enqueued flows. 8461 * 8462 * @param[in] dev 8463 * Pointer to the rte_eth_dev structure. 8464 * @param[in] queue 8465 * The queue to pull the result. 8466 * @param[in/out] res 8467 * Array to save the results. 8468 * @param[in] n_res 8469 * Available result with the array. 8470 * @param[out] error 8471 * Pointer to error structure. 8472 * 8473 * @return 8474 * Result number on success, negative value otherwise and rte_errno is set. 8475 */ 8476 static int 8477 mlx5_flow_pull(struct rte_eth_dev *dev, 8478 uint32_t queue, 8479 struct rte_flow_op_result res[], 8480 uint16_t n_res, 8481 struct rte_flow_error *error) 8482 { 8483 const struct mlx5_flow_driver_ops *fops; 8484 8485 if (flow_get_drv_type(dev, NULL) != MLX5_FLOW_TYPE_HW) 8486 return rte_flow_error_set(error, ENOTSUP, 8487 RTE_FLOW_ERROR_TYPE_UNSPECIFIED, 8488 NULL, 8489 "flow_q pull with incorrect steering mode"); 8490 fops = flow_get_drv_ops(MLX5_FLOW_TYPE_HW); 8491 return fops->pull(dev, queue, res, n_res, error); 8492 } 8493 8494 /** 8495 * Push the enqueued flows. 8496 * 8497 * @param[in] dev 8498 * Pointer to the rte_eth_dev structure. 8499 * @param[in] queue 8500 * The queue to push the flows. 8501 * @param[out] error 8502 * Pointer to error structure. 8503 * 8504 * @return 8505 * 0 on success, negative value otherwise and rte_errno is set. 8506 */ 8507 static int 8508 mlx5_flow_push(struct rte_eth_dev *dev, 8509 uint32_t queue, 8510 struct rte_flow_error *error) 8511 { 8512 const struct mlx5_flow_driver_ops *fops; 8513 8514 if (flow_get_drv_type(dev, NULL) != MLX5_FLOW_TYPE_HW) 8515 return rte_flow_error_set(error, ENOTSUP, 8516 RTE_FLOW_ERROR_TYPE_UNSPECIFIED, 8517 NULL, 8518 "flow_q push with incorrect steering mode"); 8519 fops = flow_get_drv_ops(MLX5_FLOW_TYPE_HW); 8520 return fops->push(dev, queue, error); 8521 } 8522 8523 /** 8524 * Create shared action. 8525 * 8526 * @param[in] dev 8527 * Pointer to the rte_eth_dev structure. 8528 * @param[in] queue 8529 * Which queue to be used.. 8530 * @param[in] attr 8531 * Operation attribute. 8532 * @param[in] conf 8533 * Indirect action configuration. 8534 * @param[in] action 8535 * rte_flow action detail. 8536 * @param[in] user_data 8537 * Pointer to the user_data. 8538 * @param[out] error 8539 * Pointer to error structure. 8540 * 8541 * @return 8542 * Action handle on success, NULL otherwise and rte_errno is set. 8543 */ 8544 static struct rte_flow_action_handle * 8545 mlx5_flow_async_action_handle_create(struct rte_eth_dev *dev, uint32_t queue, 8546 const struct rte_flow_op_attr *attr, 8547 const struct rte_flow_indir_action_conf *conf, 8548 const struct rte_flow_action *action, 8549 void *user_data, 8550 struct rte_flow_error *error) 8551 { 8552 const struct mlx5_flow_driver_ops *fops = 8553 flow_get_drv_ops(MLX5_FLOW_TYPE_HW); 8554 8555 return fops->async_action_create(dev, queue, attr, conf, action, 8556 user_data, error); 8557 } 8558 8559 /** 8560 * Update shared action. 8561 * 8562 * @param[in] dev 8563 * Pointer to the rte_eth_dev structure. 8564 * @param[in] queue 8565 * Which queue to be used.. 8566 * @param[in] attr 8567 * Operation attribute. 8568 * @param[in] handle 8569 * Action handle to be updated. 8570 * @param[in] update 8571 * Update value. 8572 * @param[in] user_data 8573 * Pointer to the user_data. 8574 * @param[out] error 8575 * Pointer to error structure. 8576 * 8577 * @return 8578 * 0 on success, negative value otherwise and rte_errno is set. 8579 */ 8580 static int 8581 mlx5_flow_async_action_handle_update(struct rte_eth_dev *dev, uint32_t queue, 8582 const struct rte_flow_op_attr *attr, 8583 struct rte_flow_action_handle *handle, 8584 const void *update, 8585 void *user_data, 8586 struct rte_flow_error *error) 8587 { 8588 const struct mlx5_flow_driver_ops *fops = 8589 flow_get_drv_ops(MLX5_FLOW_TYPE_HW); 8590 8591 return fops->async_action_update(dev, queue, attr, handle, 8592 update, user_data, error); 8593 } 8594 8595 /** 8596 * Destroy shared action. 8597 * 8598 * @param[in] dev 8599 * Pointer to the rte_eth_dev structure. 8600 * @param[in] queue 8601 * Which queue to be used.. 8602 * @param[in] attr 8603 * Operation attribute. 8604 * @param[in] handle 8605 * Action handle to be destroyed. 8606 * @param[in] user_data 8607 * Pointer to the user_data. 8608 * @param[out] error 8609 * Pointer to error structure. 8610 * 8611 * @return 8612 * 0 on success, negative value otherwise and rte_errno is set. 8613 */ 8614 static int 8615 mlx5_flow_async_action_handle_destroy(struct rte_eth_dev *dev, uint32_t queue, 8616 const struct rte_flow_op_attr *attr, 8617 struct rte_flow_action_handle *handle, 8618 void *user_data, 8619 struct rte_flow_error *error) 8620 { 8621 const struct mlx5_flow_driver_ops *fops = 8622 flow_get_drv_ops(MLX5_FLOW_TYPE_HW); 8623 8624 return fops->async_action_destroy(dev, queue, attr, handle, 8625 user_data, error); 8626 } 8627 8628 /** 8629 * Allocate a new memory for the counter values wrapped by all the needed 8630 * management. 8631 * 8632 * @param[in] sh 8633 * Pointer to mlx5_dev_ctx_shared object. 8634 * 8635 * @return 8636 * 0 on success, a negative errno value otherwise. 8637 */ 8638 static int 8639 mlx5_flow_create_counter_stat_mem_mng(struct mlx5_dev_ctx_shared *sh) 8640 { 8641 struct mlx5_counter_stats_mem_mng *mem_mng; 8642 volatile struct flow_counter_stats *raw_data; 8643 int raws_n = MLX5_CNT_CONTAINER_RESIZE + MLX5_MAX_PENDING_QUERIES; 8644 int size = (sizeof(struct flow_counter_stats) * 8645 MLX5_COUNTERS_PER_POOL + 8646 sizeof(struct mlx5_counter_stats_raw)) * raws_n + 8647 sizeof(struct mlx5_counter_stats_mem_mng); 8648 size_t pgsize = rte_mem_page_size(); 8649 uint8_t *mem; 8650 int ret; 8651 int i; 8652 8653 if (pgsize == (size_t)-1) { 8654 DRV_LOG(ERR, "Failed to get mem page size"); 8655 rte_errno = ENOMEM; 8656 return -ENOMEM; 8657 } 8658 mem = mlx5_malloc(MLX5_MEM_ZERO, size, pgsize, SOCKET_ID_ANY); 8659 if (!mem) { 8660 rte_errno = ENOMEM; 8661 return -ENOMEM; 8662 } 8663 mem_mng = (struct mlx5_counter_stats_mem_mng *)(mem + size) - 1; 8664 size = sizeof(*raw_data) * MLX5_COUNTERS_PER_POOL * raws_n; 8665 ret = mlx5_os_wrapped_mkey_create(sh->cdev->ctx, sh->cdev->pd, 8666 sh->cdev->pdn, mem, size, 8667 &mem_mng->wm); 8668 if (ret) { 8669 rte_errno = errno; 8670 mlx5_free(mem); 8671 return -rte_errno; 8672 } 8673 mem_mng->raws = (struct mlx5_counter_stats_raw *)(mem + size); 8674 raw_data = (volatile struct flow_counter_stats *)mem; 8675 for (i = 0; i < raws_n; ++i) { 8676 mem_mng->raws[i].mem_mng = mem_mng; 8677 mem_mng->raws[i].data = raw_data + i * MLX5_COUNTERS_PER_POOL; 8678 } 8679 for (i = 0; i < MLX5_MAX_PENDING_QUERIES; ++i) 8680 LIST_INSERT_HEAD(&sh->cmng.free_stat_raws, 8681 mem_mng->raws + MLX5_CNT_CONTAINER_RESIZE + i, 8682 next); 8683 LIST_INSERT_HEAD(&sh->cmng.mem_mngs, mem_mng, next); 8684 sh->cmng.mem_mng = mem_mng; 8685 return 0; 8686 } 8687 8688 /** 8689 * Set the statistic memory to the new counter pool. 8690 * 8691 * @param[in] sh 8692 * Pointer to mlx5_dev_ctx_shared object. 8693 * @param[in] pool 8694 * Pointer to the pool to set the statistic memory. 8695 * 8696 * @return 8697 * 0 on success, a negative errno value otherwise. 8698 */ 8699 static int 8700 mlx5_flow_set_counter_stat_mem(struct mlx5_dev_ctx_shared *sh, 8701 struct mlx5_flow_counter_pool *pool) 8702 { 8703 struct mlx5_flow_counter_mng *cmng = &sh->cmng; 8704 /* Resize statistic memory once used out. */ 8705 if (!(pool->index % MLX5_CNT_CONTAINER_RESIZE) && 8706 mlx5_flow_create_counter_stat_mem_mng(sh)) { 8707 DRV_LOG(ERR, "Cannot resize counter stat mem."); 8708 return -1; 8709 } 8710 rte_spinlock_lock(&pool->sl); 8711 pool->raw = cmng->mem_mng->raws + pool->index % 8712 MLX5_CNT_CONTAINER_RESIZE; 8713 rte_spinlock_unlock(&pool->sl); 8714 pool->raw_hw = NULL; 8715 return 0; 8716 } 8717 8718 #define MLX5_POOL_QUERY_FREQ_US 1000000 8719 8720 /** 8721 * Set the periodic procedure for triggering asynchronous batch queries for all 8722 * the counter pools. 8723 * 8724 * @param[in] sh 8725 * Pointer to mlx5_dev_ctx_shared object. 8726 */ 8727 void 8728 mlx5_set_query_alarm(struct mlx5_dev_ctx_shared *sh) 8729 { 8730 uint32_t pools_n, us; 8731 8732 pools_n = __atomic_load_n(&sh->cmng.n_valid, __ATOMIC_RELAXED); 8733 us = MLX5_POOL_QUERY_FREQ_US / pools_n; 8734 DRV_LOG(DEBUG, "Set alarm for %u pools each %u us", pools_n, us); 8735 if (rte_eal_alarm_set(us, mlx5_flow_query_alarm, sh)) { 8736 sh->cmng.query_thread_on = 0; 8737 DRV_LOG(ERR, "Cannot reinitialize query alarm"); 8738 } else { 8739 sh->cmng.query_thread_on = 1; 8740 } 8741 } 8742 8743 /** 8744 * The periodic procedure for triggering asynchronous batch queries for all the 8745 * counter pools. This function is probably called by the host thread. 8746 * 8747 * @param[in] arg 8748 * The parameter for the alarm process. 8749 */ 8750 void 8751 mlx5_flow_query_alarm(void *arg) 8752 { 8753 struct mlx5_dev_ctx_shared *sh = arg; 8754 int ret; 8755 uint16_t pool_index = sh->cmng.pool_index; 8756 struct mlx5_flow_counter_mng *cmng = &sh->cmng; 8757 struct mlx5_flow_counter_pool *pool; 8758 uint16_t n_valid; 8759 8760 if (sh->cmng.pending_queries >= MLX5_MAX_PENDING_QUERIES) 8761 goto set_alarm; 8762 rte_spinlock_lock(&cmng->pool_update_sl); 8763 pool = cmng->pools[pool_index]; 8764 n_valid = cmng->n_valid; 8765 rte_spinlock_unlock(&cmng->pool_update_sl); 8766 /* Set the statistic memory to the new created pool. */ 8767 if ((!pool->raw && mlx5_flow_set_counter_stat_mem(sh, pool))) 8768 goto set_alarm; 8769 if (pool->raw_hw) 8770 /* There is a pool query in progress. */ 8771 goto set_alarm; 8772 pool->raw_hw = 8773 LIST_FIRST(&sh->cmng.free_stat_raws); 8774 if (!pool->raw_hw) 8775 /* No free counter statistics raw memory. */ 8776 goto set_alarm; 8777 /* 8778 * Identify the counters released between query trigger and query 8779 * handle more efficiently. The counter released in this gap period 8780 * should wait for a new round of query as the new arrived packets 8781 * will not be taken into account. 8782 */ 8783 pool->query_gen++; 8784 ret = mlx5_devx_cmd_flow_counter_query(pool->min_dcs, 0, 8785 MLX5_COUNTERS_PER_POOL, 8786 NULL, NULL, 8787 pool->raw_hw->mem_mng->wm.lkey, 8788 (void *)(uintptr_t) 8789 pool->raw_hw->data, 8790 sh->devx_comp, 8791 (uint64_t)(uintptr_t)pool); 8792 if (ret) { 8793 DRV_LOG(ERR, "Failed to trigger asynchronous query for dcs ID" 8794 " %d", pool->min_dcs->id); 8795 pool->raw_hw = NULL; 8796 goto set_alarm; 8797 } 8798 LIST_REMOVE(pool->raw_hw, next); 8799 sh->cmng.pending_queries++; 8800 pool_index++; 8801 if (pool_index >= n_valid) 8802 pool_index = 0; 8803 set_alarm: 8804 sh->cmng.pool_index = pool_index; 8805 mlx5_set_query_alarm(sh); 8806 } 8807 8808 /** 8809 * Check and callback event for new aged flow in the counter pool 8810 * 8811 * @param[in] sh 8812 * Pointer to mlx5_dev_ctx_shared object. 8813 * @param[in] pool 8814 * Pointer to Current counter pool. 8815 */ 8816 static void 8817 mlx5_flow_aging_check(struct mlx5_dev_ctx_shared *sh, 8818 struct mlx5_flow_counter_pool *pool) 8819 { 8820 struct mlx5_priv *priv; 8821 struct mlx5_flow_counter *cnt; 8822 struct mlx5_age_info *age_info; 8823 struct mlx5_age_param *age_param; 8824 struct mlx5_counter_stats_raw *cur = pool->raw_hw; 8825 struct mlx5_counter_stats_raw *prev = pool->raw; 8826 const uint64_t curr_time = MLX5_CURR_TIME_SEC; 8827 const uint32_t time_delta = curr_time - pool->time_of_last_age_check; 8828 uint16_t expected = AGE_CANDIDATE; 8829 uint32_t i; 8830 8831 pool->time_of_last_age_check = curr_time; 8832 for (i = 0; i < MLX5_COUNTERS_PER_POOL; ++i) { 8833 cnt = MLX5_POOL_GET_CNT(pool, i); 8834 age_param = MLX5_CNT_TO_AGE(cnt); 8835 if (__atomic_load_n(&age_param->state, 8836 __ATOMIC_RELAXED) != AGE_CANDIDATE) 8837 continue; 8838 if (cur->data[i].hits != prev->data[i].hits) { 8839 __atomic_store_n(&age_param->sec_since_last_hit, 0, 8840 __ATOMIC_RELAXED); 8841 continue; 8842 } 8843 if (__atomic_add_fetch(&age_param->sec_since_last_hit, 8844 time_delta, 8845 __ATOMIC_RELAXED) <= age_param->timeout) 8846 continue; 8847 /** 8848 * Hold the lock first, or if between the 8849 * state AGE_TMOUT and tailq operation the 8850 * release happened, the release procedure 8851 * may delete a non-existent tailq node. 8852 */ 8853 priv = rte_eth_devices[age_param->port_id].data->dev_private; 8854 age_info = GET_PORT_AGE_INFO(priv); 8855 rte_spinlock_lock(&age_info->aged_sl); 8856 if (__atomic_compare_exchange_n(&age_param->state, &expected, 8857 AGE_TMOUT, false, 8858 __ATOMIC_RELAXED, 8859 __ATOMIC_RELAXED)) { 8860 TAILQ_INSERT_TAIL(&age_info->aged_counters, cnt, next); 8861 MLX5_AGE_SET(age_info, MLX5_AGE_EVENT_NEW); 8862 } 8863 rte_spinlock_unlock(&age_info->aged_sl); 8864 } 8865 mlx5_age_event_prepare(sh); 8866 } 8867 8868 /** 8869 * Handler for the HW respond about ready values from an asynchronous batch 8870 * query. This function is probably called by the host thread. 8871 * 8872 * @param[in] sh 8873 * The pointer to the shared device context. 8874 * @param[in] async_id 8875 * The Devx async ID. 8876 * @param[in] status 8877 * The status of the completion. 8878 */ 8879 void 8880 mlx5_flow_async_pool_query_handle(struct mlx5_dev_ctx_shared *sh, 8881 uint64_t async_id, int status) 8882 { 8883 struct mlx5_flow_counter_pool *pool = 8884 (struct mlx5_flow_counter_pool *)(uintptr_t)async_id; 8885 struct mlx5_counter_stats_raw *raw_to_free; 8886 uint8_t query_gen = pool->query_gen ^ 1; 8887 struct mlx5_flow_counter_mng *cmng = &sh->cmng; 8888 enum mlx5_counter_type cnt_type = 8889 pool->is_aged ? MLX5_COUNTER_TYPE_AGE : 8890 MLX5_COUNTER_TYPE_ORIGIN; 8891 8892 if (unlikely(status)) { 8893 raw_to_free = pool->raw_hw; 8894 } else { 8895 raw_to_free = pool->raw; 8896 if (pool->is_aged) 8897 mlx5_flow_aging_check(sh, pool); 8898 rte_spinlock_lock(&pool->sl); 8899 pool->raw = pool->raw_hw; 8900 rte_spinlock_unlock(&pool->sl); 8901 /* Be sure the new raw counters data is updated in memory. */ 8902 rte_io_wmb(); 8903 if (!TAILQ_EMPTY(&pool->counters[query_gen])) { 8904 rte_spinlock_lock(&cmng->csl[cnt_type]); 8905 TAILQ_CONCAT(&cmng->counters[cnt_type], 8906 &pool->counters[query_gen], next); 8907 rte_spinlock_unlock(&cmng->csl[cnt_type]); 8908 } 8909 } 8910 LIST_INSERT_HEAD(&sh->cmng.free_stat_raws, raw_to_free, next); 8911 pool->raw_hw = NULL; 8912 sh->cmng.pending_queries--; 8913 } 8914 8915 static int 8916 flow_group_to_table(uint32_t port_id, uint32_t group, uint32_t *table, 8917 const struct flow_grp_info *grp_info, 8918 struct rte_flow_error *error) 8919 { 8920 if (grp_info->transfer && grp_info->external && 8921 grp_info->fdb_def_rule) { 8922 if (group == UINT32_MAX) 8923 return rte_flow_error_set 8924 (error, EINVAL, 8925 RTE_FLOW_ERROR_TYPE_ATTR_GROUP, 8926 NULL, 8927 "group index not supported"); 8928 *table = group + 1; 8929 } else { 8930 *table = group; 8931 } 8932 DRV_LOG(DEBUG, "port %u group=%#x table=%#x", port_id, group, *table); 8933 return 0; 8934 } 8935 8936 /** 8937 * Translate the rte_flow group index to HW table value. 8938 * 8939 * If tunnel offload is disabled, all group ids converted to flow table 8940 * id using the standard method. 8941 * If tunnel offload is enabled, group id can be converted using the 8942 * standard or tunnel conversion method. Group conversion method 8943 * selection depends on flags in `grp_info` parameter: 8944 * - Internal (grp_info.external == 0) groups conversion uses the 8945 * standard method. 8946 * - Group ids in JUMP action converted with the tunnel conversion. 8947 * - Group id in rule attribute conversion depends on a rule type and 8948 * group id value: 8949 * ** non zero group attributes converted with the tunnel method 8950 * ** zero group attribute in non-tunnel rule is converted using the 8951 * standard method - there's only one root table 8952 * ** zero group attribute in steer tunnel rule is converted with the 8953 * standard method - single root table 8954 * ** zero group attribute in match tunnel rule is a special OvS 8955 * case: that value is used for portability reasons. That group 8956 * id is converted with the tunnel conversion method. 8957 * 8958 * @param[in] dev 8959 * Port device 8960 * @param[in] tunnel 8961 * PMD tunnel offload object 8962 * @param[in] group 8963 * rte_flow group index value. 8964 * @param[out] table 8965 * HW table value. 8966 * @param[in] grp_info 8967 * flags used for conversion 8968 * @param[out] error 8969 * Pointer to error structure. 8970 * 8971 * @return 8972 * 0 on success, a negative errno value otherwise and rte_errno is set. 8973 */ 8974 int 8975 mlx5_flow_group_to_table(struct rte_eth_dev *dev, 8976 const struct mlx5_flow_tunnel *tunnel, 8977 uint32_t group, uint32_t *table, 8978 const struct flow_grp_info *grp_info, 8979 struct rte_flow_error *error) 8980 { 8981 int ret; 8982 bool standard_translation; 8983 8984 if (!grp_info->skip_scale && grp_info->external && 8985 group < MLX5_MAX_TABLES_EXTERNAL) 8986 group *= MLX5_FLOW_TABLE_FACTOR; 8987 if (is_tunnel_offload_active(dev)) { 8988 standard_translation = !grp_info->external || 8989 grp_info->std_tbl_fix; 8990 } else { 8991 standard_translation = true; 8992 } 8993 DRV_LOG(DEBUG, 8994 "port %u group=%u transfer=%d external=%d fdb_def_rule=%d translate=%s", 8995 dev->data->port_id, group, grp_info->transfer, 8996 grp_info->external, grp_info->fdb_def_rule, 8997 standard_translation ? "STANDARD" : "TUNNEL"); 8998 if (standard_translation) 8999 ret = flow_group_to_table(dev->data->port_id, group, table, 9000 grp_info, error); 9001 else 9002 ret = tunnel_flow_group_to_flow_table(dev, tunnel, group, 9003 table, error); 9004 9005 return ret; 9006 } 9007 9008 /** 9009 * Discover availability of metadata reg_c's. 9010 * 9011 * Iteratively use test flows to check availability. 9012 * 9013 * @param[in] dev 9014 * Pointer to the Ethernet device structure. 9015 * 9016 * @return 9017 * 0 on success, a negative errno value otherwise and rte_errno is set. 9018 */ 9019 int 9020 mlx5_flow_discover_mreg_c(struct rte_eth_dev *dev) 9021 { 9022 struct mlx5_priv *priv = dev->data->dev_private; 9023 enum modify_reg idx; 9024 int n = 0; 9025 9026 /* reg_c[0] and reg_c[1] are reserved. */ 9027 priv->sh->flow_mreg_c[n++] = REG_C_0; 9028 priv->sh->flow_mreg_c[n++] = REG_C_1; 9029 /* Discover availability of other reg_c's. */ 9030 for (idx = REG_C_2; idx <= REG_C_7; ++idx) { 9031 struct rte_flow_attr attr = { 9032 .group = MLX5_FLOW_MREG_CP_TABLE_GROUP, 9033 .priority = MLX5_FLOW_LOWEST_PRIO_INDICATOR, 9034 .ingress = 1, 9035 }; 9036 struct rte_flow_item items[] = { 9037 [0] = { 9038 .type = RTE_FLOW_ITEM_TYPE_END, 9039 }, 9040 }; 9041 struct rte_flow_action actions[] = { 9042 [0] = { 9043 .type = (enum rte_flow_action_type) 9044 MLX5_RTE_FLOW_ACTION_TYPE_COPY_MREG, 9045 .conf = &(struct mlx5_flow_action_copy_mreg){ 9046 .src = REG_C_1, 9047 .dst = idx, 9048 }, 9049 }, 9050 [1] = { 9051 .type = RTE_FLOW_ACTION_TYPE_JUMP, 9052 .conf = &(struct rte_flow_action_jump){ 9053 .group = MLX5_FLOW_MREG_ACT_TABLE_GROUP, 9054 }, 9055 }, 9056 [2] = { 9057 .type = RTE_FLOW_ACTION_TYPE_END, 9058 }, 9059 }; 9060 uint32_t flow_idx; 9061 struct rte_flow *flow; 9062 struct rte_flow_error error; 9063 9064 if (!priv->sh->config.dv_flow_en) 9065 break; 9066 /* Create internal flow, validation skips copy action. */ 9067 flow_idx = flow_list_create(dev, MLX5_FLOW_TYPE_GEN, &attr, 9068 items, actions, false, &error); 9069 flow = mlx5_ipool_get(priv->flows[MLX5_FLOW_TYPE_GEN], 9070 flow_idx); 9071 if (!flow) 9072 continue; 9073 priv->sh->flow_mreg_c[n++] = idx; 9074 flow_list_destroy(dev, MLX5_FLOW_TYPE_GEN, flow_idx); 9075 } 9076 for (; n < MLX5_MREG_C_NUM; ++n) 9077 priv->sh->flow_mreg_c[n] = REG_NON; 9078 priv->sh->metadata_regc_check_flag = 1; 9079 return 0; 9080 } 9081 9082 int 9083 save_dump_file(const uint8_t *data, uint32_t size, 9084 uint32_t type, uint64_t id, void *arg, FILE *file) 9085 { 9086 char line[BUF_SIZE]; 9087 uint32_t out = 0; 9088 uint32_t k; 9089 uint32_t actions_num; 9090 struct rte_flow_query_count *count; 9091 9092 memset(line, 0, BUF_SIZE); 9093 switch (type) { 9094 case DR_DUMP_REC_TYPE_PMD_MODIFY_HDR: 9095 actions_num = *(uint32_t *)(arg); 9096 out += snprintf(line + out, BUF_SIZE - out, "%d,0x%" PRIx64 ",%d,", 9097 type, id, actions_num); 9098 break; 9099 case DR_DUMP_REC_TYPE_PMD_PKT_REFORMAT: 9100 out += snprintf(line + out, BUF_SIZE - out, "%d,0x%" PRIx64 ",", 9101 type, id); 9102 break; 9103 case DR_DUMP_REC_TYPE_PMD_COUNTER: 9104 count = (struct rte_flow_query_count *)arg; 9105 fprintf(file, 9106 "%d,0x%" PRIx64 ",%" PRIu64 ",%" PRIu64 "\n", 9107 type, id, count->hits, count->bytes); 9108 return 0; 9109 default: 9110 return -1; 9111 } 9112 9113 for (k = 0; k < size; k++) { 9114 /* Make sure we do not overrun the line buffer length. */ 9115 if (out >= BUF_SIZE - 4) { 9116 line[out] = '\0'; 9117 break; 9118 } 9119 out += snprintf(line + out, BUF_SIZE - out, "%02x", 9120 (data[k]) & 0xff); 9121 } 9122 fprintf(file, "%s\n", line); 9123 return 0; 9124 } 9125 9126 int 9127 mlx5_flow_query_counter(struct rte_eth_dev *dev, struct rte_flow *flow, 9128 struct rte_flow_query_count *count, struct rte_flow_error *error) 9129 { 9130 struct rte_flow_action action[2]; 9131 enum mlx5_flow_drv_type ftype; 9132 const struct mlx5_flow_driver_ops *fops; 9133 9134 if (!flow) { 9135 return rte_flow_error_set(error, ENOENT, 9136 RTE_FLOW_ERROR_TYPE_UNSPECIFIED, 9137 NULL, 9138 "invalid flow handle"); 9139 } 9140 action[0].type = RTE_FLOW_ACTION_TYPE_COUNT; 9141 action[1].type = RTE_FLOW_ACTION_TYPE_END; 9142 if (flow->counter) { 9143 memset(count, 0, sizeof(struct rte_flow_query_count)); 9144 ftype = (enum mlx5_flow_drv_type)(flow->drv_type); 9145 MLX5_ASSERT(ftype > MLX5_FLOW_TYPE_MIN && 9146 ftype < MLX5_FLOW_TYPE_MAX); 9147 fops = flow_get_drv_ops(ftype); 9148 return fops->query(dev, flow, action, count, error); 9149 } 9150 return -1; 9151 } 9152 9153 #ifdef HAVE_IBV_FLOW_DV_SUPPORT 9154 /** 9155 * Dump flow ipool data to file 9156 * 9157 * @param[in] dev 9158 * The pointer to Ethernet device. 9159 * @param[in] file 9160 * A pointer to a file for output. 9161 * @param[out] error 9162 * Perform verbose error reporting if not NULL. PMDs initialize this 9163 * structure in case of error only. 9164 * @return 9165 * 0 on success, a negative value otherwise. 9166 */ 9167 int 9168 mlx5_flow_dev_dump_ipool(struct rte_eth_dev *dev, 9169 struct rte_flow *flow, FILE *file, 9170 struct rte_flow_error *error) 9171 { 9172 struct mlx5_priv *priv = dev->data->dev_private; 9173 struct mlx5_flow_dv_modify_hdr_resource *modify_hdr; 9174 struct mlx5_flow_dv_encap_decap_resource *encap_decap; 9175 uint32_t handle_idx; 9176 struct mlx5_flow_handle *dh; 9177 struct rte_flow_query_count count; 9178 uint32_t actions_num; 9179 const uint8_t *data; 9180 size_t size; 9181 uint64_t id; 9182 uint32_t type; 9183 void *action = NULL; 9184 9185 if (!flow) { 9186 return rte_flow_error_set(error, ENOENT, 9187 RTE_FLOW_ERROR_TYPE_UNSPECIFIED, 9188 NULL, 9189 "invalid flow handle"); 9190 } 9191 handle_idx = flow->dev_handles; 9192 /* query counter */ 9193 if (flow->counter && 9194 (!mlx5_counter_query(dev, flow->counter, false, 9195 &count.hits, &count.bytes, &action)) && action) { 9196 id = (uint64_t)(uintptr_t)action; 9197 type = DR_DUMP_REC_TYPE_PMD_COUNTER; 9198 save_dump_file(NULL, 0, type, 9199 id, (void *)&count, file); 9200 } 9201 9202 while (handle_idx) { 9203 dh = mlx5_ipool_get(priv->sh->ipool 9204 [MLX5_IPOOL_MLX5_FLOW], handle_idx); 9205 if (!dh) 9206 continue; 9207 handle_idx = dh->next.next; 9208 9209 /* Get modify_hdr and encap_decap buf from ipools. */ 9210 encap_decap = NULL; 9211 modify_hdr = dh->dvh.modify_hdr; 9212 9213 if (dh->dvh.rix_encap_decap) { 9214 encap_decap = mlx5_ipool_get(priv->sh->ipool 9215 [MLX5_IPOOL_DECAP_ENCAP], 9216 dh->dvh.rix_encap_decap); 9217 } 9218 if (modify_hdr) { 9219 data = (const uint8_t *)modify_hdr->actions; 9220 size = (size_t)(modify_hdr->actions_num) * 8; 9221 id = (uint64_t)(uintptr_t)modify_hdr->action; 9222 actions_num = modify_hdr->actions_num; 9223 type = DR_DUMP_REC_TYPE_PMD_MODIFY_HDR; 9224 save_dump_file(data, size, type, id, 9225 (void *)(&actions_num), file); 9226 } 9227 if (encap_decap) { 9228 data = encap_decap->buf; 9229 size = encap_decap->size; 9230 id = (uint64_t)(uintptr_t)encap_decap->action; 9231 type = DR_DUMP_REC_TYPE_PMD_PKT_REFORMAT; 9232 save_dump_file(data, size, type, 9233 id, NULL, file); 9234 } 9235 } 9236 return 0; 9237 } 9238 9239 /** 9240 * Dump all flow's encap_decap/modify_hdr/counter data to file 9241 * 9242 * @param[in] dev 9243 * The pointer to Ethernet device. 9244 * @param[in] file 9245 * A pointer to a file for output. 9246 * @param[out] error 9247 * Perform verbose error reporting if not NULL. PMDs initialize this 9248 * structure in case of error only. 9249 * @return 9250 * 0 on success, a negative value otherwise. 9251 */ 9252 static int 9253 mlx5_flow_dev_dump_sh_all(struct rte_eth_dev *dev, 9254 FILE *file, struct rte_flow_error *error __rte_unused) 9255 { 9256 struct mlx5_priv *priv = dev->data->dev_private; 9257 struct mlx5_dev_ctx_shared *sh = priv->sh; 9258 struct mlx5_hlist *h; 9259 struct mlx5_flow_dv_modify_hdr_resource *modify_hdr; 9260 struct mlx5_flow_dv_encap_decap_resource *encap_decap; 9261 struct rte_flow_query_count count; 9262 uint32_t actions_num; 9263 const uint8_t *data; 9264 size_t size; 9265 uint64_t id; 9266 uint32_t type; 9267 uint32_t i; 9268 uint32_t j; 9269 struct mlx5_list_inconst *l_inconst; 9270 struct mlx5_list_entry *e; 9271 int lcore_index; 9272 struct mlx5_flow_counter_mng *cmng = &priv->sh->cmng; 9273 uint32_t max; 9274 void *action; 9275 9276 /* encap_decap hlist is lcore_share, get global core cache. */ 9277 i = MLX5_LIST_GLOBAL; 9278 h = sh->encaps_decaps; 9279 if (h) { 9280 for (j = 0; j <= h->mask; j++) { 9281 l_inconst = &h->buckets[j].l; 9282 if (!l_inconst || !l_inconst->cache[i]) 9283 continue; 9284 9285 e = LIST_FIRST(&l_inconst->cache[i]->h); 9286 while (e) { 9287 encap_decap = 9288 (struct mlx5_flow_dv_encap_decap_resource *)e; 9289 data = encap_decap->buf; 9290 size = encap_decap->size; 9291 id = (uint64_t)(uintptr_t)encap_decap->action; 9292 type = DR_DUMP_REC_TYPE_PMD_PKT_REFORMAT; 9293 save_dump_file(data, size, type, 9294 id, NULL, file); 9295 e = LIST_NEXT(e, next); 9296 } 9297 } 9298 } 9299 9300 /* get modify_hdr */ 9301 h = sh->modify_cmds; 9302 if (h) { 9303 lcore_index = rte_lcore_index(rte_lcore_id()); 9304 if (unlikely(lcore_index == -1)) { 9305 lcore_index = MLX5_LIST_NLCORE; 9306 rte_spinlock_lock(&h->l_const.lcore_lock); 9307 } 9308 i = lcore_index; 9309 9310 for (j = 0; j <= h->mask; j++) { 9311 l_inconst = &h->buckets[j].l; 9312 if (!l_inconst || !l_inconst->cache[i]) 9313 continue; 9314 9315 e = LIST_FIRST(&l_inconst->cache[i]->h); 9316 while (e) { 9317 modify_hdr = 9318 (struct mlx5_flow_dv_modify_hdr_resource *)e; 9319 data = (const uint8_t *)modify_hdr->actions; 9320 size = (size_t)(modify_hdr->actions_num) * 8; 9321 actions_num = modify_hdr->actions_num; 9322 id = (uint64_t)(uintptr_t)modify_hdr->action; 9323 type = DR_DUMP_REC_TYPE_PMD_MODIFY_HDR; 9324 save_dump_file(data, size, type, id, 9325 (void *)(&actions_num), file); 9326 e = LIST_NEXT(e, next); 9327 } 9328 } 9329 9330 if (unlikely(lcore_index == MLX5_LIST_NLCORE)) 9331 rte_spinlock_unlock(&h->l_const.lcore_lock); 9332 } 9333 9334 /* get counter */ 9335 MLX5_ASSERT(cmng->n_valid <= cmng->n); 9336 max = MLX5_COUNTERS_PER_POOL * cmng->n_valid; 9337 for (j = 1; j <= max; j++) { 9338 action = NULL; 9339 if ((!mlx5_counter_query(dev, j, false, &count.hits, 9340 &count.bytes, &action)) && action) { 9341 id = (uint64_t)(uintptr_t)action; 9342 type = DR_DUMP_REC_TYPE_PMD_COUNTER; 9343 save_dump_file(NULL, 0, type, 9344 id, (void *)&count, file); 9345 } 9346 } 9347 return 0; 9348 } 9349 #endif 9350 9351 /** 9352 * Dump flow raw hw data to file 9353 * 9354 * @param[in] dev 9355 * The pointer to Ethernet device. 9356 * @param[in] file 9357 * A pointer to a file for output. 9358 * @param[out] error 9359 * Perform verbose error reporting if not NULL. PMDs initialize this 9360 * structure in case of error only. 9361 * @return 9362 * 0 on success, a negative value otherwise. 9363 */ 9364 int 9365 mlx5_flow_dev_dump(struct rte_eth_dev *dev, struct rte_flow *flow_idx, 9366 FILE *file, 9367 struct rte_flow_error *error __rte_unused) 9368 { 9369 struct mlx5_priv *priv = dev->data->dev_private; 9370 struct mlx5_dev_ctx_shared *sh = priv->sh; 9371 uint32_t handle_idx; 9372 int ret; 9373 struct mlx5_flow_handle *dh; 9374 struct rte_flow *flow; 9375 9376 if (!sh->config.dv_flow_en) { 9377 if (fputs("device dv flow disabled\n", file) <= 0) 9378 return -errno; 9379 return -ENOTSUP; 9380 } 9381 9382 /* dump all */ 9383 if (!flow_idx) { 9384 #ifdef HAVE_IBV_FLOW_DV_SUPPORT 9385 if (mlx5_flow_dev_dump_sh_all(dev, file, error)) 9386 return -EINVAL; 9387 #endif 9388 return mlx5_devx_cmd_flow_dump(sh->fdb_domain, 9389 sh->rx_domain, 9390 sh->tx_domain, file); 9391 } 9392 /* dump one */ 9393 flow = mlx5_ipool_get(priv->flows[MLX5_FLOW_TYPE_GEN], 9394 (uintptr_t)(void *)flow_idx); 9395 if (!flow) 9396 return -EINVAL; 9397 9398 #ifdef HAVE_IBV_FLOW_DV_SUPPORT 9399 mlx5_flow_dev_dump_ipool(dev, flow, file, error); 9400 #endif 9401 handle_idx = flow->dev_handles; 9402 while (handle_idx) { 9403 dh = mlx5_ipool_get(priv->sh->ipool[MLX5_IPOOL_MLX5_FLOW], 9404 handle_idx); 9405 if (!dh) 9406 return -ENOENT; 9407 if (dh->drv_flow) { 9408 ret = mlx5_devx_cmd_flow_single_dump(dh->drv_flow, 9409 file); 9410 if (ret) 9411 return -ENOENT; 9412 } 9413 handle_idx = dh->next.next; 9414 } 9415 return 0; 9416 } 9417 9418 /** 9419 * Get aged-out flows. 9420 * 9421 * @param[in] dev 9422 * Pointer to the Ethernet device structure. 9423 * @param[in] context 9424 * The address of an array of pointers to the aged-out flows contexts. 9425 * @param[in] nb_countexts 9426 * The length of context array pointers. 9427 * @param[out] error 9428 * Perform verbose error reporting if not NULL. Initialized in case of 9429 * error only. 9430 * 9431 * @return 9432 * how many contexts get in success, otherwise negative errno value. 9433 * if nb_contexts is 0, return the amount of all aged contexts. 9434 * if nb_contexts is not 0 , return the amount of aged flows reported 9435 * in the context array. 9436 */ 9437 int 9438 mlx5_flow_get_aged_flows(struct rte_eth_dev *dev, void **contexts, 9439 uint32_t nb_contexts, struct rte_flow_error *error) 9440 { 9441 const struct mlx5_flow_driver_ops *fops; 9442 struct rte_flow_attr attr = { .transfer = 0 }; 9443 9444 if (flow_get_drv_type(dev, &attr) == MLX5_FLOW_TYPE_DV) { 9445 fops = flow_get_drv_ops(MLX5_FLOW_TYPE_DV); 9446 return fops->get_aged_flows(dev, contexts, nb_contexts, 9447 error); 9448 } 9449 DRV_LOG(ERR, 9450 "port %u get aged flows is not supported.", 9451 dev->data->port_id); 9452 return -ENOTSUP; 9453 } 9454 9455 /* Wrapper for driver action_validate op callback */ 9456 static int 9457 flow_drv_action_validate(struct rte_eth_dev *dev, 9458 const struct rte_flow_indir_action_conf *conf, 9459 const struct rte_flow_action *action, 9460 const struct mlx5_flow_driver_ops *fops, 9461 struct rte_flow_error *error) 9462 { 9463 static const char err_msg[] = "indirect action validation unsupported"; 9464 9465 if (!fops->action_validate) { 9466 DRV_LOG(ERR, "port %u %s.", dev->data->port_id, err_msg); 9467 rte_flow_error_set(error, ENOTSUP, RTE_FLOW_ERROR_TYPE_ACTION, 9468 NULL, err_msg); 9469 return -rte_errno; 9470 } 9471 return fops->action_validate(dev, conf, action, error); 9472 } 9473 9474 /** 9475 * Destroys the shared action by handle. 9476 * 9477 * @param dev 9478 * Pointer to Ethernet device structure. 9479 * @param[in] handle 9480 * Handle for the indirect action object to be destroyed. 9481 * @param[out] error 9482 * Perform verbose error reporting if not NULL. PMDs initialize this 9483 * structure in case of error only. 9484 * 9485 * @return 9486 * 0 on success, a negative errno value otherwise and rte_errno is set. 9487 * 9488 * @note: wrapper for driver action_create op callback. 9489 */ 9490 static int 9491 mlx5_action_handle_destroy(struct rte_eth_dev *dev, 9492 struct rte_flow_action_handle *handle, 9493 struct rte_flow_error *error) 9494 { 9495 static const char err_msg[] = "indirect action destruction unsupported"; 9496 struct rte_flow_attr attr = { .transfer = 0 }; 9497 const struct mlx5_flow_driver_ops *fops = 9498 flow_get_drv_ops(flow_get_drv_type(dev, &attr)); 9499 9500 if (!fops->action_destroy) { 9501 DRV_LOG(ERR, "port %u %s.", dev->data->port_id, err_msg); 9502 rte_flow_error_set(error, ENOTSUP, RTE_FLOW_ERROR_TYPE_ACTION, 9503 NULL, err_msg); 9504 return -rte_errno; 9505 } 9506 return fops->action_destroy(dev, handle, error); 9507 } 9508 9509 /* Wrapper for driver action_destroy op callback */ 9510 static int 9511 flow_drv_action_update(struct rte_eth_dev *dev, 9512 struct rte_flow_action_handle *handle, 9513 const void *update, 9514 const struct mlx5_flow_driver_ops *fops, 9515 struct rte_flow_error *error) 9516 { 9517 static const char err_msg[] = "indirect action update unsupported"; 9518 9519 if (!fops->action_update) { 9520 DRV_LOG(ERR, "port %u %s.", dev->data->port_id, err_msg); 9521 rte_flow_error_set(error, ENOTSUP, RTE_FLOW_ERROR_TYPE_ACTION, 9522 NULL, err_msg); 9523 return -rte_errno; 9524 } 9525 return fops->action_update(dev, handle, update, error); 9526 } 9527 9528 /* Wrapper for driver action_destroy op callback */ 9529 static int 9530 flow_drv_action_query(struct rte_eth_dev *dev, 9531 const struct rte_flow_action_handle *handle, 9532 void *data, 9533 const struct mlx5_flow_driver_ops *fops, 9534 struct rte_flow_error *error) 9535 { 9536 static const char err_msg[] = "indirect action query unsupported"; 9537 9538 if (!fops->action_query) { 9539 DRV_LOG(ERR, "port %u %s.", dev->data->port_id, err_msg); 9540 rte_flow_error_set(error, ENOTSUP, RTE_FLOW_ERROR_TYPE_ACTION, 9541 NULL, err_msg); 9542 return -rte_errno; 9543 } 9544 return fops->action_query(dev, handle, data, error); 9545 } 9546 9547 /** 9548 * Create indirect action for reuse in multiple flow rules. 9549 * 9550 * @param dev 9551 * Pointer to Ethernet device structure. 9552 * @param conf 9553 * Pointer to indirect action object configuration. 9554 * @param[in] action 9555 * Action configuration for indirect action object creation. 9556 * @param[out] error 9557 * Perform verbose error reporting if not NULL. PMDs initialize this 9558 * structure in case of error only. 9559 * @return 9560 * A valid handle in case of success, NULL otherwise and rte_errno is set. 9561 */ 9562 static struct rte_flow_action_handle * 9563 mlx5_action_handle_create(struct rte_eth_dev *dev, 9564 const struct rte_flow_indir_action_conf *conf, 9565 const struct rte_flow_action *action, 9566 struct rte_flow_error *error) 9567 { 9568 static const char err_msg[] = "indirect action creation unsupported"; 9569 struct rte_flow_attr attr = { .transfer = 0 }; 9570 const struct mlx5_flow_driver_ops *fops = 9571 flow_get_drv_ops(flow_get_drv_type(dev, &attr)); 9572 9573 if (flow_drv_action_validate(dev, conf, action, fops, error)) 9574 return NULL; 9575 if (!fops->action_create) { 9576 DRV_LOG(ERR, "port %u %s.", dev->data->port_id, err_msg); 9577 rte_flow_error_set(error, ENOTSUP, RTE_FLOW_ERROR_TYPE_ACTION, 9578 NULL, err_msg); 9579 return NULL; 9580 } 9581 return fops->action_create(dev, conf, action, error); 9582 } 9583 9584 /** 9585 * Updates inplace the indirect action configuration pointed by *handle* 9586 * with the configuration provided as *update* argument. 9587 * The update of the indirect action configuration effects all flow rules 9588 * reusing the action via handle. 9589 * 9590 * @param dev 9591 * Pointer to Ethernet device structure. 9592 * @param[in] handle 9593 * Handle for the indirect action to be updated. 9594 * @param[in] update 9595 * Action specification used to modify the action pointed by handle. 9596 * *update* could be of same type with the action pointed by the *handle* 9597 * handle argument, or some other structures like a wrapper, depending on 9598 * the indirect action type. 9599 * @param[out] error 9600 * Perform verbose error reporting if not NULL. PMDs initialize this 9601 * structure in case of error only. 9602 * 9603 * @return 9604 * 0 on success, a negative errno value otherwise and rte_errno is set. 9605 */ 9606 static int 9607 mlx5_action_handle_update(struct rte_eth_dev *dev, 9608 struct rte_flow_action_handle *handle, 9609 const void *update, 9610 struct rte_flow_error *error) 9611 { 9612 struct rte_flow_attr attr = { .transfer = 0 }; 9613 const struct mlx5_flow_driver_ops *fops = 9614 flow_get_drv_ops(flow_get_drv_type(dev, &attr)); 9615 int ret; 9616 9617 ret = flow_drv_action_validate(dev, NULL, 9618 (const struct rte_flow_action *)update, fops, error); 9619 if (ret) 9620 return ret; 9621 return flow_drv_action_update(dev, handle, update, fops, 9622 error); 9623 } 9624 9625 /** 9626 * Query the indirect action by handle. 9627 * 9628 * This function allows retrieving action-specific data such as counters. 9629 * Data is gathered by special action which may be present/referenced in 9630 * more than one flow rule definition. 9631 * 9632 * see @RTE_FLOW_ACTION_TYPE_COUNT 9633 * 9634 * @param dev 9635 * Pointer to Ethernet device structure. 9636 * @param[in] handle 9637 * Handle for the indirect action to query. 9638 * @param[in, out] data 9639 * Pointer to storage for the associated query data type. 9640 * @param[out] error 9641 * Perform verbose error reporting if not NULL. PMDs initialize this 9642 * structure in case of error only. 9643 * 9644 * @return 9645 * 0 on success, a negative errno value otherwise and rte_errno is set. 9646 */ 9647 static int 9648 mlx5_action_handle_query(struct rte_eth_dev *dev, 9649 const struct rte_flow_action_handle *handle, 9650 void *data, 9651 struct rte_flow_error *error) 9652 { 9653 struct rte_flow_attr attr = { .transfer = 0 }; 9654 const struct mlx5_flow_driver_ops *fops = 9655 flow_get_drv_ops(flow_get_drv_type(dev, &attr)); 9656 9657 return flow_drv_action_query(dev, handle, data, fops, error); 9658 } 9659 9660 /** 9661 * Destroy all indirect actions (shared RSS). 9662 * 9663 * @param dev 9664 * Pointer to Ethernet device. 9665 * 9666 * @return 9667 * 0 on success, a negative errno value otherwise and rte_errno is set. 9668 */ 9669 int 9670 mlx5_action_handle_flush(struct rte_eth_dev *dev) 9671 { 9672 struct rte_flow_error error; 9673 struct mlx5_priv *priv = dev->data->dev_private; 9674 struct mlx5_shared_action_rss *shared_rss; 9675 int ret = 0; 9676 uint32_t idx; 9677 9678 ILIST_FOREACH(priv->sh->ipool[MLX5_IPOOL_RSS_SHARED_ACTIONS], 9679 priv->rss_shared_actions, idx, shared_rss, next) { 9680 ret |= mlx5_action_handle_destroy(dev, 9681 (struct rte_flow_action_handle *)(uintptr_t)idx, &error); 9682 } 9683 return ret; 9684 } 9685 9686 /** 9687 * Validate existing indirect actions against current device configuration 9688 * and attach them to device resources. 9689 * 9690 * @param dev 9691 * Pointer to Ethernet device. 9692 * 9693 * @return 9694 * 0 on success, a negative errno value otherwise and rte_errno is set. 9695 */ 9696 int 9697 mlx5_action_handle_attach(struct rte_eth_dev *dev) 9698 { 9699 struct mlx5_priv *priv = dev->data->dev_private; 9700 int ret = 0; 9701 struct mlx5_ind_table_obj *ind_tbl, *ind_tbl_last; 9702 9703 LIST_FOREACH(ind_tbl, &priv->standalone_ind_tbls, next) { 9704 const char *message; 9705 uint32_t queue_idx; 9706 9707 ret = mlx5_validate_rss_queues(dev, ind_tbl->queues, 9708 ind_tbl->queues_n, 9709 &message, &queue_idx); 9710 if (ret != 0) { 9711 DRV_LOG(ERR, "Port %u cannot use queue %u in RSS: %s", 9712 dev->data->port_id, ind_tbl->queues[queue_idx], 9713 message); 9714 break; 9715 } 9716 } 9717 if (ret != 0) 9718 return ret; 9719 LIST_FOREACH(ind_tbl, &priv->standalone_ind_tbls, next) { 9720 ret = mlx5_ind_table_obj_attach(dev, ind_tbl); 9721 if (ret != 0) { 9722 DRV_LOG(ERR, "Port %u could not attach " 9723 "indirection table obj %p", 9724 dev->data->port_id, (void *)ind_tbl); 9725 goto error; 9726 } 9727 } 9728 9729 return 0; 9730 error: 9731 ind_tbl_last = ind_tbl; 9732 LIST_FOREACH(ind_tbl, &priv->standalone_ind_tbls, next) { 9733 if (ind_tbl == ind_tbl_last) 9734 break; 9735 if (mlx5_ind_table_obj_detach(dev, ind_tbl) != 0) 9736 DRV_LOG(CRIT, "Port %u could not detach " 9737 "indirection table obj %p on rollback", 9738 dev->data->port_id, (void *)ind_tbl); 9739 } 9740 return ret; 9741 } 9742 9743 /** 9744 * Detach indirect actions of the device from its resources. 9745 * 9746 * @param dev 9747 * Pointer to Ethernet device. 9748 * 9749 * @return 9750 * 0 on success, a negative errno value otherwise and rte_errno is set. 9751 */ 9752 int 9753 mlx5_action_handle_detach(struct rte_eth_dev *dev) 9754 { 9755 struct mlx5_priv *priv = dev->data->dev_private; 9756 int ret = 0; 9757 struct mlx5_ind_table_obj *ind_tbl, *ind_tbl_last; 9758 9759 LIST_FOREACH(ind_tbl, &priv->standalone_ind_tbls, next) { 9760 ret = mlx5_ind_table_obj_detach(dev, ind_tbl); 9761 if (ret != 0) { 9762 DRV_LOG(ERR, "Port %u could not detach " 9763 "indirection table obj %p", 9764 dev->data->port_id, (void *)ind_tbl); 9765 goto error; 9766 } 9767 } 9768 return 0; 9769 error: 9770 ind_tbl_last = ind_tbl; 9771 LIST_FOREACH(ind_tbl, &priv->standalone_ind_tbls, next) { 9772 if (ind_tbl == ind_tbl_last) 9773 break; 9774 if (mlx5_ind_table_obj_attach(dev, ind_tbl) != 0) 9775 DRV_LOG(CRIT, "Port %u could not attach " 9776 "indirection table obj %p on rollback", 9777 dev->data->port_id, (void *)ind_tbl); 9778 } 9779 return ret; 9780 } 9781 9782 #ifndef HAVE_MLX5DV_DR 9783 #define MLX5_DOMAIN_SYNC_FLOW ((1 << 0) | (1 << 1)) 9784 #else 9785 #define MLX5_DOMAIN_SYNC_FLOW \ 9786 (MLX5DV_DR_DOMAIN_SYNC_FLAGS_SW | MLX5DV_DR_DOMAIN_SYNC_FLAGS_HW) 9787 #endif 9788 9789 int rte_pmd_mlx5_sync_flow(uint16_t port_id, uint32_t domains) 9790 { 9791 struct rte_eth_dev *dev = &rte_eth_devices[port_id]; 9792 const struct mlx5_flow_driver_ops *fops; 9793 int ret; 9794 struct rte_flow_attr attr = { .transfer = 0 }; 9795 9796 fops = flow_get_drv_ops(flow_get_drv_type(dev, &attr)); 9797 ret = fops->sync_domain(dev, domains, MLX5_DOMAIN_SYNC_FLOW); 9798 if (ret > 0) 9799 ret = -ret; 9800 return ret; 9801 } 9802 9803 const struct mlx5_flow_tunnel * 9804 mlx5_get_tof(const struct rte_flow_item *item, 9805 const struct rte_flow_action *action, 9806 enum mlx5_tof_rule_type *rule_type) 9807 { 9808 for (; item->type != RTE_FLOW_ITEM_TYPE_END; item++) { 9809 if (item->type == (typeof(item->type)) 9810 MLX5_RTE_FLOW_ITEM_TYPE_TUNNEL) { 9811 *rule_type = MLX5_TUNNEL_OFFLOAD_MATCH_RULE; 9812 return flow_items_to_tunnel(item); 9813 } 9814 } 9815 for (; action->conf != RTE_FLOW_ACTION_TYPE_END; action++) { 9816 if (action->type == (typeof(action->type)) 9817 MLX5_RTE_FLOW_ACTION_TYPE_TUNNEL_SET) { 9818 *rule_type = MLX5_TUNNEL_OFFLOAD_SET_RULE; 9819 return flow_actions_to_tunnel(action); 9820 } 9821 } 9822 return NULL; 9823 } 9824 9825 /** 9826 * tunnel offload functionality is defined for DV environment only 9827 */ 9828 #ifdef HAVE_IBV_FLOW_DV_SUPPORT 9829 __extension__ 9830 union tunnel_offload_mark { 9831 uint32_t val; 9832 struct { 9833 uint32_t app_reserve:8; 9834 uint32_t table_id:15; 9835 uint32_t transfer:1; 9836 uint32_t _unused_:8; 9837 }; 9838 }; 9839 9840 static bool 9841 mlx5_access_tunnel_offload_db 9842 (struct rte_eth_dev *dev, 9843 bool (*match)(struct rte_eth_dev *, 9844 struct mlx5_flow_tunnel *, const void *), 9845 void (*hit)(struct rte_eth_dev *, struct mlx5_flow_tunnel *, void *), 9846 void (*miss)(struct rte_eth_dev *, void *), 9847 void *ctx, bool lock_op); 9848 9849 static int 9850 flow_tunnel_add_default_miss(struct rte_eth_dev *dev, 9851 struct rte_flow *flow, 9852 const struct rte_flow_attr *attr, 9853 const struct rte_flow_action *app_actions, 9854 uint32_t flow_idx, 9855 const struct mlx5_flow_tunnel *tunnel, 9856 struct tunnel_default_miss_ctx *ctx, 9857 struct rte_flow_error *error) 9858 { 9859 struct mlx5_priv *priv = dev->data->dev_private; 9860 struct mlx5_flow *dev_flow; 9861 struct rte_flow_attr miss_attr = *attr; 9862 const struct rte_flow_item miss_items[2] = { 9863 { 9864 .type = RTE_FLOW_ITEM_TYPE_ETH, 9865 .spec = NULL, 9866 .last = NULL, 9867 .mask = NULL 9868 }, 9869 { 9870 .type = RTE_FLOW_ITEM_TYPE_END, 9871 .spec = NULL, 9872 .last = NULL, 9873 .mask = NULL 9874 } 9875 }; 9876 union tunnel_offload_mark mark_id; 9877 struct rte_flow_action_mark miss_mark; 9878 struct rte_flow_action miss_actions[3] = { 9879 [0] = { .type = RTE_FLOW_ACTION_TYPE_MARK, .conf = &miss_mark }, 9880 [2] = { .type = RTE_FLOW_ACTION_TYPE_END, .conf = NULL } 9881 }; 9882 const struct rte_flow_action_jump *jump_data; 9883 uint32_t i, flow_table = 0; /* prevent compilation warning */ 9884 struct flow_grp_info grp_info = { 9885 .external = 1, 9886 .transfer = attr->transfer, 9887 .fdb_def_rule = !!priv->fdb_def_rule, 9888 .std_tbl_fix = 0, 9889 }; 9890 int ret; 9891 9892 if (!attr->transfer) { 9893 uint32_t q_size; 9894 9895 miss_actions[1].type = RTE_FLOW_ACTION_TYPE_RSS; 9896 q_size = priv->reta_idx_n * sizeof(ctx->queue[0]); 9897 ctx->queue = mlx5_malloc(MLX5_MEM_SYS | MLX5_MEM_ZERO, q_size, 9898 0, SOCKET_ID_ANY); 9899 if (!ctx->queue) 9900 return rte_flow_error_set 9901 (error, ENOMEM, 9902 RTE_FLOW_ERROR_TYPE_ACTION_CONF, 9903 NULL, "invalid default miss RSS"); 9904 ctx->action_rss.func = RTE_ETH_HASH_FUNCTION_DEFAULT, 9905 ctx->action_rss.level = 0, 9906 ctx->action_rss.types = priv->rss_conf.rss_hf, 9907 ctx->action_rss.key_len = priv->rss_conf.rss_key_len, 9908 ctx->action_rss.queue_num = priv->reta_idx_n, 9909 ctx->action_rss.key = priv->rss_conf.rss_key, 9910 ctx->action_rss.queue = ctx->queue; 9911 if (!priv->reta_idx_n || !priv->rxqs_n) 9912 return rte_flow_error_set 9913 (error, EINVAL, 9914 RTE_FLOW_ERROR_TYPE_ACTION_CONF, 9915 NULL, "invalid port configuration"); 9916 if (!(dev->data->dev_conf.rxmode.mq_mode & RTE_ETH_MQ_RX_RSS_FLAG)) 9917 ctx->action_rss.types = 0; 9918 for (i = 0; i != priv->reta_idx_n; ++i) 9919 ctx->queue[i] = (*priv->reta_idx)[i]; 9920 } else { 9921 miss_actions[1].type = RTE_FLOW_ACTION_TYPE_JUMP; 9922 ctx->miss_jump.group = MLX5_TNL_MISS_FDB_JUMP_GRP; 9923 } 9924 miss_actions[1].conf = (typeof(miss_actions[1].conf))ctx->raw; 9925 for (; app_actions->type != RTE_FLOW_ACTION_TYPE_JUMP; app_actions++); 9926 jump_data = app_actions->conf; 9927 miss_attr.priority = MLX5_TNL_MISS_RULE_PRIORITY; 9928 miss_attr.group = jump_data->group; 9929 ret = mlx5_flow_group_to_table(dev, tunnel, jump_data->group, 9930 &flow_table, &grp_info, error); 9931 if (ret) 9932 return rte_flow_error_set(error, EINVAL, 9933 RTE_FLOW_ERROR_TYPE_ACTION_CONF, 9934 NULL, "invalid tunnel id"); 9935 mark_id.app_reserve = 0; 9936 mark_id.table_id = tunnel_flow_tbl_to_id(flow_table); 9937 mark_id.transfer = !!attr->transfer; 9938 mark_id._unused_ = 0; 9939 miss_mark.id = mark_id.val; 9940 dev_flow = flow_drv_prepare(dev, flow, &miss_attr, 9941 miss_items, miss_actions, flow_idx, error); 9942 if (!dev_flow) 9943 return -rte_errno; 9944 dev_flow->flow = flow; 9945 dev_flow->external = true; 9946 dev_flow->tunnel = tunnel; 9947 dev_flow->tof_type = MLX5_TUNNEL_OFFLOAD_MISS_RULE; 9948 /* Subflow object was created, we must include one in the list. */ 9949 SILIST_INSERT(&flow->dev_handles, dev_flow->handle_idx, 9950 dev_flow->handle, next); 9951 DRV_LOG(DEBUG, 9952 "port %u tunnel type=%d id=%u miss rule priority=%u group=%u", 9953 dev->data->port_id, tunnel->app_tunnel.type, 9954 tunnel->tunnel_id, miss_attr.priority, miss_attr.group); 9955 ret = flow_drv_translate(dev, dev_flow, &miss_attr, miss_items, 9956 miss_actions, error); 9957 if (!ret) 9958 ret = flow_mreg_update_copy_table(dev, flow, miss_actions, 9959 error); 9960 9961 return ret; 9962 } 9963 9964 static const struct mlx5_flow_tbl_data_entry * 9965 tunnel_mark_decode(struct rte_eth_dev *dev, uint32_t mark) 9966 { 9967 struct mlx5_priv *priv = dev->data->dev_private; 9968 struct mlx5_dev_ctx_shared *sh = priv->sh; 9969 struct mlx5_list_entry *he; 9970 union tunnel_offload_mark mbits = { .val = mark }; 9971 union mlx5_flow_tbl_key table_key = { 9972 { 9973 .level = tunnel_id_to_flow_tbl(mbits.table_id), 9974 .id = 0, 9975 .reserved = 0, 9976 .dummy = 0, 9977 .is_fdb = !!mbits.transfer, 9978 .is_egress = 0, 9979 } 9980 }; 9981 struct mlx5_flow_cb_ctx ctx = { 9982 .data = &table_key.v64, 9983 }; 9984 9985 he = mlx5_hlist_lookup(sh->flow_tbls, table_key.v64, &ctx); 9986 return he ? 9987 container_of(he, struct mlx5_flow_tbl_data_entry, entry) : NULL; 9988 } 9989 9990 static void 9991 mlx5_flow_tunnel_grp2tbl_remove_cb(void *tool_ctx, 9992 struct mlx5_list_entry *entry) 9993 { 9994 struct mlx5_dev_ctx_shared *sh = tool_ctx; 9995 struct tunnel_tbl_entry *tte = container_of(entry, typeof(*tte), hash); 9996 9997 mlx5_ipool_free(sh->ipool[MLX5_IPOOL_TNL_TBL_ID], 9998 tunnel_flow_tbl_to_id(tte->flow_table)); 9999 mlx5_free(tte); 10000 } 10001 10002 static int 10003 mlx5_flow_tunnel_grp2tbl_match_cb(void *tool_ctx __rte_unused, 10004 struct mlx5_list_entry *entry, void *cb_ctx) 10005 { 10006 struct mlx5_flow_cb_ctx *ctx = cb_ctx; 10007 union tunnel_tbl_key tbl = { 10008 .val = *(uint64_t *)(ctx->data), 10009 }; 10010 struct tunnel_tbl_entry *tte = container_of(entry, typeof(*tte), hash); 10011 10012 return tbl.tunnel_id != tte->tunnel_id || tbl.group != tte->group; 10013 } 10014 10015 static struct mlx5_list_entry * 10016 mlx5_flow_tunnel_grp2tbl_create_cb(void *tool_ctx, void *cb_ctx) 10017 { 10018 struct mlx5_dev_ctx_shared *sh = tool_ctx; 10019 struct mlx5_flow_cb_ctx *ctx = cb_ctx; 10020 struct tunnel_tbl_entry *tte; 10021 union tunnel_tbl_key tbl = { 10022 .val = *(uint64_t *)(ctx->data), 10023 }; 10024 10025 tte = mlx5_malloc(MLX5_MEM_SYS | MLX5_MEM_ZERO, 10026 sizeof(*tte), 0, 10027 SOCKET_ID_ANY); 10028 if (!tte) 10029 goto err; 10030 mlx5_ipool_malloc(sh->ipool[MLX5_IPOOL_TNL_TBL_ID], 10031 &tte->flow_table); 10032 if (tte->flow_table >= MLX5_MAX_TABLES) { 10033 DRV_LOG(ERR, "Tunnel TBL ID %d exceed max limit.", 10034 tte->flow_table); 10035 mlx5_ipool_free(sh->ipool[MLX5_IPOOL_TNL_TBL_ID], 10036 tte->flow_table); 10037 goto err; 10038 } else if (!tte->flow_table) { 10039 goto err; 10040 } 10041 tte->flow_table = tunnel_id_to_flow_tbl(tte->flow_table); 10042 tte->tunnel_id = tbl.tunnel_id; 10043 tte->group = tbl.group; 10044 return &tte->hash; 10045 err: 10046 if (tte) 10047 mlx5_free(tte); 10048 return NULL; 10049 } 10050 10051 static struct mlx5_list_entry * 10052 mlx5_flow_tunnel_grp2tbl_clone_cb(void *tool_ctx __rte_unused, 10053 struct mlx5_list_entry *oentry, 10054 void *cb_ctx __rte_unused) 10055 { 10056 struct tunnel_tbl_entry *tte = mlx5_malloc(MLX5_MEM_SYS, sizeof(*tte), 10057 0, SOCKET_ID_ANY); 10058 10059 if (!tte) 10060 return NULL; 10061 memcpy(tte, oentry, sizeof(*tte)); 10062 return &tte->hash; 10063 } 10064 10065 static void 10066 mlx5_flow_tunnel_grp2tbl_clone_free_cb(void *tool_ctx __rte_unused, 10067 struct mlx5_list_entry *entry) 10068 { 10069 struct tunnel_tbl_entry *tte = container_of(entry, typeof(*tte), hash); 10070 10071 mlx5_free(tte); 10072 } 10073 10074 static uint32_t 10075 tunnel_flow_group_to_flow_table(struct rte_eth_dev *dev, 10076 const struct mlx5_flow_tunnel *tunnel, 10077 uint32_t group, uint32_t *table, 10078 struct rte_flow_error *error) 10079 { 10080 struct mlx5_list_entry *he; 10081 struct tunnel_tbl_entry *tte; 10082 union tunnel_tbl_key key = { 10083 .tunnel_id = tunnel ? tunnel->tunnel_id : 0, 10084 .group = group 10085 }; 10086 struct mlx5_flow_tunnel_hub *thub = mlx5_tunnel_hub(dev); 10087 struct mlx5_hlist *group_hash; 10088 struct mlx5_flow_cb_ctx ctx = { 10089 .data = &key.val, 10090 }; 10091 10092 group_hash = tunnel ? tunnel->groups : thub->groups; 10093 he = mlx5_hlist_register(group_hash, key.val, &ctx); 10094 if (!he) 10095 return rte_flow_error_set(error, EINVAL, 10096 RTE_FLOW_ERROR_TYPE_ATTR_GROUP, 10097 NULL, 10098 "tunnel group index not supported"); 10099 tte = container_of(he, typeof(*tte), hash); 10100 *table = tte->flow_table; 10101 DRV_LOG(DEBUG, "port %u tunnel %u group=%#x table=%#x", 10102 dev->data->port_id, key.tunnel_id, group, *table); 10103 return 0; 10104 } 10105 10106 static void 10107 mlx5_flow_tunnel_free(struct rte_eth_dev *dev, 10108 struct mlx5_flow_tunnel *tunnel) 10109 { 10110 struct mlx5_priv *priv = dev->data->dev_private; 10111 struct mlx5_indexed_pool *ipool; 10112 10113 DRV_LOG(DEBUG, "port %u release pmd tunnel id=0x%x", 10114 dev->data->port_id, tunnel->tunnel_id); 10115 LIST_REMOVE(tunnel, chain); 10116 mlx5_hlist_destroy(tunnel->groups); 10117 ipool = priv->sh->ipool[MLX5_IPOOL_TUNNEL_ID]; 10118 mlx5_ipool_free(ipool, tunnel->tunnel_id); 10119 } 10120 10121 static bool 10122 mlx5_access_tunnel_offload_db 10123 (struct rte_eth_dev *dev, 10124 bool (*match)(struct rte_eth_dev *, 10125 struct mlx5_flow_tunnel *, const void *), 10126 void (*hit)(struct rte_eth_dev *, struct mlx5_flow_tunnel *, void *), 10127 void (*miss)(struct rte_eth_dev *, void *), 10128 void *ctx, bool lock_op) 10129 { 10130 bool verdict = false; 10131 struct mlx5_flow_tunnel_hub *thub = mlx5_tunnel_hub(dev); 10132 struct mlx5_flow_tunnel *tunnel; 10133 10134 rte_spinlock_lock(&thub->sl); 10135 LIST_FOREACH(tunnel, &thub->tunnels, chain) { 10136 verdict = match(dev, tunnel, (const void *)ctx); 10137 if (verdict) 10138 break; 10139 } 10140 if (!lock_op) 10141 rte_spinlock_unlock(&thub->sl); 10142 if (verdict && hit) 10143 hit(dev, tunnel, ctx); 10144 if (!verdict && miss) 10145 miss(dev, ctx); 10146 if (lock_op) 10147 rte_spinlock_unlock(&thub->sl); 10148 10149 return verdict; 10150 } 10151 10152 struct tunnel_db_find_tunnel_id_ctx { 10153 uint32_t tunnel_id; 10154 struct mlx5_flow_tunnel *tunnel; 10155 }; 10156 10157 static bool 10158 find_tunnel_id_match(struct rte_eth_dev *dev, 10159 struct mlx5_flow_tunnel *tunnel, const void *x) 10160 { 10161 const struct tunnel_db_find_tunnel_id_ctx *ctx = x; 10162 10163 RTE_SET_USED(dev); 10164 return tunnel->tunnel_id == ctx->tunnel_id; 10165 } 10166 10167 static void 10168 find_tunnel_id_hit(struct rte_eth_dev *dev, 10169 struct mlx5_flow_tunnel *tunnel, void *x) 10170 { 10171 struct tunnel_db_find_tunnel_id_ctx *ctx = x; 10172 RTE_SET_USED(dev); 10173 ctx->tunnel = tunnel; 10174 } 10175 10176 static struct mlx5_flow_tunnel * 10177 mlx5_find_tunnel_id(struct rte_eth_dev *dev, uint32_t id) 10178 { 10179 struct tunnel_db_find_tunnel_id_ctx ctx = { 10180 .tunnel_id = id, 10181 }; 10182 10183 mlx5_access_tunnel_offload_db(dev, find_tunnel_id_match, 10184 find_tunnel_id_hit, NULL, &ctx, true); 10185 10186 return ctx.tunnel; 10187 } 10188 10189 static struct mlx5_flow_tunnel * 10190 mlx5_flow_tunnel_allocate(struct rte_eth_dev *dev, 10191 const struct rte_flow_tunnel *app_tunnel) 10192 { 10193 struct mlx5_priv *priv = dev->data->dev_private; 10194 struct mlx5_indexed_pool *ipool; 10195 struct mlx5_flow_tunnel *tunnel; 10196 uint32_t id; 10197 10198 ipool = priv->sh->ipool[MLX5_IPOOL_TUNNEL_ID]; 10199 tunnel = mlx5_ipool_zmalloc(ipool, &id); 10200 if (!tunnel) 10201 return NULL; 10202 if (id >= MLX5_MAX_TUNNELS) { 10203 mlx5_ipool_free(ipool, id); 10204 DRV_LOG(ERR, "Tunnel ID %d exceed max limit.", id); 10205 return NULL; 10206 } 10207 tunnel->groups = mlx5_hlist_create("tunnel groups", 64, false, true, 10208 priv->sh, 10209 mlx5_flow_tunnel_grp2tbl_create_cb, 10210 mlx5_flow_tunnel_grp2tbl_match_cb, 10211 mlx5_flow_tunnel_grp2tbl_remove_cb, 10212 mlx5_flow_tunnel_grp2tbl_clone_cb, 10213 mlx5_flow_tunnel_grp2tbl_clone_free_cb); 10214 if (!tunnel->groups) { 10215 mlx5_ipool_free(ipool, id); 10216 return NULL; 10217 } 10218 /* initiate new PMD tunnel */ 10219 memcpy(&tunnel->app_tunnel, app_tunnel, sizeof(*app_tunnel)); 10220 tunnel->tunnel_id = id; 10221 tunnel->action.type = (typeof(tunnel->action.type)) 10222 MLX5_RTE_FLOW_ACTION_TYPE_TUNNEL_SET; 10223 tunnel->action.conf = tunnel; 10224 tunnel->item.type = (typeof(tunnel->item.type)) 10225 MLX5_RTE_FLOW_ITEM_TYPE_TUNNEL; 10226 tunnel->item.spec = tunnel; 10227 tunnel->item.last = NULL; 10228 tunnel->item.mask = NULL; 10229 10230 DRV_LOG(DEBUG, "port %u new pmd tunnel id=0x%x", 10231 dev->data->port_id, tunnel->tunnel_id); 10232 10233 return tunnel; 10234 } 10235 10236 struct tunnel_db_get_tunnel_ctx { 10237 const struct rte_flow_tunnel *app_tunnel; 10238 struct mlx5_flow_tunnel *tunnel; 10239 }; 10240 10241 static bool get_tunnel_match(struct rte_eth_dev *dev, 10242 struct mlx5_flow_tunnel *tunnel, const void *x) 10243 { 10244 const struct tunnel_db_get_tunnel_ctx *ctx = x; 10245 10246 RTE_SET_USED(dev); 10247 return !memcmp(ctx->app_tunnel, &tunnel->app_tunnel, 10248 sizeof(*ctx->app_tunnel)); 10249 } 10250 10251 static void get_tunnel_hit(struct rte_eth_dev *dev, 10252 struct mlx5_flow_tunnel *tunnel, void *x) 10253 { 10254 /* called under tunnel spinlock protection */ 10255 struct tunnel_db_get_tunnel_ctx *ctx = x; 10256 10257 RTE_SET_USED(dev); 10258 tunnel->refctn++; 10259 ctx->tunnel = tunnel; 10260 } 10261 10262 static void get_tunnel_miss(struct rte_eth_dev *dev, void *x) 10263 { 10264 /* called under tunnel spinlock protection */ 10265 struct mlx5_flow_tunnel_hub *thub = mlx5_tunnel_hub(dev); 10266 struct tunnel_db_get_tunnel_ctx *ctx = x; 10267 10268 rte_spinlock_unlock(&thub->sl); 10269 ctx->tunnel = mlx5_flow_tunnel_allocate(dev, ctx->app_tunnel); 10270 rte_spinlock_lock(&thub->sl); 10271 if (ctx->tunnel) { 10272 ctx->tunnel->refctn = 1; 10273 LIST_INSERT_HEAD(&thub->tunnels, ctx->tunnel, chain); 10274 } 10275 } 10276 10277 10278 static int 10279 mlx5_get_flow_tunnel(struct rte_eth_dev *dev, 10280 const struct rte_flow_tunnel *app_tunnel, 10281 struct mlx5_flow_tunnel **tunnel) 10282 { 10283 struct tunnel_db_get_tunnel_ctx ctx = { 10284 .app_tunnel = app_tunnel, 10285 }; 10286 10287 mlx5_access_tunnel_offload_db(dev, get_tunnel_match, get_tunnel_hit, 10288 get_tunnel_miss, &ctx, true); 10289 *tunnel = ctx.tunnel; 10290 return ctx.tunnel ? 0 : -ENOMEM; 10291 } 10292 10293 void mlx5_release_tunnel_hub(struct mlx5_dev_ctx_shared *sh, uint16_t port_id) 10294 { 10295 struct mlx5_flow_tunnel_hub *thub = sh->tunnel_hub; 10296 10297 if (!thub) 10298 return; 10299 if (!LIST_EMPTY(&thub->tunnels)) 10300 DRV_LOG(WARNING, "port %u tunnels present", port_id); 10301 mlx5_hlist_destroy(thub->groups); 10302 mlx5_free(thub); 10303 } 10304 10305 int mlx5_alloc_tunnel_hub(struct mlx5_dev_ctx_shared *sh) 10306 { 10307 int err; 10308 struct mlx5_flow_tunnel_hub *thub; 10309 10310 thub = mlx5_malloc(MLX5_MEM_SYS | MLX5_MEM_ZERO, sizeof(*thub), 10311 0, SOCKET_ID_ANY); 10312 if (!thub) 10313 return -ENOMEM; 10314 LIST_INIT(&thub->tunnels); 10315 rte_spinlock_init(&thub->sl); 10316 thub->groups = mlx5_hlist_create("flow groups", 64, 10317 false, true, sh, 10318 mlx5_flow_tunnel_grp2tbl_create_cb, 10319 mlx5_flow_tunnel_grp2tbl_match_cb, 10320 mlx5_flow_tunnel_grp2tbl_remove_cb, 10321 mlx5_flow_tunnel_grp2tbl_clone_cb, 10322 mlx5_flow_tunnel_grp2tbl_clone_free_cb); 10323 if (!thub->groups) { 10324 err = -rte_errno; 10325 goto err; 10326 } 10327 sh->tunnel_hub = thub; 10328 10329 return 0; 10330 10331 err: 10332 if (thub->groups) 10333 mlx5_hlist_destroy(thub->groups); 10334 if (thub) 10335 mlx5_free(thub); 10336 return err; 10337 } 10338 10339 static inline int 10340 mlx5_flow_tunnel_validate(struct rte_eth_dev *dev, 10341 struct rte_flow_tunnel *tunnel, 10342 struct rte_flow_error *error) 10343 { 10344 struct mlx5_priv *priv = dev->data->dev_private; 10345 10346 if (!priv->sh->config.dv_flow_en) 10347 return rte_flow_error_set(error, ENOTSUP, 10348 RTE_FLOW_ERROR_TYPE_ACTION_CONF, NULL, 10349 "flow DV interface is off"); 10350 if (!is_tunnel_offload_active(dev)) 10351 return rte_flow_error_set(error, ENOTSUP, 10352 RTE_FLOW_ERROR_TYPE_ACTION_CONF, NULL, 10353 "tunnel offload was not activated"); 10354 if (!tunnel) 10355 return rte_flow_error_set(error, EINVAL, 10356 RTE_FLOW_ERROR_TYPE_ACTION_CONF, NULL, 10357 "no application tunnel"); 10358 switch (tunnel->type) { 10359 default: 10360 return rte_flow_error_set(error, EINVAL, 10361 RTE_FLOW_ERROR_TYPE_ACTION_CONF, NULL, 10362 "unsupported tunnel type"); 10363 case RTE_FLOW_ITEM_TYPE_VXLAN: 10364 case RTE_FLOW_ITEM_TYPE_GRE: 10365 case RTE_FLOW_ITEM_TYPE_NVGRE: 10366 case RTE_FLOW_ITEM_TYPE_GENEVE: 10367 break; 10368 } 10369 return 0; 10370 } 10371 10372 static int 10373 mlx5_flow_tunnel_decap_set(struct rte_eth_dev *dev, 10374 struct rte_flow_tunnel *app_tunnel, 10375 struct rte_flow_action **actions, 10376 uint32_t *num_of_actions, 10377 struct rte_flow_error *error) 10378 { 10379 struct mlx5_flow_tunnel *tunnel; 10380 int ret = mlx5_flow_tunnel_validate(dev, app_tunnel, error); 10381 10382 if (ret) 10383 return ret; 10384 ret = mlx5_get_flow_tunnel(dev, app_tunnel, &tunnel); 10385 if (ret < 0) { 10386 return rte_flow_error_set(error, ret, 10387 RTE_FLOW_ERROR_TYPE_ACTION_CONF, NULL, 10388 "failed to initialize pmd tunnel"); 10389 } 10390 *actions = &tunnel->action; 10391 *num_of_actions = 1; 10392 return 0; 10393 } 10394 10395 static int 10396 mlx5_flow_tunnel_match(struct rte_eth_dev *dev, 10397 struct rte_flow_tunnel *app_tunnel, 10398 struct rte_flow_item **items, 10399 uint32_t *num_of_items, 10400 struct rte_flow_error *error) 10401 { 10402 struct mlx5_flow_tunnel *tunnel; 10403 int ret = mlx5_flow_tunnel_validate(dev, app_tunnel, error); 10404 10405 if (ret) 10406 return ret; 10407 ret = mlx5_get_flow_tunnel(dev, app_tunnel, &tunnel); 10408 if (ret < 0) { 10409 return rte_flow_error_set(error, ret, 10410 RTE_FLOW_ERROR_TYPE_HANDLE, NULL, 10411 "failed to initialize pmd tunnel"); 10412 } 10413 *items = &tunnel->item; 10414 *num_of_items = 1; 10415 return 0; 10416 } 10417 10418 struct tunnel_db_element_release_ctx { 10419 struct rte_flow_item *items; 10420 struct rte_flow_action *actions; 10421 uint32_t num_elements; 10422 struct rte_flow_error *error; 10423 int ret; 10424 }; 10425 10426 static bool 10427 tunnel_element_release_match(struct rte_eth_dev *dev, 10428 struct mlx5_flow_tunnel *tunnel, const void *x) 10429 { 10430 const struct tunnel_db_element_release_ctx *ctx = x; 10431 10432 RTE_SET_USED(dev); 10433 if (ctx->num_elements != 1) 10434 return false; 10435 else if (ctx->items) 10436 return ctx->items == &tunnel->item; 10437 else if (ctx->actions) 10438 return ctx->actions == &tunnel->action; 10439 10440 return false; 10441 } 10442 10443 static void 10444 tunnel_element_release_hit(struct rte_eth_dev *dev, 10445 struct mlx5_flow_tunnel *tunnel, void *x) 10446 { 10447 struct tunnel_db_element_release_ctx *ctx = x; 10448 ctx->ret = 0; 10449 if (!__atomic_sub_fetch(&tunnel->refctn, 1, __ATOMIC_RELAXED)) 10450 mlx5_flow_tunnel_free(dev, tunnel); 10451 } 10452 10453 static void 10454 tunnel_element_release_miss(struct rte_eth_dev *dev, void *x) 10455 { 10456 struct tunnel_db_element_release_ctx *ctx = x; 10457 RTE_SET_USED(dev); 10458 ctx->ret = rte_flow_error_set(ctx->error, EINVAL, 10459 RTE_FLOW_ERROR_TYPE_HANDLE, NULL, 10460 "invalid argument"); 10461 } 10462 10463 static int 10464 mlx5_flow_tunnel_item_release(struct rte_eth_dev *dev, 10465 struct rte_flow_item *pmd_items, 10466 uint32_t num_items, struct rte_flow_error *err) 10467 { 10468 struct tunnel_db_element_release_ctx ctx = { 10469 .items = pmd_items, 10470 .actions = NULL, 10471 .num_elements = num_items, 10472 .error = err, 10473 }; 10474 10475 mlx5_access_tunnel_offload_db(dev, tunnel_element_release_match, 10476 tunnel_element_release_hit, 10477 tunnel_element_release_miss, &ctx, false); 10478 10479 return ctx.ret; 10480 } 10481 10482 static int 10483 mlx5_flow_tunnel_action_release(struct rte_eth_dev *dev, 10484 struct rte_flow_action *pmd_actions, 10485 uint32_t num_actions, struct rte_flow_error *err) 10486 { 10487 struct tunnel_db_element_release_ctx ctx = { 10488 .items = NULL, 10489 .actions = pmd_actions, 10490 .num_elements = num_actions, 10491 .error = err, 10492 }; 10493 10494 mlx5_access_tunnel_offload_db(dev, tunnel_element_release_match, 10495 tunnel_element_release_hit, 10496 tunnel_element_release_miss, &ctx, false); 10497 10498 return ctx.ret; 10499 } 10500 10501 static int 10502 mlx5_flow_tunnel_get_restore_info(struct rte_eth_dev *dev, 10503 struct rte_mbuf *m, 10504 struct rte_flow_restore_info *info, 10505 struct rte_flow_error *err) 10506 { 10507 uint64_t ol_flags = m->ol_flags; 10508 const struct mlx5_flow_tbl_data_entry *tble; 10509 const uint64_t mask = RTE_MBUF_F_RX_FDIR | RTE_MBUF_F_RX_FDIR_ID; 10510 10511 if (!is_tunnel_offload_active(dev)) { 10512 info->flags = 0; 10513 return 0; 10514 } 10515 10516 if ((ol_flags & mask) != mask) 10517 goto err; 10518 tble = tunnel_mark_decode(dev, m->hash.fdir.hi); 10519 if (!tble) { 10520 DRV_LOG(DEBUG, "port %u invalid miss tunnel mark %#x", 10521 dev->data->port_id, m->hash.fdir.hi); 10522 goto err; 10523 } 10524 MLX5_ASSERT(tble->tunnel); 10525 memcpy(&info->tunnel, &tble->tunnel->app_tunnel, sizeof(info->tunnel)); 10526 info->group_id = tble->group_id; 10527 info->flags = RTE_FLOW_RESTORE_INFO_TUNNEL | 10528 RTE_FLOW_RESTORE_INFO_GROUP_ID | 10529 RTE_FLOW_RESTORE_INFO_ENCAPSULATED; 10530 10531 return 0; 10532 10533 err: 10534 return rte_flow_error_set(err, EINVAL, 10535 RTE_FLOW_ERROR_TYPE_UNSPECIFIED, NULL, 10536 "failed to get restore info"); 10537 } 10538 10539 #else /* HAVE_IBV_FLOW_DV_SUPPORT */ 10540 static int 10541 mlx5_flow_tunnel_decap_set(__rte_unused struct rte_eth_dev *dev, 10542 __rte_unused struct rte_flow_tunnel *app_tunnel, 10543 __rte_unused struct rte_flow_action **actions, 10544 __rte_unused uint32_t *num_of_actions, 10545 __rte_unused struct rte_flow_error *error) 10546 { 10547 return -ENOTSUP; 10548 } 10549 10550 static int 10551 mlx5_flow_tunnel_match(__rte_unused struct rte_eth_dev *dev, 10552 __rte_unused struct rte_flow_tunnel *app_tunnel, 10553 __rte_unused struct rte_flow_item **items, 10554 __rte_unused uint32_t *num_of_items, 10555 __rte_unused struct rte_flow_error *error) 10556 { 10557 return -ENOTSUP; 10558 } 10559 10560 static int 10561 mlx5_flow_tunnel_item_release(__rte_unused struct rte_eth_dev *dev, 10562 __rte_unused struct rte_flow_item *pmd_items, 10563 __rte_unused uint32_t num_items, 10564 __rte_unused struct rte_flow_error *err) 10565 { 10566 return -ENOTSUP; 10567 } 10568 10569 static int 10570 mlx5_flow_tunnel_action_release(__rte_unused struct rte_eth_dev *dev, 10571 __rte_unused struct rte_flow_action *pmd_action, 10572 __rte_unused uint32_t num_actions, 10573 __rte_unused struct rte_flow_error *err) 10574 { 10575 return -ENOTSUP; 10576 } 10577 10578 static int 10579 mlx5_flow_tunnel_get_restore_info(__rte_unused struct rte_eth_dev *dev, 10580 __rte_unused struct rte_mbuf *m, 10581 __rte_unused struct rte_flow_restore_info *i, 10582 __rte_unused struct rte_flow_error *err) 10583 { 10584 return -ENOTSUP; 10585 } 10586 10587 static int 10588 flow_tunnel_add_default_miss(__rte_unused struct rte_eth_dev *dev, 10589 __rte_unused struct rte_flow *flow, 10590 __rte_unused const struct rte_flow_attr *attr, 10591 __rte_unused const struct rte_flow_action *actions, 10592 __rte_unused uint32_t flow_idx, 10593 __rte_unused const struct mlx5_flow_tunnel *tunnel, 10594 __rte_unused struct tunnel_default_miss_ctx *ctx, 10595 __rte_unused struct rte_flow_error *error) 10596 { 10597 return -ENOTSUP; 10598 } 10599 10600 static struct mlx5_flow_tunnel * 10601 mlx5_find_tunnel_id(__rte_unused struct rte_eth_dev *dev, 10602 __rte_unused uint32_t id) 10603 { 10604 return NULL; 10605 } 10606 10607 static void 10608 mlx5_flow_tunnel_free(__rte_unused struct rte_eth_dev *dev, 10609 __rte_unused struct mlx5_flow_tunnel *tunnel) 10610 { 10611 } 10612 10613 static uint32_t 10614 tunnel_flow_group_to_flow_table(__rte_unused struct rte_eth_dev *dev, 10615 __rte_unused const struct mlx5_flow_tunnel *t, 10616 __rte_unused uint32_t group, 10617 __rte_unused uint32_t *table, 10618 struct rte_flow_error *error) 10619 { 10620 return rte_flow_error_set(error, ENOTSUP, 10621 RTE_FLOW_ERROR_TYPE_UNSPECIFIED, NULL, 10622 "tunnel offload requires DV support"); 10623 } 10624 10625 void 10626 mlx5_release_tunnel_hub(__rte_unused struct mlx5_dev_ctx_shared *sh, 10627 __rte_unused uint16_t port_id) 10628 { 10629 } 10630 #endif /* HAVE_IBV_FLOW_DV_SUPPORT */ 10631 10632 /* Flex flow item API */ 10633 static struct rte_flow_item_flex_handle * 10634 mlx5_flow_flex_item_create(struct rte_eth_dev *dev, 10635 const struct rte_flow_item_flex_conf *conf, 10636 struct rte_flow_error *error) 10637 { 10638 static const char err_msg[] = "flex item creation unsupported"; 10639 struct mlx5_priv *priv = dev->data->dev_private; 10640 struct rte_flow_attr attr = { .transfer = 0 }; 10641 const struct mlx5_flow_driver_ops *fops = 10642 flow_get_drv_ops(flow_get_drv_type(dev, &attr)); 10643 10644 if (!priv->pci_dev) { 10645 rte_flow_error_set(error, ENOTSUP, 10646 RTE_FLOW_ERROR_TYPE_UNSPECIFIED, NULL, 10647 "create flex item on PF only"); 10648 return NULL; 10649 } 10650 switch (priv->pci_dev->id.device_id) { 10651 case PCI_DEVICE_ID_MELLANOX_CONNECTX6DXBF: 10652 case PCI_DEVICE_ID_MELLANOX_CONNECTX7BF: 10653 break; 10654 default: 10655 rte_flow_error_set(error, ENOTSUP, 10656 RTE_FLOW_ERROR_TYPE_UNSPECIFIED, NULL, 10657 "flex item available on BlueField ports only"); 10658 return NULL; 10659 } 10660 if (!fops->item_create) { 10661 DRV_LOG(ERR, "port %u %s.", dev->data->port_id, err_msg); 10662 rte_flow_error_set(error, ENOTSUP, RTE_FLOW_ERROR_TYPE_ACTION, 10663 NULL, err_msg); 10664 return NULL; 10665 } 10666 return fops->item_create(dev, conf, error); 10667 } 10668 10669 static int 10670 mlx5_flow_flex_item_release(struct rte_eth_dev *dev, 10671 const struct rte_flow_item_flex_handle *handle, 10672 struct rte_flow_error *error) 10673 { 10674 static const char err_msg[] = "flex item release unsupported"; 10675 struct rte_flow_attr attr = { .transfer = 0 }; 10676 const struct mlx5_flow_driver_ops *fops = 10677 flow_get_drv_ops(flow_get_drv_type(dev, &attr)); 10678 10679 if (!fops->item_release) { 10680 DRV_LOG(ERR, "port %u %s.", dev->data->port_id, err_msg); 10681 rte_flow_error_set(error, ENOTSUP, RTE_FLOW_ERROR_TYPE_ACTION, 10682 NULL, err_msg); 10683 return -rte_errno; 10684 } 10685 return fops->item_release(dev, handle, error); 10686 } 10687 10688 static void 10689 mlx5_dbg__print_pattern(const struct rte_flow_item *item) 10690 { 10691 int ret; 10692 struct rte_flow_error error; 10693 10694 for (; item->type != RTE_FLOW_ITEM_TYPE_END; item++) { 10695 char *item_name; 10696 ret = rte_flow_conv(RTE_FLOW_CONV_OP_ITEM_NAME_PTR, &item_name, 10697 sizeof(item_name), 10698 (void *)(uintptr_t)item->type, &error); 10699 if (ret > 0) 10700 printf("%s ", item_name); 10701 else 10702 printf("%d\n", (int)item->type); 10703 } 10704 printf("END\n"); 10705 } 10706 10707 static int 10708 mlx5_flow_is_std_vxlan_port(const struct rte_flow_item *udp_item) 10709 { 10710 const struct rte_flow_item_udp *spec = udp_item->spec; 10711 const struct rte_flow_item_udp *mask = udp_item->mask; 10712 uint16_t udp_dport = 0; 10713 10714 if (spec != NULL) { 10715 if (!mask) 10716 mask = &rte_flow_item_udp_mask; 10717 udp_dport = rte_be_to_cpu_16(spec->hdr.dst_port & 10718 mask->hdr.dst_port); 10719 } 10720 return (!udp_dport || udp_dport == MLX5_UDP_PORT_VXLAN); 10721 } 10722 10723 static const struct mlx5_flow_expand_node * 10724 mlx5_flow_expand_rss_adjust_node(const struct rte_flow_item *pattern, 10725 unsigned int item_idx, 10726 const struct mlx5_flow_expand_node graph[], 10727 const struct mlx5_flow_expand_node *node) 10728 { 10729 const struct rte_flow_item *item = pattern + item_idx, *prev_item; 10730 10731 if (item->type == RTE_FLOW_ITEM_TYPE_VXLAN && 10732 node != NULL && 10733 node->type == RTE_FLOW_ITEM_TYPE_VXLAN) { 10734 /* 10735 * The expansion node is VXLAN and it is also the last 10736 * expandable item in the pattern, so need to continue 10737 * expansion of the inner tunnel. 10738 */ 10739 MLX5_ASSERT(item_idx > 0); 10740 prev_item = pattern + item_idx - 1; 10741 MLX5_ASSERT(prev_item->type == RTE_FLOW_ITEM_TYPE_UDP); 10742 if (mlx5_flow_is_std_vxlan_port(prev_item)) 10743 return &graph[MLX5_EXPANSION_STD_VXLAN]; 10744 return &graph[MLX5_EXPANSION_L3_VXLAN]; 10745 } 10746 return node; 10747 } 10748 10749 /* Map of Verbs to Flow priority with 8 Verbs priorities. */ 10750 static const uint32_t priority_map_3[][MLX5_PRIORITY_MAP_MAX] = { 10751 { 0, 1, 2 }, { 2, 3, 4 }, { 5, 6, 7 }, 10752 }; 10753 10754 /* Map of Verbs to Flow priority with 16 Verbs priorities. */ 10755 static const uint32_t priority_map_5[][MLX5_PRIORITY_MAP_MAX] = { 10756 { 0, 1, 2 }, { 3, 4, 5 }, { 6, 7, 8 }, 10757 { 9, 10, 11 }, { 12, 13, 14 }, 10758 }; 10759 10760 /** 10761 * Discover the number of available flow priorities. 10762 * 10763 * @param dev 10764 * Ethernet device. 10765 * 10766 * @return 10767 * On success, number of available flow priorities. 10768 * On failure, a negative errno-style code and rte_errno is set. 10769 */ 10770 int 10771 mlx5_flow_discover_priorities(struct rte_eth_dev *dev) 10772 { 10773 static const uint16_t vprio[] = {8, 16}; 10774 const struct mlx5_priv *priv = dev->data->dev_private; 10775 const struct mlx5_flow_driver_ops *fops; 10776 enum mlx5_flow_drv_type type; 10777 int ret; 10778 10779 type = mlx5_flow_os_get_type(); 10780 if (type == MLX5_FLOW_TYPE_MAX) { 10781 type = MLX5_FLOW_TYPE_VERBS; 10782 if (priv->sh->cdev->config.devx && priv->sh->config.dv_flow_en) 10783 type = MLX5_FLOW_TYPE_DV; 10784 } 10785 fops = flow_get_drv_ops(type); 10786 if (fops->discover_priorities == NULL) { 10787 DRV_LOG(ERR, "Priority discovery not supported"); 10788 rte_errno = ENOTSUP; 10789 return -rte_errno; 10790 } 10791 ret = fops->discover_priorities(dev, vprio, RTE_DIM(vprio)); 10792 if (ret < 0) 10793 return ret; 10794 switch (ret) { 10795 case 8: 10796 ret = RTE_DIM(priority_map_3); 10797 break; 10798 case 16: 10799 ret = RTE_DIM(priority_map_5); 10800 break; 10801 default: 10802 rte_errno = ENOTSUP; 10803 DRV_LOG(ERR, 10804 "port %u maximum priority: %d expected 8/16", 10805 dev->data->port_id, ret); 10806 return -rte_errno; 10807 } 10808 DRV_LOG(INFO, "port %u supported flow priorities:" 10809 " 0-%d for ingress or egress root table," 10810 " 0-%d for non-root table or transfer root table.", 10811 dev->data->port_id, ret - 2, 10812 MLX5_NON_ROOT_FLOW_MAX_PRIO - 1); 10813 return ret; 10814 } 10815 10816 /** 10817 * Adjust flow priority based on the highest layer and the request priority. 10818 * 10819 * @param[in] dev 10820 * Pointer to the Ethernet device structure. 10821 * @param[in] priority 10822 * The rule base priority. 10823 * @param[in] subpriority 10824 * The priority based on the items. 10825 * 10826 * @return 10827 * The new priority. 10828 */ 10829 uint32_t 10830 mlx5_flow_adjust_priority(struct rte_eth_dev *dev, int32_t priority, 10831 uint32_t subpriority) 10832 { 10833 uint32_t res = 0; 10834 struct mlx5_priv *priv = dev->data->dev_private; 10835 10836 switch (priv->sh->flow_max_priority) { 10837 case RTE_DIM(priority_map_3): 10838 res = priority_map_3[priority][subpriority]; 10839 break; 10840 case RTE_DIM(priority_map_5): 10841 res = priority_map_5[priority][subpriority]; 10842 break; 10843 } 10844 return res; 10845 } 10846