1 /* SPDX-License-Identifier: BSD-3-Clause 2 * Copyright 2016 6WIND S.A. 3 * Copyright 2016 Mellanox Technologies, Ltd 4 */ 5 6 #include <stdalign.h> 7 #include <stdint.h> 8 #include <string.h> 9 #include <stdbool.h> 10 #include <sys/queue.h> 11 12 #include <rte_common.h> 13 #include <rte_ether.h> 14 #include <ethdev_driver.h> 15 #include <rte_eal_paging.h> 16 #include <rte_flow.h> 17 #include <rte_cycles.h> 18 #include <rte_flow_driver.h> 19 #include <rte_malloc.h> 20 #include <rte_ip.h> 21 22 #include <mlx5_glue.h> 23 #include <mlx5_devx_cmds.h> 24 #include <mlx5_prm.h> 25 #include <mlx5_malloc.h> 26 27 #include "mlx5_defs.h" 28 #include "mlx5.h" 29 #include "mlx5_flow.h" 30 #include "mlx5_flow_os.h" 31 #include "mlx5_rx.h" 32 #include "mlx5_tx.h" 33 #include "mlx5_common_os.h" 34 #include "rte_pmd_mlx5.h" 35 36 /* 37 * Shared array for quick translation between port_id and vport mask/values 38 * used for HWS rules. 39 */ 40 struct flow_hw_port_info mlx5_flow_hw_port_infos[RTE_MAX_ETHPORTS]; 41 42 struct tunnel_default_miss_ctx { 43 uint16_t *queue; 44 __extension__ 45 union { 46 struct rte_flow_action_rss action_rss; 47 struct rte_flow_action_queue miss_queue; 48 struct rte_flow_action_jump miss_jump; 49 uint8_t raw[0]; 50 }; 51 }; 52 53 void 54 mlx5_indirect_list_handles_release(struct rte_eth_dev *dev) 55 { 56 struct mlx5_priv *priv = dev->data->dev_private; 57 #ifdef HAVE_MLX5_HWS_SUPPORT 58 struct rte_flow_error error; 59 #endif 60 61 while (!LIST_EMPTY(&priv->indirect_list_head)) { 62 struct mlx5_indirect_list *e = 63 LIST_FIRST(&priv->indirect_list_head); 64 65 LIST_REMOVE(e, entry); 66 switch (e->type) { 67 #ifdef HAVE_MLX5_HWS_SUPPORT 68 case MLX5_INDIRECT_ACTION_LIST_TYPE_MIRROR: 69 mlx5_hw_mirror_destroy(dev, (struct mlx5_mirror *)e); 70 break; 71 case MLX5_INDIRECT_ACTION_LIST_TYPE_LEGACY: 72 mlx5_destroy_legacy_indirect(dev, e); 73 break; 74 case MLX5_INDIRECT_ACTION_LIST_TYPE_REFORMAT: 75 mlx5_reformat_action_destroy(dev, 76 (struct rte_flow_action_list_handle *)e, &error); 77 break; 78 #endif 79 default: 80 DRV_LOG(ERR, "invalid indirect list type"); 81 MLX5_ASSERT(false); 82 break; 83 } 84 } 85 } 86 87 static int 88 flow_tunnel_add_default_miss(struct rte_eth_dev *dev, 89 struct rte_flow *flow, 90 const struct rte_flow_attr *attr, 91 const struct rte_flow_action *app_actions, 92 uint32_t flow_idx, 93 const struct mlx5_flow_tunnel *tunnel, 94 struct tunnel_default_miss_ctx *ctx, 95 struct rte_flow_error *error); 96 static struct mlx5_flow_tunnel * 97 mlx5_find_tunnel_id(struct rte_eth_dev *dev, uint32_t id); 98 static void 99 mlx5_flow_tunnel_free(struct rte_eth_dev *dev, struct mlx5_flow_tunnel *tunnel); 100 static uint32_t 101 tunnel_flow_group_to_flow_table(struct rte_eth_dev *dev, 102 const struct mlx5_flow_tunnel *tunnel, 103 uint32_t group, uint32_t *table, 104 struct rte_flow_error *error); 105 106 /** Device flow drivers. */ 107 extern const struct mlx5_flow_driver_ops mlx5_flow_verbs_drv_ops; 108 109 const struct mlx5_flow_driver_ops mlx5_flow_null_drv_ops; 110 111 const struct mlx5_flow_driver_ops *flow_drv_ops[] = { 112 [MLX5_FLOW_TYPE_MIN] = &mlx5_flow_null_drv_ops, 113 #if defined(HAVE_IBV_FLOW_DV_SUPPORT) || !defined(HAVE_INFINIBAND_VERBS_H) 114 [MLX5_FLOW_TYPE_DV] = &mlx5_flow_dv_drv_ops, 115 #endif 116 #ifdef HAVE_MLX5_HWS_SUPPORT 117 [MLX5_FLOW_TYPE_HW] = &mlx5_flow_hw_drv_ops, 118 #endif 119 [MLX5_FLOW_TYPE_VERBS] = &mlx5_flow_verbs_drv_ops, 120 [MLX5_FLOW_TYPE_MAX] = &mlx5_flow_null_drv_ops 121 }; 122 123 /** Helper macro to build input graph for mlx5_flow_expand_rss(). */ 124 #define MLX5_FLOW_EXPAND_RSS_NEXT(...) \ 125 (const int []){ \ 126 __VA_ARGS__, 0, \ 127 } 128 129 /** Node object of input graph for mlx5_flow_expand_rss(). */ 130 struct mlx5_flow_expand_node { 131 const int *const next; 132 /**< 133 * List of next node indexes. Index 0 is interpreted as a terminator. 134 */ 135 const enum rte_flow_item_type type; 136 /**< Pattern item type of current node. */ 137 uint64_t rss_types; 138 /**< 139 * RSS types bit-field associated with this node 140 * (see RTE_ETH_RSS_* definitions). 141 */ 142 uint64_t node_flags; 143 /**< 144 * Bit-fields that define how the node is used in the expansion. 145 * (see MLX5_EXPANSION_NODE_* definitions). 146 */ 147 }; 148 149 /** Keep same format with mlx5_flow_expand_rss to share the buffer for expansion. */ 150 struct mlx5_flow_expand_sqn { 151 uint32_t entries; /** Number of entries */ 152 struct { 153 struct rte_flow_item *pattern; /**< Expanded pattern array. */ 154 uint32_t priority; /**< Priority offset for each expansion. */ 155 } entry[]; 156 }; 157 158 /* Optional expand field. The expansion alg will not go deeper. */ 159 #define MLX5_EXPANSION_NODE_OPTIONAL (UINT64_C(1) << 0) 160 161 /* The node is not added implicitly as expansion to the flow pattern. 162 * If the node type does not match the flow pattern item type, the 163 * expansion alg will go deeper to its next items. 164 * In the current implementation, the list of next nodes indexes can 165 * have up to one node with this flag set and it has to be the last 166 * node index (before the list terminator). 167 */ 168 #define MLX5_EXPANSION_NODE_EXPLICIT (UINT64_C(1) << 1) 169 170 /** Object returned by mlx5_flow_expand_rss(). */ 171 struct mlx5_flow_expand_rss { 172 uint32_t entries; 173 /**< Number of entries @p patterns and @p priorities. */ 174 struct { 175 struct rte_flow_item *pattern; /**< Expanded pattern array. */ 176 uint32_t priority; /**< Priority offset for each expansion. */ 177 } entry[]; 178 }; 179 180 static void 181 mlx5_dbg__print_pattern(const struct rte_flow_item *item); 182 183 static const struct mlx5_flow_expand_node * 184 mlx5_flow_expand_rss_adjust_node(const struct rte_flow_item *pattern, 185 unsigned int item_idx, 186 const struct mlx5_flow_expand_node graph[], 187 const struct mlx5_flow_expand_node *node); 188 189 static __rte_always_inline int 190 mlx5_need_cache_flow(const struct mlx5_priv *priv, 191 const struct rte_flow_attr *attr) 192 { 193 return priv->isolated && priv->sh->config.dv_flow_en == 1 && 194 (attr ? !attr->group : true) && 195 priv->mode_info.mode == RTE_PMD_MLX5_FLOW_ENGINE_MODE_STANDBY && 196 (!priv->sh->config.dv_esw_en || !priv->sh->config.fdb_def_rule); 197 } 198 199 static bool 200 mlx5_flow_is_rss_expandable_item(const struct rte_flow_item *item) 201 { 202 switch (item->type) { 203 case RTE_FLOW_ITEM_TYPE_ETH: 204 case RTE_FLOW_ITEM_TYPE_VLAN: 205 case RTE_FLOW_ITEM_TYPE_IPV4: 206 case RTE_FLOW_ITEM_TYPE_IPV6: 207 case RTE_FLOW_ITEM_TYPE_UDP: 208 case RTE_FLOW_ITEM_TYPE_TCP: 209 case RTE_FLOW_ITEM_TYPE_ESP: 210 case RTE_FLOW_ITEM_TYPE_ICMP: 211 case RTE_FLOW_ITEM_TYPE_ICMP6: 212 case RTE_FLOW_ITEM_TYPE_VXLAN: 213 case RTE_FLOW_ITEM_TYPE_NVGRE: 214 case RTE_FLOW_ITEM_TYPE_GRE: 215 case RTE_FLOW_ITEM_TYPE_GENEVE: 216 case RTE_FLOW_ITEM_TYPE_MPLS: 217 case RTE_FLOW_ITEM_TYPE_VXLAN_GPE: 218 case RTE_FLOW_ITEM_TYPE_GRE_KEY: 219 case RTE_FLOW_ITEM_TYPE_IPV6_FRAG_EXT: 220 case RTE_FLOW_ITEM_TYPE_GTP: 221 return true; 222 default: 223 break; 224 } 225 return false; 226 } 227 228 /** 229 * Network Service Header (NSH) and its next protocol values 230 * are described in RFC-8393. 231 */ 232 static enum rte_flow_item_type 233 mlx5_nsh_proto_to_item_type(uint8_t proto_spec, uint8_t proto_mask) 234 { 235 enum rte_flow_item_type type; 236 237 switch (proto_mask & proto_spec) { 238 case 0: 239 type = RTE_FLOW_ITEM_TYPE_VOID; 240 break; 241 case RTE_VXLAN_GPE_TYPE_IPV4: 242 type = RTE_FLOW_ITEM_TYPE_IPV4; 243 break; 244 case RTE_VXLAN_GPE_TYPE_IPV6: 245 type = RTE_VXLAN_GPE_TYPE_IPV6; 246 break; 247 case RTE_VXLAN_GPE_TYPE_ETH: 248 type = RTE_FLOW_ITEM_TYPE_ETH; 249 break; 250 default: 251 type = RTE_FLOW_ITEM_TYPE_END; 252 } 253 return type; 254 } 255 256 static enum rte_flow_item_type 257 mlx5_inet_proto_to_item_type(uint8_t proto_spec, uint8_t proto_mask) 258 { 259 enum rte_flow_item_type type; 260 261 switch (proto_mask & proto_spec) { 262 case 0: 263 type = RTE_FLOW_ITEM_TYPE_VOID; 264 break; 265 case IPPROTO_UDP: 266 type = RTE_FLOW_ITEM_TYPE_UDP; 267 break; 268 case IPPROTO_TCP: 269 type = RTE_FLOW_ITEM_TYPE_TCP; 270 break; 271 case IPPROTO_IPIP: 272 type = RTE_FLOW_ITEM_TYPE_IPV4; 273 break; 274 case IPPROTO_IPV6: 275 type = RTE_FLOW_ITEM_TYPE_IPV6; 276 break; 277 case IPPROTO_ESP: 278 type = RTE_FLOW_ITEM_TYPE_ESP; 279 break; 280 default: 281 type = RTE_FLOW_ITEM_TYPE_END; 282 } 283 return type; 284 } 285 286 static enum rte_flow_item_type 287 mlx5_ethertype_to_item_type(rte_be16_t type_spec, 288 rte_be16_t type_mask, bool is_tunnel) 289 { 290 enum rte_flow_item_type type; 291 292 switch (rte_be_to_cpu_16(type_spec & type_mask)) { 293 case 0: 294 type = RTE_FLOW_ITEM_TYPE_VOID; 295 break; 296 case RTE_ETHER_TYPE_TEB: 297 type = is_tunnel ? 298 RTE_FLOW_ITEM_TYPE_ETH : RTE_FLOW_ITEM_TYPE_END; 299 break; 300 case RTE_ETHER_TYPE_VLAN: 301 type = !is_tunnel ? 302 RTE_FLOW_ITEM_TYPE_VLAN : RTE_FLOW_ITEM_TYPE_END; 303 break; 304 case RTE_ETHER_TYPE_IPV4: 305 type = RTE_FLOW_ITEM_TYPE_IPV4; 306 break; 307 case RTE_ETHER_TYPE_IPV6: 308 type = RTE_FLOW_ITEM_TYPE_IPV6; 309 break; 310 default: 311 type = RTE_FLOW_ITEM_TYPE_END; 312 } 313 return type; 314 } 315 316 static enum rte_flow_item_type 317 mlx5_flow_expand_rss_item_complete(const struct rte_flow_item *item) 318 { 319 #define MLX5_XSET_ITEM_MASK_SPEC(type, fld) \ 320 do { \ 321 const void *m = item->mask; \ 322 const void *s = item->spec; \ 323 mask = m ? \ 324 ((const struct rte_flow_item_##type *)m)->fld : \ 325 rte_flow_item_##type##_mask.fld; \ 326 spec = ((const struct rte_flow_item_##type *)s)->fld; \ 327 } while (0) 328 329 enum rte_flow_item_type ret; 330 uint16_t spec, mask; 331 332 if (item == NULL || item->spec == NULL) 333 return RTE_FLOW_ITEM_TYPE_VOID; 334 switch (item->type) { 335 case RTE_FLOW_ITEM_TYPE_ETH: 336 MLX5_XSET_ITEM_MASK_SPEC(eth, hdr.ether_type); 337 if (!mask) 338 return RTE_FLOW_ITEM_TYPE_VOID; 339 ret = mlx5_ethertype_to_item_type(spec, mask, false); 340 break; 341 case RTE_FLOW_ITEM_TYPE_VLAN: 342 MLX5_XSET_ITEM_MASK_SPEC(vlan, hdr.eth_proto); 343 if (!mask) 344 return RTE_FLOW_ITEM_TYPE_VOID; 345 ret = mlx5_ethertype_to_item_type(spec, mask, false); 346 break; 347 case RTE_FLOW_ITEM_TYPE_IPV4: 348 MLX5_XSET_ITEM_MASK_SPEC(ipv4, hdr.next_proto_id); 349 if (!mask) 350 return RTE_FLOW_ITEM_TYPE_VOID; 351 ret = mlx5_inet_proto_to_item_type(spec, mask); 352 break; 353 case RTE_FLOW_ITEM_TYPE_IPV6: 354 MLX5_XSET_ITEM_MASK_SPEC(ipv6, hdr.proto); 355 if (!mask) 356 return RTE_FLOW_ITEM_TYPE_VOID; 357 ret = mlx5_inet_proto_to_item_type(spec, mask); 358 break; 359 case RTE_FLOW_ITEM_TYPE_GENEVE: 360 MLX5_XSET_ITEM_MASK_SPEC(geneve, protocol); 361 ret = mlx5_ethertype_to_item_type(spec, mask, true); 362 break; 363 case RTE_FLOW_ITEM_TYPE_GRE: 364 MLX5_XSET_ITEM_MASK_SPEC(gre, protocol); 365 ret = mlx5_ethertype_to_item_type(spec, mask, true); 366 break; 367 case RTE_FLOW_ITEM_TYPE_VXLAN_GPE: 368 MLX5_XSET_ITEM_MASK_SPEC(vxlan_gpe, hdr.proto); 369 ret = mlx5_nsh_proto_to_item_type(spec, mask); 370 break; 371 default: 372 ret = RTE_FLOW_ITEM_TYPE_VOID; 373 break; 374 } 375 return ret; 376 #undef MLX5_XSET_ITEM_MASK_SPEC 377 } 378 379 static const int * 380 mlx5_flow_expand_rss_skip_explicit(const struct mlx5_flow_expand_node graph[], 381 const int *next_node) 382 { 383 const struct mlx5_flow_expand_node *node = NULL; 384 const int *next = next_node; 385 386 while (next && *next) { 387 /* 388 * Skip the nodes with the MLX5_EXPANSION_NODE_EXPLICIT 389 * flag set, because they were not found in the flow pattern. 390 */ 391 node = &graph[*next]; 392 if (!(node->node_flags & MLX5_EXPANSION_NODE_EXPLICIT)) 393 break; 394 next = node->next; 395 } 396 return next; 397 } 398 399 #define MLX5_RSS_EXP_ELT_N 32 400 401 /** 402 * Expand RSS flows into several possible flows according to the RSS hash 403 * fields requested and the driver capabilities. 404 * 405 * @param[out] buf 406 * Buffer to store the result expansion. 407 * @param[in] size 408 * Buffer size in bytes. If 0, @p buf can be NULL. 409 * @param[in] pattern 410 * User flow pattern. 411 * @param[in] types 412 * RSS types to expand (see RTE_ETH_RSS_* definitions). 413 * @param[in] graph 414 * Input graph to expand @p pattern according to @p types. 415 * @param[in] graph_root_index 416 * Index of root node in @p graph, typically 0. 417 * 418 * @return 419 * A positive value representing the size of @p buf in bytes regardless of 420 * @p size on success, a negative errno value otherwise and rte_errno is 421 * set, the following errors are defined: 422 * 423 * -E2BIG: graph-depth @p graph is too deep. 424 * -EINVAL: @p size has not enough space for expanded pattern. 425 */ 426 static int 427 mlx5_flow_expand_rss(struct mlx5_flow_expand_rss *buf, size_t size, 428 const struct rte_flow_item *pattern, uint64_t types, 429 const struct mlx5_flow_expand_node graph[], 430 int graph_root_index) 431 { 432 const struct rte_flow_item *item; 433 const struct mlx5_flow_expand_node *node = &graph[graph_root_index]; 434 const int *next_node; 435 const int *stack[MLX5_RSS_EXP_ELT_N]; 436 int stack_pos = 0; 437 struct rte_flow_item flow_items[MLX5_RSS_EXP_ELT_N]; 438 unsigned int i, item_idx, last_expand_item_idx = 0; 439 size_t lsize; 440 size_t user_pattern_size = 0; 441 void *addr = NULL; 442 const struct mlx5_flow_expand_node *next = NULL; 443 struct rte_flow_item missed_item; 444 int missed = 0; 445 int elt = 0; 446 const struct rte_flow_item *last_expand_item = NULL; 447 448 memset(&missed_item, 0, sizeof(missed_item)); 449 lsize = offsetof(struct mlx5_flow_expand_rss, entry) + 450 MLX5_RSS_EXP_ELT_N * sizeof(buf->entry[0]); 451 if (lsize > size) 452 return -EINVAL; 453 buf->entry[0].priority = 0; 454 buf->entry[0].pattern = (void *)&buf->entry[MLX5_RSS_EXP_ELT_N]; 455 buf->entries = 0; 456 addr = buf->entry[0].pattern; 457 for (item = pattern, item_idx = 0; 458 item->type != RTE_FLOW_ITEM_TYPE_END; 459 item++, item_idx++) { 460 if (!mlx5_flow_is_rss_expandable_item(item)) { 461 user_pattern_size += sizeof(*item); 462 continue; 463 } 464 last_expand_item = item; 465 last_expand_item_idx = item_idx; 466 i = 0; 467 while (node->next && node->next[i]) { 468 next = &graph[node->next[i]]; 469 if (next->type == item->type) 470 break; 471 if (next->node_flags & MLX5_EXPANSION_NODE_EXPLICIT) { 472 node = next; 473 i = 0; 474 } else { 475 ++i; 476 } 477 } 478 if (next) 479 node = next; 480 user_pattern_size += sizeof(*item); 481 } 482 user_pattern_size += sizeof(*item); /* Handle END item. */ 483 lsize += user_pattern_size; 484 if (lsize > size) 485 return -EINVAL; 486 /* Copy the user pattern in the first entry of the buffer. */ 487 rte_memcpy(addr, pattern, user_pattern_size); 488 addr = (void *)(((uintptr_t)addr) + user_pattern_size); 489 buf->entries = 1; 490 /* Start expanding. */ 491 memset(flow_items, 0, sizeof(flow_items)); 492 user_pattern_size -= sizeof(*item); 493 /* 494 * Check if the last valid item has spec set, need complete pattern, 495 * and the pattern can be used for expansion. 496 */ 497 missed_item.type = mlx5_flow_expand_rss_item_complete(last_expand_item); 498 if (missed_item.type == RTE_FLOW_ITEM_TYPE_END) { 499 /* Item type END indicates expansion is not required. */ 500 return lsize; 501 } 502 if (missed_item.type != RTE_FLOW_ITEM_TYPE_VOID) { 503 next = NULL; 504 missed = 1; 505 i = 0; 506 while (node->next && node->next[i]) { 507 next = &graph[node->next[i]]; 508 if (next->type == missed_item.type) { 509 flow_items[0].type = missed_item.type; 510 flow_items[1].type = RTE_FLOW_ITEM_TYPE_END; 511 break; 512 } 513 if (next->node_flags & MLX5_EXPANSION_NODE_EXPLICIT) { 514 node = next; 515 i = 0; 516 } else { 517 ++i; 518 } 519 next = NULL; 520 } 521 } 522 if (next && missed) { 523 elt = 2; /* missed item + item end. */ 524 node = next; 525 lsize += elt * sizeof(*item) + user_pattern_size; 526 if (lsize > size) 527 return -EINVAL; 528 if (node->rss_types & types) { 529 buf->entry[buf->entries].priority = 1; 530 buf->entry[buf->entries].pattern = addr; 531 buf->entries++; 532 rte_memcpy(addr, buf->entry[0].pattern, 533 user_pattern_size); 534 addr = (void *)(((uintptr_t)addr) + user_pattern_size); 535 rte_memcpy(addr, flow_items, elt * sizeof(*item)); 536 addr = (void *)(((uintptr_t)addr) + 537 elt * sizeof(*item)); 538 } 539 } else if (last_expand_item != NULL) { 540 node = mlx5_flow_expand_rss_adjust_node(pattern, 541 last_expand_item_idx, graph, node); 542 } 543 memset(flow_items, 0, sizeof(flow_items)); 544 next_node = mlx5_flow_expand_rss_skip_explicit(graph, 545 node->next); 546 stack[stack_pos] = next_node; 547 node = next_node ? &graph[*next_node] : NULL; 548 while (node) { 549 flow_items[stack_pos].type = node->type; 550 if (node->rss_types & types) { 551 size_t n; 552 /* 553 * compute the number of items to copy from the 554 * expansion and copy it. 555 * When the stack_pos is 0, there are 1 element in it, 556 * plus the addition END item. 557 */ 558 elt = stack_pos + 2; 559 flow_items[stack_pos + 1].type = RTE_FLOW_ITEM_TYPE_END; 560 lsize += elt * sizeof(*item) + user_pattern_size; 561 if (lsize > size) 562 return -EINVAL; 563 n = elt * sizeof(*item); 564 MLX5_ASSERT((buf->entries) < MLX5_RSS_EXP_ELT_N); 565 buf->entry[buf->entries].priority = 566 stack_pos + 1 + missed; 567 buf->entry[buf->entries].pattern = addr; 568 buf->entries++; 569 rte_memcpy(addr, buf->entry[0].pattern, 570 user_pattern_size); 571 addr = (void *)(((uintptr_t)addr) + 572 user_pattern_size); 573 rte_memcpy(addr, &missed_item, 574 missed * sizeof(*item)); 575 addr = (void *)(((uintptr_t)addr) + 576 missed * sizeof(*item)); 577 rte_memcpy(addr, flow_items, n); 578 addr = (void *)(((uintptr_t)addr) + n); 579 } 580 /* Go deeper. */ 581 if (!(node->node_flags & MLX5_EXPANSION_NODE_OPTIONAL) && 582 node->next) { 583 next_node = mlx5_flow_expand_rss_skip_explicit(graph, 584 node->next); 585 if (stack_pos++ == MLX5_RSS_EXP_ELT_N) { 586 rte_errno = E2BIG; 587 return -rte_errno; 588 } 589 stack[stack_pos] = next_node; 590 } else if (*(next_node + 1)) { 591 /* Follow up with the next possibility. */ 592 next_node = mlx5_flow_expand_rss_skip_explicit(graph, 593 ++next_node); 594 } else if (!stack_pos) { 595 /* 596 * Completing the traverse over the different paths. 597 * The next_node is advanced to the terminator. 598 */ 599 ++next_node; 600 } else { 601 /* Move to the next path. */ 602 while (stack_pos) { 603 next_node = stack[--stack_pos]; 604 next_node++; 605 if (*next_node) 606 break; 607 } 608 next_node = mlx5_flow_expand_rss_skip_explicit(graph, 609 next_node); 610 stack[stack_pos] = next_node; 611 } 612 node = next_node && *next_node ? &graph[*next_node] : NULL; 613 }; 614 return lsize; 615 } 616 617 /** 618 * Expand SQN flows into several possible flows according to the Tx queue 619 * number 620 * 621 * @param[in] buf 622 * Buffer to store the result expansion. 623 * @param[in] size 624 * Buffer size in bytes. If 0, @p buf can be NULL. 625 * @param[in] pattern 626 * User flow pattern. 627 * @param[in] sq_specs 628 * Buffer to store sq spec. 629 * 630 * @return 631 * 0 for success and negative value for failure 632 * 633 */ 634 static int 635 mlx5_flow_expand_sqn(struct mlx5_flow_expand_sqn *buf, size_t size, 636 const struct rte_flow_item *pattern, 637 struct mlx5_rte_flow_item_sq *sq_specs) 638 { 639 const struct rte_flow_item *item; 640 bool port_representor = false; 641 size_t user_pattern_size = 0; 642 struct rte_eth_dev *dev; 643 struct mlx5_priv *priv; 644 void *addr = NULL; 645 uint16_t port_id; 646 size_t lsize; 647 int elt = 2; 648 uint16_t i; 649 650 buf->entries = 0; 651 for (item = pattern; item->type != RTE_FLOW_ITEM_TYPE_END; item++) { 652 if (item->type == RTE_FLOW_ITEM_TYPE_PORT_REPRESENTOR) { 653 const struct rte_flow_item_ethdev *pid_v = item->spec; 654 655 if (!pid_v) 656 return 0; 657 port_id = pid_v->port_id; 658 port_representor = true; 659 } 660 user_pattern_size += sizeof(*item); 661 } 662 if (!port_representor) 663 return 0; 664 dev = &rte_eth_devices[port_id]; 665 priv = dev->data->dev_private; 666 buf->entry[0].pattern = (void *)&buf->entry[priv->txqs_n]; 667 lsize = offsetof(struct mlx5_flow_expand_sqn, entry) + 668 sizeof(buf->entry[0]) * priv->txqs_n; 669 if (lsize + (user_pattern_size + sizeof(struct rte_flow_item) * elt) * priv->txqs_n > size) 670 return -EINVAL; 671 addr = buf->entry[0].pattern; 672 for (i = 0; i != priv->txqs_n; ++i) { 673 struct rte_flow_item pattern_add[] = { 674 { 675 .type = (enum rte_flow_item_type) 676 MLX5_RTE_FLOW_ITEM_TYPE_SQ, 677 .spec = &sq_specs[i], 678 }, 679 { 680 .type = RTE_FLOW_ITEM_TYPE_END, 681 }, 682 }; 683 struct mlx5_txq_ctrl *txq = mlx5_txq_get(dev, i); 684 685 if (txq == NULL) 686 return -EINVAL; 687 buf->entry[i].pattern = addr; 688 sq_specs[i].queue = mlx5_txq_get_sqn(txq); 689 mlx5_txq_release(dev, i); 690 rte_memcpy(addr, pattern, user_pattern_size); 691 addr = (void *)(((uintptr_t)addr) + user_pattern_size); 692 rte_memcpy(addr, pattern_add, sizeof(struct rte_flow_item) * elt); 693 addr = (void *)(((uintptr_t)addr) + sizeof(struct rte_flow_item) * elt); 694 buf->entries++; 695 } 696 return 0; 697 } 698 699 enum mlx5_expansion { 700 MLX5_EXPANSION_ROOT, 701 MLX5_EXPANSION_ROOT_OUTER, 702 MLX5_EXPANSION_OUTER_ETH, 703 MLX5_EXPANSION_OUTER_VLAN, 704 MLX5_EXPANSION_OUTER_IPV4, 705 MLX5_EXPANSION_OUTER_IPV4_UDP, 706 MLX5_EXPANSION_OUTER_IPV4_TCP, 707 MLX5_EXPANSION_OUTER_IPV4_ESP, 708 MLX5_EXPANSION_OUTER_IPV4_ICMP, 709 MLX5_EXPANSION_OUTER_IPV6, 710 MLX5_EXPANSION_OUTER_IPV6_UDP, 711 MLX5_EXPANSION_OUTER_IPV6_TCP, 712 MLX5_EXPANSION_OUTER_IPV6_ESP, 713 MLX5_EXPANSION_OUTER_IPV6_ICMP6, 714 MLX5_EXPANSION_VXLAN, 715 MLX5_EXPANSION_STD_VXLAN, 716 MLX5_EXPANSION_L3_VXLAN, 717 MLX5_EXPANSION_VXLAN_GPE, 718 MLX5_EXPANSION_GRE, 719 MLX5_EXPANSION_NVGRE, 720 MLX5_EXPANSION_GRE_KEY, 721 MLX5_EXPANSION_MPLS, 722 MLX5_EXPANSION_ETH, 723 MLX5_EXPANSION_VLAN, 724 MLX5_EXPANSION_IPV4, 725 MLX5_EXPANSION_IPV4_UDP, 726 MLX5_EXPANSION_IPV4_TCP, 727 MLX5_EXPANSION_IPV4_ESP, 728 MLX5_EXPANSION_IPV4_ICMP, 729 MLX5_EXPANSION_IPV6, 730 MLX5_EXPANSION_IPV6_UDP, 731 MLX5_EXPANSION_IPV6_TCP, 732 MLX5_EXPANSION_IPV6_ESP, 733 MLX5_EXPANSION_IPV6_ICMP6, 734 MLX5_EXPANSION_IPV6_FRAG_EXT, 735 MLX5_EXPANSION_GTP, 736 MLX5_EXPANSION_GENEVE, 737 }; 738 739 /** Supported expansion of items. */ 740 static const struct mlx5_flow_expand_node mlx5_support_expansion[] = { 741 [MLX5_EXPANSION_ROOT] = { 742 .next = MLX5_FLOW_EXPAND_RSS_NEXT(MLX5_EXPANSION_ETH, 743 MLX5_EXPANSION_IPV4, 744 MLX5_EXPANSION_IPV6), 745 .type = RTE_FLOW_ITEM_TYPE_END, 746 }, 747 [MLX5_EXPANSION_ROOT_OUTER] = { 748 .next = MLX5_FLOW_EXPAND_RSS_NEXT(MLX5_EXPANSION_OUTER_ETH, 749 MLX5_EXPANSION_OUTER_IPV4, 750 MLX5_EXPANSION_OUTER_IPV6), 751 .type = RTE_FLOW_ITEM_TYPE_END, 752 }, 753 [MLX5_EXPANSION_OUTER_ETH] = { 754 .next = MLX5_FLOW_EXPAND_RSS_NEXT(MLX5_EXPANSION_OUTER_VLAN), 755 .type = RTE_FLOW_ITEM_TYPE_ETH, 756 .rss_types = 0, 757 }, 758 [MLX5_EXPANSION_OUTER_VLAN] = { 759 .next = MLX5_FLOW_EXPAND_RSS_NEXT(MLX5_EXPANSION_OUTER_IPV4, 760 MLX5_EXPANSION_OUTER_IPV6), 761 .type = RTE_FLOW_ITEM_TYPE_VLAN, 762 .node_flags = MLX5_EXPANSION_NODE_EXPLICIT, 763 }, 764 [MLX5_EXPANSION_OUTER_IPV4] = { 765 .next = MLX5_FLOW_EXPAND_RSS_NEXT 766 (MLX5_EXPANSION_OUTER_IPV4_UDP, 767 MLX5_EXPANSION_OUTER_IPV4_TCP, 768 MLX5_EXPANSION_OUTER_IPV4_ESP, 769 MLX5_EXPANSION_OUTER_IPV4_ICMP, 770 MLX5_EXPANSION_GRE, 771 MLX5_EXPANSION_NVGRE, 772 MLX5_EXPANSION_IPV4, 773 MLX5_EXPANSION_IPV6), 774 .type = RTE_FLOW_ITEM_TYPE_IPV4, 775 .rss_types = RTE_ETH_RSS_IPV4 | RTE_ETH_RSS_FRAG_IPV4 | 776 RTE_ETH_RSS_NONFRAG_IPV4_OTHER, 777 }, 778 [MLX5_EXPANSION_OUTER_IPV4_UDP] = { 779 .next = MLX5_FLOW_EXPAND_RSS_NEXT(MLX5_EXPANSION_VXLAN, 780 MLX5_EXPANSION_VXLAN_GPE, 781 MLX5_EXPANSION_MPLS, 782 MLX5_EXPANSION_GENEVE, 783 MLX5_EXPANSION_GTP), 784 .type = RTE_FLOW_ITEM_TYPE_UDP, 785 .rss_types = RTE_ETH_RSS_NONFRAG_IPV4_UDP, 786 }, 787 [MLX5_EXPANSION_OUTER_IPV4_TCP] = { 788 .type = RTE_FLOW_ITEM_TYPE_TCP, 789 .rss_types = RTE_ETH_RSS_NONFRAG_IPV4_TCP, 790 }, 791 [MLX5_EXPANSION_OUTER_IPV4_ESP] = { 792 .type = RTE_FLOW_ITEM_TYPE_ESP, 793 .rss_types = RTE_ETH_RSS_ESP, 794 }, 795 [MLX5_EXPANSION_OUTER_IPV4_ICMP] = { 796 .type = RTE_FLOW_ITEM_TYPE_ICMP, 797 }, 798 [MLX5_EXPANSION_OUTER_IPV6] = { 799 .next = MLX5_FLOW_EXPAND_RSS_NEXT 800 (MLX5_EXPANSION_OUTER_IPV6_UDP, 801 MLX5_EXPANSION_OUTER_IPV6_TCP, 802 MLX5_EXPANSION_OUTER_IPV6_ESP, 803 MLX5_EXPANSION_OUTER_IPV6_ICMP6, 804 MLX5_EXPANSION_IPV4, 805 MLX5_EXPANSION_IPV6, 806 MLX5_EXPANSION_GRE, 807 MLX5_EXPANSION_NVGRE), 808 .type = RTE_FLOW_ITEM_TYPE_IPV6, 809 .rss_types = RTE_ETH_RSS_IPV6 | RTE_ETH_RSS_FRAG_IPV6 | 810 RTE_ETH_RSS_NONFRAG_IPV6_OTHER, 811 }, 812 [MLX5_EXPANSION_OUTER_IPV6_UDP] = { 813 .next = MLX5_FLOW_EXPAND_RSS_NEXT(MLX5_EXPANSION_VXLAN, 814 MLX5_EXPANSION_VXLAN_GPE, 815 MLX5_EXPANSION_MPLS, 816 MLX5_EXPANSION_GENEVE, 817 MLX5_EXPANSION_GTP), 818 .type = RTE_FLOW_ITEM_TYPE_UDP, 819 .rss_types = RTE_ETH_RSS_NONFRAG_IPV6_UDP, 820 }, 821 [MLX5_EXPANSION_OUTER_IPV6_TCP] = { 822 .type = RTE_FLOW_ITEM_TYPE_TCP, 823 .rss_types = RTE_ETH_RSS_NONFRAG_IPV6_TCP, 824 }, 825 [MLX5_EXPANSION_OUTER_IPV6_ESP] = { 826 .type = RTE_FLOW_ITEM_TYPE_ESP, 827 .rss_types = RTE_ETH_RSS_ESP, 828 }, 829 [MLX5_EXPANSION_OUTER_IPV6_ICMP6] = { 830 .type = RTE_FLOW_ITEM_TYPE_ICMP6, 831 }, 832 [MLX5_EXPANSION_VXLAN] = { 833 .next = MLX5_FLOW_EXPAND_RSS_NEXT(MLX5_EXPANSION_ETH, 834 MLX5_EXPANSION_IPV4, 835 MLX5_EXPANSION_IPV6), 836 .type = RTE_FLOW_ITEM_TYPE_VXLAN, 837 }, 838 [MLX5_EXPANSION_STD_VXLAN] = { 839 .next = MLX5_FLOW_EXPAND_RSS_NEXT(MLX5_EXPANSION_ETH), 840 .type = RTE_FLOW_ITEM_TYPE_VXLAN, 841 }, 842 [MLX5_EXPANSION_L3_VXLAN] = { 843 .next = MLX5_FLOW_EXPAND_RSS_NEXT(MLX5_EXPANSION_IPV4, 844 MLX5_EXPANSION_IPV6), 845 .type = RTE_FLOW_ITEM_TYPE_VXLAN, 846 }, 847 [MLX5_EXPANSION_VXLAN_GPE] = { 848 .next = MLX5_FLOW_EXPAND_RSS_NEXT(MLX5_EXPANSION_ETH, 849 MLX5_EXPANSION_IPV4, 850 MLX5_EXPANSION_IPV6), 851 .type = RTE_FLOW_ITEM_TYPE_VXLAN_GPE, 852 }, 853 [MLX5_EXPANSION_GRE] = { 854 .next = MLX5_FLOW_EXPAND_RSS_NEXT(MLX5_EXPANSION_ETH, 855 MLX5_EXPANSION_IPV4, 856 MLX5_EXPANSION_IPV6, 857 MLX5_EXPANSION_GRE_KEY, 858 MLX5_EXPANSION_MPLS), 859 .type = RTE_FLOW_ITEM_TYPE_GRE, 860 }, 861 [MLX5_EXPANSION_GRE_KEY] = { 862 .next = MLX5_FLOW_EXPAND_RSS_NEXT(MLX5_EXPANSION_IPV4, 863 MLX5_EXPANSION_IPV6, 864 MLX5_EXPANSION_MPLS), 865 .type = RTE_FLOW_ITEM_TYPE_GRE_KEY, 866 .node_flags = MLX5_EXPANSION_NODE_OPTIONAL, 867 }, 868 [MLX5_EXPANSION_NVGRE] = { 869 .next = MLX5_FLOW_EXPAND_RSS_NEXT(MLX5_EXPANSION_ETH), 870 .type = RTE_FLOW_ITEM_TYPE_NVGRE, 871 }, 872 [MLX5_EXPANSION_MPLS] = { 873 .next = MLX5_FLOW_EXPAND_RSS_NEXT(MLX5_EXPANSION_IPV4, 874 MLX5_EXPANSION_IPV6, 875 MLX5_EXPANSION_ETH), 876 .type = RTE_FLOW_ITEM_TYPE_MPLS, 877 .node_flags = MLX5_EXPANSION_NODE_OPTIONAL, 878 }, 879 [MLX5_EXPANSION_ETH] = { 880 .next = MLX5_FLOW_EXPAND_RSS_NEXT(MLX5_EXPANSION_VLAN), 881 .type = RTE_FLOW_ITEM_TYPE_ETH, 882 }, 883 [MLX5_EXPANSION_VLAN] = { 884 .next = MLX5_FLOW_EXPAND_RSS_NEXT(MLX5_EXPANSION_IPV4, 885 MLX5_EXPANSION_IPV6), 886 .type = RTE_FLOW_ITEM_TYPE_VLAN, 887 .node_flags = MLX5_EXPANSION_NODE_EXPLICIT, 888 }, 889 [MLX5_EXPANSION_IPV4] = { 890 .next = MLX5_FLOW_EXPAND_RSS_NEXT(MLX5_EXPANSION_IPV4_UDP, 891 MLX5_EXPANSION_IPV4_TCP, 892 MLX5_EXPANSION_IPV4_ESP, 893 MLX5_EXPANSION_IPV4_ICMP), 894 .type = RTE_FLOW_ITEM_TYPE_IPV4, 895 .rss_types = RTE_ETH_RSS_IPV4 | RTE_ETH_RSS_FRAG_IPV4 | 896 RTE_ETH_RSS_NONFRAG_IPV4_OTHER, 897 }, 898 [MLX5_EXPANSION_IPV4_UDP] = { 899 .type = RTE_FLOW_ITEM_TYPE_UDP, 900 .rss_types = RTE_ETH_RSS_NONFRAG_IPV4_UDP, 901 }, 902 [MLX5_EXPANSION_IPV4_TCP] = { 903 .type = RTE_FLOW_ITEM_TYPE_TCP, 904 .rss_types = RTE_ETH_RSS_NONFRAG_IPV4_TCP, 905 }, 906 [MLX5_EXPANSION_IPV4_ESP] = { 907 .type = RTE_FLOW_ITEM_TYPE_ESP, 908 .rss_types = RTE_ETH_RSS_ESP, 909 }, 910 [MLX5_EXPANSION_IPV4_ICMP] = { 911 .type = RTE_FLOW_ITEM_TYPE_ICMP, 912 }, 913 [MLX5_EXPANSION_IPV6] = { 914 .next = MLX5_FLOW_EXPAND_RSS_NEXT(MLX5_EXPANSION_IPV6_UDP, 915 MLX5_EXPANSION_IPV6_TCP, 916 MLX5_EXPANSION_IPV6_ESP, 917 MLX5_EXPANSION_IPV6_ICMP6, 918 MLX5_EXPANSION_IPV6_FRAG_EXT), 919 .type = RTE_FLOW_ITEM_TYPE_IPV6, 920 .rss_types = RTE_ETH_RSS_IPV6 | RTE_ETH_RSS_FRAG_IPV6 | 921 RTE_ETH_RSS_NONFRAG_IPV6_OTHER, 922 }, 923 [MLX5_EXPANSION_IPV6_UDP] = { 924 .type = RTE_FLOW_ITEM_TYPE_UDP, 925 .rss_types = RTE_ETH_RSS_NONFRAG_IPV6_UDP, 926 }, 927 [MLX5_EXPANSION_IPV6_TCP] = { 928 .type = RTE_FLOW_ITEM_TYPE_TCP, 929 .rss_types = RTE_ETH_RSS_NONFRAG_IPV6_TCP, 930 }, 931 [MLX5_EXPANSION_IPV6_ESP] = { 932 .type = RTE_FLOW_ITEM_TYPE_ESP, 933 .rss_types = RTE_ETH_RSS_ESP, 934 }, 935 [MLX5_EXPANSION_IPV6_FRAG_EXT] = { 936 .type = RTE_FLOW_ITEM_TYPE_IPV6_FRAG_EXT, 937 }, 938 [MLX5_EXPANSION_IPV6_ICMP6] = { 939 .type = RTE_FLOW_ITEM_TYPE_ICMP6, 940 }, 941 [MLX5_EXPANSION_GTP] = { 942 .next = MLX5_FLOW_EXPAND_RSS_NEXT(MLX5_EXPANSION_IPV4, 943 MLX5_EXPANSION_IPV6), 944 .type = RTE_FLOW_ITEM_TYPE_GTP, 945 }, 946 [MLX5_EXPANSION_GENEVE] = { 947 .next = MLX5_FLOW_EXPAND_RSS_NEXT(MLX5_EXPANSION_ETH, 948 MLX5_EXPANSION_IPV4, 949 MLX5_EXPANSION_IPV6), 950 .type = RTE_FLOW_ITEM_TYPE_GENEVE, 951 }, 952 }; 953 954 static struct rte_flow_action_handle * 955 mlx5_action_handle_create(struct rte_eth_dev *dev, 956 const struct rte_flow_indir_action_conf *conf, 957 const struct rte_flow_action *action, 958 struct rte_flow_error *error); 959 static int mlx5_action_handle_destroy 960 (struct rte_eth_dev *dev, 961 struct rte_flow_action_handle *handle, 962 struct rte_flow_error *error); 963 static int mlx5_action_handle_update 964 (struct rte_eth_dev *dev, 965 struct rte_flow_action_handle *handle, 966 const void *update, 967 struct rte_flow_error *error); 968 static int mlx5_action_handle_query 969 (struct rte_eth_dev *dev, 970 const struct rte_flow_action_handle *handle, 971 void *data, 972 struct rte_flow_error *error); 973 static int 974 mlx5_flow_tunnel_decap_set(struct rte_eth_dev *dev, 975 struct rte_flow_tunnel *app_tunnel, 976 struct rte_flow_action **actions, 977 uint32_t *num_of_actions, 978 struct rte_flow_error *error); 979 static int 980 mlx5_flow_tunnel_match(struct rte_eth_dev *dev, 981 struct rte_flow_tunnel *app_tunnel, 982 struct rte_flow_item **items, 983 uint32_t *num_of_items, 984 struct rte_flow_error *error); 985 static int 986 mlx5_flow_tunnel_item_release(struct rte_eth_dev *dev, 987 struct rte_flow_item *pmd_items, 988 uint32_t num_items, struct rte_flow_error *err); 989 static int 990 mlx5_flow_tunnel_action_release(struct rte_eth_dev *dev, 991 struct rte_flow_action *pmd_actions, 992 uint32_t num_actions, 993 struct rte_flow_error *err); 994 static int 995 mlx5_flow_tunnel_get_restore_info(struct rte_eth_dev *dev, 996 struct rte_mbuf *m, 997 struct rte_flow_restore_info *info, 998 struct rte_flow_error *err); 999 static struct rte_flow_item_flex_handle * 1000 mlx5_flow_flex_item_create(struct rte_eth_dev *dev, 1001 const struct rte_flow_item_flex_conf *conf, 1002 struct rte_flow_error *error); 1003 static int 1004 mlx5_flow_flex_item_release(struct rte_eth_dev *dev, 1005 const struct rte_flow_item_flex_handle *handle, 1006 struct rte_flow_error *error); 1007 static int 1008 mlx5_flow_info_get(struct rte_eth_dev *dev, 1009 struct rte_flow_port_info *port_info, 1010 struct rte_flow_queue_info *queue_info, 1011 struct rte_flow_error *error); 1012 static int 1013 mlx5_flow_port_configure(struct rte_eth_dev *dev, 1014 const struct rte_flow_port_attr *port_attr, 1015 uint16_t nb_queue, 1016 const struct rte_flow_queue_attr *queue_attr[], 1017 struct rte_flow_error *err); 1018 1019 static struct rte_flow_pattern_template * 1020 mlx5_flow_pattern_template_create(struct rte_eth_dev *dev, 1021 const struct rte_flow_pattern_template_attr *attr, 1022 const struct rte_flow_item items[], 1023 struct rte_flow_error *error); 1024 1025 static int 1026 mlx5_flow_pattern_template_destroy(struct rte_eth_dev *dev, 1027 struct rte_flow_pattern_template *template, 1028 struct rte_flow_error *error); 1029 static struct rte_flow_actions_template * 1030 mlx5_flow_actions_template_create(struct rte_eth_dev *dev, 1031 const struct rte_flow_actions_template_attr *attr, 1032 const struct rte_flow_action actions[], 1033 const struct rte_flow_action masks[], 1034 struct rte_flow_error *error); 1035 static int 1036 mlx5_flow_actions_template_destroy(struct rte_eth_dev *dev, 1037 struct rte_flow_actions_template *template, 1038 struct rte_flow_error *error); 1039 1040 static struct rte_flow_template_table * 1041 mlx5_flow_table_create(struct rte_eth_dev *dev, 1042 const struct rte_flow_template_table_attr *attr, 1043 struct rte_flow_pattern_template *item_templates[], 1044 uint8_t nb_item_templates, 1045 struct rte_flow_actions_template *action_templates[], 1046 uint8_t nb_action_templates, 1047 struct rte_flow_error *error); 1048 static int 1049 mlx5_flow_table_destroy(struct rte_eth_dev *dev, 1050 struct rte_flow_template_table *table, 1051 struct rte_flow_error *error); 1052 static int 1053 mlx5_flow_group_set_miss_actions(struct rte_eth_dev *dev, 1054 uint32_t group_id, 1055 const struct rte_flow_group_attr *attr, 1056 const struct rte_flow_action actions[], 1057 struct rte_flow_error *error); 1058 1059 static int 1060 mlx5_action_handle_query_update(struct rte_eth_dev *dev, 1061 struct rte_flow_action_handle *handle, 1062 const void *update, void *query, 1063 enum rte_flow_query_update_mode qu_mode, 1064 struct rte_flow_error *error); 1065 1066 static struct rte_flow_action_list_handle * 1067 mlx5_action_list_handle_create(struct rte_eth_dev *dev, 1068 const struct rte_flow_indir_action_conf *conf, 1069 const struct rte_flow_action *actions, 1070 struct rte_flow_error *error); 1071 1072 static int 1073 mlx5_action_list_handle_destroy(struct rte_eth_dev *dev, 1074 struct rte_flow_action_list_handle *handle, 1075 struct rte_flow_error *error); 1076 1077 static int 1078 mlx5_flow_action_list_handle_query_update(struct rte_eth_dev *dev, 1079 const 1080 struct rte_flow_action_list_handle *handle, 1081 const void **update, void **query, 1082 enum rte_flow_query_update_mode mode, 1083 struct rte_flow_error *error); 1084 1085 static int 1086 mlx5_flow_calc_table_hash(struct rte_eth_dev *dev, 1087 const struct rte_flow_template_table *table, 1088 const struct rte_flow_item pattern[], 1089 uint8_t pattern_template_index, 1090 uint32_t *hash, struct rte_flow_error *error); 1091 static int 1092 mlx5_flow_calc_encap_hash(struct rte_eth_dev *dev, 1093 const struct rte_flow_item pattern[], 1094 enum rte_flow_encap_hash_field dest_field, 1095 uint8_t *hash, 1096 struct rte_flow_error *error); 1097 1098 static const struct rte_flow_ops mlx5_flow_ops = { 1099 .validate = mlx5_flow_validate, 1100 .create = mlx5_flow_create, 1101 .destroy = mlx5_flow_destroy, 1102 .flush = mlx5_flow_flush, 1103 .isolate = mlx5_flow_isolate, 1104 .query = mlx5_flow_query, 1105 .dev_dump = mlx5_flow_dev_dump, 1106 .get_q_aged_flows = mlx5_flow_get_q_aged_flows, 1107 .get_aged_flows = mlx5_flow_get_aged_flows, 1108 .action_handle_create = mlx5_action_handle_create, 1109 .action_handle_destroy = mlx5_action_handle_destroy, 1110 .action_handle_update = mlx5_action_handle_update, 1111 .action_handle_query = mlx5_action_handle_query, 1112 .action_handle_query_update = mlx5_action_handle_query_update, 1113 .action_list_handle_create = mlx5_action_list_handle_create, 1114 .action_list_handle_destroy = mlx5_action_list_handle_destroy, 1115 .tunnel_decap_set = mlx5_flow_tunnel_decap_set, 1116 .tunnel_match = mlx5_flow_tunnel_match, 1117 .tunnel_action_decap_release = mlx5_flow_tunnel_action_release, 1118 .tunnel_item_release = mlx5_flow_tunnel_item_release, 1119 .get_restore_info = mlx5_flow_tunnel_get_restore_info, 1120 .flex_item_create = mlx5_flow_flex_item_create, 1121 .flex_item_release = mlx5_flow_flex_item_release, 1122 .info_get = mlx5_flow_info_get, 1123 .pick_transfer_proxy = mlx5_flow_pick_transfer_proxy, 1124 .configure = mlx5_flow_port_configure, 1125 .pattern_template_create = mlx5_flow_pattern_template_create, 1126 .pattern_template_destroy = mlx5_flow_pattern_template_destroy, 1127 .actions_template_create = mlx5_flow_actions_template_create, 1128 .actions_template_destroy = mlx5_flow_actions_template_destroy, 1129 .template_table_create = mlx5_flow_table_create, 1130 .template_table_destroy = mlx5_flow_table_destroy, 1131 .group_set_miss_actions = mlx5_flow_group_set_miss_actions, 1132 .action_list_handle_query_update = 1133 mlx5_flow_action_list_handle_query_update, 1134 .flow_calc_table_hash = mlx5_flow_calc_table_hash, 1135 .flow_calc_encap_hash = mlx5_flow_calc_encap_hash, 1136 }; 1137 1138 /* Tunnel information. */ 1139 struct mlx5_flow_tunnel_info { 1140 uint64_t tunnel; /**< Tunnel bit (see MLX5_FLOW_*). */ 1141 uint32_t ptype; /**< Tunnel Ptype (see RTE_PTYPE_*). */ 1142 }; 1143 1144 static struct mlx5_flow_tunnel_info tunnels_info[] = { 1145 { 1146 .tunnel = MLX5_FLOW_LAYER_VXLAN, 1147 .ptype = RTE_PTYPE_TUNNEL_VXLAN | RTE_PTYPE_L4_UDP, 1148 }, 1149 { 1150 .tunnel = MLX5_FLOW_LAYER_GENEVE, 1151 .ptype = RTE_PTYPE_TUNNEL_GENEVE | RTE_PTYPE_L4_UDP, 1152 }, 1153 { 1154 .tunnel = MLX5_FLOW_LAYER_VXLAN_GPE, 1155 .ptype = RTE_PTYPE_TUNNEL_VXLAN_GPE | RTE_PTYPE_L4_UDP, 1156 }, 1157 { 1158 .tunnel = MLX5_FLOW_LAYER_GRE, 1159 .ptype = RTE_PTYPE_TUNNEL_GRE, 1160 }, 1161 { 1162 .tunnel = MLX5_FLOW_LAYER_MPLS | MLX5_FLOW_LAYER_OUTER_L4_UDP, 1163 .ptype = RTE_PTYPE_TUNNEL_MPLS_IN_UDP | RTE_PTYPE_L4_UDP, 1164 }, 1165 { 1166 .tunnel = MLX5_FLOW_LAYER_MPLS, 1167 .ptype = RTE_PTYPE_TUNNEL_MPLS_IN_GRE, 1168 }, 1169 { 1170 .tunnel = MLX5_FLOW_LAYER_NVGRE, 1171 .ptype = RTE_PTYPE_TUNNEL_NVGRE, 1172 }, 1173 { 1174 .tunnel = MLX5_FLOW_LAYER_IPIP, 1175 .ptype = RTE_PTYPE_TUNNEL_IP, 1176 }, 1177 { 1178 .tunnel = MLX5_FLOW_LAYER_IPV6_ENCAP, 1179 .ptype = RTE_PTYPE_TUNNEL_IP, 1180 }, 1181 { 1182 .tunnel = MLX5_FLOW_LAYER_GTP, 1183 .ptype = RTE_PTYPE_TUNNEL_GTPU, 1184 }, 1185 }; 1186 1187 1188 1189 /** 1190 * Translate tag ID to register. 1191 * 1192 * @param[in] dev 1193 * Pointer to the Ethernet device structure. 1194 * @param[in] feature 1195 * The feature that request the register. 1196 * @param[in] id 1197 * The request register ID. 1198 * @param[out] error 1199 * Error description in case of any. 1200 * 1201 * @return 1202 * The request register on success, a negative errno 1203 * value otherwise and rte_errno is set. 1204 */ 1205 int 1206 mlx5_flow_get_reg_id(struct rte_eth_dev *dev, 1207 enum mlx5_feature_name feature, 1208 uint32_t id, 1209 struct rte_flow_error *error) 1210 { 1211 struct mlx5_priv *priv = dev->data->dev_private; 1212 struct mlx5_sh_config *config = &priv->sh->config; 1213 struct mlx5_dev_registers *reg = &priv->sh->registers; 1214 enum modify_reg start_reg; 1215 bool skip_mtr_reg = false; 1216 1217 switch (feature) { 1218 case MLX5_HAIRPIN_RX: 1219 return REG_B; 1220 case MLX5_HAIRPIN_TX: 1221 return REG_A; 1222 case MLX5_METADATA_RX: 1223 switch (config->dv_xmeta_en) { 1224 case MLX5_XMETA_MODE_LEGACY: 1225 return REG_B; 1226 case MLX5_XMETA_MODE_META16: 1227 return REG_C_0; 1228 case MLX5_XMETA_MODE_META32: 1229 return REG_C_1; 1230 case MLX5_XMETA_MODE_META32_HWS: 1231 return REG_C_1; 1232 } 1233 break; 1234 case MLX5_METADATA_TX: 1235 if (config->dv_flow_en == 2 && config->dv_xmeta_en == MLX5_XMETA_MODE_META32_HWS) { 1236 return REG_C_1; 1237 } else { 1238 return REG_A; 1239 } 1240 case MLX5_METADATA_FDB: 1241 switch (config->dv_xmeta_en) { 1242 case MLX5_XMETA_MODE_LEGACY: 1243 return REG_NON; 1244 case MLX5_XMETA_MODE_META16: 1245 return REG_C_0; 1246 case MLX5_XMETA_MODE_META32: 1247 return REG_C_1; 1248 case MLX5_XMETA_MODE_META32_HWS: 1249 return REG_C_1; 1250 } 1251 break; 1252 case MLX5_FLOW_MARK: 1253 switch (config->dv_xmeta_en) { 1254 case MLX5_XMETA_MODE_LEGACY: 1255 case MLX5_XMETA_MODE_META32_HWS: 1256 return REG_NON; 1257 case MLX5_XMETA_MODE_META16: 1258 return REG_C_1; 1259 case MLX5_XMETA_MODE_META32: 1260 return REG_C_0; 1261 } 1262 break; 1263 case MLX5_MTR_ID: 1264 /* 1265 * If meter color and meter id share one register, flow match 1266 * should use the meter color register for match. 1267 */ 1268 if (priv->mtr_reg_share) 1269 return reg->aso_reg; 1270 else 1271 return reg->aso_reg != REG_C_2 ? REG_C_2 : 1272 REG_C_3; 1273 case MLX5_MTR_COLOR: 1274 case MLX5_ASO_FLOW_HIT: 1275 case MLX5_ASO_CONNTRACK: 1276 case MLX5_SAMPLE_ID: 1277 /* All features use the same REG_C. */ 1278 MLX5_ASSERT(reg->aso_reg != REG_NON); 1279 return reg->aso_reg; 1280 case MLX5_COPY_MARK: 1281 /* 1282 * Metadata COPY_MARK register using is in meter suffix sub 1283 * flow while with meter. It's safe to share the same register. 1284 */ 1285 return reg->aso_reg != REG_C_2 ? REG_C_2 : REG_C_3; 1286 case MLX5_APP_TAG: 1287 /* 1288 * If meter is enable, it will engage the register for color 1289 * match and flow match. If meter color match is not using the 1290 * REG_C_2, need to skip the REG_C_x be used by meter color 1291 * match. 1292 * If meter is disable, free to use all available registers. 1293 */ 1294 start_reg = reg->aso_reg != REG_C_2 ? REG_C_2 : 1295 (priv->mtr_reg_share ? REG_C_3 : REG_C_4); 1296 skip_mtr_reg = !!(priv->mtr_en && start_reg == REG_C_2); 1297 if (id > (uint32_t)(REG_C_7 - start_reg)) 1298 return rte_flow_error_set(error, EINVAL, 1299 RTE_FLOW_ERROR_TYPE_ITEM, 1300 NULL, "invalid tag id"); 1301 if (priv->sh->flow_mreg_c[id + start_reg - REG_C_0] == REG_NON) 1302 return rte_flow_error_set(error, ENOTSUP, 1303 RTE_FLOW_ERROR_TYPE_ITEM, 1304 NULL, "unsupported tag id"); 1305 /* 1306 * This case means meter is using the REG_C_x great than 2. 1307 * Take care not to conflict with meter color REG_C_x. 1308 * If the available index REG_C_y >= REG_C_x, skip the 1309 * color register. 1310 */ 1311 if (skip_mtr_reg && priv->sh->flow_mreg_c 1312 [id + start_reg - REG_C_0] >= reg->aso_reg) { 1313 if (id >= (uint32_t)(REG_C_7 - start_reg)) 1314 return rte_flow_error_set(error, EINVAL, 1315 RTE_FLOW_ERROR_TYPE_ITEM, 1316 NULL, "invalid tag id"); 1317 if (priv->sh->flow_mreg_c 1318 [id + 1 + start_reg - REG_C_0] != REG_NON) 1319 return priv->sh->flow_mreg_c 1320 [id + 1 + start_reg - REG_C_0]; 1321 return rte_flow_error_set(error, ENOTSUP, 1322 RTE_FLOW_ERROR_TYPE_ITEM, 1323 NULL, "unsupported tag id"); 1324 } 1325 return priv->sh->flow_mreg_c[id + start_reg - REG_C_0]; 1326 } 1327 MLX5_ASSERT(false); 1328 return rte_flow_error_set(error, EINVAL, 1329 RTE_FLOW_ERROR_TYPE_UNSPECIFIED, 1330 NULL, "invalid feature name"); 1331 } 1332 1333 /** 1334 * Check extensive flow metadata register support. 1335 * 1336 * @param dev 1337 * Pointer to rte_eth_dev structure. 1338 * 1339 * @return 1340 * True if device supports extensive flow metadata register, otherwise false. 1341 */ 1342 bool 1343 mlx5_flow_ext_mreg_supported(struct rte_eth_dev *dev) 1344 { 1345 struct mlx5_priv *priv = dev->data->dev_private; 1346 1347 /* 1348 * Having available reg_c can be regarded inclusively as supporting 1349 * extensive flow metadata register, which could mean, 1350 * - metadata register copy action by modify header. 1351 * - 16 modify header actions is supported. 1352 * - reg_c's are preserved across different domain (FDB and NIC) on 1353 * packet loopback by flow lookup miss. 1354 */ 1355 return priv->sh->flow_mreg_c[2] != REG_NON; 1356 } 1357 1358 /** 1359 * Get the lowest priority. 1360 * 1361 * @param[in] dev 1362 * Pointer to the Ethernet device structure. 1363 * @param[in] attributes 1364 * Pointer to device flow rule attributes. 1365 * 1366 * @return 1367 * The value of lowest priority of flow. 1368 */ 1369 uint32_t 1370 mlx5_get_lowest_priority(struct rte_eth_dev *dev, 1371 const struct rte_flow_attr *attr) 1372 { 1373 struct mlx5_priv *priv = dev->data->dev_private; 1374 1375 if (!attr->group && !(attr->transfer && priv->fdb_def_rule)) 1376 return priv->sh->flow_max_priority - 2; 1377 return MLX5_NON_ROOT_FLOW_MAX_PRIO - 1; 1378 } 1379 1380 /** 1381 * Calculate matcher priority of the flow. 1382 * 1383 * @param[in] dev 1384 * Pointer to the Ethernet device structure. 1385 * @param[in] attr 1386 * Pointer to device flow rule attributes. 1387 * @param[in] subpriority 1388 * The priority based on the items. 1389 * @param[in] external 1390 * Flow is user flow. 1391 * @return 1392 * The matcher priority of the flow. 1393 */ 1394 uint16_t 1395 mlx5_get_matcher_priority(struct rte_eth_dev *dev, 1396 const struct rte_flow_attr *attr, 1397 uint32_t subpriority, bool external) 1398 { 1399 uint16_t priority = (uint16_t)attr->priority; 1400 struct mlx5_priv *priv = dev->data->dev_private; 1401 1402 /* NIC root rules */ 1403 if (!attr->group && !attr->transfer) { 1404 if (attr->priority == MLX5_FLOW_LOWEST_PRIO_INDICATOR) 1405 priority = priv->sh->flow_max_priority - 1; 1406 return mlx5_os_flow_adjust_priority(dev, priority, subpriority); 1407 /* FDB root rules */ 1408 } else if (attr->transfer && (!external || !priv->fdb_def_rule) && 1409 attr->group == 0 && 1410 attr->priority == MLX5_FLOW_LOWEST_PRIO_INDICATOR) { 1411 return (priv->sh->flow_max_priority - 1) * 3; 1412 } 1413 if (attr->priority == MLX5_FLOW_LOWEST_PRIO_INDICATOR) 1414 priority = MLX5_NON_ROOT_FLOW_MAX_PRIO; 1415 return priority * 3 + subpriority; 1416 } 1417 1418 /** 1419 * Verify the @p item specifications (spec, last, mask) are compatible with the 1420 * NIC capabilities. 1421 * 1422 * @param[in] item 1423 * Item specification. 1424 * @param[in] mask 1425 * @p item->mask or flow default bit-masks. 1426 * @param[in] nic_mask 1427 * Bit-masks covering supported fields by the NIC to compare with user mask. 1428 * @param[in] size 1429 * Bit-masks size in bytes. 1430 * @param[in] range_accepted 1431 * True if range of values is accepted for specific fields, false otherwise. 1432 * @param[out] error 1433 * Pointer to error structure. 1434 * 1435 * @return 1436 * 0 on success, a negative errno value otherwise and rte_errno is set. 1437 */ 1438 int 1439 mlx5_flow_item_acceptable(const struct rte_flow_item *item, 1440 const uint8_t *mask, 1441 const uint8_t *nic_mask, 1442 unsigned int size, 1443 bool range_accepted, 1444 struct rte_flow_error *error) 1445 { 1446 unsigned int i; 1447 1448 MLX5_ASSERT(nic_mask); 1449 for (i = 0; i < size; ++i) 1450 if ((nic_mask[i] | mask[i]) != nic_mask[i]) 1451 return rte_flow_error_set(error, ENOTSUP, 1452 RTE_FLOW_ERROR_TYPE_ITEM, 1453 item, 1454 "mask enables non supported" 1455 " bits"); 1456 if (!item->spec && (item->mask || item->last)) 1457 return rte_flow_error_set(error, EINVAL, 1458 RTE_FLOW_ERROR_TYPE_ITEM, item, 1459 "mask/last without a spec is not" 1460 " supported"); 1461 if (item->spec && item->last && !range_accepted) { 1462 uint8_t spec[size]; 1463 uint8_t last[size]; 1464 unsigned int i; 1465 int ret; 1466 1467 for (i = 0; i < size; ++i) { 1468 spec[i] = ((const uint8_t *)item->spec)[i] & mask[i]; 1469 last[i] = ((const uint8_t *)item->last)[i] & mask[i]; 1470 } 1471 ret = memcmp(spec, last, size); 1472 if (ret != 0) 1473 return rte_flow_error_set(error, EINVAL, 1474 RTE_FLOW_ERROR_TYPE_ITEM, 1475 item, 1476 "range is not valid"); 1477 } 1478 return 0; 1479 } 1480 1481 /** 1482 * Adjust the hash fields according to the @p flow information. 1483 * 1484 * @param[in] dev_flow. 1485 * Pointer to the mlx5_flow. 1486 * @param[in] tunnel 1487 * 1 when the hash field is for a tunnel item. 1488 * @param[in] layer_types 1489 * RTE_ETH_RSS_* types. 1490 * @param[in] hash_fields 1491 * Item hash fields. 1492 * 1493 * @return 1494 * The hash fields that should be used. 1495 */ 1496 uint64_t 1497 mlx5_flow_hashfields_adjust(struct mlx5_flow_rss_desc *rss_desc, 1498 int tunnel __rte_unused, uint64_t layer_types, 1499 uint64_t hash_fields) 1500 { 1501 #ifdef HAVE_IBV_DEVICE_TUNNEL_SUPPORT 1502 int rss_request_inner = rss_desc->level >= 2; 1503 1504 /* Check RSS hash level for tunnel. */ 1505 if (tunnel && rss_request_inner) 1506 hash_fields |= IBV_RX_HASH_INNER; 1507 else if (tunnel || rss_request_inner) 1508 return 0; 1509 #endif 1510 /* Check if requested layer matches RSS hash fields. */ 1511 if (!(rss_desc->types & layer_types)) 1512 return 0; 1513 return hash_fields; 1514 } 1515 1516 /** 1517 * Lookup and set the ptype in the data Rx part. A single Ptype can be used, 1518 * if several tunnel rules are used on this queue, the tunnel ptype will be 1519 * cleared. 1520 * 1521 * @param rxq_ctrl 1522 * Rx queue to update. 1523 */ 1524 static void 1525 flow_rxq_tunnel_ptype_update(struct mlx5_rxq_ctrl *rxq_ctrl) 1526 { 1527 unsigned int i; 1528 uint32_t tunnel_ptype = 0; 1529 1530 /* Look up for the ptype to use. */ 1531 for (i = 0; i != MLX5_FLOW_TUNNEL; ++i) { 1532 if (!rxq_ctrl->flow_tunnels_n[i]) 1533 continue; 1534 if (!tunnel_ptype) { 1535 tunnel_ptype = tunnels_info[i].ptype; 1536 } else { 1537 tunnel_ptype = 0; 1538 break; 1539 } 1540 } 1541 rxq_ctrl->rxq.tunnel = tunnel_ptype; 1542 } 1543 1544 /** 1545 * Set the Rx queue flags (Mark/Flag and Tunnel Ptypes) according to the device 1546 * flow. 1547 * 1548 * @param[in] dev 1549 * Pointer to the Ethernet device structure. 1550 * @param[in] dev_handle 1551 * Pointer to device flow handle structure. 1552 */ 1553 void 1554 flow_drv_rxq_flags_set(struct rte_eth_dev *dev, 1555 struct mlx5_flow_handle *dev_handle) 1556 { 1557 struct mlx5_priv *priv = dev->data->dev_private; 1558 const int tunnel = !!(dev_handle->layers & MLX5_FLOW_LAYER_TUNNEL); 1559 struct mlx5_ind_table_obj *ind_tbl = NULL; 1560 unsigned int i; 1561 1562 if (dev_handle->fate_action == MLX5_FLOW_FATE_QUEUE) { 1563 struct mlx5_hrxq *hrxq; 1564 1565 hrxq = mlx5_ipool_get(priv->sh->ipool[MLX5_IPOOL_HRXQ], 1566 dev_handle->rix_hrxq); 1567 if (hrxq) 1568 ind_tbl = hrxq->ind_table; 1569 } else if (dev_handle->fate_action == MLX5_FLOW_FATE_SHARED_RSS) { 1570 struct mlx5_shared_action_rss *shared_rss; 1571 1572 shared_rss = mlx5_ipool_get 1573 (priv->sh->ipool[MLX5_IPOOL_RSS_SHARED_ACTIONS], 1574 dev_handle->rix_srss); 1575 if (shared_rss) 1576 ind_tbl = shared_rss->ind_tbl; 1577 } 1578 if (!ind_tbl) 1579 return; 1580 for (i = 0; i != ind_tbl->queues_n; ++i) { 1581 int idx = ind_tbl->queues[i]; 1582 struct mlx5_rxq_ctrl *rxq_ctrl; 1583 1584 if (mlx5_is_external_rxq(dev, idx)) 1585 continue; 1586 rxq_ctrl = mlx5_rxq_ctrl_get(dev, idx); 1587 MLX5_ASSERT(rxq_ctrl != NULL); 1588 if (rxq_ctrl == NULL) 1589 continue; 1590 /* 1591 * To support metadata register copy on Tx loopback, 1592 * this must be always enabled (metadata may arive 1593 * from other port - not from local flows only. 1594 */ 1595 if (tunnel) { 1596 unsigned int j; 1597 1598 /* Increase the counter matching the flow. */ 1599 for (j = 0; j != MLX5_FLOW_TUNNEL; ++j) { 1600 if ((tunnels_info[j].tunnel & 1601 dev_handle->layers) == 1602 tunnels_info[j].tunnel) { 1603 rxq_ctrl->flow_tunnels_n[j]++; 1604 break; 1605 } 1606 } 1607 flow_rxq_tunnel_ptype_update(rxq_ctrl); 1608 } 1609 } 1610 } 1611 1612 static void 1613 flow_rxq_mark_flag_set(struct rte_eth_dev *dev) 1614 { 1615 struct mlx5_priv *priv = dev->data->dev_private; 1616 struct mlx5_rxq_ctrl *rxq_ctrl; 1617 uint16_t port_id; 1618 1619 if (priv->sh->shared_mark_enabled) 1620 return; 1621 if (priv->master || priv->representor) { 1622 MLX5_ETH_FOREACH_DEV(port_id, dev->device) { 1623 struct mlx5_priv *opriv = 1624 rte_eth_devices[port_id].data->dev_private; 1625 1626 if (!opriv || 1627 opriv->sh != priv->sh || 1628 opriv->domain_id != priv->domain_id || 1629 opriv->mark_enabled) 1630 continue; 1631 LIST_FOREACH(rxq_ctrl, &opriv->rxqsctrl, next) { 1632 rxq_ctrl->rxq.mark = 1; 1633 } 1634 opriv->mark_enabled = 1; 1635 } 1636 } else { 1637 LIST_FOREACH(rxq_ctrl, &priv->rxqsctrl, next) { 1638 rxq_ctrl->rxq.mark = 1; 1639 } 1640 priv->mark_enabled = 1; 1641 } 1642 priv->sh->shared_mark_enabled = 1; 1643 } 1644 1645 /** 1646 * Set the Rx queue flags (Mark/Flag and Tunnel Ptypes) for a flow 1647 * 1648 * @param[in] dev 1649 * Pointer to the Ethernet device structure. 1650 * @param[in] flow 1651 * Pointer to flow structure. 1652 */ 1653 static void 1654 flow_rxq_flags_set(struct rte_eth_dev *dev, struct rte_flow *flow) 1655 { 1656 struct mlx5_priv *priv = dev->data->dev_private; 1657 uint32_t handle_idx; 1658 struct mlx5_flow_handle *dev_handle; 1659 struct mlx5_flow_workspace *wks = mlx5_flow_get_thread_workspace(); 1660 1661 MLX5_ASSERT(wks); 1662 if (wks->mark) 1663 flow_rxq_mark_flag_set(dev); 1664 SILIST_FOREACH(priv->sh->ipool[MLX5_IPOOL_MLX5_FLOW], flow->dev_handles, 1665 handle_idx, dev_handle, next) 1666 flow_drv_rxq_flags_set(dev, dev_handle); 1667 } 1668 1669 /** 1670 * Clear the Rx queue flags (Mark/Flag and Tunnel Ptype) associated with the 1671 * device flow if no other flow uses it with the same kind of request. 1672 * 1673 * @param dev 1674 * Pointer to Ethernet device. 1675 * @param[in] dev_handle 1676 * Pointer to the device flow handle structure. 1677 */ 1678 static void 1679 flow_drv_rxq_flags_trim(struct rte_eth_dev *dev, 1680 struct mlx5_flow_handle *dev_handle) 1681 { 1682 struct mlx5_priv *priv = dev->data->dev_private; 1683 const int tunnel = !!(dev_handle->layers & MLX5_FLOW_LAYER_TUNNEL); 1684 struct mlx5_ind_table_obj *ind_tbl = NULL; 1685 unsigned int i; 1686 1687 if (dev_handle->fate_action == MLX5_FLOW_FATE_QUEUE) { 1688 struct mlx5_hrxq *hrxq; 1689 1690 hrxq = mlx5_ipool_get(priv->sh->ipool[MLX5_IPOOL_HRXQ], 1691 dev_handle->rix_hrxq); 1692 if (hrxq) 1693 ind_tbl = hrxq->ind_table; 1694 } else if (dev_handle->fate_action == MLX5_FLOW_FATE_SHARED_RSS) { 1695 struct mlx5_shared_action_rss *shared_rss; 1696 1697 shared_rss = mlx5_ipool_get 1698 (priv->sh->ipool[MLX5_IPOOL_RSS_SHARED_ACTIONS], 1699 dev_handle->rix_srss); 1700 if (shared_rss) 1701 ind_tbl = shared_rss->ind_tbl; 1702 } 1703 if (!ind_tbl) 1704 return; 1705 MLX5_ASSERT(dev->data->dev_started); 1706 for (i = 0; i != ind_tbl->queues_n; ++i) { 1707 int idx = ind_tbl->queues[i]; 1708 struct mlx5_rxq_ctrl *rxq_ctrl; 1709 1710 if (mlx5_is_external_rxq(dev, idx)) 1711 continue; 1712 rxq_ctrl = mlx5_rxq_ctrl_get(dev, idx); 1713 MLX5_ASSERT(rxq_ctrl != NULL); 1714 if (rxq_ctrl == NULL) 1715 continue; 1716 if (tunnel) { 1717 unsigned int j; 1718 1719 /* Decrease the counter matching the flow. */ 1720 for (j = 0; j != MLX5_FLOW_TUNNEL; ++j) { 1721 if ((tunnels_info[j].tunnel & 1722 dev_handle->layers) == 1723 tunnels_info[j].tunnel) { 1724 rxq_ctrl->flow_tunnels_n[j]--; 1725 break; 1726 } 1727 } 1728 flow_rxq_tunnel_ptype_update(rxq_ctrl); 1729 } 1730 } 1731 } 1732 1733 /** 1734 * Clear the Rx queue flags (Mark/Flag and Tunnel Ptype) associated with the 1735 * @p flow if no other flow uses it with the same kind of request. 1736 * 1737 * @param dev 1738 * Pointer to Ethernet device. 1739 * @param[in] flow 1740 * Pointer to the flow. 1741 */ 1742 static void 1743 flow_rxq_flags_trim(struct rte_eth_dev *dev, struct rte_flow *flow) 1744 { 1745 struct mlx5_priv *priv = dev->data->dev_private; 1746 uint32_t handle_idx; 1747 struct mlx5_flow_handle *dev_handle; 1748 1749 SILIST_FOREACH(priv->sh->ipool[MLX5_IPOOL_MLX5_FLOW], flow->dev_handles, 1750 handle_idx, dev_handle, next) 1751 flow_drv_rxq_flags_trim(dev, dev_handle); 1752 } 1753 1754 /** 1755 * Clear the Mark/Flag and Tunnel ptype information in all Rx queues. 1756 * 1757 * @param dev 1758 * Pointer to Ethernet device. 1759 */ 1760 static void 1761 flow_rxq_flags_clear(struct rte_eth_dev *dev) 1762 { 1763 struct mlx5_priv *priv = dev->data->dev_private; 1764 unsigned int i; 1765 1766 for (i = 0; i != priv->rxqs_n; ++i) { 1767 struct mlx5_rxq_priv *rxq = mlx5_rxq_get(dev, i); 1768 unsigned int j; 1769 1770 if (rxq == NULL || rxq->ctrl == NULL) 1771 continue; 1772 rxq->ctrl->rxq.mark = 0; 1773 for (j = 0; j != MLX5_FLOW_TUNNEL; ++j) 1774 rxq->ctrl->flow_tunnels_n[j] = 0; 1775 rxq->ctrl->rxq.tunnel = 0; 1776 } 1777 priv->mark_enabled = 0; 1778 priv->sh->shared_mark_enabled = 0; 1779 } 1780 1781 static uint64_t mlx5_restore_info_dynflag; 1782 1783 int 1784 mlx5_flow_rx_metadata_negotiate(struct rte_eth_dev *dev, uint64_t *features) 1785 { 1786 struct mlx5_priv *priv = dev->data->dev_private; 1787 uint64_t supported = 0; 1788 1789 if (!is_tunnel_offload_active(dev)) { 1790 supported |= RTE_ETH_RX_METADATA_USER_FLAG; 1791 supported |= RTE_ETH_RX_METADATA_USER_MARK; 1792 if ((*features & RTE_ETH_RX_METADATA_TUNNEL_ID) != 0) { 1793 DRV_LOG(DEBUG, 1794 "tunnel offload was not activated, consider setting dv_xmeta_en=%d", 1795 MLX5_XMETA_MODE_MISS_INFO); 1796 } 1797 } else { 1798 supported |= RTE_ETH_RX_METADATA_TUNNEL_ID; 1799 if ((*features & RTE_ETH_RX_METADATA_TUNNEL_ID) != 0 && 1800 mlx5_restore_info_dynflag == 0) 1801 mlx5_restore_info_dynflag = rte_flow_restore_info_dynflag(); 1802 } 1803 1804 if (((*features & supported) & RTE_ETH_RX_METADATA_TUNNEL_ID) != 0) 1805 priv->tunnel_enabled = 1; 1806 else 1807 priv->tunnel_enabled = 0; 1808 1809 *features &= supported; 1810 return 0; 1811 } 1812 1813 /** 1814 * Set the Rx queue dynamic metadata (mask and offset) for a flow 1815 * 1816 * @param[in] dev 1817 * Pointer to the Ethernet device structure. 1818 */ 1819 void 1820 mlx5_flow_rxq_dynf_set(struct rte_eth_dev *dev) 1821 { 1822 struct mlx5_priv *priv = dev->data->dev_private; 1823 uint64_t mark_flag = RTE_MBUF_F_RX_FDIR_ID; 1824 unsigned int i; 1825 1826 if (priv->tunnel_enabled) 1827 mark_flag |= mlx5_restore_info_dynflag; 1828 1829 for (i = 0; i != priv->rxqs_n; ++i) { 1830 struct mlx5_rxq_priv *rxq = mlx5_rxq_get(dev, i); 1831 struct mlx5_rxq_data *data; 1832 1833 if (rxq == NULL || rxq->ctrl == NULL) 1834 continue; 1835 data = &rxq->ctrl->rxq; 1836 if (!rte_flow_dynf_metadata_avail()) { 1837 data->dynf_meta = 0; 1838 data->flow_meta_mask = 0; 1839 data->flow_meta_offset = -1; 1840 data->flow_meta_port_mask = 0; 1841 } else { 1842 data->dynf_meta = 1; 1843 data->flow_meta_mask = rte_flow_dynf_metadata_mask; 1844 data->flow_meta_offset = rte_flow_dynf_metadata_offs; 1845 data->flow_meta_port_mask = priv->sh->dv_meta_mask; 1846 } 1847 data->mark_flag = mark_flag; 1848 } 1849 } 1850 1851 /* 1852 * return a pointer to the desired action in the list of actions. 1853 * 1854 * @param[in] actions 1855 * The list of actions to search the action in. 1856 * @param[in] action 1857 * The action to find. 1858 * 1859 * @return 1860 * Pointer to the action in the list, if found. NULL otherwise. 1861 */ 1862 const struct rte_flow_action * 1863 mlx5_flow_find_action(const struct rte_flow_action *actions, 1864 enum rte_flow_action_type action) 1865 { 1866 if (actions == NULL) 1867 return NULL; 1868 for (; actions->type != RTE_FLOW_ACTION_TYPE_END; actions++) 1869 if (actions->type == action) 1870 return actions; 1871 return NULL; 1872 } 1873 1874 /* 1875 * Validate the flag action. 1876 * 1877 * @param[in] action_flags 1878 * Bit-fields that holds the actions detected until now. 1879 * @param[in] attr 1880 * Attributes of flow that includes this action. 1881 * @param[out] error 1882 * Pointer to error structure. 1883 * 1884 * @return 1885 * 0 on success, a negative errno value otherwise and rte_errno is set. 1886 */ 1887 int 1888 mlx5_flow_validate_action_flag(uint64_t action_flags, 1889 const struct rte_flow_attr *attr, 1890 struct rte_flow_error *error) 1891 { 1892 if (action_flags & MLX5_FLOW_ACTION_MARK) 1893 return rte_flow_error_set(error, EINVAL, 1894 RTE_FLOW_ERROR_TYPE_ACTION, NULL, 1895 "can't mark and flag in same flow"); 1896 if (action_flags & MLX5_FLOW_ACTION_FLAG) 1897 return rte_flow_error_set(error, EINVAL, 1898 RTE_FLOW_ERROR_TYPE_ACTION, NULL, 1899 "can't have 2 flag" 1900 " actions in same flow"); 1901 if (attr->egress) 1902 return rte_flow_error_set(error, ENOTSUP, 1903 RTE_FLOW_ERROR_TYPE_ATTR_EGRESS, NULL, 1904 "flag action not supported for " 1905 "egress"); 1906 return 0; 1907 } 1908 1909 /* 1910 * Validate the mark action. 1911 * 1912 * @param[in] action 1913 * Pointer to the queue action. 1914 * @param[in] action_flags 1915 * Bit-fields that holds the actions detected until now. 1916 * @param[in] attr 1917 * Attributes of flow that includes this action. 1918 * @param[out] error 1919 * Pointer to error structure. 1920 * 1921 * @return 1922 * 0 on success, a negative errno value otherwise and rte_errno is set. 1923 */ 1924 int 1925 mlx5_flow_validate_action_mark(const struct rte_flow_action *action, 1926 uint64_t action_flags, 1927 const struct rte_flow_attr *attr, 1928 struct rte_flow_error *error) 1929 { 1930 const struct rte_flow_action_mark *mark = action->conf; 1931 1932 if (!mark) 1933 return rte_flow_error_set(error, EINVAL, 1934 RTE_FLOW_ERROR_TYPE_ACTION, 1935 action, 1936 "configuration cannot be null"); 1937 if (mark->id >= MLX5_FLOW_MARK_MAX) 1938 return rte_flow_error_set(error, EINVAL, 1939 RTE_FLOW_ERROR_TYPE_ACTION_CONF, 1940 &mark->id, 1941 "mark id must in 0 <= id < " 1942 RTE_STR(MLX5_FLOW_MARK_MAX)); 1943 if (action_flags & MLX5_FLOW_ACTION_FLAG) 1944 return rte_flow_error_set(error, EINVAL, 1945 RTE_FLOW_ERROR_TYPE_ACTION, NULL, 1946 "can't flag and mark in same flow"); 1947 if (action_flags & MLX5_FLOW_ACTION_MARK) 1948 return rte_flow_error_set(error, EINVAL, 1949 RTE_FLOW_ERROR_TYPE_ACTION, NULL, 1950 "can't have 2 mark actions in same" 1951 " flow"); 1952 if (attr->egress) 1953 return rte_flow_error_set(error, ENOTSUP, 1954 RTE_FLOW_ERROR_TYPE_ATTR_EGRESS, NULL, 1955 "mark action not supported for " 1956 "egress"); 1957 return 0; 1958 } 1959 1960 /* 1961 * Validate the drop action. 1962 * 1963 * @param[in] dev 1964 * Pointer to the Ethernet device structure. 1965 * @param[in] is_root 1966 * True if flow is validated for root table. False otherwise. 1967 * @param[in] attr 1968 * Attributes of flow that includes this action. 1969 * @param[out] error 1970 * Pointer to error structure. 1971 * 1972 * @return 1973 * 0 on success, a negative errno value otherwise and rte_errno is set. 1974 */ 1975 int 1976 mlx5_flow_validate_action_drop(struct rte_eth_dev *dev, 1977 bool is_root, 1978 const struct rte_flow_attr *attr, 1979 struct rte_flow_error *error) 1980 { 1981 struct mlx5_priv *priv = dev->data->dev_private; 1982 1983 if (priv->sh->config.dv_flow_en == 0 && attr->egress) 1984 return rte_flow_error_set(error, ENOTSUP, 1985 RTE_FLOW_ERROR_TYPE_ATTR_EGRESS, NULL, 1986 "drop action not supported for " 1987 "egress"); 1988 if (priv->sh->config.dv_flow_en == 1 && is_root && (attr->egress || attr->transfer) && 1989 !priv->sh->dr_root_drop_action_en) { 1990 return rte_flow_error_set(error, ENOTSUP, 1991 RTE_FLOW_ERROR_TYPE_ATTR, NULL, 1992 "drop action not supported for " 1993 "egress and transfer on group 0"); 1994 } 1995 return 0; 1996 } 1997 1998 /* 1999 * Validate the queue action. 2000 * 2001 * @param[in] action 2002 * Pointer to the queue action. 2003 * @param[in] action_flags 2004 * Bit-fields that holds the actions detected until now. 2005 * @param[in] dev 2006 * Pointer to the Ethernet device structure. 2007 * @param[in] attr 2008 * Attributes of flow that includes this action. 2009 * @param[out] error 2010 * Pointer to error structure. 2011 * 2012 * @return 2013 * 0 on success, a negative errno value otherwise and rte_errno is set. 2014 */ 2015 int 2016 mlx5_flow_validate_action_queue(const struct rte_flow_action *action, 2017 uint64_t action_flags, 2018 struct rte_eth_dev *dev, 2019 const struct rte_flow_attr *attr, 2020 struct rte_flow_error *error) 2021 { 2022 struct mlx5_priv *priv = dev->data->dev_private; 2023 const struct rte_flow_action_queue *queue = action->conf; 2024 2025 if (action_flags & MLX5_FLOW_FATE_ACTIONS) 2026 return rte_flow_error_set(error, EINVAL, 2027 RTE_FLOW_ERROR_TYPE_ACTION, NULL, 2028 "can't have 2 fate actions in" 2029 " same flow"); 2030 if (attr->egress) 2031 return rte_flow_error_set(error, ENOTSUP, 2032 RTE_FLOW_ERROR_TYPE_ATTR_EGRESS, NULL, 2033 "queue action not supported for egress."); 2034 if (mlx5_is_external_rxq(dev, queue->index)) 2035 return 0; 2036 if (!priv->rxqs_n) 2037 return rte_flow_error_set(error, EINVAL, 2038 RTE_FLOW_ERROR_TYPE_ACTION_CONF, 2039 NULL, "No Rx queues configured"); 2040 if (queue->index >= priv->rxqs_n) 2041 return rte_flow_error_set(error, EINVAL, 2042 RTE_FLOW_ERROR_TYPE_ACTION_CONF, 2043 &queue->index, 2044 "queue index out of range"); 2045 if (mlx5_rxq_get(dev, queue->index) == NULL) 2046 return rte_flow_error_set(error, EINVAL, 2047 RTE_FLOW_ERROR_TYPE_ACTION_CONF, 2048 &queue->index, 2049 "queue is not configured"); 2050 return 0; 2051 } 2052 2053 /** 2054 * Validate queue numbers for device RSS. 2055 * 2056 * @param[in] dev 2057 * Configured device. 2058 * @param[in] queues 2059 * Array of queue numbers. 2060 * @param[in] queues_n 2061 * Size of the @p queues array. 2062 * @param[out] error 2063 * On error, filled with a textual error description. 2064 * @param[out] queue_idx 2065 * On error, filled with an offending queue index in @p queues array. 2066 * 2067 * @return 2068 * 0 on success, a negative errno code on error. 2069 */ 2070 static int 2071 mlx5_validate_rss_queues(struct rte_eth_dev *dev, 2072 const uint16_t *queues, uint32_t queues_n, 2073 const char **error, uint32_t *queue_idx) 2074 { 2075 const struct mlx5_priv *priv = dev->data->dev_private; 2076 bool is_hairpin = false; 2077 bool is_ext_rss = false; 2078 uint32_t i; 2079 2080 for (i = 0; i != queues_n; ++i) { 2081 struct mlx5_rxq_ctrl *rxq_ctrl; 2082 2083 if (mlx5_is_external_rxq(dev, queues[0])) { 2084 is_ext_rss = true; 2085 continue; 2086 } 2087 if (is_ext_rss) { 2088 *error = "Combining external and regular RSS queues is not supported"; 2089 *queue_idx = i; 2090 return -ENOTSUP; 2091 } 2092 if (queues[i] >= priv->rxqs_n) { 2093 *error = "queue index out of range"; 2094 *queue_idx = i; 2095 return -EINVAL; 2096 } 2097 rxq_ctrl = mlx5_rxq_ctrl_get(dev, queues[i]); 2098 if (rxq_ctrl == NULL) { 2099 *error = "queue is not configured"; 2100 *queue_idx = i; 2101 return -EINVAL; 2102 } 2103 if (i == 0 && rxq_ctrl->is_hairpin) 2104 is_hairpin = true; 2105 if (is_hairpin != rxq_ctrl->is_hairpin) { 2106 *error = "combining hairpin and regular RSS queues is not supported"; 2107 *queue_idx = i; 2108 return -ENOTSUP; 2109 } 2110 } 2111 return 0; 2112 } 2113 2114 /* 2115 * Validate the rss action. 2116 * 2117 * @param[in] dev 2118 * Pointer to the Ethernet device structure. 2119 * @param[in] action 2120 * Pointer to the queue action. 2121 * @param[out] error 2122 * Pointer to error structure. 2123 * 2124 * @return 2125 * 0 on success, a negative errno value otherwise and rte_errno is set. 2126 */ 2127 int 2128 mlx5_validate_action_rss(struct rte_eth_dev *dev, 2129 const struct rte_flow_action *action, 2130 struct rte_flow_error *error) 2131 { 2132 struct mlx5_priv *priv = dev->data->dev_private; 2133 const struct rte_flow_action_rss *rss = action->conf; 2134 int ret; 2135 const char *message; 2136 uint32_t queue_idx; 2137 2138 if (rss->func == RTE_ETH_HASH_FUNCTION_SYMMETRIC_TOEPLITZ) { 2139 DRV_LOG(WARNING, "port %u symmetric RSS supported with SORT", 2140 dev->data->port_id); 2141 } else if (rss->func != RTE_ETH_HASH_FUNCTION_DEFAULT && 2142 rss->func != RTE_ETH_HASH_FUNCTION_TOEPLITZ) 2143 return rte_flow_error_set(error, ENOTSUP, 2144 RTE_FLOW_ERROR_TYPE_ACTION_CONF, 2145 &rss->func, 2146 "RSS hash function not supported"); 2147 #ifdef HAVE_IBV_DEVICE_TUNNEL_SUPPORT 2148 if (rss->level > 2) 2149 #else 2150 if (rss->level > 1) 2151 #endif 2152 return rte_flow_error_set(error, ENOTSUP, 2153 RTE_FLOW_ERROR_TYPE_ACTION_CONF, 2154 &rss->level, 2155 "tunnel RSS is not supported"); 2156 /* allow RSS key_len 0 in case of NULL (default) RSS key. */ 2157 if (rss->key_len == 0 && rss->key != NULL) 2158 return rte_flow_error_set(error, ENOTSUP, 2159 RTE_FLOW_ERROR_TYPE_ACTION_CONF, 2160 &rss->key_len, 2161 "RSS hash key length 0"); 2162 if (rss->key_len > 0 && rss->key_len < MLX5_RSS_HASH_KEY_LEN) 2163 return rte_flow_error_set(error, ENOTSUP, 2164 RTE_FLOW_ERROR_TYPE_ACTION_CONF, 2165 &rss->key_len, 2166 "RSS hash key too small"); 2167 if (rss->key_len > MLX5_RSS_HASH_KEY_LEN) 2168 return rte_flow_error_set(error, ENOTSUP, 2169 RTE_FLOW_ERROR_TYPE_ACTION_CONF, 2170 &rss->key_len, 2171 "RSS hash key too large"); 2172 if (rss->queue_num > priv->sh->dev_cap.ind_table_max_size) 2173 return rte_flow_error_set(error, ENOTSUP, 2174 RTE_FLOW_ERROR_TYPE_ACTION_CONF, 2175 &rss->queue_num, 2176 "number of queues too large"); 2177 if (rss->types & MLX5_RSS_HF_MASK) 2178 return rte_flow_error_set(error, ENOTSUP, 2179 RTE_FLOW_ERROR_TYPE_ACTION_CONF, 2180 &rss->types, 2181 "some RSS protocols are not" 2182 " supported"); 2183 if ((rss->types & (RTE_ETH_RSS_L3_SRC_ONLY | RTE_ETH_RSS_L3_DST_ONLY)) && 2184 !(rss->types & RTE_ETH_RSS_IP)) 2185 return rte_flow_error_set(error, EINVAL, 2186 RTE_FLOW_ERROR_TYPE_ACTION_CONF, NULL, 2187 "L3 partial RSS requested but L3 RSS" 2188 " type not specified"); 2189 if ((rss->types & (RTE_ETH_RSS_L4_SRC_ONLY | RTE_ETH_RSS_L4_DST_ONLY)) && 2190 !(rss->types & (RTE_ETH_RSS_UDP | RTE_ETH_RSS_TCP))) 2191 return rte_flow_error_set(error, EINVAL, 2192 RTE_FLOW_ERROR_TYPE_ACTION_CONF, NULL, 2193 "L4 partial RSS requested but L4 RSS" 2194 " type not specified"); 2195 if (!priv->rxqs_n && priv->ext_rxqs == NULL) 2196 return rte_flow_error_set(error, EINVAL, 2197 RTE_FLOW_ERROR_TYPE_ACTION_CONF, 2198 NULL, "No Rx queues configured"); 2199 if (!rss->queue_num) 2200 return rte_flow_error_set(error, EINVAL, 2201 RTE_FLOW_ERROR_TYPE_ACTION_CONF, 2202 NULL, "No queues configured"); 2203 ret = mlx5_validate_rss_queues(dev, rss->queue, rss->queue_num, 2204 &message, &queue_idx); 2205 if (ret != 0) { 2206 return rte_flow_error_set(error, -ret, 2207 RTE_FLOW_ERROR_TYPE_ACTION_CONF, 2208 &rss->queue[queue_idx], message); 2209 } 2210 return 0; 2211 } 2212 2213 /* 2214 * Validate the rss action. 2215 * 2216 * @param[in] action 2217 * Pointer to the queue action. 2218 * @param[in] action_flags 2219 * Bit-fields that holds the actions detected until now. 2220 * @param[in] dev 2221 * Pointer to the Ethernet device structure. 2222 * @param[in] attr 2223 * Attributes of flow that includes this action. 2224 * @param[in] item_flags 2225 * Items that were detected. 2226 * @param[out] error 2227 * Pointer to error structure. 2228 * 2229 * @return 2230 * 0 on success, a negative errno value otherwise and rte_errno is set. 2231 */ 2232 int 2233 mlx5_flow_validate_action_rss(const struct rte_flow_action *action, 2234 uint64_t action_flags, 2235 struct rte_eth_dev *dev, 2236 const struct rte_flow_attr *attr, 2237 uint64_t item_flags, 2238 struct rte_flow_error *error) 2239 { 2240 const struct rte_flow_action_rss *rss = action->conf; 2241 int tunnel = !!(item_flags & MLX5_FLOW_LAYER_TUNNEL); 2242 int ret; 2243 2244 if (action_flags & MLX5_FLOW_FATE_ACTIONS) 2245 return rte_flow_error_set(error, EINVAL, 2246 RTE_FLOW_ERROR_TYPE_ACTION, NULL, 2247 "can't have 2 fate actions" 2248 " in same flow"); 2249 ret = mlx5_validate_action_rss(dev, action, error); 2250 if (ret) 2251 return ret; 2252 if (attr->egress) 2253 return rte_flow_error_set(error, ENOTSUP, 2254 RTE_FLOW_ERROR_TYPE_ATTR_EGRESS, NULL, 2255 "rss action not supported for " 2256 "egress"); 2257 if (rss->level > 1 && !tunnel) 2258 return rte_flow_error_set(error, EINVAL, 2259 RTE_FLOW_ERROR_TYPE_ACTION_CONF, NULL, 2260 "inner RSS is not supported for " 2261 "non-tunnel flows"); 2262 if ((item_flags & MLX5_FLOW_LAYER_ECPRI) && 2263 !(item_flags & MLX5_FLOW_LAYER_INNER_L4_UDP)) { 2264 return rte_flow_error_set(error, EINVAL, 2265 RTE_FLOW_ERROR_TYPE_ACTION_CONF, NULL, 2266 "RSS on eCPRI is not supported now"); 2267 } 2268 if ((item_flags & MLX5_FLOW_LAYER_MPLS) && 2269 !(item_flags & 2270 (MLX5_FLOW_LAYER_INNER_L2 | MLX5_FLOW_LAYER_INNER_L3)) && 2271 rss->level > 1) 2272 return rte_flow_error_set(error, EINVAL, 2273 RTE_FLOW_ERROR_TYPE_ITEM, NULL, 2274 "MPLS inner RSS needs to specify inner L2/L3 items after MPLS in pattern"); 2275 return 0; 2276 } 2277 2278 /* 2279 * Validate the default miss action. 2280 * 2281 * @param[in] action_flags 2282 * Bit-fields that holds the actions detected until now. 2283 * @param[out] error 2284 * Pointer to error structure. 2285 * 2286 * @return 2287 * 0 on success, a negative errno value otherwise and rte_errno is set. 2288 */ 2289 int 2290 mlx5_flow_validate_action_default_miss(uint64_t action_flags, 2291 const struct rte_flow_attr *attr, 2292 struct rte_flow_error *error) 2293 { 2294 if (action_flags & MLX5_FLOW_FATE_ACTIONS) 2295 return rte_flow_error_set(error, EINVAL, 2296 RTE_FLOW_ERROR_TYPE_ACTION, NULL, 2297 "can't have 2 fate actions in" 2298 " same flow"); 2299 if (attr->egress) 2300 return rte_flow_error_set(error, ENOTSUP, 2301 RTE_FLOW_ERROR_TYPE_ATTR_EGRESS, NULL, 2302 "default miss action not supported " 2303 "for egress"); 2304 if (attr->group) 2305 return rte_flow_error_set(error, ENOTSUP, 2306 RTE_FLOW_ERROR_TYPE_ATTR_GROUP, NULL, 2307 "only group 0 is supported"); 2308 if (attr->transfer) 2309 return rte_flow_error_set(error, ENOTSUP, 2310 RTE_FLOW_ERROR_TYPE_ATTR_TRANSFER, 2311 NULL, "transfer is not supported"); 2312 return 0; 2313 } 2314 2315 /* 2316 * Validate the count action. 2317 * 2318 * @param[in] dev 2319 * Pointer to the Ethernet device structure. 2320 * @param[in] attr 2321 * Attributes of flow that includes this action. 2322 * @param[out] error 2323 * Pointer to error structure. 2324 * 2325 * @return 2326 * 0 on success, a negative errno value otherwise and rte_errno is set. 2327 */ 2328 int 2329 mlx5_flow_validate_action_count(struct rte_eth_dev *dev __rte_unused, 2330 const struct rte_flow_attr *attr, 2331 struct rte_flow_error *error) 2332 { 2333 if (attr->egress) 2334 return rte_flow_error_set(error, ENOTSUP, 2335 RTE_FLOW_ERROR_TYPE_ATTR_EGRESS, NULL, 2336 "count action not supported for " 2337 "egress"); 2338 return 0; 2339 } 2340 2341 /* 2342 * Validate the ASO CT action. 2343 * 2344 * @param[in] dev 2345 * Pointer to the Ethernet device structure. 2346 * @param[in] conntrack 2347 * Pointer to the CT action profile. 2348 * @param[out] error 2349 * Pointer to error structure. 2350 * 2351 * @return 2352 * 0 on success, a negative errno value otherwise and rte_errno is set. 2353 */ 2354 int 2355 mlx5_validate_action_ct(struct rte_eth_dev *dev, 2356 const struct rte_flow_action_conntrack *conntrack, 2357 struct rte_flow_error *error) 2358 { 2359 RTE_SET_USED(dev); 2360 2361 if (conntrack->state > RTE_FLOW_CONNTRACK_STATE_TIME_WAIT) 2362 return rte_flow_error_set(error, EINVAL, 2363 RTE_FLOW_ERROR_TYPE_ACTION, NULL, 2364 "Invalid CT state"); 2365 if (conntrack->last_index > RTE_FLOW_CONNTRACK_FLAG_RST) 2366 return rte_flow_error_set(error, EINVAL, 2367 RTE_FLOW_ERROR_TYPE_ACTION, NULL, 2368 "Invalid last TCP packet flag"); 2369 return 0; 2370 } 2371 2372 /** 2373 * Validate the level value for modify field action. 2374 * 2375 * @param[in] data 2376 * Pointer to the rte_flow_field_data structure either src or dst. 2377 * @param[out] error 2378 * Pointer to error structure. 2379 * 2380 * @return 2381 * 0 on success, a negative errno value otherwise and rte_errno is set. 2382 */ 2383 int 2384 flow_validate_modify_field_level(const struct rte_flow_field_data *data, 2385 struct rte_flow_error *error) 2386 { 2387 if (data->level == 0) 2388 return 0; 2389 if (data->field != RTE_FLOW_FIELD_TAG && 2390 data->field != (enum rte_flow_field_id)MLX5_RTE_FLOW_FIELD_META_REG) 2391 return rte_flow_error_set(error, ENOTSUP, 2392 RTE_FLOW_ERROR_TYPE_ACTION, NULL, 2393 "inner header fields modification is not supported"); 2394 if (data->tag_index != 0) 2395 return rte_flow_error_set(error, EINVAL, 2396 RTE_FLOW_ERROR_TYPE_ACTION, NULL, 2397 "tag array can be provided using 'level' or 'tag_index' fields, not both"); 2398 /* 2399 * The tag array for RTE_FLOW_FIELD_TAG type is provided using 2400 * 'tag_index' field. In old API, it was provided using 'level' field 2401 * and it is still supported for backwards compatibility. 2402 */ 2403 DRV_LOG(DEBUG, "tag array provided in 'level' field instead of 'tag_index' field."); 2404 return 0; 2405 } 2406 2407 /** 2408 * Validate ICMP6 item. 2409 * 2410 * @param[in] item 2411 * Item specification. 2412 * @param[in] item_flags 2413 * Bit-fields that holds the items detected until now. 2414 * @param[in] ext_vlan_sup 2415 * Whether extended VLAN features are supported or not. 2416 * @param[out] error 2417 * Pointer to error structure. 2418 * 2419 * @return 2420 * 0 on success, a negative errno value otherwise and rte_errno is set. 2421 */ 2422 int 2423 mlx5_flow_validate_item_icmp6(const struct rte_flow_item *item, 2424 uint64_t item_flags, 2425 uint8_t target_protocol, 2426 struct rte_flow_error *error) 2427 { 2428 const struct rte_flow_item_icmp6 *mask = item->mask; 2429 const int tunnel = !!(item_flags & MLX5_FLOW_LAYER_TUNNEL); 2430 const uint64_t l3m = tunnel ? MLX5_FLOW_LAYER_INNER_L3_IPV6 : 2431 MLX5_FLOW_LAYER_OUTER_L3_IPV6; 2432 const uint64_t l4m = tunnel ? MLX5_FLOW_LAYER_INNER_L4 : 2433 MLX5_FLOW_LAYER_OUTER_L4; 2434 int ret; 2435 2436 if (target_protocol != 0xFF && target_protocol != IPPROTO_ICMPV6) 2437 return rte_flow_error_set(error, EINVAL, 2438 RTE_FLOW_ERROR_TYPE_ITEM, item, 2439 "protocol filtering not compatible" 2440 " with ICMP6 layer"); 2441 if (!(item_flags & l3m)) 2442 return rte_flow_error_set(error, EINVAL, 2443 RTE_FLOW_ERROR_TYPE_ITEM, item, 2444 "IPv6 is mandatory to filter on" 2445 " ICMP6"); 2446 if (item_flags & l4m) 2447 return rte_flow_error_set(error, EINVAL, 2448 RTE_FLOW_ERROR_TYPE_ITEM, item, 2449 "multiple L4 layers not supported"); 2450 if (!mask) 2451 mask = &rte_flow_item_icmp6_mask; 2452 ret = mlx5_flow_item_acceptable 2453 (item, (const uint8_t *)mask, 2454 (const uint8_t *)&rte_flow_item_icmp6_mask, 2455 sizeof(struct rte_flow_item_icmp6), 2456 MLX5_ITEM_RANGE_NOT_ACCEPTED, error); 2457 if (ret < 0) 2458 return ret; 2459 return 0; 2460 } 2461 2462 /** 2463 * Validate ICMP6 echo request/reply item. 2464 * 2465 * @param[in] item 2466 * Item specification. 2467 * @param[in] item_flags 2468 * Bit-fields that holds the items detected until now. 2469 * @param[in] ext_vlan_sup 2470 * Whether extended VLAN features are supported or not. 2471 * @param[out] error 2472 * Pointer to error structure. 2473 * 2474 * @return 2475 * 0 on success, a negative errno value otherwise and rte_errno is set. 2476 */ 2477 int 2478 mlx5_flow_validate_item_icmp6_echo(const struct rte_flow_item *item, 2479 uint64_t item_flags, 2480 uint8_t target_protocol, 2481 struct rte_flow_error *error) 2482 { 2483 const struct rte_flow_item_icmp6_echo *mask = item->mask; 2484 const struct rte_flow_item_icmp6_echo nic_mask = { 2485 .hdr.base.type = 0xff, 2486 .hdr.base.code = 0xff, 2487 .hdr.identifier = RTE_BE16(0xffff), 2488 .hdr.sequence = RTE_BE16(0xffff), 2489 }; 2490 const int tunnel = !!(item_flags & MLX5_FLOW_LAYER_TUNNEL); 2491 const uint64_t l3m = tunnel ? MLX5_FLOW_LAYER_INNER_L3_IPV6 : 2492 MLX5_FLOW_LAYER_OUTER_L3_IPV6; 2493 const uint64_t l4m = tunnel ? MLX5_FLOW_LAYER_INNER_L4 : 2494 MLX5_FLOW_LAYER_OUTER_L4; 2495 int ret; 2496 2497 if (target_protocol != 0xFF && target_protocol != IPPROTO_ICMPV6) 2498 return rte_flow_error_set(error, EINVAL, 2499 RTE_FLOW_ERROR_TYPE_ITEM, item, 2500 "protocol filtering not compatible" 2501 " with ICMP6 layer"); 2502 if (!(item_flags & l3m)) 2503 return rte_flow_error_set(error, EINVAL, 2504 RTE_FLOW_ERROR_TYPE_ITEM, item, 2505 "IPv6 is mandatory to filter on" 2506 " ICMP6"); 2507 if (item_flags & l4m) 2508 return rte_flow_error_set(error, EINVAL, 2509 RTE_FLOW_ERROR_TYPE_ITEM, item, 2510 "multiple L4 layers not supported"); 2511 if (!mask) 2512 mask = &nic_mask; 2513 ret = mlx5_flow_item_acceptable 2514 (item, (const uint8_t *)mask, 2515 (const uint8_t *)&nic_mask, 2516 sizeof(struct rte_flow_item_icmp6_echo), 2517 MLX5_ITEM_RANGE_NOT_ACCEPTED, error); 2518 if (ret < 0) 2519 return ret; 2520 return 0; 2521 } 2522 2523 /** 2524 * Validate ICMP item. 2525 * 2526 * @param[in] item 2527 * Item specification. 2528 * @param[in] item_flags 2529 * Bit-fields that holds the items detected until now. 2530 * @param[out] error 2531 * Pointer to error structure. 2532 * 2533 * @return 2534 * 0 on success, a negative errno value otherwise and rte_errno is set. 2535 */ 2536 int 2537 mlx5_flow_validate_item_icmp(const struct rte_flow_item *item, 2538 uint64_t item_flags, 2539 uint8_t target_protocol, 2540 struct rte_flow_error *error) 2541 { 2542 const struct rte_flow_item_icmp *mask = item->mask; 2543 const struct rte_flow_item_icmp nic_mask = { 2544 .hdr.icmp_type = 0xff, 2545 .hdr.icmp_code = 0xff, 2546 .hdr.icmp_ident = RTE_BE16(0xffff), 2547 .hdr.icmp_seq_nb = RTE_BE16(0xffff), 2548 }; 2549 const int tunnel = !!(item_flags & MLX5_FLOW_LAYER_TUNNEL); 2550 const uint64_t l3m = tunnel ? MLX5_FLOW_LAYER_INNER_L3_IPV4 : 2551 MLX5_FLOW_LAYER_OUTER_L3_IPV4; 2552 const uint64_t l4m = tunnel ? MLX5_FLOW_LAYER_INNER_L4 : 2553 MLX5_FLOW_LAYER_OUTER_L4; 2554 int ret; 2555 2556 if (target_protocol != 0xFF && target_protocol != IPPROTO_ICMP) 2557 return rte_flow_error_set(error, EINVAL, 2558 RTE_FLOW_ERROR_TYPE_ITEM, item, 2559 "protocol filtering not compatible" 2560 " with ICMP layer"); 2561 if (!(item_flags & l3m)) 2562 return rte_flow_error_set(error, EINVAL, 2563 RTE_FLOW_ERROR_TYPE_ITEM, item, 2564 "IPv4 is mandatory to filter" 2565 " on ICMP"); 2566 if (item_flags & l4m) 2567 return rte_flow_error_set(error, EINVAL, 2568 RTE_FLOW_ERROR_TYPE_ITEM, item, 2569 "multiple L4 layers not supported"); 2570 if (!mask) 2571 mask = &nic_mask; 2572 ret = mlx5_flow_item_acceptable 2573 (item, (const uint8_t *)mask, 2574 (const uint8_t *)&nic_mask, 2575 sizeof(struct rte_flow_item_icmp), 2576 MLX5_ITEM_RANGE_NOT_ACCEPTED, error); 2577 if (ret < 0) 2578 return ret; 2579 return 0; 2580 } 2581 2582 /** 2583 * Validate Ethernet item. 2584 * 2585 * @param[in] item 2586 * Item specification. 2587 * @param[in] item_flags 2588 * Bit-fields that holds the items detected until now. 2589 * @param[out] error 2590 * Pointer to error structure. 2591 * 2592 * @return 2593 * 0 on success, a negative errno value otherwise and rte_errno is set. 2594 */ 2595 int 2596 mlx5_flow_validate_item_eth(const struct rte_flow_item *item, 2597 uint64_t item_flags, bool ext_vlan_sup, 2598 struct rte_flow_error *error) 2599 { 2600 const struct rte_flow_item_eth *mask = item->mask; 2601 const struct rte_flow_item_eth nic_mask = { 2602 .hdr.dst_addr.addr_bytes = "\xff\xff\xff\xff\xff\xff", 2603 .hdr.src_addr.addr_bytes = "\xff\xff\xff\xff\xff\xff", 2604 .hdr.ether_type = RTE_BE16(0xffff), 2605 .has_vlan = ext_vlan_sup ? 1 : 0, 2606 }; 2607 int ret; 2608 int tunnel = !!(item_flags & MLX5_FLOW_LAYER_TUNNEL); 2609 const uint64_t ethm = tunnel ? MLX5_FLOW_LAYER_INNER_L2 : 2610 MLX5_FLOW_LAYER_OUTER_L2; 2611 2612 if (item_flags & ethm) 2613 return rte_flow_error_set(error, ENOTSUP, 2614 RTE_FLOW_ERROR_TYPE_ITEM, item, 2615 "multiple L2 layers not supported"); 2616 if ((!tunnel && (item_flags & MLX5_FLOW_LAYER_OUTER_L3)) || 2617 (tunnel && (item_flags & MLX5_FLOW_LAYER_INNER_L3))) 2618 return rte_flow_error_set(error, EINVAL, 2619 RTE_FLOW_ERROR_TYPE_ITEM, item, 2620 "L2 layer should not follow " 2621 "L3 layers"); 2622 if ((!tunnel && (item_flags & MLX5_FLOW_LAYER_OUTER_VLAN)) || 2623 (tunnel && (item_flags & MLX5_FLOW_LAYER_INNER_VLAN))) 2624 return rte_flow_error_set(error, EINVAL, 2625 RTE_FLOW_ERROR_TYPE_ITEM, item, 2626 "L2 layer should not follow VLAN"); 2627 if (item_flags & MLX5_FLOW_LAYER_GTP) 2628 return rte_flow_error_set(error, EINVAL, 2629 RTE_FLOW_ERROR_TYPE_ITEM, item, 2630 "L2 layer should not follow GTP"); 2631 if (!mask) 2632 mask = &rte_flow_item_eth_mask; 2633 ret = mlx5_flow_item_acceptable(item, (const uint8_t *)mask, 2634 (const uint8_t *)&nic_mask, 2635 sizeof(struct rte_flow_item_eth), 2636 MLX5_ITEM_RANGE_NOT_ACCEPTED, error); 2637 return ret; 2638 } 2639 2640 /** 2641 * Validate VLAN item. 2642 * 2643 * @param[in] item 2644 * Item specification. 2645 * @param[in] item_flags 2646 * Bit-fields that holds the items detected until now. 2647 * @param[in] dev 2648 * Ethernet device flow is being created on. 2649 * @param[out] error 2650 * Pointer to error structure. 2651 * 2652 * @return 2653 * 0 on success, a negative errno value otherwise and rte_errno is set. 2654 */ 2655 int 2656 mlx5_flow_validate_item_vlan(const struct rte_flow_item *item, 2657 uint64_t item_flags, 2658 struct rte_eth_dev *dev, 2659 struct rte_flow_error *error) 2660 { 2661 const struct rte_flow_item_vlan *spec = item->spec; 2662 const struct rte_flow_item_vlan *mask = item->mask; 2663 const struct rte_flow_item_vlan nic_mask = { 2664 .hdr.vlan_tci = RTE_BE16(UINT16_MAX), 2665 .hdr.eth_proto = RTE_BE16(UINT16_MAX), 2666 }; 2667 uint16_t vlan_tag = 0; 2668 const int tunnel = !!(item_flags & MLX5_FLOW_LAYER_TUNNEL); 2669 int ret; 2670 const uint64_t l34m = tunnel ? (MLX5_FLOW_LAYER_INNER_L3 | 2671 MLX5_FLOW_LAYER_INNER_L4) : 2672 (MLX5_FLOW_LAYER_OUTER_L3 | 2673 MLX5_FLOW_LAYER_OUTER_L4); 2674 const uint64_t vlanm = tunnel ? MLX5_FLOW_LAYER_INNER_VLAN : 2675 MLX5_FLOW_LAYER_OUTER_VLAN; 2676 2677 if (item_flags & vlanm) 2678 return rte_flow_error_set(error, EINVAL, 2679 RTE_FLOW_ERROR_TYPE_ITEM, item, 2680 "multiple VLAN layers not supported"); 2681 else if ((item_flags & l34m) != 0) 2682 return rte_flow_error_set(error, EINVAL, 2683 RTE_FLOW_ERROR_TYPE_ITEM, item, 2684 "VLAN cannot follow L3/L4 layer"); 2685 if (!mask) 2686 mask = &rte_flow_item_vlan_mask; 2687 ret = mlx5_flow_item_acceptable(item, (const uint8_t *)mask, 2688 (const uint8_t *)&nic_mask, 2689 sizeof(struct rte_flow_item_vlan), 2690 MLX5_ITEM_RANGE_NOT_ACCEPTED, error); 2691 if (ret) 2692 return ret; 2693 if (!tunnel && mask->hdr.vlan_tci != RTE_BE16(0x0fff)) { 2694 struct mlx5_priv *priv = dev->data->dev_private; 2695 2696 if (priv->vmwa_context) { 2697 /* 2698 * Non-NULL context means we have a virtual machine 2699 * and SR-IOV enabled, we have to create VLAN interface 2700 * to make hypervisor to setup E-Switch vport 2701 * context correctly. We avoid creating the multiple 2702 * VLAN interfaces, so we cannot support VLAN tag mask. 2703 */ 2704 return rte_flow_error_set(error, EINVAL, 2705 RTE_FLOW_ERROR_TYPE_ITEM, 2706 item, 2707 "VLAN tag mask is not" 2708 " supported in virtual" 2709 " environment"); 2710 } 2711 } 2712 if (spec) { 2713 vlan_tag = spec->hdr.vlan_tci; 2714 vlan_tag &= mask->hdr.vlan_tci; 2715 } 2716 /* 2717 * From verbs perspective an empty VLAN is equivalent 2718 * to a packet without VLAN layer. 2719 */ 2720 if (!vlan_tag) 2721 return rte_flow_error_set(error, EINVAL, 2722 RTE_FLOW_ERROR_TYPE_ITEM_SPEC, 2723 item->spec, 2724 "VLAN cannot be empty"); 2725 return 0; 2726 } 2727 2728 /** 2729 * Validate IPV4 item. 2730 * 2731 * @param[in] item 2732 * Item specification. 2733 * @param[in] item_flags 2734 * Bit-fields that holds the items detected until now. 2735 * @param[in] last_item 2736 * Previous validated item in the pattern items. 2737 * @param[in] ether_type 2738 * Type in the ethernet layer header (including dot1q). 2739 * @param[in] acc_mask 2740 * Acceptable mask, if NULL default internal default mask 2741 * will be used to check whether item fields are supported. 2742 * @param[in] range_accepted 2743 * True if range of values is accepted for specific fields, false otherwise. 2744 * @param[out] error 2745 * Pointer to error structure. 2746 * 2747 * @return 2748 * 0 on success, a negative errno value otherwise and rte_errno is set. 2749 */ 2750 int 2751 mlx5_flow_validate_item_ipv4(const struct rte_flow_item *item, 2752 uint64_t item_flags, 2753 uint64_t last_item, 2754 uint16_t ether_type, 2755 const struct rte_flow_item_ipv4 *acc_mask, 2756 bool range_accepted, 2757 struct rte_flow_error *error) 2758 { 2759 const struct rte_flow_item_ipv4 *mask = item->mask; 2760 const struct rte_flow_item_ipv4 *spec = item->spec; 2761 const struct rte_flow_item_ipv4 nic_mask = { 2762 .hdr = { 2763 .src_addr = RTE_BE32(0xffffffff), 2764 .dst_addr = RTE_BE32(0xffffffff), 2765 .type_of_service = 0xff, 2766 .next_proto_id = 0xff, 2767 }, 2768 }; 2769 const int tunnel = !!(item_flags & MLX5_FLOW_LAYER_TUNNEL); 2770 const uint64_t l3m = tunnel ? MLX5_FLOW_LAYER_INNER_L3 : 2771 MLX5_FLOW_LAYER_OUTER_L3; 2772 const uint64_t l4m = tunnel ? MLX5_FLOW_LAYER_INNER_L4 : 2773 MLX5_FLOW_LAYER_OUTER_L4; 2774 int ret; 2775 uint8_t next_proto = 0xFF; 2776 const uint64_t l2_vlan = (MLX5_FLOW_LAYER_L2 | 2777 MLX5_FLOW_LAYER_OUTER_VLAN | 2778 MLX5_FLOW_LAYER_INNER_VLAN); 2779 2780 if ((last_item & l2_vlan) && ether_type && 2781 ether_type != RTE_ETHER_TYPE_IPV4) 2782 return rte_flow_error_set(error, EINVAL, 2783 RTE_FLOW_ERROR_TYPE_ITEM, item, 2784 "IPv4 cannot follow L2/VLAN layer " 2785 "which ether type is not IPv4"); 2786 if (item_flags & MLX5_FLOW_LAYER_IPIP) { 2787 if (mask && spec) 2788 next_proto = mask->hdr.next_proto_id & 2789 spec->hdr.next_proto_id; 2790 if (next_proto == IPPROTO_IPIP || next_proto == IPPROTO_IPV6) 2791 return rte_flow_error_set(error, EINVAL, 2792 RTE_FLOW_ERROR_TYPE_ITEM, 2793 item, 2794 "multiple tunnel " 2795 "not supported"); 2796 } 2797 if (item_flags & MLX5_FLOW_LAYER_IPV6_ENCAP) 2798 return rte_flow_error_set(error, EINVAL, 2799 RTE_FLOW_ERROR_TYPE_ITEM, item, 2800 "wrong tunnel type - IPv6 specified " 2801 "but IPv4 item provided"); 2802 if (item_flags & l3m) 2803 return rte_flow_error_set(error, ENOTSUP, 2804 RTE_FLOW_ERROR_TYPE_ITEM, item, 2805 "multiple L3 layers not supported"); 2806 else if (item_flags & l4m) 2807 return rte_flow_error_set(error, EINVAL, 2808 RTE_FLOW_ERROR_TYPE_ITEM, item, 2809 "L3 cannot follow an L4 layer."); 2810 else if ((item_flags & MLX5_FLOW_LAYER_NVGRE) && 2811 !(item_flags & MLX5_FLOW_LAYER_INNER_L2)) 2812 return rte_flow_error_set(error, EINVAL, 2813 RTE_FLOW_ERROR_TYPE_ITEM, item, 2814 "L3 cannot follow an NVGRE layer."); 2815 if (!mask) 2816 mask = &rte_flow_item_ipv4_mask; 2817 else if (mask->hdr.next_proto_id != 0 && 2818 mask->hdr.next_proto_id != 0xff) 2819 return rte_flow_error_set(error, EINVAL, 2820 RTE_FLOW_ERROR_TYPE_ITEM_MASK, mask, 2821 "partial mask is not supported" 2822 " for protocol"); 2823 ret = mlx5_flow_item_acceptable(item, (const uint8_t *)mask, 2824 acc_mask ? (const uint8_t *)acc_mask 2825 : (const uint8_t *)&nic_mask, 2826 sizeof(struct rte_flow_item_ipv4), 2827 range_accepted, error); 2828 if (ret < 0) 2829 return ret; 2830 return 0; 2831 } 2832 2833 /** 2834 * Validate IPV6 item. 2835 * 2836 * @param[in] item 2837 * Item specification. 2838 * @param[in] item_flags 2839 * Bit-fields that holds the items detected until now. 2840 * @param[in] last_item 2841 * Previous validated item in the pattern items. 2842 * @param[in] ether_type 2843 * Type in the ethernet layer header (including dot1q). 2844 * @param[in] acc_mask 2845 * Acceptable mask, if NULL default internal default mask 2846 * will be used to check whether item fields are supported. 2847 * @param[out] error 2848 * Pointer to error structure. 2849 * 2850 * @return 2851 * 0 on success, a negative errno value otherwise and rte_errno is set. 2852 */ 2853 int 2854 mlx5_flow_validate_item_ipv6(const struct rte_flow_item *item, 2855 uint64_t item_flags, 2856 uint64_t last_item, 2857 uint16_t ether_type, 2858 const struct rte_flow_item_ipv6 *acc_mask, 2859 struct rte_flow_error *error) 2860 { 2861 const struct rte_flow_item_ipv6 *mask = item->mask; 2862 const struct rte_flow_item_ipv6 *spec = item->spec; 2863 const struct rte_flow_item_ipv6 nic_mask = { 2864 .hdr = { 2865 .src_addr = 2866 "\xff\xff\xff\xff\xff\xff\xff\xff" 2867 "\xff\xff\xff\xff\xff\xff\xff\xff", 2868 .dst_addr = 2869 "\xff\xff\xff\xff\xff\xff\xff\xff" 2870 "\xff\xff\xff\xff\xff\xff\xff\xff", 2871 .vtc_flow = RTE_BE32(0xffffffff), 2872 .proto = 0xff, 2873 }, 2874 }; 2875 const int tunnel = !!(item_flags & MLX5_FLOW_LAYER_TUNNEL); 2876 const uint64_t l3m = tunnel ? MLX5_FLOW_LAYER_INNER_L3 : 2877 MLX5_FLOW_LAYER_OUTER_L3; 2878 const uint64_t l4m = tunnel ? MLX5_FLOW_LAYER_INNER_L4 : 2879 MLX5_FLOW_LAYER_OUTER_L4; 2880 int ret; 2881 uint8_t next_proto = 0xFF; 2882 const uint64_t l2_vlan = (MLX5_FLOW_LAYER_L2 | 2883 MLX5_FLOW_LAYER_OUTER_VLAN | 2884 MLX5_FLOW_LAYER_INNER_VLAN); 2885 2886 if ((last_item & l2_vlan) && ether_type && 2887 ether_type != RTE_ETHER_TYPE_IPV6) 2888 return rte_flow_error_set(error, EINVAL, 2889 RTE_FLOW_ERROR_TYPE_ITEM, item, 2890 "IPv6 cannot follow L2/VLAN layer " 2891 "which ether type is not IPv6"); 2892 if (mask && mask->hdr.proto == UINT8_MAX && spec) 2893 next_proto = spec->hdr.proto; 2894 if (item_flags & MLX5_FLOW_LAYER_IPIP) { 2895 if (next_proto == IPPROTO_IPIP || next_proto == IPPROTO_IPV6) 2896 return rte_flow_error_set(error, EINVAL, 2897 RTE_FLOW_ERROR_TYPE_ITEM, 2898 item, 2899 "multiple tunnel " 2900 "not supported"); 2901 } 2902 if (next_proto == IPPROTO_HOPOPTS || 2903 next_proto == IPPROTO_ROUTING || 2904 next_proto == IPPROTO_FRAGMENT || 2905 next_proto == IPPROTO_ESP || 2906 next_proto == IPPROTO_AH || 2907 next_proto == IPPROTO_DSTOPTS) 2908 return rte_flow_error_set(error, EINVAL, 2909 RTE_FLOW_ERROR_TYPE_ITEM, item, 2910 "IPv6 proto (next header) should " 2911 "not be set as extension header"); 2912 if (item_flags & MLX5_FLOW_LAYER_IPIP) 2913 return rte_flow_error_set(error, EINVAL, 2914 RTE_FLOW_ERROR_TYPE_ITEM, item, 2915 "wrong tunnel type - IPv4 specified " 2916 "but IPv6 item provided"); 2917 if (item_flags & l3m) 2918 return rte_flow_error_set(error, ENOTSUP, 2919 RTE_FLOW_ERROR_TYPE_ITEM, item, 2920 "multiple L3 layers not supported"); 2921 else if (item_flags & l4m) 2922 return rte_flow_error_set(error, EINVAL, 2923 RTE_FLOW_ERROR_TYPE_ITEM, item, 2924 "L3 cannot follow an L4 layer."); 2925 else if ((item_flags & MLX5_FLOW_LAYER_NVGRE) && 2926 !(item_flags & MLX5_FLOW_LAYER_INNER_L2)) 2927 return rte_flow_error_set(error, EINVAL, 2928 RTE_FLOW_ERROR_TYPE_ITEM, item, 2929 "L3 cannot follow an NVGRE layer."); 2930 if (!mask) 2931 mask = &rte_flow_item_ipv6_mask; 2932 ret = mlx5_flow_item_acceptable(item, (const uint8_t *)mask, 2933 acc_mask ? (const uint8_t *)acc_mask 2934 : (const uint8_t *)&nic_mask, 2935 sizeof(struct rte_flow_item_ipv6), 2936 MLX5_ITEM_RANGE_NOT_ACCEPTED, error); 2937 if (ret < 0) 2938 return ret; 2939 return 0; 2940 } 2941 2942 /** 2943 * Validate UDP item. 2944 * 2945 * @param[in] item 2946 * Item specification. 2947 * @param[in] item_flags 2948 * Bit-fields that holds the items detected until now. 2949 * @param[in] target_protocol 2950 * The next protocol in the previous item. 2951 * @param[in] flow_mask 2952 * mlx5 flow-specific (DV, verbs, etc.) supported header fields mask. 2953 * @param[out] error 2954 * Pointer to error structure. 2955 * 2956 * @return 2957 * 0 on success, a negative errno value otherwise and rte_errno is set. 2958 */ 2959 int 2960 mlx5_flow_validate_item_udp(const struct rte_flow_item *item, 2961 uint64_t item_flags, 2962 uint8_t target_protocol, 2963 struct rte_flow_error *error) 2964 { 2965 const struct rte_flow_item_udp *mask = item->mask; 2966 const int tunnel = !!(item_flags & MLX5_FLOW_LAYER_TUNNEL); 2967 const uint64_t l3m = tunnel ? MLX5_FLOW_LAYER_INNER_L3 : 2968 MLX5_FLOW_LAYER_OUTER_L3; 2969 const uint64_t l4m = tunnel ? MLX5_FLOW_LAYER_INNER_L4 : 2970 MLX5_FLOW_LAYER_OUTER_L4; 2971 int ret; 2972 2973 if (target_protocol != 0xff && target_protocol != IPPROTO_UDP) 2974 return rte_flow_error_set(error, EINVAL, 2975 RTE_FLOW_ERROR_TYPE_ITEM, item, 2976 "protocol filtering not compatible" 2977 " with UDP layer"); 2978 if (!(item_flags & l3m)) 2979 return rte_flow_error_set(error, EINVAL, 2980 RTE_FLOW_ERROR_TYPE_ITEM, item, 2981 "L3 is mandatory to filter on L4"); 2982 if (item_flags & l4m) 2983 return rte_flow_error_set(error, EINVAL, 2984 RTE_FLOW_ERROR_TYPE_ITEM, item, 2985 "multiple L4 layers not supported"); 2986 if (!mask) 2987 mask = &rte_flow_item_udp_mask; 2988 ret = mlx5_flow_item_acceptable 2989 (item, (const uint8_t *)mask, 2990 (const uint8_t *)&rte_flow_item_udp_mask, 2991 sizeof(struct rte_flow_item_udp), MLX5_ITEM_RANGE_NOT_ACCEPTED, 2992 error); 2993 if (ret < 0) 2994 return ret; 2995 return 0; 2996 } 2997 2998 /** 2999 * Validate TCP item. 3000 * 3001 * @param[in] item 3002 * Item specification. 3003 * @param[in] item_flags 3004 * Bit-fields that holds the items detected until now. 3005 * @param[in] target_protocol 3006 * The next protocol in the previous item. 3007 * @param[out] error 3008 * Pointer to error structure. 3009 * 3010 * @return 3011 * 0 on success, a negative errno value otherwise and rte_errno is set. 3012 */ 3013 int 3014 mlx5_flow_validate_item_tcp(const struct rte_flow_item *item, 3015 uint64_t item_flags, 3016 uint8_t target_protocol, 3017 const struct rte_flow_item_tcp *flow_mask, 3018 struct rte_flow_error *error) 3019 { 3020 const struct rte_flow_item_tcp *mask = item->mask; 3021 const int tunnel = !!(item_flags & MLX5_FLOW_LAYER_TUNNEL); 3022 const uint64_t l3m = tunnel ? MLX5_FLOW_LAYER_INNER_L3 : 3023 MLX5_FLOW_LAYER_OUTER_L3; 3024 const uint64_t l4m = tunnel ? MLX5_FLOW_LAYER_INNER_L4 : 3025 MLX5_FLOW_LAYER_OUTER_L4; 3026 int ret; 3027 3028 MLX5_ASSERT(flow_mask); 3029 if (target_protocol != 0xff && target_protocol != IPPROTO_TCP) 3030 return rte_flow_error_set(error, EINVAL, 3031 RTE_FLOW_ERROR_TYPE_ITEM, item, 3032 "protocol filtering not compatible" 3033 " with TCP layer"); 3034 if (!(item_flags & l3m)) 3035 return rte_flow_error_set(error, EINVAL, 3036 RTE_FLOW_ERROR_TYPE_ITEM, item, 3037 "L3 is mandatory to filter on L4"); 3038 if (item_flags & l4m) 3039 return rte_flow_error_set(error, EINVAL, 3040 RTE_FLOW_ERROR_TYPE_ITEM, item, 3041 "multiple L4 layers not supported"); 3042 if (!mask) 3043 mask = &rte_flow_item_tcp_mask; 3044 ret = mlx5_flow_item_acceptable 3045 (item, (const uint8_t *)mask, 3046 (const uint8_t *)flow_mask, 3047 sizeof(struct rte_flow_item_tcp), MLX5_ITEM_RANGE_NOT_ACCEPTED, 3048 error); 3049 if (ret < 0) 3050 return ret; 3051 return 0; 3052 } 3053 3054 /** 3055 * Validate VXLAN item. 3056 * 3057 * @param[in] dev 3058 * Pointer to the Ethernet device structure. 3059 * @param[in] udp_dport 3060 * UDP destination port 3061 * @param[in] item 3062 * Item specification. 3063 * @param[in] item_flags 3064 * Bit-fields that holds the items detected until now. 3065 * @param root 3066 * Whether action is on root table. 3067 * @param[out] error 3068 * Pointer to error structure. 3069 * 3070 * @return 3071 * 0 on success, a negative errno value otherwise and rte_errno is set. 3072 */ 3073 int 3074 mlx5_flow_validate_item_vxlan(struct rte_eth_dev *dev, 3075 uint16_t udp_dport, 3076 const struct rte_flow_item *item, 3077 uint64_t item_flags, 3078 bool root, 3079 struct rte_flow_error *error) 3080 { 3081 const struct rte_flow_item_vxlan *spec = item->spec; 3082 const struct rte_flow_item_vxlan *mask = item->mask; 3083 int ret; 3084 struct mlx5_priv *priv = dev->data->dev_private; 3085 union vni { 3086 uint32_t vlan_id; 3087 uint8_t vni[4]; 3088 } id = { .vlan_id = 0, }; 3089 const struct rte_flow_item_vxlan nic_mask = { 3090 .hdr.vni = "\xff\xff\xff", 3091 .hdr.rsvd1 = 0xff, 3092 }; 3093 const struct rte_flow_item_vxlan *valid_mask; 3094 3095 if (item_flags & MLX5_FLOW_LAYER_TUNNEL) 3096 return rte_flow_error_set(error, ENOTSUP, 3097 RTE_FLOW_ERROR_TYPE_ITEM, item, 3098 "multiple tunnel layers not" 3099 " supported"); 3100 valid_mask = &rte_flow_item_vxlan_mask; 3101 /* 3102 * Verify only UDPv4 is present as defined in 3103 * https://tools.ietf.org/html/rfc7348 3104 */ 3105 if (!(item_flags & MLX5_FLOW_LAYER_OUTER_L4_UDP)) 3106 return rte_flow_error_set(error, EINVAL, 3107 RTE_FLOW_ERROR_TYPE_ITEM, item, 3108 "no outer UDP layer found"); 3109 if (!mask) 3110 mask = &rte_flow_item_vxlan_mask; 3111 3112 if (priv->sh->steering_format_version != 3113 MLX5_STEERING_LOGIC_FORMAT_CONNECTX_5 || 3114 !udp_dport || udp_dport == MLX5_UDP_PORT_VXLAN) { 3115 /* non-root table */ 3116 if (!root && priv->sh->misc5_cap) 3117 valid_mask = &nic_mask; 3118 /* Group zero in NIC domain */ 3119 if (!root && priv->sh->tunnel_header_0_1) 3120 valid_mask = &nic_mask; 3121 } 3122 ret = mlx5_flow_item_acceptable 3123 (item, (const uint8_t *)mask, 3124 (const uint8_t *)valid_mask, 3125 sizeof(struct rte_flow_item_vxlan), 3126 MLX5_ITEM_RANGE_NOT_ACCEPTED, error); 3127 if (ret < 0) 3128 return ret; 3129 if (spec) { 3130 memcpy(&id.vni[1], spec->hdr.vni, 3); 3131 memcpy(&id.vni[1], mask->hdr.vni, 3); 3132 } 3133 if (!(item_flags & MLX5_FLOW_LAYER_OUTER)) 3134 return rte_flow_error_set(error, ENOTSUP, 3135 RTE_FLOW_ERROR_TYPE_ITEM, item, 3136 "VXLAN tunnel must be fully defined"); 3137 return 0; 3138 } 3139 3140 /** 3141 * Validate VXLAN_GPE item. 3142 * 3143 * @param[in] item 3144 * Item specification. 3145 * @param[in] item_flags 3146 * Bit-fields that holds the items detected until now. 3147 * @param[in] priv 3148 * Pointer to the private data structure. 3149 * @param[in] target_protocol 3150 * The next protocol in the previous item. 3151 * @param[out] error 3152 * Pointer to error structure. 3153 * 3154 * @return 3155 * 0 on success, a negative errno value otherwise and rte_errno is set. 3156 */ 3157 int 3158 mlx5_flow_validate_item_vxlan_gpe(const struct rte_flow_item *item, 3159 uint64_t item_flags, 3160 struct rte_eth_dev *dev, 3161 struct rte_flow_error *error) 3162 { 3163 struct mlx5_priv *priv = dev->data->dev_private; 3164 const struct rte_flow_item_vxlan_gpe *spec = item->spec; 3165 const struct rte_flow_item_vxlan_gpe *mask = item->mask; 3166 int ret; 3167 union vni { 3168 uint32_t vlan_id; 3169 uint8_t vni[4]; 3170 } id = { .vlan_id = 0, }; 3171 3172 struct rte_flow_item_vxlan_gpe nic_mask = { 3173 .vni = "\xff\xff\xff", 3174 .protocol = 0xff, 3175 }; 3176 3177 if (!priv->sh->config.l3_vxlan_en) 3178 return rte_flow_error_set(error, ENOTSUP, 3179 RTE_FLOW_ERROR_TYPE_ITEM, item, 3180 "L3 VXLAN is not enabled by device" 3181 " parameter and/or not configured in" 3182 " firmware"); 3183 if (item_flags & MLX5_FLOW_LAYER_TUNNEL) 3184 return rte_flow_error_set(error, ENOTSUP, 3185 RTE_FLOW_ERROR_TYPE_ITEM, item, 3186 "multiple tunnel layers not" 3187 " supported"); 3188 /* 3189 * Verify only UDPv4 is present as defined in 3190 * https://tools.ietf.org/html/rfc7348 3191 */ 3192 if (!(item_flags & MLX5_FLOW_LAYER_OUTER_L4_UDP)) 3193 return rte_flow_error_set(error, EINVAL, 3194 RTE_FLOW_ERROR_TYPE_ITEM, item, 3195 "no outer UDP layer found"); 3196 if (!mask) 3197 mask = &rte_flow_item_vxlan_gpe_mask; 3198 ret = mlx5_flow_item_acceptable 3199 (item, (const uint8_t *)mask, 3200 (const uint8_t *)&nic_mask, 3201 sizeof(struct rte_flow_item_vxlan_gpe), 3202 MLX5_ITEM_RANGE_NOT_ACCEPTED, error); 3203 if (ret < 0) 3204 return ret; 3205 if (spec) { 3206 memcpy(&id.vni[1], spec->hdr.vni, 3); 3207 memcpy(&id.vni[1], mask->hdr.vni, 3); 3208 } 3209 if (!(item_flags & MLX5_FLOW_LAYER_OUTER)) 3210 return rte_flow_error_set(error, ENOTSUP, 3211 RTE_FLOW_ERROR_TYPE_ITEM, item, 3212 "VXLAN-GPE tunnel must be fully" 3213 " defined"); 3214 return 0; 3215 } 3216 /** 3217 * Validate GRE Key item. 3218 * 3219 * @param[in] item 3220 * Item specification. 3221 * @param[in] item_flags 3222 * Bit flags to mark detected items. 3223 * @param[in] gre_item 3224 * Pointer to gre_item 3225 * @param[out] error 3226 * Pointer to error structure. 3227 * 3228 * @return 3229 * 0 on success, a negative errno value otherwise and rte_errno is set. 3230 */ 3231 int 3232 mlx5_flow_validate_item_gre_key(const struct rte_flow_item *item, 3233 uint64_t item_flags, 3234 const struct rte_flow_item *gre_item, 3235 struct rte_flow_error *error) 3236 { 3237 const rte_be32_t *mask = item->mask; 3238 int ret = 0; 3239 rte_be32_t gre_key_default_mask = RTE_BE32(UINT32_MAX); 3240 const struct rte_flow_item_gre *gre_spec; 3241 const struct rte_flow_item_gre *gre_mask; 3242 3243 if (item_flags & MLX5_FLOW_LAYER_GRE_KEY) 3244 return rte_flow_error_set(error, ENOTSUP, 3245 RTE_FLOW_ERROR_TYPE_ITEM, item, 3246 "Multiple GRE key not support"); 3247 if (!(item_flags & MLX5_FLOW_LAYER_GRE)) 3248 return rte_flow_error_set(error, ENOTSUP, 3249 RTE_FLOW_ERROR_TYPE_ITEM, item, 3250 "No preceding GRE header"); 3251 if (item_flags & MLX5_FLOW_LAYER_INNER) 3252 return rte_flow_error_set(error, ENOTSUP, 3253 RTE_FLOW_ERROR_TYPE_ITEM, item, 3254 "GRE key following a wrong item"); 3255 gre_mask = gre_item->mask; 3256 if (!gre_mask) 3257 gre_mask = &rte_flow_item_gre_mask; 3258 gre_spec = gre_item->spec; 3259 if (gre_spec && (gre_mask->c_rsvd0_ver & RTE_BE16(0x2000)) && 3260 !(gre_spec->c_rsvd0_ver & RTE_BE16(0x2000))) 3261 return rte_flow_error_set(error, EINVAL, 3262 RTE_FLOW_ERROR_TYPE_ITEM, item, 3263 "Key bit must be on"); 3264 3265 if (!mask) 3266 mask = &gre_key_default_mask; 3267 ret = mlx5_flow_item_acceptable 3268 (item, (const uint8_t *)mask, 3269 (const uint8_t *)&gre_key_default_mask, 3270 sizeof(rte_be32_t), MLX5_ITEM_RANGE_NOT_ACCEPTED, error); 3271 return ret; 3272 } 3273 3274 /** 3275 * Validate GRE optional item. 3276 * 3277 * @param[in] dev 3278 * Pointer to the Ethernet device structure. 3279 * @param[in] item 3280 * Item specification. 3281 * @param[in] item_flags 3282 * Bit flags to mark detected items. 3283 * @param[in] attr 3284 * Flow rule attributes. 3285 * @param[in] gre_item 3286 * Pointer to gre_item 3287 * @param[out] error 3288 * Pointer to error structure. 3289 * 3290 * @return 3291 * 0 on success, a negative errno value otherwise and rte_errno is set. 3292 */ 3293 int 3294 mlx5_flow_validate_item_gre_option(struct rte_eth_dev *dev, 3295 const struct rte_flow_item *item, 3296 uint64_t item_flags, 3297 const struct rte_flow_attr *attr, 3298 const struct rte_flow_item *gre_item, 3299 struct rte_flow_error *error) 3300 { 3301 const struct rte_flow_item_gre *gre_spec = gre_item->spec; 3302 const struct rte_flow_item_gre *gre_mask = gre_item->mask; 3303 const struct rte_flow_item_gre_opt *spec = item->spec; 3304 const struct rte_flow_item_gre_opt *mask = item->mask; 3305 struct mlx5_priv *priv = dev->data->dev_private; 3306 int ret = 0; 3307 struct rte_flow_item_gre_opt nic_mask = { 3308 .checksum_rsvd = { 3309 .checksum = RTE_BE16(UINT16_MAX), 3310 .reserved1 = 0x0, 3311 }, 3312 .key = { 3313 .key = RTE_BE32(UINT32_MAX), 3314 }, 3315 .sequence = { 3316 .sequence = RTE_BE32(UINT32_MAX), 3317 }, 3318 }; 3319 3320 if (!(item_flags & MLX5_FLOW_LAYER_GRE)) 3321 return rte_flow_error_set(error, ENOTSUP, 3322 RTE_FLOW_ERROR_TYPE_ITEM, item, 3323 "No preceding GRE header"); 3324 if (item_flags & MLX5_FLOW_LAYER_INNER) 3325 return rte_flow_error_set(error, ENOTSUP, 3326 RTE_FLOW_ERROR_TYPE_ITEM, item, 3327 "GRE option following a wrong item"); 3328 if (!spec || !mask) 3329 return rte_flow_error_set(error, EINVAL, 3330 RTE_FLOW_ERROR_TYPE_ITEM, item, 3331 "At least one field gre_option(checksum/key/sequence) must be specified"); 3332 if (!gre_mask) 3333 gre_mask = &rte_flow_item_gre_mask; 3334 if (mask->checksum_rsvd.checksum) 3335 if (gre_spec && (gre_mask->c_rsvd0_ver & RTE_BE16(0x8000)) && 3336 !(gre_spec->c_rsvd0_ver & RTE_BE16(0x8000))) 3337 return rte_flow_error_set(error, EINVAL, 3338 RTE_FLOW_ERROR_TYPE_ITEM, 3339 item, 3340 "Checksum bit must be on"); 3341 if (mask->key.key) 3342 if (gre_spec && (gre_mask->c_rsvd0_ver & RTE_BE16(0x2000)) && 3343 !(gre_spec->c_rsvd0_ver & RTE_BE16(0x2000))) 3344 return rte_flow_error_set(error, EINVAL, 3345 RTE_FLOW_ERROR_TYPE_ITEM, 3346 item, "Key bit must be on"); 3347 if (mask->sequence.sequence) 3348 if (gre_spec && (gre_mask->c_rsvd0_ver & RTE_BE16(0x1000)) && 3349 !(gre_spec->c_rsvd0_ver & RTE_BE16(0x1000))) 3350 return rte_flow_error_set(error, EINVAL, 3351 RTE_FLOW_ERROR_TYPE_ITEM, 3352 item, 3353 "Sequence bit must be on"); 3354 if (mask->checksum_rsvd.checksum || mask->sequence.sequence) { 3355 if (priv->sh->steering_format_version == 3356 MLX5_STEERING_LOGIC_FORMAT_CONNECTX_5 || 3357 ((attr->group || (attr->transfer && priv->fdb_def_rule)) && 3358 !priv->sh->misc5_cap) || 3359 (!(priv->sh->tunnel_header_0_1 && 3360 priv->sh->tunnel_header_2_3) && 3361 !attr->group && (!attr->transfer || !priv->fdb_def_rule))) 3362 return rte_flow_error_set(error, EINVAL, 3363 RTE_FLOW_ERROR_TYPE_ITEM, 3364 item, 3365 "Checksum/Sequence not supported"); 3366 } 3367 ret = mlx5_flow_item_acceptable 3368 (item, (const uint8_t *)mask, 3369 (const uint8_t *)&nic_mask, 3370 sizeof(struct rte_flow_item_gre_opt), 3371 MLX5_ITEM_RANGE_NOT_ACCEPTED, error); 3372 return ret; 3373 } 3374 3375 /** 3376 * Validate GRE item. 3377 * 3378 * @param[in] item 3379 * Item specification. 3380 * @param[in] item_flags 3381 * Bit flags to mark detected items. 3382 * @param[in] target_protocol 3383 * The next protocol in the previous item. 3384 * @param[out] error 3385 * Pointer to error structure. 3386 * 3387 * @return 3388 * 0 on success, a negative errno value otherwise and rte_errno is set. 3389 */ 3390 int 3391 mlx5_flow_validate_item_gre(const struct rte_flow_item *item, 3392 uint64_t item_flags, 3393 uint8_t target_protocol, 3394 struct rte_flow_error *error) 3395 { 3396 const struct rte_flow_item_gre *spec __rte_unused = item->spec; 3397 const struct rte_flow_item_gre *mask = item->mask; 3398 int ret; 3399 const struct rte_flow_item_gre nic_mask = { 3400 .c_rsvd0_ver = RTE_BE16(0xB000), 3401 .protocol = RTE_BE16(UINT16_MAX), 3402 }; 3403 3404 if (target_protocol != 0xff && target_protocol != IPPROTO_GRE) 3405 return rte_flow_error_set(error, EINVAL, 3406 RTE_FLOW_ERROR_TYPE_ITEM, item, 3407 "protocol filtering not compatible" 3408 " with this GRE layer"); 3409 if (item_flags & MLX5_FLOW_LAYER_TUNNEL) 3410 return rte_flow_error_set(error, ENOTSUP, 3411 RTE_FLOW_ERROR_TYPE_ITEM, item, 3412 "multiple tunnel layers not" 3413 " supported"); 3414 if (!(item_flags & MLX5_FLOW_LAYER_OUTER_L3)) 3415 return rte_flow_error_set(error, ENOTSUP, 3416 RTE_FLOW_ERROR_TYPE_ITEM, item, 3417 "L3 Layer is missing"); 3418 if (!mask) 3419 mask = &rte_flow_item_gre_mask; 3420 ret = mlx5_flow_item_acceptable 3421 (item, (const uint8_t *)mask, 3422 (const uint8_t *)&nic_mask, 3423 sizeof(struct rte_flow_item_gre), MLX5_ITEM_RANGE_NOT_ACCEPTED, 3424 error); 3425 if (ret < 0) 3426 return ret; 3427 #ifndef HAVE_MLX5DV_DR 3428 #ifndef HAVE_IBV_DEVICE_MPLS_SUPPORT 3429 if (spec && (spec->protocol & mask->protocol)) 3430 return rte_flow_error_set(error, ENOTSUP, 3431 RTE_FLOW_ERROR_TYPE_ITEM, item, 3432 "without MPLS support the" 3433 " specification cannot be used for" 3434 " filtering"); 3435 #endif 3436 #endif 3437 return 0; 3438 } 3439 3440 /** 3441 * Validate Geneve item. 3442 * 3443 * @param[in] item 3444 * Item specification. 3445 * @param[in] itemFlags 3446 * Bit-fields that holds the items detected until now. 3447 * @param[in] enPriv 3448 * Pointer to the private data structure. 3449 * @param[out] error 3450 * Pointer to error structure. 3451 * 3452 * @return 3453 * 0 on success, a negative errno value otherwise and rte_errno is set. 3454 */ 3455 3456 int 3457 mlx5_flow_validate_item_geneve(const struct rte_flow_item *item, 3458 uint64_t item_flags, 3459 struct rte_eth_dev *dev, 3460 struct rte_flow_error *error) 3461 { 3462 struct mlx5_priv *priv = dev->data->dev_private; 3463 const struct rte_flow_item_geneve *spec = item->spec; 3464 const struct rte_flow_item_geneve *mask = item->mask; 3465 int ret; 3466 uint16_t gbhdr; 3467 uint8_t opt_len = priv->sh->cdev->config.hca_attr.geneve_max_opt_len ? 3468 MLX5_GENEVE_OPT_LEN_1 : MLX5_GENEVE_OPT_LEN_0; 3469 const struct rte_flow_item_geneve nic_mask = { 3470 .ver_opt_len_o_c_rsvd0 = RTE_BE16(0x3f80), 3471 .vni = "\xff\xff\xff", 3472 .protocol = RTE_BE16(UINT16_MAX), 3473 }; 3474 3475 if (!priv->sh->cdev->config.hca_attr.tunnel_stateless_geneve_rx) 3476 return rte_flow_error_set(error, ENOTSUP, 3477 RTE_FLOW_ERROR_TYPE_ITEM, item, 3478 "L3 Geneve is not enabled by device" 3479 " parameter and/or not configured in" 3480 " firmware"); 3481 if (item_flags & MLX5_FLOW_LAYER_TUNNEL) 3482 return rte_flow_error_set(error, ENOTSUP, 3483 RTE_FLOW_ERROR_TYPE_ITEM, item, 3484 "multiple tunnel layers not" 3485 " supported"); 3486 /* 3487 * Verify only UDPv4 is present as defined in 3488 * https://tools.ietf.org/html/rfc7348 3489 */ 3490 if (!(item_flags & MLX5_FLOW_LAYER_OUTER_L4_UDP)) 3491 return rte_flow_error_set(error, EINVAL, 3492 RTE_FLOW_ERROR_TYPE_ITEM, item, 3493 "no outer UDP layer found"); 3494 if (!mask) 3495 mask = &rte_flow_item_geneve_mask; 3496 ret = mlx5_flow_item_acceptable 3497 (item, (const uint8_t *)mask, 3498 (const uint8_t *)&nic_mask, 3499 sizeof(struct rte_flow_item_geneve), 3500 MLX5_ITEM_RANGE_NOT_ACCEPTED, error); 3501 if (ret) 3502 return ret; 3503 if (spec) { 3504 gbhdr = rte_be_to_cpu_16(spec->ver_opt_len_o_c_rsvd0); 3505 if (MLX5_GENEVE_VER_VAL(gbhdr) || 3506 MLX5_GENEVE_CRITO_VAL(gbhdr) || 3507 MLX5_GENEVE_RSVD_VAL(gbhdr) || spec->rsvd1) 3508 return rte_flow_error_set(error, ENOTSUP, 3509 RTE_FLOW_ERROR_TYPE_ITEM, 3510 item, 3511 "Geneve protocol unsupported" 3512 " fields are being used"); 3513 if (MLX5_GENEVE_OPTLEN_VAL(gbhdr) > opt_len) 3514 return rte_flow_error_set 3515 (error, ENOTSUP, 3516 RTE_FLOW_ERROR_TYPE_ITEM, 3517 item, 3518 "Unsupported Geneve options length"); 3519 } 3520 if (!(item_flags & MLX5_FLOW_LAYER_OUTER)) 3521 return rte_flow_error_set 3522 (error, ENOTSUP, 3523 RTE_FLOW_ERROR_TYPE_ITEM, item, 3524 "Geneve tunnel must be fully defined"); 3525 return 0; 3526 } 3527 3528 /** 3529 * Validate Geneve TLV option item. 3530 * 3531 * @param[in] item 3532 * Item specification. 3533 * @param[in] last_item 3534 * Previous validated item in the pattern items. 3535 * @param[in] geneve_item 3536 * Previous GENEVE item specification. 3537 * @param[in] dev 3538 * Pointer to the rte_eth_dev structure. 3539 * @param[out] error 3540 * Pointer to error structure. 3541 * 3542 * @return 3543 * 0 on success, a negative errno value otherwise and rte_errno is set. 3544 */ 3545 int 3546 mlx5_flow_validate_item_geneve_opt(const struct rte_flow_item *item, 3547 uint64_t last_item, 3548 const struct rte_flow_item *geneve_item, 3549 struct rte_eth_dev *dev, 3550 struct rte_flow_error *error) 3551 { 3552 struct mlx5_priv *priv = dev->data->dev_private; 3553 struct mlx5_dev_ctx_shared *sh = priv->sh; 3554 struct mlx5_geneve_tlv_option_resource *geneve_opt_resource; 3555 struct mlx5_hca_attr *hca_attr = &sh->cdev->config.hca_attr; 3556 uint8_t data_max_supported = 3557 hca_attr->max_geneve_tlv_option_data_len * 4; 3558 const struct rte_flow_item_geneve *geneve_spec; 3559 const struct rte_flow_item_geneve *geneve_mask; 3560 const struct rte_flow_item_geneve_opt *spec = item->spec; 3561 const struct rte_flow_item_geneve_opt *mask = item->mask; 3562 unsigned int i; 3563 unsigned int data_len; 3564 uint8_t tlv_option_len; 3565 uint16_t optlen_m, optlen_v; 3566 const struct rte_flow_item_geneve_opt full_mask = { 3567 .option_class = RTE_BE16(0xffff), 3568 .option_type = 0xff, 3569 .option_len = 0x1f, 3570 }; 3571 3572 if (!mask) 3573 mask = &rte_flow_item_geneve_opt_mask; 3574 if (!spec) 3575 return rte_flow_error_set 3576 (error, ENOTSUP, RTE_FLOW_ERROR_TYPE_ITEM, item, 3577 "Geneve TLV opt class/type/length must be specified"); 3578 if ((uint32_t)spec->option_len > MLX5_GENEVE_OPTLEN_MASK) 3579 return rte_flow_error_set 3580 (error, ENOTSUP, RTE_FLOW_ERROR_TYPE_ITEM, item, 3581 "Geneve TLV opt length exceeds the limit (31)"); 3582 /* Check if class type and length masks are full. */ 3583 if (full_mask.option_class != mask->option_class || 3584 full_mask.option_type != mask->option_type || 3585 full_mask.option_len != (mask->option_len & full_mask.option_len)) 3586 return rte_flow_error_set 3587 (error, ENOTSUP, RTE_FLOW_ERROR_TYPE_ITEM, item, 3588 "Geneve TLV opt class/type/length masks must be full"); 3589 /* Check if length is supported */ 3590 if ((uint32_t)spec->option_len > 3591 hca_attr->max_geneve_tlv_option_data_len) 3592 return rte_flow_error_set 3593 (error, ENOTSUP, RTE_FLOW_ERROR_TYPE_ITEM, item, 3594 "Geneve TLV opt length not supported"); 3595 if (hca_attr->max_geneve_tlv_options > 1) 3596 DRV_LOG(DEBUG, 3597 "max_geneve_tlv_options supports more than 1 option"); 3598 /* Check GENEVE item preceding. */ 3599 if (!geneve_item || !(last_item & MLX5_FLOW_LAYER_GENEVE)) 3600 return rte_flow_error_set 3601 (error, ENOTSUP, RTE_FLOW_ERROR_TYPE_ITEM, item, 3602 "Geneve opt item must be preceded with Geneve item"); 3603 geneve_spec = geneve_item->spec; 3604 geneve_mask = geneve_item->mask ? geneve_item->mask : 3605 &rte_flow_item_geneve_mask; 3606 /* Check if GENEVE TLV option size doesn't exceed option length */ 3607 if (geneve_spec && (geneve_mask->ver_opt_len_o_c_rsvd0 || 3608 geneve_spec->ver_opt_len_o_c_rsvd0)) { 3609 tlv_option_len = spec->option_len & mask->option_len; 3610 optlen_v = rte_be_to_cpu_16(geneve_spec->ver_opt_len_o_c_rsvd0); 3611 optlen_v = MLX5_GENEVE_OPTLEN_VAL(optlen_v); 3612 optlen_m = rte_be_to_cpu_16(geneve_mask->ver_opt_len_o_c_rsvd0); 3613 optlen_m = MLX5_GENEVE_OPTLEN_VAL(optlen_m); 3614 if ((optlen_v & optlen_m) <= tlv_option_len) 3615 return rte_flow_error_set 3616 (error, ENOTSUP, RTE_FLOW_ERROR_TYPE_ITEM, item, 3617 "GENEVE TLV option length exceeds optlen"); 3618 } 3619 /* Check if length is 0 or data is 0. */ 3620 if (spec->data == NULL || spec->option_len == 0) 3621 return rte_flow_error_set 3622 (error, ENOTSUP, RTE_FLOW_ERROR_TYPE_ITEM, item, 3623 "Geneve TLV opt with zero data/length not supported"); 3624 /* Check not all data & mask are 0. */ 3625 data_len = spec->option_len * 4; 3626 if (mask->data == NULL) { 3627 for (i = 0; i < data_len; i++) 3628 if (spec->data[i]) 3629 break; 3630 if (i == data_len) 3631 return rte_flow_error_set(error, ENOTSUP, 3632 RTE_FLOW_ERROR_TYPE_ITEM, item, 3633 "Can't match on Geneve option data 0"); 3634 } else { 3635 for (i = 0; i < data_len; i++) 3636 if (spec->data[i] & mask->data[i]) 3637 break; 3638 if (i == data_len) 3639 return rte_flow_error_set(error, ENOTSUP, 3640 RTE_FLOW_ERROR_TYPE_ITEM, item, 3641 "Can't match on Geneve option data and mask 0"); 3642 /* Check data mask supported. */ 3643 for (i = data_max_supported; i < data_len ; i++) 3644 if (mask->data[i]) 3645 return rte_flow_error_set(error, ENOTSUP, 3646 RTE_FLOW_ERROR_TYPE_ITEM, item, 3647 "Data mask is of unsupported size"); 3648 } 3649 /* Check GENEVE option is supported in NIC. */ 3650 if (!hca_attr->geneve_tlv_opt) 3651 return rte_flow_error_set 3652 (error, ENOTSUP, RTE_FLOW_ERROR_TYPE_ITEM, item, 3653 "Geneve TLV opt not supported"); 3654 /* Check if we already have geneve option with different type/class. */ 3655 rte_spinlock_lock(&sh->geneve_tlv_opt_sl); 3656 geneve_opt_resource = sh->geneve_tlv_option_resource; 3657 if (geneve_opt_resource != NULL) 3658 if (geneve_opt_resource->option_class != spec->option_class || 3659 geneve_opt_resource->option_type != spec->option_type || 3660 geneve_opt_resource->length != spec->option_len) { 3661 rte_spinlock_unlock(&sh->geneve_tlv_opt_sl); 3662 return rte_flow_error_set(error, ENOTSUP, 3663 RTE_FLOW_ERROR_TYPE_ITEM, item, 3664 "Only one Geneve TLV option supported"); 3665 } 3666 rte_spinlock_unlock(&sh->geneve_tlv_opt_sl); 3667 return 0; 3668 } 3669 3670 /** 3671 * Validate MPLS item. 3672 * 3673 * @param[in] dev 3674 * Pointer to the rte_eth_dev structure. 3675 * @param[in] item 3676 * Item specification. 3677 * @param[in] item_flags 3678 * Bit-fields that holds the items detected until now. 3679 * @param[in] prev_layer 3680 * The protocol layer indicated in previous item. 3681 * @param[out] error 3682 * Pointer to error structure. 3683 * 3684 * @return 3685 * 0 on success, a negative errno value otherwise and rte_errno is set. 3686 */ 3687 int 3688 mlx5_flow_validate_item_mpls(struct rte_eth_dev *dev __rte_unused, 3689 const struct rte_flow_item *item __rte_unused, 3690 uint64_t item_flags __rte_unused, 3691 uint64_t prev_layer __rte_unused, 3692 struct rte_flow_error *error) 3693 { 3694 #ifdef HAVE_IBV_DEVICE_MPLS_SUPPORT 3695 const struct rte_flow_item_mpls *mask = item->mask; 3696 struct mlx5_priv *priv = dev->data->dev_private; 3697 int ret; 3698 3699 if (!priv->sh->dev_cap.mpls_en) 3700 return rte_flow_error_set(error, ENOTSUP, 3701 RTE_FLOW_ERROR_TYPE_ITEM, item, 3702 "MPLS not supported or" 3703 " disabled in firmware" 3704 " configuration."); 3705 /* MPLS over UDP, GRE is allowed */ 3706 if (!(prev_layer & (MLX5_FLOW_LAYER_OUTER_L4_UDP | 3707 MLX5_FLOW_LAYER_GRE | 3708 MLX5_FLOW_LAYER_GRE_KEY))) 3709 return rte_flow_error_set(error, EINVAL, 3710 RTE_FLOW_ERROR_TYPE_ITEM, item, 3711 "protocol filtering not compatible" 3712 " with MPLS layer"); 3713 /* Multi-tunnel isn't allowed but MPLS over GRE is an exception. */ 3714 if ((item_flags & MLX5_FLOW_LAYER_TUNNEL) && 3715 !(item_flags & MLX5_FLOW_LAYER_GRE)) 3716 return rte_flow_error_set(error, ENOTSUP, 3717 RTE_FLOW_ERROR_TYPE_ITEM, item, 3718 "multiple tunnel layers not" 3719 " supported"); 3720 if (!mask) 3721 mask = &rte_flow_item_mpls_mask; 3722 ret = mlx5_flow_item_acceptable 3723 (item, (const uint8_t *)mask, 3724 (const uint8_t *)&rte_flow_item_mpls_mask, 3725 sizeof(struct rte_flow_item_mpls), 3726 MLX5_ITEM_RANGE_NOT_ACCEPTED, error); 3727 if (ret < 0) 3728 return ret; 3729 return 0; 3730 #else 3731 return rte_flow_error_set(error, ENOTSUP, 3732 RTE_FLOW_ERROR_TYPE_ITEM, item, 3733 "MPLS is not supported by Verbs, please" 3734 " update."); 3735 #endif 3736 } 3737 3738 /** 3739 * Validate NVGRE item. 3740 * 3741 * @param[in] item 3742 * Item specification. 3743 * @param[in] item_flags 3744 * Bit flags to mark detected items. 3745 * @param[in] target_protocol 3746 * The next protocol in the previous item. 3747 * @param[out] error 3748 * Pointer to error structure. 3749 * 3750 * @return 3751 * 0 on success, a negative errno value otherwise and rte_errno is set. 3752 */ 3753 int 3754 mlx5_flow_validate_item_nvgre(const struct rte_flow_item *item, 3755 uint64_t item_flags, 3756 uint8_t target_protocol, 3757 struct rte_flow_error *error) 3758 { 3759 const struct rte_flow_item_nvgre *mask = item->mask; 3760 int ret; 3761 3762 if (target_protocol != 0xff && target_protocol != IPPROTO_GRE) 3763 return rte_flow_error_set(error, EINVAL, 3764 RTE_FLOW_ERROR_TYPE_ITEM, item, 3765 "protocol filtering not compatible" 3766 " with this GRE layer"); 3767 if (item_flags & MLX5_FLOW_LAYER_TUNNEL) 3768 return rte_flow_error_set(error, ENOTSUP, 3769 RTE_FLOW_ERROR_TYPE_ITEM, item, 3770 "multiple tunnel layers not" 3771 " supported"); 3772 if (!(item_flags & MLX5_FLOW_LAYER_OUTER_L3)) 3773 return rte_flow_error_set(error, ENOTSUP, 3774 RTE_FLOW_ERROR_TYPE_ITEM, item, 3775 "L3 Layer is missing"); 3776 if (!mask) 3777 mask = &rte_flow_item_nvgre_mask; 3778 ret = mlx5_flow_item_acceptable 3779 (item, (const uint8_t *)mask, 3780 (const uint8_t *)&rte_flow_item_nvgre_mask, 3781 sizeof(struct rte_flow_item_nvgre), 3782 MLX5_ITEM_RANGE_NOT_ACCEPTED, error); 3783 if (ret < 0) 3784 return ret; 3785 return 0; 3786 } 3787 3788 /** 3789 * Validate eCPRI item. 3790 * 3791 * @param[in] item 3792 * Item specification. 3793 * @param[in] item_flags 3794 * Bit-fields that holds the items detected until now. 3795 * @param[in] last_item 3796 * Previous validated item in the pattern items. 3797 * @param[in] ether_type 3798 * Type in the ethernet layer header (including dot1q). 3799 * @param[in] acc_mask 3800 * Acceptable mask, if NULL default internal default mask 3801 * will be used to check whether item fields are supported. 3802 * @param[out] error 3803 * Pointer to error structure. 3804 * 3805 * @return 3806 * 0 on success, a negative errno value otherwise and rte_errno is set. 3807 */ 3808 int 3809 mlx5_flow_validate_item_ecpri(const struct rte_flow_item *item, 3810 uint64_t item_flags, 3811 uint64_t last_item, 3812 uint16_t ether_type, 3813 const struct rte_flow_item_ecpri *acc_mask, 3814 struct rte_flow_error *error) 3815 { 3816 const struct rte_flow_item_ecpri *mask = item->mask; 3817 const struct rte_flow_item_ecpri nic_mask = { 3818 .hdr = { 3819 .common = { 3820 .u32 = 3821 RTE_BE32(((const struct rte_ecpri_common_hdr) { 3822 .type = 0xFF, 3823 }).u32), 3824 }, 3825 .dummy[0] = 0xFFFFFFFF, 3826 }, 3827 }; 3828 const uint64_t outer_l2_vlan = (MLX5_FLOW_LAYER_OUTER_L2 | 3829 MLX5_FLOW_LAYER_OUTER_VLAN); 3830 struct rte_flow_item_ecpri mask_lo; 3831 3832 if (!(last_item & outer_l2_vlan) && 3833 last_item != MLX5_FLOW_LAYER_OUTER_L4_UDP) 3834 return rte_flow_error_set(error, EINVAL, 3835 RTE_FLOW_ERROR_TYPE_ITEM, item, 3836 "eCPRI can only follow L2/VLAN layer or UDP layer"); 3837 if ((last_item & outer_l2_vlan) && ether_type && 3838 ether_type != RTE_ETHER_TYPE_ECPRI) 3839 return rte_flow_error_set(error, EINVAL, 3840 RTE_FLOW_ERROR_TYPE_ITEM, item, 3841 "eCPRI cannot follow L2/VLAN layer which ether type is not 0xAEFE"); 3842 if (item_flags & MLX5_FLOW_LAYER_TUNNEL) 3843 return rte_flow_error_set(error, EINVAL, 3844 RTE_FLOW_ERROR_TYPE_ITEM, item, 3845 "eCPRI with tunnel is not supported right now"); 3846 if (item_flags & MLX5_FLOW_LAYER_OUTER_L3) 3847 return rte_flow_error_set(error, ENOTSUP, 3848 RTE_FLOW_ERROR_TYPE_ITEM, item, 3849 "multiple L3 layers not supported"); 3850 else if (item_flags & MLX5_FLOW_LAYER_OUTER_L4_TCP) 3851 return rte_flow_error_set(error, EINVAL, 3852 RTE_FLOW_ERROR_TYPE_ITEM, item, 3853 "eCPRI cannot coexist with a TCP layer"); 3854 /* In specification, eCPRI could be over UDP layer. */ 3855 else if (item_flags & MLX5_FLOW_LAYER_OUTER_L4_UDP) 3856 return rte_flow_error_set(error, EINVAL, 3857 RTE_FLOW_ERROR_TYPE_ITEM, item, 3858 "eCPRI over UDP layer is not yet supported right now"); 3859 /* Mask for type field in common header could be zero. */ 3860 if (!mask) 3861 mask = &rte_flow_item_ecpri_mask; 3862 mask_lo.hdr.common.u32 = rte_be_to_cpu_32(mask->hdr.common.u32); 3863 /* Input mask is in big-endian format. */ 3864 if (mask_lo.hdr.common.type != 0 && mask_lo.hdr.common.type != 0xff) 3865 return rte_flow_error_set(error, EINVAL, 3866 RTE_FLOW_ERROR_TYPE_ITEM_MASK, mask, 3867 "partial mask is not supported for protocol"); 3868 else if (mask_lo.hdr.common.type == 0 && mask->hdr.dummy[0] != 0) 3869 return rte_flow_error_set(error, EINVAL, 3870 RTE_FLOW_ERROR_TYPE_ITEM_MASK, mask, 3871 "message header mask must be after a type mask"); 3872 return mlx5_flow_item_acceptable(item, (const uint8_t *)mask, 3873 acc_mask ? (const uint8_t *)acc_mask 3874 : (const uint8_t *)&nic_mask, 3875 sizeof(struct rte_flow_item_ecpri), 3876 MLX5_ITEM_RANGE_NOT_ACCEPTED, error); 3877 } 3878 3879 /** 3880 * Validate the NSH item. 3881 * 3882 * @param[in] dev 3883 * Pointer to Ethernet device on which flow rule is being created on. 3884 * @param[out] error 3885 * Pointer to error structure. 3886 * 3887 * @return 3888 * 0 on success, a negative errno value otherwise and rte_errno is set. 3889 */ 3890 int 3891 mlx5_flow_validate_item_nsh(struct rte_eth_dev *dev, 3892 const struct rte_flow_item *item, 3893 struct rte_flow_error *error) 3894 { 3895 struct mlx5_priv *priv = dev->data->dev_private; 3896 3897 if (item->mask) { 3898 return rte_flow_error_set(error, ENOTSUP, 3899 RTE_FLOW_ERROR_TYPE_ITEM, item, 3900 "NSH fields matching is not supported"); 3901 } 3902 3903 if (!priv->sh->config.dv_flow_en) { 3904 return rte_flow_error_set(error, ENOTSUP, 3905 RTE_FLOW_ERROR_TYPE_UNSPECIFIED, 3906 NULL, "NSH support requires DV flow interface"); 3907 } 3908 3909 if (!priv->sh->cdev->config.hca_attr.tunnel_stateless_vxlan_gpe_nsh) { 3910 return rte_flow_error_set(error, ENOTSUP, 3911 RTE_FLOW_ERROR_TYPE_ITEM, item, 3912 "Current FW does not support matching on NSH"); 3913 } 3914 3915 return 0; 3916 } 3917 3918 static int 3919 flow_null_validate(struct rte_eth_dev *dev __rte_unused, 3920 const struct rte_flow_attr *attr __rte_unused, 3921 const struct rte_flow_item items[] __rte_unused, 3922 const struct rte_flow_action actions[] __rte_unused, 3923 bool external __rte_unused, 3924 int hairpin __rte_unused, 3925 struct rte_flow_error *error) 3926 { 3927 return rte_flow_error_set(error, ENOTSUP, 3928 RTE_FLOW_ERROR_TYPE_UNSPECIFIED, NULL, NULL); 3929 } 3930 3931 static struct mlx5_flow * 3932 flow_null_prepare(struct rte_eth_dev *dev __rte_unused, 3933 const struct rte_flow_attr *attr __rte_unused, 3934 const struct rte_flow_item items[] __rte_unused, 3935 const struct rte_flow_action actions[] __rte_unused, 3936 struct rte_flow_error *error) 3937 { 3938 rte_flow_error_set(error, ENOTSUP, 3939 RTE_FLOW_ERROR_TYPE_UNSPECIFIED, NULL, NULL); 3940 return NULL; 3941 } 3942 3943 static int 3944 flow_null_translate(struct rte_eth_dev *dev __rte_unused, 3945 struct mlx5_flow *dev_flow __rte_unused, 3946 const struct rte_flow_attr *attr __rte_unused, 3947 const struct rte_flow_item items[] __rte_unused, 3948 const struct rte_flow_action actions[] __rte_unused, 3949 struct rte_flow_error *error) 3950 { 3951 return rte_flow_error_set(error, ENOTSUP, 3952 RTE_FLOW_ERROR_TYPE_UNSPECIFIED, NULL, NULL); 3953 } 3954 3955 static int 3956 flow_null_apply(struct rte_eth_dev *dev __rte_unused, 3957 struct rte_flow *flow __rte_unused, 3958 struct rte_flow_error *error) 3959 { 3960 return rte_flow_error_set(error, ENOTSUP, 3961 RTE_FLOW_ERROR_TYPE_UNSPECIFIED, NULL, NULL); 3962 } 3963 3964 static void 3965 flow_null_remove(struct rte_eth_dev *dev __rte_unused, 3966 struct rte_flow *flow __rte_unused) 3967 { 3968 } 3969 3970 static void 3971 flow_null_destroy(struct rte_eth_dev *dev __rte_unused, 3972 struct rte_flow *flow __rte_unused) 3973 { 3974 } 3975 3976 static int 3977 flow_null_query(struct rte_eth_dev *dev __rte_unused, 3978 struct rte_flow *flow __rte_unused, 3979 const struct rte_flow_action *actions __rte_unused, 3980 void *data __rte_unused, 3981 struct rte_flow_error *error) 3982 { 3983 return rte_flow_error_set(error, ENOTSUP, 3984 RTE_FLOW_ERROR_TYPE_UNSPECIFIED, NULL, NULL); 3985 } 3986 3987 static int 3988 flow_null_sync_domain(struct rte_eth_dev *dev __rte_unused, 3989 uint32_t domains __rte_unused, 3990 uint32_t flags __rte_unused) 3991 { 3992 return 0; 3993 } 3994 3995 int 3996 flow_null_get_aged_flows(struct rte_eth_dev *dev, 3997 void **context __rte_unused, 3998 uint32_t nb_contexts __rte_unused, 3999 struct rte_flow_error *error __rte_unused) 4000 { 4001 DRV_LOG(ERR, "port %u get aged flows is not supported.", 4002 dev->data->port_id); 4003 return -ENOTSUP; 4004 } 4005 4006 uint32_t 4007 flow_null_counter_allocate(struct rte_eth_dev *dev) 4008 { 4009 DRV_LOG(ERR, "port %u counter allocate is not supported.", 4010 dev->data->port_id); 4011 return 0; 4012 } 4013 4014 void 4015 flow_null_counter_free(struct rte_eth_dev *dev, 4016 uint32_t counter __rte_unused) 4017 { 4018 DRV_LOG(ERR, "port %u counter free is not supported.", 4019 dev->data->port_id); 4020 } 4021 4022 int 4023 flow_null_counter_query(struct rte_eth_dev *dev, 4024 uint32_t counter __rte_unused, 4025 bool clear __rte_unused, 4026 uint64_t *pkts __rte_unused, 4027 uint64_t *bytes __rte_unused, 4028 void **action __rte_unused) 4029 { 4030 DRV_LOG(ERR, "port %u counter query is not supported.", 4031 dev->data->port_id); 4032 return -ENOTSUP; 4033 } 4034 4035 /* Void driver to protect from null pointer reference. */ 4036 const struct mlx5_flow_driver_ops mlx5_flow_null_drv_ops = { 4037 .validate = flow_null_validate, 4038 .prepare = flow_null_prepare, 4039 .translate = flow_null_translate, 4040 .apply = flow_null_apply, 4041 .remove = flow_null_remove, 4042 .destroy = flow_null_destroy, 4043 .query = flow_null_query, 4044 .sync_domain = flow_null_sync_domain, 4045 .get_aged_flows = flow_null_get_aged_flows, 4046 .counter_alloc = flow_null_counter_allocate, 4047 .counter_free = flow_null_counter_free, 4048 .counter_query = flow_null_counter_query 4049 }; 4050 4051 /** 4052 * Select flow driver type according to flow attributes and device 4053 * configuration. 4054 * 4055 * @param[in] dev 4056 * Pointer to the dev structure. 4057 * @param[in] attr 4058 * Pointer to the flow attributes. 4059 * 4060 * @return 4061 * flow driver type, MLX5_FLOW_TYPE_MAX otherwise. 4062 */ 4063 static enum mlx5_flow_drv_type 4064 flow_get_drv_type(struct rte_eth_dev *dev, const struct rte_flow_attr *attr) 4065 { 4066 struct mlx5_priv *priv = dev->data->dev_private; 4067 /* The OS can determine first a specific flow type (DV, VERBS) */ 4068 enum mlx5_flow_drv_type type = mlx5_flow_os_get_type(); 4069 4070 if (type != MLX5_FLOW_TYPE_MAX) 4071 return type; 4072 /* 4073 * Currently when dv_flow_en == 2, only HW steering engine is 4074 * supported. New engines can also be chosen here if ready. 4075 */ 4076 if (priv->sh->config.dv_flow_en == 2) 4077 return MLX5_FLOW_TYPE_HW; 4078 if (!attr) 4079 return MLX5_FLOW_TYPE_MIN; 4080 /* If no OS specific type - continue with DV/VERBS selection */ 4081 if (attr->transfer && priv->sh->config.dv_esw_en) 4082 type = MLX5_FLOW_TYPE_DV; 4083 if (!attr->transfer) 4084 type = priv->sh->config.dv_flow_en ? MLX5_FLOW_TYPE_DV : 4085 MLX5_FLOW_TYPE_VERBS; 4086 return type; 4087 } 4088 4089 #define flow_get_drv_ops(type) flow_drv_ops[type] 4090 4091 /** 4092 * Flow driver validation API. This abstracts calling driver specific functions. 4093 * The type of flow driver is determined according to flow attributes. 4094 * 4095 * @param[in] dev 4096 * Pointer to the dev structure. 4097 * @param[in] attr 4098 * Pointer to the flow attributes. 4099 * @param[in] items 4100 * Pointer to the list of items. 4101 * @param[in] actions 4102 * Pointer to the list of actions. 4103 * @param[in] external 4104 * This flow rule is created by request external to PMD. 4105 * @param[in] hairpin 4106 * Number of hairpin TX actions, 0 means classic flow. 4107 * @param[out] error 4108 * Pointer to the error structure. 4109 * 4110 * @return 4111 * 0 on success, a negative errno value otherwise and rte_errno is set. 4112 */ 4113 static inline int 4114 flow_drv_validate(struct rte_eth_dev *dev, 4115 const struct rte_flow_attr *attr, 4116 const struct rte_flow_item items[], 4117 const struct rte_flow_action actions[], 4118 bool external, int hairpin, struct rte_flow_error *error) 4119 { 4120 const struct mlx5_flow_driver_ops *fops; 4121 enum mlx5_flow_drv_type type = flow_get_drv_type(dev, attr); 4122 4123 fops = flow_get_drv_ops(type); 4124 return fops->validate(dev, attr, items, actions, external, 4125 hairpin, error); 4126 } 4127 4128 /** 4129 * Flow driver preparation API. This abstracts calling driver specific 4130 * functions. Parent flow (rte_flow) should have driver type (drv_type). It 4131 * calculates the size of memory required for device flow, allocates the memory, 4132 * initializes the device flow and returns the pointer. 4133 * 4134 * @note 4135 * This function initializes device flow structure such as dv or verbs in 4136 * struct mlx5_flow. However, it is caller's responsibility to initialize the 4137 * rest. For example, adding returning device flow to flow->dev_flow list and 4138 * setting backward reference to the flow should be done out of this function. 4139 * layers field is not filled either. 4140 * 4141 * @param[in] dev 4142 * Pointer to the dev structure. 4143 * @param[in] attr 4144 * Pointer to the flow attributes. 4145 * @param[in] items 4146 * Pointer to the list of items. 4147 * @param[in] actions 4148 * Pointer to the list of actions. 4149 * @param[in] flow_idx 4150 * This memory pool index to the flow. 4151 * @param[out] error 4152 * Pointer to the error structure. 4153 * 4154 * @return 4155 * Pointer to device flow on success, otherwise NULL and rte_errno is set. 4156 */ 4157 static inline struct mlx5_flow * 4158 flow_drv_prepare(struct rte_eth_dev *dev, 4159 const struct rte_flow *flow, 4160 const struct rte_flow_attr *attr, 4161 const struct rte_flow_item items[], 4162 const struct rte_flow_action actions[], 4163 uint32_t flow_idx, 4164 struct rte_flow_error *error) 4165 { 4166 const struct mlx5_flow_driver_ops *fops; 4167 enum mlx5_flow_drv_type type = flow->drv_type; 4168 struct mlx5_flow *mlx5_flow = NULL; 4169 4170 MLX5_ASSERT(type > MLX5_FLOW_TYPE_MIN && type < MLX5_FLOW_TYPE_MAX); 4171 fops = flow_get_drv_ops(type); 4172 mlx5_flow = fops->prepare(dev, attr, items, actions, error); 4173 if (mlx5_flow) 4174 mlx5_flow->flow_idx = flow_idx; 4175 return mlx5_flow; 4176 } 4177 4178 /** 4179 * Flow driver translation API. This abstracts calling driver specific 4180 * functions. Parent flow (rte_flow) should have driver type (drv_type). It 4181 * translates a generic flow into a driver flow. flow_drv_prepare() must 4182 * precede. 4183 * 4184 * @note 4185 * dev_flow->layers could be filled as a result of parsing during translation 4186 * if needed by flow_drv_apply(). dev_flow->flow->actions can also be filled 4187 * if necessary. As a flow can have multiple dev_flows by RSS flow expansion, 4188 * flow->actions could be overwritten even though all the expanded dev_flows 4189 * have the same actions. 4190 * 4191 * @param[in] dev 4192 * Pointer to the rte dev structure. 4193 * @param[in, out] dev_flow 4194 * Pointer to the mlx5 flow. 4195 * @param[in] attr 4196 * Pointer to the flow attributes. 4197 * @param[in] items 4198 * Pointer to the list of items. 4199 * @param[in] actions 4200 * Pointer to the list of actions. 4201 * @param[out] error 4202 * Pointer to the error structure. 4203 * 4204 * @return 4205 * 0 on success, a negative errno value otherwise and rte_errno is set. 4206 */ 4207 static inline int 4208 flow_drv_translate(struct rte_eth_dev *dev, struct mlx5_flow *dev_flow, 4209 const struct rte_flow_attr *attr, 4210 const struct rte_flow_item items[], 4211 const struct rte_flow_action actions[], 4212 struct rte_flow_error *error) 4213 { 4214 const struct mlx5_flow_driver_ops *fops; 4215 enum mlx5_flow_drv_type type = dev_flow->flow->drv_type; 4216 4217 MLX5_ASSERT(type > MLX5_FLOW_TYPE_MIN && type < MLX5_FLOW_TYPE_MAX); 4218 fops = flow_get_drv_ops(type); 4219 return fops->translate(dev, dev_flow, attr, items, actions, error); 4220 } 4221 4222 /** 4223 * Flow driver apply API. This abstracts calling driver specific functions. 4224 * Parent flow (rte_flow) should have driver type (drv_type). It applies 4225 * translated driver flows on to device. flow_drv_translate() must precede. 4226 * 4227 * @param[in] dev 4228 * Pointer to Ethernet device structure. 4229 * @param[in, out] flow 4230 * Pointer to flow structure. 4231 * @param[out] error 4232 * Pointer to error structure. 4233 * 4234 * @return 4235 * 0 on success, a negative errno value otherwise and rte_errno is set. 4236 */ 4237 static inline int 4238 flow_drv_apply(struct rte_eth_dev *dev, struct rte_flow *flow, 4239 struct rte_flow_error *error) 4240 { 4241 const struct mlx5_flow_driver_ops *fops; 4242 enum mlx5_flow_drv_type type = flow->drv_type; 4243 4244 MLX5_ASSERT(type > MLX5_FLOW_TYPE_MIN && type < MLX5_FLOW_TYPE_MAX); 4245 fops = flow_get_drv_ops(type); 4246 return fops->apply(dev, flow, error); 4247 } 4248 4249 /** 4250 * Flow driver destroy API. This abstracts calling driver specific functions. 4251 * Parent flow (rte_flow) should have driver type (drv_type). It removes a flow 4252 * on device and releases resources of the flow. 4253 * 4254 * @param[in] dev 4255 * Pointer to Ethernet device. 4256 * @param[in, out] flow 4257 * Pointer to flow structure. 4258 */ 4259 static inline void 4260 flow_drv_destroy(struct rte_eth_dev *dev, struct rte_flow *flow) 4261 { 4262 const struct mlx5_flow_driver_ops *fops; 4263 enum mlx5_flow_drv_type type = flow->drv_type; 4264 4265 MLX5_ASSERT(type > MLX5_FLOW_TYPE_MIN && type < MLX5_FLOW_TYPE_MAX); 4266 fops = flow_get_drv_ops(type); 4267 fops->destroy(dev, flow); 4268 } 4269 4270 /** 4271 * Flow driver find RSS policy tbl API. This abstracts calling driver 4272 * specific functions. Parent flow (rte_flow) should have driver 4273 * type (drv_type). It will find the RSS policy table that has the rss_desc. 4274 * 4275 * @param[in] dev 4276 * Pointer to Ethernet device. 4277 * @param[in, out] flow 4278 * Pointer to flow structure. 4279 * @param[in] policy 4280 * Pointer to meter policy table. 4281 * @param[in] rss_desc 4282 * Pointer to rss_desc 4283 */ 4284 static struct mlx5_flow_meter_sub_policy * 4285 flow_drv_meter_sub_policy_rss_prepare(struct rte_eth_dev *dev, 4286 struct rte_flow *flow, 4287 struct mlx5_flow_meter_policy *policy, 4288 struct mlx5_flow_rss_desc *rss_desc[MLX5_MTR_RTE_COLORS]) 4289 { 4290 const struct mlx5_flow_driver_ops *fops; 4291 enum mlx5_flow_drv_type type = flow->drv_type; 4292 4293 MLX5_ASSERT(type > MLX5_FLOW_TYPE_MIN && type < MLX5_FLOW_TYPE_MAX); 4294 fops = flow_get_drv_ops(type); 4295 return fops->meter_sub_policy_rss_prepare(dev, policy, rss_desc); 4296 } 4297 4298 /** 4299 * Flow driver color tag rule API. This abstracts calling driver 4300 * specific functions. Parent flow (rte_flow) should have driver 4301 * type (drv_type). It will create the color tag rules in hierarchy meter. 4302 * 4303 * @param[in] dev 4304 * Pointer to Ethernet device. 4305 * @param[in, out] flow 4306 * Pointer to flow structure. 4307 * @param[in] fm 4308 * Pointer to flow meter structure. 4309 * @param[in] src_port 4310 * The src port this extra rule should use. 4311 * @param[in] item 4312 * The src port id match item. 4313 * @param[out] error 4314 * Pointer to error structure. 4315 */ 4316 static int 4317 flow_drv_mtr_hierarchy_rule_create(struct rte_eth_dev *dev, 4318 struct rte_flow *flow, 4319 struct mlx5_flow_meter_info *fm, 4320 int32_t src_port, 4321 const struct rte_flow_item *item, 4322 struct rte_flow_error *error) 4323 { 4324 const struct mlx5_flow_driver_ops *fops; 4325 enum mlx5_flow_drv_type type = flow->drv_type; 4326 4327 MLX5_ASSERT(type > MLX5_FLOW_TYPE_MIN && type < MLX5_FLOW_TYPE_MAX); 4328 fops = flow_get_drv_ops(type); 4329 return fops->meter_hierarchy_rule_create(dev, fm, 4330 src_port, item, error); 4331 } 4332 4333 /** 4334 * Get RSS action from the action list. 4335 * 4336 * @param[in] dev 4337 * Pointer to Ethernet device. 4338 * @param[in] actions 4339 * Pointer to the list of actions. 4340 * @param[in] flow 4341 * Parent flow structure pointer. 4342 * 4343 * @return 4344 * Pointer to the RSS action if exist, else return NULL. 4345 */ 4346 static const struct rte_flow_action_rss* 4347 flow_get_rss_action(struct rte_eth_dev *dev, 4348 const struct rte_flow_action actions[]) 4349 { 4350 struct mlx5_priv *priv = dev->data->dev_private; 4351 const struct rte_flow_action_rss *rss = NULL; 4352 struct mlx5_meter_policy_action_container *acg; 4353 struct mlx5_meter_policy_action_container *acy; 4354 4355 for (; actions->type != RTE_FLOW_ACTION_TYPE_END; actions++) { 4356 switch (actions->type) { 4357 case RTE_FLOW_ACTION_TYPE_RSS: 4358 rss = actions->conf; 4359 break; 4360 case RTE_FLOW_ACTION_TYPE_SAMPLE: 4361 { 4362 const struct rte_flow_action_sample *sample = 4363 actions->conf; 4364 const struct rte_flow_action *act = sample->actions; 4365 for (; act->type != RTE_FLOW_ACTION_TYPE_END; act++) 4366 if (act->type == RTE_FLOW_ACTION_TYPE_RSS) 4367 rss = act->conf; 4368 break; 4369 } 4370 case RTE_FLOW_ACTION_TYPE_METER: 4371 { 4372 uint32_t mtr_idx; 4373 struct mlx5_flow_meter_info *fm; 4374 struct mlx5_flow_meter_policy *policy; 4375 const struct rte_flow_action_meter *mtr = actions->conf; 4376 4377 fm = mlx5_flow_meter_find(priv, mtr->mtr_id, &mtr_idx); 4378 if (fm && !fm->def_policy) { 4379 policy = mlx5_flow_meter_policy_find(dev, 4380 fm->policy_id, NULL); 4381 MLX5_ASSERT(policy); 4382 if (policy->is_hierarchy) { 4383 policy = 4384 mlx5_flow_meter_hierarchy_get_final_policy(dev, 4385 policy); 4386 if (!policy) 4387 return NULL; 4388 } 4389 if (policy->is_rss) { 4390 acg = 4391 &policy->act_cnt[RTE_COLOR_GREEN]; 4392 acy = 4393 &policy->act_cnt[RTE_COLOR_YELLOW]; 4394 if (acg->fate_action == 4395 MLX5_FLOW_FATE_SHARED_RSS) 4396 rss = acg->rss->conf; 4397 else if (acy->fate_action == 4398 MLX5_FLOW_FATE_SHARED_RSS) 4399 rss = acy->rss->conf; 4400 } 4401 } 4402 break; 4403 } 4404 default: 4405 break; 4406 } 4407 } 4408 return rss; 4409 } 4410 4411 /** 4412 * Get ASO age action by index. 4413 * 4414 * @param[in] dev 4415 * Pointer to the Ethernet device structure. 4416 * @param[in] age_idx 4417 * Index to the ASO age action. 4418 * 4419 * @return 4420 * The specified ASO age action. 4421 */ 4422 struct mlx5_aso_age_action* 4423 flow_aso_age_get_by_idx(struct rte_eth_dev *dev, uint32_t age_idx) 4424 { 4425 uint16_t pool_idx = age_idx & UINT16_MAX; 4426 uint16_t offset = (age_idx >> 16) & UINT16_MAX; 4427 struct mlx5_priv *priv = dev->data->dev_private; 4428 struct mlx5_aso_age_mng *mng = priv->sh->aso_age_mng; 4429 struct mlx5_aso_age_pool *pool; 4430 4431 rte_rwlock_read_lock(&mng->resize_rwl); 4432 pool = mng->pools[pool_idx]; 4433 rte_rwlock_read_unlock(&mng->resize_rwl); 4434 return &pool->actions[offset - 1]; 4435 } 4436 4437 /* maps indirect action to translated direct in some actions array */ 4438 struct mlx5_translated_action_handle { 4439 struct rte_flow_action_handle *action; /**< Indirect action handle. */ 4440 int index; /**< Index in related array of rte_flow_action. */ 4441 }; 4442 4443 /** 4444 * Translates actions of type RTE_FLOW_ACTION_TYPE_INDIRECT to related 4445 * direct action if translation possible. 4446 * This functionality used to run same execution path for both direct and 4447 * indirect actions on flow create. All necessary preparations for indirect 4448 * action handling should be performed on *handle* actions list returned 4449 * from this call. 4450 * 4451 * @param[in] dev 4452 * Pointer to Ethernet device. 4453 * @param[in] actions 4454 * List of actions to translate. 4455 * @param[out] handle 4456 * List to store translated indirect action object handles. 4457 * @param[in, out] indir_n 4458 * Size of *handle* array. On return should be updated with number of 4459 * indirect actions retrieved from the *actions* list. 4460 * @param[out] translated_actions 4461 * List of actions where all indirect actions were translated to direct 4462 * if possible. NULL if no translation took place. 4463 * @param[out] error 4464 * Pointer to the error structure. 4465 * 4466 * @return 4467 * 0 on success, a negative errno value otherwise and rte_errno is set. 4468 */ 4469 static int 4470 flow_action_handles_translate(struct rte_eth_dev *dev, 4471 const struct rte_flow_action actions[], 4472 struct mlx5_translated_action_handle *handle, 4473 int *indir_n, 4474 struct rte_flow_action **translated_actions, 4475 struct rte_flow_error *error) 4476 { 4477 struct mlx5_priv *priv = dev->data->dev_private; 4478 struct rte_flow_action *translated = NULL; 4479 size_t actions_size; 4480 int n; 4481 int copied_n = 0; 4482 struct mlx5_translated_action_handle *handle_end = NULL; 4483 4484 for (n = 0; actions[n].type != RTE_FLOW_ACTION_TYPE_END; n++) { 4485 if (actions[n].type != RTE_FLOW_ACTION_TYPE_INDIRECT) 4486 continue; 4487 if (copied_n == *indir_n) { 4488 return rte_flow_error_set 4489 (error, EINVAL, RTE_FLOW_ERROR_TYPE_ACTION_NUM, 4490 NULL, "too many shared actions"); 4491 } 4492 rte_memcpy(&handle[copied_n].action, &actions[n].conf, 4493 sizeof(actions[n].conf)); 4494 handle[copied_n].index = n; 4495 copied_n++; 4496 } 4497 n++; 4498 *indir_n = copied_n; 4499 if (!copied_n) 4500 return 0; 4501 actions_size = sizeof(struct rte_flow_action) * n; 4502 translated = mlx5_malloc(MLX5_MEM_ZERO, actions_size, 0, SOCKET_ID_ANY); 4503 if (!translated) { 4504 rte_errno = ENOMEM; 4505 return -ENOMEM; 4506 } 4507 memcpy(translated, actions, actions_size); 4508 for (handle_end = handle + copied_n; handle < handle_end; handle++) { 4509 struct mlx5_shared_action_rss *shared_rss; 4510 uint32_t act_idx = (uint32_t)(uintptr_t)handle->action; 4511 uint32_t type = act_idx >> MLX5_INDIRECT_ACTION_TYPE_OFFSET; 4512 uint32_t idx = act_idx & 4513 ((1u << MLX5_INDIRECT_ACTION_TYPE_OFFSET) - 1); 4514 4515 switch (type) { 4516 case MLX5_INDIRECT_ACTION_TYPE_RSS: 4517 shared_rss = mlx5_ipool_get 4518 (priv->sh->ipool[MLX5_IPOOL_RSS_SHARED_ACTIONS], idx); 4519 translated[handle->index].type = 4520 RTE_FLOW_ACTION_TYPE_RSS; 4521 translated[handle->index].conf = 4522 &shared_rss->origin; 4523 break; 4524 case MLX5_INDIRECT_ACTION_TYPE_COUNT: 4525 translated[handle->index].type = 4526 (enum rte_flow_action_type) 4527 MLX5_RTE_FLOW_ACTION_TYPE_COUNT; 4528 translated[handle->index].conf = (void *)(uintptr_t)idx; 4529 break; 4530 case MLX5_INDIRECT_ACTION_TYPE_METER_MARK: 4531 translated[handle->index].type = 4532 (enum rte_flow_action_type) 4533 MLX5_RTE_FLOW_ACTION_TYPE_METER_MARK; 4534 translated[handle->index].conf = (void *)(uintptr_t)idx; 4535 break; 4536 case MLX5_INDIRECT_ACTION_TYPE_AGE: 4537 if (priv->sh->flow_hit_aso_en) { 4538 translated[handle->index].type = 4539 (enum rte_flow_action_type) 4540 MLX5_RTE_FLOW_ACTION_TYPE_AGE; 4541 translated[handle->index].conf = 4542 (void *)(uintptr_t)idx; 4543 break; 4544 } 4545 /* Fall-through */ 4546 case MLX5_INDIRECT_ACTION_TYPE_CT: 4547 if (priv->sh->ct_aso_en) { 4548 translated[handle->index].type = 4549 RTE_FLOW_ACTION_TYPE_CONNTRACK; 4550 translated[handle->index].conf = 4551 (void *)(uintptr_t)idx; 4552 break; 4553 } 4554 /* Fall-through */ 4555 default: 4556 mlx5_free(translated); 4557 return rte_flow_error_set 4558 (error, EINVAL, RTE_FLOW_ERROR_TYPE_ACTION, 4559 NULL, "invalid indirect action type"); 4560 } 4561 } 4562 *translated_actions = translated; 4563 return 0; 4564 } 4565 4566 /** 4567 * Get Shared RSS action from the action list. 4568 * 4569 * @param[in] dev 4570 * Pointer to Ethernet device. 4571 * @param[in] shared 4572 * Pointer to the list of actions. 4573 * @param[in] shared_n 4574 * Actions list length. 4575 * 4576 * @return 4577 * The MLX5 RSS action ID if exists, otherwise return 0. 4578 */ 4579 static uint32_t 4580 flow_get_shared_rss_action(struct rte_eth_dev *dev, 4581 struct mlx5_translated_action_handle *handle, 4582 int shared_n) 4583 { 4584 struct mlx5_translated_action_handle *handle_end; 4585 struct mlx5_priv *priv = dev->data->dev_private; 4586 struct mlx5_shared_action_rss *shared_rss; 4587 4588 4589 for (handle_end = handle + shared_n; handle < handle_end; handle++) { 4590 uint32_t act_idx = (uint32_t)(uintptr_t)handle->action; 4591 uint32_t type = act_idx >> MLX5_INDIRECT_ACTION_TYPE_OFFSET; 4592 uint32_t idx = act_idx & 4593 ((1u << MLX5_INDIRECT_ACTION_TYPE_OFFSET) - 1); 4594 switch (type) { 4595 case MLX5_INDIRECT_ACTION_TYPE_RSS: 4596 shared_rss = mlx5_ipool_get 4597 (priv->sh->ipool[MLX5_IPOOL_RSS_SHARED_ACTIONS], 4598 idx); 4599 __atomic_fetch_add(&shared_rss->refcnt, 1, 4600 __ATOMIC_RELAXED); 4601 return idx; 4602 default: 4603 break; 4604 } 4605 } 4606 return 0; 4607 } 4608 4609 static unsigned int 4610 find_graph_root(uint32_t rss_level) 4611 { 4612 return rss_level < 2 ? MLX5_EXPANSION_ROOT : 4613 MLX5_EXPANSION_ROOT_OUTER; 4614 } 4615 4616 /** 4617 * Get layer flags from the prefix flow. 4618 * 4619 * Some flows may be split to several subflows, the prefix subflow gets the 4620 * match items and the suffix sub flow gets the actions. 4621 * Some actions need the user defined match item flags to get the detail for 4622 * the action. 4623 * This function helps the suffix flow to get the item layer flags from prefix 4624 * subflow. 4625 * 4626 * @param[in] dev_flow 4627 * Pointer the created prefix subflow. 4628 * 4629 * @return 4630 * The layers get from prefix subflow. 4631 */ 4632 static inline uint64_t 4633 flow_get_prefix_layer_flags(struct mlx5_flow *dev_flow) 4634 { 4635 uint64_t layers = 0; 4636 4637 /* 4638 * Layers bits could be localization, but usually the compiler will 4639 * help to do the optimization work for source code. 4640 * If no decap actions, use the layers directly. 4641 */ 4642 if (!(dev_flow->act_flags & MLX5_FLOW_ACTION_DECAP)) 4643 return dev_flow->handle->layers; 4644 /* Convert L3 layers with decap action. */ 4645 if (dev_flow->handle->layers & MLX5_FLOW_LAYER_INNER_L3_IPV4) 4646 layers |= MLX5_FLOW_LAYER_OUTER_L3_IPV4; 4647 else if (dev_flow->handle->layers & MLX5_FLOW_LAYER_INNER_L3_IPV6) 4648 layers |= MLX5_FLOW_LAYER_OUTER_L3_IPV6; 4649 /* Convert L4 layers with decap action. */ 4650 if (dev_flow->handle->layers & MLX5_FLOW_LAYER_INNER_L4_TCP) 4651 layers |= MLX5_FLOW_LAYER_OUTER_L4_TCP; 4652 else if (dev_flow->handle->layers & MLX5_FLOW_LAYER_INNER_L4_UDP) 4653 layers |= MLX5_FLOW_LAYER_OUTER_L4_UDP; 4654 return layers; 4655 } 4656 4657 /** 4658 * Get metadata split action information. 4659 * 4660 * @param[in] actions 4661 * Pointer to the list of actions. 4662 * @param[out] qrss 4663 * Pointer to the return pointer. 4664 * @param[out] qrss_type 4665 * Pointer to the action type to return. RTE_FLOW_ACTION_TYPE_END is returned 4666 * if no QUEUE/RSS is found. 4667 * @param[out] encap_idx 4668 * Pointer to the index of the encap action if exists, otherwise the last 4669 * action index. 4670 * 4671 * @return 4672 * Total number of actions. 4673 */ 4674 static int 4675 flow_parse_metadata_split_actions_info(const struct rte_flow_action actions[], 4676 const struct rte_flow_action **qrss, 4677 int *encap_idx) 4678 { 4679 const struct rte_flow_action_raw_encap *raw_encap; 4680 int actions_n = 0; 4681 int raw_decap_idx = -1; 4682 4683 *encap_idx = -1; 4684 for (; actions->type != RTE_FLOW_ACTION_TYPE_END; actions++) { 4685 switch (actions->type) { 4686 case RTE_FLOW_ACTION_TYPE_VXLAN_ENCAP: 4687 case RTE_FLOW_ACTION_TYPE_NVGRE_ENCAP: 4688 *encap_idx = actions_n; 4689 break; 4690 case RTE_FLOW_ACTION_TYPE_RAW_DECAP: 4691 raw_decap_idx = actions_n; 4692 break; 4693 case RTE_FLOW_ACTION_TYPE_RAW_ENCAP: 4694 raw_encap = actions->conf; 4695 if (raw_encap->size > MLX5_ENCAPSULATION_DECISION_SIZE) 4696 *encap_idx = raw_decap_idx != -1 ? 4697 raw_decap_idx : actions_n; 4698 break; 4699 case RTE_FLOW_ACTION_TYPE_QUEUE: 4700 case RTE_FLOW_ACTION_TYPE_RSS: 4701 *qrss = actions; 4702 break; 4703 default: 4704 break; 4705 } 4706 actions_n++; 4707 } 4708 if (*encap_idx == -1) 4709 *encap_idx = actions_n; 4710 /* Count RTE_FLOW_ACTION_TYPE_END. */ 4711 return actions_n + 1; 4712 } 4713 4714 /** 4715 * Check if the action will change packet. 4716 * 4717 * @param dev 4718 * Pointer to Ethernet device. 4719 * @param[in] type 4720 * action type. 4721 * 4722 * @return 4723 * true if action will change packet, false otherwise. 4724 */ 4725 static bool flow_check_modify_action_type(struct rte_eth_dev *dev, 4726 enum rte_flow_action_type type) 4727 { 4728 struct mlx5_priv *priv = dev->data->dev_private; 4729 4730 switch (type) { 4731 case RTE_FLOW_ACTION_TYPE_SET_MAC_SRC: 4732 case RTE_FLOW_ACTION_TYPE_SET_MAC_DST: 4733 case RTE_FLOW_ACTION_TYPE_SET_IPV4_SRC: 4734 case RTE_FLOW_ACTION_TYPE_SET_IPV4_DST: 4735 case RTE_FLOW_ACTION_TYPE_SET_IPV6_SRC: 4736 case RTE_FLOW_ACTION_TYPE_SET_IPV6_DST: 4737 case RTE_FLOW_ACTION_TYPE_SET_TP_SRC: 4738 case RTE_FLOW_ACTION_TYPE_SET_TP_DST: 4739 case RTE_FLOW_ACTION_TYPE_DEC_TTL: 4740 case RTE_FLOW_ACTION_TYPE_SET_TTL: 4741 case RTE_FLOW_ACTION_TYPE_INC_TCP_SEQ: 4742 case RTE_FLOW_ACTION_TYPE_DEC_TCP_SEQ: 4743 case RTE_FLOW_ACTION_TYPE_INC_TCP_ACK: 4744 case RTE_FLOW_ACTION_TYPE_DEC_TCP_ACK: 4745 case RTE_FLOW_ACTION_TYPE_SET_IPV4_DSCP: 4746 case RTE_FLOW_ACTION_TYPE_SET_IPV6_DSCP: 4747 case RTE_FLOW_ACTION_TYPE_SET_META: 4748 case RTE_FLOW_ACTION_TYPE_SET_TAG: 4749 case RTE_FLOW_ACTION_TYPE_OF_POP_VLAN: 4750 case RTE_FLOW_ACTION_TYPE_OF_PUSH_VLAN: 4751 case RTE_FLOW_ACTION_TYPE_OF_SET_VLAN_VID: 4752 case RTE_FLOW_ACTION_TYPE_OF_SET_VLAN_PCP: 4753 case RTE_FLOW_ACTION_TYPE_VXLAN_ENCAP: 4754 case RTE_FLOW_ACTION_TYPE_VXLAN_DECAP: 4755 case RTE_FLOW_ACTION_TYPE_NVGRE_ENCAP: 4756 case RTE_FLOW_ACTION_TYPE_NVGRE_DECAP: 4757 case RTE_FLOW_ACTION_TYPE_RAW_ENCAP: 4758 case RTE_FLOW_ACTION_TYPE_RAW_DECAP: 4759 case RTE_FLOW_ACTION_TYPE_MODIFY_FIELD: 4760 return true; 4761 case RTE_FLOW_ACTION_TYPE_FLAG: 4762 case RTE_FLOW_ACTION_TYPE_MARK: 4763 if (priv->sh->config.dv_xmeta_en != MLX5_XMETA_MODE_LEGACY && 4764 priv->sh->config.dv_xmeta_en != MLX5_XMETA_MODE_META32_HWS) 4765 return true; 4766 else 4767 return false; 4768 default: 4769 return false; 4770 } 4771 } 4772 4773 /** 4774 * Check meter action from the action list. 4775 * 4776 * @param dev 4777 * Pointer to Ethernet device. 4778 * @param[in] actions 4779 * Pointer to the list of actions. 4780 * @param[out] has_mtr 4781 * Pointer to the meter exist flag. 4782 * @param[out] has_modify 4783 * Pointer to the flag showing there's packet change action. 4784 * @param[out] meter_id 4785 * Pointer to the meter id. 4786 * 4787 * @return 4788 * Total number of actions. 4789 */ 4790 static int 4791 flow_check_meter_action(struct rte_eth_dev *dev, 4792 const struct rte_flow_action actions[], 4793 bool *has_mtr, bool *has_modify, uint32_t *meter_id) 4794 { 4795 const struct rte_flow_action_meter *mtr = NULL; 4796 int actions_n = 0; 4797 4798 MLX5_ASSERT(has_mtr); 4799 *has_mtr = false; 4800 for (; actions->type != RTE_FLOW_ACTION_TYPE_END; actions++) { 4801 switch (actions->type) { 4802 case RTE_FLOW_ACTION_TYPE_METER: 4803 mtr = actions->conf; 4804 *meter_id = mtr->mtr_id; 4805 *has_mtr = true; 4806 break; 4807 default: 4808 break; 4809 } 4810 if (!*has_mtr) 4811 *has_modify |= flow_check_modify_action_type(dev, 4812 actions->type); 4813 actions_n++; 4814 } 4815 /* Count RTE_FLOW_ACTION_TYPE_END. */ 4816 return actions_n + 1; 4817 } 4818 4819 /** 4820 * Check if the flow should be split due to hairpin. 4821 * The reason for the split is that in current HW we can't 4822 * support encap and push-vlan on Rx, so if a flow contains 4823 * these actions we move it to Tx. 4824 * 4825 * @param dev 4826 * Pointer to Ethernet device. 4827 * @param[in] attr 4828 * Flow rule attributes. 4829 * @param[in] actions 4830 * Associated actions (list terminated by the END action). 4831 * 4832 * @return 4833 * > 0 the number of actions and the flow should be split, 4834 * 0 when no split required. 4835 */ 4836 static int 4837 flow_check_hairpin_split(struct rte_eth_dev *dev, 4838 const struct rte_flow_attr *attr, 4839 const struct rte_flow_action actions[]) 4840 { 4841 int queue_action = 0; 4842 int action_n = 0; 4843 int split = 0; 4844 int push_vlan = 0; 4845 const struct rte_flow_action_queue *queue; 4846 const struct rte_flow_action_rss *rss; 4847 const struct rte_flow_action_raw_encap *raw_encap; 4848 const struct rte_eth_hairpin_conf *conf; 4849 4850 if (!attr->ingress) 4851 return 0; 4852 for (; actions->type != RTE_FLOW_ACTION_TYPE_END; actions++) { 4853 if (actions->type == RTE_FLOW_ACTION_TYPE_OF_PUSH_VLAN) 4854 push_vlan = 1; 4855 switch (actions->type) { 4856 case RTE_FLOW_ACTION_TYPE_QUEUE: 4857 queue = actions->conf; 4858 if (queue == NULL) 4859 return 0; 4860 conf = mlx5_rxq_get_hairpin_conf(dev, queue->index); 4861 if (conf == NULL || conf->tx_explicit != 0) 4862 return 0; 4863 queue_action = 1; 4864 action_n++; 4865 break; 4866 case RTE_FLOW_ACTION_TYPE_RSS: 4867 rss = actions->conf; 4868 if (rss == NULL || rss->queue_num == 0) 4869 return 0; 4870 conf = mlx5_rxq_get_hairpin_conf(dev, rss->queue[0]); 4871 if (conf == NULL || conf->tx_explicit != 0) 4872 return 0; 4873 queue_action = 1; 4874 action_n++; 4875 break; 4876 case RTE_FLOW_ACTION_TYPE_VXLAN_ENCAP: 4877 case RTE_FLOW_ACTION_TYPE_NVGRE_ENCAP: 4878 case RTE_FLOW_ACTION_TYPE_OF_PUSH_VLAN: 4879 case RTE_FLOW_ACTION_TYPE_OF_SET_VLAN_PCP: 4880 split++; 4881 action_n++; 4882 break; 4883 case RTE_FLOW_ACTION_TYPE_OF_SET_VLAN_VID: 4884 if (push_vlan) 4885 split++; 4886 action_n++; 4887 break; 4888 case RTE_FLOW_ACTION_TYPE_RAW_ENCAP: 4889 raw_encap = actions->conf; 4890 if (raw_encap->size > MLX5_ENCAPSULATION_DECISION_SIZE) 4891 split++; 4892 action_n++; 4893 break; 4894 default: 4895 action_n++; 4896 break; 4897 } 4898 } 4899 if (split && queue_action) 4900 return action_n; 4901 return 0; 4902 } 4903 4904 /* Declare flow create/destroy prototype in advance. */ 4905 static uint32_t 4906 flow_list_create(struct rte_eth_dev *dev, enum mlx5_flow_type type, 4907 const struct rte_flow_attr *attr, 4908 const struct rte_flow_item items[], 4909 const struct rte_flow_action actions[], 4910 bool external, struct rte_flow_error *error); 4911 4912 static void 4913 flow_list_destroy(struct rte_eth_dev *dev, enum mlx5_flow_type type, 4914 uint32_t flow_idx); 4915 4916 int 4917 flow_dv_mreg_match_cb(void *tool_ctx __rte_unused, 4918 struct mlx5_list_entry *entry, void *cb_ctx) 4919 { 4920 struct mlx5_flow_cb_ctx *ctx = cb_ctx; 4921 struct mlx5_flow_mreg_copy_resource *mcp_res = 4922 container_of(entry, typeof(*mcp_res), hlist_ent); 4923 4924 return mcp_res->mark_id != *(uint32_t *)(ctx->data); 4925 } 4926 4927 struct mlx5_list_entry * 4928 flow_dv_mreg_create_cb(void *tool_ctx, void *cb_ctx) 4929 { 4930 struct rte_eth_dev *dev = tool_ctx; 4931 struct mlx5_priv *priv = dev->data->dev_private; 4932 struct mlx5_flow_cb_ctx *ctx = cb_ctx; 4933 struct mlx5_flow_mreg_copy_resource *mcp_res; 4934 struct rte_flow_error *error = ctx->error; 4935 uint32_t idx = 0; 4936 int ret; 4937 uint32_t mark_id = *(uint32_t *)(ctx->data); 4938 struct rte_flow_attr attr = { 4939 .group = MLX5_FLOW_MREG_CP_TABLE_GROUP, 4940 .ingress = 1, 4941 }; 4942 struct mlx5_rte_flow_item_tag tag_spec = { 4943 .data = mark_id, 4944 }; 4945 struct rte_flow_item items[] = { 4946 [1] = { .type = RTE_FLOW_ITEM_TYPE_END, }, 4947 }; 4948 struct rte_flow_action_mark ftag = { 4949 .id = mark_id, 4950 }; 4951 struct mlx5_flow_action_copy_mreg cp_mreg = { 4952 .dst = REG_B, 4953 .src = REG_NON, 4954 }; 4955 struct rte_flow_action_jump jump = { 4956 .group = MLX5_FLOW_MREG_ACT_TABLE_GROUP, 4957 }; 4958 struct rte_flow_action actions[] = { 4959 [3] = { .type = RTE_FLOW_ACTION_TYPE_END, }, 4960 }; 4961 4962 /* Fill the register fields in the flow. */ 4963 ret = mlx5_flow_get_reg_id(dev, MLX5_FLOW_MARK, 0, error); 4964 if (ret < 0) 4965 return NULL; 4966 tag_spec.id = ret; 4967 ret = mlx5_flow_get_reg_id(dev, MLX5_METADATA_RX, 0, error); 4968 if (ret < 0) 4969 return NULL; 4970 cp_mreg.src = ret; 4971 /* Provide the full width of FLAG specific value. */ 4972 if (mark_id == (priv->sh->dv_regc0_mask & MLX5_FLOW_MARK_DEFAULT)) 4973 tag_spec.data = MLX5_FLOW_MARK_DEFAULT; 4974 /* Build a new flow. */ 4975 if (mark_id != MLX5_DEFAULT_COPY_ID) { 4976 items[0] = (struct rte_flow_item){ 4977 .type = (enum rte_flow_item_type) 4978 MLX5_RTE_FLOW_ITEM_TYPE_TAG, 4979 .spec = &tag_spec, 4980 }; 4981 items[1] = (struct rte_flow_item){ 4982 .type = RTE_FLOW_ITEM_TYPE_END, 4983 }; 4984 actions[0] = (struct rte_flow_action){ 4985 .type = (enum rte_flow_action_type) 4986 MLX5_RTE_FLOW_ACTION_TYPE_MARK, 4987 .conf = &ftag, 4988 }; 4989 actions[1] = (struct rte_flow_action){ 4990 .type = (enum rte_flow_action_type) 4991 MLX5_RTE_FLOW_ACTION_TYPE_COPY_MREG, 4992 .conf = &cp_mreg, 4993 }; 4994 actions[2] = (struct rte_flow_action){ 4995 .type = RTE_FLOW_ACTION_TYPE_JUMP, 4996 .conf = &jump, 4997 }; 4998 actions[3] = (struct rte_flow_action){ 4999 .type = RTE_FLOW_ACTION_TYPE_END, 5000 }; 5001 } else { 5002 /* Default rule, wildcard match. */ 5003 attr.priority = MLX5_FLOW_LOWEST_PRIO_INDICATOR; 5004 items[0] = (struct rte_flow_item){ 5005 .type = RTE_FLOW_ITEM_TYPE_END, 5006 }; 5007 actions[0] = (struct rte_flow_action){ 5008 .type = (enum rte_flow_action_type) 5009 MLX5_RTE_FLOW_ACTION_TYPE_COPY_MREG, 5010 .conf = &cp_mreg, 5011 }; 5012 actions[1] = (struct rte_flow_action){ 5013 .type = RTE_FLOW_ACTION_TYPE_JUMP, 5014 .conf = &jump, 5015 }; 5016 actions[2] = (struct rte_flow_action){ 5017 .type = RTE_FLOW_ACTION_TYPE_END, 5018 }; 5019 } 5020 /* Build a new entry. */ 5021 mcp_res = mlx5_ipool_zmalloc(priv->sh->ipool[MLX5_IPOOL_MCP], &idx); 5022 if (!mcp_res) { 5023 rte_errno = ENOMEM; 5024 return NULL; 5025 } 5026 mcp_res->idx = idx; 5027 mcp_res->mark_id = mark_id; 5028 /* 5029 * The copy Flows are not included in any list. There 5030 * ones are referenced from other Flows and can not 5031 * be applied, removed, deleted in arbitrary order 5032 * by list traversing. 5033 */ 5034 mcp_res->rix_flow = flow_list_create(dev, MLX5_FLOW_TYPE_MCP, 5035 &attr, items, actions, false, error); 5036 if (!mcp_res->rix_flow) { 5037 mlx5_ipool_free(priv->sh->ipool[MLX5_IPOOL_MCP], idx); 5038 return NULL; 5039 } 5040 return &mcp_res->hlist_ent; 5041 } 5042 5043 struct mlx5_list_entry * 5044 flow_dv_mreg_clone_cb(void *tool_ctx, struct mlx5_list_entry *oentry, 5045 void *cb_ctx __rte_unused) 5046 { 5047 struct rte_eth_dev *dev = tool_ctx; 5048 struct mlx5_priv *priv = dev->data->dev_private; 5049 struct mlx5_flow_mreg_copy_resource *mcp_res; 5050 uint32_t idx = 0; 5051 5052 mcp_res = mlx5_ipool_malloc(priv->sh->ipool[MLX5_IPOOL_MCP], &idx); 5053 if (!mcp_res) { 5054 rte_errno = ENOMEM; 5055 return NULL; 5056 } 5057 memcpy(mcp_res, oentry, sizeof(*mcp_res)); 5058 mcp_res->idx = idx; 5059 return &mcp_res->hlist_ent; 5060 } 5061 5062 void 5063 flow_dv_mreg_clone_free_cb(void *tool_ctx, struct mlx5_list_entry *entry) 5064 { 5065 struct mlx5_flow_mreg_copy_resource *mcp_res = 5066 container_of(entry, typeof(*mcp_res), hlist_ent); 5067 struct rte_eth_dev *dev = tool_ctx; 5068 struct mlx5_priv *priv = dev->data->dev_private; 5069 5070 mlx5_ipool_free(priv->sh->ipool[MLX5_IPOOL_MCP], mcp_res->idx); 5071 } 5072 5073 /** 5074 * Add a flow of copying flow metadata registers in RX_CP_TBL. 5075 * 5076 * As mark_id is unique, if there's already a registered flow for the mark_id, 5077 * return by increasing the reference counter of the resource. Otherwise, create 5078 * the resource (mcp_res) and flow. 5079 * 5080 * Flow looks like, 5081 * - If ingress port is ANY and reg_c[1] is mark_id, 5082 * flow_tag := mark_id, reg_b := reg_c[0] and jump to RX_ACT_TBL. 5083 * 5084 * For default flow (zero mark_id), flow is like, 5085 * - If ingress port is ANY, 5086 * reg_b := reg_c[0] and jump to RX_ACT_TBL. 5087 * 5088 * @param dev 5089 * Pointer to Ethernet device. 5090 * @param mark_id 5091 * ID of MARK action, zero means default flow for META. 5092 * @param[out] error 5093 * Perform verbose error reporting if not NULL. 5094 * 5095 * @return 5096 * Associated resource on success, NULL otherwise and rte_errno is set. 5097 */ 5098 static struct mlx5_flow_mreg_copy_resource * 5099 flow_mreg_add_copy_action(struct rte_eth_dev *dev, uint32_t mark_id, 5100 struct rte_flow_error *error) 5101 { 5102 struct mlx5_priv *priv = dev->data->dev_private; 5103 struct mlx5_list_entry *entry; 5104 struct mlx5_flow_cb_ctx ctx = { 5105 .dev = dev, 5106 .error = error, 5107 .data = &mark_id, 5108 }; 5109 5110 /* Check if already registered. */ 5111 MLX5_ASSERT(priv->mreg_cp_tbl); 5112 entry = mlx5_hlist_register(priv->mreg_cp_tbl, mark_id, &ctx); 5113 if (!entry) 5114 return NULL; 5115 return container_of(entry, struct mlx5_flow_mreg_copy_resource, 5116 hlist_ent); 5117 } 5118 5119 void 5120 flow_dv_mreg_remove_cb(void *tool_ctx, struct mlx5_list_entry *entry) 5121 { 5122 struct mlx5_flow_mreg_copy_resource *mcp_res = 5123 container_of(entry, typeof(*mcp_res), hlist_ent); 5124 struct rte_eth_dev *dev = tool_ctx; 5125 struct mlx5_priv *priv = dev->data->dev_private; 5126 5127 MLX5_ASSERT(mcp_res->rix_flow); 5128 flow_list_destroy(dev, MLX5_FLOW_TYPE_MCP, mcp_res->rix_flow); 5129 mlx5_ipool_free(priv->sh->ipool[MLX5_IPOOL_MCP], mcp_res->idx); 5130 } 5131 5132 /** 5133 * Release flow in RX_CP_TBL. 5134 * 5135 * @param dev 5136 * Pointer to Ethernet device. 5137 * @flow 5138 * Parent flow for wich copying is provided. 5139 */ 5140 static void 5141 flow_mreg_del_copy_action(struct rte_eth_dev *dev, 5142 struct rte_flow *flow) 5143 { 5144 struct mlx5_flow_mreg_copy_resource *mcp_res; 5145 struct mlx5_priv *priv = dev->data->dev_private; 5146 5147 if (!flow->rix_mreg_copy) 5148 return; 5149 mcp_res = mlx5_ipool_get(priv->sh->ipool[MLX5_IPOOL_MCP], 5150 flow->rix_mreg_copy); 5151 if (!mcp_res || !priv->mreg_cp_tbl) 5152 return; 5153 MLX5_ASSERT(mcp_res->rix_flow); 5154 mlx5_hlist_unregister(priv->mreg_cp_tbl, &mcp_res->hlist_ent); 5155 flow->rix_mreg_copy = 0; 5156 } 5157 5158 /** 5159 * Remove the default copy action from RX_CP_TBL. 5160 * 5161 * This functions is called in the mlx5_dev_start(). No thread safe 5162 * is guaranteed. 5163 * 5164 * @param dev 5165 * Pointer to Ethernet device. 5166 */ 5167 static void 5168 flow_mreg_del_default_copy_action(struct rte_eth_dev *dev) 5169 { 5170 struct mlx5_list_entry *entry; 5171 struct mlx5_priv *priv = dev->data->dev_private; 5172 struct mlx5_flow_cb_ctx ctx; 5173 uint32_t mark_id; 5174 5175 /* Check if default flow is registered. */ 5176 if (!priv->mreg_cp_tbl) 5177 return; 5178 mark_id = MLX5_DEFAULT_COPY_ID; 5179 ctx.data = &mark_id; 5180 entry = mlx5_hlist_lookup(priv->mreg_cp_tbl, mark_id, &ctx); 5181 if (!entry) 5182 return; 5183 mlx5_hlist_unregister(priv->mreg_cp_tbl, entry); 5184 } 5185 5186 /** 5187 * Add the default copy action in RX_CP_TBL. 5188 * 5189 * This functions is called in the mlx5_dev_start(). No thread safe 5190 * is guaranteed. 5191 * 5192 * @param dev 5193 * Pointer to Ethernet device. 5194 * @param[out] error 5195 * Perform verbose error reporting if not NULL. 5196 * 5197 * @return 5198 * 0 for success, negative value otherwise and rte_errno is set. 5199 */ 5200 static int 5201 flow_mreg_add_default_copy_action(struct rte_eth_dev *dev, 5202 struct rte_flow_error *error) 5203 { 5204 struct mlx5_priv *priv = dev->data->dev_private; 5205 struct mlx5_flow_mreg_copy_resource *mcp_res; 5206 struct mlx5_flow_cb_ctx ctx; 5207 uint32_t mark_id; 5208 5209 /* Check whether extensive metadata feature is engaged. */ 5210 if (!priv->sh->config.dv_flow_en || 5211 priv->sh->config.dv_xmeta_en == MLX5_XMETA_MODE_LEGACY || 5212 !mlx5_flow_ext_mreg_supported(dev) || 5213 !priv->sh->dv_regc0_mask) 5214 return 0; 5215 /* 5216 * Add default mreg copy flow may be called multiple time, but 5217 * only be called once in stop. Avoid register it twice. 5218 */ 5219 mark_id = MLX5_DEFAULT_COPY_ID; 5220 ctx.data = &mark_id; 5221 if (mlx5_hlist_lookup(priv->mreg_cp_tbl, mark_id, &ctx)) 5222 return 0; 5223 mcp_res = flow_mreg_add_copy_action(dev, mark_id, error); 5224 if (!mcp_res) 5225 return -rte_errno; 5226 return 0; 5227 } 5228 5229 /** 5230 * Add a flow of copying flow metadata registers in RX_CP_TBL. 5231 * 5232 * All the flow having Q/RSS action should be split by 5233 * flow_mreg_split_qrss_prep() to pass by RX_CP_TBL. A flow in the RX_CP_TBL 5234 * performs the following, 5235 * - CQE->flow_tag := reg_c[1] (MARK) 5236 * - CQE->flow_table_metadata (reg_b) := reg_c[0] (META) 5237 * As CQE's flow_tag is not a register, it can't be simply copied from reg_c[1] 5238 * but there should be a flow per each MARK ID set by MARK action. 5239 * 5240 * For the aforementioned reason, if there's a MARK action in flow's action 5241 * list, a corresponding flow should be added to the RX_CP_TBL in order to copy 5242 * the MARK ID to CQE's flow_tag like, 5243 * - If reg_c[1] is mark_id, 5244 * flow_tag := mark_id, reg_b := reg_c[0] and jump to RX_ACT_TBL. 5245 * 5246 * For SET_META action which stores value in reg_c[0], as the destination is 5247 * also a flow metadata register (reg_b), adding a default flow is enough. Zero 5248 * MARK ID means the default flow. The default flow looks like, 5249 * - For all flow, reg_b := reg_c[0] and jump to RX_ACT_TBL. 5250 * 5251 * @param dev 5252 * Pointer to Ethernet device. 5253 * @param flow 5254 * Pointer to flow structure. 5255 * @param[in] actions 5256 * Pointer to the list of actions. 5257 * @param[out] error 5258 * Perform verbose error reporting if not NULL. 5259 * 5260 * @return 5261 * 0 on success, negative value otherwise and rte_errno is set. 5262 */ 5263 static int 5264 flow_mreg_update_copy_table(struct rte_eth_dev *dev, 5265 struct rte_flow *flow, 5266 const struct rte_flow_action *actions, 5267 struct rte_flow_error *error) 5268 { 5269 struct mlx5_priv *priv = dev->data->dev_private; 5270 struct mlx5_sh_config *config = &priv->sh->config; 5271 struct mlx5_flow_mreg_copy_resource *mcp_res; 5272 const struct rte_flow_action_mark *mark; 5273 5274 /* Check whether extensive metadata feature is engaged. */ 5275 if (!config->dv_flow_en || 5276 config->dv_xmeta_en == MLX5_XMETA_MODE_LEGACY || 5277 !mlx5_flow_ext_mreg_supported(dev) || 5278 !priv->sh->dv_regc0_mask) 5279 return 0; 5280 /* Find MARK action. */ 5281 for (; actions->type != RTE_FLOW_ACTION_TYPE_END; actions++) { 5282 switch (actions->type) { 5283 case RTE_FLOW_ACTION_TYPE_FLAG: 5284 mcp_res = flow_mreg_add_copy_action 5285 (dev, MLX5_FLOW_MARK_DEFAULT, error); 5286 if (!mcp_res) 5287 return -rte_errno; 5288 flow->rix_mreg_copy = mcp_res->idx; 5289 return 0; 5290 case RTE_FLOW_ACTION_TYPE_MARK: 5291 mark = (const struct rte_flow_action_mark *) 5292 actions->conf; 5293 mcp_res = 5294 flow_mreg_add_copy_action(dev, mark->id, error); 5295 if (!mcp_res) 5296 return -rte_errno; 5297 flow->rix_mreg_copy = mcp_res->idx; 5298 return 0; 5299 default: 5300 break; 5301 } 5302 } 5303 return 0; 5304 } 5305 5306 #define MLX5_MAX_SPLIT_ACTIONS 24 5307 #define MLX5_MAX_SPLIT_ITEMS 24 5308 5309 /** 5310 * Split the hairpin flow. 5311 * Since HW can't support encap and push-vlan on Rx, we move these 5312 * actions to Tx. 5313 * If the count action is after the encap then we also 5314 * move the count action. in this case the count will also measure 5315 * the outer bytes. 5316 * 5317 * @param dev 5318 * Pointer to Ethernet device. 5319 * @param[in] actions 5320 * Associated actions (list terminated by the END action). 5321 * @param[out] actions_rx 5322 * Rx flow actions. 5323 * @param[out] actions_tx 5324 * Tx flow actions.. 5325 * @param[out] pattern_tx 5326 * The pattern items for the Tx flow. 5327 * @param[out] flow_id 5328 * The flow ID connected to this flow. 5329 * 5330 * @return 5331 * 0 on success. 5332 */ 5333 static int 5334 flow_hairpin_split(struct rte_eth_dev *dev, 5335 const struct rte_flow_action actions[], 5336 struct rte_flow_action actions_rx[], 5337 struct rte_flow_action actions_tx[], 5338 struct rte_flow_item pattern_tx[], 5339 uint32_t flow_id) 5340 { 5341 const struct rte_flow_action_raw_encap *raw_encap; 5342 const struct rte_flow_action_raw_decap *raw_decap; 5343 struct mlx5_rte_flow_action_set_tag *set_tag; 5344 struct rte_flow_action *tag_action; 5345 struct mlx5_rte_flow_item_tag *tag_item; 5346 struct rte_flow_item *item; 5347 char *addr; 5348 int push_vlan = 0; 5349 int encap = 0; 5350 5351 for (; actions->type != RTE_FLOW_ACTION_TYPE_END; actions++) { 5352 if (actions->type == RTE_FLOW_ACTION_TYPE_OF_PUSH_VLAN) 5353 push_vlan = 1; 5354 switch (actions->type) { 5355 case RTE_FLOW_ACTION_TYPE_VXLAN_ENCAP: 5356 case RTE_FLOW_ACTION_TYPE_NVGRE_ENCAP: 5357 case RTE_FLOW_ACTION_TYPE_OF_PUSH_VLAN: 5358 case RTE_FLOW_ACTION_TYPE_OF_SET_VLAN_PCP: 5359 rte_memcpy(actions_tx, actions, 5360 sizeof(struct rte_flow_action)); 5361 actions_tx++; 5362 break; 5363 case RTE_FLOW_ACTION_TYPE_OF_SET_VLAN_VID: 5364 if (push_vlan) { 5365 rte_memcpy(actions_tx, actions, 5366 sizeof(struct rte_flow_action)); 5367 actions_tx++; 5368 } else { 5369 rte_memcpy(actions_rx, actions, 5370 sizeof(struct rte_flow_action)); 5371 actions_rx++; 5372 } 5373 break; 5374 case RTE_FLOW_ACTION_TYPE_COUNT: 5375 if (encap) { 5376 rte_memcpy(actions_tx, actions, 5377 sizeof(struct rte_flow_action)); 5378 actions_tx++; 5379 } else { 5380 rte_memcpy(actions_rx, actions, 5381 sizeof(struct rte_flow_action)); 5382 actions_rx++; 5383 } 5384 break; 5385 case RTE_FLOW_ACTION_TYPE_RAW_ENCAP: 5386 raw_encap = actions->conf; 5387 if (raw_encap->size > MLX5_ENCAPSULATION_DECISION_SIZE) { 5388 memcpy(actions_tx, actions, 5389 sizeof(struct rte_flow_action)); 5390 actions_tx++; 5391 encap = 1; 5392 } else { 5393 rte_memcpy(actions_rx, actions, 5394 sizeof(struct rte_flow_action)); 5395 actions_rx++; 5396 } 5397 break; 5398 case RTE_FLOW_ACTION_TYPE_RAW_DECAP: 5399 raw_decap = actions->conf; 5400 if (raw_decap->size < MLX5_ENCAPSULATION_DECISION_SIZE) { 5401 memcpy(actions_tx, actions, 5402 sizeof(struct rte_flow_action)); 5403 actions_tx++; 5404 } else { 5405 rte_memcpy(actions_rx, actions, 5406 sizeof(struct rte_flow_action)); 5407 actions_rx++; 5408 } 5409 break; 5410 default: 5411 rte_memcpy(actions_rx, actions, 5412 sizeof(struct rte_flow_action)); 5413 actions_rx++; 5414 break; 5415 } 5416 } 5417 /* Add set meta action and end action for the Rx flow. */ 5418 tag_action = actions_rx; 5419 tag_action->type = (enum rte_flow_action_type) 5420 MLX5_RTE_FLOW_ACTION_TYPE_TAG; 5421 actions_rx++; 5422 rte_memcpy(actions_rx, actions, sizeof(struct rte_flow_action)); 5423 actions_rx++; 5424 set_tag = (void *)actions_rx; 5425 *set_tag = (struct mlx5_rte_flow_action_set_tag) { 5426 .id = mlx5_flow_get_reg_id(dev, MLX5_HAIRPIN_RX, 0, NULL), 5427 .data = flow_id, 5428 }; 5429 MLX5_ASSERT(set_tag->id > REG_NON); 5430 tag_action->conf = set_tag; 5431 /* Create Tx item list. */ 5432 rte_memcpy(actions_tx, actions, sizeof(struct rte_flow_action)); 5433 addr = (void *)&pattern_tx[2]; 5434 item = pattern_tx; 5435 item->type = (enum rte_flow_item_type) 5436 MLX5_RTE_FLOW_ITEM_TYPE_TAG; 5437 tag_item = (void *)addr; 5438 tag_item->data = flow_id; 5439 tag_item->id = mlx5_flow_get_reg_id(dev, MLX5_HAIRPIN_TX, 0, NULL); 5440 MLX5_ASSERT(set_tag->id > REG_NON); 5441 item->spec = tag_item; 5442 addr += sizeof(struct mlx5_rte_flow_item_tag); 5443 tag_item = (void *)addr; 5444 tag_item->data = UINT32_MAX; 5445 tag_item->id = UINT16_MAX; 5446 item->mask = tag_item; 5447 item->last = NULL; 5448 item++; 5449 item->type = RTE_FLOW_ITEM_TYPE_END; 5450 return 0; 5451 } 5452 5453 /** 5454 * The last stage of splitting chain, just creates the subflow 5455 * without any modification. 5456 * 5457 * @param[in] dev 5458 * Pointer to Ethernet device. 5459 * @param[in] flow 5460 * Parent flow structure pointer. 5461 * @param[in, out] sub_flow 5462 * Pointer to return the created subflow, may be NULL. 5463 * @param[in] attr 5464 * Flow rule attributes. 5465 * @param[in] items 5466 * Pattern specification (list terminated by the END pattern item). 5467 * @param[in] actions 5468 * Associated actions (list terminated by the END action). 5469 * @param[in] flow_split_info 5470 * Pointer to flow split info structure. 5471 * @param[out] error 5472 * Perform verbose error reporting if not NULL. 5473 * @return 5474 * 0 on success, negative value otherwise 5475 */ 5476 static int 5477 flow_create_split_inner(struct rte_eth_dev *dev, 5478 struct rte_flow *flow, 5479 struct mlx5_flow **sub_flow, 5480 const struct rte_flow_attr *attr, 5481 const struct rte_flow_item items[], 5482 const struct rte_flow_action actions[], 5483 struct mlx5_flow_split_info *flow_split_info, 5484 struct rte_flow_error *error) 5485 { 5486 struct mlx5_flow *dev_flow; 5487 struct mlx5_flow_workspace *wks = mlx5_flow_get_thread_workspace(); 5488 5489 dev_flow = flow_drv_prepare(dev, flow, attr, items, actions, 5490 flow_split_info->flow_idx, error); 5491 if (!dev_flow) 5492 return -rte_errno; 5493 dev_flow->flow = flow; 5494 dev_flow->external = flow_split_info->external; 5495 dev_flow->skip_scale = flow_split_info->skip_scale; 5496 /* Subflow object was created, we must include one in the list. */ 5497 SILIST_INSERT(&flow->dev_handles, dev_flow->handle_idx, 5498 dev_flow->handle, next); 5499 /* 5500 * If dev_flow is as one of the suffix flow, some actions in suffix 5501 * flow may need some user defined item layer flags, and pass the 5502 * Metadata rxq mark flag to suffix flow as well. 5503 */ 5504 if (flow_split_info->prefix_layers) 5505 dev_flow->handle->layers = flow_split_info->prefix_layers; 5506 if (flow_split_info->prefix_mark) { 5507 MLX5_ASSERT(wks); 5508 wks->mark = 1; 5509 } 5510 if (sub_flow) 5511 *sub_flow = dev_flow; 5512 #ifdef HAVE_IBV_FLOW_DV_SUPPORT 5513 dev_flow->dv.table_id = flow_split_info->table_id; 5514 #endif 5515 return flow_drv_translate(dev, dev_flow, attr, items, actions, error); 5516 } 5517 5518 /** 5519 * Get the sub policy of a meter. 5520 * 5521 * @param[in] dev 5522 * Pointer to Ethernet device. 5523 * @param[in] flow 5524 * Parent flow structure pointer. 5525 * @param wks 5526 * Pointer to thread flow work space. 5527 * @param[in] attr 5528 * Flow rule attributes. 5529 * @param[in] items 5530 * Pattern specification (list terminated by the END pattern item). 5531 * @param[out] error 5532 * Perform verbose error reporting if not NULL. 5533 * 5534 * @return 5535 * Pointer to the meter sub policy, NULL otherwise and rte_errno is set. 5536 */ 5537 static struct mlx5_flow_meter_sub_policy * 5538 get_meter_sub_policy(struct rte_eth_dev *dev, 5539 struct rte_flow *flow, 5540 struct mlx5_flow_workspace *wks, 5541 const struct rte_flow_attr *attr, 5542 const struct rte_flow_item items[], 5543 struct rte_flow_error *error) 5544 { 5545 struct mlx5_flow_meter_policy *policy; 5546 struct mlx5_flow_meter_policy *final_policy; 5547 struct mlx5_flow_meter_sub_policy *sub_policy = NULL; 5548 5549 policy = wks->policy; 5550 final_policy = policy->is_hierarchy ? wks->final_policy : policy; 5551 if (final_policy->is_rss || final_policy->is_queue) { 5552 struct mlx5_flow_rss_desc rss_desc_v[MLX5_MTR_RTE_COLORS]; 5553 struct mlx5_flow_rss_desc *rss_desc[MLX5_MTR_RTE_COLORS] = {0}; 5554 uint32_t i; 5555 5556 /* 5557 * This is a tmp dev_flow, 5558 * no need to register any matcher for it in translate. 5559 */ 5560 wks->skip_matcher_reg = 1; 5561 for (i = 0; i < MLX5_MTR_RTE_COLORS; i++) { 5562 struct mlx5_flow dev_flow = {0}; 5563 struct mlx5_flow_handle dev_handle = { {0} }; 5564 uint8_t fate = final_policy->act_cnt[i].fate_action; 5565 5566 if (fate == MLX5_FLOW_FATE_SHARED_RSS) { 5567 const struct rte_flow_action_rss *rss_act = 5568 final_policy->act_cnt[i].rss->conf; 5569 struct rte_flow_action rss_actions[2] = { 5570 [0] = { 5571 .type = RTE_FLOW_ACTION_TYPE_RSS, 5572 .conf = rss_act, 5573 }, 5574 [1] = { 5575 .type = RTE_FLOW_ACTION_TYPE_END, 5576 .conf = NULL, 5577 } 5578 }; 5579 5580 dev_flow.handle = &dev_handle; 5581 dev_flow.ingress = attr->ingress; 5582 dev_flow.flow = flow; 5583 dev_flow.external = 0; 5584 #ifdef HAVE_IBV_FLOW_DV_SUPPORT 5585 dev_flow.dv.transfer = attr->transfer; 5586 #endif 5587 /** 5588 * Translate RSS action to get rss hash fields. 5589 */ 5590 if (flow_drv_translate(dev, &dev_flow, attr, 5591 items, rss_actions, error)) 5592 goto exit; 5593 rss_desc_v[i] = wks->rss_desc; 5594 rss_desc_v[i].symmetric_hash_function = 5595 dev_flow.symmetric_hash_function; 5596 rss_desc_v[i].key_len = MLX5_RSS_HASH_KEY_LEN; 5597 rss_desc_v[i].hash_fields = 5598 dev_flow.hash_fields; 5599 rss_desc_v[i].queue_num = 5600 rss_desc_v[i].hash_fields ? 5601 rss_desc_v[i].queue_num : 1; 5602 rss_desc_v[i].tunnel = 5603 !!(dev_flow.handle->layers & 5604 MLX5_FLOW_LAYER_TUNNEL); 5605 /* Use the RSS queues in the containers. */ 5606 rss_desc_v[i].queue = 5607 (uint16_t *)(uintptr_t)rss_act->queue; 5608 rss_desc[i] = &rss_desc_v[i]; 5609 } else if (fate == MLX5_FLOW_FATE_QUEUE) { 5610 /* This is queue action. */ 5611 rss_desc_v[i] = wks->rss_desc; 5612 rss_desc_v[i].key_len = 0; 5613 rss_desc_v[i].hash_fields = 0; 5614 rss_desc_v[i].queue = 5615 &final_policy->act_cnt[i].queue; 5616 rss_desc_v[i].queue_num = 1; 5617 rss_desc[i] = &rss_desc_v[i]; 5618 } else { 5619 rss_desc[i] = NULL; 5620 } 5621 } 5622 sub_policy = flow_drv_meter_sub_policy_rss_prepare(dev, 5623 flow, policy, rss_desc); 5624 } else { 5625 enum mlx5_meter_domain mtr_domain = 5626 attr->transfer ? MLX5_MTR_DOMAIN_TRANSFER : 5627 (attr->egress ? MLX5_MTR_DOMAIN_EGRESS : 5628 MLX5_MTR_DOMAIN_INGRESS); 5629 sub_policy = policy->sub_policys[mtr_domain][0]; 5630 } 5631 if (!sub_policy) 5632 rte_flow_error_set(error, EINVAL, 5633 RTE_FLOW_ERROR_TYPE_UNSPECIFIED, NULL, 5634 "Failed to get meter sub-policy."); 5635 exit: 5636 return sub_policy; 5637 } 5638 5639 /** 5640 * Split the meter flow. 5641 * 5642 * As meter flow will split to three sub flow, other than meter 5643 * action, the other actions make sense to only meter accepts 5644 * the packet. If it need to be dropped, no other additional 5645 * actions should be take. 5646 * 5647 * One kind of special action which decapsulates the L3 tunnel 5648 * header will be in the prefix sub flow, as not to take the 5649 * L3 tunnel header into account. 5650 * 5651 * @param[in] dev 5652 * Pointer to Ethernet device. 5653 * @param[in] flow 5654 * Parent flow structure pointer. 5655 * @param wks 5656 * Pointer to thread flow work space. 5657 * @param[in] attr 5658 * Flow rule attributes. 5659 * @param[in] items 5660 * Pattern specification (list terminated by the END pattern item). 5661 * @param[out] sfx_items 5662 * Suffix flow match items (list terminated by the END pattern item). 5663 * @param[in] actions 5664 * Associated actions (list terminated by the END action). 5665 * @param[out] actions_sfx 5666 * Suffix flow actions. 5667 * @param[out] actions_pre 5668 * Prefix flow actions. 5669 * @param[out] mtr_flow_id 5670 * Pointer to meter flow id. 5671 * @param[out] error 5672 * Perform verbose error reporting if not NULL. 5673 * 5674 * @return 5675 * 0 on success, a negative errno value otherwise and rte_errno is set. 5676 */ 5677 static int 5678 flow_meter_split_prep(struct rte_eth_dev *dev, 5679 struct rte_flow *flow, 5680 struct mlx5_flow_workspace *wks, 5681 const struct rte_flow_attr *attr, 5682 const struct rte_flow_item items[], 5683 struct rte_flow_item sfx_items[], 5684 const struct rte_flow_action actions[], 5685 struct rte_flow_action actions_sfx[], 5686 struct rte_flow_action actions_pre[], 5687 uint32_t *mtr_flow_id, 5688 struct rte_flow_error *error) 5689 { 5690 struct mlx5_priv *priv = dev->data->dev_private; 5691 struct mlx5_flow_meter_info *fm = wks->fm; 5692 struct rte_flow_action *tag_action = NULL; 5693 struct rte_flow_item *tag_item; 5694 struct mlx5_rte_flow_action_set_tag *set_tag; 5695 const struct rte_flow_action_raw_encap *raw_encap; 5696 const struct rte_flow_action_raw_decap *raw_decap; 5697 struct mlx5_rte_flow_item_tag *tag_item_spec; 5698 struct mlx5_rte_flow_item_tag *tag_item_mask; 5699 uint32_t tag_id = 0; 5700 struct rte_flow_item *vlan_item_dst = NULL; 5701 const struct rte_flow_item *vlan_item_src = NULL; 5702 const struct rte_flow_item *orig_items = items; 5703 struct rte_flow_action *hw_mtr_action; 5704 struct rte_flow_action *action_pre_head = NULL; 5705 uint16_t flow_src_port = priv->representor_id; 5706 bool mtr_first; 5707 uint8_t mtr_id_offset = priv->mtr_reg_share ? MLX5_MTR_COLOR_BITS : 0; 5708 uint8_t mtr_reg_bits = priv->mtr_reg_share ? 5709 MLX5_MTR_IDLE_BITS_IN_COLOR_REG : MLX5_REG_BITS; 5710 uint32_t flow_id = 0; 5711 uint32_t flow_id_reversed = 0; 5712 uint8_t flow_id_bits = 0; 5713 bool after_meter = false; 5714 int shift; 5715 5716 /* Prepare the suffix subflow items. */ 5717 tag_item = sfx_items++; 5718 for (; items->type != RTE_FLOW_ITEM_TYPE_END; items++) { 5719 int item_type = items->type; 5720 5721 switch (item_type) { 5722 case RTE_FLOW_ITEM_TYPE_PORT_ID: 5723 case RTE_FLOW_ITEM_TYPE_REPRESENTED_PORT: 5724 case RTE_FLOW_ITEM_TYPE_PORT_REPRESENTOR: 5725 if (mlx5_flow_get_item_vport_id(dev, items, &flow_src_port, NULL, error)) 5726 return -rte_errno; 5727 if (!fm->def_policy && wks->policy->hierarchy_match_port && 5728 flow_src_port != priv->representor_id) { 5729 if (flow_drv_mtr_hierarchy_rule_create(dev, 5730 flow, fm, 5731 flow_src_port, 5732 items, 5733 error)) 5734 return -rte_errno; 5735 } 5736 memcpy(sfx_items, items, sizeof(*sfx_items)); 5737 sfx_items++; 5738 break; 5739 case RTE_FLOW_ITEM_TYPE_VLAN: 5740 /* Determine if copy vlan item below. */ 5741 vlan_item_src = items; 5742 vlan_item_dst = sfx_items++; 5743 vlan_item_dst->type = RTE_FLOW_ITEM_TYPE_VOID; 5744 break; 5745 default: 5746 break; 5747 } 5748 } 5749 sfx_items->type = RTE_FLOW_ITEM_TYPE_END; 5750 sfx_items++; 5751 mtr_first = priv->sh->meter_aso_en && 5752 (attr->egress || (attr->transfer && flow_src_port != UINT16_MAX)); 5753 /* For ASO meter, meter must be before tag in TX direction. */ 5754 if (mtr_first) { 5755 action_pre_head = actions_pre++; 5756 /* Leave space for tag action. */ 5757 tag_action = actions_pre++; 5758 } 5759 /* Prepare the actions for prefix and suffix flow. */ 5760 for (; actions->type != RTE_FLOW_ACTION_TYPE_END; actions++) { 5761 struct rte_flow_action *action_cur = NULL; 5762 5763 switch (actions->type) { 5764 case RTE_FLOW_ACTION_TYPE_METER: 5765 if (mtr_first) { 5766 action_cur = action_pre_head; 5767 } else { 5768 /* Leave space for tag action. */ 5769 tag_action = actions_pre++; 5770 action_cur = actions_pre++; 5771 } 5772 after_meter = true; 5773 break; 5774 case RTE_FLOW_ACTION_TYPE_VXLAN_DECAP: 5775 case RTE_FLOW_ACTION_TYPE_NVGRE_DECAP: 5776 action_cur = actions_pre++; 5777 break; 5778 case RTE_FLOW_ACTION_TYPE_RAW_ENCAP: 5779 raw_encap = actions->conf; 5780 if (raw_encap->size < MLX5_ENCAPSULATION_DECISION_SIZE) 5781 action_cur = actions_pre++; 5782 break; 5783 case RTE_FLOW_ACTION_TYPE_RAW_DECAP: 5784 raw_decap = actions->conf; 5785 if (raw_decap->size > MLX5_ENCAPSULATION_DECISION_SIZE) 5786 action_cur = actions_pre++; 5787 break; 5788 case RTE_FLOW_ACTION_TYPE_OF_PUSH_VLAN: 5789 case RTE_FLOW_ACTION_TYPE_OF_SET_VLAN_VID: 5790 if (vlan_item_dst && vlan_item_src) { 5791 memcpy(vlan_item_dst, vlan_item_src, 5792 sizeof(*vlan_item_dst)); 5793 /* 5794 * Convert to internal match item, it is used 5795 * for vlan push and set vid. 5796 */ 5797 vlan_item_dst->type = (enum rte_flow_item_type) 5798 MLX5_RTE_FLOW_ITEM_TYPE_VLAN; 5799 } 5800 break; 5801 case RTE_FLOW_ACTION_TYPE_COUNT: 5802 if (fm->def_policy) 5803 action_cur = after_meter ? 5804 actions_sfx++ : actions_pre++; 5805 break; 5806 default: 5807 break; 5808 } 5809 if (!action_cur) 5810 action_cur = (fm->def_policy) ? 5811 actions_sfx++ : actions_pre++; 5812 memcpy(action_cur, actions, sizeof(struct rte_flow_action)); 5813 } 5814 /* Add end action to the actions. */ 5815 actions_sfx->type = RTE_FLOW_ACTION_TYPE_END; 5816 if (priv->sh->meter_aso_en) { 5817 /** 5818 * For ASO meter, need to add an extra jump action explicitly, 5819 * to jump from meter to policer table. 5820 */ 5821 struct mlx5_flow_meter_sub_policy *sub_policy; 5822 struct mlx5_flow_tbl_data_entry *tbl_data; 5823 5824 if (!fm->def_policy) { 5825 sub_policy = get_meter_sub_policy(dev, flow, wks, 5826 attr, orig_items, 5827 error); 5828 if (!sub_policy) 5829 return -rte_errno; 5830 } else { 5831 enum mlx5_meter_domain mtr_domain = 5832 attr->transfer ? MLX5_MTR_DOMAIN_TRANSFER : 5833 (attr->egress ? MLX5_MTR_DOMAIN_EGRESS : 5834 MLX5_MTR_DOMAIN_INGRESS); 5835 5836 sub_policy = 5837 &priv->sh->mtrmng->def_policy[mtr_domain]->sub_policy; 5838 } 5839 tbl_data = container_of(sub_policy->tbl_rsc, 5840 struct mlx5_flow_tbl_data_entry, tbl); 5841 hw_mtr_action = actions_pre++; 5842 hw_mtr_action->type = (enum rte_flow_action_type) 5843 MLX5_RTE_FLOW_ACTION_TYPE_JUMP; 5844 hw_mtr_action->conf = tbl_data->jump.action; 5845 } 5846 actions_pre->type = RTE_FLOW_ACTION_TYPE_END; 5847 actions_pre++; 5848 if (!tag_action) 5849 return rte_flow_error_set(error, ENOMEM, 5850 RTE_FLOW_ERROR_TYPE_UNSPECIFIED, 5851 NULL, "No tag action space."); 5852 if (!mtr_flow_id) { 5853 tag_action->type = RTE_FLOW_ACTION_TYPE_VOID; 5854 goto exit; 5855 } 5856 /* Only default-policy Meter creates mtr flow id. */ 5857 if (fm->def_policy) { 5858 mlx5_ipool_malloc(fm->flow_ipool, &tag_id); 5859 if (!tag_id) 5860 return rte_flow_error_set(error, ENOMEM, 5861 RTE_FLOW_ERROR_TYPE_UNSPECIFIED, NULL, 5862 "Failed to allocate meter flow id."); 5863 flow_id = tag_id - 1; 5864 flow_id_bits = (!flow_id) ? 1 : 5865 (MLX5_REG_BITS - rte_clz32(flow_id)); 5866 if ((flow_id_bits + priv->sh->mtrmng->max_mtr_bits) > 5867 mtr_reg_bits) { 5868 mlx5_ipool_free(fm->flow_ipool, tag_id); 5869 return rte_flow_error_set(error, EINVAL, 5870 RTE_FLOW_ERROR_TYPE_UNSPECIFIED, NULL, 5871 "Meter flow id exceeds max limit."); 5872 } 5873 if (flow_id_bits > priv->sh->mtrmng->max_mtr_flow_bits) 5874 priv->sh->mtrmng->max_mtr_flow_bits = flow_id_bits; 5875 } 5876 /* Build tag actions and items for meter_id/meter flow_id. */ 5877 set_tag = (struct mlx5_rte_flow_action_set_tag *)actions_pre; 5878 tag_item_spec = (struct mlx5_rte_flow_item_tag *)sfx_items; 5879 tag_item_mask = tag_item_spec + 1; 5880 /* Both flow_id and meter_id share the same register. */ 5881 *set_tag = (struct mlx5_rte_flow_action_set_tag) { 5882 .id = (enum modify_reg)mlx5_flow_get_reg_id(dev, MLX5_MTR_ID, 5883 0, error), 5884 .offset = mtr_id_offset, 5885 .length = mtr_reg_bits, 5886 .data = flow->meter, 5887 }; 5888 /* 5889 * The color Reg bits used by flow_id are growing from 5890 * msb to lsb, so must do bit reverse for flow_id val in RegC. 5891 */ 5892 for (shift = 0; shift < flow_id_bits; shift++) 5893 flow_id_reversed = (flow_id_reversed << 1) | 5894 ((flow_id >> shift) & 0x1); 5895 set_tag->data |= 5896 flow_id_reversed << (mtr_reg_bits - flow_id_bits); 5897 tag_item_spec->id = set_tag->id; 5898 tag_item_spec->data = set_tag->data << mtr_id_offset; 5899 tag_item_mask->data = UINT32_MAX << mtr_id_offset; 5900 tag_action->type = (enum rte_flow_action_type) 5901 MLX5_RTE_FLOW_ACTION_TYPE_TAG; 5902 tag_action->conf = set_tag; 5903 tag_item->type = (enum rte_flow_item_type) 5904 MLX5_RTE_FLOW_ITEM_TYPE_TAG; 5905 tag_item->spec = tag_item_spec; 5906 tag_item->last = NULL; 5907 tag_item->mask = tag_item_mask; 5908 exit: 5909 if (mtr_flow_id) 5910 *mtr_flow_id = tag_id; 5911 return 0; 5912 } 5913 5914 /** 5915 * Split action list having QUEUE/RSS for metadata register copy. 5916 * 5917 * Once Q/RSS action is detected in user's action list, the flow action 5918 * should be split in order to copy metadata registers, which will happen in 5919 * RX_CP_TBL like, 5920 * - CQE->flow_tag := reg_c[1] (MARK) 5921 * - CQE->flow_table_metadata (reg_b) := reg_c[0] (META) 5922 * The Q/RSS action will be performed on RX_ACT_TBL after passing by RX_CP_TBL. 5923 * This is because the last action of each flow must be a terminal action 5924 * (QUEUE, RSS or DROP). 5925 * 5926 * Flow ID must be allocated to identify actions in the RX_ACT_TBL and it is 5927 * stored and kept in the mlx5_flow structure per each sub_flow. 5928 * 5929 * The Q/RSS action is replaced with, 5930 * - SET_TAG, setting the allocated flow ID to reg_c[2]. 5931 * And the following JUMP action is added at the end, 5932 * - JUMP, to RX_CP_TBL. 5933 * 5934 * A flow to perform remained Q/RSS action will be created in RX_ACT_TBL by 5935 * flow_create_split_metadata() routine. The flow will look like, 5936 * - If flow ID matches (reg_c[2]), perform Q/RSS. 5937 * 5938 * @param dev 5939 * Pointer to Ethernet device. 5940 * @param[out] split_actions 5941 * Pointer to store split actions to jump to CP_TBL. 5942 * @param[in] actions 5943 * Pointer to the list of original flow actions. 5944 * @param[in] qrss 5945 * Pointer to the Q/RSS action. 5946 * @param[in] actions_n 5947 * Number of original actions. 5948 * @param[in] mtr_sfx 5949 * Check if it is in meter suffix table. 5950 * @param[out] error 5951 * Perform verbose error reporting if not NULL. 5952 * 5953 * @return 5954 * non-zero unique flow_id on success, otherwise 0 and 5955 * error/rte_error are set. 5956 */ 5957 static uint32_t 5958 flow_mreg_split_qrss_prep(struct rte_eth_dev *dev, 5959 struct rte_flow_action *split_actions, 5960 const struct rte_flow_action *actions, 5961 const struct rte_flow_action *qrss, 5962 int actions_n, int mtr_sfx, 5963 struct rte_flow_error *error) 5964 { 5965 struct mlx5_priv *priv = dev->data->dev_private; 5966 struct mlx5_rte_flow_action_set_tag *set_tag; 5967 struct rte_flow_action_jump *jump; 5968 const int qrss_idx = qrss - actions; 5969 uint32_t flow_id = 0; 5970 int ret = 0; 5971 5972 /* 5973 * Given actions will be split 5974 * - Replace QUEUE/RSS action with SET_TAG to set flow ID. 5975 * - Add jump to mreg CP_TBL. 5976 * As a result, there will be one more action. 5977 */ 5978 memcpy(split_actions, actions, sizeof(*split_actions) * actions_n); 5979 /* Count MLX5_RTE_FLOW_ACTION_TYPE_TAG. */ 5980 ++actions_n; 5981 set_tag = (void *)(split_actions + actions_n); 5982 /* 5983 * If we are not the meter suffix flow, add the tag action. 5984 * Since meter suffix flow already has the tag added. 5985 */ 5986 if (!mtr_sfx) { 5987 /* 5988 * Allocate the new subflow ID. This one is unique within 5989 * device and not shared with representors. Otherwise, 5990 * we would have to resolve multi-thread access synch 5991 * issue. Each flow on the shared device is appended 5992 * with source vport identifier, so the resulting 5993 * flows will be unique in the shared (by master and 5994 * representors) domain even if they have coinciding 5995 * IDs. 5996 */ 5997 mlx5_ipool_malloc(priv->sh->ipool 5998 [MLX5_IPOOL_RSS_EXPANTION_FLOW_ID], &flow_id); 5999 if (!flow_id) 6000 return rte_flow_error_set(error, ENOMEM, 6001 RTE_FLOW_ERROR_TYPE_ACTION, 6002 NULL, "can't allocate id " 6003 "for split Q/RSS subflow"); 6004 /* Internal SET_TAG action to set flow ID. */ 6005 *set_tag = (struct mlx5_rte_flow_action_set_tag){ 6006 .data = flow_id, 6007 }; 6008 ret = mlx5_flow_get_reg_id(dev, MLX5_COPY_MARK, 0, error); 6009 if (ret < 0) 6010 return ret; 6011 set_tag->id = ret; 6012 /* Construct new actions array. */ 6013 /* Replace QUEUE/RSS action. */ 6014 split_actions[qrss_idx] = (struct rte_flow_action){ 6015 .type = (enum rte_flow_action_type) 6016 MLX5_RTE_FLOW_ACTION_TYPE_TAG, 6017 .conf = set_tag, 6018 }; 6019 } else { 6020 /* 6021 * If we are the suffix flow of meter, tag already exist. 6022 * Set the QUEUE/RSS action to void. 6023 */ 6024 split_actions[qrss_idx].type = RTE_FLOW_ACTION_TYPE_VOID; 6025 } 6026 /* JUMP action to jump to mreg copy table (CP_TBL). */ 6027 jump = (void *)(set_tag + 1); 6028 *jump = (struct rte_flow_action_jump){ 6029 .group = MLX5_FLOW_MREG_CP_TABLE_GROUP, 6030 }; 6031 split_actions[actions_n - 2] = (struct rte_flow_action){ 6032 .type = RTE_FLOW_ACTION_TYPE_JUMP, 6033 .conf = jump, 6034 }; 6035 split_actions[actions_n - 1] = (struct rte_flow_action){ 6036 .type = RTE_FLOW_ACTION_TYPE_END, 6037 }; 6038 return flow_id; 6039 } 6040 6041 /** 6042 * Extend the given action list for Tx metadata copy. 6043 * 6044 * Copy the given action list to the ext_actions and add flow metadata register 6045 * copy action in order to copy reg_a set by WQE to reg_c[0]. 6046 * 6047 * @param[out] ext_actions 6048 * Pointer to the extended action list. 6049 * @param[in] actions 6050 * Pointer to the list of actions. 6051 * @param[in] actions_n 6052 * Number of actions in the list. 6053 * @param[out] error 6054 * Perform verbose error reporting if not NULL. 6055 * @param[in] encap_idx 6056 * The encap action index. 6057 * 6058 * @return 6059 * 0 on success, negative value otherwise 6060 */ 6061 static int 6062 flow_mreg_tx_copy_prep(struct rte_eth_dev *dev, 6063 struct rte_flow_action *ext_actions, 6064 const struct rte_flow_action *actions, 6065 int actions_n, struct rte_flow_error *error, 6066 int encap_idx) 6067 { 6068 struct mlx5_flow_action_copy_mreg *cp_mreg = 6069 (struct mlx5_flow_action_copy_mreg *) 6070 (ext_actions + actions_n + 1); 6071 int ret; 6072 6073 ret = mlx5_flow_get_reg_id(dev, MLX5_METADATA_RX, 0, error); 6074 if (ret < 0) 6075 return ret; 6076 cp_mreg->dst = ret; 6077 ret = mlx5_flow_get_reg_id(dev, MLX5_METADATA_TX, 0, error); 6078 if (ret < 0) 6079 return ret; 6080 cp_mreg->src = ret; 6081 if (encap_idx != 0) 6082 memcpy(ext_actions, actions, sizeof(*ext_actions) * encap_idx); 6083 if (encap_idx == actions_n - 1) { 6084 ext_actions[actions_n - 1] = (struct rte_flow_action){ 6085 .type = (enum rte_flow_action_type) 6086 MLX5_RTE_FLOW_ACTION_TYPE_COPY_MREG, 6087 .conf = cp_mreg, 6088 }; 6089 ext_actions[actions_n] = (struct rte_flow_action){ 6090 .type = RTE_FLOW_ACTION_TYPE_END, 6091 }; 6092 } else { 6093 ext_actions[encap_idx] = (struct rte_flow_action){ 6094 .type = (enum rte_flow_action_type) 6095 MLX5_RTE_FLOW_ACTION_TYPE_COPY_MREG, 6096 .conf = cp_mreg, 6097 }; 6098 memcpy(ext_actions + encap_idx + 1, actions + encap_idx, 6099 sizeof(*ext_actions) * (actions_n - encap_idx)); 6100 } 6101 return 0; 6102 } 6103 6104 /** 6105 * Check the match action from the action list. 6106 * 6107 * @param[in] actions 6108 * Pointer to the list of actions. 6109 * @param[in] attr 6110 * Flow rule attributes. 6111 * @param[in] action 6112 * The action to be check if exist. 6113 * @param[out] match_action_pos 6114 * Pointer to the position of the matched action if exists, otherwise is -1. 6115 * @param[out] qrss_action_pos 6116 * Pointer to the position of the Queue/RSS action if exists, otherwise is -1. 6117 * @param[out] modify_after_mirror 6118 * Pointer to the flag of modify action after FDB mirroring. 6119 * 6120 * @return 6121 * > 0 the total number of actions. 6122 * 0 if not found match action in action list. 6123 */ 6124 static int 6125 flow_check_match_action(const struct rte_flow_action actions[], 6126 const struct rte_flow_attr *attr, 6127 enum rte_flow_action_type action, 6128 int *match_action_pos, int *qrss_action_pos, 6129 int *modify_after_mirror) 6130 { 6131 const struct rte_flow_action_sample *sample; 6132 const struct rte_flow_action_raw_decap *decap; 6133 const struct rte_flow_action *action_cur = NULL; 6134 int actions_n = 0; 6135 uint32_t ratio = 0; 6136 int sub_type = 0; 6137 int flag = 0; 6138 int fdb_mirror = 0; 6139 6140 *match_action_pos = -1; 6141 *qrss_action_pos = -1; 6142 for (; actions->type != RTE_FLOW_ACTION_TYPE_END; actions++) { 6143 if (actions->type == action) { 6144 flag = 1; 6145 *match_action_pos = actions_n; 6146 } 6147 switch (actions->type) { 6148 case RTE_FLOW_ACTION_TYPE_QUEUE: 6149 case RTE_FLOW_ACTION_TYPE_RSS: 6150 *qrss_action_pos = actions_n; 6151 break; 6152 case RTE_FLOW_ACTION_TYPE_SAMPLE: 6153 sample = actions->conf; 6154 ratio = sample->ratio; 6155 sub_type = ((const struct rte_flow_action *) 6156 (sample->actions))->type; 6157 if (ratio == 1 && attr->transfer && 6158 sub_type != RTE_FLOW_ACTION_TYPE_END) 6159 fdb_mirror = 1; 6160 break; 6161 case RTE_FLOW_ACTION_TYPE_SET_MAC_SRC: 6162 case RTE_FLOW_ACTION_TYPE_SET_MAC_DST: 6163 case RTE_FLOW_ACTION_TYPE_SET_IPV4_SRC: 6164 case RTE_FLOW_ACTION_TYPE_SET_IPV4_DST: 6165 case RTE_FLOW_ACTION_TYPE_SET_IPV6_SRC: 6166 case RTE_FLOW_ACTION_TYPE_SET_IPV6_DST: 6167 case RTE_FLOW_ACTION_TYPE_SET_TP_SRC: 6168 case RTE_FLOW_ACTION_TYPE_SET_TP_DST: 6169 case RTE_FLOW_ACTION_TYPE_DEC_TTL: 6170 case RTE_FLOW_ACTION_TYPE_SET_TTL: 6171 case RTE_FLOW_ACTION_TYPE_INC_TCP_SEQ: 6172 case RTE_FLOW_ACTION_TYPE_DEC_TCP_SEQ: 6173 case RTE_FLOW_ACTION_TYPE_INC_TCP_ACK: 6174 case RTE_FLOW_ACTION_TYPE_DEC_TCP_ACK: 6175 case RTE_FLOW_ACTION_TYPE_SET_IPV4_DSCP: 6176 case RTE_FLOW_ACTION_TYPE_SET_IPV6_DSCP: 6177 case RTE_FLOW_ACTION_TYPE_FLAG: 6178 case RTE_FLOW_ACTION_TYPE_MARK: 6179 case RTE_FLOW_ACTION_TYPE_SET_META: 6180 case RTE_FLOW_ACTION_TYPE_SET_TAG: 6181 case RTE_FLOW_ACTION_TYPE_OF_POP_VLAN: 6182 case RTE_FLOW_ACTION_TYPE_OF_PUSH_VLAN: 6183 case RTE_FLOW_ACTION_TYPE_OF_SET_VLAN_VID: 6184 case RTE_FLOW_ACTION_TYPE_OF_SET_VLAN_PCP: 6185 case RTE_FLOW_ACTION_TYPE_VXLAN_DECAP: 6186 case RTE_FLOW_ACTION_TYPE_NVGRE_DECAP: 6187 case RTE_FLOW_ACTION_TYPE_MODIFY_FIELD: 6188 case RTE_FLOW_ACTION_TYPE_METER: 6189 if (fdb_mirror) 6190 *modify_after_mirror = 1; 6191 break; 6192 case RTE_FLOW_ACTION_TYPE_RAW_DECAP: 6193 decap = actions->conf; 6194 action_cur = actions; 6195 while ((++action_cur)->type == RTE_FLOW_ACTION_TYPE_VOID) 6196 ; 6197 if (action_cur->type == RTE_FLOW_ACTION_TYPE_RAW_ENCAP) { 6198 const struct rte_flow_action_raw_encap *encap = 6199 action_cur->conf; 6200 if (decap->size <= 6201 MLX5_ENCAPSULATION_DECISION_SIZE && 6202 encap->size > 6203 MLX5_ENCAPSULATION_DECISION_SIZE) 6204 /* L3 encap. */ 6205 break; 6206 } 6207 if (fdb_mirror) 6208 *modify_after_mirror = 1; 6209 break; 6210 default: 6211 break; 6212 } 6213 actions_n++; 6214 } 6215 if (flag && fdb_mirror && !*modify_after_mirror) { 6216 /* FDB mirroring uses the destination array to implement 6217 * instead of FLOW_SAMPLER object. 6218 */ 6219 if (sub_type != RTE_FLOW_ACTION_TYPE_END) 6220 flag = 0; 6221 } 6222 /* Count RTE_FLOW_ACTION_TYPE_END. */ 6223 return flag ? actions_n + 1 : 0; 6224 } 6225 6226 #define SAMPLE_SUFFIX_ITEM 3 6227 6228 /** 6229 * Split the sample flow. 6230 * 6231 * As sample flow will split to two sub flow, sample flow with 6232 * sample action, the other actions will move to new suffix flow. 6233 * 6234 * Also add unique tag id with tag action in the sample flow, 6235 * the same tag id will be as match in the suffix flow. 6236 * 6237 * @param dev 6238 * Pointer to Ethernet device. 6239 * @param[in] add_tag 6240 * Add extra tag action flag. 6241 * @param[out] sfx_items 6242 * Suffix flow match items (list terminated by the END pattern item). 6243 * @param[in] actions 6244 * Associated actions (list terminated by the END action). 6245 * @param[out] actions_sfx 6246 * Suffix flow actions. 6247 * @param[out] actions_pre 6248 * Prefix flow actions. 6249 * @param[in] actions_n 6250 * The total number of actions. 6251 * @param[in] sample_action_pos 6252 * The sample action position. 6253 * @param[in] qrss_action_pos 6254 * The Queue/RSS action position. 6255 * @param[in] jump_table 6256 * Add extra jump action flag. 6257 * @param[out] error 6258 * Perform verbose error reporting if not NULL. 6259 * 6260 * @return 6261 * 0 on success, or unique flow_id, a negative errno value 6262 * otherwise and rte_errno is set. 6263 */ 6264 static int 6265 flow_sample_split_prep(struct rte_eth_dev *dev, 6266 int add_tag, 6267 const struct rte_flow_item items[], 6268 struct rte_flow_item sfx_items[], 6269 const struct rte_flow_action actions[], 6270 struct rte_flow_action actions_sfx[], 6271 struct rte_flow_action actions_pre[], 6272 int actions_n, 6273 int sample_action_pos, 6274 int qrss_action_pos, 6275 int jump_table, 6276 struct rte_flow_error *error) 6277 { 6278 struct mlx5_priv *priv = dev->data->dev_private; 6279 struct mlx5_rte_flow_action_set_tag *set_tag; 6280 struct mlx5_rte_flow_item_tag *tag_spec; 6281 struct mlx5_rte_flow_item_tag *tag_mask; 6282 struct rte_flow_action_jump *jump_action; 6283 uint32_t tag_id = 0; 6284 int append_index = 0; 6285 int set_tag_idx = -1; 6286 int index; 6287 int ret; 6288 6289 if (sample_action_pos < 0) 6290 return rte_flow_error_set(error, EINVAL, 6291 RTE_FLOW_ERROR_TYPE_ACTION, 6292 NULL, "invalid position of sample " 6293 "action in list"); 6294 /* Prepare the actions for prefix and suffix flow. */ 6295 if (add_tag) { 6296 /* Update the new added tag action index preceding 6297 * the PUSH_VLAN or ENCAP action. 6298 */ 6299 const struct rte_flow_action_raw_encap *raw_encap; 6300 const struct rte_flow_action *action = actions; 6301 int encap_idx; 6302 int action_idx = 0; 6303 int raw_decap_idx = -1; 6304 int push_vlan_idx = -1; 6305 for (; action->type != RTE_FLOW_ACTION_TYPE_END; action++) { 6306 switch (action->type) { 6307 case RTE_FLOW_ACTION_TYPE_RAW_DECAP: 6308 raw_decap_idx = action_idx; 6309 break; 6310 case RTE_FLOW_ACTION_TYPE_RAW_ENCAP: 6311 raw_encap = action->conf; 6312 if (raw_encap->size > 6313 MLX5_ENCAPSULATION_DECISION_SIZE) { 6314 encap_idx = raw_decap_idx != -1 ? 6315 raw_decap_idx : action_idx; 6316 if (encap_idx < sample_action_pos && 6317 push_vlan_idx == -1) 6318 set_tag_idx = encap_idx; 6319 } 6320 break; 6321 case RTE_FLOW_ACTION_TYPE_VXLAN_ENCAP: 6322 case RTE_FLOW_ACTION_TYPE_NVGRE_ENCAP: 6323 encap_idx = action_idx; 6324 if (encap_idx < sample_action_pos && 6325 push_vlan_idx == -1) 6326 set_tag_idx = encap_idx; 6327 break; 6328 case RTE_FLOW_ACTION_TYPE_OF_PUSH_VLAN: 6329 case RTE_FLOW_ACTION_TYPE_OF_SET_VLAN_VID: 6330 if (action_idx < sample_action_pos && 6331 push_vlan_idx == -1) { 6332 set_tag_idx = action_idx; 6333 push_vlan_idx = action_idx; 6334 } 6335 break; 6336 default: 6337 break; 6338 } 6339 action_idx++; 6340 } 6341 } 6342 /* Prepare the actions for prefix and suffix flow. */ 6343 if (qrss_action_pos >= 0 && qrss_action_pos < sample_action_pos) { 6344 index = qrss_action_pos; 6345 /* Put the preceding the Queue/RSS action into prefix flow. */ 6346 if (index != 0) 6347 memcpy(actions_pre, actions, 6348 sizeof(struct rte_flow_action) * index); 6349 /* Put others preceding the sample action into prefix flow. */ 6350 if (sample_action_pos > index + 1) 6351 memcpy(actions_pre + index, actions + index + 1, 6352 sizeof(struct rte_flow_action) * 6353 (sample_action_pos - index - 1)); 6354 index = sample_action_pos - 1; 6355 /* Put Queue/RSS action into Suffix flow. */ 6356 memcpy(actions_sfx, actions + qrss_action_pos, 6357 sizeof(struct rte_flow_action)); 6358 actions_sfx++; 6359 } else if (add_tag && set_tag_idx >= 0) { 6360 if (set_tag_idx > 0) 6361 memcpy(actions_pre, actions, 6362 sizeof(struct rte_flow_action) * set_tag_idx); 6363 memcpy(actions_pre + set_tag_idx + 1, actions + set_tag_idx, 6364 sizeof(struct rte_flow_action) * 6365 (sample_action_pos - set_tag_idx)); 6366 index = sample_action_pos; 6367 } else { 6368 index = sample_action_pos; 6369 if (index != 0) 6370 memcpy(actions_pre, actions, 6371 sizeof(struct rte_flow_action) * index); 6372 } 6373 /* For CX5, add an extra tag action for NIC-RX and E-Switch ingress. 6374 * For CX6DX and above, metadata registers Cx preserve their value, 6375 * add an extra tag action for NIC-RX and E-Switch Domain. 6376 */ 6377 if (add_tag) { 6378 /* Prepare the prefix tag action. */ 6379 append_index++; 6380 set_tag = (void *)(actions_pre + actions_n + append_index); 6381 /* Trust VF/SF on CX5 not supported meter so that the reserved 6382 * metadata regC is REG_NON, back to use application tag 6383 * index 0. 6384 */ 6385 if (unlikely(priv->sh->registers.aso_reg == REG_NON)) 6386 ret = mlx5_flow_get_reg_id(dev, MLX5_APP_TAG, 0, error); 6387 else 6388 ret = mlx5_flow_get_reg_id(dev, MLX5_SAMPLE_ID, 0, error); 6389 if (ret < 0) 6390 return ret; 6391 mlx5_ipool_malloc(priv->sh->ipool 6392 [MLX5_IPOOL_RSS_EXPANTION_FLOW_ID], &tag_id); 6393 *set_tag = (struct mlx5_rte_flow_action_set_tag) { 6394 .id = ret, 6395 .data = tag_id, 6396 }; 6397 /* Prepare the suffix subflow items. */ 6398 tag_spec = (void *)(sfx_items + SAMPLE_SUFFIX_ITEM); 6399 tag_spec->data = tag_id; 6400 tag_spec->id = set_tag->id; 6401 tag_mask = tag_spec + 1; 6402 tag_mask->data = UINT32_MAX; 6403 for (; items->type != RTE_FLOW_ITEM_TYPE_END; items++) { 6404 if (items->type == RTE_FLOW_ITEM_TYPE_PORT_ID || 6405 items->type == RTE_FLOW_ITEM_TYPE_PORT_REPRESENTOR || 6406 items->type == RTE_FLOW_ITEM_TYPE_REPRESENTED_PORT) { 6407 memcpy(sfx_items, items, sizeof(*sfx_items)); 6408 sfx_items++; 6409 break; 6410 } 6411 } 6412 sfx_items[0] = (struct rte_flow_item){ 6413 .type = (enum rte_flow_item_type) 6414 MLX5_RTE_FLOW_ITEM_TYPE_TAG, 6415 .spec = tag_spec, 6416 .last = NULL, 6417 .mask = tag_mask, 6418 }; 6419 sfx_items[1] = (struct rte_flow_item){ 6420 .type = (enum rte_flow_item_type) 6421 RTE_FLOW_ITEM_TYPE_END, 6422 }; 6423 /* Prepare the tag action in prefix subflow. */ 6424 set_tag_idx = (set_tag_idx == -1) ? index : set_tag_idx; 6425 actions_pre[set_tag_idx] = 6426 (struct rte_flow_action){ 6427 .type = (enum rte_flow_action_type) 6428 MLX5_RTE_FLOW_ACTION_TYPE_TAG, 6429 .conf = set_tag, 6430 }; 6431 /* Update next sample position due to add one tag action */ 6432 index += 1; 6433 } 6434 /* Copy the sample action into prefix flow. */ 6435 memcpy(actions_pre + index, actions + sample_action_pos, 6436 sizeof(struct rte_flow_action)); 6437 index += 1; 6438 /* For the modify action after the sample action in E-Switch mirroring, 6439 * Add the extra jump action in prefix subflow and jump into the next 6440 * table, then do the modify action in the new table. 6441 */ 6442 if (jump_table) { 6443 /* Prepare the prefix jump action. */ 6444 append_index++; 6445 jump_action = (void *)(actions_pre + actions_n + append_index); 6446 jump_action->group = jump_table; 6447 actions_pre[index++] = 6448 (struct rte_flow_action){ 6449 .type = (enum rte_flow_action_type) 6450 RTE_FLOW_ACTION_TYPE_JUMP, 6451 .conf = jump_action, 6452 }; 6453 } 6454 actions_pre[index] = (struct rte_flow_action){ 6455 .type = (enum rte_flow_action_type) 6456 RTE_FLOW_ACTION_TYPE_END, 6457 }; 6458 /* Put the actions after sample into Suffix flow. */ 6459 memcpy(actions_sfx, actions + sample_action_pos + 1, 6460 sizeof(struct rte_flow_action) * 6461 (actions_n - sample_action_pos - 1)); 6462 return tag_id; 6463 } 6464 6465 /** 6466 * The splitting for metadata feature. 6467 * 6468 * - Q/RSS action on NIC Rx should be split in order to pass by 6469 * the mreg copy table (RX_CP_TBL) and then it jumps to the 6470 * action table (RX_ACT_TBL) which has the split Q/RSS action. 6471 * 6472 * - All the actions on NIC Tx should have a mreg copy action to 6473 * copy reg_a from WQE to reg_c[0]. 6474 * 6475 * @param dev 6476 * Pointer to Ethernet device. 6477 * @param[in] flow 6478 * Parent flow structure pointer. 6479 * @param[in] attr 6480 * Flow rule attributes. 6481 * @param[in] items 6482 * Pattern specification (list terminated by the END pattern item). 6483 * @param[in] actions 6484 * Associated actions (list terminated by the END action). 6485 * @param[in] flow_split_info 6486 * Pointer to flow split info structure. 6487 * @param[out] error 6488 * Perform verbose error reporting if not NULL. 6489 * @return 6490 * 0 on success, negative value otherwise 6491 */ 6492 static int 6493 flow_create_split_metadata(struct rte_eth_dev *dev, 6494 struct rte_flow *flow, 6495 const struct rte_flow_attr *attr, 6496 const struct rte_flow_item items[], 6497 const struct rte_flow_action actions[], 6498 struct mlx5_flow_split_info *flow_split_info, 6499 struct rte_flow_error *error) 6500 { 6501 struct mlx5_priv *priv = dev->data->dev_private; 6502 struct mlx5_sh_config *config = &priv->sh->config; 6503 const struct rte_flow_action *qrss = NULL; 6504 struct rte_flow_action *ext_actions = NULL; 6505 struct mlx5_flow *dev_flow = NULL; 6506 uint32_t qrss_id = 0; 6507 int mtr_sfx = 0; 6508 size_t act_size; 6509 int actions_n; 6510 int encap_idx; 6511 int ret; 6512 6513 /* Check whether extensive metadata feature is engaged. */ 6514 if (!config->dv_flow_en || 6515 config->dv_xmeta_en == MLX5_XMETA_MODE_LEGACY || 6516 !mlx5_flow_ext_mreg_supported(dev)) 6517 return flow_create_split_inner(dev, flow, NULL, attr, items, 6518 actions, flow_split_info, error); 6519 actions_n = flow_parse_metadata_split_actions_info(actions, &qrss, 6520 &encap_idx); 6521 if (qrss) { 6522 /* Exclude hairpin flows from splitting. */ 6523 if (qrss->type == RTE_FLOW_ACTION_TYPE_QUEUE) { 6524 const struct rte_flow_action_queue *queue; 6525 6526 queue = qrss->conf; 6527 if (mlx5_rxq_is_hairpin(dev, queue->index)) 6528 qrss = NULL; 6529 } else if (qrss->type == RTE_FLOW_ACTION_TYPE_RSS) { 6530 const struct rte_flow_action_rss *rss; 6531 6532 rss = qrss->conf; 6533 if (mlx5_rxq_is_hairpin(dev, rss->queue[0])) 6534 qrss = NULL; 6535 } 6536 } 6537 if (qrss) { 6538 /* Check if it is in meter suffix table. */ 6539 mtr_sfx = attr->group == 6540 ((attr->transfer && priv->fdb_def_rule) ? 6541 (MLX5_FLOW_TABLE_LEVEL_METER - 1) : 6542 MLX5_FLOW_TABLE_LEVEL_METER); 6543 /* 6544 * Q/RSS action on NIC Rx should be split in order to pass by 6545 * the mreg copy table (RX_CP_TBL) and then it jumps to the 6546 * action table (RX_ACT_TBL) which has the split Q/RSS action. 6547 */ 6548 act_size = sizeof(struct rte_flow_action) * (actions_n + 1) + 6549 sizeof(struct rte_flow_action_set_tag) + 6550 sizeof(struct rte_flow_action_jump); 6551 ext_actions = mlx5_malloc(MLX5_MEM_ZERO, act_size, 0, 6552 SOCKET_ID_ANY); 6553 if (!ext_actions) 6554 return rte_flow_error_set(error, ENOMEM, 6555 RTE_FLOW_ERROR_TYPE_ACTION, 6556 NULL, "no memory to split " 6557 "metadata flow"); 6558 /* 6559 * Create the new actions list with removed Q/RSS action 6560 * and appended set tag and jump to register copy table 6561 * (RX_CP_TBL). We should preallocate unique tag ID here 6562 * in advance, because it is needed for set tag action. 6563 */ 6564 qrss_id = flow_mreg_split_qrss_prep(dev, ext_actions, actions, 6565 qrss, actions_n, 6566 mtr_sfx, error); 6567 if (!mtr_sfx && !qrss_id) { 6568 ret = -rte_errno; 6569 goto exit; 6570 } 6571 } else if (attr->egress) { 6572 /* 6573 * All the actions on NIC Tx should have a metadata register 6574 * copy action to copy reg_a from WQE to reg_c[meta] 6575 */ 6576 act_size = sizeof(struct rte_flow_action) * (actions_n + 1) + 6577 sizeof(struct mlx5_flow_action_copy_mreg); 6578 ext_actions = mlx5_malloc(MLX5_MEM_ZERO, act_size, 0, 6579 SOCKET_ID_ANY); 6580 if (!ext_actions) 6581 return rte_flow_error_set(error, ENOMEM, 6582 RTE_FLOW_ERROR_TYPE_ACTION, 6583 NULL, "no memory to split " 6584 "metadata flow"); 6585 /* Create the action list appended with copy register. */ 6586 ret = flow_mreg_tx_copy_prep(dev, ext_actions, actions, 6587 actions_n, error, encap_idx); 6588 if (ret < 0) 6589 goto exit; 6590 } 6591 /* Add the unmodified original or prefix subflow. */ 6592 ret = flow_create_split_inner(dev, flow, &dev_flow, attr, 6593 items, ext_actions ? ext_actions : 6594 actions, flow_split_info, error); 6595 if (ret < 0) 6596 goto exit; 6597 MLX5_ASSERT(dev_flow); 6598 if (qrss) { 6599 const struct rte_flow_attr q_attr = { 6600 .group = MLX5_FLOW_MREG_ACT_TABLE_GROUP, 6601 .ingress = 1, 6602 }; 6603 /* Internal PMD action to set register. */ 6604 struct mlx5_rte_flow_item_tag q_tag_spec = { 6605 .data = qrss_id, 6606 .id = REG_NON, 6607 }; 6608 struct rte_flow_item q_items[] = { 6609 { 6610 .type = (enum rte_flow_item_type) 6611 MLX5_RTE_FLOW_ITEM_TYPE_TAG, 6612 .spec = &q_tag_spec, 6613 .last = NULL, 6614 .mask = NULL, 6615 }, 6616 { 6617 .type = RTE_FLOW_ITEM_TYPE_END, 6618 }, 6619 }; 6620 struct rte_flow_action q_actions[] = { 6621 { 6622 .type = qrss->type, 6623 .conf = qrss->conf, 6624 }, 6625 { 6626 .type = RTE_FLOW_ACTION_TYPE_END, 6627 }, 6628 }; 6629 uint64_t layers = flow_get_prefix_layer_flags(dev_flow); 6630 6631 /* 6632 * Configure the tag item only if there is no meter subflow. 6633 * Since tag is already marked in the meter suffix subflow 6634 * we can just use the meter suffix items as is. 6635 */ 6636 if (qrss_id) { 6637 /* Not meter subflow. */ 6638 MLX5_ASSERT(!mtr_sfx); 6639 /* 6640 * Put unique id in prefix flow due to it is destroyed 6641 * after suffix flow and id will be freed after there 6642 * is no actual flows with this id and identifier 6643 * reallocation becomes possible (for example, for 6644 * other flows in other threads). 6645 */ 6646 dev_flow->handle->split_flow_id = qrss_id; 6647 ret = mlx5_flow_get_reg_id(dev, MLX5_COPY_MARK, 0, 6648 error); 6649 if (ret < 0) 6650 goto exit; 6651 q_tag_spec.id = ret; 6652 } 6653 dev_flow = NULL; 6654 /* Add suffix subflow to execute Q/RSS. */ 6655 flow_split_info->prefix_layers = layers; 6656 flow_split_info->prefix_mark = 0; 6657 flow_split_info->table_id = 0; 6658 ret = flow_create_split_inner(dev, flow, &dev_flow, 6659 &q_attr, mtr_sfx ? items : 6660 q_items, q_actions, 6661 flow_split_info, error); 6662 if (ret < 0) 6663 goto exit; 6664 /* qrss ID should be freed if failed. */ 6665 qrss_id = 0; 6666 MLX5_ASSERT(dev_flow); 6667 } 6668 6669 exit: 6670 /* 6671 * We do not destroy the partially created sub_flows in case of error. 6672 * These ones are included into parent flow list and will be destroyed 6673 * by flow_drv_destroy. 6674 */ 6675 mlx5_ipool_free(priv->sh->ipool[MLX5_IPOOL_RSS_EXPANTION_FLOW_ID], 6676 qrss_id); 6677 mlx5_free(ext_actions); 6678 return ret; 6679 } 6680 6681 /** 6682 * Create meter internal drop flow with the original pattern. 6683 * 6684 * @param dev 6685 * Pointer to Ethernet device. 6686 * @param[in] flow 6687 * Parent flow structure pointer. 6688 * @param[in] attr 6689 * Flow rule attributes. 6690 * @param[in] items 6691 * Pattern specification (list terminated by the END pattern item). 6692 * @param[in] flow_split_info 6693 * Pointer to flow split info structure. 6694 * @param[in] fm 6695 * Pointer to flow meter structure. 6696 * @param[out] error 6697 * Perform verbose error reporting if not NULL. 6698 * @return 6699 * 0 on success, negative value otherwise 6700 */ 6701 static uint32_t 6702 flow_meter_create_drop_flow_with_org_pattern(struct rte_eth_dev *dev, 6703 struct rte_flow *flow, 6704 const struct rte_flow_attr *attr, 6705 const struct rte_flow_item items[], 6706 struct mlx5_flow_split_info *flow_split_info, 6707 struct mlx5_flow_meter_info *fm, 6708 struct rte_flow_error *error) 6709 { 6710 struct mlx5_flow *dev_flow = NULL; 6711 struct rte_flow_attr drop_attr = *attr; 6712 struct rte_flow_action drop_actions[3]; 6713 struct mlx5_flow_split_info drop_split_info = *flow_split_info; 6714 6715 MLX5_ASSERT(fm->drop_cnt); 6716 drop_actions[0].type = 6717 (enum rte_flow_action_type)MLX5_RTE_FLOW_ACTION_TYPE_COUNT; 6718 drop_actions[0].conf = (void *)(uintptr_t)fm->drop_cnt; 6719 drop_actions[1].type = RTE_FLOW_ACTION_TYPE_DROP; 6720 drop_actions[1].conf = NULL; 6721 drop_actions[2].type = RTE_FLOW_ACTION_TYPE_END; 6722 drop_actions[2].conf = NULL; 6723 drop_split_info.external = false; 6724 drop_split_info.skip_scale |= 1 << MLX5_SCALE_FLOW_GROUP_BIT; 6725 drop_split_info.table_id = MLX5_MTR_TABLE_ID_DROP; 6726 drop_attr.group = MLX5_FLOW_TABLE_LEVEL_METER; 6727 return flow_create_split_inner(dev, flow, &dev_flow, 6728 &drop_attr, items, drop_actions, 6729 &drop_split_info, error); 6730 } 6731 6732 /** 6733 * The splitting for meter feature. 6734 * 6735 * - The meter flow will be split to two flows as prefix and 6736 * suffix flow. The packets make sense only it pass the prefix 6737 * meter action. 6738 * 6739 * - Reg_C_5 is used for the packet to match betweend prefix and 6740 * suffix flow. 6741 * 6742 * @param dev 6743 * Pointer to Ethernet device. 6744 * @param[in] flow 6745 * Parent flow structure pointer. 6746 * @param[in] attr 6747 * Flow rule attributes. 6748 * @param[in] items 6749 * Pattern specification (list terminated by the END pattern item). 6750 * @param[in] actions 6751 * Associated actions (list terminated by the END action). 6752 * @param[in] flow_split_info 6753 * Pointer to flow split info structure. 6754 * @param[out] error 6755 * Perform verbose error reporting if not NULL. 6756 * @return 6757 * 0 on success, negative value otherwise 6758 */ 6759 static int 6760 flow_create_split_meter(struct rte_eth_dev *dev, 6761 struct rte_flow *flow, 6762 const struct rte_flow_attr *attr, 6763 const struct rte_flow_item items[], 6764 const struct rte_flow_action actions[], 6765 struct mlx5_flow_split_info *flow_split_info, 6766 struct rte_flow_error *error) 6767 { 6768 struct mlx5_priv *priv = dev->data->dev_private; 6769 struct mlx5_flow_workspace *wks = mlx5_flow_get_thread_workspace(); 6770 struct rte_flow_action *sfx_actions = NULL; 6771 struct rte_flow_action *pre_actions = NULL; 6772 struct rte_flow_item *sfx_items = NULL; 6773 struct mlx5_flow *dev_flow = NULL; 6774 struct rte_flow_attr sfx_attr = *attr; 6775 struct mlx5_flow_meter_info *fm = NULL; 6776 uint8_t skip_scale_restore; 6777 bool has_mtr = false; 6778 bool has_modify = false; 6779 bool set_mtr_reg = true; 6780 bool is_mtr_hierarchy = false; 6781 uint32_t meter_id = 0; 6782 uint32_t mtr_idx = 0; 6783 uint32_t mtr_flow_id = 0; 6784 size_t act_size; 6785 size_t item_size; 6786 int actions_n = 0; 6787 int ret = 0; 6788 6789 if (priv->mtr_en) 6790 actions_n = flow_check_meter_action(dev, actions, &has_mtr, 6791 &has_modify, &meter_id); 6792 if (has_mtr) { 6793 if (flow->meter) { 6794 fm = flow_dv_meter_find_by_idx(priv, flow->meter); 6795 if (!fm) 6796 return rte_flow_error_set(error, EINVAL, 6797 RTE_FLOW_ERROR_TYPE_UNSPECIFIED, 6798 NULL, "Meter not found."); 6799 } else { 6800 fm = mlx5_flow_meter_find(priv, meter_id, &mtr_idx); 6801 if (!fm) 6802 return rte_flow_error_set(error, EINVAL, 6803 RTE_FLOW_ERROR_TYPE_UNSPECIFIED, 6804 NULL, "Meter not found."); 6805 ret = mlx5_flow_meter_attach(priv, fm, 6806 &sfx_attr, error); 6807 if (ret) 6808 return -rte_errno; 6809 flow->meter = mtr_idx; 6810 } 6811 MLX5_ASSERT(wks); 6812 wks->fm = fm; 6813 if (!fm->def_policy) { 6814 wks->policy = mlx5_flow_meter_policy_find(dev, 6815 fm->policy_id, 6816 NULL); 6817 MLX5_ASSERT(wks->policy); 6818 if (wks->policy->mark) 6819 wks->mark = 1; 6820 if (wks->policy->is_hierarchy) { 6821 wks->final_policy = 6822 mlx5_flow_meter_hierarchy_get_final_policy(dev, 6823 wks->policy); 6824 if (!wks->final_policy) 6825 return rte_flow_error_set(error, 6826 EINVAL, 6827 RTE_FLOW_ERROR_TYPE_ACTION, NULL, 6828 "Failed to find terminal policy of hierarchy."); 6829 is_mtr_hierarchy = true; 6830 } 6831 } 6832 /* 6833 * If it isn't default-policy Meter, and 6834 * 1. Not meter hierarchy and there's no action in flow to change 6835 * packet (modify/encap/decap etc.), OR 6836 * 2. No drop count needed for this meter. 6837 * Then no need to use regC to save meter id anymore. 6838 */ 6839 if (!fm->def_policy && ((!has_modify && !is_mtr_hierarchy) || !fm->drop_cnt)) 6840 set_mtr_reg = false; 6841 /* Prefix actions: meter, decap, encap, tag, jump, end, cnt. */ 6842 #define METER_PREFIX_ACTION 7 6843 act_size = (sizeof(struct rte_flow_action) * 6844 (actions_n + METER_PREFIX_ACTION)) + 6845 sizeof(struct mlx5_rte_flow_action_set_tag); 6846 /* Suffix items: tag, vlan, port id, end. */ 6847 #define METER_SUFFIX_ITEM 4 6848 item_size = sizeof(struct rte_flow_item) * METER_SUFFIX_ITEM + 6849 sizeof(struct mlx5_rte_flow_item_tag) * 2; 6850 sfx_actions = mlx5_malloc(MLX5_MEM_ZERO, (act_size + item_size), 6851 0, SOCKET_ID_ANY); 6852 if (!sfx_actions) 6853 return rte_flow_error_set(error, ENOMEM, 6854 RTE_FLOW_ERROR_TYPE_ACTION, 6855 NULL, "no memory to split " 6856 "meter flow"); 6857 sfx_items = (struct rte_flow_item *)((char *)sfx_actions + 6858 act_size); 6859 /* There's no suffix flow for meter of non-default policy. */ 6860 if (!fm->def_policy) 6861 pre_actions = sfx_actions + 1; 6862 else 6863 pre_actions = sfx_actions + actions_n; 6864 ret = flow_meter_split_prep(dev, flow, wks, &sfx_attr, 6865 items, sfx_items, actions, 6866 sfx_actions, pre_actions, 6867 (set_mtr_reg ? &mtr_flow_id : NULL), 6868 error); 6869 if (ret) { 6870 ret = -rte_errno; 6871 goto exit; 6872 } 6873 /* Add the prefix subflow. */ 6874 skip_scale_restore = flow_split_info->skip_scale; 6875 flow_split_info->skip_scale |= 6876 1 << MLX5_SCALE_JUMP_FLOW_GROUP_BIT; 6877 ret = flow_create_split_inner(dev, flow, &dev_flow, 6878 attr, items, pre_actions, 6879 flow_split_info, error); 6880 flow_split_info->skip_scale = skip_scale_restore; 6881 if (ret) { 6882 if (mtr_flow_id) 6883 mlx5_ipool_free(fm->flow_ipool, mtr_flow_id); 6884 ret = -rte_errno; 6885 goto exit; 6886 } 6887 if (mtr_flow_id) { 6888 dev_flow->handle->split_flow_id = mtr_flow_id; 6889 dev_flow->handle->is_meter_flow_id = 1; 6890 } 6891 if (!fm->def_policy) { 6892 if (!set_mtr_reg && fm->drop_cnt) 6893 ret = 6894 flow_meter_create_drop_flow_with_org_pattern(dev, flow, 6895 &sfx_attr, items, 6896 flow_split_info, 6897 fm, error); 6898 goto exit; 6899 } 6900 /* Setting the sfx group atrr. */ 6901 sfx_attr.group = sfx_attr.transfer ? 6902 (MLX5_FLOW_TABLE_LEVEL_METER - 1) : 6903 MLX5_FLOW_TABLE_LEVEL_METER; 6904 flow_split_info->prefix_layers = 6905 flow_get_prefix_layer_flags(dev_flow); 6906 flow_split_info->prefix_mark |= wks->mark; 6907 flow_split_info->table_id = MLX5_MTR_TABLE_ID_SUFFIX; 6908 } 6909 /* Add the prefix subflow. */ 6910 ret = flow_create_split_metadata(dev, flow, 6911 &sfx_attr, sfx_items ? 6912 sfx_items : items, 6913 sfx_actions ? sfx_actions : actions, 6914 flow_split_info, error); 6915 exit: 6916 if (sfx_actions) 6917 mlx5_free(sfx_actions); 6918 return ret; 6919 } 6920 6921 /** 6922 * The splitting for sample feature. 6923 * 6924 * Once Sample action is detected in the action list, the flow actions should 6925 * be split into prefix sub flow and suffix sub flow. 6926 * 6927 * The original items remain in the prefix sub flow, all actions preceding the 6928 * sample action and the sample action itself will be copied to the prefix 6929 * sub flow, the actions following the sample action will be copied to the 6930 * suffix sub flow, Queue action always be located in the suffix sub flow. 6931 * 6932 * In order to make the packet from prefix sub flow matches with suffix sub 6933 * flow, an extra tag action be added into prefix sub flow, and the suffix sub 6934 * flow uses tag item with the unique flow id. 6935 * 6936 * @param dev 6937 * Pointer to Ethernet device. 6938 * @param[in] flow 6939 * Parent flow structure pointer. 6940 * @param[in] attr 6941 * Flow rule attributes. 6942 * @param[in] items 6943 * Pattern specification (list terminated by the END pattern item). 6944 * @param[in] actions 6945 * Associated actions (list terminated by the END action). 6946 * @param[in] flow_split_info 6947 * Pointer to flow split info structure. 6948 * @param[out] error 6949 * Perform verbose error reporting if not NULL. 6950 * @return 6951 * 0 on success, negative value otherwise 6952 */ 6953 static int 6954 flow_create_split_sample(struct rte_eth_dev *dev, 6955 struct rte_flow *flow, 6956 const struct rte_flow_attr *attr, 6957 const struct rte_flow_item items[], 6958 const struct rte_flow_action actions[], 6959 struct mlx5_flow_split_info *flow_split_info, 6960 struct rte_flow_error *error) 6961 { 6962 struct mlx5_priv *priv = dev->data->dev_private; 6963 struct rte_flow_action *sfx_actions = NULL; 6964 struct rte_flow_action *pre_actions = NULL; 6965 struct rte_flow_item *sfx_items = NULL; 6966 struct mlx5_flow *dev_flow = NULL; 6967 struct rte_flow_attr sfx_attr = *attr; 6968 #ifdef HAVE_IBV_FLOW_DV_SUPPORT 6969 struct mlx5_flow_dv_sample_resource *sample_res; 6970 struct mlx5_flow_tbl_data_entry *sfx_tbl_data; 6971 struct mlx5_flow_tbl_resource *sfx_tbl; 6972 struct mlx5_flow_workspace *wks = mlx5_flow_get_thread_workspace(); 6973 #endif 6974 size_t act_size; 6975 size_t item_size; 6976 uint32_t fdb_tx = 0; 6977 int32_t tag_id = 0; 6978 int actions_n = 0; 6979 int sample_action_pos; 6980 int qrss_action_pos; 6981 int add_tag = 0; 6982 int modify_after_mirror = 0; 6983 uint16_t jump_table = 0; 6984 const uint32_t next_ft_step = 1; 6985 int ret = 0; 6986 struct mlx5_priv *item_port_priv = NULL; 6987 const struct rte_flow_item *item; 6988 6989 if (priv->sampler_en) 6990 actions_n = flow_check_match_action(actions, attr, 6991 RTE_FLOW_ACTION_TYPE_SAMPLE, 6992 &sample_action_pos, &qrss_action_pos, 6993 &modify_after_mirror); 6994 if (actions_n) { 6995 /* The prefix actions must includes sample, tag, end. */ 6996 act_size = sizeof(struct rte_flow_action) * (actions_n * 2 + 1) 6997 + sizeof(struct mlx5_rte_flow_action_set_tag); 6998 item_size = sizeof(struct rte_flow_item) * SAMPLE_SUFFIX_ITEM + 6999 sizeof(struct mlx5_rte_flow_item_tag) * 2; 7000 sfx_actions = mlx5_malloc(MLX5_MEM_ZERO, (act_size + 7001 item_size), 0, SOCKET_ID_ANY); 7002 if (!sfx_actions) 7003 return rte_flow_error_set(error, ENOMEM, 7004 RTE_FLOW_ERROR_TYPE_ACTION, 7005 NULL, "no memory to split " 7006 "sample flow"); 7007 for (item = items; item->type != RTE_FLOW_ITEM_TYPE_END; item++) { 7008 if (item->type == RTE_FLOW_ITEM_TYPE_PORT_ID) { 7009 const struct rte_flow_item_port_id *spec; 7010 7011 spec = (const struct rte_flow_item_port_id *)item->spec; 7012 if (spec) 7013 item_port_priv = 7014 mlx5_port_to_eswitch_info(spec->id, true); 7015 break; 7016 } else if (item->type == RTE_FLOW_ITEM_TYPE_REPRESENTED_PORT) { 7017 const struct rte_flow_item_ethdev *spec; 7018 7019 spec = (const struct rte_flow_item_ethdev *)item->spec; 7020 if (spec) 7021 item_port_priv = 7022 mlx5_port_to_eswitch_info(spec->port_id, true); 7023 break; 7024 } else if (item->type == RTE_FLOW_ITEM_TYPE_PORT_REPRESENTOR) { 7025 const struct rte_flow_item_ethdev *spec; 7026 7027 spec = (const struct rte_flow_item_ethdev *)item->spec; 7028 if (spec) 7029 item_port_priv = 7030 mlx5_port_to_eswitch_info(spec->port_id, true); 7031 break; 7032 } 7033 } 7034 /* The representor_id is UINT16_MAX for uplink. */ 7035 fdb_tx = (attr->transfer && 7036 flow_source_vport_representor(priv, item_port_priv)); 7037 /* 7038 * When reg_c_preserve is set, metadata registers Cx preserve 7039 * their value even through packet duplication. 7040 */ 7041 add_tag = (!fdb_tx || 7042 priv->sh->cdev->config.hca_attr.reg_c_preserve); 7043 if (add_tag) 7044 sfx_items = (struct rte_flow_item *)((char *)sfx_actions 7045 + act_size); 7046 if (modify_after_mirror) 7047 jump_table = attr->group * MLX5_FLOW_TABLE_FACTOR + 7048 next_ft_step; 7049 pre_actions = sfx_actions + actions_n; 7050 tag_id = flow_sample_split_prep(dev, add_tag, items, sfx_items, 7051 actions, sfx_actions, 7052 pre_actions, actions_n, 7053 sample_action_pos, 7054 qrss_action_pos, jump_table, 7055 error); 7056 if (tag_id < 0 || (add_tag && !tag_id)) { 7057 ret = -rte_errno; 7058 goto exit; 7059 } 7060 if (modify_after_mirror) 7061 flow_split_info->skip_scale = 7062 1 << MLX5_SCALE_JUMP_FLOW_GROUP_BIT; 7063 /* Add the prefix subflow. */ 7064 ret = flow_create_split_inner(dev, flow, &dev_flow, attr, 7065 items, pre_actions, 7066 flow_split_info, error); 7067 if (ret) { 7068 ret = -rte_errno; 7069 goto exit; 7070 } 7071 dev_flow->handle->split_flow_id = tag_id; 7072 #ifdef HAVE_IBV_FLOW_DV_SUPPORT 7073 if (!modify_after_mirror) { 7074 /* Set the sfx group attr. */ 7075 sample_res = (struct mlx5_flow_dv_sample_resource *) 7076 dev_flow->dv.sample_res; 7077 sfx_tbl = (struct mlx5_flow_tbl_resource *) 7078 sample_res->normal_path_tbl; 7079 sfx_tbl_data = container_of(sfx_tbl, 7080 struct mlx5_flow_tbl_data_entry, 7081 tbl); 7082 sfx_attr.group = sfx_attr.transfer ? 7083 (sfx_tbl_data->level - 1) : sfx_tbl_data->level; 7084 } else { 7085 MLX5_ASSERT(attr->transfer); 7086 sfx_attr.group = jump_table; 7087 } 7088 flow_split_info->prefix_layers = 7089 flow_get_prefix_layer_flags(dev_flow); 7090 MLX5_ASSERT(wks); 7091 flow_split_info->prefix_mark |= wks->mark; 7092 /* Suffix group level already be scaled with factor, set 7093 * MLX5_SCALE_FLOW_GROUP_BIT of skip_scale to 1 to avoid scale 7094 * again in translation. 7095 */ 7096 flow_split_info->skip_scale = 1 << MLX5_SCALE_FLOW_GROUP_BIT; 7097 #endif 7098 } 7099 /* Add the suffix subflow. */ 7100 ret = flow_create_split_meter(dev, flow, &sfx_attr, 7101 sfx_items ? sfx_items : items, 7102 sfx_actions ? sfx_actions : actions, 7103 flow_split_info, error); 7104 exit: 7105 if (sfx_actions) 7106 mlx5_free(sfx_actions); 7107 return ret; 7108 } 7109 7110 /** 7111 * Split the flow to subflow set. The splitters might be linked 7112 * in the chain, like this: 7113 * flow_create_split_outer() calls: 7114 * flow_create_split_meter() calls: 7115 * flow_create_split_metadata(meter_subflow_0) calls: 7116 * flow_create_split_inner(metadata_subflow_0) 7117 * flow_create_split_inner(metadata_subflow_1) 7118 * flow_create_split_inner(metadata_subflow_2) 7119 * flow_create_split_metadata(meter_subflow_1) calls: 7120 * flow_create_split_inner(metadata_subflow_0) 7121 * flow_create_split_inner(metadata_subflow_1) 7122 * flow_create_split_inner(metadata_subflow_2) 7123 * 7124 * This provide flexible way to add new levels of flow splitting. 7125 * The all of successfully created subflows are included to the 7126 * parent flow dev_flow list. 7127 * 7128 * @param dev 7129 * Pointer to Ethernet device. 7130 * @param[in] flow 7131 * Parent flow structure pointer. 7132 * @param[in] attr 7133 * Flow rule attributes. 7134 * @param[in] items 7135 * Pattern specification (list terminated by the END pattern item). 7136 * @param[in] actions 7137 * Associated actions (list terminated by the END action). 7138 * @param[in] flow_split_info 7139 * Pointer to flow split info structure. 7140 * @param[out] error 7141 * Perform verbose error reporting if not NULL. 7142 * @return 7143 * 0 on success, negative value otherwise 7144 */ 7145 static int 7146 flow_create_split_outer(struct rte_eth_dev *dev, 7147 struct rte_flow *flow, 7148 const struct rte_flow_attr *attr, 7149 const struct rte_flow_item items[], 7150 const struct rte_flow_action actions[], 7151 struct mlx5_flow_split_info *flow_split_info, 7152 struct rte_flow_error *error) 7153 { 7154 int ret; 7155 7156 ret = flow_create_split_sample(dev, flow, attr, items, 7157 actions, flow_split_info, error); 7158 MLX5_ASSERT(ret <= 0); 7159 return ret; 7160 } 7161 7162 static inline struct mlx5_flow_tunnel * 7163 flow_tunnel_from_rule(const struct mlx5_flow *flow) 7164 { 7165 struct mlx5_flow_tunnel *tunnel; 7166 7167 #pragma GCC diagnostic push 7168 #pragma GCC diagnostic ignored "-Wcast-qual" 7169 tunnel = (typeof(tunnel))flow->tunnel; 7170 #pragma GCC diagnostic pop 7171 7172 return tunnel; 7173 } 7174 7175 /** 7176 * Create a flow and add it to @p list. 7177 * 7178 * @param dev 7179 * Pointer to Ethernet device. 7180 * @param list 7181 * Pointer to a TAILQ flow list. If this parameter NULL, 7182 * no list insertion occurred, flow is just created, 7183 * this is caller's responsibility to track the 7184 * created flow. 7185 * @param[in] attr 7186 * Flow rule attributes. 7187 * @param[in] items 7188 * Pattern specification (list terminated by the END pattern item). 7189 * @param[in] actions 7190 * Associated actions (list terminated by the END action). 7191 * @param[in] external 7192 * This flow rule is created by request external to PMD. 7193 * @param[out] error 7194 * Perform verbose error reporting if not NULL. 7195 * 7196 * @return 7197 * A flow index on success, 0 otherwise and rte_errno is set. 7198 */ 7199 static uint32_t 7200 flow_list_create(struct rte_eth_dev *dev, enum mlx5_flow_type type, 7201 const struct rte_flow_attr *attr, 7202 const struct rte_flow_item items[], 7203 const struct rte_flow_action original_actions[], 7204 bool external, struct rte_flow_error *error) 7205 { 7206 struct mlx5_priv *priv = dev->data->dev_private; 7207 struct rte_flow *flow = NULL; 7208 struct mlx5_flow *dev_flow; 7209 const struct rte_flow_action_rss *rss = NULL; 7210 struct mlx5_translated_action_handle 7211 indir_actions[MLX5_MAX_INDIRECT_ACTIONS]; 7212 int indir_actions_n = MLX5_MAX_INDIRECT_ACTIONS; 7213 union { 7214 struct mlx5_flow_expand_rss buf; 7215 uint8_t buffer[8192]; 7216 } expand_buffer; 7217 union { 7218 struct rte_flow_action actions[MLX5_MAX_SPLIT_ACTIONS]; 7219 uint8_t buffer[2048]; 7220 } actions_rx; 7221 union { 7222 struct rte_flow_action actions[MLX5_MAX_SPLIT_ACTIONS]; 7223 uint8_t buffer[2048]; 7224 } actions_hairpin_tx; 7225 union { 7226 struct rte_flow_item items[MLX5_MAX_SPLIT_ITEMS]; 7227 uint8_t buffer[2048]; 7228 } items_tx; 7229 struct mlx5_rte_flow_item_sq sq_specs[RTE_MAX_QUEUES_PER_PORT]; 7230 struct mlx5_flow_expand_rss *buf = &expand_buffer.buf; 7231 struct mlx5_flow_rss_desc *rss_desc; 7232 const struct rte_flow_action *p_actions_rx; 7233 uint32_t i; 7234 uint32_t idx = 0; 7235 int hairpin_flow; 7236 struct rte_flow_attr attr_tx = { .priority = 0 }; 7237 const struct rte_flow_action *actions; 7238 struct rte_flow_action *translated_actions = NULL; 7239 struct mlx5_flow_tunnel *tunnel; 7240 struct tunnel_default_miss_ctx default_miss_ctx = { 0, }; 7241 struct mlx5_flow_workspace *wks = mlx5_flow_push_thread_workspace(); 7242 struct mlx5_flow_split_info flow_split_info = { 7243 .external = !!external, 7244 .skip_scale = 0, 7245 .flow_idx = 0, 7246 .prefix_mark = 0, 7247 .prefix_layers = 0, 7248 .table_id = 0 7249 }; 7250 int ret; 7251 7252 MLX5_ASSERT(wks); 7253 rss_desc = &wks->rss_desc; 7254 ret = flow_action_handles_translate(dev, original_actions, 7255 indir_actions, 7256 &indir_actions_n, 7257 &translated_actions, error); 7258 if (ret < 0) { 7259 MLX5_ASSERT(translated_actions == NULL); 7260 return 0; 7261 } 7262 actions = translated_actions ? translated_actions : original_actions; 7263 p_actions_rx = actions; 7264 hairpin_flow = flow_check_hairpin_split(dev, attr, actions); 7265 ret = flow_drv_validate(dev, attr, items, p_actions_rx, 7266 external, hairpin_flow, error); 7267 if (ret < 0) 7268 goto error_before_hairpin_split; 7269 flow = mlx5_ipool_zmalloc(priv->flows[type], &idx); 7270 if (!flow) { 7271 rte_errno = ENOMEM; 7272 goto error_before_hairpin_split; 7273 } 7274 if (hairpin_flow > 0) { 7275 if (hairpin_flow > MLX5_MAX_SPLIT_ACTIONS) { 7276 rte_errno = EINVAL; 7277 goto error_before_hairpin_split; 7278 } 7279 flow_hairpin_split(dev, actions, actions_rx.actions, 7280 actions_hairpin_tx.actions, items_tx.items, 7281 idx); 7282 p_actions_rx = actions_rx.actions; 7283 } 7284 flow_split_info.flow_idx = idx; 7285 flow->drv_type = flow_get_drv_type(dev, attr); 7286 MLX5_ASSERT(flow->drv_type > MLX5_FLOW_TYPE_MIN && 7287 flow->drv_type < MLX5_FLOW_TYPE_MAX); 7288 memset(rss_desc, 0, offsetof(struct mlx5_flow_rss_desc, queue)); 7289 /* RSS Action only works on NIC RX domain */ 7290 if (attr->ingress) 7291 rss = flow_get_rss_action(dev, p_actions_rx); 7292 if (rss) { 7293 MLX5_ASSERT(rss->queue_num <= RTE_ETH_RSS_RETA_SIZE_512); 7294 rss_desc->symmetric_hash_function = MLX5_RSS_IS_SYMM(rss->func); 7295 /* 7296 * The following information is required by 7297 * mlx5_flow_hashfields_adjust() in advance. 7298 */ 7299 rss_desc->level = rss->level; 7300 /* RSS type 0 indicates default RSS type (RTE_ETH_RSS_IP). */ 7301 rss_desc->types = !rss->types ? RTE_ETH_RSS_IP : rss->types; 7302 } 7303 flow->dev_handles = 0; 7304 if (rss && rss->types) { 7305 unsigned int graph_root; 7306 7307 graph_root = find_graph_root(rss->level); 7308 ret = mlx5_flow_expand_rss(buf, sizeof(expand_buffer.buffer), 7309 items, rss->types, 7310 mlx5_support_expansion, graph_root); 7311 MLX5_ASSERT(ret > 0 && 7312 (unsigned int)ret < sizeof(expand_buffer.buffer)); 7313 if (rte_log_can_log(mlx5_logtype, RTE_LOG_DEBUG)) { 7314 for (i = 0; i < buf->entries; ++i) 7315 mlx5_dbg__print_pattern(buf->entry[i].pattern); 7316 } 7317 } else { 7318 ret = mlx5_flow_expand_sqn((struct mlx5_flow_expand_sqn *)buf, 7319 sizeof(expand_buffer.buffer), 7320 items, sq_specs); 7321 if (ret) { 7322 rte_flow_error_set(error, ENOMEM, RTE_FLOW_ERROR_TYPE_HANDLE, 7323 NULL, "not enough memory for rte_flow"); 7324 goto error; 7325 } 7326 if (buf->entries == 0) { 7327 buf->entries = 1; 7328 buf->entry[0].pattern = (void *)(uintptr_t)items; 7329 } 7330 } 7331 rss_desc->shared_rss = flow_get_shared_rss_action(dev, indir_actions, 7332 indir_actions_n); 7333 for (i = 0; i < buf->entries; ++i) { 7334 /* Initialize flow split data. */ 7335 flow_split_info.prefix_layers = 0; 7336 flow_split_info.prefix_mark = 0; 7337 flow_split_info.skip_scale = 0; 7338 /* 7339 * The splitter may create multiple dev_flows, 7340 * depending on configuration. In the simplest 7341 * case it just creates unmodified original flow. 7342 */ 7343 ret = flow_create_split_outer(dev, flow, attr, 7344 buf->entry[i].pattern, 7345 p_actions_rx, &flow_split_info, 7346 error); 7347 if (ret < 0) 7348 goto error; 7349 if (is_flow_tunnel_steer_rule(wks->flows[0].tof_type)) { 7350 ret = flow_tunnel_add_default_miss(dev, flow, attr, 7351 p_actions_rx, 7352 idx, 7353 wks->flows[0].tunnel, 7354 &default_miss_ctx, 7355 error); 7356 if (ret < 0) { 7357 mlx5_free(default_miss_ctx.queue); 7358 goto error; 7359 } 7360 } 7361 } 7362 /* Create the tx flow. */ 7363 if (hairpin_flow) { 7364 attr_tx.group = MLX5_HAIRPIN_TX_TABLE; 7365 attr_tx.ingress = 0; 7366 attr_tx.egress = 1; 7367 dev_flow = flow_drv_prepare(dev, flow, &attr_tx, items_tx.items, 7368 actions_hairpin_tx.actions, 7369 idx, error); 7370 if (!dev_flow) 7371 goto error; 7372 dev_flow->flow = flow; 7373 dev_flow->external = 0; 7374 SILIST_INSERT(&flow->dev_handles, dev_flow->handle_idx, 7375 dev_flow->handle, next); 7376 ret = flow_drv_translate(dev, dev_flow, &attr_tx, 7377 items_tx.items, 7378 actions_hairpin_tx.actions, error); 7379 if (ret < 0) 7380 goto error; 7381 } 7382 /* 7383 * Update the metadata register copy table. If extensive 7384 * metadata feature is enabled and registers are supported 7385 * we might create the extra rte_flow for each unique 7386 * MARK/FLAG action ID. 7387 * 7388 * The table is updated for ingress and transfer flows only, because 7389 * the egress Flows belong to the different device and 7390 * copy table should be updated in peer NIC Rx domain. 7391 */ 7392 if ((attr->ingress || attr->transfer) && 7393 (external || attr->group != MLX5_FLOW_MREG_CP_TABLE_GROUP)) { 7394 ret = flow_mreg_update_copy_table(dev, flow, actions, error); 7395 if (ret) 7396 goto error; 7397 } 7398 /* 7399 * If the flow is external (from application) OR device is started, 7400 * OR mreg discover, then apply immediately. 7401 */ 7402 if (external || dev->data->dev_started || 7403 (attr->group == MLX5_FLOW_MREG_CP_TABLE_GROUP && 7404 attr->priority == MLX5_FLOW_LOWEST_PRIO_INDICATOR)) { 7405 ret = flow_drv_apply(dev, flow, error); 7406 if (ret < 0) 7407 goto error; 7408 } 7409 flow->type = type; 7410 flow_rxq_flags_set(dev, flow); 7411 rte_free(translated_actions); 7412 tunnel = flow_tunnel_from_rule(wks->flows); 7413 if (tunnel) { 7414 flow->tunnel = 1; 7415 flow->tunnel_id = tunnel->tunnel_id; 7416 __atomic_fetch_add(&tunnel->refctn, 1, __ATOMIC_RELAXED); 7417 mlx5_free(default_miss_ctx.queue); 7418 } 7419 mlx5_flow_pop_thread_workspace(); 7420 return idx; 7421 error: 7422 MLX5_ASSERT(flow); 7423 ret = rte_errno; /* Save rte_errno before cleanup. */ 7424 flow_mreg_del_copy_action(dev, flow); 7425 flow_drv_destroy(dev, flow); 7426 if (rss_desc->shared_rss) 7427 __atomic_fetch_sub(&((struct mlx5_shared_action_rss *) 7428 mlx5_ipool_get 7429 (priv->sh->ipool[MLX5_IPOOL_RSS_SHARED_ACTIONS], 7430 rss_desc->shared_rss))->refcnt, 1, __ATOMIC_RELAXED); 7431 mlx5_ipool_free(priv->flows[type], idx); 7432 rte_errno = ret; /* Restore rte_errno. */ 7433 ret = rte_errno; 7434 rte_errno = ret; 7435 error_before_hairpin_split: 7436 mlx5_flow_pop_thread_workspace(); 7437 rte_free(translated_actions); 7438 return 0; 7439 } 7440 7441 /** 7442 * Create a dedicated flow rule on e-switch table 0 (root table), to direct all 7443 * incoming packets to table 1. 7444 * 7445 * Other flow rules, requested for group n, will be created in 7446 * e-switch table n+1. 7447 * Jump action to e-switch group n will be created to group n+1. 7448 * 7449 * Used when working in switchdev mode, to utilise advantages of table 1 7450 * and above. 7451 * 7452 * @param dev 7453 * Pointer to Ethernet device. 7454 * 7455 * @return 7456 * Pointer to flow on success, NULL otherwise and rte_errno is set. 7457 */ 7458 struct rte_flow * 7459 mlx5_flow_create_esw_table_zero_flow(struct rte_eth_dev *dev) 7460 { 7461 const struct rte_flow_attr attr = { 7462 .group = 0, 7463 .priority = 0, 7464 .ingress = 0, 7465 .egress = 0, 7466 .transfer = 1, 7467 }; 7468 const struct rte_flow_item pattern = { 7469 .type = RTE_FLOW_ITEM_TYPE_END, 7470 }; 7471 struct rte_flow_action_jump jump = { 7472 .group = 1, 7473 }; 7474 const struct rte_flow_action actions[] = { 7475 { 7476 .type = RTE_FLOW_ACTION_TYPE_JUMP, 7477 .conf = &jump, 7478 }, 7479 { 7480 .type = RTE_FLOW_ACTION_TYPE_END, 7481 }, 7482 }; 7483 struct rte_flow_error error; 7484 7485 return (void *)(uintptr_t)flow_list_create(dev, MLX5_FLOW_TYPE_CTL, 7486 &attr, &pattern, 7487 actions, false, &error); 7488 } 7489 7490 /** 7491 * Create a dedicated flow rule on e-switch table 1, matches ESW manager 7492 * and sq number, directs all packets to peer vport. 7493 * 7494 * @param dev 7495 * Pointer to Ethernet device. 7496 * @param sq_num 7497 * SQ number. 7498 * 7499 * @return 7500 * Flow ID on success, 0 otherwise and rte_errno is set. 7501 */ 7502 uint32_t 7503 mlx5_flow_create_devx_sq_miss_flow(struct rte_eth_dev *dev, uint32_t sq_num) 7504 { 7505 struct rte_flow_attr attr = { 7506 .group = 0, 7507 .priority = MLX5_FLOW_LOWEST_PRIO_INDICATOR, 7508 .ingress = 0, 7509 .egress = 0, 7510 .transfer = 1, 7511 }; 7512 struct rte_flow_item_port_id port_spec = { 7513 .id = MLX5_PORT_ESW_MGR, 7514 }; 7515 struct mlx5_rte_flow_item_sq sq_spec = { 7516 .queue = sq_num, 7517 }; 7518 struct rte_flow_item pattern[] = { 7519 { 7520 .type = RTE_FLOW_ITEM_TYPE_PORT_ID, 7521 .spec = &port_spec, 7522 }, 7523 { 7524 .type = (enum rte_flow_item_type) 7525 MLX5_RTE_FLOW_ITEM_TYPE_SQ, 7526 .spec = &sq_spec, 7527 }, 7528 { 7529 .type = RTE_FLOW_ITEM_TYPE_END, 7530 }, 7531 }; 7532 struct rte_flow_action_jump jump = { 7533 .group = 1, 7534 }; 7535 struct rte_flow_action_port_id port = { 7536 .id = dev->data->port_id, 7537 }; 7538 struct rte_flow_action actions[] = { 7539 { 7540 .type = RTE_FLOW_ACTION_TYPE_JUMP, 7541 .conf = &jump, 7542 }, 7543 { 7544 .type = RTE_FLOW_ACTION_TYPE_END, 7545 }, 7546 }; 7547 struct rte_flow_error error; 7548 7549 /* 7550 * Creates group 0, highest priority jump flow. 7551 * Matches txq to bypass kernel packets. 7552 */ 7553 if (flow_list_create(dev, MLX5_FLOW_TYPE_CTL, &attr, pattern, actions, 7554 false, &error) == 0) 7555 return 0; 7556 /* Create group 1, lowest priority redirect flow for txq. */ 7557 attr.group = 1; 7558 actions[0].conf = &port; 7559 actions[0].type = RTE_FLOW_ACTION_TYPE_PORT_ID; 7560 return flow_list_create(dev, MLX5_FLOW_TYPE_CTL, &attr, pattern, 7561 actions, false, &error); 7562 } 7563 7564 /** 7565 * Validate a flow supported by the NIC. 7566 * 7567 * @see rte_flow_validate() 7568 * @see rte_flow_ops 7569 */ 7570 int 7571 mlx5_flow_validate(struct rte_eth_dev *dev, 7572 const struct rte_flow_attr *attr, 7573 const struct rte_flow_item items[], 7574 const struct rte_flow_action original_actions[], 7575 struct rte_flow_error *error) 7576 { 7577 int hairpin_flow; 7578 struct mlx5_translated_action_handle 7579 indir_actions[MLX5_MAX_INDIRECT_ACTIONS]; 7580 int indir_actions_n = MLX5_MAX_INDIRECT_ACTIONS; 7581 const struct rte_flow_action *actions; 7582 struct rte_flow_action *translated_actions = NULL; 7583 int ret = flow_action_handles_translate(dev, original_actions, 7584 indir_actions, 7585 &indir_actions_n, 7586 &translated_actions, error); 7587 7588 if (ret) 7589 return ret; 7590 actions = translated_actions ? translated_actions : original_actions; 7591 hairpin_flow = flow_check_hairpin_split(dev, attr, actions); 7592 ret = flow_drv_validate(dev, attr, items, actions, 7593 true, hairpin_flow, error); 7594 rte_free(translated_actions); 7595 return ret; 7596 } 7597 7598 static int 7599 mlx5_flow_cache_flow_info(struct rte_eth_dev *dev, 7600 const struct rte_flow_attr *attr, 7601 const uint32_t orig_prio, 7602 const struct rte_flow_item *items, 7603 const struct rte_flow_action *actions, 7604 uint32_t flow_idx) 7605 { 7606 struct mlx5_priv *priv = dev->data->dev_private; 7607 struct rte_pmd_mlx5_flow_engine_mode_info *mode_info = &priv->mode_info; 7608 struct mlx5_dv_flow_info *flow_info, *tmp_info; 7609 struct rte_flow_error error; 7610 int len, ret; 7611 7612 flow_info = mlx5_malloc(MLX5_MEM_ZERO, sizeof(*flow_info), 0, SOCKET_ID_ANY); 7613 if (!flow_info) { 7614 DRV_LOG(ERR, "No enough memory for flow_info caching."); 7615 return -1; 7616 } 7617 flow_info->orig_prio = orig_prio; 7618 flow_info->attr = *attr; 7619 /* Standby mode rule awlays saves it in low priority entry. */ 7620 flow_info->flow_idx_low_prio = flow_idx; 7621 7622 /* Store matching items. */ 7623 ret = rte_flow_conv(RTE_FLOW_CONV_OP_PATTERN, NULL, 0, items, &error); 7624 if (ret <= 0) { 7625 DRV_LOG(ERR, "Can't get items length."); 7626 goto end; 7627 } 7628 len = RTE_ALIGN(ret, 16); 7629 flow_info->items = mlx5_malloc(MLX5_MEM_ZERO, len, 0, SOCKET_ID_ANY); 7630 if (!flow_info->items) { 7631 DRV_LOG(ERR, "No enough memory for items caching."); 7632 goto end; 7633 } 7634 ret = rte_flow_conv(RTE_FLOW_CONV_OP_PATTERN, flow_info->items, ret, items, &error); 7635 if (ret <= 0) { 7636 DRV_LOG(ERR, "Can't duplicate items."); 7637 goto end; 7638 } 7639 7640 /* Store flow actions. */ 7641 ret = rte_flow_conv(RTE_FLOW_CONV_OP_ACTIONS, NULL, 0, actions, &error); 7642 if (ret <= 0) { 7643 DRV_LOG(ERR, "Can't get actions length."); 7644 goto end; 7645 } 7646 len = RTE_ALIGN(ret, 16); 7647 flow_info->actions = mlx5_malloc(MLX5_MEM_ZERO, len, 0, SOCKET_ID_ANY); 7648 if (!flow_info->actions) { 7649 DRV_LOG(ERR, "No enough memory for actions caching."); 7650 goto end; 7651 } 7652 ret = rte_flow_conv(RTE_FLOW_CONV_OP_ACTIONS, flow_info->actions, ret, actions, &error); 7653 if (ret <= 0) { 7654 DRV_LOG(ERR, "Can't duplicate actions."); 7655 goto end; 7656 } 7657 7658 /* Insert to the list end. */ 7659 if (LIST_EMPTY(&mode_info->hot_upgrade)) { 7660 LIST_INSERT_HEAD(&mode_info->hot_upgrade, flow_info, next); 7661 } else { 7662 tmp_info = LIST_FIRST(&mode_info->hot_upgrade); 7663 while (LIST_NEXT(tmp_info, next)) 7664 tmp_info = LIST_NEXT(tmp_info, next); 7665 LIST_INSERT_AFTER(tmp_info, flow_info, next); 7666 } 7667 return 0; 7668 end: 7669 if (flow_info->items) 7670 mlx5_free(flow_info->items); 7671 if (flow_info->actions) 7672 mlx5_free(flow_info->actions); 7673 mlx5_free(flow_info); 7674 return -1; 7675 } 7676 7677 static int 7678 mlx5_flow_cache_flow_toggle(struct rte_eth_dev *dev, bool orig_prio) 7679 { 7680 struct mlx5_priv *priv = dev->data->dev_private; 7681 struct rte_pmd_mlx5_flow_engine_mode_info *mode_info = &priv->mode_info; 7682 struct mlx5_dv_flow_info *flow_info; 7683 struct rte_flow_attr attr; 7684 struct rte_flow_error error; 7685 struct rte_flow *high, *low; 7686 7687 flow_info = LIST_FIRST(&mode_info->hot_upgrade); 7688 while (flow_info) { 7689 /* DUP flow may have the same priority. */ 7690 if (flow_info->orig_prio != flow_info->attr.priority) { 7691 attr = flow_info->attr; 7692 if (orig_prio) 7693 attr.priority = flow_info->orig_prio; 7694 flow_info->flow_idx_high_prio = flow_list_create(dev, MLX5_FLOW_TYPE_GEN, 7695 &attr, flow_info->items, flow_info->actions, 7696 true, &error); 7697 if (!flow_info->flow_idx_high_prio) { 7698 DRV_LOG(ERR, "Priority toggle failed internally."); 7699 goto err; 7700 } 7701 } 7702 flow_info = LIST_NEXT(flow_info, next); 7703 } 7704 /* Delete the low priority rules and swap the flow handle. */ 7705 flow_info = LIST_FIRST(&mode_info->hot_upgrade); 7706 while (flow_info) { 7707 MLX5_ASSERT(flow_info->flow_idx_low_prio); 7708 if (flow_info->orig_prio != flow_info->attr.priority) { 7709 high = mlx5_ipool_get(priv->flows[MLX5_FLOW_TYPE_GEN], 7710 flow_info->flow_idx_high_prio); 7711 low = mlx5_ipool_get(priv->flows[MLX5_FLOW_TYPE_GEN], 7712 flow_info->flow_idx_low_prio); 7713 if (high && low) { 7714 RTE_SWAP(*low, *high); 7715 flow_list_destroy(dev, MLX5_FLOW_TYPE_GEN, 7716 flow_info->flow_idx_low_prio); 7717 flow_info->flow_idx_high_prio = 0; 7718 } 7719 } 7720 flow_info = LIST_NEXT(flow_info, next); 7721 } 7722 return 0; 7723 err: 7724 /* Destroy preceding successful high priority rules. */ 7725 flow_info = LIST_FIRST(&mode_info->hot_upgrade); 7726 while (flow_info) { 7727 if (flow_info->orig_prio != flow_info->attr.priority) { 7728 if (flow_info->flow_idx_high_prio) 7729 flow_list_destroy(dev, MLX5_FLOW_TYPE_GEN, 7730 flow_info->flow_idx_high_prio); 7731 else 7732 break; 7733 flow_info->flow_idx_high_prio = 0; 7734 } 7735 flow_info = LIST_NEXT(flow_info, next); 7736 } 7737 return -1; 7738 } 7739 7740 /** 7741 * Set the mode of the flow engine of a process to active or standby during live migration. 7742 * 7743 * @param[in] mode 7744 * MLX5 flow engine mode, @see `enum rte_pmd_mlx5_flow_engine_mode`. 7745 * @param[in] flags 7746 * Flow engine mode specific flags. 7747 * 7748 * @return 7749 * Negative value on error, positive on success. 7750 */ 7751 int 7752 rte_pmd_mlx5_flow_engine_set_mode(enum rte_pmd_mlx5_flow_engine_mode mode, uint32_t flags) 7753 { 7754 struct mlx5_priv *priv; 7755 struct rte_pmd_mlx5_flow_engine_mode_info *mode_info; 7756 struct mlx5_dv_flow_info *flow_info, *tmp_info; 7757 uint16_t port, port_id; 7758 uint16_t toggle_num = 0; 7759 struct rte_eth_dev *dev; 7760 enum rte_pmd_mlx5_flow_engine_mode orig_mode; 7761 uint32_t orig_flags; 7762 bool need_toggle = false; 7763 7764 /* Check if flags combinations are supported. */ 7765 if (flags && flags != RTE_PMD_MLX5_FLOW_ENGINE_FLAG_STANDBY_DUP_INGRESS) { 7766 DRV_LOG(ERR, "Doesn't support such flags %u", flags); 7767 return -1; 7768 } 7769 MLX5_ETH_FOREACH_DEV(port, NULL) { 7770 dev = &rte_eth_devices[port]; 7771 priv = dev->data->dev_private; 7772 mode_info = &priv->mode_info; 7773 /* No mode change. Assume all devices hold the same mode. */ 7774 if (mode_info->mode == mode) { 7775 DRV_LOG(INFO, "Process flow engine has been in mode %u", mode); 7776 if (mode_info->mode_flag != flags && !LIST_EMPTY(&mode_info->hot_upgrade)) { 7777 DRV_LOG(ERR, "Port %u has rule cache with different flag %u\n", 7778 port, mode_info->mode_flag); 7779 orig_mode = mode_info->mode; 7780 orig_flags = mode_info->mode_flag; 7781 goto err; 7782 } 7783 mode_info->mode_flag = flags; 7784 toggle_num++; 7785 continue; 7786 } 7787 /* Active -> standby. */ 7788 if (mode == RTE_PMD_MLX5_FLOW_ENGINE_MODE_STANDBY) { 7789 if (!LIST_EMPTY(&mode_info->hot_upgrade)) { 7790 DRV_LOG(ERR, "Cached rule existed"); 7791 orig_mode = mode_info->mode; 7792 orig_flags = mode_info->mode_flag; 7793 goto err; 7794 } 7795 mode_info->mode_flag = flags; 7796 mode_info->mode = mode; 7797 toggle_num++; 7798 /* Standby -> active. */ 7799 } else if (mode == RTE_PMD_MLX5_FLOW_ENGINE_MODE_ACTIVE) { 7800 if (LIST_EMPTY(&mode_info->hot_upgrade)) { 7801 DRV_LOG(INFO, "No cached rule existed"); 7802 } else { 7803 if (mlx5_flow_cache_flow_toggle(dev, true)) { 7804 orig_mode = mode_info->mode; 7805 orig_flags = mode_info->mode_flag; 7806 need_toggle = true; 7807 goto err; 7808 } 7809 } 7810 toggle_num++; 7811 } 7812 } 7813 if (mode == RTE_PMD_MLX5_FLOW_ENGINE_MODE_ACTIVE) { 7814 /* Clear cache flow rules. */ 7815 MLX5_ETH_FOREACH_DEV(port, NULL) { 7816 priv = rte_eth_devices[port].data->dev_private; 7817 mode_info = &priv->mode_info; 7818 flow_info = LIST_FIRST(&mode_info->hot_upgrade); 7819 while (flow_info) { 7820 tmp_info = LIST_NEXT(flow_info, next); 7821 LIST_REMOVE(flow_info, next); 7822 mlx5_free(flow_info->actions); 7823 mlx5_free(flow_info->items); 7824 mlx5_free(flow_info); 7825 flow_info = tmp_info; 7826 } 7827 MLX5_ASSERT(LIST_EMPTY(&mode_info->hot_upgrade)); 7828 } 7829 } 7830 return toggle_num; 7831 err: 7832 /* Rollback all preceding successful ports. */ 7833 MLX5_ETH_FOREACH_DEV(port_id, NULL) { 7834 if (port_id == port) 7835 break; 7836 priv = rte_eth_devices[port_id].data->dev_private; 7837 mode_info = &priv->mode_info; 7838 if (need_toggle && !LIST_EMPTY(&mode_info->hot_upgrade) && 7839 mlx5_flow_cache_flow_toggle(dev, false)) 7840 return -EPERM; 7841 mode_info->mode = orig_mode; 7842 mode_info->mode_flag = orig_flags; 7843 } 7844 return -EINVAL; 7845 } 7846 /** 7847 * Create a flow. 7848 * 7849 * @see rte_flow_create() 7850 * @see rte_flow_ops 7851 */ 7852 struct rte_flow * 7853 mlx5_flow_create(struct rte_eth_dev *dev, 7854 const struct rte_flow_attr *attr, 7855 const struct rte_flow_item items[], 7856 const struct rte_flow_action actions[], 7857 struct rte_flow_error *error) 7858 { 7859 struct mlx5_priv *priv = dev->data->dev_private; 7860 struct rte_flow_attr *new_attr = (void *)(uintptr_t)attr; 7861 uint32_t prio = attr->priority; 7862 uint32_t flow_idx; 7863 7864 if (priv->sh->config.dv_flow_en == 2) { 7865 rte_flow_error_set(error, ENOTSUP, 7866 RTE_FLOW_ERROR_TYPE_UNSPECIFIED, 7867 NULL, 7868 "Flow non-Q creation not supported"); 7869 return NULL; 7870 } 7871 /* 7872 * If the device is not started yet, it is not allowed to created a 7873 * flow from application. PMD default flows and traffic control flows 7874 * are not affected. 7875 */ 7876 if (unlikely(!dev->data->dev_started)) { 7877 DRV_LOG(DEBUG, "port %u is not started when " 7878 "inserting a flow", dev->data->port_id); 7879 rte_flow_error_set(error, ENODEV, 7880 RTE_FLOW_ERROR_TYPE_UNSPECIFIED, 7881 NULL, 7882 "port not started"); 7883 return NULL; 7884 } 7885 if (unlikely(mlx5_need_cache_flow(priv, attr))) { 7886 if (attr->transfer || 7887 (attr->ingress && !(priv->mode_info.mode_flag & 7888 RTE_PMD_MLX5_FLOW_ENGINE_FLAG_STANDBY_DUP_INGRESS))) 7889 new_attr->priority += 1; 7890 } 7891 flow_idx = flow_list_create(dev, MLX5_FLOW_TYPE_GEN, attr, items, actions, true, error); 7892 if (!flow_idx) 7893 return NULL; 7894 if (unlikely(mlx5_need_cache_flow(priv, attr))) { 7895 if (mlx5_flow_cache_flow_info(dev, attr, prio, items, actions, flow_idx)) { 7896 flow_list_destroy(dev, MLX5_FLOW_TYPE_GEN, flow_idx); 7897 flow_idx = 0; 7898 } 7899 } 7900 return (void *)(uintptr_t)flow_idx; 7901 } 7902 7903 /** 7904 * Destroy a flow in a list. 7905 * 7906 * @param dev 7907 * Pointer to Ethernet device. 7908 * @param[in] flow_idx 7909 * Index of flow to destroy. 7910 */ 7911 static void 7912 flow_list_destroy(struct rte_eth_dev *dev, enum mlx5_flow_type type, 7913 uint32_t flow_idx) 7914 { 7915 struct mlx5_priv *priv = dev->data->dev_private; 7916 struct rte_flow *flow = mlx5_ipool_get(priv->flows[type], flow_idx); 7917 7918 if (!flow) 7919 return; 7920 MLX5_ASSERT(flow->type == type); 7921 /* 7922 * Update RX queue flags only if port is started, otherwise it is 7923 * already clean. 7924 */ 7925 if (dev->data->dev_started) 7926 flow_rxq_flags_trim(dev, flow); 7927 flow_drv_destroy(dev, flow); 7928 if (flow->tunnel) { 7929 struct mlx5_flow_tunnel *tunnel; 7930 7931 tunnel = mlx5_find_tunnel_id(dev, flow->tunnel_id); 7932 RTE_VERIFY(tunnel); 7933 if (!(__atomic_fetch_sub(&tunnel->refctn, 1, __ATOMIC_RELAXED) - 1)) 7934 mlx5_flow_tunnel_free(dev, tunnel); 7935 } 7936 flow_mreg_del_copy_action(dev, flow); 7937 mlx5_ipool_free(priv->flows[type], flow_idx); 7938 } 7939 7940 /** 7941 * Destroy all flows. 7942 * 7943 * @param dev 7944 * Pointer to Ethernet device. 7945 * @param type 7946 * Flow type to be flushed. 7947 * @param active 7948 * If flushing is called actively. 7949 */ 7950 void 7951 mlx5_flow_list_flush(struct rte_eth_dev *dev, enum mlx5_flow_type type, 7952 bool active) 7953 { 7954 struct mlx5_priv *priv = dev->data->dev_private; 7955 uint32_t num_flushed = 0, fidx = 1; 7956 struct rte_flow *flow; 7957 struct rte_pmd_mlx5_flow_engine_mode_info *mode_info = &priv->mode_info; 7958 struct mlx5_dv_flow_info *flow_info; 7959 7960 #ifdef HAVE_IBV_FLOW_DV_SUPPORT 7961 if (priv->sh->config.dv_flow_en == 2 && 7962 type == MLX5_FLOW_TYPE_GEN) { 7963 flow_hw_q_flow_flush(dev, NULL); 7964 return; 7965 } 7966 #endif 7967 7968 MLX5_IPOOL_FOREACH(priv->flows[type], fidx, flow) { 7969 flow_list_destroy(dev, type, fidx); 7970 if (unlikely(mlx5_need_cache_flow(priv, NULL) && type == MLX5_FLOW_TYPE_GEN)) { 7971 flow_info = LIST_FIRST(&mode_info->hot_upgrade); 7972 while (flow_info) { 7973 /* Romove the cache flow info. */ 7974 if (flow_info->flow_idx_low_prio == (uint32_t)(uintptr_t)fidx) { 7975 MLX5_ASSERT(!flow_info->flow_idx_high_prio); 7976 LIST_REMOVE(flow_info, next); 7977 mlx5_free(flow_info->items); 7978 mlx5_free(flow_info->actions); 7979 mlx5_free(flow_info); 7980 break; 7981 } 7982 flow_info = LIST_NEXT(flow_info, next); 7983 } 7984 } 7985 num_flushed++; 7986 } 7987 if (active) { 7988 DRV_LOG(INFO, "port %u: %u flows flushed before stopping", 7989 dev->data->port_id, num_flushed); 7990 } 7991 } 7992 7993 /** 7994 * Stop all default actions for flows. 7995 * 7996 * @param dev 7997 * Pointer to Ethernet device. 7998 */ 7999 void 8000 mlx5_flow_stop_default(struct rte_eth_dev *dev) 8001 { 8002 flow_mreg_del_default_copy_action(dev); 8003 flow_rxq_flags_clear(dev); 8004 } 8005 8006 /** 8007 * Set rxq flag. 8008 * 8009 * @param[in] dev 8010 * Pointer to the rte_eth_dev structure. 8011 * @param[in] enable 8012 * Flag to enable or not. 8013 */ 8014 void 8015 flow_hw_rxq_flag_set(struct rte_eth_dev *dev, bool enable) 8016 { 8017 struct mlx5_priv *priv = dev->data->dev_private; 8018 unsigned int i; 8019 8020 if ((!priv->mark_enabled && !enable) || 8021 (priv->mark_enabled && enable)) 8022 return; 8023 for (i = 0; i < priv->rxqs_n; ++i) { 8024 struct mlx5_rxq_ctrl *rxq_ctrl = mlx5_rxq_ctrl_get(dev, i); 8025 8026 /* With RXQ start/stop feature, RXQ might be stopped. */ 8027 if (!rxq_ctrl) 8028 continue; 8029 rxq_ctrl->rxq.mark = enable; 8030 } 8031 priv->mark_enabled = enable; 8032 } 8033 8034 /** 8035 * Start all default actions for flows. 8036 * 8037 * @param dev 8038 * Pointer to Ethernet device. 8039 * @return 8040 * 0 on success, a negative errno value otherwise and rte_errno is set. 8041 */ 8042 int 8043 mlx5_flow_start_default(struct rte_eth_dev *dev) 8044 { 8045 struct rte_flow_error error; 8046 8047 /* Make sure default copy action (reg_c[0] -> reg_b) is created. */ 8048 return flow_mreg_add_default_copy_action(dev, &error); 8049 } 8050 8051 /** 8052 * Release key of thread specific flow workspace data. 8053 */ 8054 void 8055 flow_release_workspace(void *data) 8056 { 8057 struct mlx5_flow_workspace *wks = data; 8058 struct mlx5_flow_workspace *next; 8059 8060 while (wks) { 8061 next = wks->next; 8062 free(wks); 8063 wks = next; 8064 } 8065 } 8066 8067 /** 8068 * Get thread specific current flow workspace. 8069 * 8070 * @return pointer to thread specific flow workspace data, NULL on error. 8071 */ 8072 struct mlx5_flow_workspace* 8073 mlx5_flow_get_thread_workspace(void) 8074 { 8075 struct mlx5_flow_workspace *data; 8076 8077 data = mlx5_flow_os_get_specific_workspace(); 8078 MLX5_ASSERT(data && data->inuse); 8079 if (!data || !data->inuse) 8080 DRV_LOG(ERR, "flow workspace not initialized."); 8081 return data; 8082 } 8083 8084 /** 8085 * Allocate and init new flow workspace. 8086 * 8087 * @return pointer to flow workspace data, NULL on error. 8088 */ 8089 static struct mlx5_flow_workspace* 8090 flow_alloc_thread_workspace(void) 8091 { 8092 size_t data_size = RTE_ALIGN(sizeof(struct mlx5_flow_workspace), sizeof(long)); 8093 size_t rss_queue_array_size = sizeof(uint16_t) * RTE_ETH_RSS_RETA_SIZE_512; 8094 struct mlx5_flow_workspace *data = calloc(1, data_size + 8095 rss_queue_array_size); 8096 8097 if (!data) { 8098 DRV_LOG(ERR, "Failed to allocate flow workspace memory."); 8099 return NULL; 8100 } 8101 data->rss_desc.queue = RTE_PTR_ADD(data, data_size); 8102 return data; 8103 } 8104 8105 /** 8106 * Get new thread specific flow workspace. 8107 * 8108 * If current workspace inuse, create new one and set as current. 8109 * 8110 * @return pointer to thread specific flow workspace data, NULL on error. 8111 */ 8112 struct mlx5_flow_workspace* 8113 mlx5_flow_push_thread_workspace(void) 8114 { 8115 struct mlx5_flow_workspace *curr; 8116 struct mlx5_flow_workspace *data; 8117 8118 curr = mlx5_flow_os_get_specific_workspace(); 8119 if (!curr) { 8120 data = flow_alloc_thread_workspace(); 8121 if (!data) 8122 return NULL; 8123 mlx5_flow_os_workspace_gc_add(data); 8124 } else if (!curr->inuse) { 8125 data = curr; 8126 } else if (curr->next) { 8127 data = curr->next; 8128 } else { 8129 data = flow_alloc_thread_workspace(); 8130 if (!data) 8131 return NULL; 8132 curr->next = data; 8133 data->prev = curr; 8134 } 8135 data->inuse = 1; 8136 data->flow_idx = 0; 8137 /* Set as current workspace */ 8138 if (mlx5_flow_os_set_specific_workspace(data)) 8139 DRV_LOG(ERR, "Failed to set flow workspace to thread."); 8140 return data; 8141 } 8142 8143 /** 8144 * Close current thread specific flow workspace. 8145 * 8146 * If previous workspace available, set it as current. 8147 * 8148 * @return pointer to thread specific flow workspace data, NULL on error. 8149 */ 8150 void 8151 mlx5_flow_pop_thread_workspace(void) 8152 { 8153 struct mlx5_flow_workspace *data = mlx5_flow_get_thread_workspace(); 8154 8155 if (!data) 8156 return; 8157 if (!data->inuse) { 8158 DRV_LOG(ERR, "Failed to close unused flow workspace."); 8159 return; 8160 } 8161 data->inuse = 0; 8162 if (!data->prev) 8163 return; 8164 if (mlx5_flow_os_set_specific_workspace(data->prev)) 8165 DRV_LOG(ERR, "Failed to set flow workspace to thread."); 8166 } 8167 8168 /** 8169 * Verify the flow list is empty 8170 * 8171 * @param dev 8172 * Pointer to Ethernet device. 8173 * 8174 * @return the number of flows not released. 8175 */ 8176 int 8177 mlx5_flow_verify(struct rte_eth_dev *dev __rte_unused) 8178 { 8179 struct mlx5_priv *priv = dev->data->dev_private; 8180 struct rte_flow *flow; 8181 uint32_t idx = 0; 8182 int ret = 0, i; 8183 8184 for (i = 0; i < MLX5_FLOW_TYPE_MAXI; i++) { 8185 MLX5_IPOOL_FOREACH(priv->flows[i], idx, flow) { 8186 DRV_LOG(DEBUG, "port %u flow %p still referenced", 8187 dev->data->port_id, (void *)flow); 8188 ret++; 8189 } 8190 } 8191 return ret; 8192 } 8193 8194 /** 8195 * Enable default hairpin egress flow. 8196 * 8197 * @param dev 8198 * Pointer to Ethernet device. 8199 * @param sq_num 8200 * The SQ hw number. 8201 * 8202 * @return 8203 * 0 on success, a negative errno value otherwise and rte_errno is set. 8204 */ 8205 int 8206 mlx5_ctrl_flow_source_queue(struct rte_eth_dev *dev, 8207 uint32_t sq_num) 8208 { 8209 const struct rte_flow_attr attr = { 8210 .egress = 1, 8211 .priority = 0, 8212 }; 8213 struct mlx5_rte_flow_item_sq queue_spec = { 8214 .queue = sq_num, 8215 }; 8216 struct mlx5_rte_flow_item_sq queue_mask = { 8217 .queue = UINT32_MAX, 8218 }; 8219 struct rte_flow_item items[] = { 8220 { 8221 .type = (enum rte_flow_item_type) 8222 MLX5_RTE_FLOW_ITEM_TYPE_SQ, 8223 .spec = &queue_spec, 8224 .last = NULL, 8225 .mask = &queue_mask, 8226 }, 8227 { 8228 .type = RTE_FLOW_ITEM_TYPE_END, 8229 }, 8230 }; 8231 struct rte_flow_action_jump jump = { 8232 .group = MLX5_HAIRPIN_TX_TABLE, 8233 }; 8234 struct rte_flow_action actions[2]; 8235 uint32_t flow_idx; 8236 struct rte_flow_error error; 8237 8238 actions[0].type = RTE_FLOW_ACTION_TYPE_JUMP; 8239 actions[0].conf = &jump; 8240 actions[1].type = RTE_FLOW_ACTION_TYPE_END; 8241 flow_idx = flow_list_create(dev, MLX5_FLOW_TYPE_CTL, 8242 &attr, items, actions, false, &error); 8243 if (!flow_idx) { 8244 DRV_LOG(DEBUG, 8245 "Failed to create ctrl flow: rte_errno(%d)," 8246 " type(%d), message(%s)", 8247 rte_errno, error.type, 8248 error.message ? error.message : " (no stated reason)"); 8249 return -rte_errno; 8250 } 8251 return 0; 8252 } 8253 8254 /** 8255 * Enable a control flow configured from the control plane. 8256 * 8257 * @param dev 8258 * Pointer to Ethernet device. 8259 * @param eth_spec 8260 * An Ethernet flow spec to apply. 8261 * @param eth_mask 8262 * An Ethernet flow mask to apply. 8263 * @param vlan_spec 8264 * A VLAN flow spec to apply. 8265 * @param vlan_mask 8266 * A VLAN flow mask to apply. 8267 * 8268 * @return 8269 * 0 on success, a negative errno value otherwise and rte_errno is set. 8270 */ 8271 int 8272 mlx5_ctrl_flow_vlan(struct rte_eth_dev *dev, 8273 struct rte_flow_item_eth *eth_spec, 8274 struct rte_flow_item_eth *eth_mask, 8275 struct rte_flow_item_vlan *vlan_spec, 8276 struct rte_flow_item_vlan *vlan_mask) 8277 { 8278 struct mlx5_priv *priv = dev->data->dev_private; 8279 const struct rte_flow_attr attr = { 8280 .ingress = 1, 8281 .priority = MLX5_FLOW_LOWEST_PRIO_INDICATOR, 8282 }; 8283 struct rte_flow_item items[] = { 8284 { 8285 .type = RTE_FLOW_ITEM_TYPE_ETH, 8286 .spec = eth_spec, 8287 .last = NULL, 8288 .mask = eth_mask, 8289 }, 8290 { 8291 .type = (vlan_spec) ? RTE_FLOW_ITEM_TYPE_VLAN : 8292 RTE_FLOW_ITEM_TYPE_END, 8293 .spec = vlan_spec, 8294 .last = NULL, 8295 .mask = vlan_mask, 8296 }, 8297 { 8298 .type = RTE_FLOW_ITEM_TYPE_END, 8299 }, 8300 }; 8301 uint16_t queue[priv->reta_idx_n]; 8302 struct rte_flow_action_rss action_rss = { 8303 .func = RTE_ETH_HASH_FUNCTION_DEFAULT, 8304 .level = 0, 8305 .types = priv->rss_conf.rss_hf, 8306 .key_len = priv->rss_conf.rss_key_len, 8307 .queue_num = priv->reta_idx_n, 8308 .key = priv->rss_conf.rss_key, 8309 .queue = queue, 8310 }; 8311 struct rte_flow_action actions[] = { 8312 { 8313 .type = RTE_FLOW_ACTION_TYPE_RSS, 8314 .conf = &action_rss, 8315 }, 8316 { 8317 .type = RTE_FLOW_ACTION_TYPE_END, 8318 }, 8319 }; 8320 uint32_t flow_idx; 8321 struct rte_flow_error error; 8322 unsigned int i; 8323 8324 if (!priv->reta_idx_n || !priv->rxqs_n) { 8325 return 0; 8326 } 8327 if (!(dev->data->dev_conf.rxmode.mq_mode & RTE_ETH_MQ_RX_RSS_FLAG)) 8328 action_rss.types = 0; 8329 for (i = 0; i != priv->reta_idx_n; ++i) 8330 queue[i] = (*priv->reta_idx)[i]; 8331 flow_idx = flow_list_create(dev, MLX5_FLOW_TYPE_CTL, 8332 &attr, items, actions, false, &error); 8333 if (!flow_idx) 8334 return -rte_errno; 8335 return 0; 8336 } 8337 8338 /** 8339 * Enable a flow control configured from the control plane. 8340 * 8341 * @param dev 8342 * Pointer to Ethernet device. 8343 * @param eth_spec 8344 * An Ethernet flow spec to apply. 8345 * @param eth_mask 8346 * An Ethernet flow mask to apply. 8347 * 8348 * @return 8349 * 0 on success, a negative errno value otherwise and rte_errno is set. 8350 */ 8351 int 8352 mlx5_ctrl_flow(struct rte_eth_dev *dev, 8353 struct rte_flow_item_eth *eth_spec, 8354 struct rte_flow_item_eth *eth_mask) 8355 { 8356 return mlx5_ctrl_flow_vlan(dev, eth_spec, eth_mask, NULL, NULL); 8357 } 8358 8359 /** 8360 * Create default miss flow rule matching lacp traffic 8361 * 8362 * @param dev 8363 * Pointer to Ethernet device. 8364 * @param eth_spec 8365 * An Ethernet flow spec to apply. 8366 * 8367 * @return 8368 * 0 on success, a negative errno value otherwise and rte_errno is set. 8369 */ 8370 int 8371 mlx5_flow_lacp_miss(struct rte_eth_dev *dev) 8372 { 8373 /* 8374 * The LACP matching is done by only using ether type since using 8375 * a multicast dst mac causes kernel to give low priority to this flow. 8376 */ 8377 static const struct rte_flow_item_eth lacp_spec = { 8378 .hdr.ether_type = RTE_BE16(0x8809), 8379 }; 8380 static const struct rte_flow_item_eth lacp_mask = { 8381 .hdr.ether_type = 0xffff, 8382 }; 8383 const struct rte_flow_attr attr = { 8384 .ingress = 1, 8385 }; 8386 struct rte_flow_item items[] = { 8387 { 8388 .type = RTE_FLOW_ITEM_TYPE_ETH, 8389 .spec = &lacp_spec, 8390 .mask = &lacp_mask, 8391 }, 8392 { 8393 .type = RTE_FLOW_ITEM_TYPE_END, 8394 }, 8395 }; 8396 struct rte_flow_action actions[] = { 8397 { 8398 .type = (enum rte_flow_action_type) 8399 MLX5_RTE_FLOW_ACTION_TYPE_DEFAULT_MISS, 8400 }, 8401 { 8402 .type = RTE_FLOW_ACTION_TYPE_END, 8403 }, 8404 }; 8405 struct rte_flow_error error; 8406 uint32_t flow_idx = flow_list_create(dev, MLX5_FLOW_TYPE_CTL, 8407 &attr, items, actions, 8408 false, &error); 8409 8410 if (!flow_idx) 8411 return -rte_errno; 8412 return 0; 8413 } 8414 8415 /** 8416 * Destroy a flow. 8417 * 8418 * @see rte_flow_destroy() 8419 * @see rte_flow_ops 8420 */ 8421 int 8422 mlx5_flow_destroy(struct rte_eth_dev *dev, 8423 struct rte_flow *flow, 8424 struct rte_flow_error *error __rte_unused) 8425 { 8426 struct mlx5_priv *priv = dev->data->dev_private; 8427 struct rte_pmd_mlx5_flow_engine_mode_info *mode_info = &priv->mode_info; 8428 struct mlx5_dv_flow_info *flow_info; 8429 8430 if (priv->sh->config.dv_flow_en == 2) 8431 return rte_flow_error_set(error, ENOTSUP, 8432 RTE_FLOW_ERROR_TYPE_UNSPECIFIED, 8433 NULL, 8434 "Flow non-Q destruction not supported"); 8435 flow_list_destroy(dev, MLX5_FLOW_TYPE_GEN, 8436 (uintptr_t)(void *)flow); 8437 if (unlikely(mlx5_need_cache_flow(priv, NULL))) { 8438 flow_info = LIST_FIRST(&mode_info->hot_upgrade); 8439 while (flow_info) { 8440 /* Romove the cache flow info. */ 8441 if (flow_info->flow_idx_low_prio == (uint32_t)(uintptr_t)flow) { 8442 MLX5_ASSERT(!flow_info->flow_idx_high_prio); 8443 LIST_REMOVE(flow_info, next); 8444 mlx5_free(flow_info->items); 8445 mlx5_free(flow_info->actions); 8446 mlx5_free(flow_info); 8447 break; 8448 } 8449 flow_info = LIST_NEXT(flow_info, next); 8450 } 8451 } 8452 return 0; 8453 } 8454 8455 /** 8456 * Destroy all flows. 8457 * 8458 * @see rte_flow_flush() 8459 * @see rte_flow_ops 8460 */ 8461 int 8462 mlx5_flow_flush(struct rte_eth_dev *dev, 8463 struct rte_flow_error *error __rte_unused) 8464 { 8465 mlx5_flow_list_flush(dev, MLX5_FLOW_TYPE_GEN, false); 8466 return 0; 8467 } 8468 8469 /** 8470 * Isolated mode. 8471 * 8472 * @see rte_flow_isolate() 8473 * @see rte_flow_ops 8474 */ 8475 int 8476 mlx5_flow_isolate(struct rte_eth_dev *dev, 8477 int enable, 8478 struct rte_flow_error *error) 8479 { 8480 struct mlx5_priv *priv = dev->data->dev_private; 8481 8482 if (dev->data->dev_started) { 8483 rte_flow_error_set(error, EBUSY, 8484 RTE_FLOW_ERROR_TYPE_UNSPECIFIED, 8485 NULL, 8486 "port must be stopped first"); 8487 return -rte_errno; 8488 } 8489 if (!enable && !priv->sh->config.repr_matching) 8490 return rte_flow_error_set(error, ENOTSUP, RTE_FLOW_ERROR_TYPE_UNSPECIFIED, NULL, 8491 "isolated mode cannot be disabled when " 8492 "representor matching is disabled"); 8493 priv->isolated = !!enable; 8494 if (enable) 8495 dev->dev_ops = &mlx5_dev_ops_isolate; 8496 else 8497 dev->dev_ops = &mlx5_dev_ops; 8498 8499 dev->rx_descriptor_status = mlx5_rx_descriptor_status; 8500 dev->tx_descriptor_status = mlx5_tx_descriptor_status; 8501 8502 return 0; 8503 } 8504 8505 /** 8506 * Query a flow. 8507 * 8508 * @see rte_flow_query() 8509 * @see rte_flow_ops 8510 */ 8511 static int 8512 flow_drv_query(struct rte_eth_dev *dev, 8513 struct rte_flow *eflow, 8514 const struct rte_flow_action *actions, 8515 void *data, 8516 struct rte_flow_error *error) 8517 { 8518 struct mlx5_priv *priv = dev->data->dev_private; 8519 const struct mlx5_flow_driver_ops *fops; 8520 struct rte_flow *flow = NULL; 8521 enum mlx5_flow_drv_type ftype = MLX5_FLOW_TYPE_MIN; 8522 8523 if (priv->sh->config.dv_flow_en == 2) { 8524 #ifdef HAVE_MLX5_HWS_SUPPORT 8525 flow = eflow; 8526 ftype = MLX5_FLOW_TYPE_HW; 8527 #endif 8528 } else { 8529 flow = (struct rte_flow *)mlx5_ipool_get(priv->flows[MLX5_FLOW_TYPE_GEN], 8530 (uintptr_t)(void *)eflow); 8531 } 8532 if (!flow) { 8533 return rte_flow_error_set(error, ENOENT, 8534 RTE_FLOW_ERROR_TYPE_UNSPECIFIED, 8535 NULL, 8536 "invalid flow handle"); 8537 } 8538 if (ftype == MLX5_FLOW_TYPE_MIN) 8539 ftype = flow->drv_type; 8540 MLX5_ASSERT(ftype > MLX5_FLOW_TYPE_MIN && ftype < MLX5_FLOW_TYPE_MAX); 8541 fops = flow_get_drv_ops(ftype); 8542 8543 return fops->query(dev, flow, actions, data, error); 8544 } 8545 8546 /** 8547 * Query a flow. 8548 * 8549 * @see rte_flow_query() 8550 * @see rte_flow_ops 8551 */ 8552 int 8553 mlx5_flow_query(struct rte_eth_dev *dev, 8554 struct rte_flow *flow, 8555 const struct rte_flow_action *actions, 8556 void *data, 8557 struct rte_flow_error *error) 8558 { 8559 int ret; 8560 8561 ret = flow_drv_query(dev, flow, actions, data, 8562 error); 8563 if (ret < 0) 8564 return ret; 8565 return 0; 8566 } 8567 8568 /** 8569 * Get rte_flow callbacks. 8570 * 8571 * @param dev 8572 * Pointer to Ethernet device structure. 8573 * @param ops 8574 * Pointer to operation-specific structure. 8575 * 8576 * @return 0 8577 */ 8578 int 8579 mlx5_flow_ops_get(struct rte_eth_dev *dev __rte_unused, 8580 const struct rte_flow_ops **ops) 8581 { 8582 *ops = &mlx5_flow_ops; 8583 return 0; 8584 } 8585 8586 /** 8587 * Validate meter policy actions. 8588 * Dispatcher for action type specific validation. 8589 * 8590 * @param[in] dev 8591 * Pointer to the Ethernet device structure. 8592 * @param[in] action 8593 * The meter policy action object to validate. 8594 * @param[in] attr 8595 * Attributes of flow to determine steering domain. 8596 * @param[out] is_rss 8597 * Is RSS or not. 8598 * @param[out] domain_bitmap 8599 * Domain bitmap. 8600 * @param[out] is_def_policy 8601 * Is default policy or not. 8602 * @param[out] error 8603 * Perform verbose error reporting if not NULL. Initialized in case of 8604 * error only. 8605 * 8606 * @return 8607 * 0 on success, otherwise negative errno value. 8608 */ 8609 int 8610 mlx5_flow_validate_mtr_acts(struct rte_eth_dev *dev, 8611 const struct rte_flow_action *actions[RTE_COLORS], 8612 struct rte_flow_attr *attr, 8613 bool *is_rss, 8614 uint8_t *domain_bitmap, 8615 uint8_t *policy_mode, 8616 struct rte_mtr_error *error) 8617 { 8618 const struct mlx5_flow_driver_ops *fops; 8619 8620 fops = flow_get_drv_ops(MLX5_FLOW_TYPE_DV); 8621 return fops->validate_mtr_acts(dev, actions, attr, is_rss, 8622 domain_bitmap, policy_mode, error); 8623 } 8624 8625 /** 8626 * Destroy the meter table set. 8627 * 8628 * @param[in] dev 8629 * Pointer to Ethernet device. 8630 * @param[in] mtr_policy 8631 * Meter policy struct. 8632 */ 8633 void 8634 mlx5_flow_destroy_mtr_acts(struct rte_eth_dev *dev, 8635 struct mlx5_flow_meter_policy *mtr_policy) 8636 { 8637 const struct mlx5_flow_driver_ops *fops; 8638 8639 fops = flow_get_drv_ops(MLX5_FLOW_TYPE_DV); 8640 fops->destroy_mtr_acts(dev, mtr_policy); 8641 } 8642 8643 /** 8644 * Create policy action, lock free, 8645 * (mutex should be acquired by caller). 8646 * Dispatcher for action type specific call. 8647 * 8648 * @param[in] dev 8649 * Pointer to the Ethernet device structure. 8650 * @param[in] mtr_policy 8651 * Meter policy struct. 8652 * @param[in] action 8653 * Action specification used to create meter actions. 8654 * @param[in] attr 8655 * Flow rule attributes. 8656 * @param[out] error 8657 * Perform verbose error reporting if not NULL. Initialized in case of 8658 * error only. 8659 * 8660 * @return 8661 * 0 on success, otherwise negative errno value. 8662 */ 8663 int 8664 mlx5_flow_create_mtr_acts(struct rte_eth_dev *dev, 8665 struct mlx5_flow_meter_policy *mtr_policy, 8666 const struct rte_flow_action *actions[RTE_COLORS], 8667 struct rte_flow_attr *attr, 8668 struct rte_mtr_error *error) 8669 { 8670 const struct mlx5_flow_driver_ops *fops; 8671 8672 fops = flow_get_drv_ops(MLX5_FLOW_TYPE_DV); 8673 return fops->create_mtr_acts(dev, mtr_policy, actions, attr, error); 8674 } 8675 8676 /** 8677 * Create policy rules, lock free, 8678 * (mutex should be acquired by caller). 8679 * Dispatcher for action type specific call. 8680 * 8681 * @param[in] dev 8682 * Pointer to the Ethernet device structure. 8683 * @param[in] mtr_policy 8684 * Meter policy struct. 8685 * 8686 * @return 8687 * 0 on success, -1 otherwise. 8688 */ 8689 int 8690 mlx5_flow_create_policy_rules(struct rte_eth_dev *dev, 8691 struct mlx5_flow_meter_policy *mtr_policy) 8692 { 8693 const struct mlx5_flow_driver_ops *fops; 8694 8695 fops = flow_get_drv_ops(MLX5_FLOW_TYPE_DV); 8696 return fops->create_policy_rules(dev, mtr_policy); 8697 } 8698 8699 /** 8700 * Destroy policy rules, lock free, 8701 * (mutex should be acquired by caller). 8702 * Dispatcher for action type specific call. 8703 * 8704 * @param[in] dev 8705 * Pointer to the Ethernet device structure. 8706 * @param[in] mtr_policy 8707 * Meter policy struct. 8708 */ 8709 void 8710 mlx5_flow_destroy_policy_rules(struct rte_eth_dev *dev, 8711 struct mlx5_flow_meter_policy *mtr_policy) 8712 { 8713 const struct mlx5_flow_driver_ops *fops; 8714 8715 fops = flow_get_drv_ops(MLX5_FLOW_TYPE_DV); 8716 fops->destroy_policy_rules(dev, mtr_policy); 8717 } 8718 8719 /** 8720 * Destroy the default policy table set. 8721 * 8722 * @param[in] dev 8723 * Pointer to Ethernet device. 8724 */ 8725 void 8726 mlx5_flow_destroy_def_policy(struct rte_eth_dev *dev) 8727 { 8728 const struct mlx5_flow_driver_ops *fops; 8729 8730 fops = flow_get_drv_ops(MLX5_FLOW_TYPE_DV); 8731 fops->destroy_def_policy(dev); 8732 } 8733 8734 /** 8735 * Destroy the default policy table set. 8736 * 8737 * @param[in] dev 8738 * Pointer to Ethernet device. 8739 * 8740 * @return 8741 * 0 on success, -1 otherwise. 8742 */ 8743 int 8744 mlx5_flow_create_def_policy(struct rte_eth_dev *dev) 8745 { 8746 const struct mlx5_flow_driver_ops *fops; 8747 8748 fops = flow_get_drv_ops(MLX5_FLOW_TYPE_DV); 8749 return fops->create_def_policy(dev); 8750 } 8751 8752 /** 8753 * Create the needed meter and suffix tables. 8754 * 8755 * @param[in] dev 8756 * Pointer to Ethernet device. 8757 * 8758 * @return 8759 * 0 on success, -1 otherwise. 8760 */ 8761 int 8762 mlx5_flow_create_mtr_tbls(struct rte_eth_dev *dev, 8763 struct mlx5_flow_meter_info *fm, 8764 uint32_t mtr_idx, 8765 uint8_t domain_bitmap) 8766 { 8767 const struct mlx5_flow_driver_ops *fops; 8768 8769 fops = flow_get_drv_ops(MLX5_FLOW_TYPE_DV); 8770 return fops->create_mtr_tbls(dev, fm, mtr_idx, domain_bitmap); 8771 } 8772 8773 /** 8774 * Destroy the meter table set. 8775 * 8776 * @param[in] dev 8777 * Pointer to Ethernet device. 8778 * @param[in] tbl 8779 * Pointer to the meter table set. 8780 */ 8781 void 8782 mlx5_flow_destroy_mtr_tbls(struct rte_eth_dev *dev, 8783 struct mlx5_flow_meter_info *fm) 8784 { 8785 const struct mlx5_flow_driver_ops *fops; 8786 8787 fops = flow_get_drv_ops(MLX5_FLOW_TYPE_DV); 8788 fops->destroy_mtr_tbls(dev, fm); 8789 } 8790 8791 /** 8792 * Destroy the global meter drop table. 8793 * 8794 * @param[in] dev 8795 * Pointer to Ethernet device. 8796 */ 8797 void 8798 mlx5_flow_destroy_mtr_drop_tbls(struct rte_eth_dev *dev) 8799 { 8800 const struct mlx5_flow_driver_ops *fops; 8801 8802 fops = flow_get_drv_ops(MLX5_FLOW_TYPE_DV); 8803 fops->destroy_mtr_drop_tbls(dev); 8804 } 8805 8806 /** 8807 * Destroy the sub policy table with RX queue. 8808 * 8809 * @param[in] dev 8810 * Pointer to Ethernet device. 8811 * @param[in] mtr_policy 8812 * Pointer to meter policy table. 8813 */ 8814 void 8815 mlx5_flow_destroy_sub_policy_with_rxq(struct rte_eth_dev *dev, 8816 struct mlx5_flow_meter_policy *mtr_policy) 8817 { 8818 const struct mlx5_flow_driver_ops *fops; 8819 8820 fops = flow_get_drv_ops(MLX5_FLOW_TYPE_DV); 8821 fops->destroy_sub_policy_with_rxq(dev, mtr_policy); 8822 } 8823 8824 /** 8825 * Allocate the needed aso flow meter id. 8826 * 8827 * @param[in] dev 8828 * Pointer to Ethernet device. 8829 * 8830 * @return 8831 * Index to aso flow meter on success, NULL otherwise. 8832 */ 8833 uint32_t 8834 mlx5_flow_mtr_alloc(struct rte_eth_dev *dev) 8835 { 8836 const struct mlx5_flow_driver_ops *fops; 8837 8838 fops = flow_get_drv_ops(MLX5_FLOW_TYPE_DV); 8839 return fops->create_meter(dev); 8840 } 8841 8842 /** 8843 * Free the aso flow meter id. 8844 * 8845 * @param[in] dev 8846 * Pointer to Ethernet device. 8847 * @param[in] mtr_idx 8848 * Index to aso flow meter to be free. 8849 * 8850 * @return 8851 * 0 on success. 8852 */ 8853 void 8854 mlx5_flow_mtr_free(struct rte_eth_dev *dev, uint32_t mtr_idx) 8855 { 8856 const struct mlx5_flow_driver_ops *fops; 8857 8858 fops = flow_get_drv_ops(MLX5_FLOW_TYPE_DV); 8859 fops->free_meter(dev, mtr_idx); 8860 } 8861 8862 /** 8863 * Allocate a counter. 8864 * 8865 * @param[in] dev 8866 * Pointer to Ethernet device structure. 8867 * 8868 * @return 8869 * Index to allocated counter on success, 0 otherwise. 8870 */ 8871 uint32_t 8872 mlx5_counter_alloc(struct rte_eth_dev *dev) 8873 { 8874 struct rte_flow_attr attr = { .transfer = 0 }; 8875 8876 return flow_get_drv_ops(flow_get_drv_type(dev, &attr))->counter_alloc 8877 (dev); 8878 } 8879 8880 /** 8881 * Free a counter. 8882 * 8883 * @param[in] dev 8884 * Pointer to Ethernet device structure. 8885 * @param[in] cnt 8886 * Index to counter to be free. 8887 */ 8888 void 8889 mlx5_counter_free(struct rte_eth_dev *dev, uint32_t cnt) 8890 { 8891 struct rte_flow_attr attr = { .transfer = 0 }; 8892 8893 flow_get_drv_ops(flow_get_drv_type(dev, &attr))->counter_free(dev, cnt); 8894 } 8895 8896 /** 8897 * Query counter statistics. 8898 * 8899 * @param[in] dev 8900 * Pointer to Ethernet device structure. 8901 * @param[in] cnt 8902 * Index to counter to query. 8903 * @param[in] clear 8904 * Set to clear counter statistics. 8905 * @param[out] pkts 8906 * The counter hits packets number to save. 8907 * @param[out] bytes 8908 * The counter hits bytes number to save. 8909 * 8910 * @return 8911 * 0 on success, a negative errno value otherwise. 8912 */ 8913 int 8914 mlx5_counter_query(struct rte_eth_dev *dev, uint32_t cnt, 8915 bool clear, uint64_t *pkts, uint64_t *bytes, void **action) 8916 { 8917 struct rte_flow_attr attr = { .transfer = 0 }; 8918 8919 return flow_get_drv_ops(flow_get_drv_type(dev, &attr))->counter_query 8920 (dev, cnt, clear, pkts, bytes, action); 8921 } 8922 8923 /** 8924 * Get information about HWS pre-configurable resources. 8925 * 8926 * @param[in] dev 8927 * Pointer to the rte_eth_dev structure. 8928 * @param[out] port_info 8929 * Pointer to port information. 8930 * @param[out] queue_info 8931 * Pointer to queue information. 8932 * @param[out] error 8933 * Pointer to error structure. 8934 * 8935 * @return 8936 * 0 on success, a negative errno value otherwise and rte_errno is set. 8937 */ 8938 static int 8939 mlx5_flow_info_get(struct rte_eth_dev *dev, 8940 struct rte_flow_port_info *port_info, 8941 struct rte_flow_queue_info *queue_info, 8942 struct rte_flow_error *error) 8943 { 8944 const struct mlx5_flow_driver_ops *fops; 8945 struct rte_flow_attr attr = {0}; 8946 8947 if (flow_get_drv_type(dev, &attr) != MLX5_FLOW_TYPE_HW) 8948 return rte_flow_error_set(error, ENOTSUP, 8949 RTE_FLOW_ERROR_TYPE_UNSPECIFIED, 8950 NULL, 8951 "info get with incorrect steering mode"); 8952 fops = flow_get_drv_ops(MLX5_FLOW_TYPE_HW); 8953 return fops->info_get(dev, port_info, queue_info, error); 8954 } 8955 8956 /** 8957 * Configure port HWS resources. 8958 * 8959 * @param[in] dev 8960 * Pointer to the rte_eth_dev structure. 8961 * @param[in] port_attr 8962 * Port configuration attributes. 8963 * @param[in] nb_queue 8964 * Number of queue. 8965 * @param[in] queue_attr 8966 * Array that holds attributes for each flow queue. 8967 * @param[out] error 8968 * Pointer to error structure. 8969 * 8970 * @return 8971 * 0 on success, a negative errno value otherwise and rte_errno is set. 8972 */ 8973 static int 8974 mlx5_flow_port_configure(struct rte_eth_dev *dev, 8975 const struct rte_flow_port_attr *port_attr, 8976 uint16_t nb_queue, 8977 const struct rte_flow_queue_attr *queue_attr[], 8978 struct rte_flow_error *error) 8979 { 8980 const struct mlx5_flow_driver_ops *fops; 8981 struct rte_flow_attr attr = {0}; 8982 8983 if (flow_get_drv_type(dev, &attr) != MLX5_FLOW_TYPE_HW) 8984 return rte_flow_error_set(error, ENOTSUP, 8985 RTE_FLOW_ERROR_TYPE_UNSPECIFIED, 8986 NULL, 8987 "port configure with incorrect steering mode"); 8988 fops = flow_get_drv_ops(MLX5_FLOW_TYPE_HW); 8989 return fops->configure(dev, port_attr, nb_queue, queue_attr, error); 8990 } 8991 8992 /** 8993 * Validate item template. 8994 * 8995 * @param[in] dev 8996 * Pointer to the rte_eth_dev structure. 8997 * @param[in] attr 8998 * Pointer to the item template attributes. 8999 * @param[in] items 9000 * The template item pattern. 9001 * @param[out] error 9002 * Pointer to error structure. 9003 * 9004 * @return 9005 * 0 on success, a negative errno value otherwise and rte_errno is set. 9006 */ 9007 int 9008 mlx5_flow_pattern_validate(struct rte_eth_dev *dev, 9009 const struct rte_flow_pattern_template_attr *attr, 9010 const struct rte_flow_item items[], 9011 struct rte_flow_error *error) 9012 { 9013 const struct mlx5_flow_driver_ops *fops; 9014 struct rte_flow_attr fattr = {0}; 9015 9016 if (flow_get_drv_type(dev, &fattr) != MLX5_FLOW_TYPE_HW) { 9017 rte_flow_error_set(error, ENOTSUP, 9018 RTE_FLOW_ERROR_TYPE_UNSPECIFIED, NULL, 9019 "pattern validate with incorrect steering mode"); 9020 return -ENOTSUP; 9021 } 9022 fops = flow_get_drv_ops(MLX5_FLOW_TYPE_HW); 9023 return fops->pattern_validate(dev, attr, items, error); 9024 } 9025 9026 /** 9027 * Create flow item template. 9028 * 9029 * @param[in] dev 9030 * Pointer to the rte_eth_dev structure. 9031 * @param[in] attr 9032 * Pointer to the item template attributes. 9033 * @param[in] items 9034 * The template item pattern. 9035 * @param[out] error 9036 * Pointer to error structure. 9037 * 9038 * @return 9039 * 0 on success, a negative errno value otherwise and rte_errno is set. 9040 */ 9041 static struct rte_flow_pattern_template * 9042 mlx5_flow_pattern_template_create(struct rte_eth_dev *dev, 9043 const struct rte_flow_pattern_template_attr *attr, 9044 const struct rte_flow_item items[], 9045 struct rte_flow_error *error) 9046 { 9047 const struct mlx5_flow_driver_ops *fops; 9048 struct rte_flow_attr fattr = {0}; 9049 9050 if (flow_get_drv_type(dev, &fattr) != MLX5_FLOW_TYPE_HW) { 9051 rte_flow_error_set(error, ENOTSUP, 9052 RTE_FLOW_ERROR_TYPE_UNSPECIFIED, 9053 NULL, 9054 "pattern create with incorrect steering mode"); 9055 return NULL; 9056 } 9057 fops = flow_get_drv_ops(MLX5_FLOW_TYPE_HW); 9058 return fops->pattern_template_create(dev, attr, items, error); 9059 } 9060 9061 /** 9062 * Destroy flow item template. 9063 * 9064 * @param[in] dev 9065 * Pointer to the rte_eth_dev structure. 9066 * @param[in] template 9067 * Pointer to the item template to be destroyed. 9068 * @param[out] error 9069 * Pointer to error structure. 9070 * 9071 * @return 9072 * 0 on success, a negative errno value otherwise and rte_errno is set. 9073 */ 9074 static int 9075 mlx5_flow_pattern_template_destroy(struct rte_eth_dev *dev, 9076 struct rte_flow_pattern_template *template, 9077 struct rte_flow_error *error) 9078 { 9079 const struct mlx5_flow_driver_ops *fops; 9080 struct rte_flow_attr attr = {0}; 9081 9082 if (flow_get_drv_type(dev, &attr) != MLX5_FLOW_TYPE_HW) 9083 return rte_flow_error_set(error, ENOTSUP, 9084 RTE_FLOW_ERROR_TYPE_UNSPECIFIED, 9085 NULL, 9086 "pattern destroy with incorrect steering mode"); 9087 fops = flow_get_drv_ops(MLX5_FLOW_TYPE_HW); 9088 return fops->pattern_template_destroy(dev, template, error); 9089 } 9090 9091 /** 9092 * Validate flow actions template. 9093 * 9094 * @param[in] dev 9095 * Pointer to the rte_eth_dev structure. 9096 * @param[in] attr 9097 * Pointer to the action template attributes. 9098 * @param[in] actions 9099 * Associated actions (list terminated by the END action). 9100 * @param[in] masks 9101 * List of actions that marks which of the action's member is constant. 9102 * @param[out] error 9103 * Pointer to error structure. 9104 * 9105 * @return 9106 * 0 on success, a negative errno value otherwise and rte_errno is set. 9107 */ 9108 int 9109 mlx5_flow_actions_validate(struct rte_eth_dev *dev, 9110 const struct rte_flow_actions_template_attr *attr, 9111 const struct rte_flow_action actions[], 9112 const struct rte_flow_action masks[], 9113 struct rte_flow_error *error) 9114 { 9115 const struct mlx5_flow_driver_ops *fops; 9116 struct rte_flow_attr fattr = {0}; 9117 9118 if (flow_get_drv_type(dev, &fattr) != MLX5_FLOW_TYPE_HW) { 9119 rte_flow_error_set(error, ENOTSUP, 9120 RTE_FLOW_ERROR_TYPE_UNSPECIFIED, NULL, 9121 "actions validate with incorrect steering mode"); 9122 return -ENOTSUP; 9123 } 9124 fops = flow_get_drv_ops(MLX5_FLOW_TYPE_HW); 9125 return fops->actions_validate(dev, attr, actions, masks, error); 9126 } 9127 9128 /** 9129 * Create flow item template. 9130 * 9131 * @param[in] dev 9132 * Pointer to the rte_eth_dev structure. 9133 * @param[in] attr 9134 * Pointer to the action template attributes. 9135 * @param[in] actions 9136 * Associated actions (list terminated by the END action). 9137 * @param[in] masks 9138 * List of actions that marks which of the action's member is constant. 9139 * @param[out] error 9140 * Pointer to error structure. 9141 * 9142 * @return 9143 * 0 on success, a negative errno value otherwise and rte_errno is set. 9144 */ 9145 static struct rte_flow_actions_template * 9146 mlx5_flow_actions_template_create(struct rte_eth_dev *dev, 9147 const struct rte_flow_actions_template_attr *attr, 9148 const struct rte_flow_action actions[], 9149 const struct rte_flow_action masks[], 9150 struct rte_flow_error *error) 9151 { 9152 const struct mlx5_flow_driver_ops *fops; 9153 struct rte_flow_attr fattr = {0}; 9154 9155 if (flow_get_drv_type(dev, &fattr) != MLX5_FLOW_TYPE_HW) { 9156 rte_flow_error_set(error, ENOTSUP, 9157 RTE_FLOW_ERROR_TYPE_UNSPECIFIED, 9158 NULL, 9159 "action create with incorrect steering mode"); 9160 return NULL; 9161 } 9162 fops = flow_get_drv_ops(MLX5_FLOW_TYPE_HW); 9163 return fops->actions_template_create(dev, attr, actions, masks, error); 9164 } 9165 9166 /** 9167 * Destroy flow action template. 9168 * 9169 * @param[in] dev 9170 * Pointer to the rte_eth_dev structure. 9171 * @param[in] template 9172 * Pointer to the action template to be destroyed. 9173 * @param[out] error 9174 * Pointer to error structure. 9175 * 9176 * @return 9177 * 0 on success, a negative errno value otherwise and rte_errno is set. 9178 */ 9179 static int 9180 mlx5_flow_actions_template_destroy(struct rte_eth_dev *dev, 9181 struct rte_flow_actions_template *template, 9182 struct rte_flow_error *error) 9183 { 9184 const struct mlx5_flow_driver_ops *fops; 9185 struct rte_flow_attr attr = {0}; 9186 9187 if (flow_get_drv_type(dev, &attr) != MLX5_FLOW_TYPE_HW) 9188 return rte_flow_error_set(error, ENOTSUP, 9189 RTE_FLOW_ERROR_TYPE_UNSPECIFIED, 9190 NULL, 9191 "action destroy with incorrect steering mode"); 9192 fops = flow_get_drv_ops(MLX5_FLOW_TYPE_HW); 9193 return fops->actions_template_destroy(dev, template, error); 9194 } 9195 9196 /** 9197 * Create flow table. 9198 * 9199 * @param[in] dev 9200 * Pointer to the rte_eth_dev structure. 9201 * @param[in] attr 9202 * Pointer to the table attributes. 9203 * @param[in] item_templates 9204 * Item template array to be binded to the table. 9205 * @param[in] nb_item_templates 9206 * Number of item template. 9207 * @param[in] action_templates 9208 * Action template array to be binded to the table. 9209 * @param[in] nb_action_templates 9210 * Number of action template. 9211 * @param[out] error 9212 * Pointer to error structure. 9213 * 9214 * @return 9215 * Table on success, NULL otherwise and rte_errno is set. 9216 */ 9217 static struct rte_flow_template_table * 9218 mlx5_flow_table_create(struct rte_eth_dev *dev, 9219 const struct rte_flow_template_table_attr *attr, 9220 struct rte_flow_pattern_template *item_templates[], 9221 uint8_t nb_item_templates, 9222 struct rte_flow_actions_template *action_templates[], 9223 uint8_t nb_action_templates, 9224 struct rte_flow_error *error) 9225 { 9226 const struct mlx5_flow_driver_ops *fops; 9227 struct rte_flow_attr fattr = {0}; 9228 9229 if (flow_get_drv_type(dev, &fattr) != MLX5_FLOW_TYPE_HW) { 9230 rte_flow_error_set(error, ENOTSUP, 9231 RTE_FLOW_ERROR_TYPE_UNSPECIFIED, 9232 NULL, 9233 "table create with incorrect steering mode"); 9234 return NULL; 9235 } 9236 fops = flow_get_drv_ops(MLX5_FLOW_TYPE_HW); 9237 return fops->template_table_create(dev, 9238 attr, 9239 item_templates, 9240 nb_item_templates, 9241 action_templates, 9242 nb_action_templates, 9243 error); 9244 } 9245 9246 /** 9247 * PMD destroy flow table. 9248 * 9249 * @param[in] dev 9250 * Pointer to the rte_eth_dev structure. 9251 * @param[in] table 9252 * Pointer to the table to be destroyed. 9253 * @param[out] error 9254 * Pointer to error structure. 9255 * 9256 * @return 9257 * 0 on success, a negative errno value otherwise and rte_errno is set. 9258 */ 9259 static int 9260 mlx5_flow_table_destroy(struct rte_eth_dev *dev, 9261 struct rte_flow_template_table *table, 9262 struct rte_flow_error *error) 9263 { 9264 const struct mlx5_flow_driver_ops *fops; 9265 struct rte_flow_attr attr = {0}; 9266 9267 if (flow_get_drv_type(dev, &attr) != MLX5_FLOW_TYPE_HW) 9268 return rte_flow_error_set(error, ENOTSUP, 9269 RTE_FLOW_ERROR_TYPE_UNSPECIFIED, 9270 NULL, 9271 "table destroy with incorrect steering mode"); 9272 fops = flow_get_drv_ops(MLX5_FLOW_TYPE_HW); 9273 return fops->template_table_destroy(dev, table, error); 9274 } 9275 9276 /** 9277 * PMD group set miss actions. 9278 * 9279 * @param[in] dev 9280 * Pointer to the rte_eth_dev structure. 9281 * @param[in] attr 9282 * Pointer to group attributes 9283 * @param[in] actions 9284 * Array of actions 9285 * @param[out] error 9286 * Pointer to error structure. 9287 * 9288 * @return 9289 * 0 on success, a negative errno value otherwise and rte_errno is set. 9290 */ 9291 static int 9292 mlx5_flow_group_set_miss_actions(struct rte_eth_dev *dev, 9293 uint32_t group_id, 9294 const struct rte_flow_group_attr *attr, 9295 const struct rte_flow_action actions[], 9296 struct rte_flow_error *error) 9297 { 9298 const struct mlx5_flow_driver_ops *fops; 9299 struct rte_flow_attr fattr = {0}; 9300 9301 if (flow_get_drv_type(dev, &fattr) != MLX5_FLOW_TYPE_HW) 9302 return rte_flow_error_set(error, ENOTSUP, 9303 RTE_FLOW_ERROR_TYPE_UNSPECIFIED, 9304 NULL, 9305 "group set miss actions with incorrect steering mode"); 9306 fops = flow_get_drv_ops(MLX5_FLOW_TYPE_HW); 9307 return fops->group_set_miss_actions(dev, group_id, attr, actions, error); 9308 } 9309 9310 /** 9311 * Allocate a new memory for the counter values wrapped by all the needed 9312 * management. 9313 * 9314 * @param[in] sh 9315 * Pointer to mlx5_dev_ctx_shared object. 9316 * 9317 * @return 9318 * 0 on success, a negative errno value otherwise. 9319 */ 9320 static int 9321 mlx5_flow_create_counter_stat_mem_mng(struct mlx5_dev_ctx_shared *sh) 9322 { 9323 struct mlx5_counter_stats_mem_mng *mem_mng; 9324 volatile struct flow_counter_stats *raw_data; 9325 int raws_n = MLX5_CNT_MR_ALLOC_BULK + MLX5_MAX_PENDING_QUERIES; 9326 int size = (sizeof(struct flow_counter_stats) * 9327 MLX5_COUNTERS_PER_POOL + 9328 sizeof(struct mlx5_counter_stats_raw)) * raws_n + 9329 sizeof(struct mlx5_counter_stats_mem_mng); 9330 size_t pgsize = rte_mem_page_size(); 9331 uint8_t *mem; 9332 int ret; 9333 int i; 9334 9335 if (pgsize == (size_t)-1) { 9336 DRV_LOG(ERR, "Failed to get mem page size"); 9337 rte_errno = ENOMEM; 9338 return -ENOMEM; 9339 } 9340 mem = mlx5_malloc(MLX5_MEM_ZERO, size, pgsize, SOCKET_ID_ANY); 9341 if (!mem) { 9342 rte_errno = ENOMEM; 9343 return -ENOMEM; 9344 } 9345 mem_mng = (struct mlx5_counter_stats_mem_mng *)(mem + size) - 1; 9346 size = sizeof(*raw_data) * MLX5_COUNTERS_PER_POOL * raws_n; 9347 ret = mlx5_os_wrapped_mkey_create(sh->cdev->ctx, sh->cdev->pd, 9348 sh->cdev->pdn, mem, size, 9349 &mem_mng->wm); 9350 if (ret) { 9351 rte_errno = errno; 9352 mlx5_free(mem); 9353 return -rte_errno; 9354 } 9355 mem_mng->raws = (struct mlx5_counter_stats_raw *)(mem + size); 9356 raw_data = (volatile struct flow_counter_stats *)mem; 9357 for (i = 0; i < raws_n; ++i) { 9358 mem_mng->raws[i].mem_mng = mem_mng; 9359 mem_mng->raws[i].data = raw_data + i * MLX5_COUNTERS_PER_POOL; 9360 } 9361 for (i = 0; i < MLX5_MAX_PENDING_QUERIES; ++i) 9362 LIST_INSERT_HEAD(&sh->sws_cmng.free_stat_raws, 9363 mem_mng->raws + MLX5_CNT_MR_ALLOC_BULK + i, 9364 next); 9365 LIST_INSERT_HEAD(&sh->sws_cmng.mem_mngs, mem_mng, next); 9366 sh->sws_cmng.mem_mng = mem_mng; 9367 return 0; 9368 } 9369 9370 /** 9371 * Set the statistic memory to the new counter pool. 9372 * 9373 * @param[in] sh 9374 * Pointer to mlx5_dev_ctx_shared object. 9375 * @param[in] pool 9376 * Pointer to the pool to set the statistic memory. 9377 * 9378 * @return 9379 * 0 on success, a negative errno value otherwise. 9380 */ 9381 static int 9382 mlx5_flow_set_counter_stat_mem(struct mlx5_dev_ctx_shared *sh, 9383 struct mlx5_flow_counter_pool *pool) 9384 { 9385 struct mlx5_flow_counter_mng *cmng = &sh->sws_cmng; 9386 /* Resize statistic memory once used out. */ 9387 if (!(pool->index % MLX5_CNT_MR_ALLOC_BULK) && 9388 mlx5_flow_create_counter_stat_mem_mng(sh)) { 9389 DRV_LOG(ERR, "Cannot resize counter stat mem."); 9390 return -1; 9391 } 9392 rte_spinlock_lock(&pool->sl); 9393 pool->raw = cmng->mem_mng->raws + pool->index % MLX5_CNT_MR_ALLOC_BULK; 9394 rte_spinlock_unlock(&pool->sl); 9395 pool->raw_hw = NULL; 9396 return 0; 9397 } 9398 9399 #define MLX5_POOL_QUERY_FREQ_US 1000000 9400 9401 /** 9402 * Set the periodic procedure for triggering asynchronous batch queries for all 9403 * the counter pools. 9404 * 9405 * @param[in] sh 9406 * Pointer to mlx5_dev_ctx_shared object. 9407 */ 9408 void 9409 mlx5_set_query_alarm(struct mlx5_dev_ctx_shared *sh) 9410 { 9411 uint32_t pools_n, us; 9412 9413 pools_n = __atomic_load_n(&sh->sws_cmng.n_valid, __ATOMIC_RELAXED); 9414 us = MLX5_POOL_QUERY_FREQ_US / pools_n; 9415 DRV_LOG(DEBUG, "Set alarm for %u pools each %u us", pools_n, us); 9416 if (rte_eal_alarm_set(us, mlx5_flow_query_alarm, sh)) { 9417 sh->sws_cmng.query_thread_on = 0; 9418 DRV_LOG(ERR, "Cannot reinitialize query alarm"); 9419 } else { 9420 sh->sws_cmng.query_thread_on = 1; 9421 } 9422 } 9423 9424 /** 9425 * The periodic procedure for triggering asynchronous batch queries for all the 9426 * counter pools. This function is probably called by the host thread. 9427 * 9428 * @param[in] arg 9429 * The parameter for the alarm process. 9430 */ 9431 void 9432 mlx5_flow_query_alarm(void *arg) 9433 { 9434 struct mlx5_dev_ctx_shared *sh = arg; 9435 struct mlx5_flow_counter_mng *cmng = &sh->sws_cmng; 9436 uint16_t pool_index = cmng->pool_index; 9437 struct mlx5_flow_counter_pool *pool; 9438 uint16_t n_valid; 9439 int ret; 9440 9441 if (cmng->pending_queries >= MLX5_MAX_PENDING_QUERIES) 9442 goto set_alarm; 9443 rte_spinlock_lock(&cmng->pool_update_sl); 9444 pool = cmng->pools[pool_index]; 9445 n_valid = cmng->n_valid; 9446 rte_spinlock_unlock(&cmng->pool_update_sl); 9447 /* Set the statistic memory to the new created pool. */ 9448 if ((!pool->raw && mlx5_flow_set_counter_stat_mem(sh, pool))) 9449 goto set_alarm; 9450 if (pool->raw_hw) 9451 /* There is a pool query in progress. */ 9452 goto set_alarm; 9453 pool->raw_hw = LIST_FIRST(&cmng->free_stat_raws); 9454 if (!pool->raw_hw) 9455 /* No free counter statistics raw memory. */ 9456 goto set_alarm; 9457 /* 9458 * Identify the counters released between query trigger and query 9459 * handle more efficiently. The counter released in this gap period 9460 * should wait for a new round of query as the new arrived packets 9461 * will not be taken into account. 9462 */ 9463 pool->query_gen++; 9464 ret = mlx5_devx_cmd_flow_counter_query(pool->min_dcs, 0, 9465 MLX5_COUNTERS_PER_POOL, 9466 NULL, NULL, 9467 pool->raw_hw->mem_mng->wm.lkey, 9468 (void *)(uintptr_t) 9469 pool->raw_hw->data, 9470 sh->devx_comp, 9471 (uint64_t)(uintptr_t)pool); 9472 if (ret) { 9473 DRV_LOG(ERR, "Failed to trigger asynchronous query for dcs ID" 9474 " %d", pool->min_dcs->id); 9475 pool->raw_hw = NULL; 9476 goto set_alarm; 9477 } 9478 LIST_REMOVE(pool->raw_hw, next); 9479 cmng->pending_queries++; 9480 pool_index++; 9481 if (pool_index >= n_valid) 9482 pool_index = 0; 9483 set_alarm: 9484 cmng->pool_index = pool_index; 9485 mlx5_set_query_alarm(sh); 9486 } 9487 9488 /** 9489 * Check and callback event for new aged flow in the counter pool 9490 * 9491 * @param[in] sh 9492 * Pointer to mlx5_dev_ctx_shared object. 9493 * @param[in] pool 9494 * Pointer to Current counter pool. 9495 */ 9496 static void 9497 mlx5_flow_aging_check(struct mlx5_dev_ctx_shared *sh, 9498 struct mlx5_flow_counter_pool *pool) 9499 { 9500 struct mlx5_priv *priv; 9501 struct mlx5_flow_counter *cnt; 9502 struct mlx5_age_info *age_info; 9503 struct mlx5_age_param *age_param; 9504 struct mlx5_counter_stats_raw *cur = pool->raw_hw; 9505 struct mlx5_counter_stats_raw *prev = pool->raw; 9506 const uint64_t curr_time = MLX5_CURR_TIME_SEC; 9507 const uint32_t time_delta = curr_time - pool->time_of_last_age_check; 9508 uint16_t expected = AGE_CANDIDATE; 9509 uint32_t i; 9510 9511 pool->time_of_last_age_check = curr_time; 9512 for (i = 0; i < MLX5_COUNTERS_PER_POOL; ++i) { 9513 cnt = MLX5_POOL_GET_CNT(pool, i); 9514 age_param = MLX5_CNT_TO_AGE(cnt); 9515 if (__atomic_load_n(&age_param->state, 9516 __ATOMIC_RELAXED) != AGE_CANDIDATE) 9517 continue; 9518 if (cur->data[i].hits != prev->data[i].hits) { 9519 __atomic_store_n(&age_param->sec_since_last_hit, 0, 9520 __ATOMIC_RELAXED); 9521 continue; 9522 } 9523 if (__atomic_fetch_add(&age_param->sec_since_last_hit, 9524 time_delta, 9525 __ATOMIC_RELAXED) + time_delta <= age_param->timeout) 9526 continue; 9527 /** 9528 * Hold the lock first, or if between the 9529 * state AGE_TMOUT and tailq operation the 9530 * release happened, the release procedure 9531 * may delete a non-existent tailq node. 9532 */ 9533 priv = rte_eth_devices[age_param->port_id].data->dev_private; 9534 age_info = GET_PORT_AGE_INFO(priv); 9535 rte_spinlock_lock(&age_info->aged_sl); 9536 if (__atomic_compare_exchange_n(&age_param->state, &expected, 9537 AGE_TMOUT, false, 9538 __ATOMIC_RELAXED, 9539 __ATOMIC_RELAXED)) { 9540 TAILQ_INSERT_TAIL(&age_info->aged_counters, cnt, next); 9541 MLX5_AGE_SET(age_info, MLX5_AGE_EVENT_NEW); 9542 } 9543 rte_spinlock_unlock(&age_info->aged_sl); 9544 } 9545 mlx5_age_event_prepare(sh); 9546 } 9547 9548 /** 9549 * Handler for the HW respond about ready values from an asynchronous batch 9550 * query. This function is probably called by the host thread. 9551 * 9552 * @param[in] sh 9553 * The pointer to the shared device context. 9554 * @param[in] async_id 9555 * The Devx async ID. 9556 * @param[in] status 9557 * The status of the completion. 9558 */ 9559 void 9560 mlx5_flow_async_pool_query_handle(struct mlx5_dev_ctx_shared *sh, 9561 uint64_t async_id, int status) 9562 { 9563 struct mlx5_flow_counter_pool *pool = 9564 (struct mlx5_flow_counter_pool *)(uintptr_t)async_id; 9565 struct mlx5_counter_stats_raw *raw_to_free; 9566 uint8_t query_gen = pool->query_gen ^ 1; 9567 struct mlx5_flow_counter_mng *cmng = &sh->sws_cmng; 9568 enum mlx5_counter_type cnt_type = 9569 pool->is_aged ? MLX5_COUNTER_TYPE_AGE : 9570 MLX5_COUNTER_TYPE_ORIGIN; 9571 9572 if (unlikely(status)) { 9573 raw_to_free = pool->raw_hw; 9574 } else { 9575 raw_to_free = pool->raw; 9576 if (pool->is_aged) 9577 mlx5_flow_aging_check(sh, pool); 9578 rte_spinlock_lock(&pool->sl); 9579 pool->raw = pool->raw_hw; 9580 rte_spinlock_unlock(&pool->sl); 9581 /* Be sure the new raw counters data is updated in memory. */ 9582 rte_io_wmb(); 9583 if (!TAILQ_EMPTY(&pool->counters[query_gen])) { 9584 rte_spinlock_lock(&cmng->csl[cnt_type]); 9585 TAILQ_CONCAT(&cmng->counters[cnt_type], 9586 &pool->counters[query_gen], next); 9587 rte_spinlock_unlock(&cmng->csl[cnt_type]); 9588 } 9589 } 9590 LIST_INSERT_HEAD(&sh->sws_cmng.free_stat_raws, raw_to_free, next); 9591 pool->raw_hw = NULL; 9592 sh->sws_cmng.pending_queries--; 9593 } 9594 9595 static int 9596 flow_group_to_table(uint32_t port_id, uint32_t group, uint32_t *table, 9597 const struct flow_grp_info *grp_info, 9598 struct rte_flow_error *error) 9599 { 9600 if (grp_info->transfer && grp_info->external && 9601 grp_info->fdb_def_rule) { 9602 if (group == UINT32_MAX) 9603 return rte_flow_error_set 9604 (error, EINVAL, 9605 RTE_FLOW_ERROR_TYPE_ATTR_GROUP, 9606 NULL, 9607 "group index not supported"); 9608 *table = group + 1; 9609 } else { 9610 *table = group; 9611 } 9612 DRV_LOG(DEBUG, "port %u group=%#x table=%#x", port_id, group, *table); 9613 return 0; 9614 } 9615 9616 /** 9617 * Translate the rte_flow group index to HW table value. 9618 * 9619 * If tunnel offload is disabled, all group ids converted to flow table 9620 * id using the standard method. 9621 * If tunnel offload is enabled, group id can be converted using the 9622 * standard or tunnel conversion method. Group conversion method 9623 * selection depends on flags in `grp_info` parameter: 9624 * - Internal (grp_info.external == 0) groups conversion uses the 9625 * standard method. 9626 * - Group ids in JUMP action converted with the tunnel conversion. 9627 * - Group id in rule attribute conversion depends on a rule type and 9628 * group id value: 9629 * ** non zero group attributes converted with the tunnel method 9630 * ** zero group attribute in non-tunnel rule is converted using the 9631 * standard method - there's only one root table 9632 * ** zero group attribute in steer tunnel rule is converted with the 9633 * standard method - single root table 9634 * ** zero group attribute in match tunnel rule is a special OvS 9635 * case: that value is used for portability reasons. That group 9636 * id is converted with the tunnel conversion method. 9637 * 9638 * @param[in] dev 9639 * Port device 9640 * @param[in] tunnel 9641 * PMD tunnel offload object 9642 * @param[in] group 9643 * rte_flow group index value. 9644 * @param[out] table 9645 * HW table value. 9646 * @param[in] grp_info 9647 * flags used for conversion 9648 * @param[out] error 9649 * Pointer to error structure. 9650 * 9651 * @return 9652 * 0 on success, a negative errno value otherwise and rte_errno is set. 9653 */ 9654 int 9655 mlx5_flow_group_to_table(struct rte_eth_dev *dev, 9656 const struct mlx5_flow_tunnel *tunnel, 9657 uint32_t group, uint32_t *table, 9658 const struct flow_grp_info *grp_info, 9659 struct rte_flow_error *error) 9660 { 9661 int ret; 9662 bool standard_translation; 9663 9664 if (!grp_info->skip_scale && grp_info->external && 9665 group < MLX5_MAX_TABLES_EXTERNAL) 9666 group *= MLX5_FLOW_TABLE_FACTOR; 9667 if (is_tunnel_offload_active(dev)) { 9668 standard_translation = !grp_info->external || 9669 grp_info->std_tbl_fix; 9670 } else { 9671 standard_translation = true; 9672 } 9673 DRV_LOG(DEBUG, 9674 "port %u group=%u transfer=%d external=%d fdb_def_rule=%d translate=%s", 9675 dev->data->port_id, group, grp_info->transfer, 9676 grp_info->external, grp_info->fdb_def_rule, 9677 standard_translation ? "STANDARD" : "TUNNEL"); 9678 if (standard_translation) 9679 ret = flow_group_to_table(dev->data->port_id, group, table, 9680 grp_info, error); 9681 else 9682 ret = tunnel_flow_group_to_flow_table(dev, tunnel, group, 9683 table, error); 9684 9685 return ret; 9686 } 9687 9688 /** 9689 * Discover availability of metadata reg_c's. 9690 * 9691 * Iteratively use test flows to check availability. 9692 * 9693 * @param[in] dev 9694 * Pointer to the Ethernet device structure. 9695 * 9696 * @return 9697 * 0 on success, a negative errno value otherwise and rte_errno is set. 9698 */ 9699 int 9700 mlx5_flow_discover_mreg_c(struct rte_eth_dev *dev) 9701 { 9702 struct mlx5_priv *priv = dev->data->dev_private; 9703 enum modify_reg idx; 9704 int n = 0; 9705 9706 /* reg_c[0] and reg_c[1] are reserved. */ 9707 priv->sh->flow_mreg_c[n++] = REG_C_0; 9708 priv->sh->flow_mreg_c[n++] = REG_C_1; 9709 /* Discover availability of other reg_c's. */ 9710 for (idx = REG_C_2; idx <= REG_C_7; ++idx) { 9711 struct rte_flow_attr attr = { 9712 .group = MLX5_FLOW_MREG_CP_TABLE_GROUP, 9713 .priority = MLX5_FLOW_LOWEST_PRIO_INDICATOR, 9714 .ingress = 1, 9715 }; 9716 struct rte_flow_item items[] = { 9717 [0] = { 9718 .type = RTE_FLOW_ITEM_TYPE_END, 9719 }, 9720 }; 9721 struct rte_flow_action actions[] = { 9722 [0] = { 9723 .type = (enum rte_flow_action_type) 9724 MLX5_RTE_FLOW_ACTION_TYPE_COPY_MREG, 9725 .conf = &(struct mlx5_flow_action_copy_mreg){ 9726 .src = REG_C_1, 9727 .dst = idx, 9728 }, 9729 }, 9730 [1] = { 9731 .type = RTE_FLOW_ACTION_TYPE_JUMP, 9732 .conf = &(struct rte_flow_action_jump){ 9733 .group = MLX5_FLOW_MREG_ACT_TABLE_GROUP, 9734 }, 9735 }, 9736 [2] = { 9737 .type = RTE_FLOW_ACTION_TYPE_END, 9738 }, 9739 }; 9740 uint32_t flow_idx; 9741 struct rte_flow *flow; 9742 struct rte_flow_error error; 9743 9744 if (!priv->sh->config.dv_flow_en) 9745 break; 9746 /* Create internal flow, validation skips copy action. */ 9747 flow_idx = flow_list_create(dev, MLX5_FLOW_TYPE_GEN, &attr, 9748 items, actions, false, &error); 9749 flow = mlx5_ipool_get(priv->flows[MLX5_FLOW_TYPE_GEN], 9750 flow_idx); 9751 if (!flow) 9752 continue; 9753 priv->sh->flow_mreg_c[n++] = idx; 9754 flow_list_destroy(dev, MLX5_FLOW_TYPE_GEN, flow_idx); 9755 } 9756 for (; n < MLX5_MREG_C_NUM; ++n) 9757 priv->sh->flow_mreg_c[n] = REG_NON; 9758 priv->sh->metadata_regc_check_flag = 1; 9759 return 0; 9760 } 9761 9762 int 9763 save_dump_file(const uint8_t *data, uint32_t size, 9764 uint32_t type, uint64_t id, void *arg, FILE *file) 9765 { 9766 char line[BUF_SIZE]; 9767 uint32_t out = 0; 9768 uint32_t k; 9769 uint32_t actions_num; 9770 struct rte_flow_query_count *count; 9771 9772 memset(line, 0, BUF_SIZE); 9773 switch (type) { 9774 case DR_DUMP_REC_TYPE_PMD_MODIFY_HDR: 9775 actions_num = *(uint32_t *)(arg); 9776 out += snprintf(line + out, BUF_SIZE - out, "%d,0x%" PRIx64 ",%d,", 9777 type, id, actions_num); 9778 break; 9779 case DR_DUMP_REC_TYPE_PMD_PKT_REFORMAT: 9780 out += snprintf(line + out, BUF_SIZE - out, "%d,0x%" PRIx64 ",", 9781 type, id); 9782 break; 9783 case DR_DUMP_REC_TYPE_PMD_COUNTER: 9784 count = (struct rte_flow_query_count *)arg; 9785 fprintf(file, 9786 "%d,0x%" PRIx64 ",%" PRIu64 ",%" PRIu64 "\n", 9787 type, id, count->hits, count->bytes); 9788 return 0; 9789 default: 9790 return -1; 9791 } 9792 9793 for (k = 0; k < size; k++) { 9794 /* Make sure we do not overrun the line buffer length. */ 9795 if (out >= BUF_SIZE - 4) { 9796 line[out] = '\0'; 9797 break; 9798 } 9799 out += snprintf(line + out, BUF_SIZE - out, "%02x", 9800 (data[k]) & 0xff); 9801 } 9802 fprintf(file, "%s\n", line); 9803 return 0; 9804 } 9805 9806 int 9807 mlx5_flow_query_counter(struct rte_eth_dev *dev, struct rte_flow *flow, 9808 struct rte_flow_query_count *count, struct rte_flow_error *error) 9809 { 9810 struct rte_flow_action action[2]; 9811 enum mlx5_flow_drv_type ftype; 9812 const struct mlx5_flow_driver_ops *fops; 9813 9814 if (!flow) { 9815 return rte_flow_error_set(error, ENOENT, 9816 RTE_FLOW_ERROR_TYPE_UNSPECIFIED, 9817 NULL, 9818 "invalid flow handle"); 9819 } 9820 action[0].type = RTE_FLOW_ACTION_TYPE_COUNT; 9821 action[1].type = RTE_FLOW_ACTION_TYPE_END; 9822 if (flow->counter) { 9823 memset(count, 0, sizeof(struct rte_flow_query_count)); 9824 ftype = (enum mlx5_flow_drv_type)(flow->drv_type); 9825 MLX5_ASSERT(ftype > MLX5_FLOW_TYPE_MIN && 9826 ftype < MLX5_FLOW_TYPE_MAX); 9827 fops = flow_get_drv_ops(ftype); 9828 return fops->query(dev, flow, action, count, error); 9829 } 9830 return -1; 9831 } 9832 9833 #ifdef HAVE_IBV_FLOW_DV_SUPPORT 9834 /** 9835 * Dump flow ipool data to file 9836 * 9837 * @param[in] dev 9838 * The pointer to Ethernet device. 9839 * @param[in] file 9840 * A pointer to a file for output. 9841 * @param[out] error 9842 * Perform verbose error reporting if not NULL. PMDs initialize this 9843 * structure in case of error only. 9844 * @return 9845 * 0 on success, a negative value otherwise. 9846 */ 9847 int 9848 mlx5_flow_dev_dump_ipool(struct rte_eth_dev *dev, 9849 struct rte_flow *flow, FILE *file, 9850 struct rte_flow_error *error) 9851 { 9852 struct mlx5_priv *priv = dev->data->dev_private; 9853 struct mlx5_flow_dv_modify_hdr_resource *modify_hdr; 9854 struct mlx5_flow_dv_encap_decap_resource *encap_decap; 9855 uint32_t handle_idx; 9856 struct mlx5_flow_handle *dh; 9857 struct rte_flow_query_count count; 9858 uint32_t actions_num; 9859 const uint8_t *data; 9860 size_t size; 9861 uint64_t id; 9862 uint32_t type; 9863 void *action = NULL; 9864 9865 if (!flow) { 9866 return rte_flow_error_set(error, ENOENT, 9867 RTE_FLOW_ERROR_TYPE_UNSPECIFIED, 9868 NULL, 9869 "invalid flow handle"); 9870 } 9871 handle_idx = flow->dev_handles; 9872 /* query counter */ 9873 if (flow->counter && 9874 (!mlx5_counter_query(dev, flow->counter, false, 9875 &count.hits, &count.bytes, &action)) && action) { 9876 id = (uint64_t)(uintptr_t)action; 9877 type = DR_DUMP_REC_TYPE_PMD_COUNTER; 9878 save_dump_file(NULL, 0, type, 9879 id, (void *)&count, file); 9880 } 9881 9882 while (handle_idx) { 9883 dh = mlx5_ipool_get(priv->sh->ipool 9884 [MLX5_IPOOL_MLX5_FLOW], handle_idx); 9885 if (!dh) 9886 continue; 9887 handle_idx = dh->next.next; 9888 9889 /* Get modify_hdr and encap_decap buf from ipools. */ 9890 encap_decap = NULL; 9891 modify_hdr = dh->dvh.modify_hdr; 9892 9893 if (dh->dvh.rix_encap_decap) { 9894 encap_decap = mlx5_ipool_get(priv->sh->ipool 9895 [MLX5_IPOOL_DECAP_ENCAP], 9896 dh->dvh.rix_encap_decap); 9897 } 9898 if (modify_hdr) { 9899 data = (const uint8_t *)modify_hdr->actions; 9900 size = (size_t)(modify_hdr->actions_num) * 8; 9901 id = (uint64_t)(uintptr_t)modify_hdr->action; 9902 actions_num = modify_hdr->actions_num; 9903 type = DR_DUMP_REC_TYPE_PMD_MODIFY_HDR; 9904 save_dump_file(data, size, type, id, 9905 (void *)(&actions_num), file); 9906 } 9907 if (encap_decap) { 9908 data = encap_decap->buf; 9909 size = encap_decap->size; 9910 id = (uint64_t)(uintptr_t)encap_decap->action; 9911 type = DR_DUMP_REC_TYPE_PMD_PKT_REFORMAT; 9912 save_dump_file(data, size, type, 9913 id, NULL, file); 9914 } 9915 } 9916 return 0; 9917 } 9918 9919 /** 9920 * Dump all flow's encap_decap/modify_hdr/counter data to file 9921 * 9922 * @param[in] dev 9923 * The pointer to Ethernet device. 9924 * @param[in] file 9925 * A pointer to a file for output. 9926 * @param[out] error 9927 * Perform verbose error reporting if not NULL. PMDs initialize this 9928 * structure in case of error only. 9929 * @return 9930 * 0 on success, a negative value otherwise. 9931 */ 9932 static int 9933 mlx5_flow_dev_dump_sh_all(struct rte_eth_dev *dev, 9934 FILE *file, struct rte_flow_error *error __rte_unused) 9935 { 9936 struct mlx5_priv *priv = dev->data->dev_private; 9937 struct mlx5_dev_ctx_shared *sh = priv->sh; 9938 struct mlx5_hlist *h; 9939 struct mlx5_flow_dv_modify_hdr_resource *modify_hdr; 9940 struct mlx5_flow_dv_encap_decap_resource *encap_decap; 9941 struct rte_flow_query_count count; 9942 uint32_t actions_num; 9943 const uint8_t *data; 9944 size_t size; 9945 uint64_t id; 9946 uint32_t type; 9947 uint32_t i; 9948 uint32_t j; 9949 struct mlx5_list_inconst *l_inconst; 9950 struct mlx5_list_entry *e; 9951 int lcore_index; 9952 struct mlx5_flow_counter_mng *cmng = &priv->sh->sws_cmng; 9953 uint32_t max; 9954 void *action; 9955 9956 /* encap_decap hlist is lcore_share, get global core cache. */ 9957 i = MLX5_LIST_GLOBAL; 9958 h = sh->encaps_decaps; 9959 if (h) { 9960 for (j = 0; j <= h->mask; j++) { 9961 l_inconst = &h->buckets[j].l; 9962 if (!l_inconst || !l_inconst->cache[i]) 9963 continue; 9964 9965 e = LIST_FIRST(&l_inconst->cache[i]->h); 9966 while (e) { 9967 encap_decap = 9968 (struct mlx5_flow_dv_encap_decap_resource *)e; 9969 data = encap_decap->buf; 9970 size = encap_decap->size; 9971 id = (uint64_t)(uintptr_t)encap_decap->action; 9972 type = DR_DUMP_REC_TYPE_PMD_PKT_REFORMAT; 9973 save_dump_file(data, size, type, 9974 id, NULL, file); 9975 e = LIST_NEXT(e, next); 9976 } 9977 } 9978 } 9979 9980 /* get modify_hdr */ 9981 h = sh->modify_cmds; 9982 if (h) { 9983 lcore_index = rte_lcore_index(rte_lcore_id()); 9984 if (unlikely(lcore_index == -1)) { 9985 lcore_index = MLX5_LIST_NLCORE; 9986 rte_spinlock_lock(&h->l_const.lcore_lock); 9987 } 9988 i = lcore_index; 9989 9990 if (lcore_index == MLX5_LIST_NLCORE) { 9991 for (i = 0; i <= (uint32_t)lcore_index; i++) { 9992 for (j = 0; j <= h->mask; j++) { 9993 l_inconst = &h->buckets[j].l; 9994 if (!l_inconst || !l_inconst->cache[i]) 9995 continue; 9996 9997 e = LIST_FIRST(&l_inconst->cache[i]->h); 9998 while (e) { 9999 modify_hdr = 10000 (struct mlx5_flow_dv_modify_hdr_resource *)e; 10001 data = (const uint8_t *)modify_hdr->actions; 10002 size = (size_t)(modify_hdr->actions_num) * 8; 10003 actions_num = modify_hdr->actions_num; 10004 id = (uint64_t)(uintptr_t)modify_hdr->action; 10005 type = DR_DUMP_REC_TYPE_PMD_MODIFY_HDR; 10006 save_dump_file(data, size, type, id, 10007 (void *)(&actions_num), file); 10008 e = LIST_NEXT(e, next); 10009 } 10010 } 10011 } 10012 } else { 10013 for (j = 0; j <= h->mask; j++) { 10014 l_inconst = &h->buckets[j].l; 10015 if (!l_inconst || !l_inconst->cache[i]) 10016 continue; 10017 10018 e = LIST_FIRST(&l_inconst->cache[i]->h); 10019 while (e) { 10020 modify_hdr = 10021 (struct mlx5_flow_dv_modify_hdr_resource *)e; 10022 data = (const uint8_t *)modify_hdr->actions; 10023 size = (size_t)(modify_hdr->actions_num) * 8; 10024 actions_num = modify_hdr->actions_num; 10025 id = (uint64_t)(uintptr_t)modify_hdr->action; 10026 type = DR_DUMP_REC_TYPE_PMD_MODIFY_HDR; 10027 save_dump_file(data, size, type, id, 10028 (void *)(&actions_num), file); 10029 e = LIST_NEXT(e, next); 10030 } 10031 } 10032 } 10033 10034 if (unlikely(lcore_index == MLX5_LIST_NLCORE)) 10035 rte_spinlock_unlock(&h->l_const.lcore_lock); 10036 } 10037 10038 /* get counter */ 10039 MLX5_ASSERT(cmng->n_valid <= MLX5_COUNTER_POOLS_MAX_NUM); 10040 max = MLX5_COUNTERS_PER_POOL * cmng->n_valid; 10041 for (j = 1; j <= max; j++) { 10042 action = NULL; 10043 if ((!mlx5_counter_query(dev, j, false, &count.hits, 10044 &count.bytes, &action)) && action) { 10045 id = (uint64_t)(uintptr_t)action; 10046 type = DR_DUMP_REC_TYPE_PMD_COUNTER; 10047 save_dump_file(NULL, 0, type, 10048 id, (void *)&count, file); 10049 } 10050 } 10051 return 0; 10052 } 10053 #endif 10054 10055 /** 10056 * Dump flow raw hw data to file 10057 * 10058 * @param[in] dev 10059 * The pointer to Ethernet device. 10060 * @param[in] file 10061 * A pointer to a file for output. 10062 * @param[out] error 10063 * Perform verbose error reporting if not NULL. PMDs initialize this 10064 * structure in case of error only. 10065 * @return 10066 * 0 on success, a negative value otherwise. 10067 */ 10068 int 10069 mlx5_flow_dev_dump(struct rte_eth_dev *dev, struct rte_flow *flow_idx, 10070 FILE *file, 10071 struct rte_flow_error *error __rte_unused) 10072 { 10073 struct mlx5_priv *priv = dev->data->dev_private; 10074 struct mlx5_dev_ctx_shared *sh = priv->sh; 10075 uint32_t handle_idx; 10076 int ret; 10077 struct mlx5_flow_handle *dh; 10078 struct rte_flow *flow; 10079 10080 if (!sh->config.dv_flow_en) { 10081 if (fputs("device dv flow disabled\n", file) <= 0) 10082 return -errno; 10083 return -ENOTSUP; 10084 } 10085 10086 /* dump all */ 10087 if (!flow_idx) { 10088 #ifdef HAVE_IBV_FLOW_DV_SUPPORT 10089 if (mlx5_flow_dev_dump_sh_all(dev, file, error)) 10090 return -EINVAL; 10091 10092 if (sh->config.dv_flow_en == 2) 10093 return mlx5dr_debug_dump(priv->dr_ctx, file); 10094 #endif 10095 return mlx5_devx_cmd_flow_dump(sh->fdb_domain, 10096 sh->rx_domain, 10097 sh->tx_domain, file); 10098 } 10099 /* dump one */ 10100 flow = mlx5_ipool_get(priv->flows[MLX5_FLOW_TYPE_GEN], 10101 (uintptr_t)(void *)flow_idx); 10102 if (!flow) 10103 return -EINVAL; 10104 10105 #ifdef HAVE_IBV_FLOW_DV_SUPPORT 10106 mlx5_flow_dev_dump_ipool(dev, flow, file, error); 10107 #endif 10108 handle_idx = flow->dev_handles; 10109 while (handle_idx) { 10110 dh = mlx5_ipool_get(priv->sh->ipool[MLX5_IPOOL_MLX5_FLOW], 10111 handle_idx); 10112 if (!dh) 10113 return -ENOENT; 10114 if (dh->drv_flow) { 10115 if (sh->config.dv_flow_en == 2) 10116 return -ENOTSUP; 10117 10118 ret = mlx5_devx_cmd_flow_single_dump(dh->drv_flow, 10119 file); 10120 if (ret) 10121 return -ENOENT; 10122 } 10123 handle_idx = dh->next.next; 10124 } 10125 return 0; 10126 } 10127 10128 /** 10129 * Get aged-out flows. 10130 * 10131 * @param[in] dev 10132 * Pointer to the Ethernet device structure. 10133 * @param[in] context 10134 * The address of an array of pointers to the aged-out flows contexts. 10135 * @param[in] nb_countexts 10136 * The length of context array pointers. 10137 * @param[out] error 10138 * Perform verbose error reporting if not NULL. Initialized in case of 10139 * error only. 10140 * 10141 * @return 10142 * how many contexts get in success, otherwise negative errno value. 10143 * if nb_contexts is 0, return the amount of all aged contexts. 10144 * if nb_contexts is not 0 , return the amount of aged flows reported 10145 * in the context array. 10146 */ 10147 int 10148 mlx5_flow_get_aged_flows(struct rte_eth_dev *dev, void **contexts, 10149 uint32_t nb_contexts, struct rte_flow_error *error) 10150 { 10151 struct rte_flow_attr attr = { .transfer = 0 }; 10152 10153 return flow_get_drv_ops(flow_get_drv_type(dev, &attr))->get_aged_flows 10154 (dev, contexts, nb_contexts, error); 10155 } 10156 10157 /** 10158 * Get aged-out flows per HWS queue. 10159 * 10160 * @param[in] dev 10161 * Pointer to the Ethernet device structure. 10162 * @param[in] queue_id 10163 * Flow queue to query. 10164 * @param[in] context 10165 * The address of an array of pointers to the aged-out flows contexts. 10166 * @param[in] nb_countexts 10167 * The length of context array pointers. 10168 * @param[out] error 10169 * Perform verbose error reporting if not NULL. Initialized in case of 10170 * error only. 10171 * 10172 * @return 10173 * how many contexts get in success, otherwise negative errno value. 10174 * if nb_contexts is 0, return the amount of all aged contexts. 10175 * if nb_contexts is not 0 , return the amount of aged flows reported 10176 * in the context array. 10177 */ 10178 int 10179 mlx5_flow_get_q_aged_flows(struct rte_eth_dev *dev, uint32_t queue_id, 10180 void **contexts, uint32_t nb_contexts, 10181 struct rte_flow_error *error) 10182 { 10183 const struct mlx5_flow_driver_ops *fops; 10184 struct rte_flow_attr attr = { 0 }; 10185 10186 if (flow_get_drv_type(dev, &attr) == MLX5_FLOW_TYPE_HW) { 10187 fops = flow_get_drv_ops(MLX5_FLOW_TYPE_HW); 10188 return fops->get_q_aged_flows(dev, queue_id, contexts, 10189 nb_contexts, error); 10190 } 10191 DRV_LOG(ERR, "port %u queue %u get aged flows is not supported.", 10192 dev->data->port_id, queue_id); 10193 return rte_flow_error_set(error, ENOTSUP, 10194 RTE_FLOW_ERROR_TYPE_UNSPECIFIED, NULL, 10195 "get Q aged flows with incorrect steering mode"); 10196 } 10197 10198 /* Wrapper for driver action_validate op callback */ 10199 static int 10200 flow_drv_action_validate(struct rte_eth_dev *dev, 10201 const struct rte_flow_indir_action_conf *conf, 10202 const struct rte_flow_action *action, 10203 const struct mlx5_flow_driver_ops *fops, 10204 struct rte_flow_error *error) 10205 { 10206 static const char err_msg[] = "indirect action validation unsupported"; 10207 10208 if (!fops->action_validate) { 10209 DRV_LOG(ERR, "port %u %s.", dev->data->port_id, err_msg); 10210 rte_flow_error_set(error, ENOTSUP, RTE_FLOW_ERROR_TYPE_ACTION, 10211 NULL, err_msg); 10212 return -rte_errno; 10213 } 10214 return fops->action_validate(dev, conf, action, error); 10215 } 10216 10217 /** 10218 * Destroys the shared action by handle. 10219 * 10220 * @param dev 10221 * Pointer to Ethernet device structure. 10222 * @param[in] handle 10223 * Handle for the indirect action object to be destroyed. 10224 * @param[out] error 10225 * Perform verbose error reporting if not NULL. PMDs initialize this 10226 * structure in case of error only. 10227 * 10228 * @return 10229 * 0 on success, a negative errno value otherwise and rte_errno is set. 10230 * 10231 * @note: wrapper for driver action_create op callback. 10232 */ 10233 static int 10234 mlx5_action_handle_destroy(struct rte_eth_dev *dev, 10235 struct rte_flow_action_handle *handle, 10236 struct rte_flow_error *error) 10237 { 10238 static const char err_msg[] = "indirect action destruction unsupported"; 10239 struct rte_flow_attr attr = { .transfer = 0 }; 10240 const struct mlx5_flow_driver_ops *fops = 10241 flow_get_drv_ops(flow_get_drv_type(dev, &attr)); 10242 10243 if (!fops->action_destroy) { 10244 DRV_LOG(ERR, "port %u %s.", dev->data->port_id, err_msg); 10245 rte_flow_error_set(error, ENOTSUP, RTE_FLOW_ERROR_TYPE_ACTION, 10246 NULL, err_msg); 10247 return -rte_errno; 10248 } 10249 return fops->action_destroy(dev, handle, error); 10250 } 10251 10252 /* Wrapper for driver action_destroy op callback */ 10253 static int 10254 flow_drv_action_update(struct rte_eth_dev *dev, 10255 struct rte_flow_action_handle *handle, 10256 const void *update, 10257 const struct mlx5_flow_driver_ops *fops, 10258 struct rte_flow_error *error) 10259 { 10260 static const char err_msg[] = "indirect action update unsupported"; 10261 10262 if (!fops->action_update) { 10263 DRV_LOG(ERR, "port %u %s.", dev->data->port_id, err_msg); 10264 rte_flow_error_set(error, ENOTSUP, RTE_FLOW_ERROR_TYPE_ACTION, 10265 NULL, err_msg); 10266 return -rte_errno; 10267 } 10268 return fops->action_update(dev, handle, update, error); 10269 } 10270 10271 /* Wrapper for driver action_destroy op callback */ 10272 static int 10273 flow_drv_action_query(struct rte_eth_dev *dev, 10274 const struct rte_flow_action_handle *handle, 10275 void *data, 10276 const struct mlx5_flow_driver_ops *fops, 10277 struct rte_flow_error *error) 10278 { 10279 static const char err_msg[] = "indirect action query unsupported"; 10280 10281 if (!fops->action_query) { 10282 DRV_LOG(ERR, "port %u %s.", dev->data->port_id, err_msg); 10283 rte_flow_error_set(error, ENOTSUP, RTE_FLOW_ERROR_TYPE_ACTION, 10284 NULL, err_msg); 10285 return -rte_errno; 10286 } 10287 return fops->action_query(dev, handle, data, error); 10288 } 10289 10290 /** 10291 * Create indirect action for reuse in multiple flow rules. 10292 * 10293 * @param dev 10294 * Pointer to Ethernet device structure. 10295 * @param conf 10296 * Pointer to indirect action object configuration. 10297 * @param[in] action 10298 * Action configuration for indirect action object creation. 10299 * @param[out] error 10300 * Perform verbose error reporting if not NULL. PMDs initialize this 10301 * structure in case of error only. 10302 * @return 10303 * A valid handle in case of success, NULL otherwise and rte_errno is set. 10304 */ 10305 static struct rte_flow_action_handle * 10306 mlx5_action_handle_create(struct rte_eth_dev *dev, 10307 const struct rte_flow_indir_action_conf *conf, 10308 const struct rte_flow_action *action, 10309 struct rte_flow_error *error) 10310 { 10311 static const char err_msg[] = "indirect action creation unsupported"; 10312 struct rte_flow_attr attr = { .transfer = 0 }; 10313 const struct mlx5_flow_driver_ops *fops = 10314 flow_get_drv_ops(flow_get_drv_type(dev, &attr)); 10315 10316 if (flow_drv_action_validate(dev, conf, action, fops, error)) 10317 return NULL; 10318 if (!fops->action_create) { 10319 DRV_LOG(ERR, "port %u %s.", dev->data->port_id, err_msg); 10320 rte_flow_error_set(error, ENOTSUP, RTE_FLOW_ERROR_TYPE_ACTION, 10321 NULL, err_msg); 10322 return NULL; 10323 } 10324 return fops->action_create(dev, conf, action, error); 10325 } 10326 10327 /** 10328 * Updates inplace the indirect action configuration pointed by *handle* 10329 * with the configuration provided as *update* argument. 10330 * The update of the indirect action configuration effects all flow rules 10331 * reusing the action via handle. 10332 * 10333 * @param dev 10334 * Pointer to Ethernet device structure. 10335 * @param[in] handle 10336 * Handle for the indirect action to be updated. 10337 * @param[in] update 10338 * Action specification used to modify the action pointed by handle. 10339 * *update* could be of same type with the action pointed by the *handle* 10340 * handle argument, or some other structures like a wrapper, depending on 10341 * the indirect action type. 10342 * @param[out] error 10343 * Perform verbose error reporting if not NULL. PMDs initialize this 10344 * structure in case of error only. 10345 * 10346 * @return 10347 * 0 on success, a negative errno value otherwise and rte_errno is set. 10348 */ 10349 static int 10350 mlx5_action_handle_update(struct rte_eth_dev *dev, 10351 struct rte_flow_action_handle *handle, 10352 const void *update, 10353 struct rte_flow_error *error) 10354 { 10355 struct rte_flow_attr attr = { .transfer = 0 }; 10356 const struct mlx5_flow_driver_ops *fops = 10357 flow_get_drv_ops(flow_get_drv_type(dev, &attr)); 10358 int ret; 10359 uint32_t act_idx = (uint32_t)(uintptr_t)handle; 10360 uint32_t type = act_idx >> MLX5_INDIRECT_ACTION_TYPE_OFFSET; 10361 10362 switch (type) { 10363 case MLX5_INDIRECT_ACTION_TYPE_CT: 10364 case MLX5_INDIRECT_ACTION_TYPE_METER_MARK: 10365 ret = 0; 10366 break; 10367 default: 10368 ret = flow_drv_action_validate(dev, NULL, 10369 (const struct rte_flow_action *)update, 10370 fops, error); 10371 } 10372 if (ret) 10373 return ret; 10374 return flow_drv_action_update(dev, handle, update, fops, 10375 error); 10376 } 10377 10378 /** 10379 * Query the indirect action by handle. 10380 * 10381 * This function allows retrieving action-specific data such as counters. 10382 * Data is gathered by special action which may be present/referenced in 10383 * more than one flow rule definition. 10384 * 10385 * see @RTE_FLOW_ACTION_TYPE_COUNT 10386 * 10387 * @param dev 10388 * Pointer to Ethernet device structure. 10389 * @param[in] handle 10390 * Handle for the indirect action to query. 10391 * @param[in, out] data 10392 * Pointer to storage for the associated query data type. 10393 * @param[out] error 10394 * Perform verbose error reporting if not NULL. PMDs initialize this 10395 * structure in case of error only. 10396 * 10397 * @return 10398 * 0 on success, a negative errno value otherwise and rte_errno is set. 10399 */ 10400 static int 10401 mlx5_action_handle_query(struct rte_eth_dev *dev, 10402 const struct rte_flow_action_handle *handle, 10403 void *data, 10404 struct rte_flow_error *error) 10405 { 10406 struct rte_flow_attr attr = { .transfer = 0 }; 10407 const struct mlx5_flow_driver_ops *fops = 10408 flow_get_drv_ops(flow_get_drv_type(dev, &attr)); 10409 10410 return flow_drv_action_query(dev, handle, data, fops, error); 10411 } 10412 10413 static int 10414 mlx5_action_handle_query_update(struct rte_eth_dev *dev, 10415 struct rte_flow_action_handle *handle, 10416 const void *update, void *query, 10417 enum rte_flow_query_update_mode qu_mode, 10418 struct rte_flow_error *error) 10419 { 10420 struct rte_flow_attr attr = { .transfer = 0 }; 10421 enum mlx5_flow_drv_type drv_type = flow_get_drv_type(dev, &attr); 10422 const struct mlx5_flow_driver_ops *fops; 10423 10424 if (drv_type == MLX5_FLOW_TYPE_MIN || drv_type == MLX5_FLOW_TYPE_MAX) 10425 return rte_flow_error_set(error, ENOTSUP, 10426 RTE_FLOW_ERROR_TYPE_ACTION, 10427 NULL, "invalid driver type"); 10428 fops = flow_get_drv_ops(drv_type); 10429 if (!fops || !fops->action_query_update) 10430 return rte_flow_error_set(error, ENOTSUP, 10431 RTE_FLOW_ERROR_TYPE_ACTION, 10432 NULL, "no query_update handler"); 10433 return fops->action_query_update(dev, handle, update, 10434 query, qu_mode, error); 10435 } 10436 10437 10438 #define MLX5_DRV_FOPS_OR_ERR(dev, fops, drv_cb, ret) \ 10439 { \ 10440 struct rte_flow_attr attr = { .transfer = 0 }; \ 10441 enum mlx5_flow_drv_type drv_type = flow_get_drv_type((dev), &attr); \ 10442 if (drv_type == MLX5_FLOW_TYPE_MIN || \ 10443 drv_type == MLX5_FLOW_TYPE_MAX) { \ 10444 rte_flow_error_set(error, ENOTSUP, \ 10445 RTE_FLOW_ERROR_TYPE_ACTION, \ 10446 NULL, "invalid driver type"); \ 10447 return ret; \ 10448 } \ 10449 (fops) = flow_get_drv_ops(drv_type); \ 10450 if (!(fops) || !(fops)->drv_cb) { \ 10451 rte_flow_error_set(error, ENOTSUP, RTE_FLOW_ERROR_TYPE_ACTION, \ 10452 NULL, "no action_list handler"); \ 10453 return ret; \ 10454 } \ 10455 } 10456 10457 static struct rte_flow_action_list_handle * 10458 mlx5_action_list_handle_create(struct rte_eth_dev *dev, 10459 const struct rte_flow_indir_action_conf *conf, 10460 const struct rte_flow_action *actions, 10461 struct rte_flow_error *error) 10462 { 10463 const struct mlx5_flow_driver_ops *fops; 10464 10465 MLX5_DRV_FOPS_OR_ERR(dev, fops, action_list_handle_create, NULL); 10466 return fops->action_list_handle_create(dev, conf, actions, error); 10467 } 10468 10469 static int 10470 mlx5_action_list_handle_destroy(struct rte_eth_dev *dev, 10471 struct rte_flow_action_list_handle *handle, 10472 struct rte_flow_error *error) 10473 { 10474 const struct mlx5_flow_driver_ops *fops; 10475 10476 MLX5_DRV_FOPS_OR_ERR(dev, fops, action_list_handle_destroy, ENOTSUP); 10477 return fops->action_list_handle_destroy(dev, handle, error); 10478 } 10479 10480 static int 10481 mlx5_flow_action_list_handle_query_update(struct rte_eth_dev *dev, 10482 const 10483 struct rte_flow_action_list_handle *handle, 10484 const void **update, void **query, 10485 enum rte_flow_query_update_mode mode, 10486 struct rte_flow_error *error) 10487 { 10488 const struct mlx5_flow_driver_ops *fops; 10489 10490 MLX5_DRV_FOPS_OR_ERR(dev, fops, 10491 action_list_handle_query_update, ENOTSUP); 10492 return fops->action_list_handle_query_update(dev, handle, update, query, 10493 mode, error); 10494 } 10495 static int 10496 mlx5_flow_calc_table_hash(struct rte_eth_dev *dev, 10497 const struct rte_flow_template_table *table, 10498 const struct rte_flow_item pattern[], 10499 uint8_t pattern_template_index, 10500 uint32_t *hash, struct rte_flow_error *error) 10501 { 10502 struct rte_flow_attr attr = { .transfer = 0 }; 10503 enum mlx5_flow_drv_type drv_type = flow_get_drv_type(dev, &attr); 10504 const struct mlx5_flow_driver_ops *fops; 10505 10506 if (drv_type == MLX5_FLOW_TYPE_MIN || drv_type == MLX5_FLOW_TYPE_MAX) 10507 return rte_flow_error_set(error, ENOTSUP, 10508 RTE_FLOW_ERROR_TYPE_ACTION, 10509 NULL, "invalid driver type"); 10510 fops = flow_get_drv_ops(drv_type); 10511 if (!fops || !fops->action_query_update) 10512 return rte_flow_error_set(error, ENOTSUP, 10513 RTE_FLOW_ERROR_TYPE_ACTION, 10514 NULL, "no query_update handler"); 10515 return fops->flow_calc_table_hash(dev, table, pattern, pattern_template_index, 10516 hash, error); 10517 } 10518 10519 static int 10520 mlx5_flow_calc_encap_hash(struct rte_eth_dev *dev, 10521 const struct rte_flow_item pattern[], 10522 enum rte_flow_encap_hash_field dest_field, 10523 uint8_t *hash, 10524 struct rte_flow_error *error) 10525 { 10526 enum mlx5_flow_drv_type drv_type = flow_get_drv_type(dev, NULL); 10527 const struct mlx5_flow_driver_ops *fops; 10528 10529 if (drv_type == MLX5_FLOW_TYPE_MIN || drv_type == MLX5_FLOW_TYPE_MAX) 10530 return rte_flow_error_set(error, ENOTSUP, 10531 RTE_FLOW_ERROR_TYPE_ACTION, 10532 NULL, "invalid driver type"); 10533 fops = flow_get_drv_ops(drv_type); 10534 if (!fops || !fops->flow_calc_encap_hash) 10535 return rte_flow_error_set(error, ENOTSUP, 10536 RTE_FLOW_ERROR_TYPE_ACTION, 10537 NULL, "no calc encap hash handler"); 10538 return fops->flow_calc_encap_hash(dev, pattern, dest_field, hash, error); 10539 } 10540 10541 /** 10542 * Destroy all indirect actions (shared RSS). 10543 * 10544 * @param dev 10545 * Pointer to Ethernet device. 10546 * 10547 * @return 10548 * 0 on success, a negative errno value otherwise and rte_errno is set. 10549 */ 10550 int 10551 mlx5_action_handle_flush(struct rte_eth_dev *dev) 10552 { 10553 struct rte_flow_error error; 10554 struct mlx5_priv *priv = dev->data->dev_private; 10555 struct mlx5_shared_action_rss *shared_rss; 10556 int ret = 0; 10557 uint32_t idx; 10558 10559 ILIST_FOREACH(priv->sh->ipool[MLX5_IPOOL_RSS_SHARED_ACTIONS], 10560 priv->rss_shared_actions, idx, shared_rss, next) { 10561 ret |= mlx5_action_handle_destroy(dev, 10562 (struct rte_flow_action_handle *)(uintptr_t)idx, &error); 10563 } 10564 return ret; 10565 } 10566 10567 /** 10568 * Validate existing indirect actions against current device configuration 10569 * and attach them to device resources. 10570 * 10571 * @param dev 10572 * Pointer to Ethernet device. 10573 * 10574 * @return 10575 * 0 on success, a negative errno value otherwise and rte_errno is set. 10576 */ 10577 int 10578 mlx5_action_handle_attach(struct rte_eth_dev *dev) 10579 { 10580 struct mlx5_priv *priv = dev->data->dev_private; 10581 int ret = 0; 10582 struct mlx5_ind_table_obj *ind_tbl, *ind_tbl_last; 10583 10584 LIST_FOREACH(ind_tbl, &priv->standalone_ind_tbls, next) { 10585 const char *message; 10586 uint32_t queue_idx; 10587 10588 ret = mlx5_validate_rss_queues(dev, ind_tbl->queues, 10589 ind_tbl->queues_n, 10590 &message, &queue_idx); 10591 if (ret != 0) { 10592 DRV_LOG(ERR, "Port %u cannot use queue %u in RSS: %s", 10593 dev->data->port_id, ind_tbl->queues[queue_idx], 10594 message); 10595 break; 10596 } 10597 } 10598 if (ret != 0) 10599 return ret; 10600 LIST_FOREACH(ind_tbl, &priv->standalone_ind_tbls, next) { 10601 ret = mlx5_ind_table_obj_attach(dev, ind_tbl); 10602 if (ret != 0) { 10603 DRV_LOG(ERR, "Port %u could not attach " 10604 "indirection table obj %p", 10605 dev->data->port_id, (void *)ind_tbl); 10606 goto error; 10607 } 10608 } 10609 10610 return 0; 10611 error: 10612 ind_tbl_last = ind_tbl; 10613 LIST_FOREACH(ind_tbl, &priv->standalone_ind_tbls, next) { 10614 if (ind_tbl == ind_tbl_last) 10615 break; 10616 if (mlx5_ind_table_obj_detach(dev, ind_tbl) != 0) 10617 DRV_LOG(CRIT, "Port %u could not detach " 10618 "indirection table obj %p on rollback", 10619 dev->data->port_id, (void *)ind_tbl); 10620 } 10621 return ret; 10622 } 10623 10624 /** 10625 * Detach indirect actions of the device from its resources. 10626 * 10627 * @param dev 10628 * Pointer to Ethernet device. 10629 * 10630 * @return 10631 * 0 on success, a negative errno value otherwise and rte_errno is set. 10632 */ 10633 int 10634 mlx5_action_handle_detach(struct rte_eth_dev *dev) 10635 { 10636 struct mlx5_priv *priv = dev->data->dev_private; 10637 int ret = 0; 10638 struct mlx5_ind_table_obj *ind_tbl, *ind_tbl_last; 10639 10640 LIST_FOREACH(ind_tbl, &priv->standalone_ind_tbls, next) { 10641 ret = mlx5_ind_table_obj_detach(dev, ind_tbl); 10642 if (ret != 0) { 10643 DRV_LOG(ERR, "Port %u could not detach " 10644 "indirection table obj %p", 10645 dev->data->port_id, (void *)ind_tbl); 10646 goto error; 10647 } 10648 } 10649 return 0; 10650 error: 10651 ind_tbl_last = ind_tbl; 10652 LIST_FOREACH(ind_tbl, &priv->standalone_ind_tbls, next) { 10653 if (ind_tbl == ind_tbl_last) 10654 break; 10655 if (mlx5_ind_table_obj_attach(dev, ind_tbl) != 0) 10656 DRV_LOG(CRIT, "Port %u could not attach " 10657 "indirection table obj %p on rollback", 10658 dev->data->port_id, (void *)ind_tbl); 10659 } 10660 return ret; 10661 } 10662 10663 #ifndef HAVE_MLX5DV_DR 10664 #define MLX5_DOMAIN_SYNC_FLOW ((1 << 0) | (1 << 1)) 10665 #else 10666 #define MLX5_DOMAIN_SYNC_FLOW \ 10667 (MLX5DV_DR_DOMAIN_SYNC_FLAGS_SW | MLX5DV_DR_DOMAIN_SYNC_FLAGS_HW) 10668 #endif 10669 10670 int rte_pmd_mlx5_sync_flow(uint16_t port_id, uint32_t domains) 10671 { 10672 struct rte_eth_dev *dev = &rte_eth_devices[port_id]; 10673 const struct mlx5_flow_driver_ops *fops; 10674 int ret; 10675 struct rte_flow_attr attr = { .transfer = 0 }; 10676 10677 fops = flow_get_drv_ops(flow_get_drv_type(dev, &attr)); 10678 ret = fops->sync_domain(dev, domains, MLX5_DOMAIN_SYNC_FLOW); 10679 if (ret > 0) 10680 ret = -ret; 10681 return ret; 10682 } 10683 10684 const struct mlx5_flow_tunnel * 10685 mlx5_get_tof(const struct rte_flow_item *item, 10686 const struct rte_flow_action *action, 10687 enum mlx5_tof_rule_type *rule_type) 10688 { 10689 for (; item->type != RTE_FLOW_ITEM_TYPE_END; item++) { 10690 if (item->type == (typeof(item->type)) 10691 MLX5_RTE_FLOW_ITEM_TYPE_TUNNEL) { 10692 *rule_type = MLX5_TUNNEL_OFFLOAD_MATCH_RULE; 10693 return flow_items_to_tunnel(item); 10694 } 10695 } 10696 for (; action->conf != RTE_FLOW_ACTION_TYPE_END; action++) { 10697 if (action->type == (typeof(action->type)) 10698 MLX5_RTE_FLOW_ACTION_TYPE_TUNNEL_SET) { 10699 *rule_type = MLX5_TUNNEL_OFFLOAD_SET_RULE; 10700 return flow_actions_to_tunnel(action); 10701 } 10702 } 10703 return NULL; 10704 } 10705 10706 /** 10707 * tunnel offload functionality is defined for DV environment only 10708 */ 10709 #ifdef HAVE_IBV_FLOW_DV_SUPPORT 10710 __extension__ 10711 union tunnel_offload_mark { 10712 uint32_t val; 10713 struct { 10714 uint32_t app_reserve:8; 10715 uint32_t table_id:15; 10716 uint32_t transfer:1; 10717 uint32_t _unused_:8; 10718 }; 10719 }; 10720 10721 static bool 10722 mlx5_access_tunnel_offload_db 10723 (struct rte_eth_dev *dev, 10724 bool (*match)(struct rte_eth_dev *, 10725 struct mlx5_flow_tunnel *, const void *), 10726 void (*hit)(struct rte_eth_dev *, struct mlx5_flow_tunnel *, void *), 10727 void (*miss)(struct rte_eth_dev *, void *), 10728 void *ctx, bool lock_op); 10729 10730 static int 10731 flow_tunnel_add_default_miss(struct rte_eth_dev *dev, 10732 struct rte_flow *flow, 10733 const struct rte_flow_attr *attr, 10734 const struct rte_flow_action *app_actions, 10735 uint32_t flow_idx, 10736 const struct mlx5_flow_tunnel *tunnel, 10737 struct tunnel_default_miss_ctx *ctx, 10738 struct rte_flow_error *error) 10739 { 10740 struct mlx5_priv *priv = dev->data->dev_private; 10741 struct mlx5_flow *dev_flow; 10742 struct rte_flow_attr miss_attr = *attr; 10743 const struct rte_flow_item miss_items[2] = { 10744 { 10745 .type = RTE_FLOW_ITEM_TYPE_ETH, 10746 .spec = NULL, 10747 .last = NULL, 10748 .mask = NULL 10749 }, 10750 { 10751 .type = RTE_FLOW_ITEM_TYPE_END, 10752 .spec = NULL, 10753 .last = NULL, 10754 .mask = NULL 10755 } 10756 }; 10757 union tunnel_offload_mark mark_id; 10758 struct rte_flow_action_mark miss_mark; 10759 struct rte_flow_action miss_actions[3] = { 10760 [0] = { .type = RTE_FLOW_ACTION_TYPE_MARK, .conf = &miss_mark }, 10761 [2] = { .type = RTE_FLOW_ACTION_TYPE_END, .conf = NULL } 10762 }; 10763 const struct rte_flow_action_jump *jump_data; 10764 uint32_t i, flow_table = 0; /* prevent compilation warning */ 10765 struct flow_grp_info grp_info = { 10766 .external = 1, 10767 .transfer = attr->transfer, 10768 .fdb_def_rule = !!priv->fdb_def_rule, 10769 .std_tbl_fix = 0, 10770 }; 10771 int ret; 10772 10773 if (!attr->transfer) { 10774 uint32_t q_size; 10775 10776 miss_actions[1].type = RTE_FLOW_ACTION_TYPE_RSS; 10777 q_size = priv->reta_idx_n * sizeof(ctx->queue[0]); 10778 ctx->queue = mlx5_malloc(MLX5_MEM_SYS | MLX5_MEM_ZERO, q_size, 10779 0, SOCKET_ID_ANY); 10780 if (!ctx->queue) 10781 return rte_flow_error_set 10782 (error, ENOMEM, 10783 RTE_FLOW_ERROR_TYPE_ACTION_CONF, 10784 NULL, "invalid default miss RSS"); 10785 ctx->action_rss.func = RTE_ETH_HASH_FUNCTION_DEFAULT, 10786 ctx->action_rss.level = 0, 10787 ctx->action_rss.types = priv->rss_conf.rss_hf, 10788 ctx->action_rss.key_len = priv->rss_conf.rss_key_len, 10789 ctx->action_rss.queue_num = priv->reta_idx_n, 10790 ctx->action_rss.key = priv->rss_conf.rss_key, 10791 ctx->action_rss.queue = ctx->queue; 10792 if (!priv->reta_idx_n || !priv->rxqs_n) 10793 return rte_flow_error_set 10794 (error, EINVAL, 10795 RTE_FLOW_ERROR_TYPE_ACTION_CONF, 10796 NULL, "invalid port configuration"); 10797 if (!(dev->data->dev_conf.rxmode.mq_mode & RTE_ETH_MQ_RX_RSS_FLAG)) 10798 ctx->action_rss.types = 0; 10799 for (i = 0; i != priv->reta_idx_n; ++i) 10800 ctx->queue[i] = (*priv->reta_idx)[i]; 10801 } else { 10802 miss_actions[1].type = RTE_FLOW_ACTION_TYPE_JUMP; 10803 ctx->miss_jump.group = MLX5_TNL_MISS_FDB_JUMP_GRP; 10804 } 10805 miss_actions[1].conf = (typeof(miss_actions[1].conf))ctx->raw; 10806 for (; app_actions->type != RTE_FLOW_ACTION_TYPE_JUMP; app_actions++); 10807 jump_data = app_actions->conf; 10808 miss_attr.priority = MLX5_TNL_MISS_RULE_PRIORITY; 10809 miss_attr.group = jump_data->group; 10810 ret = mlx5_flow_group_to_table(dev, tunnel, jump_data->group, 10811 &flow_table, &grp_info, error); 10812 if (ret) 10813 return rte_flow_error_set(error, EINVAL, 10814 RTE_FLOW_ERROR_TYPE_ACTION_CONF, 10815 NULL, "invalid tunnel id"); 10816 mark_id.app_reserve = 0; 10817 mark_id.table_id = tunnel_flow_tbl_to_id(flow_table); 10818 mark_id.transfer = !!attr->transfer; 10819 mark_id._unused_ = 0; 10820 miss_mark.id = mark_id.val; 10821 dev_flow = flow_drv_prepare(dev, flow, &miss_attr, 10822 miss_items, miss_actions, flow_idx, error); 10823 if (!dev_flow) 10824 return -rte_errno; 10825 dev_flow->flow = flow; 10826 dev_flow->external = true; 10827 dev_flow->tunnel = tunnel; 10828 dev_flow->tof_type = MLX5_TUNNEL_OFFLOAD_MISS_RULE; 10829 /* Subflow object was created, we must include one in the list. */ 10830 SILIST_INSERT(&flow->dev_handles, dev_flow->handle_idx, 10831 dev_flow->handle, next); 10832 DRV_LOG(DEBUG, 10833 "port %u tunnel type=%d id=%u miss rule priority=%u group=%u", 10834 dev->data->port_id, tunnel->app_tunnel.type, 10835 tunnel->tunnel_id, miss_attr.priority, miss_attr.group); 10836 ret = flow_drv_translate(dev, dev_flow, &miss_attr, miss_items, 10837 miss_actions, error); 10838 if (!ret) 10839 ret = flow_mreg_update_copy_table(dev, flow, miss_actions, 10840 error); 10841 10842 return ret; 10843 } 10844 10845 static const struct mlx5_flow_tbl_data_entry * 10846 tunnel_mark_decode(struct rte_eth_dev *dev, uint32_t mark) 10847 { 10848 struct mlx5_priv *priv = dev->data->dev_private; 10849 struct mlx5_dev_ctx_shared *sh = priv->sh; 10850 struct mlx5_list_entry *he; 10851 union tunnel_offload_mark mbits = { .val = mark }; 10852 union mlx5_flow_tbl_key table_key = { 10853 { 10854 .level = tunnel_id_to_flow_tbl(mbits.table_id), 10855 .id = 0, 10856 .reserved = 0, 10857 .dummy = 0, 10858 .is_fdb = !!mbits.transfer, 10859 .is_egress = 0, 10860 } 10861 }; 10862 struct mlx5_flow_cb_ctx ctx = { 10863 .data = &table_key.v64, 10864 }; 10865 10866 he = mlx5_hlist_lookup(sh->flow_tbls, table_key.v64, &ctx); 10867 return he ? 10868 container_of(he, struct mlx5_flow_tbl_data_entry, entry) : NULL; 10869 } 10870 10871 static void 10872 mlx5_flow_tunnel_grp2tbl_remove_cb(void *tool_ctx, 10873 struct mlx5_list_entry *entry) 10874 { 10875 struct mlx5_dev_ctx_shared *sh = tool_ctx; 10876 struct tunnel_tbl_entry *tte = container_of(entry, typeof(*tte), hash); 10877 10878 mlx5_ipool_free(sh->ipool[MLX5_IPOOL_TNL_TBL_ID], 10879 tunnel_flow_tbl_to_id(tte->flow_table)); 10880 mlx5_free(tte); 10881 } 10882 10883 static int 10884 mlx5_flow_tunnel_grp2tbl_match_cb(void *tool_ctx __rte_unused, 10885 struct mlx5_list_entry *entry, void *cb_ctx) 10886 { 10887 struct mlx5_flow_cb_ctx *ctx = cb_ctx; 10888 union tunnel_tbl_key tbl = { 10889 .val = *(uint64_t *)(ctx->data), 10890 }; 10891 struct tunnel_tbl_entry *tte = container_of(entry, typeof(*tte), hash); 10892 10893 return tbl.tunnel_id != tte->tunnel_id || tbl.group != tte->group; 10894 } 10895 10896 static struct mlx5_list_entry * 10897 mlx5_flow_tunnel_grp2tbl_create_cb(void *tool_ctx, void *cb_ctx) 10898 { 10899 struct mlx5_dev_ctx_shared *sh = tool_ctx; 10900 struct mlx5_flow_cb_ctx *ctx = cb_ctx; 10901 struct tunnel_tbl_entry *tte; 10902 union tunnel_tbl_key tbl = { 10903 .val = *(uint64_t *)(ctx->data), 10904 }; 10905 10906 tte = mlx5_malloc(MLX5_MEM_SYS | MLX5_MEM_ZERO, 10907 sizeof(*tte), 0, 10908 SOCKET_ID_ANY); 10909 if (!tte) 10910 goto err; 10911 mlx5_ipool_malloc(sh->ipool[MLX5_IPOOL_TNL_TBL_ID], 10912 &tte->flow_table); 10913 if (tte->flow_table >= MLX5_MAX_TABLES) { 10914 DRV_LOG(ERR, "Tunnel TBL ID %d exceed max limit.", 10915 tte->flow_table); 10916 mlx5_ipool_free(sh->ipool[MLX5_IPOOL_TNL_TBL_ID], 10917 tte->flow_table); 10918 goto err; 10919 } else if (!tte->flow_table) { 10920 goto err; 10921 } 10922 tte->flow_table = tunnel_id_to_flow_tbl(tte->flow_table); 10923 tte->tunnel_id = tbl.tunnel_id; 10924 tte->group = tbl.group; 10925 return &tte->hash; 10926 err: 10927 if (tte) 10928 mlx5_free(tte); 10929 return NULL; 10930 } 10931 10932 static struct mlx5_list_entry * 10933 mlx5_flow_tunnel_grp2tbl_clone_cb(void *tool_ctx __rte_unused, 10934 struct mlx5_list_entry *oentry, 10935 void *cb_ctx __rte_unused) 10936 { 10937 struct tunnel_tbl_entry *tte = mlx5_malloc(MLX5_MEM_SYS, sizeof(*tte), 10938 0, SOCKET_ID_ANY); 10939 10940 if (!tte) 10941 return NULL; 10942 memcpy(tte, oentry, sizeof(*tte)); 10943 return &tte->hash; 10944 } 10945 10946 static void 10947 mlx5_flow_tunnel_grp2tbl_clone_free_cb(void *tool_ctx __rte_unused, 10948 struct mlx5_list_entry *entry) 10949 { 10950 struct tunnel_tbl_entry *tte = container_of(entry, typeof(*tte), hash); 10951 10952 mlx5_free(tte); 10953 } 10954 10955 static uint32_t 10956 tunnel_flow_group_to_flow_table(struct rte_eth_dev *dev, 10957 const struct mlx5_flow_tunnel *tunnel, 10958 uint32_t group, uint32_t *table, 10959 struct rte_flow_error *error) 10960 { 10961 struct mlx5_list_entry *he; 10962 struct tunnel_tbl_entry *tte; 10963 union tunnel_tbl_key key = { 10964 .tunnel_id = tunnel ? tunnel->tunnel_id : 0, 10965 .group = group 10966 }; 10967 struct mlx5_flow_tunnel_hub *thub = mlx5_tunnel_hub(dev); 10968 struct mlx5_hlist *group_hash; 10969 struct mlx5_flow_cb_ctx ctx = { 10970 .data = &key.val, 10971 }; 10972 10973 group_hash = tunnel ? tunnel->groups : thub->groups; 10974 he = mlx5_hlist_register(group_hash, key.val, &ctx); 10975 if (!he) 10976 return rte_flow_error_set(error, EINVAL, 10977 RTE_FLOW_ERROR_TYPE_ATTR_GROUP, 10978 NULL, 10979 "tunnel group index not supported"); 10980 tte = container_of(he, typeof(*tte), hash); 10981 *table = tte->flow_table; 10982 DRV_LOG(DEBUG, "port %u tunnel %u group=%#x table=%#x", 10983 dev->data->port_id, key.tunnel_id, group, *table); 10984 return 0; 10985 } 10986 10987 static void 10988 mlx5_flow_tunnel_free(struct rte_eth_dev *dev, 10989 struct mlx5_flow_tunnel *tunnel) 10990 { 10991 struct mlx5_priv *priv = dev->data->dev_private; 10992 struct mlx5_indexed_pool *ipool; 10993 10994 DRV_LOG(DEBUG, "port %u release pmd tunnel id=0x%x", 10995 dev->data->port_id, tunnel->tunnel_id); 10996 LIST_REMOVE(tunnel, chain); 10997 mlx5_hlist_destroy(tunnel->groups); 10998 ipool = priv->sh->ipool[MLX5_IPOOL_TUNNEL_ID]; 10999 mlx5_ipool_free(ipool, tunnel->tunnel_id); 11000 } 11001 11002 static bool 11003 mlx5_access_tunnel_offload_db 11004 (struct rte_eth_dev *dev, 11005 bool (*match)(struct rte_eth_dev *, 11006 struct mlx5_flow_tunnel *, const void *), 11007 void (*hit)(struct rte_eth_dev *, struct mlx5_flow_tunnel *, void *), 11008 void (*miss)(struct rte_eth_dev *, void *), 11009 void *ctx, bool lock_op) 11010 { 11011 bool verdict = false; 11012 struct mlx5_flow_tunnel_hub *thub = mlx5_tunnel_hub(dev); 11013 struct mlx5_flow_tunnel *tunnel; 11014 11015 rte_spinlock_lock(&thub->sl); 11016 LIST_FOREACH(tunnel, &thub->tunnels, chain) { 11017 verdict = match(dev, tunnel, (const void *)ctx); 11018 if (verdict) 11019 break; 11020 } 11021 if (!lock_op) 11022 rte_spinlock_unlock(&thub->sl); 11023 if (verdict && hit) 11024 hit(dev, tunnel, ctx); 11025 if (!verdict && miss) 11026 miss(dev, ctx); 11027 if (lock_op) 11028 rte_spinlock_unlock(&thub->sl); 11029 11030 return verdict; 11031 } 11032 11033 struct tunnel_db_find_tunnel_id_ctx { 11034 uint32_t tunnel_id; 11035 struct mlx5_flow_tunnel *tunnel; 11036 }; 11037 11038 static bool 11039 find_tunnel_id_match(struct rte_eth_dev *dev, 11040 struct mlx5_flow_tunnel *tunnel, const void *x) 11041 { 11042 const struct tunnel_db_find_tunnel_id_ctx *ctx = x; 11043 11044 RTE_SET_USED(dev); 11045 return tunnel->tunnel_id == ctx->tunnel_id; 11046 } 11047 11048 static void 11049 find_tunnel_id_hit(struct rte_eth_dev *dev, 11050 struct mlx5_flow_tunnel *tunnel, void *x) 11051 { 11052 struct tunnel_db_find_tunnel_id_ctx *ctx = x; 11053 RTE_SET_USED(dev); 11054 ctx->tunnel = tunnel; 11055 } 11056 11057 static struct mlx5_flow_tunnel * 11058 mlx5_find_tunnel_id(struct rte_eth_dev *dev, uint32_t id) 11059 { 11060 struct tunnel_db_find_tunnel_id_ctx ctx = { 11061 .tunnel_id = id, 11062 }; 11063 11064 mlx5_access_tunnel_offload_db(dev, find_tunnel_id_match, 11065 find_tunnel_id_hit, NULL, &ctx, true); 11066 11067 return ctx.tunnel; 11068 } 11069 11070 static struct mlx5_flow_tunnel * 11071 mlx5_flow_tunnel_allocate(struct rte_eth_dev *dev, 11072 const struct rte_flow_tunnel *app_tunnel) 11073 { 11074 struct mlx5_priv *priv = dev->data->dev_private; 11075 struct mlx5_indexed_pool *ipool; 11076 struct mlx5_flow_tunnel *tunnel; 11077 uint32_t id; 11078 11079 ipool = priv->sh->ipool[MLX5_IPOOL_TUNNEL_ID]; 11080 tunnel = mlx5_ipool_zmalloc(ipool, &id); 11081 if (!tunnel) 11082 return NULL; 11083 if (id >= MLX5_MAX_TUNNELS) { 11084 mlx5_ipool_free(ipool, id); 11085 DRV_LOG(ERR, "Tunnel ID %d exceed max limit.", id); 11086 return NULL; 11087 } 11088 tunnel->groups = mlx5_hlist_create("tunnel groups", 64, false, true, 11089 priv->sh, 11090 mlx5_flow_tunnel_grp2tbl_create_cb, 11091 mlx5_flow_tunnel_grp2tbl_match_cb, 11092 mlx5_flow_tunnel_grp2tbl_remove_cb, 11093 mlx5_flow_tunnel_grp2tbl_clone_cb, 11094 mlx5_flow_tunnel_grp2tbl_clone_free_cb); 11095 if (!tunnel->groups) { 11096 mlx5_ipool_free(ipool, id); 11097 return NULL; 11098 } 11099 /* initiate new PMD tunnel */ 11100 memcpy(&tunnel->app_tunnel, app_tunnel, sizeof(*app_tunnel)); 11101 tunnel->tunnel_id = id; 11102 tunnel->action.type = (typeof(tunnel->action.type)) 11103 MLX5_RTE_FLOW_ACTION_TYPE_TUNNEL_SET; 11104 tunnel->action.conf = tunnel; 11105 tunnel->item.type = (typeof(tunnel->item.type)) 11106 MLX5_RTE_FLOW_ITEM_TYPE_TUNNEL; 11107 tunnel->item.spec = tunnel; 11108 tunnel->item.last = NULL; 11109 tunnel->item.mask = NULL; 11110 11111 DRV_LOG(DEBUG, "port %u new pmd tunnel id=0x%x", 11112 dev->data->port_id, tunnel->tunnel_id); 11113 11114 return tunnel; 11115 } 11116 11117 struct tunnel_db_get_tunnel_ctx { 11118 const struct rte_flow_tunnel *app_tunnel; 11119 struct mlx5_flow_tunnel *tunnel; 11120 }; 11121 11122 static bool get_tunnel_match(struct rte_eth_dev *dev, 11123 struct mlx5_flow_tunnel *tunnel, const void *x) 11124 { 11125 const struct tunnel_db_get_tunnel_ctx *ctx = x; 11126 11127 RTE_SET_USED(dev); 11128 return !memcmp(ctx->app_tunnel, &tunnel->app_tunnel, 11129 sizeof(*ctx->app_tunnel)); 11130 } 11131 11132 static void get_tunnel_hit(struct rte_eth_dev *dev, 11133 struct mlx5_flow_tunnel *tunnel, void *x) 11134 { 11135 /* called under tunnel spinlock protection */ 11136 struct tunnel_db_get_tunnel_ctx *ctx = x; 11137 11138 RTE_SET_USED(dev); 11139 tunnel->refctn++; 11140 ctx->tunnel = tunnel; 11141 } 11142 11143 static void get_tunnel_miss(struct rte_eth_dev *dev, void *x) 11144 { 11145 /* called under tunnel spinlock protection */ 11146 struct mlx5_flow_tunnel_hub *thub = mlx5_tunnel_hub(dev); 11147 struct tunnel_db_get_tunnel_ctx *ctx = x; 11148 11149 rte_spinlock_unlock(&thub->sl); 11150 ctx->tunnel = mlx5_flow_tunnel_allocate(dev, ctx->app_tunnel); 11151 rte_spinlock_lock(&thub->sl); 11152 if (ctx->tunnel) { 11153 ctx->tunnel->refctn = 1; 11154 LIST_INSERT_HEAD(&thub->tunnels, ctx->tunnel, chain); 11155 } 11156 } 11157 11158 11159 static int 11160 mlx5_get_flow_tunnel(struct rte_eth_dev *dev, 11161 const struct rte_flow_tunnel *app_tunnel, 11162 struct mlx5_flow_tunnel **tunnel) 11163 { 11164 struct tunnel_db_get_tunnel_ctx ctx = { 11165 .app_tunnel = app_tunnel, 11166 }; 11167 11168 mlx5_access_tunnel_offload_db(dev, get_tunnel_match, get_tunnel_hit, 11169 get_tunnel_miss, &ctx, true); 11170 *tunnel = ctx.tunnel; 11171 return ctx.tunnel ? 0 : -ENOMEM; 11172 } 11173 11174 void mlx5_release_tunnel_hub(struct mlx5_dev_ctx_shared *sh, uint16_t port_id) 11175 { 11176 struct mlx5_flow_tunnel_hub *thub = sh->tunnel_hub; 11177 11178 if (!thub) 11179 return; 11180 if (!LIST_EMPTY(&thub->tunnels)) 11181 DRV_LOG(WARNING, "port %u tunnels present", port_id); 11182 mlx5_hlist_destroy(thub->groups); 11183 mlx5_free(thub); 11184 } 11185 11186 int mlx5_alloc_tunnel_hub(struct mlx5_dev_ctx_shared *sh) 11187 { 11188 int err; 11189 struct mlx5_flow_tunnel_hub *thub; 11190 11191 thub = mlx5_malloc(MLX5_MEM_SYS | MLX5_MEM_ZERO, sizeof(*thub), 11192 0, SOCKET_ID_ANY); 11193 if (!thub) 11194 return -ENOMEM; 11195 LIST_INIT(&thub->tunnels); 11196 rte_spinlock_init(&thub->sl); 11197 thub->groups = mlx5_hlist_create("flow groups", 64, 11198 false, true, sh, 11199 mlx5_flow_tunnel_grp2tbl_create_cb, 11200 mlx5_flow_tunnel_grp2tbl_match_cb, 11201 mlx5_flow_tunnel_grp2tbl_remove_cb, 11202 mlx5_flow_tunnel_grp2tbl_clone_cb, 11203 mlx5_flow_tunnel_grp2tbl_clone_free_cb); 11204 if (!thub->groups) { 11205 err = -rte_errno; 11206 goto err; 11207 } 11208 sh->tunnel_hub = thub; 11209 11210 return 0; 11211 11212 err: 11213 if (thub->groups) 11214 mlx5_hlist_destroy(thub->groups); 11215 if (thub) 11216 mlx5_free(thub); 11217 return err; 11218 } 11219 11220 static inline int 11221 mlx5_flow_tunnel_validate(struct rte_eth_dev *dev, 11222 struct rte_flow_tunnel *tunnel, 11223 struct rte_flow_error *error) 11224 { 11225 struct mlx5_priv *priv = dev->data->dev_private; 11226 11227 if (!priv->sh->config.dv_flow_en) 11228 return rte_flow_error_set(error, ENOTSUP, 11229 RTE_FLOW_ERROR_TYPE_ACTION_CONF, NULL, 11230 "flow DV interface is off"); 11231 if (!is_tunnel_offload_active(dev)) 11232 return rte_flow_error_set(error, ENOTSUP, 11233 RTE_FLOW_ERROR_TYPE_ACTION_CONF, NULL, 11234 "tunnel offload was not activated, consider setting dv_xmeta_en=3"); 11235 if (!tunnel) 11236 return rte_flow_error_set(error, EINVAL, 11237 RTE_FLOW_ERROR_TYPE_ACTION_CONF, NULL, 11238 "no application tunnel"); 11239 switch (tunnel->type) { 11240 default: 11241 return rte_flow_error_set(error, EINVAL, 11242 RTE_FLOW_ERROR_TYPE_ACTION_CONF, NULL, 11243 "unsupported tunnel type"); 11244 case RTE_FLOW_ITEM_TYPE_VXLAN: 11245 case RTE_FLOW_ITEM_TYPE_GRE: 11246 case RTE_FLOW_ITEM_TYPE_NVGRE: 11247 case RTE_FLOW_ITEM_TYPE_GENEVE: 11248 break; 11249 } 11250 return 0; 11251 } 11252 11253 static int 11254 mlx5_flow_tunnel_decap_set(struct rte_eth_dev *dev, 11255 struct rte_flow_tunnel *app_tunnel, 11256 struct rte_flow_action **actions, 11257 uint32_t *num_of_actions, 11258 struct rte_flow_error *error) 11259 { 11260 struct mlx5_flow_tunnel *tunnel; 11261 int ret = mlx5_flow_tunnel_validate(dev, app_tunnel, error); 11262 11263 if (ret) 11264 return ret; 11265 ret = mlx5_get_flow_tunnel(dev, app_tunnel, &tunnel); 11266 if (ret < 0) { 11267 return rte_flow_error_set(error, ret, 11268 RTE_FLOW_ERROR_TYPE_ACTION_CONF, NULL, 11269 "failed to initialize pmd tunnel"); 11270 } 11271 *actions = &tunnel->action; 11272 *num_of_actions = 1; 11273 return 0; 11274 } 11275 11276 static int 11277 mlx5_flow_tunnel_match(struct rte_eth_dev *dev, 11278 struct rte_flow_tunnel *app_tunnel, 11279 struct rte_flow_item **items, 11280 uint32_t *num_of_items, 11281 struct rte_flow_error *error) 11282 { 11283 struct mlx5_flow_tunnel *tunnel; 11284 int ret = mlx5_flow_tunnel_validate(dev, app_tunnel, error); 11285 11286 if (ret) 11287 return ret; 11288 ret = mlx5_get_flow_tunnel(dev, app_tunnel, &tunnel); 11289 if (ret < 0) { 11290 return rte_flow_error_set(error, ret, 11291 RTE_FLOW_ERROR_TYPE_HANDLE, NULL, 11292 "failed to initialize pmd tunnel"); 11293 } 11294 *items = &tunnel->item; 11295 *num_of_items = 1; 11296 return 0; 11297 } 11298 11299 struct tunnel_db_element_release_ctx { 11300 struct rte_flow_item *items; 11301 struct rte_flow_action *actions; 11302 uint32_t num_elements; 11303 struct rte_flow_error *error; 11304 int ret; 11305 }; 11306 11307 static bool 11308 tunnel_element_release_match(struct rte_eth_dev *dev, 11309 struct mlx5_flow_tunnel *tunnel, const void *x) 11310 { 11311 const struct tunnel_db_element_release_ctx *ctx = x; 11312 11313 RTE_SET_USED(dev); 11314 if (ctx->num_elements != 1) 11315 return false; 11316 else if (ctx->items) 11317 return ctx->items == &tunnel->item; 11318 else if (ctx->actions) 11319 return ctx->actions == &tunnel->action; 11320 11321 return false; 11322 } 11323 11324 static void 11325 tunnel_element_release_hit(struct rte_eth_dev *dev, 11326 struct mlx5_flow_tunnel *tunnel, void *x) 11327 { 11328 struct tunnel_db_element_release_ctx *ctx = x; 11329 ctx->ret = 0; 11330 if (!(__atomic_fetch_sub(&tunnel->refctn, 1, __ATOMIC_RELAXED) - 1)) 11331 mlx5_flow_tunnel_free(dev, tunnel); 11332 } 11333 11334 static void 11335 tunnel_element_release_miss(struct rte_eth_dev *dev, void *x) 11336 { 11337 struct tunnel_db_element_release_ctx *ctx = x; 11338 RTE_SET_USED(dev); 11339 ctx->ret = rte_flow_error_set(ctx->error, EINVAL, 11340 RTE_FLOW_ERROR_TYPE_HANDLE, NULL, 11341 "invalid argument"); 11342 } 11343 11344 static int 11345 mlx5_flow_tunnel_item_release(struct rte_eth_dev *dev, 11346 struct rte_flow_item *pmd_items, 11347 uint32_t num_items, struct rte_flow_error *err) 11348 { 11349 struct tunnel_db_element_release_ctx ctx = { 11350 .items = pmd_items, 11351 .actions = NULL, 11352 .num_elements = num_items, 11353 .error = err, 11354 }; 11355 11356 mlx5_access_tunnel_offload_db(dev, tunnel_element_release_match, 11357 tunnel_element_release_hit, 11358 tunnel_element_release_miss, &ctx, false); 11359 11360 return ctx.ret; 11361 } 11362 11363 static int 11364 mlx5_flow_tunnel_action_release(struct rte_eth_dev *dev, 11365 struct rte_flow_action *pmd_actions, 11366 uint32_t num_actions, struct rte_flow_error *err) 11367 { 11368 struct tunnel_db_element_release_ctx ctx = { 11369 .items = NULL, 11370 .actions = pmd_actions, 11371 .num_elements = num_actions, 11372 .error = err, 11373 }; 11374 11375 mlx5_access_tunnel_offload_db(dev, tunnel_element_release_match, 11376 tunnel_element_release_hit, 11377 tunnel_element_release_miss, &ctx, false); 11378 11379 return ctx.ret; 11380 } 11381 11382 static int 11383 mlx5_flow_tunnel_get_restore_info(struct rte_eth_dev *dev, 11384 struct rte_mbuf *m, 11385 struct rte_flow_restore_info *info, 11386 struct rte_flow_error *err) 11387 { 11388 uint64_t ol_flags = m->ol_flags; 11389 const struct mlx5_flow_tbl_data_entry *tble; 11390 const uint64_t mask = RTE_MBUF_F_RX_FDIR | RTE_MBUF_F_RX_FDIR_ID; 11391 struct mlx5_priv *priv = dev->data->dev_private; 11392 11393 if (priv->tunnel_enabled == 0) 11394 goto err; 11395 if ((ol_flags & mask) != mask) 11396 goto err; 11397 tble = tunnel_mark_decode(dev, m->hash.fdir.hi); 11398 if (!tble) { 11399 DRV_LOG(DEBUG, "port %u invalid miss tunnel mark %#x", 11400 dev->data->port_id, m->hash.fdir.hi); 11401 goto err; 11402 } 11403 MLX5_ASSERT(tble->tunnel); 11404 memcpy(&info->tunnel, &tble->tunnel->app_tunnel, sizeof(info->tunnel)); 11405 info->group_id = tble->group_id; 11406 info->flags = RTE_FLOW_RESTORE_INFO_TUNNEL | 11407 RTE_FLOW_RESTORE_INFO_GROUP_ID | 11408 RTE_FLOW_RESTORE_INFO_ENCAPSULATED; 11409 11410 return 0; 11411 11412 err: 11413 return rte_flow_error_set(err, EINVAL, 11414 RTE_FLOW_ERROR_TYPE_UNSPECIFIED, NULL, 11415 "failed to get restore info"); 11416 } 11417 11418 #else /* HAVE_IBV_FLOW_DV_SUPPORT */ 11419 static int 11420 mlx5_flow_tunnel_decap_set(__rte_unused struct rte_eth_dev *dev, 11421 __rte_unused struct rte_flow_tunnel *app_tunnel, 11422 __rte_unused struct rte_flow_action **actions, 11423 __rte_unused uint32_t *num_of_actions, 11424 __rte_unused struct rte_flow_error *error) 11425 { 11426 return -ENOTSUP; 11427 } 11428 11429 static int 11430 mlx5_flow_tunnel_match(__rte_unused struct rte_eth_dev *dev, 11431 __rte_unused struct rte_flow_tunnel *app_tunnel, 11432 __rte_unused struct rte_flow_item **items, 11433 __rte_unused uint32_t *num_of_items, 11434 __rte_unused struct rte_flow_error *error) 11435 { 11436 return -ENOTSUP; 11437 } 11438 11439 static int 11440 mlx5_flow_tunnel_item_release(__rte_unused struct rte_eth_dev *dev, 11441 __rte_unused struct rte_flow_item *pmd_items, 11442 __rte_unused uint32_t num_items, 11443 __rte_unused struct rte_flow_error *err) 11444 { 11445 return -ENOTSUP; 11446 } 11447 11448 static int 11449 mlx5_flow_tunnel_action_release(__rte_unused struct rte_eth_dev *dev, 11450 __rte_unused struct rte_flow_action *pmd_action, 11451 __rte_unused uint32_t num_actions, 11452 __rte_unused struct rte_flow_error *err) 11453 { 11454 return -ENOTSUP; 11455 } 11456 11457 static int 11458 mlx5_flow_tunnel_get_restore_info(__rte_unused struct rte_eth_dev *dev, 11459 __rte_unused struct rte_mbuf *m, 11460 __rte_unused struct rte_flow_restore_info *i, 11461 __rte_unused struct rte_flow_error *err) 11462 { 11463 return -ENOTSUP; 11464 } 11465 11466 static int 11467 flow_tunnel_add_default_miss(__rte_unused struct rte_eth_dev *dev, 11468 __rte_unused struct rte_flow *flow, 11469 __rte_unused const struct rte_flow_attr *attr, 11470 __rte_unused const struct rte_flow_action *actions, 11471 __rte_unused uint32_t flow_idx, 11472 __rte_unused const struct mlx5_flow_tunnel *tunnel, 11473 __rte_unused struct tunnel_default_miss_ctx *ctx, 11474 __rte_unused struct rte_flow_error *error) 11475 { 11476 return -ENOTSUP; 11477 } 11478 11479 static struct mlx5_flow_tunnel * 11480 mlx5_find_tunnel_id(__rte_unused struct rte_eth_dev *dev, 11481 __rte_unused uint32_t id) 11482 { 11483 return NULL; 11484 } 11485 11486 static void 11487 mlx5_flow_tunnel_free(__rte_unused struct rte_eth_dev *dev, 11488 __rte_unused struct mlx5_flow_tunnel *tunnel) 11489 { 11490 } 11491 11492 static uint32_t 11493 tunnel_flow_group_to_flow_table(__rte_unused struct rte_eth_dev *dev, 11494 __rte_unused const struct mlx5_flow_tunnel *t, 11495 __rte_unused uint32_t group, 11496 __rte_unused uint32_t *table, 11497 struct rte_flow_error *error) 11498 { 11499 return rte_flow_error_set(error, ENOTSUP, 11500 RTE_FLOW_ERROR_TYPE_UNSPECIFIED, NULL, 11501 "tunnel offload requires DV support"); 11502 } 11503 11504 void 11505 mlx5_release_tunnel_hub(__rte_unused struct mlx5_dev_ctx_shared *sh, 11506 __rte_unused uint16_t port_id) 11507 { 11508 } 11509 #endif /* HAVE_IBV_FLOW_DV_SUPPORT */ 11510 11511 /* Flex flow item API */ 11512 static struct rte_flow_item_flex_handle * 11513 mlx5_flow_flex_item_create(struct rte_eth_dev *dev, 11514 const struct rte_flow_item_flex_conf *conf, 11515 struct rte_flow_error *error) 11516 { 11517 static const char err_msg[] = "flex item creation unsupported"; 11518 struct mlx5_priv *priv = dev->data->dev_private; 11519 struct rte_flow_attr attr = { .transfer = 0 }; 11520 const struct mlx5_flow_driver_ops *fops = 11521 flow_get_drv_ops(flow_get_drv_type(dev, &attr)); 11522 11523 if (!priv->pci_dev) { 11524 rte_flow_error_set(error, ENOTSUP, 11525 RTE_FLOW_ERROR_TYPE_UNSPECIFIED, NULL, 11526 "create flex item on PF only"); 11527 return NULL; 11528 } 11529 switch (priv->pci_dev->id.device_id) { 11530 case PCI_DEVICE_ID_MELLANOX_BLUEFIELD2: 11531 case PCI_DEVICE_ID_MELLANOX_BLUEFIELD3: 11532 break; 11533 default: 11534 rte_flow_error_set(error, ENOTSUP, 11535 RTE_FLOW_ERROR_TYPE_UNSPECIFIED, NULL, 11536 "flex item available on BlueField ports only"); 11537 return NULL; 11538 } 11539 if (!fops->item_create) { 11540 DRV_LOG(ERR, "port %u %s.", dev->data->port_id, err_msg); 11541 rte_flow_error_set(error, ENOTSUP, RTE_FLOW_ERROR_TYPE_ACTION, 11542 NULL, err_msg); 11543 return NULL; 11544 } 11545 return fops->item_create(dev, conf, error); 11546 } 11547 11548 static int 11549 mlx5_flow_flex_item_release(struct rte_eth_dev *dev, 11550 const struct rte_flow_item_flex_handle *handle, 11551 struct rte_flow_error *error) 11552 { 11553 static const char err_msg[] = "flex item release unsupported"; 11554 struct rte_flow_attr attr = { .transfer = 0 }; 11555 const struct mlx5_flow_driver_ops *fops = 11556 flow_get_drv_ops(flow_get_drv_type(dev, &attr)); 11557 11558 if (!fops->item_release) { 11559 DRV_LOG(ERR, "port %u %s.", dev->data->port_id, err_msg); 11560 rte_flow_error_set(error, ENOTSUP, RTE_FLOW_ERROR_TYPE_ACTION, 11561 NULL, err_msg); 11562 return -rte_errno; 11563 } 11564 return fops->item_release(dev, handle, error); 11565 } 11566 11567 static void 11568 mlx5_dbg__print_pattern(const struct rte_flow_item *item) 11569 { 11570 int ret; 11571 struct rte_flow_error error; 11572 11573 for (; item->type != RTE_FLOW_ITEM_TYPE_END; item++) { 11574 char *item_name; 11575 ret = rte_flow_conv(RTE_FLOW_CONV_OP_ITEM_NAME_PTR, &item_name, 11576 sizeof(item_name), 11577 (void *)(uintptr_t)item->type, &error); 11578 if (ret > 0) 11579 printf("%s ", item_name); 11580 else 11581 printf("%d\n", (int)item->type); 11582 } 11583 printf("END\n"); 11584 } 11585 11586 static int 11587 mlx5_flow_is_std_vxlan_port(const struct rte_flow_item *udp_item) 11588 { 11589 const struct rte_flow_item_udp *spec = udp_item->spec; 11590 const struct rte_flow_item_udp *mask = udp_item->mask; 11591 uint16_t udp_dport = 0; 11592 11593 if (spec != NULL) { 11594 if (!mask) 11595 mask = &rte_flow_item_udp_mask; 11596 udp_dport = rte_be_to_cpu_16(spec->hdr.dst_port & 11597 mask->hdr.dst_port); 11598 } 11599 return (!udp_dport || udp_dport == MLX5_UDP_PORT_VXLAN); 11600 } 11601 11602 static const struct mlx5_flow_expand_node * 11603 mlx5_flow_expand_rss_adjust_node(const struct rte_flow_item *pattern, 11604 unsigned int item_idx, 11605 const struct mlx5_flow_expand_node graph[], 11606 const struct mlx5_flow_expand_node *node) 11607 { 11608 const struct rte_flow_item *item = pattern + item_idx, *prev_item; 11609 11610 if (item->type == RTE_FLOW_ITEM_TYPE_VXLAN && 11611 node != NULL && 11612 node->type == RTE_FLOW_ITEM_TYPE_VXLAN) { 11613 /* 11614 * The expansion node is VXLAN and it is also the last 11615 * expandable item in the pattern, so need to continue 11616 * expansion of the inner tunnel. 11617 */ 11618 MLX5_ASSERT(item_idx > 0); 11619 prev_item = pattern + item_idx - 1; 11620 MLX5_ASSERT(prev_item->type == RTE_FLOW_ITEM_TYPE_UDP); 11621 if (mlx5_flow_is_std_vxlan_port(prev_item)) 11622 return &graph[MLX5_EXPANSION_STD_VXLAN]; 11623 return &graph[MLX5_EXPANSION_L3_VXLAN]; 11624 } 11625 return node; 11626 } 11627 11628 /* Map of Verbs to Flow priority with 8 Verbs priorities. */ 11629 static const uint32_t priority_map_3[][MLX5_PRIORITY_MAP_MAX] = { 11630 { 0, 1, 2 }, { 2, 3, 4 }, { 5, 6, 7 }, 11631 }; 11632 11633 /* Map of Verbs to Flow priority with 16 Verbs priorities. */ 11634 static const uint32_t priority_map_5[][MLX5_PRIORITY_MAP_MAX] = { 11635 { 0, 1, 2 }, { 3, 4, 5 }, { 6, 7, 8 }, 11636 { 9, 10, 11 }, { 12, 13, 14 }, 11637 }; 11638 11639 /** 11640 * Discover the number of available flow priorities. 11641 * 11642 * @param dev 11643 * Ethernet device. 11644 * 11645 * @return 11646 * On success, number of available flow priorities. 11647 * On failure, a negative errno-style code and rte_errno is set. 11648 */ 11649 int 11650 mlx5_flow_discover_priorities(struct rte_eth_dev *dev) 11651 { 11652 static const uint16_t vprio[] = {8, 16}; 11653 const struct mlx5_priv *priv = dev->data->dev_private; 11654 const struct mlx5_flow_driver_ops *fops; 11655 enum mlx5_flow_drv_type type; 11656 int ret; 11657 11658 type = mlx5_flow_os_get_type(); 11659 if (type == MLX5_FLOW_TYPE_MAX) { 11660 type = MLX5_FLOW_TYPE_VERBS; 11661 if (priv->sh->cdev->config.devx && priv->sh->config.dv_flow_en) 11662 type = MLX5_FLOW_TYPE_DV; 11663 } 11664 fops = flow_get_drv_ops(type); 11665 if (fops->discover_priorities == NULL) { 11666 DRV_LOG(ERR, "Priority discovery not supported"); 11667 rte_errno = ENOTSUP; 11668 return -rte_errno; 11669 } 11670 ret = fops->discover_priorities(dev, vprio, RTE_DIM(vprio)); 11671 if (ret < 0) 11672 return ret; 11673 switch (ret) { 11674 case 8: 11675 ret = RTE_DIM(priority_map_3); 11676 break; 11677 case 16: 11678 ret = RTE_DIM(priority_map_5); 11679 break; 11680 default: 11681 rte_errno = ENOTSUP; 11682 DRV_LOG(ERR, 11683 "port %u maximum priority: %d expected 8/16", 11684 dev->data->port_id, ret); 11685 return -rte_errno; 11686 } 11687 DRV_LOG(INFO, "port %u supported flow priorities:" 11688 " 0-%d for ingress or egress root table," 11689 " 0-%d for non-root table or transfer root table.", 11690 dev->data->port_id, ret - 2, 11691 MLX5_NON_ROOT_FLOW_MAX_PRIO - 1); 11692 return ret; 11693 } 11694 11695 /** 11696 * Adjust flow priority based on the highest layer and the request priority. 11697 * 11698 * @param[in] dev 11699 * Pointer to the Ethernet device structure. 11700 * @param[in] priority 11701 * The rule base priority. 11702 * @param[in] subpriority 11703 * The priority based on the items. 11704 * 11705 * @return 11706 * The new priority. 11707 */ 11708 uint32_t 11709 mlx5_flow_adjust_priority(struct rte_eth_dev *dev, int32_t priority, 11710 uint32_t subpriority) 11711 { 11712 uint32_t res = 0; 11713 struct mlx5_priv *priv = dev->data->dev_private; 11714 11715 switch (priv->sh->flow_max_priority) { 11716 case RTE_DIM(priority_map_3): 11717 res = priority_map_3[priority][subpriority]; 11718 break; 11719 case RTE_DIM(priority_map_5): 11720 res = priority_map_5[priority][subpriority]; 11721 break; 11722 } 11723 return res; 11724 } 11725 11726 /** 11727 * Get the priority for sending traffic to kernel table. 11728 * 11729 * @param[in] dev 11730 * Pointer to the Ethernet device structure. 11731 * 11732 * @return 11733 * On success: the value of priority for sending traffic to kernel table 11734 * On failure: -1 11735 */ 11736 uint32_t 11737 mlx5_get_send_to_kernel_priority(struct rte_eth_dev *dev) 11738 { 11739 struct mlx5_priv *priv = dev->data->dev_private; 11740 uint32_t res; 11741 11742 switch (priv->sh->flow_max_priority) { 11743 case RTE_DIM(priority_map_5): 11744 res = 15; 11745 break; 11746 case RTE_DIM(priority_map_3): 11747 res = 7; 11748 break; 11749 default: 11750 DRV_LOG(ERR, 11751 "port %u maximum priority: %d expected 8/16", 11752 dev->data->port_id, priv->sh->flow_max_priority); 11753 res = (uint32_t)-1; 11754 } 11755 return res; 11756 } 11757 11758 /** 11759 * Get the E-Switch Manager vport id. 11760 * 11761 * @param[in] dev 11762 * Pointer to the Ethernet device structure. 11763 * 11764 * @return 11765 * The vport id. 11766 */ 11767 int16_t mlx5_flow_get_esw_manager_vport_id(struct rte_eth_dev *dev) 11768 { 11769 struct mlx5_priv *priv = dev->data->dev_private; 11770 struct mlx5_common_device *cdev = priv->sh->cdev; 11771 11772 /* New FW exposes E-Switch Manager vport ID, can use it directly. */ 11773 if (cdev->config.hca_attr.esw_mgr_vport_id_valid) 11774 return (int16_t)cdev->config.hca_attr.esw_mgr_vport_id; 11775 11776 if (priv->pci_dev == NULL) 11777 return 0; 11778 switch (priv->pci_dev->id.device_id) { 11779 case PCI_DEVICE_ID_MELLANOX_BLUEFIELD: 11780 case PCI_DEVICE_ID_MELLANOX_BLUEFIELD2: 11781 case PCI_DEVICE_ID_MELLANOX_BLUEFIELD3: 11782 /* 11783 * In old FW which doesn't expose the E-Switch Manager vport ID in the capability, 11784 * only the BF embedded CPUs control the E-Switch Manager port. Hence, 11785 * ECPF vport ID is selected and not the host port (0) in any BF case. 11786 */ 11787 return (int16_t)MLX5_ECPF_VPORT_ID; 11788 default: 11789 return MLX5_PF_VPORT_ID; 11790 } 11791 } 11792 11793 /** 11794 * Parse item to get the vport id. 11795 * 11796 * @param[in] dev 11797 * Pointer to the Ethernet device structure. 11798 * @param[in] item 11799 * The src port id match item. 11800 * @param[out] vport_id 11801 * Pointer to put the vport id. 11802 * @param[out] all_ports 11803 * Indicate if the item matches all ports. 11804 * @param[out] error 11805 * Pointer to error structure. 11806 * 11807 * @return 11808 * 0 on success, a negative errno value otherwise and rte_errno is set. 11809 */ 11810 int mlx5_flow_get_item_vport_id(struct rte_eth_dev *dev, 11811 const struct rte_flow_item *item, 11812 uint16_t *vport_id, 11813 bool *all_ports, 11814 struct rte_flow_error *error) 11815 { 11816 struct mlx5_priv *port_priv; 11817 const struct rte_flow_item_port_id *pid_v = NULL; 11818 const struct rte_flow_item_ethdev *dev_v = NULL; 11819 uint32_t esw_mgr_port; 11820 uint32_t src_port; 11821 11822 if (all_ports) 11823 *all_ports = false; 11824 switch (item->type) { 11825 case RTE_FLOW_ITEM_TYPE_PORT_ID: 11826 pid_v = item->spec; 11827 if (!pid_v) 11828 return 0; 11829 src_port = pid_v->id; 11830 esw_mgr_port = MLX5_PORT_ESW_MGR; 11831 break; 11832 case RTE_FLOW_ITEM_TYPE_REPRESENTED_PORT: 11833 dev_v = item->spec; 11834 if (!dev_v) { 11835 if (all_ports) 11836 *all_ports = true; 11837 return 0; 11838 } 11839 src_port = dev_v->port_id; 11840 esw_mgr_port = MLX5_REPRESENTED_PORT_ESW_MGR; 11841 break; 11842 case RTE_FLOW_ITEM_TYPE_PORT_REPRESENTOR: 11843 src_port = MLX5_REPRESENTED_PORT_ESW_MGR; 11844 esw_mgr_port = MLX5_REPRESENTED_PORT_ESW_MGR; 11845 break; 11846 default: 11847 return rte_flow_error_set(error, EINVAL, RTE_FLOW_ERROR_TYPE_ITEM_SPEC, 11848 NULL, "Incorrect item type."); 11849 } 11850 if (src_port == esw_mgr_port) { 11851 *vport_id = mlx5_flow_get_esw_manager_vport_id(dev); 11852 } else { 11853 port_priv = mlx5_port_to_eswitch_info(src_port, false); 11854 if (!port_priv) 11855 return rte_flow_error_set(error, EINVAL, RTE_FLOW_ERROR_TYPE_ITEM_SPEC, 11856 NULL, "Failed to get port info."); 11857 *vport_id = port_priv->representor_id; 11858 } 11859 11860 return 0; 11861 } 11862 11863 int 11864 mlx5_flow_pick_transfer_proxy(struct rte_eth_dev *dev, 11865 uint16_t *proxy_port_id, 11866 struct rte_flow_error *error) 11867 { 11868 const struct mlx5_priv *priv = dev->data->dev_private; 11869 uint16_t port_id; 11870 11871 if (!priv->sh->config.dv_esw_en) 11872 return rte_flow_error_set(error, EINVAL, 11873 RTE_FLOW_ERROR_TYPE_UNSPECIFIED, 11874 NULL, 11875 "unable to provide a proxy port" 11876 " without E-Switch configured"); 11877 if (!priv->master && !priv->representor) 11878 return rte_flow_error_set(error, EINVAL, 11879 RTE_FLOW_ERROR_TYPE_UNSPECIFIED, 11880 NULL, 11881 "unable to provide a proxy port" 11882 " for port which is not a master" 11883 " or a representor port"); 11884 if (priv->master) { 11885 *proxy_port_id = dev->data->port_id; 11886 return 0; 11887 } 11888 MLX5_ETH_FOREACH_DEV(port_id, dev->device) { 11889 const struct rte_eth_dev *port_dev = &rte_eth_devices[port_id]; 11890 const struct mlx5_priv *port_priv = port_dev->data->dev_private; 11891 11892 if (port_priv->master && 11893 port_priv->domain_id == priv->domain_id) { 11894 *proxy_port_id = port_id; 11895 return 0; 11896 } 11897 } 11898 return rte_flow_error_set(error, ENODEV, 11899 RTE_FLOW_ERROR_TYPE_UNSPECIFIED, 11900 NULL, "unable to find a proxy port"); 11901 } 11902