1 /* SPDX-License-Identifier: BSD-3-Clause 2 * Copyright 2016 6WIND S.A. 3 * Copyright 2016 Mellanox Technologies, Ltd 4 */ 5 6 #include <stdalign.h> 7 #include <stdint.h> 8 #include <string.h> 9 #include <stdbool.h> 10 #include <sys/queue.h> 11 12 #include <rte_common.h> 13 #include <rte_ether.h> 14 #include <ethdev_driver.h> 15 #include <rte_eal_paging.h> 16 #include <rte_flow.h> 17 #include <rte_cycles.h> 18 #include <rte_flow_driver.h> 19 #include <rte_malloc.h> 20 #include <rte_ip.h> 21 22 #include <mlx5_glue.h> 23 #include <mlx5_devx_cmds.h> 24 #include <mlx5_prm.h> 25 #include <mlx5_malloc.h> 26 27 #include "mlx5_defs.h" 28 #include "mlx5.h" 29 #include "mlx5_flow.h" 30 #include "mlx5_flow_os.h" 31 #include "mlx5_rx.h" 32 #include "mlx5_tx.h" 33 #include "mlx5_common_os.h" 34 #include "rte_pmd_mlx5.h" 35 36 /* 37 * Shared array for quick translation between port_id and vport mask/values 38 * used for HWS rules. 39 */ 40 struct flow_hw_port_info mlx5_flow_hw_port_infos[RTE_MAX_ETHPORTS]; 41 42 /* 43 * A global structure to save the available REG_C_x for tags usage. 44 * The Meter color REG (ASO) and the last available one will be reserved 45 * for PMD internal usage. 46 * Since there is no "port" concept in the driver, it is assumed that the 47 * available tags set will be the minimum intersection. 48 * 3 - in FDB mode / 5 - in legacy mode 49 */ 50 uint32_t mlx5_flow_hw_avl_tags_init_cnt; 51 enum modify_reg mlx5_flow_hw_avl_tags[MLX5_FLOW_HW_TAGS_MAX] = {REG_NON}; 52 enum modify_reg mlx5_flow_hw_aso_tag; 53 54 struct tunnel_default_miss_ctx { 55 uint16_t *queue; 56 __extension__ 57 union { 58 struct rte_flow_action_rss action_rss; 59 struct rte_flow_action_queue miss_queue; 60 struct rte_flow_action_jump miss_jump; 61 uint8_t raw[0]; 62 }; 63 }; 64 65 void 66 mlx5_indirect_list_handles_release(struct rte_eth_dev *dev) 67 { 68 struct mlx5_priv *priv = dev->data->dev_private; 69 #ifdef HAVE_MLX5_HWS_SUPPORT 70 struct rte_flow_error error; 71 #endif 72 73 while (!LIST_EMPTY(&priv->indirect_list_head)) { 74 struct mlx5_indirect_list *e = 75 LIST_FIRST(&priv->indirect_list_head); 76 77 LIST_REMOVE(e, entry); 78 switch (e->type) { 79 #ifdef HAVE_MLX5_HWS_SUPPORT 80 case MLX5_INDIRECT_ACTION_LIST_TYPE_MIRROR: 81 mlx5_hw_mirror_destroy(dev, (struct mlx5_mirror *)e); 82 break; 83 case MLX5_INDIRECT_ACTION_LIST_TYPE_LEGACY: 84 mlx5_destroy_legacy_indirect(dev, e); 85 break; 86 case MLX5_INDIRECT_ACTION_LIST_TYPE_REFORMAT: 87 mlx5_reformat_action_destroy(dev, 88 (struct rte_flow_action_list_handle *)e, &error); 89 break; 90 #endif 91 default: 92 DRV_LOG(ERR, "invalid indirect list type"); 93 MLX5_ASSERT(false); 94 break; 95 } 96 } 97 } 98 99 static int 100 flow_tunnel_add_default_miss(struct rte_eth_dev *dev, 101 struct rte_flow *flow, 102 const struct rte_flow_attr *attr, 103 const struct rte_flow_action *app_actions, 104 uint32_t flow_idx, 105 const struct mlx5_flow_tunnel *tunnel, 106 struct tunnel_default_miss_ctx *ctx, 107 struct rte_flow_error *error); 108 static struct mlx5_flow_tunnel * 109 mlx5_find_tunnel_id(struct rte_eth_dev *dev, uint32_t id); 110 static void 111 mlx5_flow_tunnel_free(struct rte_eth_dev *dev, struct mlx5_flow_tunnel *tunnel); 112 static uint32_t 113 tunnel_flow_group_to_flow_table(struct rte_eth_dev *dev, 114 const struct mlx5_flow_tunnel *tunnel, 115 uint32_t group, uint32_t *table, 116 struct rte_flow_error *error); 117 118 /** Device flow drivers. */ 119 extern const struct mlx5_flow_driver_ops mlx5_flow_verbs_drv_ops; 120 121 const struct mlx5_flow_driver_ops mlx5_flow_null_drv_ops; 122 123 const struct mlx5_flow_driver_ops *flow_drv_ops[] = { 124 [MLX5_FLOW_TYPE_MIN] = &mlx5_flow_null_drv_ops, 125 #if defined(HAVE_IBV_FLOW_DV_SUPPORT) || !defined(HAVE_INFINIBAND_VERBS_H) 126 [MLX5_FLOW_TYPE_DV] = &mlx5_flow_dv_drv_ops, 127 #endif 128 #ifdef HAVE_MLX5_HWS_SUPPORT 129 [MLX5_FLOW_TYPE_HW] = &mlx5_flow_hw_drv_ops, 130 #endif 131 [MLX5_FLOW_TYPE_VERBS] = &mlx5_flow_verbs_drv_ops, 132 [MLX5_FLOW_TYPE_MAX] = &mlx5_flow_null_drv_ops 133 }; 134 135 /** Helper macro to build input graph for mlx5_flow_expand_rss(). */ 136 #define MLX5_FLOW_EXPAND_RSS_NEXT(...) \ 137 (const int []){ \ 138 __VA_ARGS__, 0, \ 139 } 140 141 /** Node object of input graph for mlx5_flow_expand_rss(). */ 142 struct mlx5_flow_expand_node { 143 const int *const next; 144 /**< 145 * List of next node indexes. Index 0 is interpreted as a terminator. 146 */ 147 const enum rte_flow_item_type type; 148 /**< Pattern item type of current node. */ 149 uint64_t rss_types; 150 /**< 151 * RSS types bit-field associated with this node 152 * (see RTE_ETH_RSS_* definitions). 153 */ 154 uint64_t node_flags; 155 /**< 156 * Bit-fields that define how the node is used in the expansion. 157 * (see MLX5_EXPANSION_NODE_* definitions). 158 */ 159 }; 160 161 /** Keep same format with mlx5_flow_expand_rss to share the buffer for expansion. */ 162 struct mlx5_flow_expand_sqn { 163 uint32_t entries; /** Number of entries */ 164 struct { 165 struct rte_flow_item *pattern; /**< Expanded pattern array. */ 166 uint32_t priority; /**< Priority offset for each expansion. */ 167 } entry[]; 168 }; 169 170 /* Optional expand field. The expansion alg will not go deeper. */ 171 #define MLX5_EXPANSION_NODE_OPTIONAL (UINT64_C(1) << 0) 172 173 /* The node is not added implicitly as expansion to the flow pattern. 174 * If the node type does not match the flow pattern item type, the 175 * expansion alg will go deeper to its next items. 176 * In the current implementation, the list of next nodes indexes can 177 * have up to one node with this flag set and it has to be the last 178 * node index (before the list terminator). 179 */ 180 #define MLX5_EXPANSION_NODE_EXPLICIT (UINT64_C(1) << 1) 181 182 /** Object returned by mlx5_flow_expand_rss(). */ 183 struct mlx5_flow_expand_rss { 184 uint32_t entries; 185 /**< Number of entries @p patterns and @p priorities. */ 186 struct { 187 struct rte_flow_item *pattern; /**< Expanded pattern array. */ 188 uint32_t priority; /**< Priority offset for each expansion. */ 189 } entry[]; 190 }; 191 192 static void 193 mlx5_dbg__print_pattern(const struct rte_flow_item *item); 194 195 static const struct mlx5_flow_expand_node * 196 mlx5_flow_expand_rss_adjust_node(const struct rte_flow_item *pattern, 197 unsigned int item_idx, 198 const struct mlx5_flow_expand_node graph[], 199 const struct mlx5_flow_expand_node *node); 200 201 static __rte_always_inline int 202 mlx5_need_cache_flow(const struct mlx5_priv *priv, 203 const struct rte_flow_attr *attr) 204 { 205 return priv->isolated && priv->sh->config.dv_flow_en == 1 && 206 (attr ? !attr->group : true) && 207 priv->mode_info.mode == MLX5_FLOW_ENGINE_MODE_STANDBY && 208 (!priv->sh->config.dv_esw_en || !priv->sh->config.fdb_def_rule); 209 } 210 211 static bool 212 mlx5_flow_is_rss_expandable_item(const struct rte_flow_item *item) 213 { 214 switch (item->type) { 215 case RTE_FLOW_ITEM_TYPE_ETH: 216 case RTE_FLOW_ITEM_TYPE_VLAN: 217 case RTE_FLOW_ITEM_TYPE_IPV4: 218 case RTE_FLOW_ITEM_TYPE_IPV6: 219 case RTE_FLOW_ITEM_TYPE_UDP: 220 case RTE_FLOW_ITEM_TYPE_TCP: 221 case RTE_FLOW_ITEM_TYPE_ESP: 222 case RTE_FLOW_ITEM_TYPE_ICMP: 223 case RTE_FLOW_ITEM_TYPE_ICMP6: 224 case RTE_FLOW_ITEM_TYPE_VXLAN: 225 case RTE_FLOW_ITEM_TYPE_NVGRE: 226 case RTE_FLOW_ITEM_TYPE_GRE: 227 case RTE_FLOW_ITEM_TYPE_GENEVE: 228 case RTE_FLOW_ITEM_TYPE_MPLS: 229 case RTE_FLOW_ITEM_TYPE_VXLAN_GPE: 230 case RTE_FLOW_ITEM_TYPE_GRE_KEY: 231 case RTE_FLOW_ITEM_TYPE_IPV6_FRAG_EXT: 232 case RTE_FLOW_ITEM_TYPE_GTP: 233 return true; 234 default: 235 break; 236 } 237 return false; 238 } 239 240 /** 241 * Network Service Header (NSH) and its next protocol values 242 * are described in RFC-8393. 243 */ 244 static enum rte_flow_item_type 245 mlx5_nsh_proto_to_item_type(uint8_t proto_spec, uint8_t proto_mask) 246 { 247 enum rte_flow_item_type type; 248 249 switch (proto_mask & proto_spec) { 250 case 0: 251 type = RTE_FLOW_ITEM_TYPE_VOID; 252 break; 253 case RTE_VXLAN_GPE_TYPE_IPV4: 254 type = RTE_FLOW_ITEM_TYPE_IPV4; 255 break; 256 case RTE_VXLAN_GPE_TYPE_IPV6: 257 type = RTE_VXLAN_GPE_TYPE_IPV6; 258 break; 259 case RTE_VXLAN_GPE_TYPE_ETH: 260 type = RTE_FLOW_ITEM_TYPE_ETH; 261 break; 262 default: 263 type = RTE_FLOW_ITEM_TYPE_END; 264 } 265 return type; 266 } 267 268 static enum rte_flow_item_type 269 mlx5_inet_proto_to_item_type(uint8_t proto_spec, uint8_t proto_mask) 270 { 271 enum rte_flow_item_type type; 272 273 switch (proto_mask & proto_spec) { 274 case 0: 275 type = RTE_FLOW_ITEM_TYPE_VOID; 276 break; 277 case IPPROTO_UDP: 278 type = RTE_FLOW_ITEM_TYPE_UDP; 279 break; 280 case IPPROTO_TCP: 281 type = RTE_FLOW_ITEM_TYPE_TCP; 282 break; 283 case IPPROTO_IPIP: 284 type = RTE_FLOW_ITEM_TYPE_IPV4; 285 break; 286 case IPPROTO_IPV6: 287 type = RTE_FLOW_ITEM_TYPE_IPV6; 288 break; 289 case IPPROTO_ESP: 290 type = RTE_FLOW_ITEM_TYPE_ESP; 291 break; 292 default: 293 type = RTE_FLOW_ITEM_TYPE_END; 294 } 295 return type; 296 } 297 298 static enum rte_flow_item_type 299 mlx5_ethertype_to_item_type(rte_be16_t type_spec, 300 rte_be16_t type_mask, bool is_tunnel) 301 { 302 enum rte_flow_item_type type; 303 304 switch (rte_be_to_cpu_16(type_spec & type_mask)) { 305 case 0: 306 type = RTE_FLOW_ITEM_TYPE_VOID; 307 break; 308 case RTE_ETHER_TYPE_TEB: 309 type = is_tunnel ? 310 RTE_FLOW_ITEM_TYPE_ETH : RTE_FLOW_ITEM_TYPE_END; 311 break; 312 case RTE_ETHER_TYPE_VLAN: 313 type = !is_tunnel ? 314 RTE_FLOW_ITEM_TYPE_VLAN : RTE_FLOW_ITEM_TYPE_END; 315 break; 316 case RTE_ETHER_TYPE_IPV4: 317 type = RTE_FLOW_ITEM_TYPE_IPV4; 318 break; 319 case RTE_ETHER_TYPE_IPV6: 320 type = RTE_FLOW_ITEM_TYPE_IPV6; 321 break; 322 default: 323 type = RTE_FLOW_ITEM_TYPE_END; 324 } 325 return type; 326 } 327 328 static enum rte_flow_item_type 329 mlx5_flow_expand_rss_item_complete(const struct rte_flow_item *item) 330 { 331 #define MLX5_XSET_ITEM_MASK_SPEC(type, fld) \ 332 do { \ 333 const void *m = item->mask; \ 334 const void *s = item->spec; \ 335 mask = m ? \ 336 ((const struct rte_flow_item_##type *)m)->fld : \ 337 rte_flow_item_##type##_mask.fld; \ 338 spec = ((const struct rte_flow_item_##type *)s)->fld; \ 339 } while (0) 340 341 enum rte_flow_item_type ret; 342 uint16_t spec, mask; 343 344 if (item == NULL || item->spec == NULL) 345 return RTE_FLOW_ITEM_TYPE_VOID; 346 switch (item->type) { 347 case RTE_FLOW_ITEM_TYPE_ETH: 348 MLX5_XSET_ITEM_MASK_SPEC(eth, hdr.ether_type); 349 if (!mask) 350 return RTE_FLOW_ITEM_TYPE_VOID; 351 ret = mlx5_ethertype_to_item_type(spec, mask, false); 352 break; 353 case RTE_FLOW_ITEM_TYPE_VLAN: 354 MLX5_XSET_ITEM_MASK_SPEC(vlan, hdr.eth_proto); 355 if (!mask) 356 return RTE_FLOW_ITEM_TYPE_VOID; 357 ret = mlx5_ethertype_to_item_type(spec, mask, false); 358 break; 359 case RTE_FLOW_ITEM_TYPE_IPV4: 360 MLX5_XSET_ITEM_MASK_SPEC(ipv4, hdr.next_proto_id); 361 if (!mask) 362 return RTE_FLOW_ITEM_TYPE_VOID; 363 ret = mlx5_inet_proto_to_item_type(spec, mask); 364 break; 365 case RTE_FLOW_ITEM_TYPE_IPV6: 366 MLX5_XSET_ITEM_MASK_SPEC(ipv6, hdr.proto); 367 if (!mask) 368 return RTE_FLOW_ITEM_TYPE_VOID; 369 ret = mlx5_inet_proto_to_item_type(spec, mask); 370 break; 371 case RTE_FLOW_ITEM_TYPE_GENEVE: 372 MLX5_XSET_ITEM_MASK_SPEC(geneve, protocol); 373 ret = mlx5_ethertype_to_item_type(spec, mask, true); 374 break; 375 case RTE_FLOW_ITEM_TYPE_GRE: 376 MLX5_XSET_ITEM_MASK_SPEC(gre, protocol); 377 ret = mlx5_ethertype_to_item_type(spec, mask, true); 378 break; 379 case RTE_FLOW_ITEM_TYPE_VXLAN_GPE: 380 MLX5_XSET_ITEM_MASK_SPEC(vxlan_gpe, hdr.proto); 381 ret = mlx5_nsh_proto_to_item_type(spec, mask); 382 break; 383 default: 384 ret = RTE_FLOW_ITEM_TYPE_VOID; 385 break; 386 } 387 return ret; 388 #undef MLX5_XSET_ITEM_MASK_SPEC 389 } 390 391 static const int * 392 mlx5_flow_expand_rss_skip_explicit(const struct mlx5_flow_expand_node graph[], 393 const int *next_node) 394 { 395 const struct mlx5_flow_expand_node *node = NULL; 396 const int *next = next_node; 397 398 while (next && *next) { 399 /* 400 * Skip the nodes with the MLX5_EXPANSION_NODE_EXPLICIT 401 * flag set, because they were not found in the flow pattern. 402 */ 403 node = &graph[*next]; 404 if (!(node->node_flags & MLX5_EXPANSION_NODE_EXPLICIT)) 405 break; 406 next = node->next; 407 } 408 return next; 409 } 410 411 #define MLX5_RSS_EXP_ELT_N 32 412 413 /** 414 * Expand RSS flows into several possible flows according to the RSS hash 415 * fields requested and the driver capabilities. 416 * 417 * @param[out] buf 418 * Buffer to store the result expansion. 419 * @param[in] size 420 * Buffer size in bytes. If 0, @p buf can be NULL. 421 * @param[in] pattern 422 * User flow pattern. 423 * @param[in] types 424 * RSS types to expand (see RTE_ETH_RSS_* definitions). 425 * @param[in] graph 426 * Input graph to expand @p pattern according to @p types. 427 * @param[in] graph_root_index 428 * Index of root node in @p graph, typically 0. 429 * 430 * @return 431 * A positive value representing the size of @p buf in bytes regardless of 432 * @p size on success, a negative errno value otherwise and rte_errno is 433 * set, the following errors are defined: 434 * 435 * -E2BIG: graph-depth @p graph is too deep. 436 * -EINVAL: @p size has not enough space for expanded pattern. 437 */ 438 static int 439 mlx5_flow_expand_rss(struct mlx5_flow_expand_rss *buf, size_t size, 440 const struct rte_flow_item *pattern, uint64_t types, 441 const struct mlx5_flow_expand_node graph[], 442 int graph_root_index) 443 { 444 const struct rte_flow_item *item; 445 const struct mlx5_flow_expand_node *node = &graph[graph_root_index]; 446 const int *next_node; 447 const int *stack[MLX5_RSS_EXP_ELT_N]; 448 int stack_pos = 0; 449 struct rte_flow_item flow_items[MLX5_RSS_EXP_ELT_N]; 450 unsigned int i, item_idx, last_expand_item_idx = 0; 451 size_t lsize; 452 size_t user_pattern_size = 0; 453 void *addr = NULL; 454 const struct mlx5_flow_expand_node *next = NULL; 455 struct rte_flow_item missed_item; 456 int missed = 0; 457 int elt = 0; 458 const struct rte_flow_item *last_expand_item = NULL; 459 460 memset(&missed_item, 0, sizeof(missed_item)); 461 lsize = offsetof(struct mlx5_flow_expand_rss, entry) + 462 MLX5_RSS_EXP_ELT_N * sizeof(buf->entry[0]); 463 if (lsize > size) 464 return -EINVAL; 465 buf->entry[0].priority = 0; 466 buf->entry[0].pattern = (void *)&buf->entry[MLX5_RSS_EXP_ELT_N]; 467 buf->entries = 0; 468 addr = buf->entry[0].pattern; 469 for (item = pattern, item_idx = 0; 470 item->type != RTE_FLOW_ITEM_TYPE_END; 471 item++, item_idx++) { 472 if (!mlx5_flow_is_rss_expandable_item(item)) { 473 user_pattern_size += sizeof(*item); 474 continue; 475 } 476 last_expand_item = item; 477 last_expand_item_idx = item_idx; 478 i = 0; 479 while (node->next && node->next[i]) { 480 next = &graph[node->next[i]]; 481 if (next->type == item->type) 482 break; 483 if (next->node_flags & MLX5_EXPANSION_NODE_EXPLICIT) { 484 node = next; 485 i = 0; 486 } else { 487 ++i; 488 } 489 } 490 if (next) 491 node = next; 492 user_pattern_size += sizeof(*item); 493 } 494 user_pattern_size += sizeof(*item); /* Handle END item. */ 495 lsize += user_pattern_size; 496 if (lsize > size) 497 return -EINVAL; 498 /* Copy the user pattern in the first entry of the buffer. */ 499 rte_memcpy(addr, pattern, user_pattern_size); 500 addr = (void *)(((uintptr_t)addr) + user_pattern_size); 501 buf->entries = 1; 502 /* Start expanding. */ 503 memset(flow_items, 0, sizeof(flow_items)); 504 user_pattern_size -= sizeof(*item); 505 /* 506 * Check if the last valid item has spec set, need complete pattern, 507 * and the pattern can be used for expansion. 508 */ 509 missed_item.type = mlx5_flow_expand_rss_item_complete(last_expand_item); 510 if (missed_item.type == RTE_FLOW_ITEM_TYPE_END) { 511 /* Item type END indicates expansion is not required. */ 512 return lsize; 513 } 514 if (missed_item.type != RTE_FLOW_ITEM_TYPE_VOID) { 515 next = NULL; 516 missed = 1; 517 i = 0; 518 while (node->next && node->next[i]) { 519 next = &graph[node->next[i]]; 520 if (next->type == missed_item.type) { 521 flow_items[0].type = missed_item.type; 522 flow_items[1].type = RTE_FLOW_ITEM_TYPE_END; 523 break; 524 } 525 if (next->node_flags & MLX5_EXPANSION_NODE_EXPLICIT) { 526 node = next; 527 i = 0; 528 } else { 529 ++i; 530 } 531 next = NULL; 532 } 533 } 534 if (next && missed) { 535 elt = 2; /* missed item + item end. */ 536 node = next; 537 lsize += elt * sizeof(*item) + user_pattern_size; 538 if (lsize > size) 539 return -EINVAL; 540 if (node->rss_types & types) { 541 buf->entry[buf->entries].priority = 1; 542 buf->entry[buf->entries].pattern = addr; 543 buf->entries++; 544 rte_memcpy(addr, buf->entry[0].pattern, 545 user_pattern_size); 546 addr = (void *)(((uintptr_t)addr) + user_pattern_size); 547 rte_memcpy(addr, flow_items, elt * sizeof(*item)); 548 addr = (void *)(((uintptr_t)addr) + 549 elt * sizeof(*item)); 550 } 551 } else if (last_expand_item != NULL) { 552 node = mlx5_flow_expand_rss_adjust_node(pattern, 553 last_expand_item_idx, graph, node); 554 } 555 memset(flow_items, 0, sizeof(flow_items)); 556 next_node = mlx5_flow_expand_rss_skip_explicit(graph, 557 node->next); 558 stack[stack_pos] = next_node; 559 node = next_node ? &graph[*next_node] : NULL; 560 while (node) { 561 flow_items[stack_pos].type = node->type; 562 if (node->rss_types & types) { 563 size_t n; 564 /* 565 * compute the number of items to copy from the 566 * expansion and copy it. 567 * When the stack_pos is 0, there are 1 element in it, 568 * plus the addition END item. 569 */ 570 elt = stack_pos + 2; 571 flow_items[stack_pos + 1].type = RTE_FLOW_ITEM_TYPE_END; 572 lsize += elt * sizeof(*item) + user_pattern_size; 573 if (lsize > size) 574 return -EINVAL; 575 n = elt * sizeof(*item); 576 MLX5_ASSERT((buf->entries) < MLX5_RSS_EXP_ELT_N); 577 buf->entry[buf->entries].priority = 578 stack_pos + 1 + missed; 579 buf->entry[buf->entries].pattern = addr; 580 buf->entries++; 581 rte_memcpy(addr, buf->entry[0].pattern, 582 user_pattern_size); 583 addr = (void *)(((uintptr_t)addr) + 584 user_pattern_size); 585 rte_memcpy(addr, &missed_item, 586 missed * sizeof(*item)); 587 addr = (void *)(((uintptr_t)addr) + 588 missed * sizeof(*item)); 589 rte_memcpy(addr, flow_items, n); 590 addr = (void *)(((uintptr_t)addr) + n); 591 } 592 /* Go deeper. */ 593 if (!(node->node_flags & MLX5_EXPANSION_NODE_OPTIONAL) && 594 node->next) { 595 next_node = mlx5_flow_expand_rss_skip_explicit(graph, 596 node->next); 597 if (stack_pos++ == MLX5_RSS_EXP_ELT_N) { 598 rte_errno = E2BIG; 599 return -rte_errno; 600 } 601 stack[stack_pos] = next_node; 602 } else if (*(next_node + 1)) { 603 /* Follow up with the next possibility. */ 604 next_node = mlx5_flow_expand_rss_skip_explicit(graph, 605 ++next_node); 606 } else if (!stack_pos) { 607 /* 608 * Completing the traverse over the different paths. 609 * The next_node is advanced to the terminator. 610 */ 611 ++next_node; 612 } else { 613 /* Move to the next path. */ 614 while (stack_pos) { 615 next_node = stack[--stack_pos]; 616 next_node++; 617 if (*next_node) 618 break; 619 } 620 next_node = mlx5_flow_expand_rss_skip_explicit(graph, 621 next_node); 622 stack[stack_pos] = next_node; 623 } 624 node = next_node && *next_node ? &graph[*next_node] : NULL; 625 }; 626 return lsize; 627 } 628 629 /** 630 * Expand SQN flows into several possible flows according to the Tx queue 631 * number 632 * 633 * @param[in] buf 634 * Buffer to store the result expansion. 635 * @param[in] size 636 * Buffer size in bytes. If 0, @p buf can be NULL. 637 * @param[in] pattern 638 * User flow pattern. 639 * @param[in] sq_specs 640 * Buffer to store sq spec. 641 * 642 * @return 643 * 0 for success and negative value for failure 644 * 645 */ 646 static int 647 mlx5_flow_expand_sqn(struct mlx5_flow_expand_sqn *buf, size_t size, 648 const struct rte_flow_item *pattern, 649 struct mlx5_rte_flow_item_sq *sq_specs) 650 { 651 const struct rte_flow_item *item; 652 bool port_representor = false; 653 size_t user_pattern_size = 0; 654 struct rte_eth_dev *dev; 655 struct mlx5_priv *priv; 656 void *addr = NULL; 657 uint16_t port_id; 658 size_t lsize; 659 int elt = 2; 660 uint16_t i; 661 662 buf->entries = 0; 663 for (item = pattern; item->type != RTE_FLOW_ITEM_TYPE_END; item++) { 664 if (item->type == RTE_FLOW_ITEM_TYPE_PORT_REPRESENTOR) { 665 const struct rte_flow_item_ethdev *pid_v = item->spec; 666 667 if (!pid_v) 668 return 0; 669 port_id = pid_v->port_id; 670 port_representor = true; 671 } 672 user_pattern_size += sizeof(*item); 673 } 674 if (!port_representor) 675 return 0; 676 dev = &rte_eth_devices[port_id]; 677 priv = dev->data->dev_private; 678 buf->entry[0].pattern = (void *)&buf->entry[priv->txqs_n]; 679 lsize = offsetof(struct mlx5_flow_expand_sqn, entry) + 680 sizeof(buf->entry[0]) * priv->txqs_n; 681 if (lsize + (user_pattern_size + sizeof(struct rte_flow_item) * elt) * priv->txqs_n > size) 682 return -EINVAL; 683 addr = buf->entry[0].pattern; 684 for (i = 0; i != priv->txqs_n; ++i) { 685 struct rte_flow_item pattern_add[] = { 686 { 687 .type = (enum rte_flow_item_type) 688 MLX5_RTE_FLOW_ITEM_TYPE_SQ, 689 .spec = &sq_specs[i], 690 }, 691 { 692 .type = RTE_FLOW_ITEM_TYPE_END, 693 }, 694 }; 695 struct mlx5_txq_ctrl *txq = mlx5_txq_get(dev, i); 696 697 if (txq == NULL) 698 return -EINVAL; 699 buf->entry[i].pattern = addr; 700 sq_specs[i].queue = mlx5_txq_get_sqn(txq); 701 mlx5_txq_release(dev, i); 702 rte_memcpy(addr, pattern, user_pattern_size); 703 addr = (void *)(((uintptr_t)addr) + user_pattern_size); 704 rte_memcpy(addr, pattern_add, sizeof(struct rte_flow_item) * elt); 705 addr = (void *)(((uintptr_t)addr) + sizeof(struct rte_flow_item) * elt); 706 buf->entries++; 707 } 708 return 0; 709 } 710 711 enum mlx5_expansion { 712 MLX5_EXPANSION_ROOT, 713 MLX5_EXPANSION_ROOT_OUTER, 714 MLX5_EXPANSION_OUTER_ETH, 715 MLX5_EXPANSION_OUTER_VLAN, 716 MLX5_EXPANSION_OUTER_IPV4, 717 MLX5_EXPANSION_OUTER_IPV4_UDP, 718 MLX5_EXPANSION_OUTER_IPV4_TCP, 719 MLX5_EXPANSION_OUTER_IPV4_ESP, 720 MLX5_EXPANSION_OUTER_IPV4_ICMP, 721 MLX5_EXPANSION_OUTER_IPV6, 722 MLX5_EXPANSION_OUTER_IPV6_UDP, 723 MLX5_EXPANSION_OUTER_IPV6_TCP, 724 MLX5_EXPANSION_OUTER_IPV6_ESP, 725 MLX5_EXPANSION_OUTER_IPV6_ICMP6, 726 MLX5_EXPANSION_VXLAN, 727 MLX5_EXPANSION_STD_VXLAN, 728 MLX5_EXPANSION_L3_VXLAN, 729 MLX5_EXPANSION_VXLAN_GPE, 730 MLX5_EXPANSION_GRE, 731 MLX5_EXPANSION_NVGRE, 732 MLX5_EXPANSION_GRE_KEY, 733 MLX5_EXPANSION_MPLS, 734 MLX5_EXPANSION_ETH, 735 MLX5_EXPANSION_VLAN, 736 MLX5_EXPANSION_IPV4, 737 MLX5_EXPANSION_IPV4_UDP, 738 MLX5_EXPANSION_IPV4_TCP, 739 MLX5_EXPANSION_IPV4_ESP, 740 MLX5_EXPANSION_IPV4_ICMP, 741 MLX5_EXPANSION_IPV6, 742 MLX5_EXPANSION_IPV6_UDP, 743 MLX5_EXPANSION_IPV6_TCP, 744 MLX5_EXPANSION_IPV6_ESP, 745 MLX5_EXPANSION_IPV6_ICMP6, 746 MLX5_EXPANSION_IPV6_FRAG_EXT, 747 MLX5_EXPANSION_GTP, 748 MLX5_EXPANSION_GENEVE, 749 }; 750 751 /** Supported expansion of items. */ 752 static const struct mlx5_flow_expand_node mlx5_support_expansion[] = { 753 [MLX5_EXPANSION_ROOT] = { 754 .next = MLX5_FLOW_EXPAND_RSS_NEXT(MLX5_EXPANSION_ETH, 755 MLX5_EXPANSION_IPV4, 756 MLX5_EXPANSION_IPV6), 757 .type = RTE_FLOW_ITEM_TYPE_END, 758 }, 759 [MLX5_EXPANSION_ROOT_OUTER] = { 760 .next = MLX5_FLOW_EXPAND_RSS_NEXT(MLX5_EXPANSION_OUTER_ETH, 761 MLX5_EXPANSION_OUTER_IPV4, 762 MLX5_EXPANSION_OUTER_IPV6), 763 .type = RTE_FLOW_ITEM_TYPE_END, 764 }, 765 [MLX5_EXPANSION_OUTER_ETH] = { 766 .next = MLX5_FLOW_EXPAND_RSS_NEXT(MLX5_EXPANSION_OUTER_VLAN), 767 .type = RTE_FLOW_ITEM_TYPE_ETH, 768 .rss_types = 0, 769 }, 770 [MLX5_EXPANSION_OUTER_VLAN] = { 771 .next = MLX5_FLOW_EXPAND_RSS_NEXT(MLX5_EXPANSION_OUTER_IPV4, 772 MLX5_EXPANSION_OUTER_IPV6), 773 .type = RTE_FLOW_ITEM_TYPE_VLAN, 774 .node_flags = MLX5_EXPANSION_NODE_EXPLICIT, 775 }, 776 [MLX5_EXPANSION_OUTER_IPV4] = { 777 .next = MLX5_FLOW_EXPAND_RSS_NEXT 778 (MLX5_EXPANSION_OUTER_IPV4_UDP, 779 MLX5_EXPANSION_OUTER_IPV4_TCP, 780 MLX5_EXPANSION_OUTER_IPV4_ESP, 781 MLX5_EXPANSION_OUTER_IPV4_ICMP, 782 MLX5_EXPANSION_GRE, 783 MLX5_EXPANSION_NVGRE, 784 MLX5_EXPANSION_IPV4, 785 MLX5_EXPANSION_IPV6), 786 .type = RTE_FLOW_ITEM_TYPE_IPV4, 787 .rss_types = RTE_ETH_RSS_IPV4 | RTE_ETH_RSS_FRAG_IPV4 | 788 RTE_ETH_RSS_NONFRAG_IPV4_OTHER, 789 }, 790 [MLX5_EXPANSION_OUTER_IPV4_UDP] = { 791 .next = MLX5_FLOW_EXPAND_RSS_NEXT(MLX5_EXPANSION_VXLAN, 792 MLX5_EXPANSION_VXLAN_GPE, 793 MLX5_EXPANSION_MPLS, 794 MLX5_EXPANSION_GENEVE, 795 MLX5_EXPANSION_GTP), 796 .type = RTE_FLOW_ITEM_TYPE_UDP, 797 .rss_types = RTE_ETH_RSS_NONFRAG_IPV4_UDP, 798 }, 799 [MLX5_EXPANSION_OUTER_IPV4_TCP] = { 800 .type = RTE_FLOW_ITEM_TYPE_TCP, 801 .rss_types = RTE_ETH_RSS_NONFRAG_IPV4_TCP, 802 }, 803 [MLX5_EXPANSION_OUTER_IPV4_ESP] = { 804 .type = RTE_FLOW_ITEM_TYPE_ESP, 805 .rss_types = RTE_ETH_RSS_ESP, 806 }, 807 [MLX5_EXPANSION_OUTER_IPV4_ICMP] = { 808 .type = RTE_FLOW_ITEM_TYPE_ICMP, 809 }, 810 [MLX5_EXPANSION_OUTER_IPV6] = { 811 .next = MLX5_FLOW_EXPAND_RSS_NEXT 812 (MLX5_EXPANSION_OUTER_IPV6_UDP, 813 MLX5_EXPANSION_OUTER_IPV6_TCP, 814 MLX5_EXPANSION_OUTER_IPV6_ESP, 815 MLX5_EXPANSION_OUTER_IPV6_ICMP6, 816 MLX5_EXPANSION_IPV4, 817 MLX5_EXPANSION_IPV6, 818 MLX5_EXPANSION_GRE, 819 MLX5_EXPANSION_NVGRE), 820 .type = RTE_FLOW_ITEM_TYPE_IPV6, 821 .rss_types = RTE_ETH_RSS_IPV6 | RTE_ETH_RSS_FRAG_IPV6 | 822 RTE_ETH_RSS_NONFRAG_IPV6_OTHER, 823 }, 824 [MLX5_EXPANSION_OUTER_IPV6_UDP] = { 825 .next = MLX5_FLOW_EXPAND_RSS_NEXT(MLX5_EXPANSION_VXLAN, 826 MLX5_EXPANSION_VXLAN_GPE, 827 MLX5_EXPANSION_MPLS, 828 MLX5_EXPANSION_GENEVE, 829 MLX5_EXPANSION_GTP), 830 .type = RTE_FLOW_ITEM_TYPE_UDP, 831 .rss_types = RTE_ETH_RSS_NONFRAG_IPV6_UDP, 832 }, 833 [MLX5_EXPANSION_OUTER_IPV6_TCP] = { 834 .type = RTE_FLOW_ITEM_TYPE_TCP, 835 .rss_types = RTE_ETH_RSS_NONFRAG_IPV6_TCP, 836 }, 837 [MLX5_EXPANSION_OUTER_IPV6_ESP] = { 838 .type = RTE_FLOW_ITEM_TYPE_ESP, 839 .rss_types = RTE_ETH_RSS_ESP, 840 }, 841 [MLX5_EXPANSION_OUTER_IPV6_ICMP6] = { 842 .type = RTE_FLOW_ITEM_TYPE_ICMP6, 843 }, 844 [MLX5_EXPANSION_VXLAN] = { 845 .next = MLX5_FLOW_EXPAND_RSS_NEXT(MLX5_EXPANSION_ETH, 846 MLX5_EXPANSION_IPV4, 847 MLX5_EXPANSION_IPV6), 848 .type = RTE_FLOW_ITEM_TYPE_VXLAN, 849 }, 850 [MLX5_EXPANSION_STD_VXLAN] = { 851 .next = MLX5_FLOW_EXPAND_RSS_NEXT(MLX5_EXPANSION_ETH), 852 .type = RTE_FLOW_ITEM_TYPE_VXLAN, 853 }, 854 [MLX5_EXPANSION_L3_VXLAN] = { 855 .next = MLX5_FLOW_EXPAND_RSS_NEXT(MLX5_EXPANSION_IPV4, 856 MLX5_EXPANSION_IPV6), 857 .type = RTE_FLOW_ITEM_TYPE_VXLAN, 858 }, 859 [MLX5_EXPANSION_VXLAN_GPE] = { 860 .next = MLX5_FLOW_EXPAND_RSS_NEXT(MLX5_EXPANSION_ETH, 861 MLX5_EXPANSION_IPV4, 862 MLX5_EXPANSION_IPV6), 863 .type = RTE_FLOW_ITEM_TYPE_VXLAN_GPE, 864 }, 865 [MLX5_EXPANSION_GRE] = { 866 .next = MLX5_FLOW_EXPAND_RSS_NEXT(MLX5_EXPANSION_ETH, 867 MLX5_EXPANSION_IPV4, 868 MLX5_EXPANSION_IPV6, 869 MLX5_EXPANSION_GRE_KEY, 870 MLX5_EXPANSION_MPLS), 871 .type = RTE_FLOW_ITEM_TYPE_GRE, 872 }, 873 [MLX5_EXPANSION_GRE_KEY] = { 874 .next = MLX5_FLOW_EXPAND_RSS_NEXT(MLX5_EXPANSION_IPV4, 875 MLX5_EXPANSION_IPV6, 876 MLX5_EXPANSION_MPLS), 877 .type = RTE_FLOW_ITEM_TYPE_GRE_KEY, 878 .node_flags = MLX5_EXPANSION_NODE_OPTIONAL, 879 }, 880 [MLX5_EXPANSION_NVGRE] = { 881 .next = MLX5_FLOW_EXPAND_RSS_NEXT(MLX5_EXPANSION_ETH), 882 .type = RTE_FLOW_ITEM_TYPE_NVGRE, 883 }, 884 [MLX5_EXPANSION_MPLS] = { 885 .next = MLX5_FLOW_EXPAND_RSS_NEXT(MLX5_EXPANSION_IPV4, 886 MLX5_EXPANSION_IPV6, 887 MLX5_EXPANSION_ETH), 888 .type = RTE_FLOW_ITEM_TYPE_MPLS, 889 .node_flags = MLX5_EXPANSION_NODE_OPTIONAL, 890 }, 891 [MLX5_EXPANSION_ETH] = { 892 .next = MLX5_FLOW_EXPAND_RSS_NEXT(MLX5_EXPANSION_VLAN), 893 .type = RTE_FLOW_ITEM_TYPE_ETH, 894 }, 895 [MLX5_EXPANSION_VLAN] = { 896 .next = MLX5_FLOW_EXPAND_RSS_NEXT(MLX5_EXPANSION_IPV4, 897 MLX5_EXPANSION_IPV6), 898 .type = RTE_FLOW_ITEM_TYPE_VLAN, 899 .node_flags = MLX5_EXPANSION_NODE_EXPLICIT, 900 }, 901 [MLX5_EXPANSION_IPV4] = { 902 .next = MLX5_FLOW_EXPAND_RSS_NEXT(MLX5_EXPANSION_IPV4_UDP, 903 MLX5_EXPANSION_IPV4_TCP, 904 MLX5_EXPANSION_IPV4_ESP, 905 MLX5_EXPANSION_IPV4_ICMP), 906 .type = RTE_FLOW_ITEM_TYPE_IPV4, 907 .rss_types = RTE_ETH_RSS_IPV4 | RTE_ETH_RSS_FRAG_IPV4 | 908 RTE_ETH_RSS_NONFRAG_IPV4_OTHER, 909 }, 910 [MLX5_EXPANSION_IPV4_UDP] = { 911 .type = RTE_FLOW_ITEM_TYPE_UDP, 912 .rss_types = RTE_ETH_RSS_NONFRAG_IPV4_UDP, 913 }, 914 [MLX5_EXPANSION_IPV4_TCP] = { 915 .type = RTE_FLOW_ITEM_TYPE_TCP, 916 .rss_types = RTE_ETH_RSS_NONFRAG_IPV4_TCP, 917 }, 918 [MLX5_EXPANSION_IPV4_ESP] = { 919 .type = RTE_FLOW_ITEM_TYPE_ESP, 920 .rss_types = RTE_ETH_RSS_ESP, 921 }, 922 [MLX5_EXPANSION_IPV4_ICMP] = { 923 .type = RTE_FLOW_ITEM_TYPE_ICMP, 924 }, 925 [MLX5_EXPANSION_IPV6] = { 926 .next = MLX5_FLOW_EXPAND_RSS_NEXT(MLX5_EXPANSION_IPV6_UDP, 927 MLX5_EXPANSION_IPV6_TCP, 928 MLX5_EXPANSION_IPV6_ESP, 929 MLX5_EXPANSION_IPV6_ICMP6, 930 MLX5_EXPANSION_IPV6_FRAG_EXT), 931 .type = RTE_FLOW_ITEM_TYPE_IPV6, 932 .rss_types = RTE_ETH_RSS_IPV6 | RTE_ETH_RSS_FRAG_IPV6 | 933 RTE_ETH_RSS_NONFRAG_IPV6_OTHER, 934 }, 935 [MLX5_EXPANSION_IPV6_UDP] = { 936 .type = RTE_FLOW_ITEM_TYPE_UDP, 937 .rss_types = RTE_ETH_RSS_NONFRAG_IPV6_UDP, 938 }, 939 [MLX5_EXPANSION_IPV6_TCP] = { 940 .type = RTE_FLOW_ITEM_TYPE_TCP, 941 .rss_types = RTE_ETH_RSS_NONFRAG_IPV6_TCP, 942 }, 943 [MLX5_EXPANSION_IPV6_ESP] = { 944 .type = RTE_FLOW_ITEM_TYPE_ESP, 945 .rss_types = RTE_ETH_RSS_ESP, 946 }, 947 [MLX5_EXPANSION_IPV6_FRAG_EXT] = { 948 .type = RTE_FLOW_ITEM_TYPE_IPV6_FRAG_EXT, 949 }, 950 [MLX5_EXPANSION_IPV6_ICMP6] = { 951 .type = RTE_FLOW_ITEM_TYPE_ICMP6, 952 }, 953 [MLX5_EXPANSION_GTP] = { 954 .next = MLX5_FLOW_EXPAND_RSS_NEXT(MLX5_EXPANSION_IPV4, 955 MLX5_EXPANSION_IPV6), 956 .type = RTE_FLOW_ITEM_TYPE_GTP, 957 }, 958 [MLX5_EXPANSION_GENEVE] = { 959 .next = MLX5_FLOW_EXPAND_RSS_NEXT(MLX5_EXPANSION_ETH, 960 MLX5_EXPANSION_IPV4, 961 MLX5_EXPANSION_IPV6), 962 .type = RTE_FLOW_ITEM_TYPE_GENEVE, 963 }, 964 }; 965 966 static struct rte_flow_action_handle * 967 mlx5_action_handle_create(struct rte_eth_dev *dev, 968 const struct rte_flow_indir_action_conf *conf, 969 const struct rte_flow_action *action, 970 struct rte_flow_error *error); 971 static int mlx5_action_handle_destroy 972 (struct rte_eth_dev *dev, 973 struct rte_flow_action_handle *handle, 974 struct rte_flow_error *error); 975 static int mlx5_action_handle_update 976 (struct rte_eth_dev *dev, 977 struct rte_flow_action_handle *handle, 978 const void *update, 979 struct rte_flow_error *error); 980 static int mlx5_action_handle_query 981 (struct rte_eth_dev *dev, 982 const struct rte_flow_action_handle *handle, 983 void *data, 984 struct rte_flow_error *error); 985 static int 986 mlx5_flow_tunnel_decap_set(struct rte_eth_dev *dev, 987 struct rte_flow_tunnel *app_tunnel, 988 struct rte_flow_action **actions, 989 uint32_t *num_of_actions, 990 struct rte_flow_error *error); 991 static int 992 mlx5_flow_tunnel_match(struct rte_eth_dev *dev, 993 struct rte_flow_tunnel *app_tunnel, 994 struct rte_flow_item **items, 995 uint32_t *num_of_items, 996 struct rte_flow_error *error); 997 static int 998 mlx5_flow_tunnel_item_release(struct rte_eth_dev *dev, 999 struct rte_flow_item *pmd_items, 1000 uint32_t num_items, struct rte_flow_error *err); 1001 static int 1002 mlx5_flow_tunnel_action_release(struct rte_eth_dev *dev, 1003 struct rte_flow_action *pmd_actions, 1004 uint32_t num_actions, 1005 struct rte_flow_error *err); 1006 static int 1007 mlx5_flow_tunnel_get_restore_info(struct rte_eth_dev *dev, 1008 struct rte_mbuf *m, 1009 struct rte_flow_restore_info *info, 1010 struct rte_flow_error *err); 1011 static struct rte_flow_item_flex_handle * 1012 mlx5_flow_flex_item_create(struct rte_eth_dev *dev, 1013 const struct rte_flow_item_flex_conf *conf, 1014 struct rte_flow_error *error); 1015 static int 1016 mlx5_flow_flex_item_release(struct rte_eth_dev *dev, 1017 const struct rte_flow_item_flex_handle *handle, 1018 struct rte_flow_error *error); 1019 static int 1020 mlx5_flow_info_get(struct rte_eth_dev *dev, 1021 struct rte_flow_port_info *port_info, 1022 struct rte_flow_queue_info *queue_info, 1023 struct rte_flow_error *error); 1024 static int 1025 mlx5_flow_port_configure(struct rte_eth_dev *dev, 1026 const struct rte_flow_port_attr *port_attr, 1027 uint16_t nb_queue, 1028 const struct rte_flow_queue_attr *queue_attr[], 1029 struct rte_flow_error *err); 1030 1031 static struct rte_flow_pattern_template * 1032 mlx5_flow_pattern_template_create(struct rte_eth_dev *dev, 1033 const struct rte_flow_pattern_template_attr *attr, 1034 const struct rte_flow_item items[], 1035 struct rte_flow_error *error); 1036 1037 static int 1038 mlx5_flow_pattern_template_destroy(struct rte_eth_dev *dev, 1039 struct rte_flow_pattern_template *template, 1040 struct rte_flow_error *error); 1041 static struct rte_flow_actions_template * 1042 mlx5_flow_actions_template_create(struct rte_eth_dev *dev, 1043 const struct rte_flow_actions_template_attr *attr, 1044 const struct rte_flow_action actions[], 1045 const struct rte_flow_action masks[], 1046 struct rte_flow_error *error); 1047 static int 1048 mlx5_flow_actions_template_destroy(struct rte_eth_dev *dev, 1049 struct rte_flow_actions_template *template, 1050 struct rte_flow_error *error); 1051 1052 static struct rte_flow_template_table * 1053 mlx5_flow_table_create(struct rte_eth_dev *dev, 1054 const struct rte_flow_template_table_attr *attr, 1055 struct rte_flow_pattern_template *item_templates[], 1056 uint8_t nb_item_templates, 1057 struct rte_flow_actions_template *action_templates[], 1058 uint8_t nb_action_templates, 1059 struct rte_flow_error *error); 1060 static int 1061 mlx5_flow_table_destroy(struct rte_eth_dev *dev, 1062 struct rte_flow_template_table *table, 1063 struct rte_flow_error *error); 1064 static int 1065 mlx5_flow_group_set_miss_actions(struct rte_eth_dev *dev, 1066 uint32_t group_id, 1067 const struct rte_flow_group_attr *attr, 1068 const struct rte_flow_action actions[], 1069 struct rte_flow_error *error); 1070 static struct rte_flow * 1071 mlx5_flow_async_flow_create(struct rte_eth_dev *dev, 1072 uint32_t queue, 1073 const struct rte_flow_op_attr *attr, 1074 struct rte_flow_template_table *table, 1075 const struct rte_flow_item items[], 1076 uint8_t pattern_template_index, 1077 const struct rte_flow_action actions[], 1078 uint8_t action_template_index, 1079 void *user_data, 1080 struct rte_flow_error *error); 1081 static struct rte_flow * 1082 mlx5_flow_async_flow_create_by_index(struct rte_eth_dev *dev, 1083 uint32_t queue, 1084 const struct rte_flow_op_attr *attr, 1085 struct rte_flow_template_table *table, 1086 uint32_t rule_index, 1087 const struct rte_flow_action actions[], 1088 uint8_t action_template_index, 1089 void *user_data, 1090 struct rte_flow_error *error); 1091 static int 1092 mlx5_flow_async_flow_update(struct rte_eth_dev *dev, 1093 uint32_t queue, 1094 const struct rte_flow_op_attr *attr, 1095 struct rte_flow *flow, 1096 const struct rte_flow_action actions[], 1097 uint8_t action_template_index, 1098 void *user_data, 1099 struct rte_flow_error *error); 1100 static int 1101 mlx5_flow_async_flow_destroy(struct rte_eth_dev *dev, 1102 uint32_t queue, 1103 const struct rte_flow_op_attr *attr, 1104 struct rte_flow *flow, 1105 void *user_data, 1106 struct rte_flow_error *error); 1107 static int 1108 mlx5_flow_pull(struct rte_eth_dev *dev, 1109 uint32_t queue, 1110 struct rte_flow_op_result res[], 1111 uint16_t n_res, 1112 struct rte_flow_error *error); 1113 static int 1114 mlx5_flow_push(struct rte_eth_dev *dev, 1115 uint32_t queue, 1116 struct rte_flow_error *error); 1117 1118 static struct rte_flow_action_handle * 1119 mlx5_flow_async_action_handle_create(struct rte_eth_dev *dev, uint32_t queue, 1120 const struct rte_flow_op_attr *attr, 1121 const struct rte_flow_indir_action_conf *conf, 1122 const struct rte_flow_action *action, 1123 void *user_data, 1124 struct rte_flow_error *error); 1125 1126 static int 1127 mlx5_flow_async_action_handle_update(struct rte_eth_dev *dev, uint32_t queue, 1128 const struct rte_flow_op_attr *attr, 1129 struct rte_flow_action_handle *handle, 1130 const void *update, 1131 void *user_data, 1132 struct rte_flow_error *error); 1133 1134 static int 1135 mlx5_flow_async_action_handle_destroy(struct rte_eth_dev *dev, uint32_t queue, 1136 const struct rte_flow_op_attr *attr, 1137 struct rte_flow_action_handle *handle, 1138 void *user_data, 1139 struct rte_flow_error *error); 1140 1141 static int 1142 mlx5_flow_async_action_handle_query(struct rte_eth_dev *dev, uint32_t queue, 1143 const struct rte_flow_op_attr *attr, 1144 const struct rte_flow_action_handle *handle, 1145 void *data, 1146 void *user_data, 1147 struct rte_flow_error *error); 1148 static int 1149 mlx5_action_handle_query_update(struct rte_eth_dev *dev, 1150 struct rte_flow_action_handle *handle, 1151 const void *update, void *query, 1152 enum rte_flow_query_update_mode qu_mode, 1153 struct rte_flow_error *error); 1154 static int 1155 mlx5_flow_async_action_handle_query_update 1156 (struct rte_eth_dev *dev, uint32_t queue_id, 1157 const struct rte_flow_op_attr *op_attr, 1158 struct rte_flow_action_handle *action_handle, 1159 const void *update, void *query, 1160 enum rte_flow_query_update_mode qu_mode, 1161 void *user_data, struct rte_flow_error *error); 1162 1163 static struct rte_flow_action_list_handle * 1164 mlx5_action_list_handle_create(struct rte_eth_dev *dev, 1165 const struct rte_flow_indir_action_conf *conf, 1166 const struct rte_flow_action *actions, 1167 struct rte_flow_error *error); 1168 1169 static int 1170 mlx5_action_list_handle_destroy(struct rte_eth_dev *dev, 1171 struct rte_flow_action_list_handle *handle, 1172 struct rte_flow_error *error); 1173 1174 static struct rte_flow_action_list_handle * 1175 mlx5_flow_async_action_list_handle_create(struct rte_eth_dev *dev, uint32_t queue_id, 1176 const struct rte_flow_op_attr *attr, 1177 const struct 1178 rte_flow_indir_action_conf *conf, 1179 const struct rte_flow_action *actions, 1180 void *user_data, 1181 struct rte_flow_error *error); 1182 static int 1183 mlx5_flow_async_action_list_handle_destroy 1184 (struct rte_eth_dev *dev, uint32_t queue_id, 1185 const struct rte_flow_op_attr *op_attr, 1186 struct rte_flow_action_list_handle *action_handle, 1187 void *user_data, struct rte_flow_error *error); 1188 static int 1189 mlx5_flow_action_list_handle_query_update(struct rte_eth_dev *dev, 1190 const 1191 struct rte_flow_action_list_handle *handle, 1192 const void **update, void **query, 1193 enum rte_flow_query_update_mode mode, 1194 struct rte_flow_error *error); 1195 static int 1196 mlx5_flow_async_action_list_handle_query_update(struct rte_eth_dev *dev, 1197 uint32_t queue_id, 1198 const struct rte_flow_op_attr *attr, 1199 const struct 1200 rte_flow_action_list_handle *handle, 1201 const void **update, 1202 void **query, 1203 enum rte_flow_query_update_mode mode, 1204 void *user_data, 1205 struct rte_flow_error *error); 1206 static const struct rte_flow_ops mlx5_flow_ops = { 1207 .validate = mlx5_flow_validate, 1208 .create = mlx5_flow_create, 1209 .destroy = mlx5_flow_destroy, 1210 .flush = mlx5_flow_flush, 1211 .isolate = mlx5_flow_isolate, 1212 .query = mlx5_flow_query, 1213 .dev_dump = mlx5_flow_dev_dump, 1214 .get_q_aged_flows = mlx5_flow_get_q_aged_flows, 1215 .get_aged_flows = mlx5_flow_get_aged_flows, 1216 .action_handle_create = mlx5_action_handle_create, 1217 .action_handle_destroy = mlx5_action_handle_destroy, 1218 .action_handle_update = mlx5_action_handle_update, 1219 .action_handle_query = mlx5_action_handle_query, 1220 .action_handle_query_update = mlx5_action_handle_query_update, 1221 .action_list_handle_create = mlx5_action_list_handle_create, 1222 .action_list_handle_destroy = mlx5_action_list_handle_destroy, 1223 .tunnel_decap_set = mlx5_flow_tunnel_decap_set, 1224 .tunnel_match = mlx5_flow_tunnel_match, 1225 .tunnel_action_decap_release = mlx5_flow_tunnel_action_release, 1226 .tunnel_item_release = mlx5_flow_tunnel_item_release, 1227 .get_restore_info = mlx5_flow_tunnel_get_restore_info, 1228 .flex_item_create = mlx5_flow_flex_item_create, 1229 .flex_item_release = mlx5_flow_flex_item_release, 1230 .info_get = mlx5_flow_info_get, 1231 .pick_transfer_proxy = mlx5_flow_pick_transfer_proxy, 1232 .configure = mlx5_flow_port_configure, 1233 .pattern_template_create = mlx5_flow_pattern_template_create, 1234 .pattern_template_destroy = mlx5_flow_pattern_template_destroy, 1235 .actions_template_create = mlx5_flow_actions_template_create, 1236 .actions_template_destroy = mlx5_flow_actions_template_destroy, 1237 .template_table_create = mlx5_flow_table_create, 1238 .template_table_destroy = mlx5_flow_table_destroy, 1239 .group_set_miss_actions = mlx5_flow_group_set_miss_actions, 1240 .async_create = mlx5_flow_async_flow_create, 1241 .async_create_by_index = mlx5_flow_async_flow_create_by_index, 1242 .async_destroy = mlx5_flow_async_flow_destroy, 1243 .pull = mlx5_flow_pull, 1244 .push = mlx5_flow_push, 1245 .async_action_handle_create = mlx5_flow_async_action_handle_create, 1246 .async_action_handle_update = mlx5_flow_async_action_handle_update, 1247 .async_action_handle_query_update = 1248 mlx5_flow_async_action_handle_query_update, 1249 .async_action_handle_query = mlx5_flow_async_action_handle_query, 1250 .async_action_handle_destroy = mlx5_flow_async_action_handle_destroy, 1251 .async_actions_update = mlx5_flow_async_flow_update, 1252 .async_action_list_handle_create = 1253 mlx5_flow_async_action_list_handle_create, 1254 .async_action_list_handle_destroy = 1255 mlx5_flow_async_action_list_handle_destroy, 1256 .action_list_handle_query_update = 1257 mlx5_flow_action_list_handle_query_update, 1258 .async_action_list_handle_query_update = 1259 mlx5_flow_async_action_list_handle_query_update, 1260 }; 1261 1262 /* Tunnel information. */ 1263 struct mlx5_flow_tunnel_info { 1264 uint64_t tunnel; /**< Tunnel bit (see MLX5_FLOW_*). */ 1265 uint32_t ptype; /**< Tunnel Ptype (see RTE_PTYPE_*). */ 1266 }; 1267 1268 static struct mlx5_flow_tunnel_info tunnels_info[] = { 1269 { 1270 .tunnel = MLX5_FLOW_LAYER_VXLAN, 1271 .ptype = RTE_PTYPE_TUNNEL_VXLAN | RTE_PTYPE_L4_UDP, 1272 }, 1273 { 1274 .tunnel = MLX5_FLOW_LAYER_GENEVE, 1275 .ptype = RTE_PTYPE_TUNNEL_GENEVE | RTE_PTYPE_L4_UDP, 1276 }, 1277 { 1278 .tunnel = MLX5_FLOW_LAYER_VXLAN_GPE, 1279 .ptype = RTE_PTYPE_TUNNEL_VXLAN_GPE | RTE_PTYPE_L4_UDP, 1280 }, 1281 { 1282 .tunnel = MLX5_FLOW_LAYER_GRE, 1283 .ptype = RTE_PTYPE_TUNNEL_GRE, 1284 }, 1285 { 1286 .tunnel = MLX5_FLOW_LAYER_MPLS | MLX5_FLOW_LAYER_OUTER_L4_UDP, 1287 .ptype = RTE_PTYPE_TUNNEL_MPLS_IN_UDP | RTE_PTYPE_L4_UDP, 1288 }, 1289 { 1290 .tunnel = MLX5_FLOW_LAYER_MPLS, 1291 .ptype = RTE_PTYPE_TUNNEL_MPLS_IN_GRE, 1292 }, 1293 { 1294 .tunnel = MLX5_FLOW_LAYER_NVGRE, 1295 .ptype = RTE_PTYPE_TUNNEL_NVGRE, 1296 }, 1297 { 1298 .tunnel = MLX5_FLOW_LAYER_IPIP, 1299 .ptype = RTE_PTYPE_TUNNEL_IP, 1300 }, 1301 { 1302 .tunnel = MLX5_FLOW_LAYER_IPV6_ENCAP, 1303 .ptype = RTE_PTYPE_TUNNEL_IP, 1304 }, 1305 { 1306 .tunnel = MLX5_FLOW_LAYER_GTP, 1307 .ptype = RTE_PTYPE_TUNNEL_GTPU, 1308 }, 1309 }; 1310 1311 1312 1313 /** 1314 * Translate tag ID to register. 1315 * 1316 * @param[in] dev 1317 * Pointer to the Ethernet device structure. 1318 * @param[in] feature 1319 * The feature that request the register. 1320 * @param[in] id 1321 * The request register ID. 1322 * @param[out] error 1323 * Error description in case of any. 1324 * 1325 * @return 1326 * The request register on success, a negative errno 1327 * value otherwise and rte_errno is set. 1328 */ 1329 int 1330 mlx5_flow_get_reg_id(struct rte_eth_dev *dev, 1331 enum mlx5_feature_name feature, 1332 uint32_t id, 1333 struct rte_flow_error *error) 1334 { 1335 struct mlx5_priv *priv = dev->data->dev_private; 1336 struct mlx5_sh_config *config = &priv->sh->config; 1337 enum modify_reg start_reg; 1338 bool skip_mtr_reg = false; 1339 1340 switch (feature) { 1341 case MLX5_HAIRPIN_RX: 1342 return REG_B; 1343 case MLX5_HAIRPIN_TX: 1344 return REG_A; 1345 case MLX5_METADATA_RX: 1346 switch (config->dv_xmeta_en) { 1347 case MLX5_XMETA_MODE_LEGACY: 1348 return REG_B; 1349 case MLX5_XMETA_MODE_META16: 1350 return REG_C_0; 1351 case MLX5_XMETA_MODE_META32: 1352 return REG_C_1; 1353 case MLX5_XMETA_MODE_META32_HWS: 1354 return REG_C_1; 1355 } 1356 break; 1357 case MLX5_METADATA_TX: 1358 if (config->dv_flow_en == 2 && config->dv_xmeta_en == MLX5_XMETA_MODE_META32_HWS) { 1359 return REG_C_1; 1360 } else { 1361 return REG_A; 1362 } 1363 case MLX5_METADATA_FDB: 1364 switch (config->dv_xmeta_en) { 1365 case MLX5_XMETA_MODE_LEGACY: 1366 return REG_NON; 1367 case MLX5_XMETA_MODE_META16: 1368 return REG_C_0; 1369 case MLX5_XMETA_MODE_META32: 1370 return REG_C_1; 1371 case MLX5_XMETA_MODE_META32_HWS: 1372 return REG_C_1; 1373 } 1374 break; 1375 case MLX5_FLOW_MARK: 1376 switch (config->dv_xmeta_en) { 1377 case MLX5_XMETA_MODE_LEGACY: 1378 case MLX5_XMETA_MODE_META32_HWS: 1379 return REG_NON; 1380 case MLX5_XMETA_MODE_META16: 1381 return REG_C_1; 1382 case MLX5_XMETA_MODE_META32: 1383 return REG_C_0; 1384 } 1385 break; 1386 case MLX5_MTR_ID: 1387 /* 1388 * If meter color and meter id share one register, flow match 1389 * should use the meter color register for match. 1390 */ 1391 if (priv->mtr_reg_share) 1392 return priv->mtr_color_reg; 1393 else 1394 return priv->mtr_color_reg != REG_C_2 ? REG_C_2 : 1395 REG_C_3; 1396 case MLX5_MTR_COLOR: 1397 case MLX5_ASO_FLOW_HIT: 1398 case MLX5_ASO_CONNTRACK: 1399 case MLX5_SAMPLE_ID: 1400 /* All features use the same REG_C. */ 1401 MLX5_ASSERT(priv->mtr_color_reg != REG_NON); 1402 return priv->mtr_color_reg; 1403 case MLX5_COPY_MARK: 1404 /* 1405 * Metadata COPY_MARK register using is in meter suffix sub 1406 * flow while with meter. It's safe to share the same register. 1407 */ 1408 return priv->mtr_color_reg != REG_C_2 ? REG_C_2 : REG_C_3; 1409 case MLX5_APP_TAG: 1410 /* 1411 * If meter is enable, it will engage the register for color 1412 * match and flow match. If meter color match is not using the 1413 * REG_C_2, need to skip the REG_C_x be used by meter color 1414 * match. 1415 * If meter is disable, free to use all available registers. 1416 */ 1417 start_reg = priv->mtr_color_reg != REG_C_2 ? REG_C_2 : 1418 (priv->mtr_reg_share ? REG_C_3 : REG_C_4); 1419 skip_mtr_reg = !!(priv->mtr_en && start_reg == REG_C_2); 1420 if (id > (uint32_t)(REG_C_7 - start_reg)) 1421 return rte_flow_error_set(error, EINVAL, 1422 RTE_FLOW_ERROR_TYPE_ITEM, 1423 NULL, "invalid tag id"); 1424 if (priv->sh->flow_mreg_c[id + start_reg - REG_C_0] == REG_NON) 1425 return rte_flow_error_set(error, ENOTSUP, 1426 RTE_FLOW_ERROR_TYPE_ITEM, 1427 NULL, "unsupported tag id"); 1428 /* 1429 * This case means meter is using the REG_C_x great than 2. 1430 * Take care not to conflict with meter color REG_C_x. 1431 * If the available index REG_C_y >= REG_C_x, skip the 1432 * color register. 1433 */ 1434 if (skip_mtr_reg && priv->sh->flow_mreg_c 1435 [id + start_reg - REG_C_0] >= priv->mtr_color_reg) { 1436 if (id >= (uint32_t)(REG_C_7 - start_reg)) 1437 return rte_flow_error_set(error, EINVAL, 1438 RTE_FLOW_ERROR_TYPE_ITEM, 1439 NULL, "invalid tag id"); 1440 if (priv->sh->flow_mreg_c 1441 [id + 1 + start_reg - REG_C_0] != REG_NON) 1442 return priv->sh->flow_mreg_c 1443 [id + 1 + start_reg - REG_C_0]; 1444 return rte_flow_error_set(error, ENOTSUP, 1445 RTE_FLOW_ERROR_TYPE_ITEM, 1446 NULL, "unsupported tag id"); 1447 } 1448 return priv->sh->flow_mreg_c[id + start_reg - REG_C_0]; 1449 } 1450 MLX5_ASSERT(false); 1451 return rte_flow_error_set(error, EINVAL, 1452 RTE_FLOW_ERROR_TYPE_UNSPECIFIED, 1453 NULL, "invalid feature name"); 1454 } 1455 1456 /** 1457 * Check extensive flow metadata register support. 1458 * 1459 * @param dev 1460 * Pointer to rte_eth_dev structure. 1461 * 1462 * @return 1463 * True if device supports extensive flow metadata register, otherwise false. 1464 */ 1465 bool 1466 mlx5_flow_ext_mreg_supported(struct rte_eth_dev *dev) 1467 { 1468 struct mlx5_priv *priv = dev->data->dev_private; 1469 1470 /* 1471 * Having available reg_c can be regarded inclusively as supporting 1472 * extensive flow metadata register, which could mean, 1473 * - metadata register copy action by modify header. 1474 * - 16 modify header actions is supported. 1475 * - reg_c's are preserved across different domain (FDB and NIC) on 1476 * packet loopback by flow lookup miss. 1477 */ 1478 return priv->sh->flow_mreg_c[2] != REG_NON; 1479 } 1480 1481 /** 1482 * Get the lowest priority. 1483 * 1484 * @param[in] dev 1485 * Pointer to the Ethernet device structure. 1486 * @param[in] attributes 1487 * Pointer to device flow rule attributes. 1488 * 1489 * @return 1490 * The value of lowest priority of flow. 1491 */ 1492 uint32_t 1493 mlx5_get_lowest_priority(struct rte_eth_dev *dev, 1494 const struct rte_flow_attr *attr) 1495 { 1496 struct mlx5_priv *priv = dev->data->dev_private; 1497 1498 if (!attr->group && !(attr->transfer && priv->fdb_def_rule)) 1499 return priv->sh->flow_max_priority - 2; 1500 return MLX5_NON_ROOT_FLOW_MAX_PRIO - 1; 1501 } 1502 1503 /** 1504 * Calculate matcher priority of the flow. 1505 * 1506 * @param[in] dev 1507 * Pointer to the Ethernet device structure. 1508 * @param[in] attr 1509 * Pointer to device flow rule attributes. 1510 * @param[in] subpriority 1511 * The priority based on the items. 1512 * @param[in] external 1513 * Flow is user flow. 1514 * @return 1515 * The matcher priority of the flow. 1516 */ 1517 uint16_t 1518 mlx5_get_matcher_priority(struct rte_eth_dev *dev, 1519 const struct rte_flow_attr *attr, 1520 uint32_t subpriority, bool external) 1521 { 1522 uint16_t priority = (uint16_t)attr->priority; 1523 struct mlx5_priv *priv = dev->data->dev_private; 1524 1525 /* NIC root rules */ 1526 if (!attr->group && !attr->transfer) { 1527 if (attr->priority == MLX5_FLOW_LOWEST_PRIO_INDICATOR) 1528 priority = priv->sh->flow_max_priority - 1; 1529 return mlx5_os_flow_adjust_priority(dev, priority, subpriority); 1530 /* FDB root rules */ 1531 } else if (attr->transfer && (!external || !priv->fdb_def_rule) && 1532 attr->group == 0 && 1533 attr->priority == MLX5_FLOW_LOWEST_PRIO_INDICATOR) { 1534 return (priv->sh->flow_max_priority - 1) * 3; 1535 } 1536 if (attr->priority == MLX5_FLOW_LOWEST_PRIO_INDICATOR) 1537 priority = MLX5_NON_ROOT_FLOW_MAX_PRIO; 1538 return priority * 3 + subpriority; 1539 } 1540 1541 /** 1542 * Verify the @p item specifications (spec, last, mask) are compatible with the 1543 * NIC capabilities. 1544 * 1545 * @param[in] item 1546 * Item specification. 1547 * @param[in] mask 1548 * @p item->mask or flow default bit-masks. 1549 * @param[in] nic_mask 1550 * Bit-masks covering supported fields by the NIC to compare with user mask. 1551 * @param[in] size 1552 * Bit-masks size in bytes. 1553 * @param[in] range_accepted 1554 * True if range of values is accepted for specific fields, false otherwise. 1555 * @param[out] error 1556 * Pointer to error structure. 1557 * 1558 * @return 1559 * 0 on success, a negative errno value otherwise and rte_errno is set. 1560 */ 1561 int 1562 mlx5_flow_item_acceptable(const struct rte_flow_item *item, 1563 const uint8_t *mask, 1564 const uint8_t *nic_mask, 1565 unsigned int size, 1566 bool range_accepted, 1567 struct rte_flow_error *error) 1568 { 1569 unsigned int i; 1570 1571 MLX5_ASSERT(nic_mask); 1572 for (i = 0; i < size; ++i) 1573 if ((nic_mask[i] | mask[i]) != nic_mask[i]) 1574 return rte_flow_error_set(error, ENOTSUP, 1575 RTE_FLOW_ERROR_TYPE_ITEM, 1576 item, 1577 "mask enables non supported" 1578 " bits"); 1579 if (!item->spec && (item->mask || item->last)) 1580 return rte_flow_error_set(error, EINVAL, 1581 RTE_FLOW_ERROR_TYPE_ITEM, item, 1582 "mask/last without a spec is not" 1583 " supported"); 1584 if (item->spec && item->last && !range_accepted) { 1585 uint8_t spec[size]; 1586 uint8_t last[size]; 1587 unsigned int i; 1588 int ret; 1589 1590 for (i = 0; i < size; ++i) { 1591 spec[i] = ((const uint8_t *)item->spec)[i] & mask[i]; 1592 last[i] = ((const uint8_t *)item->last)[i] & mask[i]; 1593 } 1594 ret = memcmp(spec, last, size); 1595 if (ret != 0) 1596 return rte_flow_error_set(error, EINVAL, 1597 RTE_FLOW_ERROR_TYPE_ITEM, 1598 item, 1599 "range is not valid"); 1600 } 1601 return 0; 1602 } 1603 1604 /** 1605 * Adjust the hash fields according to the @p flow information. 1606 * 1607 * @param[in] dev_flow. 1608 * Pointer to the mlx5_flow. 1609 * @param[in] tunnel 1610 * 1 when the hash field is for a tunnel item. 1611 * @param[in] layer_types 1612 * RTE_ETH_RSS_* types. 1613 * @param[in] hash_fields 1614 * Item hash fields. 1615 * 1616 * @return 1617 * The hash fields that should be used. 1618 */ 1619 uint64_t 1620 mlx5_flow_hashfields_adjust(struct mlx5_flow_rss_desc *rss_desc, 1621 int tunnel __rte_unused, uint64_t layer_types, 1622 uint64_t hash_fields) 1623 { 1624 #ifdef HAVE_IBV_DEVICE_TUNNEL_SUPPORT 1625 int rss_request_inner = rss_desc->level >= 2; 1626 1627 /* Check RSS hash level for tunnel. */ 1628 if (tunnel && rss_request_inner) 1629 hash_fields |= IBV_RX_HASH_INNER; 1630 else if (tunnel || rss_request_inner) 1631 return 0; 1632 #endif 1633 /* Check if requested layer matches RSS hash fields. */ 1634 if (!(rss_desc->types & layer_types)) 1635 return 0; 1636 return hash_fields; 1637 } 1638 1639 /** 1640 * Lookup and set the ptype in the data Rx part. A single Ptype can be used, 1641 * if several tunnel rules are used on this queue, the tunnel ptype will be 1642 * cleared. 1643 * 1644 * @param rxq_ctrl 1645 * Rx queue to update. 1646 */ 1647 static void 1648 flow_rxq_tunnel_ptype_update(struct mlx5_rxq_ctrl *rxq_ctrl) 1649 { 1650 unsigned int i; 1651 uint32_t tunnel_ptype = 0; 1652 1653 /* Look up for the ptype to use. */ 1654 for (i = 0; i != MLX5_FLOW_TUNNEL; ++i) { 1655 if (!rxq_ctrl->flow_tunnels_n[i]) 1656 continue; 1657 if (!tunnel_ptype) { 1658 tunnel_ptype = tunnels_info[i].ptype; 1659 } else { 1660 tunnel_ptype = 0; 1661 break; 1662 } 1663 } 1664 rxq_ctrl->rxq.tunnel = tunnel_ptype; 1665 } 1666 1667 /** 1668 * Set the Rx queue flags (Mark/Flag and Tunnel Ptypes) according to the device 1669 * flow. 1670 * 1671 * @param[in] dev 1672 * Pointer to the Ethernet device structure. 1673 * @param[in] dev_handle 1674 * Pointer to device flow handle structure. 1675 */ 1676 void 1677 flow_drv_rxq_flags_set(struct rte_eth_dev *dev, 1678 struct mlx5_flow_handle *dev_handle) 1679 { 1680 struct mlx5_priv *priv = dev->data->dev_private; 1681 const int tunnel = !!(dev_handle->layers & MLX5_FLOW_LAYER_TUNNEL); 1682 struct mlx5_ind_table_obj *ind_tbl = NULL; 1683 unsigned int i; 1684 1685 if (dev_handle->fate_action == MLX5_FLOW_FATE_QUEUE) { 1686 struct mlx5_hrxq *hrxq; 1687 1688 hrxq = mlx5_ipool_get(priv->sh->ipool[MLX5_IPOOL_HRXQ], 1689 dev_handle->rix_hrxq); 1690 if (hrxq) 1691 ind_tbl = hrxq->ind_table; 1692 } else if (dev_handle->fate_action == MLX5_FLOW_FATE_SHARED_RSS) { 1693 struct mlx5_shared_action_rss *shared_rss; 1694 1695 shared_rss = mlx5_ipool_get 1696 (priv->sh->ipool[MLX5_IPOOL_RSS_SHARED_ACTIONS], 1697 dev_handle->rix_srss); 1698 if (shared_rss) 1699 ind_tbl = shared_rss->ind_tbl; 1700 } 1701 if (!ind_tbl) 1702 return; 1703 for (i = 0; i != ind_tbl->queues_n; ++i) { 1704 int idx = ind_tbl->queues[i]; 1705 struct mlx5_rxq_ctrl *rxq_ctrl; 1706 1707 if (mlx5_is_external_rxq(dev, idx)) 1708 continue; 1709 rxq_ctrl = mlx5_rxq_ctrl_get(dev, idx); 1710 MLX5_ASSERT(rxq_ctrl != NULL); 1711 if (rxq_ctrl == NULL) 1712 continue; 1713 /* 1714 * To support metadata register copy on Tx loopback, 1715 * this must be always enabled (metadata may arive 1716 * from other port - not from local flows only. 1717 */ 1718 if (tunnel) { 1719 unsigned int j; 1720 1721 /* Increase the counter matching the flow. */ 1722 for (j = 0; j != MLX5_FLOW_TUNNEL; ++j) { 1723 if ((tunnels_info[j].tunnel & 1724 dev_handle->layers) == 1725 tunnels_info[j].tunnel) { 1726 rxq_ctrl->flow_tunnels_n[j]++; 1727 break; 1728 } 1729 } 1730 flow_rxq_tunnel_ptype_update(rxq_ctrl); 1731 } 1732 } 1733 } 1734 1735 static void 1736 flow_rxq_mark_flag_set(struct rte_eth_dev *dev) 1737 { 1738 struct mlx5_priv *priv = dev->data->dev_private; 1739 struct mlx5_rxq_ctrl *rxq_ctrl; 1740 uint16_t port_id; 1741 1742 if (priv->sh->shared_mark_enabled) 1743 return; 1744 if (priv->master || priv->representor) { 1745 MLX5_ETH_FOREACH_DEV(port_id, dev->device) { 1746 struct mlx5_priv *opriv = 1747 rte_eth_devices[port_id].data->dev_private; 1748 1749 if (!opriv || 1750 opriv->sh != priv->sh || 1751 opriv->domain_id != priv->domain_id || 1752 opriv->mark_enabled) 1753 continue; 1754 LIST_FOREACH(rxq_ctrl, &opriv->rxqsctrl, next) { 1755 rxq_ctrl->rxq.mark = 1; 1756 } 1757 opriv->mark_enabled = 1; 1758 } 1759 } else { 1760 LIST_FOREACH(rxq_ctrl, &priv->rxqsctrl, next) { 1761 rxq_ctrl->rxq.mark = 1; 1762 } 1763 priv->mark_enabled = 1; 1764 } 1765 priv->sh->shared_mark_enabled = 1; 1766 } 1767 1768 /** 1769 * Set the Rx queue flags (Mark/Flag and Tunnel Ptypes) for a flow 1770 * 1771 * @param[in] dev 1772 * Pointer to the Ethernet device structure. 1773 * @param[in] flow 1774 * Pointer to flow structure. 1775 */ 1776 static void 1777 flow_rxq_flags_set(struct rte_eth_dev *dev, struct rte_flow *flow) 1778 { 1779 struct mlx5_priv *priv = dev->data->dev_private; 1780 uint32_t handle_idx; 1781 struct mlx5_flow_handle *dev_handle; 1782 struct mlx5_flow_workspace *wks = mlx5_flow_get_thread_workspace(); 1783 1784 MLX5_ASSERT(wks); 1785 if (wks->mark) 1786 flow_rxq_mark_flag_set(dev); 1787 SILIST_FOREACH(priv->sh->ipool[MLX5_IPOOL_MLX5_FLOW], flow->dev_handles, 1788 handle_idx, dev_handle, next) 1789 flow_drv_rxq_flags_set(dev, dev_handle); 1790 } 1791 1792 /** 1793 * Clear the Rx queue flags (Mark/Flag and Tunnel Ptype) associated with the 1794 * device flow if no other flow uses it with the same kind of request. 1795 * 1796 * @param dev 1797 * Pointer to Ethernet device. 1798 * @param[in] dev_handle 1799 * Pointer to the device flow handle structure. 1800 */ 1801 static void 1802 flow_drv_rxq_flags_trim(struct rte_eth_dev *dev, 1803 struct mlx5_flow_handle *dev_handle) 1804 { 1805 struct mlx5_priv *priv = dev->data->dev_private; 1806 const int tunnel = !!(dev_handle->layers & MLX5_FLOW_LAYER_TUNNEL); 1807 struct mlx5_ind_table_obj *ind_tbl = NULL; 1808 unsigned int i; 1809 1810 if (dev_handle->fate_action == MLX5_FLOW_FATE_QUEUE) { 1811 struct mlx5_hrxq *hrxq; 1812 1813 hrxq = mlx5_ipool_get(priv->sh->ipool[MLX5_IPOOL_HRXQ], 1814 dev_handle->rix_hrxq); 1815 if (hrxq) 1816 ind_tbl = hrxq->ind_table; 1817 } else if (dev_handle->fate_action == MLX5_FLOW_FATE_SHARED_RSS) { 1818 struct mlx5_shared_action_rss *shared_rss; 1819 1820 shared_rss = mlx5_ipool_get 1821 (priv->sh->ipool[MLX5_IPOOL_RSS_SHARED_ACTIONS], 1822 dev_handle->rix_srss); 1823 if (shared_rss) 1824 ind_tbl = shared_rss->ind_tbl; 1825 } 1826 if (!ind_tbl) 1827 return; 1828 MLX5_ASSERT(dev->data->dev_started); 1829 for (i = 0; i != ind_tbl->queues_n; ++i) { 1830 int idx = ind_tbl->queues[i]; 1831 struct mlx5_rxq_ctrl *rxq_ctrl; 1832 1833 if (mlx5_is_external_rxq(dev, idx)) 1834 continue; 1835 rxq_ctrl = mlx5_rxq_ctrl_get(dev, idx); 1836 MLX5_ASSERT(rxq_ctrl != NULL); 1837 if (rxq_ctrl == NULL) 1838 continue; 1839 if (tunnel) { 1840 unsigned int j; 1841 1842 /* Decrease the counter matching the flow. */ 1843 for (j = 0; j != MLX5_FLOW_TUNNEL; ++j) { 1844 if ((tunnels_info[j].tunnel & 1845 dev_handle->layers) == 1846 tunnels_info[j].tunnel) { 1847 rxq_ctrl->flow_tunnels_n[j]--; 1848 break; 1849 } 1850 } 1851 flow_rxq_tunnel_ptype_update(rxq_ctrl); 1852 } 1853 } 1854 } 1855 1856 /** 1857 * Clear the Rx queue flags (Mark/Flag and Tunnel Ptype) associated with the 1858 * @p flow if no other flow uses it with the same kind of request. 1859 * 1860 * @param dev 1861 * Pointer to Ethernet device. 1862 * @param[in] flow 1863 * Pointer to the flow. 1864 */ 1865 static void 1866 flow_rxq_flags_trim(struct rte_eth_dev *dev, struct rte_flow *flow) 1867 { 1868 struct mlx5_priv *priv = dev->data->dev_private; 1869 uint32_t handle_idx; 1870 struct mlx5_flow_handle *dev_handle; 1871 1872 SILIST_FOREACH(priv->sh->ipool[MLX5_IPOOL_MLX5_FLOW], flow->dev_handles, 1873 handle_idx, dev_handle, next) 1874 flow_drv_rxq_flags_trim(dev, dev_handle); 1875 } 1876 1877 /** 1878 * Clear the Mark/Flag and Tunnel ptype information in all Rx queues. 1879 * 1880 * @param dev 1881 * Pointer to Ethernet device. 1882 */ 1883 static void 1884 flow_rxq_flags_clear(struct rte_eth_dev *dev) 1885 { 1886 struct mlx5_priv *priv = dev->data->dev_private; 1887 unsigned int i; 1888 1889 for (i = 0; i != priv->rxqs_n; ++i) { 1890 struct mlx5_rxq_priv *rxq = mlx5_rxq_get(dev, i); 1891 unsigned int j; 1892 1893 if (rxq == NULL || rxq->ctrl == NULL) 1894 continue; 1895 rxq->ctrl->rxq.mark = 0; 1896 for (j = 0; j != MLX5_FLOW_TUNNEL; ++j) 1897 rxq->ctrl->flow_tunnels_n[j] = 0; 1898 rxq->ctrl->rxq.tunnel = 0; 1899 } 1900 priv->mark_enabled = 0; 1901 priv->sh->shared_mark_enabled = 0; 1902 } 1903 1904 static uint64_t mlx5_restore_info_dynflag; 1905 1906 int 1907 mlx5_flow_rx_metadata_negotiate(struct rte_eth_dev *dev, uint64_t *features) 1908 { 1909 struct mlx5_priv *priv = dev->data->dev_private; 1910 uint64_t supported = 0; 1911 1912 if (!is_tunnel_offload_active(dev)) { 1913 supported |= RTE_ETH_RX_METADATA_USER_FLAG; 1914 supported |= RTE_ETH_RX_METADATA_USER_MARK; 1915 if ((*features & RTE_ETH_RX_METADATA_TUNNEL_ID) != 0) { 1916 DRV_LOG(DEBUG, 1917 "tunnel offload was not activated, consider setting dv_xmeta_en=%d", 1918 MLX5_XMETA_MODE_MISS_INFO); 1919 } 1920 } else { 1921 supported |= RTE_ETH_RX_METADATA_TUNNEL_ID; 1922 if ((*features & RTE_ETH_RX_METADATA_TUNNEL_ID) != 0 && 1923 mlx5_restore_info_dynflag == 0) 1924 mlx5_restore_info_dynflag = rte_flow_restore_info_dynflag(); 1925 } 1926 1927 if (((*features & supported) & RTE_ETH_RX_METADATA_TUNNEL_ID) != 0) 1928 priv->tunnel_enabled = 1; 1929 else 1930 priv->tunnel_enabled = 0; 1931 1932 *features &= supported; 1933 return 0; 1934 } 1935 1936 /** 1937 * Set the Rx queue dynamic metadata (mask and offset) for a flow 1938 * 1939 * @param[in] dev 1940 * Pointer to the Ethernet device structure. 1941 */ 1942 void 1943 mlx5_flow_rxq_dynf_set(struct rte_eth_dev *dev) 1944 { 1945 struct mlx5_priv *priv = dev->data->dev_private; 1946 uint64_t mark_flag = RTE_MBUF_F_RX_FDIR_ID; 1947 unsigned int i; 1948 1949 if (priv->tunnel_enabled) 1950 mark_flag |= mlx5_restore_info_dynflag; 1951 1952 for (i = 0; i != priv->rxqs_n; ++i) { 1953 struct mlx5_rxq_priv *rxq = mlx5_rxq_get(dev, i); 1954 struct mlx5_rxq_data *data; 1955 1956 if (rxq == NULL || rxq->ctrl == NULL) 1957 continue; 1958 data = &rxq->ctrl->rxq; 1959 if (!rte_flow_dynf_metadata_avail()) { 1960 data->dynf_meta = 0; 1961 data->flow_meta_mask = 0; 1962 data->flow_meta_offset = -1; 1963 data->flow_meta_port_mask = 0; 1964 } else { 1965 data->dynf_meta = 1; 1966 data->flow_meta_mask = rte_flow_dynf_metadata_mask; 1967 data->flow_meta_offset = rte_flow_dynf_metadata_offs; 1968 data->flow_meta_port_mask = priv->sh->dv_meta_mask; 1969 } 1970 data->mark_flag = mark_flag; 1971 } 1972 } 1973 1974 /* 1975 * return a pointer to the desired action in the list of actions. 1976 * 1977 * @param[in] actions 1978 * The list of actions to search the action in. 1979 * @param[in] action 1980 * The action to find. 1981 * 1982 * @return 1983 * Pointer to the action in the list, if found. NULL otherwise. 1984 */ 1985 const struct rte_flow_action * 1986 mlx5_flow_find_action(const struct rte_flow_action *actions, 1987 enum rte_flow_action_type action) 1988 { 1989 if (actions == NULL) 1990 return NULL; 1991 for (; actions->type != RTE_FLOW_ACTION_TYPE_END; actions++) 1992 if (actions->type == action) 1993 return actions; 1994 return NULL; 1995 } 1996 1997 /* 1998 * Validate the flag action. 1999 * 2000 * @param[in] action_flags 2001 * Bit-fields that holds the actions detected until now. 2002 * @param[in] attr 2003 * Attributes of flow that includes this action. 2004 * @param[out] error 2005 * Pointer to error structure. 2006 * 2007 * @return 2008 * 0 on success, a negative errno value otherwise and rte_errno is set. 2009 */ 2010 int 2011 mlx5_flow_validate_action_flag(uint64_t action_flags, 2012 const struct rte_flow_attr *attr, 2013 struct rte_flow_error *error) 2014 { 2015 if (action_flags & MLX5_FLOW_ACTION_MARK) 2016 return rte_flow_error_set(error, EINVAL, 2017 RTE_FLOW_ERROR_TYPE_ACTION, NULL, 2018 "can't mark and flag in same flow"); 2019 if (action_flags & MLX5_FLOW_ACTION_FLAG) 2020 return rte_flow_error_set(error, EINVAL, 2021 RTE_FLOW_ERROR_TYPE_ACTION, NULL, 2022 "can't have 2 flag" 2023 " actions in same flow"); 2024 if (attr->egress) 2025 return rte_flow_error_set(error, ENOTSUP, 2026 RTE_FLOW_ERROR_TYPE_ATTR_EGRESS, NULL, 2027 "flag action not supported for " 2028 "egress"); 2029 return 0; 2030 } 2031 2032 /* 2033 * Validate the mark action. 2034 * 2035 * @param[in] action 2036 * Pointer to the queue action. 2037 * @param[in] action_flags 2038 * Bit-fields that holds the actions detected until now. 2039 * @param[in] attr 2040 * Attributes of flow that includes this action. 2041 * @param[out] error 2042 * Pointer to error structure. 2043 * 2044 * @return 2045 * 0 on success, a negative errno value otherwise and rte_errno is set. 2046 */ 2047 int 2048 mlx5_flow_validate_action_mark(const struct rte_flow_action *action, 2049 uint64_t action_flags, 2050 const struct rte_flow_attr *attr, 2051 struct rte_flow_error *error) 2052 { 2053 const struct rte_flow_action_mark *mark = action->conf; 2054 2055 if (!mark) 2056 return rte_flow_error_set(error, EINVAL, 2057 RTE_FLOW_ERROR_TYPE_ACTION, 2058 action, 2059 "configuration cannot be null"); 2060 if (mark->id >= MLX5_FLOW_MARK_MAX) 2061 return rte_flow_error_set(error, EINVAL, 2062 RTE_FLOW_ERROR_TYPE_ACTION_CONF, 2063 &mark->id, 2064 "mark id must in 0 <= id < " 2065 RTE_STR(MLX5_FLOW_MARK_MAX)); 2066 if (action_flags & MLX5_FLOW_ACTION_FLAG) 2067 return rte_flow_error_set(error, EINVAL, 2068 RTE_FLOW_ERROR_TYPE_ACTION, NULL, 2069 "can't flag and mark in same flow"); 2070 if (action_flags & MLX5_FLOW_ACTION_MARK) 2071 return rte_flow_error_set(error, EINVAL, 2072 RTE_FLOW_ERROR_TYPE_ACTION, NULL, 2073 "can't have 2 mark actions in same" 2074 " flow"); 2075 if (attr->egress) 2076 return rte_flow_error_set(error, ENOTSUP, 2077 RTE_FLOW_ERROR_TYPE_ATTR_EGRESS, NULL, 2078 "mark action not supported for " 2079 "egress"); 2080 return 0; 2081 } 2082 2083 /* 2084 * Validate the drop action. 2085 * 2086 * @param[in] dev 2087 * Pointer to the Ethernet device structure. 2088 * @param[in] is_root 2089 * True if flow is validated for root table. False otherwise. 2090 * @param[in] attr 2091 * Attributes of flow that includes this action. 2092 * @param[out] error 2093 * Pointer to error structure. 2094 * 2095 * @return 2096 * 0 on success, a negative errno value otherwise and rte_errno is set. 2097 */ 2098 int 2099 mlx5_flow_validate_action_drop(struct rte_eth_dev *dev, 2100 bool is_root, 2101 const struct rte_flow_attr *attr, 2102 struct rte_flow_error *error) 2103 { 2104 struct mlx5_priv *priv = dev->data->dev_private; 2105 2106 if (priv->sh->config.dv_flow_en == 0 && attr->egress) 2107 return rte_flow_error_set(error, ENOTSUP, 2108 RTE_FLOW_ERROR_TYPE_ATTR_EGRESS, NULL, 2109 "drop action not supported for " 2110 "egress"); 2111 if (priv->sh->config.dv_flow_en == 1 && is_root && (attr->egress || attr->transfer) && 2112 !priv->sh->dr_root_drop_action_en) { 2113 return rte_flow_error_set(error, ENOTSUP, 2114 RTE_FLOW_ERROR_TYPE_ATTR, NULL, 2115 "drop action not supported for " 2116 "egress and transfer on group 0"); 2117 } 2118 return 0; 2119 } 2120 2121 /* 2122 * Validate the queue action. 2123 * 2124 * @param[in] action 2125 * Pointer to the queue action. 2126 * @param[in] action_flags 2127 * Bit-fields that holds the actions detected until now. 2128 * @param[in] dev 2129 * Pointer to the Ethernet device structure. 2130 * @param[in] attr 2131 * Attributes of flow that includes this action. 2132 * @param[out] error 2133 * Pointer to error structure. 2134 * 2135 * @return 2136 * 0 on success, a negative errno value otherwise and rte_errno is set. 2137 */ 2138 int 2139 mlx5_flow_validate_action_queue(const struct rte_flow_action *action, 2140 uint64_t action_flags, 2141 struct rte_eth_dev *dev, 2142 const struct rte_flow_attr *attr, 2143 struct rte_flow_error *error) 2144 { 2145 struct mlx5_priv *priv = dev->data->dev_private; 2146 const struct rte_flow_action_queue *queue = action->conf; 2147 2148 if (action_flags & MLX5_FLOW_FATE_ACTIONS) 2149 return rte_flow_error_set(error, EINVAL, 2150 RTE_FLOW_ERROR_TYPE_ACTION, NULL, 2151 "can't have 2 fate actions in" 2152 " same flow"); 2153 if (attr->egress) 2154 return rte_flow_error_set(error, ENOTSUP, 2155 RTE_FLOW_ERROR_TYPE_ATTR_EGRESS, NULL, 2156 "queue action not supported for egress."); 2157 if (mlx5_is_external_rxq(dev, queue->index)) 2158 return 0; 2159 if (!priv->rxqs_n) 2160 return rte_flow_error_set(error, EINVAL, 2161 RTE_FLOW_ERROR_TYPE_ACTION_CONF, 2162 NULL, "No Rx queues configured"); 2163 if (queue->index >= priv->rxqs_n) 2164 return rte_flow_error_set(error, EINVAL, 2165 RTE_FLOW_ERROR_TYPE_ACTION_CONF, 2166 &queue->index, 2167 "queue index out of range"); 2168 if (mlx5_rxq_get(dev, queue->index) == NULL) 2169 return rte_flow_error_set(error, EINVAL, 2170 RTE_FLOW_ERROR_TYPE_ACTION_CONF, 2171 &queue->index, 2172 "queue is not configured"); 2173 return 0; 2174 } 2175 2176 /** 2177 * Validate queue numbers for device RSS. 2178 * 2179 * @param[in] dev 2180 * Configured device. 2181 * @param[in] queues 2182 * Array of queue numbers. 2183 * @param[in] queues_n 2184 * Size of the @p queues array. 2185 * @param[out] error 2186 * On error, filled with a textual error description. 2187 * @param[out] queue_idx 2188 * On error, filled with an offending queue index in @p queues array. 2189 * 2190 * @return 2191 * 0 on success, a negative errno code on error. 2192 */ 2193 static int 2194 mlx5_validate_rss_queues(struct rte_eth_dev *dev, 2195 const uint16_t *queues, uint32_t queues_n, 2196 const char **error, uint32_t *queue_idx) 2197 { 2198 const struct mlx5_priv *priv = dev->data->dev_private; 2199 bool is_hairpin = false; 2200 bool is_ext_rss = false; 2201 uint32_t i; 2202 2203 for (i = 0; i != queues_n; ++i) { 2204 struct mlx5_rxq_ctrl *rxq_ctrl; 2205 2206 if (mlx5_is_external_rxq(dev, queues[0])) { 2207 is_ext_rss = true; 2208 continue; 2209 } 2210 if (is_ext_rss) { 2211 *error = "Combining external and regular RSS queues is not supported"; 2212 *queue_idx = i; 2213 return -ENOTSUP; 2214 } 2215 if (queues[i] >= priv->rxqs_n) { 2216 *error = "queue index out of range"; 2217 *queue_idx = i; 2218 return -EINVAL; 2219 } 2220 rxq_ctrl = mlx5_rxq_ctrl_get(dev, queues[i]); 2221 if (rxq_ctrl == NULL) { 2222 *error = "queue is not configured"; 2223 *queue_idx = i; 2224 return -EINVAL; 2225 } 2226 if (i == 0 && rxq_ctrl->is_hairpin) 2227 is_hairpin = true; 2228 if (is_hairpin != rxq_ctrl->is_hairpin) { 2229 *error = "combining hairpin and regular RSS queues is not supported"; 2230 *queue_idx = i; 2231 return -ENOTSUP; 2232 } 2233 } 2234 return 0; 2235 } 2236 2237 /* 2238 * Validate the rss action. 2239 * 2240 * @param[in] dev 2241 * Pointer to the Ethernet device structure. 2242 * @param[in] action 2243 * Pointer to the queue action. 2244 * @param[out] error 2245 * Pointer to error structure. 2246 * 2247 * @return 2248 * 0 on success, a negative errno value otherwise and rte_errno is set. 2249 */ 2250 int 2251 mlx5_validate_action_rss(struct rte_eth_dev *dev, 2252 const struct rte_flow_action *action, 2253 struct rte_flow_error *error) 2254 { 2255 struct mlx5_priv *priv = dev->data->dev_private; 2256 const struct rte_flow_action_rss *rss = action->conf; 2257 int ret; 2258 const char *message; 2259 uint32_t queue_idx; 2260 2261 if (rss->func == RTE_ETH_HASH_FUNCTION_SYMMETRIC_TOEPLITZ) { 2262 DRV_LOG(WARNING, "port %u symmetric RSS supported with SORT", 2263 dev->data->port_id); 2264 } else if (rss->func != RTE_ETH_HASH_FUNCTION_DEFAULT && 2265 rss->func != RTE_ETH_HASH_FUNCTION_TOEPLITZ) 2266 return rte_flow_error_set(error, ENOTSUP, 2267 RTE_FLOW_ERROR_TYPE_ACTION_CONF, 2268 &rss->func, 2269 "RSS hash function not supported"); 2270 #ifdef HAVE_IBV_DEVICE_TUNNEL_SUPPORT 2271 if (rss->level > 2) 2272 #else 2273 if (rss->level > 1) 2274 #endif 2275 return rte_flow_error_set(error, ENOTSUP, 2276 RTE_FLOW_ERROR_TYPE_ACTION_CONF, 2277 &rss->level, 2278 "tunnel RSS is not supported"); 2279 /* allow RSS key_len 0 in case of NULL (default) RSS key. */ 2280 if (rss->key_len == 0 && rss->key != NULL) 2281 return rte_flow_error_set(error, ENOTSUP, 2282 RTE_FLOW_ERROR_TYPE_ACTION_CONF, 2283 &rss->key_len, 2284 "RSS hash key length 0"); 2285 if (rss->key_len > 0 && rss->key_len < MLX5_RSS_HASH_KEY_LEN) 2286 return rte_flow_error_set(error, ENOTSUP, 2287 RTE_FLOW_ERROR_TYPE_ACTION_CONF, 2288 &rss->key_len, 2289 "RSS hash key too small"); 2290 if (rss->key_len > MLX5_RSS_HASH_KEY_LEN) 2291 return rte_flow_error_set(error, ENOTSUP, 2292 RTE_FLOW_ERROR_TYPE_ACTION_CONF, 2293 &rss->key_len, 2294 "RSS hash key too large"); 2295 if (rss->queue_num > priv->sh->dev_cap.ind_table_max_size) 2296 return rte_flow_error_set(error, ENOTSUP, 2297 RTE_FLOW_ERROR_TYPE_ACTION_CONF, 2298 &rss->queue_num, 2299 "number of queues too large"); 2300 if (rss->types & MLX5_RSS_HF_MASK) 2301 return rte_flow_error_set(error, ENOTSUP, 2302 RTE_FLOW_ERROR_TYPE_ACTION_CONF, 2303 &rss->types, 2304 "some RSS protocols are not" 2305 " supported"); 2306 if ((rss->types & (RTE_ETH_RSS_L3_SRC_ONLY | RTE_ETH_RSS_L3_DST_ONLY)) && 2307 !(rss->types & RTE_ETH_RSS_IP)) 2308 return rte_flow_error_set(error, EINVAL, 2309 RTE_FLOW_ERROR_TYPE_ACTION_CONF, NULL, 2310 "L3 partial RSS requested but L3 RSS" 2311 " type not specified"); 2312 if ((rss->types & (RTE_ETH_RSS_L4_SRC_ONLY | RTE_ETH_RSS_L4_DST_ONLY)) && 2313 !(rss->types & (RTE_ETH_RSS_UDP | RTE_ETH_RSS_TCP))) 2314 return rte_flow_error_set(error, EINVAL, 2315 RTE_FLOW_ERROR_TYPE_ACTION_CONF, NULL, 2316 "L4 partial RSS requested but L4 RSS" 2317 " type not specified"); 2318 if (!priv->rxqs_n && priv->ext_rxqs == NULL) 2319 return rte_flow_error_set(error, EINVAL, 2320 RTE_FLOW_ERROR_TYPE_ACTION_CONF, 2321 NULL, "No Rx queues configured"); 2322 if (!rss->queue_num) 2323 return rte_flow_error_set(error, EINVAL, 2324 RTE_FLOW_ERROR_TYPE_ACTION_CONF, 2325 NULL, "No queues configured"); 2326 ret = mlx5_validate_rss_queues(dev, rss->queue, rss->queue_num, 2327 &message, &queue_idx); 2328 if (ret != 0) { 2329 return rte_flow_error_set(error, -ret, 2330 RTE_FLOW_ERROR_TYPE_ACTION_CONF, 2331 &rss->queue[queue_idx], message); 2332 } 2333 return 0; 2334 } 2335 2336 /* 2337 * Validate the rss action. 2338 * 2339 * @param[in] action 2340 * Pointer to the queue action. 2341 * @param[in] action_flags 2342 * Bit-fields that holds the actions detected until now. 2343 * @param[in] dev 2344 * Pointer to the Ethernet device structure. 2345 * @param[in] attr 2346 * Attributes of flow that includes this action. 2347 * @param[in] item_flags 2348 * Items that were detected. 2349 * @param[out] error 2350 * Pointer to error structure. 2351 * 2352 * @return 2353 * 0 on success, a negative errno value otherwise and rte_errno is set. 2354 */ 2355 int 2356 mlx5_flow_validate_action_rss(const struct rte_flow_action *action, 2357 uint64_t action_flags, 2358 struct rte_eth_dev *dev, 2359 const struct rte_flow_attr *attr, 2360 uint64_t item_flags, 2361 struct rte_flow_error *error) 2362 { 2363 const struct rte_flow_action_rss *rss = action->conf; 2364 int tunnel = !!(item_flags & MLX5_FLOW_LAYER_TUNNEL); 2365 int ret; 2366 2367 if (action_flags & MLX5_FLOW_FATE_ACTIONS) 2368 return rte_flow_error_set(error, EINVAL, 2369 RTE_FLOW_ERROR_TYPE_ACTION, NULL, 2370 "can't have 2 fate actions" 2371 " in same flow"); 2372 ret = mlx5_validate_action_rss(dev, action, error); 2373 if (ret) 2374 return ret; 2375 if (attr->egress) 2376 return rte_flow_error_set(error, ENOTSUP, 2377 RTE_FLOW_ERROR_TYPE_ATTR_EGRESS, NULL, 2378 "rss action not supported for " 2379 "egress"); 2380 if (rss->level > 1 && !tunnel) 2381 return rte_flow_error_set(error, EINVAL, 2382 RTE_FLOW_ERROR_TYPE_ACTION_CONF, NULL, 2383 "inner RSS is not supported for " 2384 "non-tunnel flows"); 2385 if ((item_flags & MLX5_FLOW_LAYER_ECPRI) && 2386 !(item_flags & MLX5_FLOW_LAYER_INNER_L4_UDP)) { 2387 return rte_flow_error_set(error, EINVAL, 2388 RTE_FLOW_ERROR_TYPE_ACTION_CONF, NULL, 2389 "RSS on eCPRI is not supported now"); 2390 } 2391 if ((item_flags & MLX5_FLOW_LAYER_MPLS) && 2392 !(item_flags & 2393 (MLX5_FLOW_LAYER_INNER_L2 | MLX5_FLOW_LAYER_INNER_L3)) && 2394 rss->level > 1) 2395 return rte_flow_error_set(error, EINVAL, 2396 RTE_FLOW_ERROR_TYPE_ITEM, NULL, 2397 "MPLS inner RSS needs to specify inner L2/L3 items after MPLS in pattern"); 2398 return 0; 2399 } 2400 2401 /* 2402 * Validate the default miss action. 2403 * 2404 * @param[in] action_flags 2405 * Bit-fields that holds the actions detected until now. 2406 * @param[out] error 2407 * Pointer to error structure. 2408 * 2409 * @return 2410 * 0 on success, a negative errno value otherwise and rte_errno is set. 2411 */ 2412 int 2413 mlx5_flow_validate_action_default_miss(uint64_t action_flags, 2414 const struct rte_flow_attr *attr, 2415 struct rte_flow_error *error) 2416 { 2417 if (action_flags & MLX5_FLOW_FATE_ACTIONS) 2418 return rte_flow_error_set(error, EINVAL, 2419 RTE_FLOW_ERROR_TYPE_ACTION, NULL, 2420 "can't have 2 fate actions in" 2421 " same flow"); 2422 if (attr->egress) 2423 return rte_flow_error_set(error, ENOTSUP, 2424 RTE_FLOW_ERROR_TYPE_ATTR_EGRESS, NULL, 2425 "default miss action not supported " 2426 "for egress"); 2427 if (attr->group) 2428 return rte_flow_error_set(error, ENOTSUP, 2429 RTE_FLOW_ERROR_TYPE_ATTR_GROUP, NULL, 2430 "only group 0 is supported"); 2431 if (attr->transfer) 2432 return rte_flow_error_set(error, ENOTSUP, 2433 RTE_FLOW_ERROR_TYPE_ATTR_TRANSFER, 2434 NULL, "transfer is not supported"); 2435 return 0; 2436 } 2437 2438 /* 2439 * Validate the count action. 2440 * 2441 * @param[in] dev 2442 * Pointer to the Ethernet device structure. 2443 * @param[in] attr 2444 * Attributes of flow that includes this action. 2445 * @param[out] error 2446 * Pointer to error structure. 2447 * 2448 * @return 2449 * 0 on success, a negative errno value otherwise and rte_errno is set. 2450 */ 2451 int 2452 mlx5_flow_validate_action_count(struct rte_eth_dev *dev __rte_unused, 2453 const struct rte_flow_attr *attr, 2454 struct rte_flow_error *error) 2455 { 2456 if (attr->egress) 2457 return rte_flow_error_set(error, ENOTSUP, 2458 RTE_FLOW_ERROR_TYPE_ATTR_EGRESS, NULL, 2459 "count action not supported for " 2460 "egress"); 2461 return 0; 2462 } 2463 2464 /* 2465 * Validate the ASO CT action. 2466 * 2467 * @param[in] dev 2468 * Pointer to the Ethernet device structure. 2469 * @param[in] conntrack 2470 * Pointer to the CT action profile. 2471 * @param[out] error 2472 * Pointer to error structure. 2473 * 2474 * @return 2475 * 0 on success, a negative errno value otherwise and rte_errno is set. 2476 */ 2477 int 2478 mlx5_validate_action_ct(struct rte_eth_dev *dev, 2479 const struct rte_flow_action_conntrack *conntrack, 2480 struct rte_flow_error *error) 2481 { 2482 RTE_SET_USED(dev); 2483 2484 if (conntrack->state > RTE_FLOW_CONNTRACK_STATE_TIME_WAIT) 2485 return rte_flow_error_set(error, EINVAL, 2486 RTE_FLOW_ERROR_TYPE_ACTION, NULL, 2487 "Invalid CT state"); 2488 if (conntrack->last_index > RTE_FLOW_CONNTRACK_FLAG_RST) 2489 return rte_flow_error_set(error, EINVAL, 2490 RTE_FLOW_ERROR_TYPE_ACTION, NULL, 2491 "Invalid last TCP packet flag"); 2492 return 0; 2493 } 2494 2495 /** 2496 * Validate the level value for modify field action. 2497 * 2498 * @param[in] data 2499 * Pointer to the rte_flow_action_modify_data structure either src or dst. 2500 * @param[out] error 2501 * Pointer to error structure. 2502 * 2503 * @return 2504 * 0 on success, a negative errno value otherwise and rte_errno is set. 2505 */ 2506 int 2507 flow_validate_modify_field_level(const struct rte_flow_action_modify_data *data, 2508 struct rte_flow_error *error) 2509 { 2510 if (data->level == 0) 2511 return 0; 2512 if (data->field != RTE_FLOW_FIELD_TAG && 2513 data->field != (enum rte_flow_field_id)MLX5_RTE_FLOW_FIELD_META_REG) 2514 return rte_flow_error_set(error, ENOTSUP, 2515 RTE_FLOW_ERROR_TYPE_ACTION, NULL, 2516 "inner header fields modification is not supported"); 2517 if (data->tag_index != 0) 2518 return rte_flow_error_set(error, EINVAL, 2519 RTE_FLOW_ERROR_TYPE_ACTION, NULL, 2520 "tag array can be provided using 'level' or 'tag_index' fields, not both"); 2521 /* 2522 * The tag array for RTE_FLOW_FIELD_TAG type is provided using 2523 * 'tag_index' field. In old API, it was provided using 'level' field 2524 * and it is still supported for backwards compatibility. 2525 */ 2526 DRV_LOG(DEBUG, "tag array provided in 'level' field instead of 'tag_index' field."); 2527 return 0; 2528 } 2529 2530 /** 2531 * Validate ICMP6 item. 2532 * 2533 * @param[in] item 2534 * Item specification. 2535 * @param[in] item_flags 2536 * Bit-fields that holds the items detected until now. 2537 * @param[in] ext_vlan_sup 2538 * Whether extended VLAN features are supported or not. 2539 * @param[out] error 2540 * Pointer to error structure. 2541 * 2542 * @return 2543 * 0 on success, a negative errno value otherwise and rte_errno is set. 2544 */ 2545 int 2546 mlx5_flow_validate_item_icmp6(const struct rte_flow_item *item, 2547 uint64_t item_flags, 2548 uint8_t target_protocol, 2549 struct rte_flow_error *error) 2550 { 2551 const struct rte_flow_item_icmp6 *mask = item->mask; 2552 const int tunnel = !!(item_flags & MLX5_FLOW_LAYER_TUNNEL); 2553 const uint64_t l3m = tunnel ? MLX5_FLOW_LAYER_INNER_L3_IPV6 : 2554 MLX5_FLOW_LAYER_OUTER_L3_IPV6; 2555 const uint64_t l4m = tunnel ? MLX5_FLOW_LAYER_INNER_L4 : 2556 MLX5_FLOW_LAYER_OUTER_L4; 2557 int ret; 2558 2559 if (target_protocol != 0xFF && target_protocol != IPPROTO_ICMPV6) 2560 return rte_flow_error_set(error, EINVAL, 2561 RTE_FLOW_ERROR_TYPE_ITEM, item, 2562 "protocol filtering not compatible" 2563 " with ICMP6 layer"); 2564 if (!(item_flags & l3m)) 2565 return rte_flow_error_set(error, EINVAL, 2566 RTE_FLOW_ERROR_TYPE_ITEM, item, 2567 "IPv6 is mandatory to filter on" 2568 " ICMP6"); 2569 if (item_flags & l4m) 2570 return rte_flow_error_set(error, EINVAL, 2571 RTE_FLOW_ERROR_TYPE_ITEM, item, 2572 "multiple L4 layers not supported"); 2573 if (!mask) 2574 mask = &rte_flow_item_icmp6_mask; 2575 ret = mlx5_flow_item_acceptable 2576 (item, (const uint8_t *)mask, 2577 (const uint8_t *)&rte_flow_item_icmp6_mask, 2578 sizeof(struct rte_flow_item_icmp6), 2579 MLX5_ITEM_RANGE_NOT_ACCEPTED, error); 2580 if (ret < 0) 2581 return ret; 2582 return 0; 2583 } 2584 2585 /** 2586 * Validate ICMP6 echo request/reply item. 2587 * 2588 * @param[in] item 2589 * Item specification. 2590 * @param[in] item_flags 2591 * Bit-fields that holds the items detected until now. 2592 * @param[in] ext_vlan_sup 2593 * Whether extended VLAN features are supported or not. 2594 * @param[out] error 2595 * Pointer to error structure. 2596 * 2597 * @return 2598 * 0 on success, a negative errno value otherwise and rte_errno is set. 2599 */ 2600 int 2601 mlx5_flow_validate_item_icmp6_echo(const struct rte_flow_item *item, 2602 uint64_t item_flags, 2603 uint8_t target_protocol, 2604 struct rte_flow_error *error) 2605 { 2606 const struct rte_flow_item_icmp6_echo *mask = item->mask; 2607 const struct rte_flow_item_icmp6_echo nic_mask = { 2608 .hdr.base.type = 0xff, 2609 .hdr.base.code = 0xff, 2610 .hdr.identifier = RTE_BE16(0xffff), 2611 .hdr.sequence = RTE_BE16(0xffff), 2612 }; 2613 const int tunnel = !!(item_flags & MLX5_FLOW_LAYER_TUNNEL); 2614 const uint64_t l3m = tunnel ? MLX5_FLOW_LAYER_INNER_L3_IPV6 : 2615 MLX5_FLOW_LAYER_OUTER_L3_IPV6; 2616 const uint64_t l4m = tunnel ? MLX5_FLOW_LAYER_INNER_L4 : 2617 MLX5_FLOW_LAYER_OUTER_L4; 2618 int ret; 2619 2620 if (target_protocol != 0xFF && target_protocol != IPPROTO_ICMPV6) 2621 return rte_flow_error_set(error, EINVAL, 2622 RTE_FLOW_ERROR_TYPE_ITEM, item, 2623 "protocol filtering not compatible" 2624 " with ICMP6 layer"); 2625 if (!(item_flags & l3m)) 2626 return rte_flow_error_set(error, EINVAL, 2627 RTE_FLOW_ERROR_TYPE_ITEM, item, 2628 "IPv6 is mandatory to filter on" 2629 " ICMP6"); 2630 if (item_flags & l4m) 2631 return rte_flow_error_set(error, EINVAL, 2632 RTE_FLOW_ERROR_TYPE_ITEM, item, 2633 "multiple L4 layers not supported"); 2634 if (!mask) 2635 mask = &nic_mask; 2636 ret = mlx5_flow_item_acceptable 2637 (item, (const uint8_t *)mask, 2638 (const uint8_t *)&nic_mask, 2639 sizeof(struct rte_flow_item_icmp6_echo), 2640 MLX5_ITEM_RANGE_NOT_ACCEPTED, error); 2641 if (ret < 0) 2642 return ret; 2643 return 0; 2644 } 2645 2646 /** 2647 * Validate ICMP item. 2648 * 2649 * @param[in] item 2650 * Item specification. 2651 * @param[in] item_flags 2652 * Bit-fields that holds the items detected until now. 2653 * @param[out] error 2654 * Pointer to error structure. 2655 * 2656 * @return 2657 * 0 on success, a negative errno value otherwise and rte_errno is set. 2658 */ 2659 int 2660 mlx5_flow_validate_item_icmp(const struct rte_flow_item *item, 2661 uint64_t item_flags, 2662 uint8_t target_protocol, 2663 struct rte_flow_error *error) 2664 { 2665 const struct rte_flow_item_icmp *mask = item->mask; 2666 const struct rte_flow_item_icmp nic_mask = { 2667 .hdr.icmp_type = 0xff, 2668 .hdr.icmp_code = 0xff, 2669 .hdr.icmp_ident = RTE_BE16(0xffff), 2670 .hdr.icmp_seq_nb = RTE_BE16(0xffff), 2671 }; 2672 const int tunnel = !!(item_flags & MLX5_FLOW_LAYER_TUNNEL); 2673 const uint64_t l3m = tunnel ? MLX5_FLOW_LAYER_INNER_L3_IPV4 : 2674 MLX5_FLOW_LAYER_OUTER_L3_IPV4; 2675 const uint64_t l4m = tunnel ? MLX5_FLOW_LAYER_INNER_L4 : 2676 MLX5_FLOW_LAYER_OUTER_L4; 2677 int ret; 2678 2679 if (target_protocol != 0xFF && target_protocol != IPPROTO_ICMP) 2680 return rte_flow_error_set(error, EINVAL, 2681 RTE_FLOW_ERROR_TYPE_ITEM, item, 2682 "protocol filtering not compatible" 2683 " with ICMP layer"); 2684 if (!(item_flags & l3m)) 2685 return rte_flow_error_set(error, EINVAL, 2686 RTE_FLOW_ERROR_TYPE_ITEM, item, 2687 "IPv4 is mandatory to filter" 2688 " on ICMP"); 2689 if (item_flags & l4m) 2690 return rte_flow_error_set(error, EINVAL, 2691 RTE_FLOW_ERROR_TYPE_ITEM, item, 2692 "multiple L4 layers not supported"); 2693 if (!mask) 2694 mask = &nic_mask; 2695 ret = mlx5_flow_item_acceptable 2696 (item, (const uint8_t *)mask, 2697 (const uint8_t *)&nic_mask, 2698 sizeof(struct rte_flow_item_icmp), 2699 MLX5_ITEM_RANGE_NOT_ACCEPTED, error); 2700 if (ret < 0) 2701 return ret; 2702 return 0; 2703 } 2704 2705 /** 2706 * Validate Ethernet item. 2707 * 2708 * @param[in] item 2709 * Item specification. 2710 * @param[in] item_flags 2711 * Bit-fields that holds the items detected until now. 2712 * @param[out] error 2713 * Pointer to error structure. 2714 * 2715 * @return 2716 * 0 on success, a negative errno value otherwise and rte_errno is set. 2717 */ 2718 int 2719 mlx5_flow_validate_item_eth(const struct rte_flow_item *item, 2720 uint64_t item_flags, bool ext_vlan_sup, 2721 struct rte_flow_error *error) 2722 { 2723 const struct rte_flow_item_eth *mask = item->mask; 2724 const struct rte_flow_item_eth nic_mask = { 2725 .hdr.dst_addr.addr_bytes = "\xff\xff\xff\xff\xff\xff", 2726 .hdr.src_addr.addr_bytes = "\xff\xff\xff\xff\xff\xff", 2727 .hdr.ether_type = RTE_BE16(0xffff), 2728 .has_vlan = ext_vlan_sup ? 1 : 0, 2729 }; 2730 int ret; 2731 int tunnel = !!(item_flags & MLX5_FLOW_LAYER_TUNNEL); 2732 const uint64_t ethm = tunnel ? MLX5_FLOW_LAYER_INNER_L2 : 2733 MLX5_FLOW_LAYER_OUTER_L2; 2734 2735 if (item_flags & ethm) 2736 return rte_flow_error_set(error, ENOTSUP, 2737 RTE_FLOW_ERROR_TYPE_ITEM, item, 2738 "multiple L2 layers not supported"); 2739 if ((!tunnel && (item_flags & MLX5_FLOW_LAYER_OUTER_L3)) || 2740 (tunnel && (item_flags & MLX5_FLOW_LAYER_INNER_L3))) 2741 return rte_flow_error_set(error, EINVAL, 2742 RTE_FLOW_ERROR_TYPE_ITEM, item, 2743 "L2 layer should not follow " 2744 "L3 layers"); 2745 if ((!tunnel && (item_flags & MLX5_FLOW_LAYER_OUTER_VLAN)) || 2746 (tunnel && (item_flags & MLX5_FLOW_LAYER_INNER_VLAN))) 2747 return rte_flow_error_set(error, EINVAL, 2748 RTE_FLOW_ERROR_TYPE_ITEM, item, 2749 "L2 layer should not follow VLAN"); 2750 if (item_flags & MLX5_FLOW_LAYER_GTP) 2751 return rte_flow_error_set(error, EINVAL, 2752 RTE_FLOW_ERROR_TYPE_ITEM, item, 2753 "L2 layer should not follow GTP"); 2754 if (!mask) 2755 mask = &rte_flow_item_eth_mask; 2756 ret = mlx5_flow_item_acceptable(item, (const uint8_t *)mask, 2757 (const uint8_t *)&nic_mask, 2758 sizeof(struct rte_flow_item_eth), 2759 MLX5_ITEM_RANGE_NOT_ACCEPTED, error); 2760 return ret; 2761 } 2762 2763 /** 2764 * Validate VLAN item. 2765 * 2766 * @param[in] item 2767 * Item specification. 2768 * @param[in] item_flags 2769 * Bit-fields that holds the items detected until now. 2770 * @param[in] dev 2771 * Ethernet device flow is being created on. 2772 * @param[out] error 2773 * Pointer to error structure. 2774 * 2775 * @return 2776 * 0 on success, a negative errno value otherwise and rte_errno is set. 2777 */ 2778 int 2779 mlx5_flow_validate_item_vlan(const struct rte_flow_item *item, 2780 uint64_t item_flags, 2781 struct rte_eth_dev *dev, 2782 struct rte_flow_error *error) 2783 { 2784 const struct rte_flow_item_vlan *spec = item->spec; 2785 const struct rte_flow_item_vlan *mask = item->mask; 2786 const struct rte_flow_item_vlan nic_mask = { 2787 .hdr.vlan_tci = RTE_BE16(UINT16_MAX), 2788 .hdr.eth_proto = RTE_BE16(UINT16_MAX), 2789 }; 2790 uint16_t vlan_tag = 0; 2791 const int tunnel = !!(item_flags & MLX5_FLOW_LAYER_TUNNEL); 2792 int ret; 2793 const uint64_t l34m = tunnel ? (MLX5_FLOW_LAYER_INNER_L3 | 2794 MLX5_FLOW_LAYER_INNER_L4) : 2795 (MLX5_FLOW_LAYER_OUTER_L3 | 2796 MLX5_FLOW_LAYER_OUTER_L4); 2797 const uint64_t vlanm = tunnel ? MLX5_FLOW_LAYER_INNER_VLAN : 2798 MLX5_FLOW_LAYER_OUTER_VLAN; 2799 2800 if (item_flags & vlanm) 2801 return rte_flow_error_set(error, EINVAL, 2802 RTE_FLOW_ERROR_TYPE_ITEM, item, 2803 "multiple VLAN layers not supported"); 2804 else if ((item_flags & l34m) != 0) 2805 return rte_flow_error_set(error, EINVAL, 2806 RTE_FLOW_ERROR_TYPE_ITEM, item, 2807 "VLAN cannot follow L3/L4 layer"); 2808 if (!mask) 2809 mask = &rte_flow_item_vlan_mask; 2810 ret = mlx5_flow_item_acceptable(item, (const uint8_t *)mask, 2811 (const uint8_t *)&nic_mask, 2812 sizeof(struct rte_flow_item_vlan), 2813 MLX5_ITEM_RANGE_NOT_ACCEPTED, error); 2814 if (ret) 2815 return ret; 2816 if (!tunnel && mask->hdr.vlan_tci != RTE_BE16(0x0fff)) { 2817 struct mlx5_priv *priv = dev->data->dev_private; 2818 2819 if (priv->vmwa_context) { 2820 /* 2821 * Non-NULL context means we have a virtual machine 2822 * and SR-IOV enabled, we have to create VLAN interface 2823 * to make hypervisor to setup E-Switch vport 2824 * context correctly. We avoid creating the multiple 2825 * VLAN interfaces, so we cannot support VLAN tag mask. 2826 */ 2827 return rte_flow_error_set(error, EINVAL, 2828 RTE_FLOW_ERROR_TYPE_ITEM, 2829 item, 2830 "VLAN tag mask is not" 2831 " supported in virtual" 2832 " environment"); 2833 } 2834 } 2835 if (spec) { 2836 vlan_tag = spec->hdr.vlan_tci; 2837 vlan_tag &= mask->hdr.vlan_tci; 2838 } 2839 /* 2840 * From verbs perspective an empty VLAN is equivalent 2841 * to a packet without VLAN layer. 2842 */ 2843 if (!vlan_tag) 2844 return rte_flow_error_set(error, EINVAL, 2845 RTE_FLOW_ERROR_TYPE_ITEM_SPEC, 2846 item->spec, 2847 "VLAN cannot be empty"); 2848 return 0; 2849 } 2850 2851 /** 2852 * Validate IPV4 item. 2853 * 2854 * @param[in] item 2855 * Item specification. 2856 * @param[in] item_flags 2857 * Bit-fields that holds the items detected until now. 2858 * @param[in] last_item 2859 * Previous validated item in the pattern items. 2860 * @param[in] ether_type 2861 * Type in the ethernet layer header (including dot1q). 2862 * @param[in] acc_mask 2863 * Acceptable mask, if NULL default internal default mask 2864 * will be used to check whether item fields are supported. 2865 * @param[in] range_accepted 2866 * True if range of values is accepted for specific fields, false otherwise. 2867 * @param[out] error 2868 * Pointer to error structure. 2869 * 2870 * @return 2871 * 0 on success, a negative errno value otherwise and rte_errno is set. 2872 */ 2873 int 2874 mlx5_flow_validate_item_ipv4(const struct rte_flow_item *item, 2875 uint64_t item_flags, 2876 uint64_t last_item, 2877 uint16_t ether_type, 2878 const struct rte_flow_item_ipv4 *acc_mask, 2879 bool range_accepted, 2880 struct rte_flow_error *error) 2881 { 2882 const struct rte_flow_item_ipv4 *mask = item->mask; 2883 const struct rte_flow_item_ipv4 *spec = item->spec; 2884 const struct rte_flow_item_ipv4 nic_mask = { 2885 .hdr = { 2886 .src_addr = RTE_BE32(0xffffffff), 2887 .dst_addr = RTE_BE32(0xffffffff), 2888 .type_of_service = 0xff, 2889 .next_proto_id = 0xff, 2890 }, 2891 }; 2892 const int tunnel = !!(item_flags & MLX5_FLOW_LAYER_TUNNEL); 2893 const uint64_t l3m = tunnel ? MLX5_FLOW_LAYER_INNER_L3 : 2894 MLX5_FLOW_LAYER_OUTER_L3; 2895 const uint64_t l4m = tunnel ? MLX5_FLOW_LAYER_INNER_L4 : 2896 MLX5_FLOW_LAYER_OUTER_L4; 2897 int ret; 2898 uint8_t next_proto = 0xFF; 2899 const uint64_t l2_vlan = (MLX5_FLOW_LAYER_L2 | 2900 MLX5_FLOW_LAYER_OUTER_VLAN | 2901 MLX5_FLOW_LAYER_INNER_VLAN); 2902 2903 if ((last_item & l2_vlan) && ether_type && 2904 ether_type != RTE_ETHER_TYPE_IPV4) 2905 return rte_flow_error_set(error, EINVAL, 2906 RTE_FLOW_ERROR_TYPE_ITEM, item, 2907 "IPv4 cannot follow L2/VLAN layer " 2908 "which ether type is not IPv4"); 2909 if (item_flags & MLX5_FLOW_LAYER_IPIP) { 2910 if (mask && spec) 2911 next_proto = mask->hdr.next_proto_id & 2912 spec->hdr.next_proto_id; 2913 if (next_proto == IPPROTO_IPIP || next_proto == IPPROTO_IPV6) 2914 return rte_flow_error_set(error, EINVAL, 2915 RTE_FLOW_ERROR_TYPE_ITEM, 2916 item, 2917 "multiple tunnel " 2918 "not supported"); 2919 } 2920 if (item_flags & MLX5_FLOW_LAYER_IPV6_ENCAP) 2921 return rte_flow_error_set(error, EINVAL, 2922 RTE_FLOW_ERROR_TYPE_ITEM, item, 2923 "wrong tunnel type - IPv6 specified " 2924 "but IPv4 item provided"); 2925 if (item_flags & l3m) 2926 return rte_flow_error_set(error, ENOTSUP, 2927 RTE_FLOW_ERROR_TYPE_ITEM, item, 2928 "multiple L3 layers not supported"); 2929 else if (item_flags & l4m) 2930 return rte_flow_error_set(error, EINVAL, 2931 RTE_FLOW_ERROR_TYPE_ITEM, item, 2932 "L3 cannot follow an L4 layer."); 2933 else if ((item_flags & MLX5_FLOW_LAYER_NVGRE) && 2934 !(item_flags & MLX5_FLOW_LAYER_INNER_L2)) 2935 return rte_flow_error_set(error, EINVAL, 2936 RTE_FLOW_ERROR_TYPE_ITEM, item, 2937 "L3 cannot follow an NVGRE layer."); 2938 if (!mask) 2939 mask = &rte_flow_item_ipv4_mask; 2940 else if (mask->hdr.next_proto_id != 0 && 2941 mask->hdr.next_proto_id != 0xff) 2942 return rte_flow_error_set(error, EINVAL, 2943 RTE_FLOW_ERROR_TYPE_ITEM_MASK, mask, 2944 "partial mask is not supported" 2945 " for protocol"); 2946 ret = mlx5_flow_item_acceptable(item, (const uint8_t *)mask, 2947 acc_mask ? (const uint8_t *)acc_mask 2948 : (const uint8_t *)&nic_mask, 2949 sizeof(struct rte_flow_item_ipv4), 2950 range_accepted, error); 2951 if (ret < 0) 2952 return ret; 2953 return 0; 2954 } 2955 2956 /** 2957 * Validate IPV6 item. 2958 * 2959 * @param[in] item 2960 * Item specification. 2961 * @param[in] item_flags 2962 * Bit-fields that holds the items detected until now. 2963 * @param[in] last_item 2964 * Previous validated item in the pattern items. 2965 * @param[in] ether_type 2966 * Type in the ethernet layer header (including dot1q). 2967 * @param[in] acc_mask 2968 * Acceptable mask, if NULL default internal default mask 2969 * will be used to check whether item fields are supported. 2970 * @param[out] error 2971 * Pointer to error structure. 2972 * 2973 * @return 2974 * 0 on success, a negative errno value otherwise and rte_errno is set. 2975 */ 2976 int 2977 mlx5_flow_validate_item_ipv6(const struct rte_flow_item *item, 2978 uint64_t item_flags, 2979 uint64_t last_item, 2980 uint16_t ether_type, 2981 const struct rte_flow_item_ipv6 *acc_mask, 2982 struct rte_flow_error *error) 2983 { 2984 const struct rte_flow_item_ipv6 *mask = item->mask; 2985 const struct rte_flow_item_ipv6 *spec = item->spec; 2986 const struct rte_flow_item_ipv6 nic_mask = { 2987 .hdr = { 2988 .src_addr = 2989 "\xff\xff\xff\xff\xff\xff\xff\xff" 2990 "\xff\xff\xff\xff\xff\xff\xff\xff", 2991 .dst_addr = 2992 "\xff\xff\xff\xff\xff\xff\xff\xff" 2993 "\xff\xff\xff\xff\xff\xff\xff\xff", 2994 .vtc_flow = RTE_BE32(0xffffffff), 2995 .proto = 0xff, 2996 }, 2997 }; 2998 const int tunnel = !!(item_flags & MLX5_FLOW_LAYER_TUNNEL); 2999 const uint64_t l3m = tunnel ? MLX5_FLOW_LAYER_INNER_L3 : 3000 MLX5_FLOW_LAYER_OUTER_L3; 3001 const uint64_t l4m = tunnel ? MLX5_FLOW_LAYER_INNER_L4 : 3002 MLX5_FLOW_LAYER_OUTER_L4; 3003 int ret; 3004 uint8_t next_proto = 0xFF; 3005 const uint64_t l2_vlan = (MLX5_FLOW_LAYER_L2 | 3006 MLX5_FLOW_LAYER_OUTER_VLAN | 3007 MLX5_FLOW_LAYER_INNER_VLAN); 3008 3009 if ((last_item & l2_vlan) && ether_type && 3010 ether_type != RTE_ETHER_TYPE_IPV6) 3011 return rte_flow_error_set(error, EINVAL, 3012 RTE_FLOW_ERROR_TYPE_ITEM, item, 3013 "IPv6 cannot follow L2/VLAN layer " 3014 "which ether type is not IPv6"); 3015 if (mask && mask->hdr.proto == UINT8_MAX && spec) 3016 next_proto = spec->hdr.proto; 3017 if (item_flags & MLX5_FLOW_LAYER_IPIP) { 3018 if (next_proto == IPPROTO_IPIP || next_proto == IPPROTO_IPV6) 3019 return rte_flow_error_set(error, EINVAL, 3020 RTE_FLOW_ERROR_TYPE_ITEM, 3021 item, 3022 "multiple tunnel " 3023 "not supported"); 3024 } 3025 if (next_proto == IPPROTO_HOPOPTS || 3026 next_proto == IPPROTO_ROUTING || 3027 next_proto == IPPROTO_FRAGMENT || 3028 next_proto == IPPROTO_ESP || 3029 next_proto == IPPROTO_AH || 3030 next_proto == IPPROTO_DSTOPTS) 3031 return rte_flow_error_set(error, EINVAL, 3032 RTE_FLOW_ERROR_TYPE_ITEM, item, 3033 "IPv6 proto (next header) should " 3034 "not be set as extension header"); 3035 if (item_flags & MLX5_FLOW_LAYER_IPIP) 3036 return rte_flow_error_set(error, EINVAL, 3037 RTE_FLOW_ERROR_TYPE_ITEM, item, 3038 "wrong tunnel type - IPv4 specified " 3039 "but IPv6 item provided"); 3040 if (item_flags & l3m) 3041 return rte_flow_error_set(error, ENOTSUP, 3042 RTE_FLOW_ERROR_TYPE_ITEM, item, 3043 "multiple L3 layers not supported"); 3044 else if (item_flags & l4m) 3045 return rte_flow_error_set(error, EINVAL, 3046 RTE_FLOW_ERROR_TYPE_ITEM, item, 3047 "L3 cannot follow an L4 layer."); 3048 else if ((item_flags & MLX5_FLOW_LAYER_NVGRE) && 3049 !(item_flags & MLX5_FLOW_LAYER_INNER_L2)) 3050 return rte_flow_error_set(error, EINVAL, 3051 RTE_FLOW_ERROR_TYPE_ITEM, item, 3052 "L3 cannot follow an NVGRE layer."); 3053 if (!mask) 3054 mask = &rte_flow_item_ipv6_mask; 3055 ret = mlx5_flow_item_acceptable(item, (const uint8_t *)mask, 3056 acc_mask ? (const uint8_t *)acc_mask 3057 : (const uint8_t *)&nic_mask, 3058 sizeof(struct rte_flow_item_ipv6), 3059 MLX5_ITEM_RANGE_NOT_ACCEPTED, error); 3060 if (ret < 0) 3061 return ret; 3062 return 0; 3063 } 3064 3065 /** 3066 * Validate UDP item. 3067 * 3068 * @param[in] item 3069 * Item specification. 3070 * @param[in] item_flags 3071 * Bit-fields that holds the items detected until now. 3072 * @param[in] target_protocol 3073 * The next protocol in the previous item. 3074 * @param[in] flow_mask 3075 * mlx5 flow-specific (DV, verbs, etc.) supported header fields mask. 3076 * @param[out] error 3077 * Pointer to error structure. 3078 * 3079 * @return 3080 * 0 on success, a negative errno value otherwise and rte_errno is set. 3081 */ 3082 int 3083 mlx5_flow_validate_item_udp(const struct rte_flow_item *item, 3084 uint64_t item_flags, 3085 uint8_t target_protocol, 3086 struct rte_flow_error *error) 3087 { 3088 const struct rte_flow_item_udp *mask = item->mask; 3089 const int tunnel = !!(item_flags & MLX5_FLOW_LAYER_TUNNEL); 3090 const uint64_t l3m = tunnel ? MLX5_FLOW_LAYER_INNER_L3 : 3091 MLX5_FLOW_LAYER_OUTER_L3; 3092 const uint64_t l4m = tunnel ? MLX5_FLOW_LAYER_INNER_L4 : 3093 MLX5_FLOW_LAYER_OUTER_L4; 3094 int ret; 3095 3096 if (target_protocol != 0xff && target_protocol != IPPROTO_UDP) 3097 return rte_flow_error_set(error, EINVAL, 3098 RTE_FLOW_ERROR_TYPE_ITEM, item, 3099 "protocol filtering not compatible" 3100 " with UDP layer"); 3101 if (!(item_flags & l3m)) 3102 return rte_flow_error_set(error, EINVAL, 3103 RTE_FLOW_ERROR_TYPE_ITEM, item, 3104 "L3 is mandatory to filter on L4"); 3105 if (item_flags & l4m) 3106 return rte_flow_error_set(error, EINVAL, 3107 RTE_FLOW_ERROR_TYPE_ITEM, item, 3108 "multiple L4 layers not supported"); 3109 if (!mask) 3110 mask = &rte_flow_item_udp_mask; 3111 ret = mlx5_flow_item_acceptable 3112 (item, (const uint8_t *)mask, 3113 (const uint8_t *)&rte_flow_item_udp_mask, 3114 sizeof(struct rte_flow_item_udp), MLX5_ITEM_RANGE_NOT_ACCEPTED, 3115 error); 3116 if (ret < 0) 3117 return ret; 3118 return 0; 3119 } 3120 3121 /** 3122 * Validate TCP item. 3123 * 3124 * @param[in] item 3125 * Item specification. 3126 * @param[in] item_flags 3127 * Bit-fields that holds the items detected until now. 3128 * @param[in] target_protocol 3129 * The next protocol in the previous item. 3130 * @param[out] error 3131 * Pointer to error structure. 3132 * 3133 * @return 3134 * 0 on success, a negative errno value otherwise and rte_errno is set. 3135 */ 3136 int 3137 mlx5_flow_validate_item_tcp(const struct rte_flow_item *item, 3138 uint64_t item_flags, 3139 uint8_t target_protocol, 3140 const struct rte_flow_item_tcp *flow_mask, 3141 struct rte_flow_error *error) 3142 { 3143 const struct rte_flow_item_tcp *mask = item->mask; 3144 const int tunnel = !!(item_flags & MLX5_FLOW_LAYER_TUNNEL); 3145 const uint64_t l3m = tunnel ? MLX5_FLOW_LAYER_INNER_L3 : 3146 MLX5_FLOW_LAYER_OUTER_L3; 3147 const uint64_t l4m = tunnel ? MLX5_FLOW_LAYER_INNER_L4 : 3148 MLX5_FLOW_LAYER_OUTER_L4; 3149 int ret; 3150 3151 MLX5_ASSERT(flow_mask); 3152 if (target_protocol != 0xff && target_protocol != IPPROTO_TCP) 3153 return rte_flow_error_set(error, EINVAL, 3154 RTE_FLOW_ERROR_TYPE_ITEM, item, 3155 "protocol filtering not compatible" 3156 " with TCP layer"); 3157 if (!(item_flags & l3m)) 3158 return rte_flow_error_set(error, EINVAL, 3159 RTE_FLOW_ERROR_TYPE_ITEM, item, 3160 "L3 is mandatory to filter on L4"); 3161 if (item_flags & l4m) 3162 return rte_flow_error_set(error, EINVAL, 3163 RTE_FLOW_ERROR_TYPE_ITEM, item, 3164 "multiple L4 layers not supported"); 3165 if (!mask) 3166 mask = &rte_flow_item_tcp_mask; 3167 ret = mlx5_flow_item_acceptable 3168 (item, (const uint8_t *)mask, 3169 (const uint8_t *)flow_mask, 3170 sizeof(struct rte_flow_item_tcp), MLX5_ITEM_RANGE_NOT_ACCEPTED, 3171 error); 3172 if (ret < 0) 3173 return ret; 3174 return 0; 3175 } 3176 3177 /** 3178 * Validate VXLAN item. 3179 * 3180 * @param[in] dev 3181 * Pointer to the Ethernet device structure. 3182 * @param[in] udp_dport 3183 * UDP destination port 3184 * @param[in] item 3185 * Item specification. 3186 * @param[in] item_flags 3187 * Bit-fields that holds the items detected until now. 3188 * @param root 3189 * Whether action is on root table. 3190 * @param[out] error 3191 * Pointer to error structure. 3192 * 3193 * @return 3194 * 0 on success, a negative errno value otherwise and rte_errno is set. 3195 */ 3196 int 3197 mlx5_flow_validate_item_vxlan(struct rte_eth_dev *dev, 3198 uint16_t udp_dport, 3199 const struct rte_flow_item *item, 3200 uint64_t item_flags, 3201 bool root, 3202 struct rte_flow_error *error) 3203 { 3204 const struct rte_flow_item_vxlan *spec = item->spec; 3205 const struct rte_flow_item_vxlan *mask = item->mask; 3206 int ret; 3207 struct mlx5_priv *priv = dev->data->dev_private; 3208 union vni { 3209 uint32_t vlan_id; 3210 uint8_t vni[4]; 3211 } id = { .vlan_id = 0, }; 3212 const struct rte_flow_item_vxlan nic_mask = { 3213 .hdr.vni = "\xff\xff\xff", 3214 .hdr.rsvd1 = 0xff, 3215 }; 3216 const struct rte_flow_item_vxlan *valid_mask; 3217 3218 if (item_flags & MLX5_FLOW_LAYER_TUNNEL) 3219 return rte_flow_error_set(error, ENOTSUP, 3220 RTE_FLOW_ERROR_TYPE_ITEM, item, 3221 "multiple tunnel layers not" 3222 " supported"); 3223 valid_mask = &rte_flow_item_vxlan_mask; 3224 /* 3225 * Verify only UDPv4 is present as defined in 3226 * https://tools.ietf.org/html/rfc7348 3227 */ 3228 if (!(item_flags & MLX5_FLOW_LAYER_OUTER_L4_UDP)) 3229 return rte_flow_error_set(error, EINVAL, 3230 RTE_FLOW_ERROR_TYPE_ITEM, item, 3231 "no outer UDP layer found"); 3232 if (!mask) 3233 mask = &rte_flow_item_vxlan_mask; 3234 3235 if (priv->sh->steering_format_version != 3236 MLX5_STEERING_LOGIC_FORMAT_CONNECTX_5 || 3237 !udp_dport || udp_dport == MLX5_UDP_PORT_VXLAN) { 3238 /* non-root table */ 3239 if (!root && priv->sh->misc5_cap) 3240 valid_mask = &nic_mask; 3241 /* Group zero in NIC domain */ 3242 if (!root && priv->sh->tunnel_header_0_1) 3243 valid_mask = &nic_mask; 3244 } 3245 ret = mlx5_flow_item_acceptable 3246 (item, (const uint8_t *)mask, 3247 (const uint8_t *)valid_mask, 3248 sizeof(struct rte_flow_item_vxlan), 3249 MLX5_ITEM_RANGE_NOT_ACCEPTED, error); 3250 if (ret < 0) 3251 return ret; 3252 if (spec) { 3253 memcpy(&id.vni[1], spec->hdr.vni, 3); 3254 memcpy(&id.vni[1], mask->hdr.vni, 3); 3255 } 3256 if (!(item_flags & MLX5_FLOW_LAYER_OUTER)) 3257 return rte_flow_error_set(error, ENOTSUP, 3258 RTE_FLOW_ERROR_TYPE_ITEM, item, 3259 "VXLAN tunnel must be fully defined"); 3260 return 0; 3261 } 3262 3263 /** 3264 * Validate VXLAN_GPE item. 3265 * 3266 * @param[in] item 3267 * Item specification. 3268 * @param[in] item_flags 3269 * Bit-fields that holds the items detected until now. 3270 * @param[in] priv 3271 * Pointer to the private data structure. 3272 * @param[in] target_protocol 3273 * The next protocol in the previous item. 3274 * @param[out] error 3275 * Pointer to error structure. 3276 * 3277 * @return 3278 * 0 on success, a negative errno value otherwise and rte_errno is set. 3279 */ 3280 int 3281 mlx5_flow_validate_item_vxlan_gpe(const struct rte_flow_item *item, 3282 uint64_t item_flags, 3283 struct rte_eth_dev *dev, 3284 struct rte_flow_error *error) 3285 { 3286 struct mlx5_priv *priv = dev->data->dev_private; 3287 const struct rte_flow_item_vxlan_gpe *spec = item->spec; 3288 const struct rte_flow_item_vxlan_gpe *mask = item->mask; 3289 int ret; 3290 union vni { 3291 uint32_t vlan_id; 3292 uint8_t vni[4]; 3293 } id = { .vlan_id = 0, }; 3294 3295 struct rte_flow_item_vxlan_gpe nic_mask = { 3296 .vni = "\xff\xff\xff", 3297 .protocol = 0xff, 3298 }; 3299 3300 if (!priv->sh->config.l3_vxlan_en) 3301 return rte_flow_error_set(error, ENOTSUP, 3302 RTE_FLOW_ERROR_TYPE_ITEM, item, 3303 "L3 VXLAN is not enabled by device" 3304 " parameter and/or not configured in" 3305 " firmware"); 3306 if (item_flags & MLX5_FLOW_LAYER_TUNNEL) 3307 return rte_flow_error_set(error, ENOTSUP, 3308 RTE_FLOW_ERROR_TYPE_ITEM, item, 3309 "multiple tunnel layers not" 3310 " supported"); 3311 /* 3312 * Verify only UDPv4 is present as defined in 3313 * https://tools.ietf.org/html/rfc7348 3314 */ 3315 if (!(item_flags & MLX5_FLOW_LAYER_OUTER_L4_UDP)) 3316 return rte_flow_error_set(error, EINVAL, 3317 RTE_FLOW_ERROR_TYPE_ITEM, item, 3318 "no outer UDP layer found"); 3319 if (!mask) 3320 mask = &rte_flow_item_vxlan_gpe_mask; 3321 ret = mlx5_flow_item_acceptable 3322 (item, (const uint8_t *)mask, 3323 (const uint8_t *)&nic_mask, 3324 sizeof(struct rte_flow_item_vxlan_gpe), 3325 MLX5_ITEM_RANGE_NOT_ACCEPTED, error); 3326 if (ret < 0) 3327 return ret; 3328 if (spec) { 3329 memcpy(&id.vni[1], spec->hdr.vni, 3); 3330 memcpy(&id.vni[1], mask->hdr.vni, 3); 3331 } 3332 if (!(item_flags & MLX5_FLOW_LAYER_OUTER)) 3333 return rte_flow_error_set(error, ENOTSUP, 3334 RTE_FLOW_ERROR_TYPE_ITEM, item, 3335 "VXLAN-GPE tunnel must be fully" 3336 " defined"); 3337 return 0; 3338 } 3339 /** 3340 * Validate GRE Key item. 3341 * 3342 * @param[in] item 3343 * Item specification. 3344 * @param[in] item_flags 3345 * Bit flags to mark detected items. 3346 * @param[in] gre_item 3347 * Pointer to gre_item 3348 * @param[out] error 3349 * Pointer to error structure. 3350 * 3351 * @return 3352 * 0 on success, a negative errno value otherwise and rte_errno is set. 3353 */ 3354 int 3355 mlx5_flow_validate_item_gre_key(const struct rte_flow_item *item, 3356 uint64_t item_flags, 3357 const struct rte_flow_item *gre_item, 3358 struct rte_flow_error *error) 3359 { 3360 const rte_be32_t *mask = item->mask; 3361 int ret = 0; 3362 rte_be32_t gre_key_default_mask = RTE_BE32(UINT32_MAX); 3363 const struct rte_flow_item_gre *gre_spec; 3364 const struct rte_flow_item_gre *gre_mask; 3365 3366 if (item_flags & MLX5_FLOW_LAYER_GRE_KEY) 3367 return rte_flow_error_set(error, ENOTSUP, 3368 RTE_FLOW_ERROR_TYPE_ITEM, item, 3369 "Multiple GRE key not support"); 3370 if (!(item_flags & MLX5_FLOW_LAYER_GRE)) 3371 return rte_flow_error_set(error, ENOTSUP, 3372 RTE_FLOW_ERROR_TYPE_ITEM, item, 3373 "No preceding GRE header"); 3374 if (item_flags & MLX5_FLOW_LAYER_INNER) 3375 return rte_flow_error_set(error, ENOTSUP, 3376 RTE_FLOW_ERROR_TYPE_ITEM, item, 3377 "GRE key following a wrong item"); 3378 gre_mask = gre_item->mask; 3379 if (!gre_mask) 3380 gre_mask = &rte_flow_item_gre_mask; 3381 gre_spec = gre_item->spec; 3382 if (gre_spec && (gre_mask->c_rsvd0_ver & RTE_BE16(0x2000)) && 3383 !(gre_spec->c_rsvd0_ver & RTE_BE16(0x2000))) 3384 return rte_flow_error_set(error, EINVAL, 3385 RTE_FLOW_ERROR_TYPE_ITEM, item, 3386 "Key bit must be on"); 3387 3388 if (!mask) 3389 mask = &gre_key_default_mask; 3390 ret = mlx5_flow_item_acceptable 3391 (item, (const uint8_t *)mask, 3392 (const uint8_t *)&gre_key_default_mask, 3393 sizeof(rte_be32_t), MLX5_ITEM_RANGE_NOT_ACCEPTED, error); 3394 return ret; 3395 } 3396 3397 /** 3398 * Validate GRE optional item. 3399 * 3400 * @param[in] dev 3401 * Pointer to the Ethernet device structure. 3402 * @param[in] item 3403 * Item specification. 3404 * @param[in] item_flags 3405 * Bit flags to mark detected items. 3406 * @param[in] attr 3407 * Flow rule attributes. 3408 * @param[in] gre_item 3409 * Pointer to gre_item 3410 * @param[out] error 3411 * Pointer to error structure. 3412 * 3413 * @return 3414 * 0 on success, a negative errno value otherwise and rte_errno is set. 3415 */ 3416 int 3417 mlx5_flow_validate_item_gre_option(struct rte_eth_dev *dev, 3418 const struct rte_flow_item *item, 3419 uint64_t item_flags, 3420 const struct rte_flow_attr *attr, 3421 const struct rte_flow_item *gre_item, 3422 struct rte_flow_error *error) 3423 { 3424 const struct rte_flow_item_gre *gre_spec = gre_item->spec; 3425 const struct rte_flow_item_gre *gre_mask = gre_item->mask; 3426 const struct rte_flow_item_gre_opt *spec = item->spec; 3427 const struct rte_flow_item_gre_opt *mask = item->mask; 3428 struct mlx5_priv *priv = dev->data->dev_private; 3429 int ret = 0; 3430 struct rte_flow_item_gre_opt nic_mask = { 3431 .checksum_rsvd = { 3432 .checksum = RTE_BE16(UINT16_MAX), 3433 .reserved1 = 0x0, 3434 }, 3435 .key = { 3436 .key = RTE_BE32(UINT32_MAX), 3437 }, 3438 .sequence = { 3439 .sequence = RTE_BE32(UINT32_MAX), 3440 }, 3441 }; 3442 3443 if (!(item_flags & MLX5_FLOW_LAYER_GRE)) 3444 return rte_flow_error_set(error, ENOTSUP, 3445 RTE_FLOW_ERROR_TYPE_ITEM, item, 3446 "No preceding GRE header"); 3447 if (item_flags & MLX5_FLOW_LAYER_INNER) 3448 return rte_flow_error_set(error, ENOTSUP, 3449 RTE_FLOW_ERROR_TYPE_ITEM, item, 3450 "GRE option following a wrong item"); 3451 if (!spec || !mask) 3452 return rte_flow_error_set(error, EINVAL, 3453 RTE_FLOW_ERROR_TYPE_ITEM, item, 3454 "At least one field gre_option(checksum/key/sequence) must be specified"); 3455 if (!gre_mask) 3456 gre_mask = &rte_flow_item_gre_mask; 3457 if (mask->checksum_rsvd.checksum) 3458 if (gre_spec && (gre_mask->c_rsvd0_ver & RTE_BE16(0x8000)) && 3459 !(gre_spec->c_rsvd0_ver & RTE_BE16(0x8000))) 3460 return rte_flow_error_set(error, EINVAL, 3461 RTE_FLOW_ERROR_TYPE_ITEM, 3462 item, 3463 "Checksum bit must be on"); 3464 if (mask->key.key) 3465 if (gre_spec && (gre_mask->c_rsvd0_ver & RTE_BE16(0x2000)) && 3466 !(gre_spec->c_rsvd0_ver & RTE_BE16(0x2000))) 3467 return rte_flow_error_set(error, EINVAL, 3468 RTE_FLOW_ERROR_TYPE_ITEM, 3469 item, "Key bit must be on"); 3470 if (mask->sequence.sequence) 3471 if (gre_spec && (gre_mask->c_rsvd0_ver & RTE_BE16(0x1000)) && 3472 !(gre_spec->c_rsvd0_ver & RTE_BE16(0x1000))) 3473 return rte_flow_error_set(error, EINVAL, 3474 RTE_FLOW_ERROR_TYPE_ITEM, 3475 item, 3476 "Sequence bit must be on"); 3477 if (mask->checksum_rsvd.checksum || mask->sequence.sequence) { 3478 if (priv->sh->steering_format_version == 3479 MLX5_STEERING_LOGIC_FORMAT_CONNECTX_5 || 3480 ((attr->group || (attr->transfer && priv->fdb_def_rule)) && 3481 !priv->sh->misc5_cap) || 3482 (!(priv->sh->tunnel_header_0_1 && 3483 priv->sh->tunnel_header_2_3) && 3484 !attr->group && (!attr->transfer || !priv->fdb_def_rule))) 3485 return rte_flow_error_set(error, EINVAL, 3486 RTE_FLOW_ERROR_TYPE_ITEM, 3487 item, 3488 "Checksum/Sequence not supported"); 3489 } 3490 ret = mlx5_flow_item_acceptable 3491 (item, (const uint8_t *)mask, 3492 (const uint8_t *)&nic_mask, 3493 sizeof(struct rte_flow_item_gre_opt), 3494 MLX5_ITEM_RANGE_NOT_ACCEPTED, error); 3495 return ret; 3496 } 3497 3498 /** 3499 * Validate GRE item. 3500 * 3501 * @param[in] item 3502 * Item specification. 3503 * @param[in] item_flags 3504 * Bit flags to mark detected items. 3505 * @param[in] target_protocol 3506 * The next protocol in the previous item. 3507 * @param[out] error 3508 * Pointer to error structure. 3509 * 3510 * @return 3511 * 0 on success, a negative errno value otherwise and rte_errno is set. 3512 */ 3513 int 3514 mlx5_flow_validate_item_gre(const struct rte_flow_item *item, 3515 uint64_t item_flags, 3516 uint8_t target_protocol, 3517 struct rte_flow_error *error) 3518 { 3519 const struct rte_flow_item_gre *spec __rte_unused = item->spec; 3520 const struct rte_flow_item_gre *mask = item->mask; 3521 int ret; 3522 const struct rte_flow_item_gre nic_mask = { 3523 .c_rsvd0_ver = RTE_BE16(0xB000), 3524 .protocol = RTE_BE16(UINT16_MAX), 3525 }; 3526 3527 if (target_protocol != 0xff && target_protocol != IPPROTO_GRE) 3528 return rte_flow_error_set(error, EINVAL, 3529 RTE_FLOW_ERROR_TYPE_ITEM, item, 3530 "protocol filtering not compatible" 3531 " with this GRE layer"); 3532 if (item_flags & MLX5_FLOW_LAYER_TUNNEL) 3533 return rte_flow_error_set(error, ENOTSUP, 3534 RTE_FLOW_ERROR_TYPE_ITEM, item, 3535 "multiple tunnel layers not" 3536 " supported"); 3537 if (!(item_flags & MLX5_FLOW_LAYER_OUTER_L3)) 3538 return rte_flow_error_set(error, ENOTSUP, 3539 RTE_FLOW_ERROR_TYPE_ITEM, item, 3540 "L3 Layer is missing"); 3541 if (!mask) 3542 mask = &rte_flow_item_gre_mask; 3543 ret = mlx5_flow_item_acceptable 3544 (item, (const uint8_t *)mask, 3545 (const uint8_t *)&nic_mask, 3546 sizeof(struct rte_flow_item_gre), MLX5_ITEM_RANGE_NOT_ACCEPTED, 3547 error); 3548 if (ret < 0) 3549 return ret; 3550 #ifndef HAVE_MLX5DV_DR 3551 #ifndef HAVE_IBV_DEVICE_MPLS_SUPPORT 3552 if (spec && (spec->protocol & mask->protocol)) 3553 return rte_flow_error_set(error, ENOTSUP, 3554 RTE_FLOW_ERROR_TYPE_ITEM, item, 3555 "without MPLS support the" 3556 " specification cannot be used for" 3557 " filtering"); 3558 #endif 3559 #endif 3560 return 0; 3561 } 3562 3563 /** 3564 * Validate Geneve item. 3565 * 3566 * @param[in] item 3567 * Item specification. 3568 * @param[in] itemFlags 3569 * Bit-fields that holds the items detected until now. 3570 * @param[in] enPriv 3571 * Pointer to the private data structure. 3572 * @param[out] error 3573 * Pointer to error structure. 3574 * 3575 * @return 3576 * 0 on success, a negative errno value otherwise and rte_errno is set. 3577 */ 3578 3579 int 3580 mlx5_flow_validate_item_geneve(const struct rte_flow_item *item, 3581 uint64_t item_flags, 3582 struct rte_eth_dev *dev, 3583 struct rte_flow_error *error) 3584 { 3585 struct mlx5_priv *priv = dev->data->dev_private; 3586 const struct rte_flow_item_geneve *spec = item->spec; 3587 const struct rte_flow_item_geneve *mask = item->mask; 3588 int ret; 3589 uint16_t gbhdr; 3590 uint8_t opt_len = priv->sh->cdev->config.hca_attr.geneve_max_opt_len ? 3591 MLX5_GENEVE_OPT_LEN_1 : MLX5_GENEVE_OPT_LEN_0; 3592 const struct rte_flow_item_geneve nic_mask = { 3593 .ver_opt_len_o_c_rsvd0 = RTE_BE16(0x3f80), 3594 .vni = "\xff\xff\xff", 3595 .protocol = RTE_BE16(UINT16_MAX), 3596 }; 3597 3598 if (!priv->sh->cdev->config.hca_attr.tunnel_stateless_geneve_rx) 3599 return rte_flow_error_set(error, ENOTSUP, 3600 RTE_FLOW_ERROR_TYPE_ITEM, item, 3601 "L3 Geneve is not enabled by device" 3602 " parameter and/or not configured in" 3603 " firmware"); 3604 if (item_flags & MLX5_FLOW_LAYER_TUNNEL) 3605 return rte_flow_error_set(error, ENOTSUP, 3606 RTE_FLOW_ERROR_TYPE_ITEM, item, 3607 "multiple tunnel layers not" 3608 " supported"); 3609 /* 3610 * Verify only UDPv4 is present as defined in 3611 * https://tools.ietf.org/html/rfc7348 3612 */ 3613 if (!(item_flags & MLX5_FLOW_LAYER_OUTER_L4_UDP)) 3614 return rte_flow_error_set(error, EINVAL, 3615 RTE_FLOW_ERROR_TYPE_ITEM, item, 3616 "no outer UDP layer found"); 3617 if (!mask) 3618 mask = &rte_flow_item_geneve_mask; 3619 ret = mlx5_flow_item_acceptable 3620 (item, (const uint8_t *)mask, 3621 (const uint8_t *)&nic_mask, 3622 sizeof(struct rte_flow_item_geneve), 3623 MLX5_ITEM_RANGE_NOT_ACCEPTED, error); 3624 if (ret) 3625 return ret; 3626 if (spec) { 3627 gbhdr = rte_be_to_cpu_16(spec->ver_opt_len_o_c_rsvd0); 3628 if (MLX5_GENEVE_VER_VAL(gbhdr) || 3629 MLX5_GENEVE_CRITO_VAL(gbhdr) || 3630 MLX5_GENEVE_RSVD_VAL(gbhdr) || spec->rsvd1) 3631 return rte_flow_error_set(error, ENOTSUP, 3632 RTE_FLOW_ERROR_TYPE_ITEM, 3633 item, 3634 "Geneve protocol unsupported" 3635 " fields are being used"); 3636 if (MLX5_GENEVE_OPTLEN_VAL(gbhdr) > opt_len) 3637 return rte_flow_error_set 3638 (error, ENOTSUP, 3639 RTE_FLOW_ERROR_TYPE_ITEM, 3640 item, 3641 "Unsupported Geneve options length"); 3642 } 3643 if (!(item_flags & MLX5_FLOW_LAYER_OUTER)) 3644 return rte_flow_error_set 3645 (error, ENOTSUP, 3646 RTE_FLOW_ERROR_TYPE_ITEM, item, 3647 "Geneve tunnel must be fully defined"); 3648 return 0; 3649 } 3650 3651 /** 3652 * Validate Geneve TLV option item. 3653 * 3654 * @param[in] item 3655 * Item specification. 3656 * @param[in] last_item 3657 * Previous validated item in the pattern items. 3658 * @param[in] geneve_item 3659 * Previous GENEVE item specification. 3660 * @param[in] dev 3661 * Pointer to the rte_eth_dev structure. 3662 * @param[out] error 3663 * Pointer to error structure. 3664 * 3665 * @return 3666 * 0 on success, a negative errno value otherwise and rte_errno is set. 3667 */ 3668 int 3669 mlx5_flow_validate_item_geneve_opt(const struct rte_flow_item *item, 3670 uint64_t last_item, 3671 const struct rte_flow_item *geneve_item, 3672 struct rte_eth_dev *dev, 3673 struct rte_flow_error *error) 3674 { 3675 struct mlx5_priv *priv = dev->data->dev_private; 3676 struct mlx5_dev_ctx_shared *sh = priv->sh; 3677 struct mlx5_geneve_tlv_option_resource *geneve_opt_resource; 3678 struct mlx5_hca_attr *hca_attr = &sh->cdev->config.hca_attr; 3679 uint8_t data_max_supported = 3680 hca_attr->max_geneve_tlv_option_data_len * 4; 3681 const struct rte_flow_item_geneve *geneve_spec; 3682 const struct rte_flow_item_geneve *geneve_mask; 3683 const struct rte_flow_item_geneve_opt *spec = item->spec; 3684 const struct rte_flow_item_geneve_opt *mask = item->mask; 3685 unsigned int i; 3686 unsigned int data_len; 3687 uint8_t tlv_option_len; 3688 uint16_t optlen_m, optlen_v; 3689 const struct rte_flow_item_geneve_opt full_mask = { 3690 .option_class = RTE_BE16(0xffff), 3691 .option_type = 0xff, 3692 .option_len = 0x1f, 3693 }; 3694 3695 if (!mask) 3696 mask = &rte_flow_item_geneve_opt_mask; 3697 if (!spec) 3698 return rte_flow_error_set 3699 (error, ENOTSUP, RTE_FLOW_ERROR_TYPE_ITEM, item, 3700 "Geneve TLV opt class/type/length must be specified"); 3701 if ((uint32_t)spec->option_len > MLX5_GENEVE_OPTLEN_MASK) 3702 return rte_flow_error_set 3703 (error, ENOTSUP, RTE_FLOW_ERROR_TYPE_ITEM, item, 3704 "Geneve TLV opt length exceeds the limit (31)"); 3705 /* Check if class type and length masks are full. */ 3706 if (full_mask.option_class != mask->option_class || 3707 full_mask.option_type != mask->option_type || 3708 full_mask.option_len != (mask->option_len & full_mask.option_len)) 3709 return rte_flow_error_set 3710 (error, ENOTSUP, RTE_FLOW_ERROR_TYPE_ITEM, item, 3711 "Geneve TLV opt class/type/length masks must be full"); 3712 /* Check if length is supported */ 3713 if ((uint32_t)spec->option_len > 3714 hca_attr->max_geneve_tlv_option_data_len) 3715 return rte_flow_error_set 3716 (error, ENOTSUP, RTE_FLOW_ERROR_TYPE_ITEM, item, 3717 "Geneve TLV opt length not supported"); 3718 if (hca_attr->max_geneve_tlv_options > 1) 3719 DRV_LOG(DEBUG, 3720 "max_geneve_tlv_options supports more than 1 option"); 3721 /* Check GENEVE item preceding. */ 3722 if (!geneve_item || !(last_item & MLX5_FLOW_LAYER_GENEVE)) 3723 return rte_flow_error_set 3724 (error, ENOTSUP, RTE_FLOW_ERROR_TYPE_ITEM, item, 3725 "Geneve opt item must be preceded with Geneve item"); 3726 geneve_spec = geneve_item->spec; 3727 geneve_mask = geneve_item->mask ? geneve_item->mask : 3728 &rte_flow_item_geneve_mask; 3729 /* Check if GENEVE TLV option size doesn't exceed option length */ 3730 if (geneve_spec && (geneve_mask->ver_opt_len_o_c_rsvd0 || 3731 geneve_spec->ver_opt_len_o_c_rsvd0)) { 3732 tlv_option_len = spec->option_len & mask->option_len; 3733 optlen_v = rte_be_to_cpu_16(geneve_spec->ver_opt_len_o_c_rsvd0); 3734 optlen_v = MLX5_GENEVE_OPTLEN_VAL(optlen_v); 3735 optlen_m = rte_be_to_cpu_16(geneve_mask->ver_opt_len_o_c_rsvd0); 3736 optlen_m = MLX5_GENEVE_OPTLEN_VAL(optlen_m); 3737 if ((optlen_v & optlen_m) <= tlv_option_len) 3738 return rte_flow_error_set 3739 (error, ENOTSUP, RTE_FLOW_ERROR_TYPE_ITEM, item, 3740 "GENEVE TLV option length exceeds optlen"); 3741 } 3742 /* Check if length is 0 or data is 0. */ 3743 if (spec->data == NULL || spec->option_len == 0) 3744 return rte_flow_error_set 3745 (error, ENOTSUP, RTE_FLOW_ERROR_TYPE_ITEM, item, 3746 "Geneve TLV opt with zero data/length not supported"); 3747 /* Check not all data & mask are 0. */ 3748 data_len = spec->option_len * 4; 3749 if (mask->data == NULL) { 3750 for (i = 0; i < data_len; i++) 3751 if (spec->data[i]) 3752 break; 3753 if (i == data_len) 3754 return rte_flow_error_set(error, ENOTSUP, 3755 RTE_FLOW_ERROR_TYPE_ITEM, item, 3756 "Can't match on Geneve option data 0"); 3757 } else { 3758 for (i = 0; i < data_len; i++) 3759 if (spec->data[i] & mask->data[i]) 3760 break; 3761 if (i == data_len) 3762 return rte_flow_error_set(error, ENOTSUP, 3763 RTE_FLOW_ERROR_TYPE_ITEM, item, 3764 "Can't match on Geneve option data and mask 0"); 3765 /* Check data mask supported. */ 3766 for (i = data_max_supported; i < data_len ; i++) 3767 if (mask->data[i]) 3768 return rte_flow_error_set(error, ENOTSUP, 3769 RTE_FLOW_ERROR_TYPE_ITEM, item, 3770 "Data mask is of unsupported size"); 3771 } 3772 /* Check GENEVE option is supported in NIC. */ 3773 if (!hca_attr->geneve_tlv_opt) 3774 return rte_flow_error_set 3775 (error, ENOTSUP, RTE_FLOW_ERROR_TYPE_ITEM, item, 3776 "Geneve TLV opt not supported"); 3777 /* Check if we already have geneve option with different type/class. */ 3778 rte_spinlock_lock(&sh->geneve_tlv_opt_sl); 3779 geneve_opt_resource = sh->geneve_tlv_option_resource; 3780 if (geneve_opt_resource != NULL) 3781 if (geneve_opt_resource->option_class != spec->option_class || 3782 geneve_opt_resource->option_type != spec->option_type || 3783 geneve_opt_resource->length != spec->option_len) { 3784 rte_spinlock_unlock(&sh->geneve_tlv_opt_sl); 3785 return rte_flow_error_set(error, ENOTSUP, 3786 RTE_FLOW_ERROR_TYPE_ITEM, item, 3787 "Only one Geneve TLV option supported"); 3788 } 3789 rte_spinlock_unlock(&sh->geneve_tlv_opt_sl); 3790 return 0; 3791 } 3792 3793 /** 3794 * Validate MPLS item. 3795 * 3796 * @param[in] dev 3797 * Pointer to the rte_eth_dev structure. 3798 * @param[in] item 3799 * Item specification. 3800 * @param[in] item_flags 3801 * Bit-fields that holds the items detected until now. 3802 * @param[in] prev_layer 3803 * The protocol layer indicated in previous item. 3804 * @param[out] error 3805 * Pointer to error structure. 3806 * 3807 * @return 3808 * 0 on success, a negative errno value otherwise and rte_errno is set. 3809 */ 3810 int 3811 mlx5_flow_validate_item_mpls(struct rte_eth_dev *dev __rte_unused, 3812 const struct rte_flow_item *item __rte_unused, 3813 uint64_t item_flags __rte_unused, 3814 uint64_t prev_layer __rte_unused, 3815 struct rte_flow_error *error) 3816 { 3817 #ifdef HAVE_IBV_DEVICE_MPLS_SUPPORT 3818 const struct rte_flow_item_mpls *mask = item->mask; 3819 struct mlx5_priv *priv = dev->data->dev_private; 3820 int ret; 3821 3822 if (!priv->sh->dev_cap.mpls_en) 3823 return rte_flow_error_set(error, ENOTSUP, 3824 RTE_FLOW_ERROR_TYPE_ITEM, item, 3825 "MPLS not supported or" 3826 " disabled in firmware" 3827 " configuration."); 3828 /* MPLS over UDP, GRE is allowed */ 3829 if (!(prev_layer & (MLX5_FLOW_LAYER_OUTER_L4_UDP | 3830 MLX5_FLOW_LAYER_GRE | 3831 MLX5_FLOW_LAYER_GRE_KEY))) 3832 return rte_flow_error_set(error, EINVAL, 3833 RTE_FLOW_ERROR_TYPE_ITEM, item, 3834 "protocol filtering not compatible" 3835 " with MPLS layer"); 3836 /* Multi-tunnel isn't allowed but MPLS over GRE is an exception. */ 3837 if ((item_flags & MLX5_FLOW_LAYER_TUNNEL) && 3838 !(item_flags & MLX5_FLOW_LAYER_GRE)) 3839 return rte_flow_error_set(error, ENOTSUP, 3840 RTE_FLOW_ERROR_TYPE_ITEM, item, 3841 "multiple tunnel layers not" 3842 " supported"); 3843 if (!mask) 3844 mask = &rte_flow_item_mpls_mask; 3845 ret = mlx5_flow_item_acceptable 3846 (item, (const uint8_t *)mask, 3847 (const uint8_t *)&rte_flow_item_mpls_mask, 3848 sizeof(struct rte_flow_item_mpls), 3849 MLX5_ITEM_RANGE_NOT_ACCEPTED, error); 3850 if (ret < 0) 3851 return ret; 3852 return 0; 3853 #else 3854 return rte_flow_error_set(error, ENOTSUP, 3855 RTE_FLOW_ERROR_TYPE_ITEM, item, 3856 "MPLS is not supported by Verbs, please" 3857 " update."); 3858 #endif 3859 } 3860 3861 /** 3862 * Validate NVGRE item. 3863 * 3864 * @param[in] item 3865 * Item specification. 3866 * @param[in] item_flags 3867 * Bit flags to mark detected items. 3868 * @param[in] target_protocol 3869 * The next protocol in the previous item. 3870 * @param[out] error 3871 * Pointer to error structure. 3872 * 3873 * @return 3874 * 0 on success, a negative errno value otherwise and rte_errno is set. 3875 */ 3876 int 3877 mlx5_flow_validate_item_nvgre(const struct rte_flow_item *item, 3878 uint64_t item_flags, 3879 uint8_t target_protocol, 3880 struct rte_flow_error *error) 3881 { 3882 const struct rte_flow_item_nvgre *mask = item->mask; 3883 int ret; 3884 3885 if (target_protocol != 0xff && target_protocol != IPPROTO_GRE) 3886 return rte_flow_error_set(error, EINVAL, 3887 RTE_FLOW_ERROR_TYPE_ITEM, item, 3888 "protocol filtering not compatible" 3889 " with this GRE layer"); 3890 if (item_flags & MLX5_FLOW_LAYER_TUNNEL) 3891 return rte_flow_error_set(error, ENOTSUP, 3892 RTE_FLOW_ERROR_TYPE_ITEM, item, 3893 "multiple tunnel layers not" 3894 " supported"); 3895 if (!(item_flags & MLX5_FLOW_LAYER_OUTER_L3)) 3896 return rte_flow_error_set(error, ENOTSUP, 3897 RTE_FLOW_ERROR_TYPE_ITEM, item, 3898 "L3 Layer is missing"); 3899 if (!mask) 3900 mask = &rte_flow_item_nvgre_mask; 3901 ret = mlx5_flow_item_acceptable 3902 (item, (const uint8_t *)mask, 3903 (const uint8_t *)&rte_flow_item_nvgre_mask, 3904 sizeof(struct rte_flow_item_nvgre), 3905 MLX5_ITEM_RANGE_NOT_ACCEPTED, error); 3906 if (ret < 0) 3907 return ret; 3908 return 0; 3909 } 3910 3911 /** 3912 * Validate eCPRI item. 3913 * 3914 * @param[in] item 3915 * Item specification. 3916 * @param[in] item_flags 3917 * Bit-fields that holds the items detected until now. 3918 * @param[in] last_item 3919 * Previous validated item in the pattern items. 3920 * @param[in] ether_type 3921 * Type in the ethernet layer header (including dot1q). 3922 * @param[in] acc_mask 3923 * Acceptable mask, if NULL default internal default mask 3924 * will be used to check whether item fields are supported. 3925 * @param[out] error 3926 * Pointer to error structure. 3927 * 3928 * @return 3929 * 0 on success, a negative errno value otherwise and rte_errno is set. 3930 */ 3931 int 3932 mlx5_flow_validate_item_ecpri(const struct rte_flow_item *item, 3933 uint64_t item_flags, 3934 uint64_t last_item, 3935 uint16_t ether_type, 3936 const struct rte_flow_item_ecpri *acc_mask, 3937 struct rte_flow_error *error) 3938 { 3939 const struct rte_flow_item_ecpri *mask = item->mask; 3940 const struct rte_flow_item_ecpri nic_mask = { 3941 .hdr = { 3942 .common = { 3943 .u32 = 3944 RTE_BE32(((const struct rte_ecpri_common_hdr) { 3945 .type = 0xFF, 3946 }).u32), 3947 }, 3948 .dummy[0] = 0xFFFFFFFF, 3949 }, 3950 }; 3951 const uint64_t outer_l2_vlan = (MLX5_FLOW_LAYER_OUTER_L2 | 3952 MLX5_FLOW_LAYER_OUTER_VLAN); 3953 struct rte_flow_item_ecpri mask_lo; 3954 3955 if (!(last_item & outer_l2_vlan) && 3956 last_item != MLX5_FLOW_LAYER_OUTER_L4_UDP) 3957 return rte_flow_error_set(error, EINVAL, 3958 RTE_FLOW_ERROR_TYPE_ITEM, item, 3959 "eCPRI can only follow L2/VLAN layer or UDP layer"); 3960 if ((last_item & outer_l2_vlan) && ether_type && 3961 ether_type != RTE_ETHER_TYPE_ECPRI) 3962 return rte_flow_error_set(error, EINVAL, 3963 RTE_FLOW_ERROR_TYPE_ITEM, item, 3964 "eCPRI cannot follow L2/VLAN layer which ether type is not 0xAEFE"); 3965 if (item_flags & MLX5_FLOW_LAYER_TUNNEL) 3966 return rte_flow_error_set(error, EINVAL, 3967 RTE_FLOW_ERROR_TYPE_ITEM, item, 3968 "eCPRI with tunnel is not supported right now"); 3969 if (item_flags & MLX5_FLOW_LAYER_OUTER_L3) 3970 return rte_flow_error_set(error, ENOTSUP, 3971 RTE_FLOW_ERROR_TYPE_ITEM, item, 3972 "multiple L3 layers not supported"); 3973 else if (item_flags & MLX5_FLOW_LAYER_OUTER_L4_TCP) 3974 return rte_flow_error_set(error, EINVAL, 3975 RTE_FLOW_ERROR_TYPE_ITEM, item, 3976 "eCPRI cannot coexist with a TCP layer"); 3977 /* In specification, eCPRI could be over UDP layer. */ 3978 else if (item_flags & MLX5_FLOW_LAYER_OUTER_L4_UDP) 3979 return rte_flow_error_set(error, EINVAL, 3980 RTE_FLOW_ERROR_TYPE_ITEM, item, 3981 "eCPRI over UDP layer is not yet supported right now"); 3982 /* Mask for type field in common header could be zero. */ 3983 if (!mask) 3984 mask = &rte_flow_item_ecpri_mask; 3985 mask_lo.hdr.common.u32 = rte_be_to_cpu_32(mask->hdr.common.u32); 3986 /* Input mask is in big-endian format. */ 3987 if (mask_lo.hdr.common.type != 0 && mask_lo.hdr.common.type != 0xff) 3988 return rte_flow_error_set(error, EINVAL, 3989 RTE_FLOW_ERROR_TYPE_ITEM_MASK, mask, 3990 "partial mask is not supported for protocol"); 3991 else if (mask_lo.hdr.common.type == 0 && mask->hdr.dummy[0] != 0) 3992 return rte_flow_error_set(error, EINVAL, 3993 RTE_FLOW_ERROR_TYPE_ITEM_MASK, mask, 3994 "message header mask must be after a type mask"); 3995 return mlx5_flow_item_acceptable(item, (const uint8_t *)mask, 3996 acc_mask ? (const uint8_t *)acc_mask 3997 : (const uint8_t *)&nic_mask, 3998 sizeof(struct rte_flow_item_ecpri), 3999 MLX5_ITEM_RANGE_NOT_ACCEPTED, error); 4000 } 4001 4002 /** 4003 * Validate the NSH item. 4004 * 4005 * @param[in] dev 4006 * Pointer to Ethernet device on which flow rule is being created on. 4007 * @param[out] error 4008 * Pointer to error structure. 4009 * 4010 * @return 4011 * 0 on success, a negative errno value otherwise and rte_errno is set. 4012 */ 4013 int 4014 mlx5_flow_validate_item_nsh(struct rte_eth_dev *dev, 4015 const struct rte_flow_item *item, 4016 struct rte_flow_error *error) 4017 { 4018 struct mlx5_priv *priv = dev->data->dev_private; 4019 4020 if (item->mask) { 4021 return rte_flow_error_set(error, ENOTSUP, 4022 RTE_FLOW_ERROR_TYPE_ITEM, item, 4023 "NSH fields matching is not supported"); 4024 } 4025 4026 if (!priv->sh->config.dv_flow_en) { 4027 return rte_flow_error_set(error, ENOTSUP, 4028 RTE_FLOW_ERROR_TYPE_UNSPECIFIED, 4029 NULL, "NSH support requires DV flow interface"); 4030 } 4031 4032 if (!priv->sh->cdev->config.hca_attr.tunnel_stateless_vxlan_gpe_nsh) { 4033 return rte_flow_error_set(error, ENOTSUP, 4034 RTE_FLOW_ERROR_TYPE_ITEM, item, 4035 "Current FW does not support matching on NSH"); 4036 } 4037 4038 return 0; 4039 } 4040 4041 static int 4042 flow_null_validate(struct rte_eth_dev *dev __rte_unused, 4043 const struct rte_flow_attr *attr __rte_unused, 4044 const struct rte_flow_item items[] __rte_unused, 4045 const struct rte_flow_action actions[] __rte_unused, 4046 bool external __rte_unused, 4047 int hairpin __rte_unused, 4048 struct rte_flow_error *error) 4049 { 4050 return rte_flow_error_set(error, ENOTSUP, 4051 RTE_FLOW_ERROR_TYPE_UNSPECIFIED, NULL, NULL); 4052 } 4053 4054 static struct mlx5_flow * 4055 flow_null_prepare(struct rte_eth_dev *dev __rte_unused, 4056 const struct rte_flow_attr *attr __rte_unused, 4057 const struct rte_flow_item items[] __rte_unused, 4058 const struct rte_flow_action actions[] __rte_unused, 4059 struct rte_flow_error *error) 4060 { 4061 rte_flow_error_set(error, ENOTSUP, 4062 RTE_FLOW_ERROR_TYPE_UNSPECIFIED, NULL, NULL); 4063 return NULL; 4064 } 4065 4066 static int 4067 flow_null_translate(struct rte_eth_dev *dev __rte_unused, 4068 struct mlx5_flow *dev_flow __rte_unused, 4069 const struct rte_flow_attr *attr __rte_unused, 4070 const struct rte_flow_item items[] __rte_unused, 4071 const struct rte_flow_action actions[] __rte_unused, 4072 struct rte_flow_error *error) 4073 { 4074 return rte_flow_error_set(error, ENOTSUP, 4075 RTE_FLOW_ERROR_TYPE_UNSPECIFIED, NULL, NULL); 4076 } 4077 4078 static int 4079 flow_null_apply(struct rte_eth_dev *dev __rte_unused, 4080 struct rte_flow *flow __rte_unused, 4081 struct rte_flow_error *error) 4082 { 4083 return rte_flow_error_set(error, ENOTSUP, 4084 RTE_FLOW_ERROR_TYPE_UNSPECIFIED, NULL, NULL); 4085 } 4086 4087 static void 4088 flow_null_remove(struct rte_eth_dev *dev __rte_unused, 4089 struct rte_flow *flow __rte_unused) 4090 { 4091 } 4092 4093 static void 4094 flow_null_destroy(struct rte_eth_dev *dev __rte_unused, 4095 struct rte_flow *flow __rte_unused) 4096 { 4097 } 4098 4099 static int 4100 flow_null_query(struct rte_eth_dev *dev __rte_unused, 4101 struct rte_flow *flow __rte_unused, 4102 const struct rte_flow_action *actions __rte_unused, 4103 void *data __rte_unused, 4104 struct rte_flow_error *error) 4105 { 4106 return rte_flow_error_set(error, ENOTSUP, 4107 RTE_FLOW_ERROR_TYPE_UNSPECIFIED, NULL, NULL); 4108 } 4109 4110 static int 4111 flow_null_sync_domain(struct rte_eth_dev *dev __rte_unused, 4112 uint32_t domains __rte_unused, 4113 uint32_t flags __rte_unused) 4114 { 4115 return 0; 4116 } 4117 4118 int 4119 flow_null_get_aged_flows(struct rte_eth_dev *dev, 4120 void **context __rte_unused, 4121 uint32_t nb_contexts __rte_unused, 4122 struct rte_flow_error *error __rte_unused) 4123 { 4124 DRV_LOG(ERR, "port %u get aged flows is not supported.", 4125 dev->data->port_id); 4126 return -ENOTSUP; 4127 } 4128 4129 uint32_t 4130 flow_null_counter_allocate(struct rte_eth_dev *dev) 4131 { 4132 DRV_LOG(ERR, "port %u counter allocate is not supported.", 4133 dev->data->port_id); 4134 return 0; 4135 } 4136 4137 void 4138 flow_null_counter_free(struct rte_eth_dev *dev, 4139 uint32_t counter __rte_unused) 4140 { 4141 DRV_LOG(ERR, "port %u counter free is not supported.", 4142 dev->data->port_id); 4143 } 4144 4145 int 4146 flow_null_counter_query(struct rte_eth_dev *dev, 4147 uint32_t counter __rte_unused, 4148 bool clear __rte_unused, 4149 uint64_t *pkts __rte_unused, 4150 uint64_t *bytes __rte_unused, 4151 void **action __rte_unused) 4152 { 4153 DRV_LOG(ERR, "port %u counter query is not supported.", 4154 dev->data->port_id); 4155 return -ENOTSUP; 4156 } 4157 4158 /* Void driver to protect from null pointer reference. */ 4159 const struct mlx5_flow_driver_ops mlx5_flow_null_drv_ops = { 4160 .validate = flow_null_validate, 4161 .prepare = flow_null_prepare, 4162 .translate = flow_null_translate, 4163 .apply = flow_null_apply, 4164 .remove = flow_null_remove, 4165 .destroy = flow_null_destroy, 4166 .query = flow_null_query, 4167 .sync_domain = flow_null_sync_domain, 4168 .get_aged_flows = flow_null_get_aged_flows, 4169 .counter_alloc = flow_null_counter_allocate, 4170 .counter_free = flow_null_counter_free, 4171 .counter_query = flow_null_counter_query 4172 }; 4173 4174 /** 4175 * Select flow driver type according to flow attributes and device 4176 * configuration. 4177 * 4178 * @param[in] dev 4179 * Pointer to the dev structure. 4180 * @param[in] attr 4181 * Pointer to the flow attributes. 4182 * 4183 * @return 4184 * flow driver type, MLX5_FLOW_TYPE_MAX otherwise. 4185 */ 4186 static enum mlx5_flow_drv_type 4187 flow_get_drv_type(struct rte_eth_dev *dev, const struct rte_flow_attr *attr) 4188 { 4189 struct mlx5_priv *priv = dev->data->dev_private; 4190 /* The OS can determine first a specific flow type (DV, VERBS) */ 4191 enum mlx5_flow_drv_type type = mlx5_flow_os_get_type(); 4192 4193 if (type != MLX5_FLOW_TYPE_MAX) 4194 return type; 4195 /* 4196 * Currently when dv_flow_en == 2, only HW steering engine is 4197 * supported. New engines can also be chosen here if ready. 4198 */ 4199 if (priv->sh->config.dv_flow_en == 2) 4200 return MLX5_FLOW_TYPE_HW; 4201 if (!attr) 4202 return MLX5_FLOW_TYPE_MIN; 4203 /* If no OS specific type - continue with DV/VERBS selection */ 4204 if (attr->transfer && priv->sh->config.dv_esw_en) 4205 type = MLX5_FLOW_TYPE_DV; 4206 if (!attr->transfer) 4207 type = priv->sh->config.dv_flow_en ? MLX5_FLOW_TYPE_DV : 4208 MLX5_FLOW_TYPE_VERBS; 4209 return type; 4210 } 4211 4212 #define flow_get_drv_ops(type) flow_drv_ops[type] 4213 4214 /** 4215 * Flow driver validation API. This abstracts calling driver specific functions. 4216 * The type of flow driver is determined according to flow attributes. 4217 * 4218 * @param[in] dev 4219 * Pointer to the dev structure. 4220 * @param[in] attr 4221 * Pointer to the flow attributes. 4222 * @param[in] items 4223 * Pointer to the list of items. 4224 * @param[in] actions 4225 * Pointer to the list of actions. 4226 * @param[in] external 4227 * This flow rule is created by request external to PMD. 4228 * @param[in] hairpin 4229 * Number of hairpin TX actions, 0 means classic flow. 4230 * @param[out] error 4231 * Pointer to the error structure. 4232 * 4233 * @return 4234 * 0 on success, a negative errno value otherwise and rte_errno is set. 4235 */ 4236 static inline int 4237 flow_drv_validate(struct rte_eth_dev *dev, 4238 const struct rte_flow_attr *attr, 4239 const struct rte_flow_item items[], 4240 const struct rte_flow_action actions[], 4241 bool external, int hairpin, struct rte_flow_error *error) 4242 { 4243 const struct mlx5_flow_driver_ops *fops; 4244 enum mlx5_flow_drv_type type = flow_get_drv_type(dev, attr); 4245 4246 fops = flow_get_drv_ops(type); 4247 return fops->validate(dev, attr, items, actions, external, 4248 hairpin, error); 4249 } 4250 4251 /** 4252 * Flow driver preparation API. This abstracts calling driver specific 4253 * functions. Parent flow (rte_flow) should have driver type (drv_type). It 4254 * calculates the size of memory required for device flow, allocates the memory, 4255 * initializes the device flow and returns the pointer. 4256 * 4257 * @note 4258 * This function initializes device flow structure such as dv or verbs in 4259 * struct mlx5_flow. However, it is caller's responsibility to initialize the 4260 * rest. For example, adding returning device flow to flow->dev_flow list and 4261 * setting backward reference to the flow should be done out of this function. 4262 * layers field is not filled either. 4263 * 4264 * @param[in] dev 4265 * Pointer to the dev structure. 4266 * @param[in] attr 4267 * Pointer to the flow attributes. 4268 * @param[in] items 4269 * Pointer to the list of items. 4270 * @param[in] actions 4271 * Pointer to the list of actions. 4272 * @param[in] flow_idx 4273 * This memory pool index to the flow. 4274 * @param[out] error 4275 * Pointer to the error structure. 4276 * 4277 * @return 4278 * Pointer to device flow on success, otherwise NULL and rte_errno is set. 4279 */ 4280 static inline struct mlx5_flow * 4281 flow_drv_prepare(struct rte_eth_dev *dev, 4282 const struct rte_flow *flow, 4283 const struct rte_flow_attr *attr, 4284 const struct rte_flow_item items[], 4285 const struct rte_flow_action actions[], 4286 uint32_t flow_idx, 4287 struct rte_flow_error *error) 4288 { 4289 const struct mlx5_flow_driver_ops *fops; 4290 enum mlx5_flow_drv_type type = flow->drv_type; 4291 struct mlx5_flow *mlx5_flow = NULL; 4292 4293 MLX5_ASSERT(type > MLX5_FLOW_TYPE_MIN && type < MLX5_FLOW_TYPE_MAX); 4294 fops = flow_get_drv_ops(type); 4295 mlx5_flow = fops->prepare(dev, attr, items, actions, error); 4296 if (mlx5_flow) 4297 mlx5_flow->flow_idx = flow_idx; 4298 return mlx5_flow; 4299 } 4300 4301 /** 4302 * Flow driver translation API. This abstracts calling driver specific 4303 * functions. Parent flow (rte_flow) should have driver type (drv_type). It 4304 * translates a generic flow into a driver flow. flow_drv_prepare() must 4305 * precede. 4306 * 4307 * @note 4308 * dev_flow->layers could be filled as a result of parsing during translation 4309 * if needed by flow_drv_apply(). dev_flow->flow->actions can also be filled 4310 * if necessary. As a flow can have multiple dev_flows by RSS flow expansion, 4311 * flow->actions could be overwritten even though all the expanded dev_flows 4312 * have the same actions. 4313 * 4314 * @param[in] dev 4315 * Pointer to the rte dev structure. 4316 * @param[in, out] dev_flow 4317 * Pointer to the mlx5 flow. 4318 * @param[in] attr 4319 * Pointer to the flow attributes. 4320 * @param[in] items 4321 * Pointer to the list of items. 4322 * @param[in] actions 4323 * Pointer to the list of actions. 4324 * @param[out] error 4325 * Pointer to the error structure. 4326 * 4327 * @return 4328 * 0 on success, a negative errno value otherwise and rte_errno is set. 4329 */ 4330 static inline int 4331 flow_drv_translate(struct rte_eth_dev *dev, struct mlx5_flow *dev_flow, 4332 const struct rte_flow_attr *attr, 4333 const struct rte_flow_item items[], 4334 const struct rte_flow_action actions[], 4335 struct rte_flow_error *error) 4336 { 4337 const struct mlx5_flow_driver_ops *fops; 4338 enum mlx5_flow_drv_type type = dev_flow->flow->drv_type; 4339 4340 MLX5_ASSERT(type > MLX5_FLOW_TYPE_MIN && type < MLX5_FLOW_TYPE_MAX); 4341 fops = flow_get_drv_ops(type); 4342 return fops->translate(dev, dev_flow, attr, items, actions, error); 4343 } 4344 4345 /** 4346 * Flow driver apply API. This abstracts calling driver specific functions. 4347 * Parent flow (rte_flow) should have driver type (drv_type). It applies 4348 * translated driver flows on to device. flow_drv_translate() must precede. 4349 * 4350 * @param[in] dev 4351 * Pointer to Ethernet device structure. 4352 * @param[in, out] flow 4353 * Pointer to flow structure. 4354 * @param[out] error 4355 * Pointer to error structure. 4356 * 4357 * @return 4358 * 0 on success, a negative errno value otherwise and rte_errno is set. 4359 */ 4360 static inline int 4361 flow_drv_apply(struct rte_eth_dev *dev, struct rte_flow *flow, 4362 struct rte_flow_error *error) 4363 { 4364 const struct mlx5_flow_driver_ops *fops; 4365 enum mlx5_flow_drv_type type = flow->drv_type; 4366 4367 MLX5_ASSERT(type > MLX5_FLOW_TYPE_MIN && type < MLX5_FLOW_TYPE_MAX); 4368 fops = flow_get_drv_ops(type); 4369 return fops->apply(dev, flow, error); 4370 } 4371 4372 /** 4373 * Flow driver destroy API. This abstracts calling driver specific functions. 4374 * Parent flow (rte_flow) should have driver type (drv_type). It removes a flow 4375 * on device and releases resources of the flow. 4376 * 4377 * @param[in] dev 4378 * Pointer to Ethernet device. 4379 * @param[in, out] flow 4380 * Pointer to flow structure. 4381 */ 4382 static inline void 4383 flow_drv_destroy(struct rte_eth_dev *dev, struct rte_flow *flow) 4384 { 4385 const struct mlx5_flow_driver_ops *fops; 4386 enum mlx5_flow_drv_type type = flow->drv_type; 4387 4388 MLX5_ASSERT(type > MLX5_FLOW_TYPE_MIN && type < MLX5_FLOW_TYPE_MAX); 4389 fops = flow_get_drv_ops(type); 4390 fops->destroy(dev, flow); 4391 } 4392 4393 /** 4394 * Flow driver find RSS policy tbl API. This abstracts calling driver 4395 * specific functions. Parent flow (rte_flow) should have driver 4396 * type (drv_type). It will find the RSS policy table that has the rss_desc. 4397 * 4398 * @param[in] dev 4399 * Pointer to Ethernet device. 4400 * @param[in, out] flow 4401 * Pointer to flow structure. 4402 * @param[in] policy 4403 * Pointer to meter policy table. 4404 * @param[in] rss_desc 4405 * Pointer to rss_desc 4406 */ 4407 static struct mlx5_flow_meter_sub_policy * 4408 flow_drv_meter_sub_policy_rss_prepare(struct rte_eth_dev *dev, 4409 struct rte_flow *flow, 4410 struct mlx5_flow_meter_policy *policy, 4411 struct mlx5_flow_rss_desc *rss_desc[MLX5_MTR_RTE_COLORS]) 4412 { 4413 const struct mlx5_flow_driver_ops *fops; 4414 enum mlx5_flow_drv_type type = flow->drv_type; 4415 4416 MLX5_ASSERT(type > MLX5_FLOW_TYPE_MIN && type < MLX5_FLOW_TYPE_MAX); 4417 fops = flow_get_drv_ops(type); 4418 return fops->meter_sub_policy_rss_prepare(dev, policy, rss_desc); 4419 } 4420 4421 /** 4422 * Flow driver color tag rule API. This abstracts calling driver 4423 * specific functions. Parent flow (rte_flow) should have driver 4424 * type (drv_type). It will create the color tag rules in hierarchy meter. 4425 * 4426 * @param[in] dev 4427 * Pointer to Ethernet device. 4428 * @param[in, out] flow 4429 * Pointer to flow structure. 4430 * @param[in] fm 4431 * Pointer to flow meter structure. 4432 * @param[in] src_port 4433 * The src port this extra rule should use. 4434 * @param[in] item 4435 * The src port id match item. 4436 * @param[out] error 4437 * Pointer to error structure. 4438 */ 4439 static int 4440 flow_drv_mtr_hierarchy_rule_create(struct rte_eth_dev *dev, 4441 struct rte_flow *flow, 4442 struct mlx5_flow_meter_info *fm, 4443 int32_t src_port, 4444 const struct rte_flow_item *item, 4445 struct rte_flow_error *error) 4446 { 4447 const struct mlx5_flow_driver_ops *fops; 4448 enum mlx5_flow_drv_type type = flow->drv_type; 4449 4450 MLX5_ASSERT(type > MLX5_FLOW_TYPE_MIN && type < MLX5_FLOW_TYPE_MAX); 4451 fops = flow_get_drv_ops(type); 4452 return fops->meter_hierarchy_rule_create(dev, fm, 4453 src_port, item, error); 4454 } 4455 4456 /** 4457 * Get RSS action from the action list. 4458 * 4459 * @param[in] dev 4460 * Pointer to Ethernet device. 4461 * @param[in] actions 4462 * Pointer to the list of actions. 4463 * @param[in] flow 4464 * Parent flow structure pointer. 4465 * 4466 * @return 4467 * Pointer to the RSS action if exist, else return NULL. 4468 */ 4469 static const struct rte_flow_action_rss* 4470 flow_get_rss_action(struct rte_eth_dev *dev, 4471 const struct rte_flow_action actions[]) 4472 { 4473 struct mlx5_priv *priv = dev->data->dev_private; 4474 const struct rte_flow_action_rss *rss = NULL; 4475 struct mlx5_meter_policy_action_container *acg; 4476 struct mlx5_meter_policy_action_container *acy; 4477 4478 for (; actions->type != RTE_FLOW_ACTION_TYPE_END; actions++) { 4479 switch (actions->type) { 4480 case RTE_FLOW_ACTION_TYPE_RSS: 4481 rss = actions->conf; 4482 break; 4483 case RTE_FLOW_ACTION_TYPE_SAMPLE: 4484 { 4485 const struct rte_flow_action_sample *sample = 4486 actions->conf; 4487 const struct rte_flow_action *act = sample->actions; 4488 for (; act->type != RTE_FLOW_ACTION_TYPE_END; act++) 4489 if (act->type == RTE_FLOW_ACTION_TYPE_RSS) 4490 rss = act->conf; 4491 break; 4492 } 4493 case RTE_FLOW_ACTION_TYPE_METER: 4494 { 4495 uint32_t mtr_idx; 4496 struct mlx5_flow_meter_info *fm; 4497 struct mlx5_flow_meter_policy *policy; 4498 const struct rte_flow_action_meter *mtr = actions->conf; 4499 4500 fm = mlx5_flow_meter_find(priv, mtr->mtr_id, &mtr_idx); 4501 if (fm && !fm->def_policy) { 4502 policy = mlx5_flow_meter_policy_find(dev, 4503 fm->policy_id, NULL); 4504 MLX5_ASSERT(policy); 4505 if (policy->is_hierarchy) { 4506 policy = 4507 mlx5_flow_meter_hierarchy_get_final_policy(dev, 4508 policy); 4509 if (!policy) 4510 return NULL; 4511 } 4512 if (policy->is_rss) { 4513 acg = 4514 &policy->act_cnt[RTE_COLOR_GREEN]; 4515 acy = 4516 &policy->act_cnt[RTE_COLOR_YELLOW]; 4517 if (acg->fate_action == 4518 MLX5_FLOW_FATE_SHARED_RSS) 4519 rss = acg->rss->conf; 4520 else if (acy->fate_action == 4521 MLX5_FLOW_FATE_SHARED_RSS) 4522 rss = acy->rss->conf; 4523 } 4524 } 4525 break; 4526 } 4527 default: 4528 break; 4529 } 4530 } 4531 return rss; 4532 } 4533 4534 /** 4535 * Get ASO age action by index. 4536 * 4537 * @param[in] dev 4538 * Pointer to the Ethernet device structure. 4539 * @param[in] age_idx 4540 * Index to the ASO age action. 4541 * 4542 * @return 4543 * The specified ASO age action. 4544 */ 4545 struct mlx5_aso_age_action* 4546 flow_aso_age_get_by_idx(struct rte_eth_dev *dev, uint32_t age_idx) 4547 { 4548 uint16_t pool_idx = age_idx & UINT16_MAX; 4549 uint16_t offset = (age_idx >> 16) & UINT16_MAX; 4550 struct mlx5_priv *priv = dev->data->dev_private; 4551 struct mlx5_aso_age_mng *mng = priv->sh->aso_age_mng; 4552 struct mlx5_aso_age_pool *pool; 4553 4554 rte_rwlock_read_lock(&mng->resize_rwl); 4555 pool = mng->pools[pool_idx]; 4556 rte_rwlock_read_unlock(&mng->resize_rwl); 4557 return &pool->actions[offset - 1]; 4558 } 4559 4560 /* maps indirect action to translated direct in some actions array */ 4561 struct mlx5_translated_action_handle { 4562 struct rte_flow_action_handle *action; /**< Indirect action handle. */ 4563 int index; /**< Index in related array of rte_flow_action. */ 4564 }; 4565 4566 /** 4567 * Translates actions of type RTE_FLOW_ACTION_TYPE_INDIRECT to related 4568 * direct action if translation possible. 4569 * This functionality used to run same execution path for both direct and 4570 * indirect actions on flow create. All necessary preparations for indirect 4571 * action handling should be performed on *handle* actions list returned 4572 * from this call. 4573 * 4574 * @param[in] dev 4575 * Pointer to Ethernet device. 4576 * @param[in] actions 4577 * List of actions to translate. 4578 * @param[out] handle 4579 * List to store translated indirect action object handles. 4580 * @param[in, out] indir_n 4581 * Size of *handle* array. On return should be updated with number of 4582 * indirect actions retrieved from the *actions* list. 4583 * @param[out] translated_actions 4584 * List of actions where all indirect actions were translated to direct 4585 * if possible. NULL if no translation took place. 4586 * @param[out] error 4587 * Pointer to the error structure. 4588 * 4589 * @return 4590 * 0 on success, a negative errno value otherwise and rte_errno is set. 4591 */ 4592 static int 4593 flow_action_handles_translate(struct rte_eth_dev *dev, 4594 const struct rte_flow_action actions[], 4595 struct mlx5_translated_action_handle *handle, 4596 int *indir_n, 4597 struct rte_flow_action **translated_actions, 4598 struct rte_flow_error *error) 4599 { 4600 struct mlx5_priv *priv = dev->data->dev_private; 4601 struct rte_flow_action *translated = NULL; 4602 size_t actions_size; 4603 int n; 4604 int copied_n = 0; 4605 struct mlx5_translated_action_handle *handle_end = NULL; 4606 4607 for (n = 0; actions[n].type != RTE_FLOW_ACTION_TYPE_END; n++) { 4608 if (actions[n].type != RTE_FLOW_ACTION_TYPE_INDIRECT) 4609 continue; 4610 if (copied_n == *indir_n) { 4611 return rte_flow_error_set 4612 (error, EINVAL, RTE_FLOW_ERROR_TYPE_ACTION_NUM, 4613 NULL, "too many shared actions"); 4614 } 4615 rte_memcpy(&handle[copied_n].action, &actions[n].conf, 4616 sizeof(actions[n].conf)); 4617 handle[copied_n].index = n; 4618 copied_n++; 4619 } 4620 n++; 4621 *indir_n = copied_n; 4622 if (!copied_n) 4623 return 0; 4624 actions_size = sizeof(struct rte_flow_action) * n; 4625 translated = mlx5_malloc(MLX5_MEM_ZERO, actions_size, 0, SOCKET_ID_ANY); 4626 if (!translated) { 4627 rte_errno = ENOMEM; 4628 return -ENOMEM; 4629 } 4630 memcpy(translated, actions, actions_size); 4631 for (handle_end = handle + copied_n; handle < handle_end; handle++) { 4632 struct mlx5_shared_action_rss *shared_rss; 4633 uint32_t act_idx = (uint32_t)(uintptr_t)handle->action; 4634 uint32_t type = act_idx >> MLX5_INDIRECT_ACTION_TYPE_OFFSET; 4635 uint32_t idx = act_idx & 4636 ((1u << MLX5_INDIRECT_ACTION_TYPE_OFFSET) - 1); 4637 4638 switch (type) { 4639 case MLX5_INDIRECT_ACTION_TYPE_RSS: 4640 shared_rss = mlx5_ipool_get 4641 (priv->sh->ipool[MLX5_IPOOL_RSS_SHARED_ACTIONS], idx); 4642 translated[handle->index].type = 4643 RTE_FLOW_ACTION_TYPE_RSS; 4644 translated[handle->index].conf = 4645 &shared_rss->origin; 4646 break; 4647 case MLX5_INDIRECT_ACTION_TYPE_COUNT: 4648 translated[handle->index].type = 4649 (enum rte_flow_action_type) 4650 MLX5_RTE_FLOW_ACTION_TYPE_COUNT; 4651 translated[handle->index].conf = (void *)(uintptr_t)idx; 4652 break; 4653 case MLX5_INDIRECT_ACTION_TYPE_METER_MARK: 4654 translated[handle->index].type = 4655 (enum rte_flow_action_type) 4656 MLX5_RTE_FLOW_ACTION_TYPE_METER_MARK; 4657 translated[handle->index].conf = (void *)(uintptr_t)idx; 4658 break; 4659 case MLX5_INDIRECT_ACTION_TYPE_AGE: 4660 if (priv->sh->flow_hit_aso_en) { 4661 translated[handle->index].type = 4662 (enum rte_flow_action_type) 4663 MLX5_RTE_FLOW_ACTION_TYPE_AGE; 4664 translated[handle->index].conf = 4665 (void *)(uintptr_t)idx; 4666 break; 4667 } 4668 /* Fall-through */ 4669 case MLX5_INDIRECT_ACTION_TYPE_CT: 4670 if (priv->sh->ct_aso_en) { 4671 translated[handle->index].type = 4672 RTE_FLOW_ACTION_TYPE_CONNTRACK; 4673 translated[handle->index].conf = 4674 (void *)(uintptr_t)idx; 4675 break; 4676 } 4677 /* Fall-through */ 4678 default: 4679 mlx5_free(translated); 4680 return rte_flow_error_set 4681 (error, EINVAL, RTE_FLOW_ERROR_TYPE_ACTION, 4682 NULL, "invalid indirect action type"); 4683 } 4684 } 4685 *translated_actions = translated; 4686 return 0; 4687 } 4688 4689 /** 4690 * Get Shared RSS action from the action list. 4691 * 4692 * @param[in] dev 4693 * Pointer to Ethernet device. 4694 * @param[in] shared 4695 * Pointer to the list of actions. 4696 * @param[in] shared_n 4697 * Actions list length. 4698 * 4699 * @return 4700 * The MLX5 RSS action ID if exists, otherwise return 0. 4701 */ 4702 static uint32_t 4703 flow_get_shared_rss_action(struct rte_eth_dev *dev, 4704 struct mlx5_translated_action_handle *handle, 4705 int shared_n) 4706 { 4707 struct mlx5_translated_action_handle *handle_end; 4708 struct mlx5_priv *priv = dev->data->dev_private; 4709 struct mlx5_shared_action_rss *shared_rss; 4710 4711 4712 for (handle_end = handle + shared_n; handle < handle_end; handle++) { 4713 uint32_t act_idx = (uint32_t)(uintptr_t)handle->action; 4714 uint32_t type = act_idx >> MLX5_INDIRECT_ACTION_TYPE_OFFSET; 4715 uint32_t idx = act_idx & 4716 ((1u << MLX5_INDIRECT_ACTION_TYPE_OFFSET) - 1); 4717 switch (type) { 4718 case MLX5_INDIRECT_ACTION_TYPE_RSS: 4719 shared_rss = mlx5_ipool_get 4720 (priv->sh->ipool[MLX5_IPOOL_RSS_SHARED_ACTIONS], 4721 idx); 4722 __atomic_fetch_add(&shared_rss->refcnt, 1, 4723 __ATOMIC_RELAXED); 4724 return idx; 4725 default: 4726 break; 4727 } 4728 } 4729 return 0; 4730 } 4731 4732 static unsigned int 4733 find_graph_root(uint32_t rss_level) 4734 { 4735 return rss_level < 2 ? MLX5_EXPANSION_ROOT : 4736 MLX5_EXPANSION_ROOT_OUTER; 4737 } 4738 4739 /** 4740 * Get layer flags from the prefix flow. 4741 * 4742 * Some flows may be split to several subflows, the prefix subflow gets the 4743 * match items and the suffix sub flow gets the actions. 4744 * Some actions need the user defined match item flags to get the detail for 4745 * the action. 4746 * This function helps the suffix flow to get the item layer flags from prefix 4747 * subflow. 4748 * 4749 * @param[in] dev_flow 4750 * Pointer the created prefix subflow. 4751 * 4752 * @return 4753 * The layers get from prefix subflow. 4754 */ 4755 static inline uint64_t 4756 flow_get_prefix_layer_flags(struct mlx5_flow *dev_flow) 4757 { 4758 uint64_t layers = 0; 4759 4760 /* 4761 * Layers bits could be localization, but usually the compiler will 4762 * help to do the optimization work for source code. 4763 * If no decap actions, use the layers directly. 4764 */ 4765 if (!(dev_flow->act_flags & MLX5_FLOW_ACTION_DECAP)) 4766 return dev_flow->handle->layers; 4767 /* Convert L3 layers with decap action. */ 4768 if (dev_flow->handle->layers & MLX5_FLOW_LAYER_INNER_L3_IPV4) 4769 layers |= MLX5_FLOW_LAYER_OUTER_L3_IPV4; 4770 else if (dev_flow->handle->layers & MLX5_FLOW_LAYER_INNER_L3_IPV6) 4771 layers |= MLX5_FLOW_LAYER_OUTER_L3_IPV6; 4772 /* Convert L4 layers with decap action. */ 4773 if (dev_flow->handle->layers & MLX5_FLOW_LAYER_INNER_L4_TCP) 4774 layers |= MLX5_FLOW_LAYER_OUTER_L4_TCP; 4775 else if (dev_flow->handle->layers & MLX5_FLOW_LAYER_INNER_L4_UDP) 4776 layers |= MLX5_FLOW_LAYER_OUTER_L4_UDP; 4777 return layers; 4778 } 4779 4780 /** 4781 * Get metadata split action information. 4782 * 4783 * @param[in] actions 4784 * Pointer to the list of actions. 4785 * @param[out] qrss 4786 * Pointer to the return pointer. 4787 * @param[out] qrss_type 4788 * Pointer to the action type to return. RTE_FLOW_ACTION_TYPE_END is returned 4789 * if no QUEUE/RSS is found. 4790 * @param[out] encap_idx 4791 * Pointer to the index of the encap action if exists, otherwise the last 4792 * action index. 4793 * 4794 * @return 4795 * Total number of actions. 4796 */ 4797 static int 4798 flow_parse_metadata_split_actions_info(const struct rte_flow_action actions[], 4799 const struct rte_flow_action **qrss, 4800 int *encap_idx) 4801 { 4802 const struct rte_flow_action_raw_encap *raw_encap; 4803 int actions_n = 0; 4804 int raw_decap_idx = -1; 4805 4806 *encap_idx = -1; 4807 for (; actions->type != RTE_FLOW_ACTION_TYPE_END; actions++) { 4808 switch (actions->type) { 4809 case RTE_FLOW_ACTION_TYPE_VXLAN_ENCAP: 4810 case RTE_FLOW_ACTION_TYPE_NVGRE_ENCAP: 4811 *encap_idx = actions_n; 4812 break; 4813 case RTE_FLOW_ACTION_TYPE_RAW_DECAP: 4814 raw_decap_idx = actions_n; 4815 break; 4816 case RTE_FLOW_ACTION_TYPE_RAW_ENCAP: 4817 raw_encap = actions->conf; 4818 if (raw_encap->size > MLX5_ENCAPSULATION_DECISION_SIZE) 4819 *encap_idx = raw_decap_idx != -1 ? 4820 raw_decap_idx : actions_n; 4821 break; 4822 case RTE_FLOW_ACTION_TYPE_QUEUE: 4823 case RTE_FLOW_ACTION_TYPE_RSS: 4824 *qrss = actions; 4825 break; 4826 default: 4827 break; 4828 } 4829 actions_n++; 4830 } 4831 if (*encap_idx == -1) 4832 *encap_idx = actions_n; 4833 /* Count RTE_FLOW_ACTION_TYPE_END. */ 4834 return actions_n + 1; 4835 } 4836 4837 /** 4838 * Check if the action will change packet. 4839 * 4840 * @param dev 4841 * Pointer to Ethernet device. 4842 * @param[in] type 4843 * action type. 4844 * 4845 * @return 4846 * true if action will change packet, false otherwise. 4847 */ 4848 static bool flow_check_modify_action_type(struct rte_eth_dev *dev, 4849 enum rte_flow_action_type type) 4850 { 4851 struct mlx5_priv *priv = dev->data->dev_private; 4852 4853 switch (type) { 4854 case RTE_FLOW_ACTION_TYPE_SET_MAC_SRC: 4855 case RTE_FLOW_ACTION_TYPE_SET_MAC_DST: 4856 case RTE_FLOW_ACTION_TYPE_SET_IPV4_SRC: 4857 case RTE_FLOW_ACTION_TYPE_SET_IPV4_DST: 4858 case RTE_FLOW_ACTION_TYPE_SET_IPV6_SRC: 4859 case RTE_FLOW_ACTION_TYPE_SET_IPV6_DST: 4860 case RTE_FLOW_ACTION_TYPE_SET_TP_SRC: 4861 case RTE_FLOW_ACTION_TYPE_SET_TP_DST: 4862 case RTE_FLOW_ACTION_TYPE_DEC_TTL: 4863 case RTE_FLOW_ACTION_TYPE_SET_TTL: 4864 case RTE_FLOW_ACTION_TYPE_INC_TCP_SEQ: 4865 case RTE_FLOW_ACTION_TYPE_DEC_TCP_SEQ: 4866 case RTE_FLOW_ACTION_TYPE_INC_TCP_ACK: 4867 case RTE_FLOW_ACTION_TYPE_DEC_TCP_ACK: 4868 case RTE_FLOW_ACTION_TYPE_SET_IPV4_DSCP: 4869 case RTE_FLOW_ACTION_TYPE_SET_IPV6_DSCP: 4870 case RTE_FLOW_ACTION_TYPE_SET_META: 4871 case RTE_FLOW_ACTION_TYPE_SET_TAG: 4872 case RTE_FLOW_ACTION_TYPE_OF_POP_VLAN: 4873 case RTE_FLOW_ACTION_TYPE_OF_PUSH_VLAN: 4874 case RTE_FLOW_ACTION_TYPE_OF_SET_VLAN_VID: 4875 case RTE_FLOW_ACTION_TYPE_OF_SET_VLAN_PCP: 4876 case RTE_FLOW_ACTION_TYPE_VXLAN_ENCAP: 4877 case RTE_FLOW_ACTION_TYPE_VXLAN_DECAP: 4878 case RTE_FLOW_ACTION_TYPE_NVGRE_ENCAP: 4879 case RTE_FLOW_ACTION_TYPE_NVGRE_DECAP: 4880 case RTE_FLOW_ACTION_TYPE_RAW_ENCAP: 4881 case RTE_FLOW_ACTION_TYPE_RAW_DECAP: 4882 case RTE_FLOW_ACTION_TYPE_MODIFY_FIELD: 4883 return true; 4884 case RTE_FLOW_ACTION_TYPE_FLAG: 4885 case RTE_FLOW_ACTION_TYPE_MARK: 4886 if (priv->sh->config.dv_xmeta_en != MLX5_XMETA_MODE_LEGACY && 4887 priv->sh->config.dv_xmeta_en != MLX5_XMETA_MODE_META32_HWS) 4888 return true; 4889 else 4890 return false; 4891 default: 4892 return false; 4893 } 4894 } 4895 4896 /** 4897 * Check meter action from the action list. 4898 * 4899 * @param dev 4900 * Pointer to Ethernet device. 4901 * @param[in] actions 4902 * Pointer to the list of actions. 4903 * @param[out] has_mtr 4904 * Pointer to the meter exist flag. 4905 * @param[out] has_modify 4906 * Pointer to the flag showing there's packet change action. 4907 * @param[out] meter_id 4908 * Pointer to the meter id. 4909 * 4910 * @return 4911 * Total number of actions. 4912 */ 4913 static int 4914 flow_check_meter_action(struct rte_eth_dev *dev, 4915 const struct rte_flow_action actions[], 4916 bool *has_mtr, bool *has_modify, uint32_t *meter_id) 4917 { 4918 const struct rte_flow_action_meter *mtr = NULL; 4919 int actions_n = 0; 4920 4921 MLX5_ASSERT(has_mtr); 4922 *has_mtr = false; 4923 for (; actions->type != RTE_FLOW_ACTION_TYPE_END; actions++) { 4924 switch (actions->type) { 4925 case RTE_FLOW_ACTION_TYPE_METER: 4926 mtr = actions->conf; 4927 *meter_id = mtr->mtr_id; 4928 *has_mtr = true; 4929 break; 4930 default: 4931 break; 4932 } 4933 if (!*has_mtr) 4934 *has_modify |= flow_check_modify_action_type(dev, 4935 actions->type); 4936 actions_n++; 4937 } 4938 /* Count RTE_FLOW_ACTION_TYPE_END. */ 4939 return actions_n + 1; 4940 } 4941 4942 /** 4943 * Check if the flow should be split due to hairpin. 4944 * The reason for the split is that in current HW we can't 4945 * support encap and push-vlan on Rx, so if a flow contains 4946 * these actions we move it to Tx. 4947 * 4948 * @param dev 4949 * Pointer to Ethernet device. 4950 * @param[in] attr 4951 * Flow rule attributes. 4952 * @param[in] actions 4953 * Associated actions (list terminated by the END action). 4954 * 4955 * @return 4956 * > 0 the number of actions and the flow should be split, 4957 * 0 when no split required. 4958 */ 4959 static int 4960 flow_check_hairpin_split(struct rte_eth_dev *dev, 4961 const struct rte_flow_attr *attr, 4962 const struct rte_flow_action actions[]) 4963 { 4964 int queue_action = 0; 4965 int action_n = 0; 4966 int split = 0; 4967 int push_vlan = 0; 4968 const struct rte_flow_action_queue *queue; 4969 const struct rte_flow_action_rss *rss; 4970 const struct rte_flow_action_raw_encap *raw_encap; 4971 const struct rte_eth_hairpin_conf *conf; 4972 4973 if (!attr->ingress) 4974 return 0; 4975 for (; actions->type != RTE_FLOW_ACTION_TYPE_END; actions++) { 4976 if (actions->type == RTE_FLOW_ACTION_TYPE_OF_PUSH_VLAN) 4977 push_vlan = 1; 4978 switch (actions->type) { 4979 case RTE_FLOW_ACTION_TYPE_QUEUE: 4980 queue = actions->conf; 4981 if (queue == NULL) 4982 return 0; 4983 conf = mlx5_rxq_get_hairpin_conf(dev, queue->index); 4984 if (conf == NULL || conf->tx_explicit != 0) 4985 return 0; 4986 queue_action = 1; 4987 action_n++; 4988 break; 4989 case RTE_FLOW_ACTION_TYPE_RSS: 4990 rss = actions->conf; 4991 if (rss == NULL || rss->queue_num == 0) 4992 return 0; 4993 conf = mlx5_rxq_get_hairpin_conf(dev, rss->queue[0]); 4994 if (conf == NULL || conf->tx_explicit != 0) 4995 return 0; 4996 queue_action = 1; 4997 action_n++; 4998 break; 4999 case RTE_FLOW_ACTION_TYPE_VXLAN_ENCAP: 5000 case RTE_FLOW_ACTION_TYPE_NVGRE_ENCAP: 5001 case RTE_FLOW_ACTION_TYPE_OF_PUSH_VLAN: 5002 case RTE_FLOW_ACTION_TYPE_OF_SET_VLAN_PCP: 5003 split++; 5004 action_n++; 5005 break; 5006 case RTE_FLOW_ACTION_TYPE_OF_SET_VLAN_VID: 5007 if (push_vlan) 5008 split++; 5009 action_n++; 5010 break; 5011 case RTE_FLOW_ACTION_TYPE_RAW_ENCAP: 5012 raw_encap = actions->conf; 5013 if (raw_encap->size > MLX5_ENCAPSULATION_DECISION_SIZE) 5014 split++; 5015 action_n++; 5016 break; 5017 default: 5018 action_n++; 5019 break; 5020 } 5021 } 5022 if (split && queue_action) 5023 return action_n; 5024 return 0; 5025 } 5026 5027 /* Declare flow create/destroy prototype in advance. */ 5028 static uint32_t 5029 flow_list_create(struct rte_eth_dev *dev, enum mlx5_flow_type type, 5030 const struct rte_flow_attr *attr, 5031 const struct rte_flow_item items[], 5032 const struct rte_flow_action actions[], 5033 bool external, struct rte_flow_error *error); 5034 5035 static void 5036 flow_list_destroy(struct rte_eth_dev *dev, enum mlx5_flow_type type, 5037 uint32_t flow_idx); 5038 5039 int 5040 flow_dv_mreg_match_cb(void *tool_ctx __rte_unused, 5041 struct mlx5_list_entry *entry, void *cb_ctx) 5042 { 5043 struct mlx5_flow_cb_ctx *ctx = cb_ctx; 5044 struct mlx5_flow_mreg_copy_resource *mcp_res = 5045 container_of(entry, typeof(*mcp_res), hlist_ent); 5046 5047 return mcp_res->mark_id != *(uint32_t *)(ctx->data); 5048 } 5049 5050 struct mlx5_list_entry * 5051 flow_dv_mreg_create_cb(void *tool_ctx, void *cb_ctx) 5052 { 5053 struct rte_eth_dev *dev = tool_ctx; 5054 struct mlx5_priv *priv = dev->data->dev_private; 5055 struct mlx5_flow_cb_ctx *ctx = cb_ctx; 5056 struct mlx5_flow_mreg_copy_resource *mcp_res; 5057 struct rte_flow_error *error = ctx->error; 5058 uint32_t idx = 0; 5059 int ret; 5060 uint32_t mark_id = *(uint32_t *)(ctx->data); 5061 struct rte_flow_attr attr = { 5062 .group = MLX5_FLOW_MREG_CP_TABLE_GROUP, 5063 .ingress = 1, 5064 }; 5065 struct mlx5_rte_flow_item_tag tag_spec = { 5066 .data = mark_id, 5067 }; 5068 struct rte_flow_item items[] = { 5069 [1] = { .type = RTE_FLOW_ITEM_TYPE_END, }, 5070 }; 5071 struct rte_flow_action_mark ftag = { 5072 .id = mark_id, 5073 }; 5074 struct mlx5_flow_action_copy_mreg cp_mreg = { 5075 .dst = REG_B, 5076 .src = REG_NON, 5077 }; 5078 struct rte_flow_action_jump jump = { 5079 .group = MLX5_FLOW_MREG_ACT_TABLE_GROUP, 5080 }; 5081 struct rte_flow_action actions[] = { 5082 [3] = { .type = RTE_FLOW_ACTION_TYPE_END, }, 5083 }; 5084 5085 /* Fill the register fields in the flow. */ 5086 ret = mlx5_flow_get_reg_id(dev, MLX5_FLOW_MARK, 0, error); 5087 if (ret < 0) 5088 return NULL; 5089 tag_spec.id = ret; 5090 ret = mlx5_flow_get_reg_id(dev, MLX5_METADATA_RX, 0, error); 5091 if (ret < 0) 5092 return NULL; 5093 cp_mreg.src = ret; 5094 /* Provide the full width of FLAG specific value. */ 5095 if (mark_id == (priv->sh->dv_regc0_mask & MLX5_FLOW_MARK_DEFAULT)) 5096 tag_spec.data = MLX5_FLOW_MARK_DEFAULT; 5097 /* Build a new flow. */ 5098 if (mark_id != MLX5_DEFAULT_COPY_ID) { 5099 items[0] = (struct rte_flow_item){ 5100 .type = (enum rte_flow_item_type) 5101 MLX5_RTE_FLOW_ITEM_TYPE_TAG, 5102 .spec = &tag_spec, 5103 }; 5104 items[1] = (struct rte_flow_item){ 5105 .type = RTE_FLOW_ITEM_TYPE_END, 5106 }; 5107 actions[0] = (struct rte_flow_action){ 5108 .type = (enum rte_flow_action_type) 5109 MLX5_RTE_FLOW_ACTION_TYPE_MARK, 5110 .conf = &ftag, 5111 }; 5112 actions[1] = (struct rte_flow_action){ 5113 .type = (enum rte_flow_action_type) 5114 MLX5_RTE_FLOW_ACTION_TYPE_COPY_MREG, 5115 .conf = &cp_mreg, 5116 }; 5117 actions[2] = (struct rte_flow_action){ 5118 .type = RTE_FLOW_ACTION_TYPE_JUMP, 5119 .conf = &jump, 5120 }; 5121 actions[3] = (struct rte_flow_action){ 5122 .type = RTE_FLOW_ACTION_TYPE_END, 5123 }; 5124 } else { 5125 /* Default rule, wildcard match. */ 5126 attr.priority = MLX5_FLOW_LOWEST_PRIO_INDICATOR; 5127 items[0] = (struct rte_flow_item){ 5128 .type = RTE_FLOW_ITEM_TYPE_END, 5129 }; 5130 actions[0] = (struct rte_flow_action){ 5131 .type = (enum rte_flow_action_type) 5132 MLX5_RTE_FLOW_ACTION_TYPE_COPY_MREG, 5133 .conf = &cp_mreg, 5134 }; 5135 actions[1] = (struct rte_flow_action){ 5136 .type = RTE_FLOW_ACTION_TYPE_JUMP, 5137 .conf = &jump, 5138 }; 5139 actions[2] = (struct rte_flow_action){ 5140 .type = RTE_FLOW_ACTION_TYPE_END, 5141 }; 5142 } 5143 /* Build a new entry. */ 5144 mcp_res = mlx5_ipool_zmalloc(priv->sh->ipool[MLX5_IPOOL_MCP], &idx); 5145 if (!mcp_res) { 5146 rte_errno = ENOMEM; 5147 return NULL; 5148 } 5149 mcp_res->idx = idx; 5150 mcp_res->mark_id = mark_id; 5151 /* 5152 * The copy Flows are not included in any list. There 5153 * ones are referenced from other Flows and can not 5154 * be applied, removed, deleted in arbitrary order 5155 * by list traversing. 5156 */ 5157 mcp_res->rix_flow = flow_list_create(dev, MLX5_FLOW_TYPE_MCP, 5158 &attr, items, actions, false, error); 5159 if (!mcp_res->rix_flow) { 5160 mlx5_ipool_free(priv->sh->ipool[MLX5_IPOOL_MCP], idx); 5161 return NULL; 5162 } 5163 return &mcp_res->hlist_ent; 5164 } 5165 5166 struct mlx5_list_entry * 5167 flow_dv_mreg_clone_cb(void *tool_ctx, struct mlx5_list_entry *oentry, 5168 void *cb_ctx __rte_unused) 5169 { 5170 struct rte_eth_dev *dev = tool_ctx; 5171 struct mlx5_priv *priv = dev->data->dev_private; 5172 struct mlx5_flow_mreg_copy_resource *mcp_res; 5173 uint32_t idx = 0; 5174 5175 mcp_res = mlx5_ipool_malloc(priv->sh->ipool[MLX5_IPOOL_MCP], &idx); 5176 if (!mcp_res) { 5177 rte_errno = ENOMEM; 5178 return NULL; 5179 } 5180 memcpy(mcp_res, oentry, sizeof(*mcp_res)); 5181 mcp_res->idx = idx; 5182 return &mcp_res->hlist_ent; 5183 } 5184 5185 void 5186 flow_dv_mreg_clone_free_cb(void *tool_ctx, struct mlx5_list_entry *entry) 5187 { 5188 struct mlx5_flow_mreg_copy_resource *mcp_res = 5189 container_of(entry, typeof(*mcp_res), hlist_ent); 5190 struct rte_eth_dev *dev = tool_ctx; 5191 struct mlx5_priv *priv = dev->data->dev_private; 5192 5193 mlx5_ipool_free(priv->sh->ipool[MLX5_IPOOL_MCP], mcp_res->idx); 5194 } 5195 5196 /** 5197 * Add a flow of copying flow metadata registers in RX_CP_TBL. 5198 * 5199 * As mark_id is unique, if there's already a registered flow for the mark_id, 5200 * return by increasing the reference counter of the resource. Otherwise, create 5201 * the resource (mcp_res) and flow. 5202 * 5203 * Flow looks like, 5204 * - If ingress port is ANY and reg_c[1] is mark_id, 5205 * flow_tag := mark_id, reg_b := reg_c[0] and jump to RX_ACT_TBL. 5206 * 5207 * For default flow (zero mark_id), flow is like, 5208 * - If ingress port is ANY, 5209 * reg_b := reg_c[0] and jump to RX_ACT_TBL. 5210 * 5211 * @param dev 5212 * Pointer to Ethernet device. 5213 * @param mark_id 5214 * ID of MARK action, zero means default flow for META. 5215 * @param[out] error 5216 * Perform verbose error reporting if not NULL. 5217 * 5218 * @return 5219 * Associated resource on success, NULL otherwise and rte_errno is set. 5220 */ 5221 static struct mlx5_flow_mreg_copy_resource * 5222 flow_mreg_add_copy_action(struct rte_eth_dev *dev, uint32_t mark_id, 5223 struct rte_flow_error *error) 5224 { 5225 struct mlx5_priv *priv = dev->data->dev_private; 5226 struct mlx5_list_entry *entry; 5227 struct mlx5_flow_cb_ctx ctx = { 5228 .dev = dev, 5229 .error = error, 5230 .data = &mark_id, 5231 }; 5232 5233 /* Check if already registered. */ 5234 MLX5_ASSERT(priv->mreg_cp_tbl); 5235 entry = mlx5_hlist_register(priv->mreg_cp_tbl, mark_id, &ctx); 5236 if (!entry) 5237 return NULL; 5238 return container_of(entry, struct mlx5_flow_mreg_copy_resource, 5239 hlist_ent); 5240 } 5241 5242 void 5243 flow_dv_mreg_remove_cb(void *tool_ctx, struct mlx5_list_entry *entry) 5244 { 5245 struct mlx5_flow_mreg_copy_resource *mcp_res = 5246 container_of(entry, typeof(*mcp_res), hlist_ent); 5247 struct rte_eth_dev *dev = tool_ctx; 5248 struct mlx5_priv *priv = dev->data->dev_private; 5249 5250 MLX5_ASSERT(mcp_res->rix_flow); 5251 flow_list_destroy(dev, MLX5_FLOW_TYPE_MCP, mcp_res->rix_flow); 5252 mlx5_ipool_free(priv->sh->ipool[MLX5_IPOOL_MCP], mcp_res->idx); 5253 } 5254 5255 /** 5256 * Release flow in RX_CP_TBL. 5257 * 5258 * @param dev 5259 * Pointer to Ethernet device. 5260 * @flow 5261 * Parent flow for wich copying is provided. 5262 */ 5263 static void 5264 flow_mreg_del_copy_action(struct rte_eth_dev *dev, 5265 struct rte_flow *flow) 5266 { 5267 struct mlx5_flow_mreg_copy_resource *mcp_res; 5268 struct mlx5_priv *priv = dev->data->dev_private; 5269 5270 if (!flow->rix_mreg_copy) 5271 return; 5272 mcp_res = mlx5_ipool_get(priv->sh->ipool[MLX5_IPOOL_MCP], 5273 flow->rix_mreg_copy); 5274 if (!mcp_res || !priv->mreg_cp_tbl) 5275 return; 5276 MLX5_ASSERT(mcp_res->rix_flow); 5277 mlx5_hlist_unregister(priv->mreg_cp_tbl, &mcp_res->hlist_ent); 5278 flow->rix_mreg_copy = 0; 5279 } 5280 5281 /** 5282 * Remove the default copy action from RX_CP_TBL. 5283 * 5284 * This functions is called in the mlx5_dev_start(). No thread safe 5285 * is guaranteed. 5286 * 5287 * @param dev 5288 * Pointer to Ethernet device. 5289 */ 5290 static void 5291 flow_mreg_del_default_copy_action(struct rte_eth_dev *dev) 5292 { 5293 struct mlx5_list_entry *entry; 5294 struct mlx5_priv *priv = dev->data->dev_private; 5295 struct mlx5_flow_cb_ctx ctx; 5296 uint32_t mark_id; 5297 5298 /* Check if default flow is registered. */ 5299 if (!priv->mreg_cp_tbl) 5300 return; 5301 mark_id = MLX5_DEFAULT_COPY_ID; 5302 ctx.data = &mark_id; 5303 entry = mlx5_hlist_lookup(priv->mreg_cp_tbl, mark_id, &ctx); 5304 if (!entry) 5305 return; 5306 mlx5_hlist_unregister(priv->mreg_cp_tbl, entry); 5307 } 5308 5309 /** 5310 * Add the default copy action in RX_CP_TBL. 5311 * 5312 * This functions is called in the mlx5_dev_start(). No thread safe 5313 * is guaranteed. 5314 * 5315 * @param dev 5316 * Pointer to Ethernet device. 5317 * @param[out] error 5318 * Perform verbose error reporting if not NULL. 5319 * 5320 * @return 5321 * 0 for success, negative value otherwise and rte_errno is set. 5322 */ 5323 static int 5324 flow_mreg_add_default_copy_action(struct rte_eth_dev *dev, 5325 struct rte_flow_error *error) 5326 { 5327 struct mlx5_priv *priv = dev->data->dev_private; 5328 struct mlx5_flow_mreg_copy_resource *mcp_res; 5329 struct mlx5_flow_cb_ctx ctx; 5330 uint32_t mark_id; 5331 5332 /* Check whether extensive metadata feature is engaged. */ 5333 if (!priv->sh->config.dv_flow_en || 5334 priv->sh->config.dv_xmeta_en == MLX5_XMETA_MODE_LEGACY || 5335 !mlx5_flow_ext_mreg_supported(dev) || 5336 !priv->sh->dv_regc0_mask) 5337 return 0; 5338 /* 5339 * Add default mreg copy flow may be called multiple time, but 5340 * only be called once in stop. Avoid register it twice. 5341 */ 5342 mark_id = MLX5_DEFAULT_COPY_ID; 5343 ctx.data = &mark_id; 5344 if (mlx5_hlist_lookup(priv->mreg_cp_tbl, mark_id, &ctx)) 5345 return 0; 5346 mcp_res = flow_mreg_add_copy_action(dev, mark_id, error); 5347 if (!mcp_res) 5348 return -rte_errno; 5349 return 0; 5350 } 5351 5352 /** 5353 * Add a flow of copying flow metadata registers in RX_CP_TBL. 5354 * 5355 * All the flow having Q/RSS action should be split by 5356 * flow_mreg_split_qrss_prep() to pass by RX_CP_TBL. A flow in the RX_CP_TBL 5357 * performs the following, 5358 * - CQE->flow_tag := reg_c[1] (MARK) 5359 * - CQE->flow_table_metadata (reg_b) := reg_c[0] (META) 5360 * As CQE's flow_tag is not a register, it can't be simply copied from reg_c[1] 5361 * but there should be a flow per each MARK ID set by MARK action. 5362 * 5363 * For the aforementioned reason, if there's a MARK action in flow's action 5364 * list, a corresponding flow should be added to the RX_CP_TBL in order to copy 5365 * the MARK ID to CQE's flow_tag like, 5366 * - If reg_c[1] is mark_id, 5367 * flow_tag := mark_id, reg_b := reg_c[0] and jump to RX_ACT_TBL. 5368 * 5369 * For SET_META action which stores value in reg_c[0], as the destination is 5370 * also a flow metadata register (reg_b), adding a default flow is enough. Zero 5371 * MARK ID means the default flow. The default flow looks like, 5372 * - For all flow, reg_b := reg_c[0] and jump to RX_ACT_TBL. 5373 * 5374 * @param dev 5375 * Pointer to Ethernet device. 5376 * @param flow 5377 * Pointer to flow structure. 5378 * @param[in] actions 5379 * Pointer to the list of actions. 5380 * @param[out] error 5381 * Perform verbose error reporting if not NULL. 5382 * 5383 * @return 5384 * 0 on success, negative value otherwise and rte_errno is set. 5385 */ 5386 static int 5387 flow_mreg_update_copy_table(struct rte_eth_dev *dev, 5388 struct rte_flow *flow, 5389 const struct rte_flow_action *actions, 5390 struct rte_flow_error *error) 5391 { 5392 struct mlx5_priv *priv = dev->data->dev_private; 5393 struct mlx5_sh_config *config = &priv->sh->config; 5394 struct mlx5_flow_mreg_copy_resource *mcp_res; 5395 const struct rte_flow_action_mark *mark; 5396 5397 /* Check whether extensive metadata feature is engaged. */ 5398 if (!config->dv_flow_en || 5399 config->dv_xmeta_en == MLX5_XMETA_MODE_LEGACY || 5400 !mlx5_flow_ext_mreg_supported(dev) || 5401 !priv->sh->dv_regc0_mask) 5402 return 0; 5403 /* Find MARK action. */ 5404 for (; actions->type != RTE_FLOW_ACTION_TYPE_END; actions++) { 5405 switch (actions->type) { 5406 case RTE_FLOW_ACTION_TYPE_FLAG: 5407 mcp_res = flow_mreg_add_copy_action 5408 (dev, MLX5_FLOW_MARK_DEFAULT, error); 5409 if (!mcp_res) 5410 return -rte_errno; 5411 flow->rix_mreg_copy = mcp_res->idx; 5412 return 0; 5413 case RTE_FLOW_ACTION_TYPE_MARK: 5414 mark = (const struct rte_flow_action_mark *) 5415 actions->conf; 5416 mcp_res = 5417 flow_mreg_add_copy_action(dev, mark->id, error); 5418 if (!mcp_res) 5419 return -rte_errno; 5420 flow->rix_mreg_copy = mcp_res->idx; 5421 return 0; 5422 default: 5423 break; 5424 } 5425 } 5426 return 0; 5427 } 5428 5429 #define MLX5_MAX_SPLIT_ACTIONS 24 5430 #define MLX5_MAX_SPLIT_ITEMS 24 5431 5432 /** 5433 * Split the hairpin flow. 5434 * Since HW can't support encap and push-vlan on Rx, we move these 5435 * actions to Tx. 5436 * If the count action is after the encap then we also 5437 * move the count action. in this case the count will also measure 5438 * the outer bytes. 5439 * 5440 * @param dev 5441 * Pointer to Ethernet device. 5442 * @param[in] actions 5443 * Associated actions (list terminated by the END action). 5444 * @param[out] actions_rx 5445 * Rx flow actions. 5446 * @param[out] actions_tx 5447 * Tx flow actions.. 5448 * @param[out] pattern_tx 5449 * The pattern items for the Tx flow. 5450 * @param[out] flow_id 5451 * The flow ID connected to this flow. 5452 * 5453 * @return 5454 * 0 on success. 5455 */ 5456 static int 5457 flow_hairpin_split(struct rte_eth_dev *dev, 5458 const struct rte_flow_action actions[], 5459 struct rte_flow_action actions_rx[], 5460 struct rte_flow_action actions_tx[], 5461 struct rte_flow_item pattern_tx[], 5462 uint32_t flow_id) 5463 { 5464 const struct rte_flow_action_raw_encap *raw_encap; 5465 const struct rte_flow_action_raw_decap *raw_decap; 5466 struct mlx5_rte_flow_action_set_tag *set_tag; 5467 struct rte_flow_action *tag_action; 5468 struct mlx5_rte_flow_item_tag *tag_item; 5469 struct rte_flow_item *item; 5470 char *addr; 5471 int push_vlan = 0; 5472 int encap = 0; 5473 5474 for (; actions->type != RTE_FLOW_ACTION_TYPE_END; actions++) { 5475 if (actions->type == RTE_FLOW_ACTION_TYPE_OF_PUSH_VLAN) 5476 push_vlan = 1; 5477 switch (actions->type) { 5478 case RTE_FLOW_ACTION_TYPE_VXLAN_ENCAP: 5479 case RTE_FLOW_ACTION_TYPE_NVGRE_ENCAP: 5480 case RTE_FLOW_ACTION_TYPE_OF_PUSH_VLAN: 5481 case RTE_FLOW_ACTION_TYPE_OF_SET_VLAN_PCP: 5482 rte_memcpy(actions_tx, actions, 5483 sizeof(struct rte_flow_action)); 5484 actions_tx++; 5485 break; 5486 case RTE_FLOW_ACTION_TYPE_OF_SET_VLAN_VID: 5487 if (push_vlan) { 5488 rte_memcpy(actions_tx, actions, 5489 sizeof(struct rte_flow_action)); 5490 actions_tx++; 5491 } else { 5492 rte_memcpy(actions_rx, actions, 5493 sizeof(struct rte_flow_action)); 5494 actions_rx++; 5495 } 5496 break; 5497 case RTE_FLOW_ACTION_TYPE_COUNT: 5498 if (encap) { 5499 rte_memcpy(actions_tx, actions, 5500 sizeof(struct rte_flow_action)); 5501 actions_tx++; 5502 } else { 5503 rte_memcpy(actions_rx, actions, 5504 sizeof(struct rte_flow_action)); 5505 actions_rx++; 5506 } 5507 break; 5508 case RTE_FLOW_ACTION_TYPE_RAW_ENCAP: 5509 raw_encap = actions->conf; 5510 if (raw_encap->size > MLX5_ENCAPSULATION_DECISION_SIZE) { 5511 memcpy(actions_tx, actions, 5512 sizeof(struct rte_flow_action)); 5513 actions_tx++; 5514 encap = 1; 5515 } else { 5516 rte_memcpy(actions_rx, actions, 5517 sizeof(struct rte_flow_action)); 5518 actions_rx++; 5519 } 5520 break; 5521 case RTE_FLOW_ACTION_TYPE_RAW_DECAP: 5522 raw_decap = actions->conf; 5523 if (raw_decap->size < MLX5_ENCAPSULATION_DECISION_SIZE) { 5524 memcpy(actions_tx, actions, 5525 sizeof(struct rte_flow_action)); 5526 actions_tx++; 5527 } else { 5528 rte_memcpy(actions_rx, actions, 5529 sizeof(struct rte_flow_action)); 5530 actions_rx++; 5531 } 5532 break; 5533 default: 5534 rte_memcpy(actions_rx, actions, 5535 sizeof(struct rte_flow_action)); 5536 actions_rx++; 5537 break; 5538 } 5539 } 5540 /* Add set meta action and end action for the Rx flow. */ 5541 tag_action = actions_rx; 5542 tag_action->type = (enum rte_flow_action_type) 5543 MLX5_RTE_FLOW_ACTION_TYPE_TAG; 5544 actions_rx++; 5545 rte_memcpy(actions_rx, actions, sizeof(struct rte_flow_action)); 5546 actions_rx++; 5547 set_tag = (void *)actions_rx; 5548 *set_tag = (struct mlx5_rte_flow_action_set_tag) { 5549 .id = mlx5_flow_get_reg_id(dev, MLX5_HAIRPIN_RX, 0, NULL), 5550 .data = flow_id, 5551 }; 5552 MLX5_ASSERT(set_tag->id > REG_NON); 5553 tag_action->conf = set_tag; 5554 /* Create Tx item list. */ 5555 rte_memcpy(actions_tx, actions, sizeof(struct rte_flow_action)); 5556 addr = (void *)&pattern_tx[2]; 5557 item = pattern_tx; 5558 item->type = (enum rte_flow_item_type) 5559 MLX5_RTE_FLOW_ITEM_TYPE_TAG; 5560 tag_item = (void *)addr; 5561 tag_item->data = flow_id; 5562 tag_item->id = mlx5_flow_get_reg_id(dev, MLX5_HAIRPIN_TX, 0, NULL); 5563 MLX5_ASSERT(set_tag->id > REG_NON); 5564 item->spec = tag_item; 5565 addr += sizeof(struct mlx5_rte_flow_item_tag); 5566 tag_item = (void *)addr; 5567 tag_item->data = UINT32_MAX; 5568 tag_item->id = UINT16_MAX; 5569 item->mask = tag_item; 5570 item->last = NULL; 5571 item++; 5572 item->type = RTE_FLOW_ITEM_TYPE_END; 5573 return 0; 5574 } 5575 5576 /** 5577 * The last stage of splitting chain, just creates the subflow 5578 * without any modification. 5579 * 5580 * @param[in] dev 5581 * Pointer to Ethernet device. 5582 * @param[in] flow 5583 * Parent flow structure pointer. 5584 * @param[in, out] sub_flow 5585 * Pointer to return the created subflow, may be NULL. 5586 * @param[in] attr 5587 * Flow rule attributes. 5588 * @param[in] items 5589 * Pattern specification (list terminated by the END pattern item). 5590 * @param[in] actions 5591 * Associated actions (list terminated by the END action). 5592 * @param[in] flow_split_info 5593 * Pointer to flow split info structure. 5594 * @param[out] error 5595 * Perform verbose error reporting if not NULL. 5596 * @return 5597 * 0 on success, negative value otherwise 5598 */ 5599 static int 5600 flow_create_split_inner(struct rte_eth_dev *dev, 5601 struct rte_flow *flow, 5602 struct mlx5_flow **sub_flow, 5603 const struct rte_flow_attr *attr, 5604 const struct rte_flow_item items[], 5605 const struct rte_flow_action actions[], 5606 struct mlx5_flow_split_info *flow_split_info, 5607 struct rte_flow_error *error) 5608 { 5609 struct mlx5_flow *dev_flow; 5610 struct mlx5_flow_workspace *wks = mlx5_flow_get_thread_workspace(); 5611 5612 dev_flow = flow_drv_prepare(dev, flow, attr, items, actions, 5613 flow_split_info->flow_idx, error); 5614 if (!dev_flow) 5615 return -rte_errno; 5616 dev_flow->flow = flow; 5617 dev_flow->external = flow_split_info->external; 5618 dev_flow->skip_scale = flow_split_info->skip_scale; 5619 /* Subflow object was created, we must include one in the list. */ 5620 SILIST_INSERT(&flow->dev_handles, dev_flow->handle_idx, 5621 dev_flow->handle, next); 5622 /* 5623 * If dev_flow is as one of the suffix flow, some actions in suffix 5624 * flow may need some user defined item layer flags, and pass the 5625 * Metadata rxq mark flag to suffix flow as well. 5626 */ 5627 if (flow_split_info->prefix_layers) 5628 dev_flow->handle->layers = flow_split_info->prefix_layers; 5629 if (flow_split_info->prefix_mark) { 5630 MLX5_ASSERT(wks); 5631 wks->mark = 1; 5632 } 5633 if (sub_flow) 5634 *sub_flow = dev_flow; 5635 #ifdef HAVE_IBV_FLOW_DV_SUPPORT 5636 dev_flow->dv.table_id = flow_split_info->table_id; 5637 #endif 5638 return flow_drv_translate(dev, dev_flow, attr, items, actions, error); 5639 } 5640 5641 /** 5642 * Get the sub policy of a meter. 5643 * 5644 * @param[in] dev 5645 * Pointer to Ethernet device. 5646 * @param[in] flow 5647 * Parent flow structure pointer. 5648 * @param wks 5649 * Pointer to thread flow work space. 5650 * @param[in] attr 5651 * Flow rule attributes. 5652 * @param[in] items 5653 * Pattern specification (list terminated by the END pattern item). 5654 * @param[out] error 5655 * Perform verbose error reporting if not NULL. 5656 * 5657 * @return 5658 * Pointer to the meter sub policy, NULL otherwise and rte_errno is set. 5659 */ 5660 static struct mlx5_flow_meter_sub_policy * 5661 get_meter_sub_policy(struct rte_eth_dev *dev, 5662 struct rte_flow *flow, 5663 struct mlx5_flow_workspace *wks, 5664 const struct rte_flow_attr *attr, 5665 const struct rte_flow_item items[], 5666 struct rte_flow_error *error) 5667 { 5668 struct mlx5_flow_meter_policy *policy; 5669 struct mlx5_flow_meter_policy *final_policy; 5670 struct mlx5_flow_meter_sub_policy *sub_policy = NULL; 5671 5672 policy = wks->policy; 5673 final_policy = policy->is_hierarchy ? wks->final_policy : policy; 5674 if (final_policy->is_rss || final_policy->is_queue) { 5675 struct mlx5_flow_rss_desc rss_desc_v[MLX5_MTR_RTE_COLORS]; 5676 struct mlx5_flow_rss_desc *rss_desc[MLX5_MTR_RTE_COLORS] = {0}; 5677 uint32_t i; 5678 5679 /* 5680 * This is a tmp dev_flow, 5681 * no need to register any matcher for it in translate. 5682 */ 5683 wks->skip_matcher_reg = 1; 5684 for (i = 0; i < MLX5_MTR_RTE_COLORS; i++) { 5685 struct mlx5_flow dev_flow = {0}; 5686 struct mlx5_flow_handle dev_handle = { {0} }; 5687 uint8_t fate = final_policy->act_cnt[i].fate_action; 5688 5689 if (fate == MLX5_FLOW_FATE_SHARED_RSS) { 5690 const struct rte_flow_action_rss *rss_act = 5691 final_policy->act_cnt[i].rss->conf; 5692 struct rte_flow_action rss_actions[2] = { 5693 [0] = { 5694 .type = RTE_FLOW_ACTION_TYPE_RSS, 5695 .conf = rss_act, 5696 }, 5697 [1] = { 5698 .type = RTE_FLOW_ACTION_TYPE_END, 5699 .conf = NULL, 5700 } 5701 }; 5702 5703 dev_flow.handle = &dev_handle; 5704 dev_flow.ingress = attr->ingress; 5705 dev_flow.flow = flow; 5706 dev_flow.external = 0; 5707 #ifdef HAVE_IBV_FLOW_DV_SUPPORT 5708 dev_flow.dv.transfer = attr->transfer; 5709 #endif 5710 /** 5711 * Translate RSS action to get rss hash fields. 5712 */ 5713 if (flow_drv_translate(dev, &dev_flow, attr, 5714 items, rss_actions, error)) 5715 goto exit; 5716 rss_desc_v[i] = wks->rss_desc; 5717 rss_desc_v[i].symmetric_hash_function = 5718 dev_flow.symmetric_hash_function; 5719 rss_desc_v[i].key_len = MLX5_RSS_HASH_KEY_LEN; 5720 rss_desc_v[i].hash_fields = 5721 dev_flow.hash_fields; 5722 rss_desc_v[i].queue_num = 5723 rss_desc_v[i].hash_fields ? 5724 rss_desc_v[i].queue_num : 1; 5725 rss_desc_v[i].tunnel = 5726 !!(dev_flow.handle->layers & 5727 MLX5_FLOW_LAYER_TUNNEL); 5728 /* Use the RSS queues in the containers. */ 5729 rss_desc_v[i].queue = 5730 (uint16_t *)(uintptr_t)rss_act->queue; 5731 rss_desc[i] = &rss_desc_v[i]; 5732 } else if (fate == MLX5_FLOW_FATE_QUEUE) { 5733 /* This is queue action. */ 5734 rss_desc_v[i] = wks->rss_desc; 5735 rss_desc_v[i].key_len = 0; 5736 rss_desc_v[i].hash_fields = 0; 5737 rss_desc_v[i].queue = 5738 &final_policy->act_cnt[i].queue; 5739 rss_desc_v[i].queue_num = 1; 5740 rss_desc[i] = &rss_desc_v[i]; 5741 } else { 5742 rss_desc[i] = NULL; 5743 } 5744 } 5745 sub_policy = flow_drv_meter_sub_policy_rss_prepare(dev, 5746 flow, policy, rss_desc); 5747 } else { 5748 enum mlx5_meter_domain mtr_domain = 5749 attr->transfer ? MLX5_MTR_DOMAIN_TRANSFER : 5750 (attr->egress ? MLX5_MTR_DOMAIN_EGRESS : 5751 MLX5_MTR_DOMAIN_INGRESS); 5752 sub_policy = policy->sub_policys[mtr_domain][0]; 5753 } 5754 if (!sub_policy) 5755 rte_flow_error_set(error, EINVAL, 5756 RTE_FLOW_ERROR_TYPE_UNSPECIFIED, NULL, 5757 "Failed to get meter sub-policy."); 5758 exit: 5759 return sub_policy; 5760 } 5761 5762 /** 5763 * Split the meter flow. 5764 * 5765 * As meter flow will split to three sub flow, other than meter 5766 * action, the other actions make sense to only meter accepts 5767 * the packet. If it need to be dropped, no other additional 5768 * actions should be take. 5769 * 5770 * One kind of special action which decapsulates the L3 tunnel 5771 * header will be in the prefix sub flow, as not to take the 5772 * L3 tunnel header into account. 5773 * 5774 * @param[in] dev 5775 * Pointer to Ethernet device. 5776 * @param[in] flow 5777 * Parent flow structure pointer. 5778 * @param wks 5779 * Pointer to thread flow work space. 5780 * @param[in] attr 5781 * Flow rule attributes. 5782 * @param[in] items 5783 * Pattern specification (list terminated by the END pattern item). 5784 * @param[out] sfx_items 5785 * Suffix flow match items (list terminated by the END pattern item). 5786 * @param[in] actions 5787 * Associated actions (list terminated by the END action). 5788 * @param[out] actions_sfx 5789 * Suffix flow actions. 5790 * @param[out] actions_pre 5791 * Prefix flow actions. 5792 * @param[out] mtr_flow_id 5793 * Pointer to meter flow id. 5794 * @param[out] error 5795 * Perform verbose error reporting if not NULL. 5796 * 5797 * @return 5798 * 0 on success, a negative errno value otherwise and rte_errno is set. 5799 */ 5800 static int 5801 flow_meter_split_prep(struct rte_eth_dev *dev, 5802 struct rte_flow *flow, 5803 struct mlx5_flow_workspace *wks, 5804 const struct rte_flow_attr *attr, 5805 const struct rte_flow_item items[], 5806 struct rte_flow_item sfx_items[], 5807 const struct rte_flow_action actions[], 5808 struct rte_flow_action actions_sfx[], 5809 struct rte_flow_action actions_pre[], 5810 uint32_t *mtr_flow_id, 5811 struct rte_flow_error *error) 5812 { 5813 struct mlx5_priv *priv = dev->data->dev_private; 5814 struct mlx5_flow_meter_info *fm = wks->fm; 5815 struct rte_flow_action *tag_action = NULL; 5816 struct rte_flow_item *tag_item; 5817 struct mlx5_rte_flow_action_set_tag *set_tag; 5818 const struct rte_flow_action_raw_encap *raw_encap; 5819 const struct rte_flow_action_raw_decap *raw_decap; 5820 struct mlx5_rte_flow_item_tag *tag_item_spec; 5821 struct mlx5_rte_flow_item_tag *tag_item_mask; 5822 uint32_t tag_id = 0; 5823 struct rte_flow_item *vlan_item_dst = NULL; 5824 const struct rte_flow_item *vlan_item_src = NULL; 5825 const struct rte_flow_item *orig_items = items; 5826 struct rte_flow_action *hw_mtr_action; 5827 struct rte_flow_action *action_pre_head = NULL; 5828 uint16_t flow_src_port = priv->representor_id; 5829 bool mtr_first; 5830 uint8_t mtr_id_offset = priv->mtr_reg_share ? MLX5_MTR_COLOR_BITS : 0; 5831 uint8_t mtr_reg_bits = priv->mtr_reg_share ? 5832 MLX5_MTR_IDLE_BITS_IN_COLOR_REG : MLX5_REG_BITS; 5833 uint32_t flow_id = 0; 5834 uint32_t flow_id_reversed = 0; 5835 uint8_t flow_id_bits = 0; 5836 bool after_meter = false; 5837 int shift; 5838 5839 /* Prepare the suffix subflow items. */ 5840 tag_item = sfx_items++; 5841 for (; items->type != RTE_FLOW_ITEM_TYPE_END; items++) { 5842 int item_type = items->type; 5843 5844 switch (item_type) { 5845 case RTE_FLOW_ITEM_TYPE_PORT_ID: 5846 case RTE_FLOW_ITEM_TYPE_REPRESENTED_PORT: 5847 case RTE_FLOW_ITEM_TYPE_PORT_REPRESENTOR: 5848 if (mlx5_flow_get_item_vport_id(dev, items, &flow_src_port, NULL, error)) 5849 return -rte_errno; 5850 if (!fm->def_policy && wks->policy->hierarchy_match_port && 5851 flow_src_port != priv->representor_id) { 5852 if (flow_drv_mtr_hierarchy_rule_create(dev, 5853 flow, fm, 5854 flow_src_port, 5855 items, 5856 error)) 5857 return -rte_errno; 5858 } 5859 memcpy(sfx_items, items, sizeof(*sfx_items)); 5860 sfx_items++; 5861 break; 5862 case RTE_FLOW_ITEM_TYPE_VLAN: 5863 /* Determine if copy vlan item below. */ 5864 vlan_item_src = items; 5865 vlan_item_dst = sfx_items++; 5866 vlan_item_dst->type = RTE_FLOW_ITEM_TYPE_VOID; 5867 break; 5868 default: 5869 break; 5870 } 5871 } 5872 sfx_items->type = RTE_FLOW_ITEM_TYPE_END; 5873 sfx_items++; 5874 mtr_first = priv->sh->meter_aso_en && 5875 (attr->egress || (attr->transfer && flow_src_port != UINT16_MAX)); 5876 /* For ASO meter, meter must be before tag in TX direction. */ 5877 if (mtr_first) { 5878 action_pre_head = actions_pre++; 5879 /* Leave space for tag action. */ 5880 tag_action = actions_pre++; 5881 } 5882 /* Prepare the actions for prefix and suffix flow. */ 5883 for (; actions->type != RTE_FLOW_ACTION_TYPE_END; actions++) { 5884 struct rte_flow_action *action_cur = NULL; 5885 5886 switch (actions->type) { 5887 case RTE_FLOW_ACTION_TYPE_METER: 5888 if (mtr_first) { 5889 action_cur = action_pre_head; 5890 } else { 5891 /* Leave space for tag action. */ 5892 tag_action = actions_pre++; 5893 action_cur = actions_pre++; 5894 } 5895 after_meter = true; 5896 break; 5897 case RTE_FLOW_ACTION_TYPE_VXLAN_DECAP: 5898 case RTE_FLOW_ACTION_TYPE_NVGRE_DECAP: 5899 action_cur = actions_pre++; 5900 break; 5901 case RTE_FLOW_ACTION_TYPE_RAW_ENCAP: 5902 raw_encap = actions->conf; 5903 if (raw_encap->size < MLX5_ENCAPSULATION_DECISION_SIZE) 5904 action_cur = actions_pre++; 5905 break; 5906 case RTE_FLOW_ACTION_TYPE_RAW_DECAP: 5907 raw_decap = actions->conf; 5908 if (raw_decap->size > MLX5_ENCAPSULATION_DECISION_SIZE) 5909 action_cur = actions_pre++; 5910 break; 5911 case RTE_FLOW_ACTION_TYPE_OF_PUSH_VLAN: 5912 case RTE_FLOW_ACTION_TYPE_OF_SET_VLAN_VID: 5913 if (vlan_item_dst && vlan_item_src) { 5914 memcpy(vlan_item_dst, vlan_item_src, 5915 sizeof(*vlan_item_dst)); 5916 /* 5917 * Convert to internal match item, it is used 5918 * for vlan push and set vid. 5919 */ 5920 vlan_item_dst->type = (enum rte_flow_item_type) 5921 MLX5_RTE_FLOW_ITEM_TYPE_VLAN; 5922 } 5923 break; 5924 case RTE_FLOW_ACTION_TYPE_COUNT: 5925 if (fm->def_policy) 5926 action_cur = after_meter ? 5927 actions_sfx++ : actions_pre++; 5928 break; 5929 default: 5930 break; 5931 } 5932 if (!action_cur) 5933 action_cur = (fm->def_policy) ? 5934 actions_sfx++ : actions_pre++; 5935 memcpy(action_cur, actions, sizeof(struct rte_flow_action)); 5936 } 5937 /* Add end action to the actions. */ 5938 actions_sfx->type = RTE_FLOW_ACTION_TYPE_END; 5939 if (priv->sh->meter_aso_en) { 5940 /** 5941 * For ASO meter, need to add an extra jump action explicitly, 5942 * to jump from meter to policer table. 5943 */ 5944 struct mlx5_flow_meter_sub_policy *sub_policy; 5945 struct mlx5_flow_tbl_data_entry *tbl_data; 5946 5947 if (!fm->def_policy) { 5948 sub_policy = get_meter_sub_policy(dev, flow, wks, 5949 attr, orig_items, 5950 error); 5951 if (!sub_policy) 5952 return -rte_errno; 5953 } else { 5954 enum mlx5_meter_domain mtr_domain = 5955 attr->transfer ? MLX5_MTR_DOMAIN_TRANSFER : 5956 (attr->egress ? MLX5_MTR_DOMAIN_EGRESS : 5957 MLX5_MTR_DOMAIN_INGRESS); 5958 5959 sub_policy = 5960 &priv->sh->mtrmng->def_policy[mtr_domain]->sub_policy; 5961 } 5962 tbl_data = container_of(sub_policy->tbl_rsc, 5963 struct mlx5_flow_tbl_data_entry, tbl); 5964 hw_mtr_action = actions_pre++; 5965 hw_mtr_action->type = (enum rte_flow_action_type) 5966 MLX5_RTE_FLOW_ACTION_TYPE_JUMP; 5967 hw_mtr_action->conf = tbl_data->jump.action; 5968 } 5969 actions_pre->type = RTE_FLOW_ACTION_TYPE_END; 5970 actions_pre++; 5971 if (!tag_action) 5972 return rte_flow_error_set(error, ENOMEM, 5973 RTE_FLOW_ERROR_TYPE_UNSPECIFIED, 5974 NULL, "No tag action space."); 5975 if (!mtr_flow_id) { 5976 tag_action->type = RTE_FLOW_ACTION_TYPE_VOID; 5977 goto exit; 5978 } 5979 /* Only default-policy Meter creates mtr flow id. */ 5980 if (fm->def_policy) { 5981 mlx5_ipool_malloc(fm->flow_ipool, &tag_id); 5982 if (!tag_id) 5983 return rte_flow_error_set(error, ENOMEM, 5984 RTE_FLOW_ERROR_TYPE_UNSPECIFIED, NULL, 5985 "Failed to allocate meter flow id."); 5986 flow_id = tag_id - 1; 5987 flow_id_bits = (!flow_id) ? 1 : 5988 (MLX5_REG_BITS - rte_clz32(flow_id)); 5989 if ((flow_id_bits + priv->sh->mtrmng->max_mtr_bits) > 5990 mtr_reg_bits) { 5991 mlx5_ipool_free(fm->flow_ipool, tag_id); 5992 return rte_flow_error_set(error, EINVAL, 5993 RTE_FLOW_ERROR_TYPE_UNSPECIFIED, NULL, 5994 "Meter flow id exceeds max limit."); 5995 } 5996 if (flow_id_bits > priv->sh->mtrmng->max_mtr_flow_bits) 5997 priv->sh->mtrmng->max_mtr_flow_bits = flow_id_bits; 5998 } 5999 /* Build tag actions and items for meter_id/meter flow_id. */ 6000 set_tag = (struct mlx5_rte_flow_action_set_tag *)actions_pre; 6001 tag_item_spec = (struct mlx5_rte_flow_item_tag *)sfx_items; 6002 tag_item_mask = tag_item_spec + 1; 6003 /* Both flow_id and meter_id share the same register. */ 6004 *set_tag = (struct mlx5_rte_flow_action_set_tag) { 6005 .id = (enum modify_reg)mlx5_flow_get_reg_id(dev, MLX5_MTR_ID, 6006 0, error), 6007 .offset = mtr_id_offset, 6008 .length = mtr_reg_bits, 6009 .data = flow->meter, 6010 }; 6011 /* 6012 * The color Reg bits used by flow_id are growing from 6013 * msb to lsb, so must do bit reverse for flow_id val in RegC. 6014 */ 6015 for (shift = 0; shift < flow_id_bits; shift++) 6016 flow_id_reversed = (flow_id_reversed << 1) | 6017 ((flow_id >> shift) & 0x1); 6018 set_tag->data |= 6019 flow_id_reversed << (mtr_reg_bits - flow_id_bits); 6020 tag_item_spec->id = set_tag->id; 6021 tag_item_spec->data = set_tag->data << mtr_id_offset; 6022 tag_item_mask->data = UINT32_MAX << mtr_id_offset; 6023 tag_action->type = (enum rte_flow_action_type) 6024 MLX5_RTE_FLOW_ACTION_TYPE_TAG; 6025 tag_action->conf = set_tag; 6026 tag_item->type = (enum rte_flow_item_type) 6027 MLX5_RTE_FLOW_ITEM_TYPE_TAG; 6028 tag_item->spec = tag_item_spec; 6029 tag_item->last = NULL; 6030 tag_item->mask = tag_item_mask; 6031 exit: 6032 if (mtr_flow_id) 6033 *mtr_flow_id = tag_id; 6034 return 0; 6035 } 6036 6037 /** 6038 * Split action list having QUEUE/RSS for metadata register copy. 6039 * 6040 * Once Q/RSS action is detected in user's action list, the flow action 6041 * should be split in order to copy metadata registers, which will happen in 6042 * RX_CP_TBL like, 6043 * - CQE->flow_tag := reg_c[1] (MARK) 6044 * - CQE->flow_table_metadata (reg_b) := reg_c[0] (META) 6045 * The Q/RSS action will be performed on RX_ACT_TBL after passing by RX_CP_TBL. 6046 * This is because the last action of each flow must be a terminal action 6047 * (QUEUE, RSS or DROP). 6048 * 6049 * Flow ID must be allocated to identify actions in the RX_ACT_TBL and it is 6050 * stored and kept in the mlx5_flow structure per each sub_flow. 6051 * 6052 * The Q/RSS action is replaced with, 6053 * - SET_TAG, setting the allocated flow ID to reg_c[2]. 6054 * And the following JUMP action is added at the end, 6055 * - JUMP, to RX_CP_TBL. 6056 * 6057 * A flow to perform remained Q/RSS action will be created in RX_ACT_TBL by 6058 * flow_create_split_metadata() routine. The flow will look like, 6059 * - If flow ID matches (reg_c[2]), perform Q/RSS. 6060 * 6061 * @param dev 6062 * Pointer to Ethernet device. 6063 * @param[out] split_actions 6064 * Pointer to store split actions to jump to CP_TBL. 6065 * @param[in] actions 6066 * Pointer to the list of original flow actions. 6067 * @param[in] qrss 6068 * Pointer to the Q/RSS action. 6069 * @param[in] actions_n 6070 * Number of original actions. 6071 * @param[in] mtr_sfx 6072 * Check if it is in meter suffix table. 6073 * @param[out] error 6074 * Perform verbose error reporting if not NULL. 6075 * 6076 * @return 6077 * non-zero unique flow_id on success, otherwise 0 and 6078 * error/rte_error are set. 6079 */ 6080 static uint32_t 6081 flow_mreg_split_qrss_prep(struct rte_eth_dev *dev, 6082 struct rte_flow_action *split_actions, 6083 const struct rte_flow_action *actions, 6084 const struct rte_flow_action *qrss, 6085 int actions_n, int mtr_sfx, 6086 struct rte_flow_error *error) 6087 { 6088 struct mlx5_priv *priv = dev->data->dev_private; 6089 struct mlx5_rte_flow_action_set_tag *set_tag; 6090 struct rte_flow_action_jump *jump; 6091 const int qrss_idx = qrss - actions; 6092 uint32_t flow_id = 0; 6093 int ret = 0; 6094 6095 /* 6096 * Given actions will be split 6097 * - Replace QUEUE/RSS action with SET_TAG to set flow ID. 6098 * - Add jump to mreg CP_TBL. 6099 * As a result, there will be one more action. 6100 */ 6101 memcpy(split_actions, actions, sizeof(*split_actions) * actions_n); 6102 /* Count MLX5_RTE_FLOW_ACTION_TYPE_TAG. */ 6103 ++actions_n; 6104 set_tag = (void *)(split_actions + actions_n); 6105 /* 6106 * If we are not the meter suffix flow, add the tag action. 6107 * Since meter suffix flow already has the tag added. 6108 */ 6109 if (!mtr_sfx) { 6110 /* 6111 * Allocate the new subflow ID. This one is unique within 6112 * device and not shared with representors. Otherwise, 6113 * we would have to resolve multi-thread access synch 6114 * issue. Each flow on the shared device is appended 6115 * with source vport identifier, so the resulting 6116 * flows will be unique in the shared (by master and 6117 * representors) domain even if they have coinciding 6118 * IDs. 6119 */ 6120 mlx5_ipool_malloc(priv->sh->ipool 6121 [MLX5_IPOOL_RSS_EXPANTION_FLOW_ID], &flow_id); 6122 if (!flow_id) 6123 return rte_flow_error_set(error, ENOMEM, 6124 RTE_FLOW_ERROR_TYPE_ACTION, 6125 NULL, "can't allocate id " 6126 "for split Q/RSS subflow"); 6127 /* Internal SET_TAG action to set flow ID. */ 6128 *set_tag = (struct mlx5_rte_flow_action_set_tag){ 6129 .data = flow_id, 6130 }; 6131 ret = mlx5_flow_get_reg_id(dev, MLX5_COPY_MARK, 0, error); 6132 if (ret < 0) 6133 return ret; 6134 set_tag->id = ret; 6135 /* Construct new actions array. */ 6136 /* Replace QUEUE/RSS action. */ 6137 split_actions[qrss_idx] = (struct rte_flow_action){ 6138 .type = (enum rte_flow_action_type) 6139 MLX5_RTE_FLOW_ACTION_TYPE_TAG, 6140 .conf = set_tag, 6141 }; 6142 } else { 6143 /* 6144 * If we are the suffix flow of meter, tag already exist. 6145 * Set the QUEUE/RSS action to void. 6146 */ 6147 split_actions[qrss_idx].type = RTE_FLOW_ACTION_TYPE_VOID; 6148 } 6149 /* JUMP action to jump to mreg copy table (CP_TBL). */ 6150 jump = (void *)(set_tag + 1); 6151 *jump = (struct rte_flow_action_jump){ 6152 .group = MLX5_FLOW_MREG_CP_TABLE_GROUP, 6153 }; 6154 split_actions[actions_n - 2] = (struct rte_flow_action){ 6155 .type = RTE_FLOW_ACTION_TYPE_JUMP, 6156 .conf = jump, 6157 }; 6158 split_actions[actions_n - 1] = (struct rte_flow_action){ 6159 .type = RTE_FLOW_ACTION_TYPE_END, 6160 }; 6161 return flow_id; 6162 } 6163 6164 /** 6165 * Extend the given action list for Tx metadata copy. 6166 * 6167 * Copy the given action list to the ext_actions and add flow metadata register 6168 * copy action in order to copy reg_a set by WQE to reg_c[0]. 6169 * 6170 * @param[out] ext_actions 6171 * Pointer to the extended action list. 6172 * @param[in] actions 6173 * Pointer to the list of actions. 6174 * @param[in] actions_n 6175 * Number of actions in the list. 6176 * @param[out] error 6177 * Perform verbose error reporting if not NULL. 6178 * @param[in] encap_idx 6179 * The encap action index. 6180 * 6181 * @return 6182 * 0 on success, negative value otherwise 6183 */ 6184 static int 6185 flow_mreg_tx_copy_prep(struct rte_eth_dev *dev, 6186 struct rte_flow_action *ext_actions, 6187 const struct rte_flow_action *actions, 6188 int actions_n, struct rte_flow_error *error, 6189 int encap_idx) 6190 { 6191 struct mlx5_flow_action_copy_mreg *cp_mreg = 6192 (struct mlx5_flow_action_copy_mreg *) 6193 (ext_actions + actions_n + 1); 6194 int ret; 6195 6196 ret = mlx5_flow_get_reg_id(dev, MLX5_METADATA_RX, 0, error); 6197 if (ret < 0) 6198 return ret; 6199 cp_mreg->dst = ret; 6200 ret = mlx5_flow_get_reg_id(dev, MLX5_METADATA_TX, 0, error); 6201 if (ret < 0) 6202 return ret; 6203 cp_mreg->src = ret; 6204 if (encap_idx != 0) 6205 memcpy(ext_actions, actions, sizeof(*ext_actions) * encap_idx); 6206 if (encap_idx == actions_n - 1) { 6207 ext_actions[actions_n - 1] = (struct rte_flow_action){ 6208 .type = (enum rte_flow_action_type) 6209 MLX5_RTE_FLOW_ACTION_TYPE_COPY_MREG, 6210 .conf = cp_mreg, 6211 }; 6212 ext_actions[actions_n] = (struct rte_flow_action){ 6213 .type = RTE_FLOW_ACTION_TYPE_END, 6214 }; 6215 } else { 6216 ext_actions[encap_idx] = (struct rte_flow_action){ 6217 .type = (enum rte_flow_action_type) 6218 MLX5_RTE_FLOW_ACTION_TYPE_COPY_MREG, 6219 .conf = cp_mreg, 6220 }; 6221 memcpy(ext_actions + encap_idx + 1, actions + encap_idx, 6222 sizeof(*ext_actions) * (actions_n - encap_idx)); 6223 } 6224 return 0; 6225 } 6226 6227 /** 6228 * Check the match action from the action list. 6229 * 6230 * @param[in] actions 6231 * Pointer to the list of actions. 6232 * @param[in] attr 6233 * Flow rule attributes. 6234 * @param[in] action 6235 * The action to be check if exist. 6236 * @param[out] match_action_pos 6237 * Pointer to the position of the matched action if exists, otherwise is -1. 6238 * @param[out] qrss_action_pos 6239 * Pointer to the position of the Queue/RSS action if exists, otherwise is -1. 6240 * @param[out] modify_after_mirror 6241 * Pointer to the flag of modify action after FDB mirroring. 6242 * 6243 * @return 6244 * > 0 the total number of actions. 6245 * 0 if not found match action in action list. 6246 */ 6247 static int 6248 flow_check_match_action(const struct rte_flow_action actions[], 6249 const struct rte_flow_attr *attr, 6250 enum rte_flow_action_type action, 6251 int *match_action_pos, int *qrss_action_pos, 6252 int *modify_after_mirror) 6253 { 6254 const struct rte_flow_action_sample *sample; 6255 const struct rte_flow_action_raw_decap *decap; 6256 const struct rte_flow_action *action_cur = NULL; 6257 int actions_n = 0; 6258 uint32_t ratio = 0; 6259 int sub_type = 0; 6260 int flag = 0; 6261 int fdb_mirror = 0; 6262 6263 *match_action_pos = -1; 6264 *qrss_action_pos = -1; 6265 for (; actions->type != RTE_FLOW_ACTION_TYPE_END; actions++) { 6266 if (actions->type == action) { 6267 flag = 1; 6268 *match_action_pos = actions_n; 6269 } 6270 switch (actions->type) { 6271 case RTE_FLOW_ACTION_TYPE_QUEUE: 6272 case RTE_FLOW_ACTION_TYPE_RSS: 6273 *qrss_action_pos = actions_n; 6274 break; 6275 case RTE_FLOW_ACTION_TYPE_SAMPLE: 6276 sample = actions->conf; 6277 ratio = sample->ratio; 6278 sub_type = ((const struct rte_flow_action *) 6279 (sample->actions))->type; 6280 if (ratio == 1 && attr->transfer && 6281 sub_type != RTE_FLOW_ACTION_TYPE_END) 6282 fdb_mirror = 1; 6283 break; 6284 case RTE_FLOW_ACTION_TYPE_SET_MAC_SRC: 6285 case RTE_FLOW_ACTION_TYPE_SET_MAC_DST: 6286 case RTE_FLOW_ACTION_TYPE_SET_IPV4_SRC: 6287 case RTE_FLOW_ACTION_TYPE_SET_IPV4_DST: 6288 case RTE_FLOW_ACTION_TYPE_SET_IPV6_SRC: 6289 case RTE_FLOW_ACTION_TYPE_SET_IPV6_DST: 6290 case RTE_FLOW_ACTION_TYPE_SET_TP_SRC: 6291 case RTE_FLOW_ACTION_TYPE_SET_TP_DST: 6292 case RTE_FLOW_ACTION_TYPE_DEC_TTL: 6293 case RTE_FLOW_ACTION_TYPE_SET_TTL: 6294 case RTE_FLOW_ACTION_TYPE_INC_TCP_SEQ: 6295 case RTE_FLOW_ACTION_TYPE_DEC_TCP_SEQ: 6296 case RTE_FLOW_ACTION_TYPE_INC_TCP_ACK: 6297 case RTE_FLOW_ACTION_TYPE_DEC_TCP_ACK: 6298 case RTE_FLOW_ACTION_TYPE_SET_IPV4_DSCP: 6299 case RTE_FLOW_ACTION_TYPE_SET_IPV6_DSCP: 6300 case RTE_FLOW_ACTION_TYPE_FLAG: 6301 case RTE_FLOW_ACTION_TYPE_MARK: 6302 case RTE_FLOW_ACTION_TYPE_SET_META: 6303 case RTE_FLOW_ACTION_TYPE_SET_TAG: 6304 case RTE_FLOW_ACTION_TYPE_OF_POP_VLAN: 6305 case RTE_FLOW_ACTION_TYPE_OF_PUSH_VLAN: 6306 case RTE_FLOW_ACTION_TYPE_OF_SET_VLAN_VID: 6307 case RTE_FLOW_ACTION_TYPE_OF_SET_VLAN_PCP: 6308 case RTE_FLOW_ACTION_TYPE_VXLAN_DECAP: 6309 case RTE_FLOW_ACTION_TYPE_NVGRE_DECAP: 6310 case RTE_FLOW_ACTION_TYPE_MODIFY_FIELD: 6311 case RTE_FLOW_ACTION_TYPE_METER: 6312 if (fdb_mirror) 6313 *modify_after_mirror = 1; 6314 break; 6315 case RTE_FLOW_ACTION_TYPE_RAW_DECAP: 6316 decap = actions->conf; 6317 action_cur = actions; 6318 while ((++action_cur)->type == RTE_FLOW_ACTION_TYPE_VOID) 6319 ; 6320 if (action_cur->type == RTE_FLOW_ACTION_TYPE_RAW_ENCAP) { 6321 const struct rte_flow_action_raw_encap *encap = 6322 action_cur->conf; 6323 if (decap->size <= 6324 MLX5_ENCAPSULATION_DECISION_SIZE && 6325 encap->size > 6326 MLX5_ENCAPSULATION_DECISION_SIZE) 6327 /* L3 encap. */ 6328 break; 6329 } 6330 if (fdb_mirror) 6331 *modify_after_mirror = 1; 6332 break; 6333 default: 6334 break; 6335 } 6336 actions_n++; 6337 } 6338 if (flag && fdb_mirror && !*modify_after_mirror) { 6339 /* FDB mirroring uses the destination array to implement 6340 * instead of FLOW_SAMPLER object. 6341 */ 6342 if (sub_type != RTE_FLOW_ACTION_TYPE_END) 6343 flag = 0; 6344 } 6345 /* Count RTE_FLOW_ACTION_TYPE_END. */ 6346 return flag ? actions_n + 1 : 0; 6347 } 6348 6349 #define SAMPLE_SUFFIX_ITEM 3 6350 6351 /** 6352 * Split the sample flow. 6353 * 6354 * As sample flow will split to two sub flow, sample flow with 6355 * sample action, the other actions will move to new suffix flow. 6356 * 6357 * Also add unique tag id with tag action in the sample flow, 6358 * the same tag id will be as match in the suffix flow. 6359 * 6360 * @param dev 6361 * Pointer to Ethernet device. 6362 * @param[in] add_tag 6363 * Add extra tag action flag. 6364 * @param[out] sfx_items 6365 * Suffix flow match items (list terminated by the END pattern item). 6366 * @param[in] actions 6367 * Associated actions (list terminated by the END action). 6368 * @param[out] actions_sfx 6369 * Suffix flow actions. 6370 * @param[out] actions_pre 6371 * Prefix flow actions. 6372 * @param[in] actions_n 6373 * The total number of actions. 6374 * @param[in] sample_action_pos 6375 * The sample action position. 6376 * @param[in] qrss_action_pos 6377 * The Queue/RSS action position. 6378 * @param[in] jump_table 6379 * Add extra jump action flag. 6380 * @param[out] error 6381 * Perform verbose error reporting if not NULL. 6382 * 6383 * @return 6384 * 0 on success, or unique flow_id, a negative errno value 6385 * otherwise and rte_errno is set. 6386 */ 6387 static int 6388 flow_sample_split_prep(struct rte_eth_dev *dev, 6389 int add_tag, 6390 const struct rte_flow_item items[], 6391 struct rte_flow_item sfx_items[], 6392 const struct rte_flow_action actions[], 6393 struct rte_flow_action actions_sfx[], 6394 struct rte_flow_action actions_pre[], 6395 int actions_n, 6396 int sample_action_pos, 6397 int qrss_action_pos, 6398 int jump_table, 6399 struct rte_flow_error *error) 6400 { 6401 struct mlx5_priv *priv = dev->data->dev_private; 6402 struct mlx5_rte_flow_action_set_tag *set_tag; 6403 struct mlx5_rte_flow_item_tag *tag_spec; 6404 struct mlx5_rte_flow_item_tag *tag_mask; 6405 struct rte_flow_action_jump *jump_action; 6406 uint32_t tag_id = 0; 6407 int append_index = 0; 6408 int set_tag_idx = -1; 6409 int index; 6410 int ret; 6411 6412 if (sample_action_pos < 0) 6413 return rte_flow_error_set(error, EINVAL, 6414 RTE_FLOW_ERROR_TYPE_ACTION, 6415 NULL, "invalid position of sample " 6416 "action in list"); 6417 /* Prepare the actions for prefix and suffix flow. */ 6418 if (add_tag) { 6419 /* Update the new added tag action index preceding 6420 * the PUSH_VLAN or ENCAP action. 6421 */ 6422 const struct rte_flow_action_raw_encap *raw_encap; 6423 const struct rte_flow_action *action = actions; 6424 int encap_idx; 6425 int action_idx = 0; 6426 int raw_decap_idx = -1; 6427 int push_vlan_idx = -1; 6428 for (; action->type != RTE_FLOW_ACTION_TYPE_END; action++) { 6429 switch (action->type) { 6430 case RTE_FLOW_ACTION_TYPE_RAW_DECAP: 6431 raw_decap_idx = action_idx; 6432 break; 6433 case RTE_FLOW_ACTION_TYPE_RAW_ENCAP: 6434 raw_encap = action->conf; 6435 if (raw_encap->size > 6436 MLX5_ENCAPSULATION_DECISION_SIZE) { 6437 encap_idx = raw_decap_idx != -1 ? 6438 raw_decap_idx : action_idx; 6439 if (encap_idx < sample_action_pos && 6440 push_vlan_idx == -1) 6441 set_tag_idx = encap_idx; 6442 } 6443 break; 6444 case RTE_FLOW_ACTION_TYPE_VXLAN_ENCAP: 6445 case RTE_FLOW_ACTION_TYPE_NVGRE_ENCAP: 6446 encap_idx = action_idx; 6447 if (encap_idx < sample_action_pos && 6448 push_vlan_idx == -1) 6449 set_tag_idx = encap_idx; 6450 break; 6451 case RTE_FLOW_ACTION_TYPE_OF_PUSH_VLAN: 6452 case RTE_FLOW_ACTION_TYPE_OF_SET_VLAN_VID: 6453 if (action_idx < sample_action_pos && 6454 push_vlan_idx == -1) { 6455 set_tag_idx = action_idx; 6456 push_vlan_idx = action_idx; 6457 } 6458 break; 6459 default: 6460 break; 6461 } 6462 action_idx++; 6463 } 6464 } 6465 /* Prepare the actions for prefix and suffix flow. */ 6466 if (qrss_action_pos >= 0 && qrss_action_pos < sample_action_pos) { 6467 index = qrss_action_pos; 6468 /* Put the preceding the Queue/RSS action into prefix flow. */ 6469 if (index != 0) 6470 memcpy(actions_pre, actions, 6471 sizeof(struct rte_flow_action) * index); 6472 /* Put others preceding the sample action into prefix flow. */ 6473 if (sample_action_pos > index + 1) 6474 memcpy(actions_pre + index, actions + index + 1, 6475 sizeof(struct rte_flow_action) * 6476 (sample_action_pos - index - 1)); 6477 index = sample_action_pos - 1; 6478 /* Put Queue/RSS action into Suffix flow. */ 6479 memcpy(actions_sfx, actions + qrss_action_pos, 6480 sizeof(struct rte_flow_action)); 6481 actions_sfx++; 6482 } else if (add_tag && set_tag_idx >= 0) { 6483 if (set_tag_idx > 0) 6484 memcpy(actions_pre, actions, 6485 sizeof(struct rte_flow_action) * set_tag_idx); 6486 memcpy(actions_pre + set_tag_idx + 1, actions + set_tag_idx, 6487 sizeof(struct rte_flow_action) * 6488 (sample_action_pos - set_tag_idx)); 6489 index = sample_action_pos; 6490 } else { 6491 index = sample_action_pos; 6492 if (index != 0) 6493 memcpy(actions_pre, actions, 6494 sizeof(struct rte_flow_action) * index); 6495 } 6496 /* For CX5, add an extra tag action for NIC-RX and E-Switch ingress. 6497 * For CX6DX and above, metadata registers Cx preserve their value, 6498 * add an extra tag action for NIC-RX and E-Switch Domain. 6499 */ 6500 if (add_tag) { 6501 /* Prepare the prefix tag action. */ 6502 append_index++; 6503 set_tag = (void *)(actions_pre + actions_n + append_index); 6504 /* Trust VF/SF on CX5 not supported meter so that the reserved 6505 * metadata regC is REG_NON, back to use application tag 6506 * index 0. 6507 */ 6508 if (unlikely(priv->mtr_color_reg == REG_NON)) 6509 ret = mlx5_flow_get_reg_id(dev, MLX5_APP_TAG, 0, error); 6510 else 6511 ret = mlx5_flow_get_reg_id(dev, MLX5_SAMPLE_ID, 0, error); 6512 if (ret < 0) 6513 return ret; 6514 mlx5_ipool_malloc(priv->sh->ipool 6515 [MLX5_IPOOL_RSS_EXPANTION_FLOW_ID], &tag_id); 6516 *set_tag = (struct mlx5_rte_flow_action_set_tag) { 6517 .id = ret, 6518 .data = tag_id, 6519 }; 6520 /* Prepare the suffix subflow items. */ 6521 tag_spec = (void *)(sfx_items + SAMPLE_SUFFIX_ITEM); 6522 tag_spec->data = tag_id; 6523 tag_spec->id = set_tag->id; 6524 tag_mask = tag_spec + 1; 6525 tag_mask->data = UINT32_MAX; 6526 for (; items->type != RTE_FLOW_ITEM_TYPE_END; items++) { 6527 if (items->type == RTE_FLOW_ITEM_TYPE_PORT_ID || 6528 items->type == RTE_FLOW_ITEM_TYPE_PORT_REPRESENTOR || 6529 items->type == RTE_FLOW_ITEM_TYPE_REPRESENTED_PORT) { 6530 memcpy(sfx_items, items, sizeof(*sfx_items)); 6531 sfx_items++; 6532 break; 6533 } 6534 } 6535 sfx_items[0] = (struct rte_flow_item){ 6536 .type = (enum rte_flow_item_type) 6537 MLX5_RTE_FLOW_ITEM_TYPE_TAG, 6538 .spec = tag_spec, 6539 .last = NULL, 6540 .mask = tag_mask, 6541 }; 6542 sfx_items[1] = (struct rte_flow_item){ 6543 .type = (enum rte_flow_item_type) 6544 RTE_FLOW_ITEM_TYPE_END, 6545 }; 6546 /* Prepare the tag action in prefix subflow. */ 6547 set_tag_idx = (set_tag_idx == -1) ? index : set_tag_idx; 6548 actions_pre[set_tag_idx] = 6549 (struct rte_flow_action){ 6550 .type = (enum rte_flow_action_type) 6551 MLX5_RTE_FLOW_ACTION_TYPE_TAG, 6552 .conf = set_tag, 6553 }; 6554 /* Update next sample position due to add one tag action */ 6555 index += 1; 6556 } 6557 /* Copy the sample action into prefix flow. */ 6558 memcpy(actions_pre + index, actions + sample_action_pos, 6559 sizeof(struct rte_flow_action)); 6560 index += 1; 6561 /* For the modify action after the sample action in E-Switch mirroring, 6562 * Add the extra jump action in prefix subflow and jump into the next 6563 * table, then do the modify action in the new table. 6564 */ 6565 if (jump_table) { 6566 /* Prepare the prefix jump action. */ 6567 append_index++; 6568 jump_action = (void *)(actions_pre + actions_n + append_index); 6569 jump_action->group = jump_table; 6570 actions_pre[index++] = 6571 (struct rte_flow_action){ 6572 .type = (enum rte_flow_action_type) 6573 RTE_FLOW_ACTION_TYPE_JUMP, 6574 .conf = jump_action, 6575 }; 6576 } 6577 actions_pre[index] = (struct rte_flow_action){ 6578 .type = (enum rte_flow_action_type) 6579 RTE_FLOW_ACTION_TYPE_END, 6580 }; 6581 /* Put the actions after sample into Suffix flow. */ 6582 memcpy(actions_sfx, actions + sample_action_pos + 1, 6583 sizeof(struct rte_flow_action) * 6584 (actions_n - sample_action_pos - 1)); 6585 return tag_id; 6586 } 6587 6588 /** 6589 * The splitting for metadata feature. 6590 * 6591 * - Q/RSS action on NIC Rx should be split in order to pass by 6592 * the mreg copy table (RX_CP_TBL) and then it jumps to the 6593 * action table (RX_ACT_TBL) which has the split Q/RSS action. 6594 * 6595 * - All the actions on NIC Tx should have a mreg copy action to 6596 * copy reg_a from WQE to reg_c[0]. 6597 * 6598 * @param dev 6599 * Pointer to Ethernet device. 6600 * @param[in] flow 6601 * Parent flow structure pointer. 6602 * @param[in] attr 6603 * Flow rule attributes. 6604 * @param[in] items 6605 * Pattern specification (list terminated by the END pattern item). 6606 * @param[in] actions 6607 * Associated actions (list terminated by the END action). 6608 * @param[in] flow_split_info 6609 * Pointer to flow split info structure. 6610 * @param[out] error 6611 * Perform verbose error reporting if not NULL. 6612 * @return 6613 * 0 on success, negative value otherwise 6614 */ 6615 static int 6616 flow_create_split_metadata(struct rte_eth_dev *dev, 6617 struct rte_flow *flow, 6618 const struct rte_flow_attr *attr, 6619 const struct rte_flow_item items[], 6620 const struct rte_flow_action actions[], 6621 struct mlx5_flow_split_info *flow_split_info, 6622 struct rte_flow_error *error) 6623 { 6624 struct mlx5_priv *priv = dev->data->dev_private; 6625 struct mlx5_sh_config *config = &priv->sh->config; 6626 const struct rte_flow_action *qrss = NULL; 6627 struct rte_flow_action *ext_actions = NULL; 6628 struct mlx5_flow *dev_flow = NULL; 6629 uint32_t qrss_id = 0; 6630 int mtr_sfx = 0; 6631 size_t act_size; 6632 int actions_n; 6633 int encap_idx; 6634 int ret; 6635 6636 /* Check whether extensive metadata feature is engaged. */ 6637 if (!config->dv_flow_en || 6638 config->dv_xmeta_en == MLX5_XMETA_MODE_LEGACY || 6639 !mlx5_flow_ext_mreg_supported(dev)) 6640 return flow_create_split_inner(dev, flow, NULL, attr, items, 6641 actions, flow_split_info, error); 6642 actions_n = flow_parse_metadata_split_actions_info(actions, &qrss, 6643 &encap_idx); 6644 if (qrss) { 6645 /* Exclude hairpin flows from splitting. */ 6646 if (qrss->type == RTE_FLOW_ACTION_TYPE_QUEUE) { 6647 const struct rte_flow_action_queue *queue; 6648 6649 queue = qrss->conf; 6650 if (mlx5_rxq_is_hairpin(dev, queue->index)) 6651 qrss = NULL; 6652 } else if (qrss->type == RTE_FLOW_ACTION_TYPE_RSS) { 6653 const struct rte_flow_action_rss *rss; 6654 6655 rss = qrss->conf; 6656 if (mlx5_rxq_is_hairpin(dev, rss->queue[0])) 6657 qrss = NULL; 6658 } 6659 } 6660 if (qrss) { 6661 /* Check if it is in meter suffix table. */ 6662 mtr_sfx = attr->group == 6663 ((attr->transfer && priv->fdb_def_rule) ? 6664 (MLX5_FLOW_TABLE_LEVEL_METER - 1) : 6665 MLX5_FLOW_TABLE_LEVEL_METER); 6666 /* 6667 * Q/RSS action on NIC Rx should be split in order to pass by 6668 * the mreg copy table (RX_CP_TBL) and then it jumps to the 6669 * action table (RX_ACT_TBL) which has the split Q/RSS action. 6670 */ 6671 act_size = sizeof(struct rte_flow_action) * (actions_n + 1) + 6672 sizeof(struct rte_flow_action_set_tag) + 6673 sizeof(struct rte_flow_action_jump); 6674 ext_actions = mlx5_malloc(MLX5_MEM_ZERO, act_size, 0, 6675 SOCKET_ID_ANY); 6676 if (!ext_actions) 6677 return rte_flow_error_set(error, ENOMEM, 6678 RTE_FLOW_ERROR_TYPE_ACTION, 6679 NULL, "no memory to split " 6680 "metadata flow"); 6681 /* 6682 * Create the new actions list with removed Q/RSS action 6683 * and appended set tag and jump to register copy table 6684 * (RX_CP_TBL). We should preallocate unique tag ID here 6685 * in advance, because it is needed for set tag action. 6686 */ 6687 qrss_id = flow_mreg_split_qrss_prep(dev, ext_actions, actions, 6688 qrss, actions_n, 6689 mtr_sfx, error); 6690 if (!mtr_sfx && !qrss_id) { 6691 ret = -rte_errno; 6692 goto exit; 6693 } 6694 } else if (attr->egress) { 6695 /* 6696 * All the actions on NIC Tx should have a metadata register 6697 * copy action to copy reg_a from WQE to reg_c[meta] 6698 */ 6699 act_size = sizeof(struct rte_flow_action) * (actions_n + 1) + 6700 sizeof(struct mlx5_flow_action_copy_mreg); 6701 ext_actions = mlx5_malloc(MLX5_MEM_ZERO, act_size, 0, 6702 SOCKET_ID_ANY); 6703 if (!ext_actions) 6704 return rte_flow_error_set(error, ENOMEM, 6705 RTE_FLOW_ERROR_TYPE_ACTION, 6706 NULL, "no memory to split " 6707 "metadata flow"); 6708 /* Create the action list appended with copy register. */ 6709 ret = flow_mreg_tx_copy_prep(dev, ext_actions, actions, 6710 actions_n, error, encap_idx); 6711 if (ret < 0) 6712 goto exit; 6713 } 6714 /* Add the unmodified original or prefix subflow. */ 6715 ret = flow_create_split_inner(dev, flow, &dev_flow, attr, 6716 items, ext_actions ? ext_actions : 6717 actions, flow_split_info, error); 6718 if (ret < 0) 6719 goto exit; 6720 MLX5_ASSERT(dev_flow); 6721 if (qrss) { 6722 const struct rte_flow_attr q_attr = { 6723 .group = MLX5_FLOW_MREG_ACT_TABLE_GROUP, 6724 .ingress = 1, 6725 }; 6726 /* Internal PMD action to set register. */ 6727 struct mlx5_rte_flow_item_tag q_tag_spec = { 6728 .data = qrss_id, 6729 .id = REG_NON, 6730 }; 6731 struct rte_flow_item q_items[] = { 6732 { 6733 .type = (enum rte_flow_item_type) 6734 MLX5_RTE_FLOW_ITEM_TYPE_TAG, 6735 .spec = &q_tag_spec, 6736 .last = NULL, 6737 .mask = NULL, 6738 }, 6739 { 6740 .type = RTE_FLOW_ITEM_TYPE_END, 6741 }, 6742 }; 6743 struct rte_flow_action q_actions[] = { 6744 { 6745 .type = qrss->type, 6746 .conf = qrss->conf, 6747 }, 6748 { 6749 .type = RTE_FLOW_ACTION_TYPE_END, 6750 }, 6751 }; 6752 uint64_t layers = flow_get_prefix_layer_flags(dev_flow); 6753 6754 /* 6755 * Configure the tag item only if there is no meter subflow. 6756 * Since tag is already marked in the meter suffix subflow 6757 * we can just use the meter suffix items as is. 6758 */ 6759 if (qrss_id) { 6760 /* Not meter subflow. */ 6761 MLX5_ASSERT(!mtr_sfx); 6762 /* 6763 * Put unique id in prefix flow due to it is destroyed 6764 * after suffix flow and id will be freed after there 6765 * is no actual flows with this id and identifier 6766 * reallocation becomes possible (for example, for 6767 * other flows in other threads). 6768 */ 6769 dev_flow->handle->split_flow_id = qrss_id; 6770 ret = mlx5_flow_get_reg_id(dev, MLX5_COPY_MARK, 0, 6771 error); 6772 if (ret < 0) 6773 goto exit; 6774 q_tag_spec.id = ret; 6775 } 6776 dev_flow = NULL; 6777 /* Add suffix subflow to execute Q/RSS. */ 6778 flow_split_info->prefix_layers = layers; 6779 flow_split_info->prefix_mark = 0; 6780 flow_split_info->table_id = 0; 6781 ret = flow_create_split_inner(dev, flow, &dev_flow, 6782 &q_attr, mtr_sfx ? items : 6783 q_items, q_actions, 6784 flow_split_info, error); 6785 if (ret < 0) 6786 goto exit; 6787 /* qrss ID should be freed if failed. */ 6788 qrss_id = 0; 6789 MLX5_ASSERT(dev_flow); 6790 } 6791 6792 exit: 6793 /* 6794 * We do not destroy the partially created sub_flows in case of error. 6795 * These ones are included into parent flow list and will be destroyed 6796 * by flow_drv_destroy. 6797 */ 6798 mlx5_ipool_free(priv->sh->ipool[MLX5_IPOOL_RSS_EXPANTION_FLOW_ID], 6799 qrss_id); 6800 mlx5_free(ext_actions); 6801 return ret; 6802 } 6803 6804 /** 6805 * Create meter internal drop flow with the original pattern. 6806 * 6807 * @param dev 6808 * Pointer to Ethernet device. 6809 * @param[in] flow 6810 * Parent flow structure pointer. 6811 * @param[in] attr 6812 * Flow rule attributes. 6813 * @param[in] items 6814 * Pattern specification (list terminated by the END pattern item). 6815 * @param[in] flow_split_info 6816 * Pointer to flow split info structure. 6817 * @param[in] fm 6818 * Pointer to flow meter structure. 6819 * @param[out] error 6820 * Perform verbose error reporting if not NULL. 6821 * @return 6822 * 0 on success, negative value otherwise 6823 */ 6824 static uint32_t 6825 flow_meter_create_drop_flow_with_org_pattern(struct rte_eth_dev *dev, 6826 struct rte_flow *flow, 6827 const struct rte_flow_attr *attr, 6828 const struct rte_flow_item items[], 6829 struct mlx5_flow_split_info *flow_split_info, 6830 struct mlx5_flow_meter_info *fm, 6831 struct rte_flow_error *error) 6832 { 6833 struct mlx5_flow *dev_flow = NULL; 6834 struct rte_flow_attr drop_attr = *attr; 6835 struct rte_flow_action drop_actions[3]; 6836 struct mlx5_flow_split_info drop_split_info = *flow_split_info; 6837 6838 MLX5_ASSERT(fm->drop_cnt); 6839 drop_actions[0].type = 6840 (enum rte_flow_action_type)MLX5_RTE_FLOW_ACTION_TYPE_COUNT; 6841 drop_actions[0].conf = (void *)(uintptr_t)fm->drop_cnt; 6842 drop_actions[1].type = RTE_FLOW_ACTION_TYPE_DROP; 6843 drop_actions[1].conf = NULL; 6844 drop_actions[2].type = RTE_FLOW_ACTION_TYPE_END; 6845 drop_actions[2].conf = NULL; 6846 drop_split_info.external = false; 6847 drop_split_info.skip_scale |= 1 << MLX5_SCALE_FLOW_GROUP_BIT; 6848 drop_split_info.table_id = MLX5_MTR_TABLE_ID_DROP; 6849 drop_attr.group = MLX5_FLOW_TABLE_LEVEL_METER; 6850 return flow_create_split_inner(dev, flow, &dev_flow, 6851 &drop_attr, items, drop_actions, 6852 &drop_split_info, error); 6853 } 6854 6855 /** 6856 * The splitting for meter feature. 6857 * 6858 * - The meter flow will be split to two flows as prefix and 6859 * suffix flow. The packets make sense only it pass the prefix 6860 * meter action. 6861 * 6862 * - Reg_C_5 is used for the packet to match betweend prefix and 6863 * suffix flow. 6864 * 6865 * @param dev 6866 * Pointer to Ethernet device. 6867 * @param[in] flow 6868 * Parent flow structure pointer. 6869 * @param[in] attr 6870 * Flow rule attributes. 6871 * @param[in] items 6872 * Pattern specification (list terminated by the END pattern item). 6873 * @param[in] actions 6874 * Associated actions (list terminated by the END action). 6875 * @param[in] flow_split_info 6876 * Pointer to flow split info structure. 6877 * @param[out] error 6878 * Perform verbose error reporting if not NULL. 6879 * @return 6880 * 0 on success, negative value otherwise 6881 */ 6882 static int 6883 flow_create_split_meter(struct rte_eth_dev *dev, 6884 struct rte_flow *flow, 6885 const struct rte_flow_attr *attr, 6886 const struct rte_flow_item items[], 6887 const struct rte_flow_action actions[], 6888 struct mlx5_flow_split_info *flow_split_info, 6889 struct rte_flow_error *error) 6890 { 6891 struct mlx5_priv *priv = dev->data->dev_private; 6892 struct mlx5_flow_workspace *wks = mlx5_flow_get_thread_workspace(); 6893 struct rte_flow_action *sfx_actions = NULL; 6894 struct rte_flow_action *pre_actions = NULL; 6895 struct rte_flow_item *sfx_items = NULL; 6896 struct mlx5_flow *dev_flow = NULL; 6897 struct rte_flow_attr sfx_attr = *attr; 6898 struct mlx5_flow_meter_info *fm = NULL; 6899 uint8_t skip_scale_restore; 6900 bool has_mtr = false; 6901 bool has_modify = false; 6902 bool set_mtr_reg = true; 6903 bool is_mtr_hierarchy = false; 6904 uint32_t meter_id = 0; 6905 uint32_t mtr_idx = 0; 6906 uint32_t mtr_flow_id = 0; 6907 size_t act_size; 6908 size_t item_size; 6909 int actions_n = 0; 6910 int ret = 0; 6911 6912 if (priv->mtr_en) 6913 actions_n = flow_check_meter_action(dev, actions, &has_mtr, 6914 &has_modify, &meter_id); 6915 if (has_mtr) { 6916 if (flow->meter) { 6917 fm = flow_dv_meter_find_by_idx(priv, flow->meter); 6918 if (!fm) 6919 return rte_flow_error_set(error, EINVAL, 6920 RTE_FLOW_ERROR_TYPE_UNSPECIFIED, 6921 NULL, "Meter not found."); 6922 } else { 6923 fm = mlx5_flow_meter_find(priv, meter_id, &mtr_idx); 6924 if (!fm) 6925 return rte_flow_error_set(error, EINVAL, 6926 RTE_FLOW_ERROR_TYPE_UNSPECIFIED, 6927 NULL, "Meter not found."); 6928 ret = mlx5_flow_meter_attach(priv, fm, 6929 &sfx_attr, error); 6930 if (ret) 6931 return -rte_errno; 6932 flow->meter = mtr_idx; 6933 } 6934 MLX5_ASSERT(wks); 6935 wks->fm = fm; 6936 if (!fm->def_policy) { 6937 wks->policy = mlx5_flow_meter_policy_find(dev, 6938 fm->policy_id, 6939 NULL); 6940 MLX5_ASSERT(wks->policy); 6941 if (wks->policy->mark) 6942 wks->mark = 1; 6943 if (wks->policy->is_hierarchy) { 6944 wks->final_policy = 6945 mlx5_flow_meter_hierarchy_get_final_policy(dev, 6946 wks->policy); 6947 if (!wks->final_policy) 6948 return rte_flow_error_set(error, 6949 EINVAL, 6950 RTE_FLOW_ERROR_TYPE_ACTION, NULL, 6951 "Failed to find terminal policy of hierarchy."); 6952 is_mtr_hierarchy = true; 6953 } 6954 } 6955 /* 6956 * If it isn't default-policy Meter, and 6957 * 1. Not meter hierarchy and there's no action in flow to change 6958 * packet (modify/encap/decap etc.), OR 6959 * 2. No drop count needed for this meter. 6960 * Then no need to use regC to save meter id anymore. 6961 */ 6962 if (!fm->def_policy && ((!has_modify && !is_mtr_hierarchy) || !fm->drop_cnt)) 6963 set_mtr_reg = false; 6964 /* Prefix actions: meter, decap, encap, tag, jump, end, cnt. */ 6965 #define METER_PREFIX_ACTION 7 6966 act_size = (sizeof(struct rte_flow_action) * 6967 (actions_n + METER_PREFIX_ACTION)) + 6968 sizeof(struct mlx5_rte_flow_action_set_tag); 6969 /* Suffix items: tag, vlan, port id, end. */ 6970 #define METER_SUFFIX_ITEM 4 6971 item_size = sizeof(struct rte_flow_item) * METER_SUFFIX_ITEM + 6972 sizeof(struct mlx5_rte_flow_item_tag) * 2; 6973 sfx_actions = mlx5_malloc(MLX5_MEM_ZERO, (act_size + item_size), 6974 0, SOCKET_ID_ANY); 6975 if (!sfx_actions) 6976 return rte_flow_error_set(error, ENOMEM, 6977 RTE_FLOW_ERROR_TYPE_ACTION, 6978 NULL, "no memory to split " 6979 "meter flow"); 6980 sfx_items = (struct rte_flow_item *)((char *)sfx_actions + 6981 act_size); 6982 /* There's no suffix flow for meter of non-default policy. */ 6983 if (!fm->def_policy) 6984 pre_actions = sfx_actions + 1; 6985 else 6986 pre_actions = sfx_actions + actions_n; 6987 ret = flow_meter_split_prep(dev, flow, wks, &sfx_attr, 6988 items, sfx_items, actions, 6989 sfx_actions, pre_actions, 6990 (set_mtr_reg ? &mtr_flow_id : NULL), 6991 error); 6992 if (ret) { 6993 ret = -rte_errno; 6994 goto exit; 6995 } 6996 /* Add the prefix subflow. */ 6997 skip_scale_restore = flow_split_info->skip_scale; 6998 flow_split_info->skip_scale |= 6999 1 << MLX5_SCALE_JUMP_FLOW_GROUP_BIT; 7000 ret = flow_create_split_inner(dev, flow, &dev_flow, 7001 attr, items, pre_actions, 7002 flow_split_info, error); 7003 flow_split_info->skip_scale = skip_scale_restore; 7004 if (ret) { 7005 if (mtr_flow_id) 7006 mlx5_ipool_free(fm->flow_ipool, mtr_flow_id); 7007 ret = -rte_errno; 7008 goto exit; 7009 } 7010 if (mtr_flow_id) { 7011 dev_flow->handle->split_flow_id = mtr_flow_id; 7012 dev_flow->handle->is_meter_flow_id = 1; 7013 } 7014 if (!fm->def_policy) { 7015 if (!set_mtr_reg && fm->drop_cnt) 7016 ret = 7017 flow_meter_create_drop_flow_with_org_pattern(dev, flow, 7018 &sfx_attr, items, 7019 flow_split_info, 7020 fm, error); 7021 goto exit; 7022 } 7023 /* Setting the sfx group atrr. */ 7024 sfx_attr.group = sfx_attr.transfer ? 7025 (MLX5_FLOW_TABLE_LEVEL_METER - 1) : 7026 MLX5_FLOW_TABLE_LEVEL_METER; 7027 flow_split_info->prefix_layers = 7028 flow_get_prefix_layer_flags(dev_flow); 7029 flow_split_info->prefix_mark |= wks->mark; 7030 flow_split_info->table_id = MLX5_MTR_TABLE_ID_SUFFIX; 7031 } 7032 /* Add the prefix subflow. */ 7033 ret = flow_create_split_metadata(dev, flow, 7034 &sfx_attr, sfx_items ? 7035 sfx_items : items, 7036 sfx_actions ? sfx_actions : actions, 7037 flow_split_info, error); 7038 exit: 7039 if (sfx_actions) 7040 mlx5_free(sfx_actions); 7041 return ret; 7042 } 7043 7044 /** 7045 * The splitting for sample feature. 7046 * 7047 * Once Sample action is detected in the action list, the flow actions should 7048 * be split into prefix sub flow and suffix sub flow. 7049 * 7050 * The original items remain in the prefix sub flow, all actions preceding the 7051 * sample action and the sample action itself will be copied to the prefix 7052 * sub flow, the actions following the sample action will be copied to the 7053 * suffix sub flow, Queue action always be located in the suffix sub flow. 7054 * 7055 * In order to make the packet from prefix sub flow matches with suffix sub 7056 * flow, an extra tag action be added into prefix sub flow, and the suffix sub 7057 * flow uses tag item with the unique flow id. 7058 * 7059 * @param dev 7060 * Pointer to Ethernet device. 7061 * @param[in] flow 7062 * Parent flow structure pointer. 7063 * @param[in] attr 7064 * Flow rule attributes. 7065 * @param[in] items 7066 * Pattern specification (list terminated by the END pattern item). 7067 * @param[in] actions 7068 * Associated actions (list terminated by the END action). 7069 * @param[in] flow_split_info 7070 * Pointer to flow split info structure. 7071 * @param[out] error 7072 * Perform verbose error reporting if not NULL. 7073 * @return 7074 * 0 on success, negative value otherwise 7075 */ 7076 static int 7077 flow_create_split_sample(struct rte_eth_dev *dev, 7078 struct rte_flow *flow, 7079 const struct rte_flow_attr *attr, 7080 const struct rte_flow_item items[], 7081 const struct rte_flow_action actions[], 7082 struct mlx5_flow_split_info *flow_split_info, 7083 struct rte_flow_error *error) 7084 { 7085 struct mlx5_priv *priv = dev->data->dev_private; 7086 struct rte_flow_action *sfx_actions = NULL; 7087 struct rte_flow_action *pre_actions = NULL; 7088 struct rte_flow_item *sfx_items = NULL; 7089 struct mlx5_flow *dev_flow = NULL; 7090 struct rte_flow_attr sfx_attr = *attr; 7091 #ifdef HAVE_IBV_FLOW_DV_SUPPORT 7092 struct mlx5_flow_dv_sample_resource *sample_res; 7093 struct mlx5_flow_tbl_data_entry *sfx_tbl_data; 7094 struct mlx5_flow_tbl_resource *sfx_tbl; 7095 struct mlx5_flow_workspace *wks = mlx5_flow_get_thread_workspace(); 7096 #endif 7097 size_t act_size; 7098 size_t item_size; 7099 uint32_t fdb_tx = 0; 7100 int32_t tag_id = 0; 7101 int actions_n = 0; 7102 int sample_action_pos; 7103 int qrss_action_pos; 7104 int add_tag = 0; 7105 int modify_after_mirror = 0; 7106 uint16_t jump_table = 0; 7107 const uint32_t next_ft_step = 1; 7108 int ret = 0; 7109 struct mlx5_priv *item_port_priv = NULL; 7110 const struct rte_flow_item *item; 7111 7112 if (priv->sampler_en) 7113 actions_n = flow_check_match_action(actions, attr, 7114 RTE_FLOW_ACTION_TYPE_SAMPLE, 7115 &sample_action_pos, &qrss_action_pos, 7116 &modify_after_mirror); 7117 if (actions_n) { 7118 /* The prefix actions must includes sample, tag, end. */ 7119 act_size = sizeof(struct rte_flow_action) * (actions_n * 2 + 1) 7120 + sizeof(struct mlx5_rte_flow_action_set_tag); 7121 item_size = sizeof(struct rte_flow_item) * SAMPLE_SUFFIX_ITEM + 7122 sizeof(struct mlx5_rte_flow_item_tag) * 2; 7123 sfx_actions = mlx5_malloc(MLX5_MEM_ZERO, (act_size + 7124 item_size), 0, SOCKET_ID_ANY); 7125 if (!sfx_actions) 7126 return rte_flow_error_set(error, ENOMEM, 7127 RTE_FLOW_ERROR_TYPE_ACTION, 7128 NULL, "no memory to split " 7129 "sample flow"); 7130 for (item = items; item->type != RTE_FLOW_ITEM_TYPE_END; item++) { 7131 if (item->type == RTE_FLOW_ITEM_TYPE_PORT_ID) { 7132 const struct rte_flow_item_port_id *spec; 7133 7134 spec = (const struct rte_flow_item_port_id *)item->spec; 7135 if (spec) 7136 item_port_priv = 7137 mlx5_port_to_eswitch_info(spec->id, true); 7138 break; 7139 } else if (item->type == RTE_FLOW_ITEM_TYPE_REPRESENTED_PORT) { 7140 const struct rte_flow_item_ethdev *spec; 7141 7142 spec = (const struct rte_flow_item_ethdev *)item->spec; 7143 if (spec) 7144 item_port_priv = 7145 mlx5_port_to_eswitch_info(spec->port_id, true); 7146 break; 7147 } else if (item->type == RTE_FLOW_ITEM_TYPE_PORT_REPRESENTOR) { 7148 const struct rte_flow_item_ethdev *spec; 7149 7150 spec = (const struct rte_flow_item_ethdev *)item->spec; 7151 if (spec) 7152 item_port_priv = 7153 mlx5_port_to_eswitch_info(spec->port_id, true); 7154 break; 7155 } 7156 } 7157 /* The representor_id is UINT16_MAX for uplink. */ 7158 fdb_tx = (attr->transfer && 7159 flow_source_vport_representor(priv, item_port_priv)); 7160 /* 7161 * When reg_c_preserve is set, metadata registers Cx preserve 7162 * their value even through packet duplication. 7163 */ 7164 add_tag = (!fdb_tx || 7165 priv->sh->cdev->config.hca_attr.reg_c_preserve); 7166 if (add_tag) 7167 sfx_items = (struct rte_flow_item *)((char *)sfx_actions 7168 + act_size); 7169 if (modify_after_mirror) 7170 jump_table = attr->group * MLX5_FLOW_TABLE_FACTOR + 7171 next_ft_step; 7172 pre_actions = sfx_actions + actions_n; 7173 tag_id = flow_sample_split_prep(dev, add_tag, items, sfx_items, 7174 actions, sfx_actions, 7175 pre_actions, actions_n, 7176 sample_action_pos, 7177 qrss_action_pos, jump_table, 7178 error); 7179 if (tag_id < 0 || (add_tag && !tag_id)) { 7180 ret = -rte_errno; 7181 goto exit; 7182 } 7183 if (modify_after_mirror) 7184 flow_split_info->skip_scale = 7185 1 << MLX5_SCALE_JUMP_FLOW_GROUP_BIT; 7186 /* Add the prefix subflow. */ 7187 ret = flow_create_split_inner(dev, flow, &dev_flow, attr, 7188 items, pre_actions, 7189 flow_split_info, error); 7190 if (ret) { 7191 ret = -rte_errno; 7192 goto exit; 7193 } 7194 dev_flow->handle->split_flow_id = tag_id; 7195 #ifdef HAVE_IBV_FLOW_DV_SUPPORT 7196 if (!modify_after_mirror) { 7197 /* Set the sfx group attr. */ 7198 sample_res = (struct mlx5_flow_dv_sample_resource *) 7199 dev_flow->dv.sample_res; 7200 sfx_tbl = (struct mlx5_flow_tbl_resource *) 7201 sample_res->normal_path_tbl; 7202 sfx_tbl_data = container_of(sfx_tbl, 7203 struct mlx5_flow_tbl_data_entry, 7204 tbl); 7205 sfx_attr.group = sfx_attr.transfer ? 7206 (sfx_tbl_data->level - 1) : sfx_tbl_data->level; 7207 } else { 7208 MLX5_ASSERT(attr->transfer); 7209 sfx_attr.group = jump_table; 7210 } 7211 flow_split_info->prefix_layers = 7212 flow_get_prefix_layer_flags(dev_flow); 7213 MLX5_ASSERT(wks); 7214 flow_split_info->prefix_mark |= wks->mark; 7215 /* Suffix group level already be scaled with factor, set 7216 * MLX5_SCALE_FLOW_GROUP_BIT of skip_scale to 1 to avoid scale 7217 * again in translation. 7218 */ 7219 flow_split_info->skip_scale = 1 << MLX5_SCALE_FLOW_GROUP_BIT; 7220 #endif 7221 } 7222 /* Add the suffix subflow. */ 7223 ret = flow_create_split_meter(dev, flow, &sfx_attr, 7224 sfx_items ? sfx_items : items, 7225 sfx_actions ? sfx_actions : actions, 7226 flow_split_info, error); 7227 exit: 7228 if (sfx_actions) 7229 mlx5_free(sfx_actions); 7230 return ret; 7231 } 7232 7233 /** 7234 * Split the flow to subflow set. The splitters might be linked 7235 * in the chain, like this: 7236 * flow_create_split_outer() calls: 7237 * flow_create_split_meter() calls: 7238 * flow_create_split_metadata(meter_subflow_0) calls: 7239 * flow_create_split_inner(metadata_subflow_0) 7240 * flow_create_split_inner(metadata_subflow_1) 7241 * flow_create_split_inner(metadata_subflow_2) 7242 * flow_create_split_metadata(meter_subflow_1) calls: 7243 * flow_create_split_inner(metadata_subflow_0) 7244 * flow_create_split_inner(metadata_subflow_1) 7245 * flow_create_split_inner(metadata_subflow_2) 7246 * 7247 * This provide flexible way to add new levels of flow splitting. 7248 * The all of successfully created subflows are included to the 7249 * parent flow dev_flow list. 7250 * 7251 * @param dev 7252 * Pointer to Ethernet device. 7253 * @param[in] flow 7254 * Parent flow structure pointer. 7255 * @param[in] attr 7256 * Flow rule attributes. 7257 * @param[in] items 7258 * Pattern specification (list terminated by the END pattern item). 7259 * @param[in] actions 7260 * Associated actions (list terminated by the END action). 7261 * @param[in] flow_split_info 7262 * Pointer to flow split info structure. 7263 * @param[out] error 7264 * Perform verbose error reporting if not NULL. 7265 * @return 7266 * 0 on success, negative value otherwise 7267 */ 7268 static int 7269 flow_create_split_outer(struct rte_eth_dev *dev, 7270 struct rte_flow *flow, 7271 const struct rte_flow_attr *attr, 7272 const struct rte_flow_item items[], 7273 const struct rte_flow_action actions[], 7274 struct mlx5_flow_split_info *flow_split_info, 7275 struct rte_flow_error *error) 7276 { 7277 int ret; 7278 7279 ret = flow_create_split_sample(dev, flow, attr, items, 7280 actions, flow_split_info, error); 7281 MLX5_ASSERT(ret <= 0); 7282 return ret; 7283 } 7284 7285 static inline struct mlx5_flow_tunnel * 7286 flow_tunnel_from_rule(const struct mlx5_flow *flow) 7287 { 7288 struct mlx5_flow_tunnel *tunnel; 7289 7290 #pragma GCC diagnostic push 7291 #pragma GCC diagnostic ignored "-Wcast-qual" 7292 tunnel = (typeof(tunnel))flow->tunnel; 7293 #pragma GCC diagnostic pop 7294 7295 return tunnel; 7296 } 7297 7298 /** 7299 * Create a flow and add it to @p list. 7300 * 7301 * @param dev 7302 * Pointer to Ethernet device. 7303 * @param list 7304 * Pointer to a TAILQ flow list. If this parameter NULL, 7305 * no list insertion occurred, flow is just created, 7306 * this is caller's responsibility to track the 7307 * created flow. 7308 * @param[in] attr 7309 * Flow rule attributes. 7310 * @param[in] items 7311 * Pattern specification (list terminated by the END pattern item). 7312 * @param[in] actions 7313 * Associated actions (list terminated by the END action). 7314 * @param[in] external 7315 * This flow rule is created by request external to PMD. 7316 * @param[out] error 7317 * Perform verbose error reporting if not NULL. 7318 * 7319 * @return 7320 * A flow index on success, 0 otherwise and rte_errno is set. 7321 */ 7322 static uint32_t 7323 flow_list_create(struct rte_eth_dev *dev, enum mlx5_flow_type type, 7324 const struct rte_flow_attr *attr, 7325 const struct rte_flow_item items[], 7326 const struct rte_flow_action original_actions[], 7327 bool external, struct rte_flow_error *error) 7328 { 7329 struct mlx5_priv *priv = dev->data->dev_private; 7330 struct rte_flow *flow = NULL; 7331 struct mlx5_flow *dev_flow; 7332 const struct rte_flow_action_rss *rss = NULL; 7333 struct mlx5_translated_action_handle 7334 indir_actions[MLX5_MAX_INDIRECT_ACTIONS]; 7335 int indir_actions_n = MLX5_MAX_INDIRECT_ACTIONS; 7336 union { 7337 struct mlx5_flow_expand_rss buf; 7338 uint8_t buffer[8192]; 7339 } expand_buffer; 7340 union { 7341 struct rte_flow_action actions[MLX5_MAX_SPLIT_ACTIONS]; 7342 uint8_t buffer[2048]; 7343 } actions_rx; 7344 union { 7345 struct rte_flow_action actions[MLX5_MAX_SPLIT_ACTIONS]; 7346 uint8_t buffer[2048]; 7347 } actions_hairpin_tx; 7348 union { 7349 struct rte_flow_item items[MLX5_MAX_SPLIT_ITEMS]; 7350 uint8_t buffer[2048]; 7351 } items_tx; 7352 struct mlx5_rte_flow_item_sq sq_specs[RTE_MAX_QUEUES_PER_PORT]; 7353 struct mlx5_flow_expand_rss *buf = &expand_buffer.buf; 7354 struct mlx5_flow_rss_desc *rss_desc; 7355 const struct rte_flow_action *p_actions_rx; 7356 uint32_t i; 7357 uint32_t idx = 0; 7358 int hairpin_flow; 7359 struct rte_flow_attr attr_tx = { .priority = 0 }; 7360 const struct rte_flow_action *actions; 7361 struct rte_flow_action *translated_actions = NULL; 7362 struct mlx5_flow_tunnel *tunnel; 7363 struct tunnel_default_miss_ctx default_miss_ctx = { 0, }; 7364 struct mlx5_flow_workspace *wks = mlx5_flow_push_thread_workspace(); 7365 struct mlx5_flow_split_info flow_split_info = { 7366 .external = !!external, 7367 .skip_scale = 0, 7368 .flow_idx = 0, 7369 .prefix_mark = 0, 7370 .prefix_layers = 0, 7371 .table_id = 0 7372 }; 7373 int ret; 7374 7375 MLX5_ASSERT(wks); 7376 rss_desc = &wks->rss_desc; 7377 ret = flow_action_handles_translate(dev, original_actions, 7378 indir_actions, 7379 &indir_actions_n, 7380 &translated_actions, error); 7381 if (ret < 0) { 7382 MLX5_ASSERT(translated_actions == NULL); 7383 return 0; 7384 } 7385 actions = translated_actions ? translated_actions : original_actions; 7386 p_actions_rx = actions; 7387 hairpin_flow = flow_check_hairpin_split(dev, attr, actions); 7388 ret = flow_drv_validate(dev, attr, items, p_actions_rx, 7389 external, hairpin_flow, error); 7390 if (ret < 0) 7391 goto error_before_hairpin_split; 7392 flow = mlx5_ipool_zmalloc(priv->flows[type], &idx); 7393 if (!flow) { 7394 rte_errno = ENOMEM; 7395 goto error_before_hairpin_split; 7396 } 7397 if (hairpin_flow > 0) { 7398 if (hairpin_flow > MLX5_MAX_SPLIT_ACTIONS) { 7399 rte_errno = EINVAL; 7400 goto error_before_hairpin_split; 7401 } 7402 flow_hairpin_split(dev, actions, actions_rx.actions, 7403 actions_hairpin_tx.actions, items_tx.items, 7404 idx); 7405 p_actions_rx = actions_rx.actions; 7406 } 7407 flow_split_info.flow_idx = idx; 7408 flow->drv_type = flow_get_drv_type(dev, attr); 7409 MLX5_ASSERT(flow->drv_type > MLX5_FLOW_TYPE_MIN && 7410 flow->drv_type < MLX5_FLOW_TYPE_MAX); 7411 memset(rss_desc, 0, offsetof(struct mlx5_flow_rss_desc, queue)); 7412 /* RSS Action only works on NIC RX domain */ 7413 if (attr->ingress) 7414 rss = flow_get_rss_action(dev, p_actions_rx); 7415 if (rss) { 7416 MLX5_ASSERT(rss->queue_num <= RTE_ETH_RSS_RETA_SIZE_512); 7417 rss_desc->symmetric_hash_function = MLX5_RSS_IS_SYMM(rss->func); 7418 /* 7419 * The following information is required by 7420 * mlx5_flow_hashfields_adjust() in advance. 7421 */ 7422 rss_desc->level = rss->level; 7423 /* RSS type 0 indicates default RSS type (RTE_ETH_RSS_IP). */ 7424 rss_desc->types = !rss->types ? RTE_ETH_RSS_IP : rss->types; 7425 } 7426 flow->dev_handles = 0; 7427 if (rss && rss->types) { 7428 unsigned int graph_root; 7429 7430 graph_root = find_graph_root(rss->level); 7431 ret = mlx5_flow_expand_rss(buf, sizeof(expand_buffer.buffer), 7432 items, rss->types, 7433 mlx5_support_expansion, graph_root); 7434 MLX5_ASSERT(ret > 0 && 7435 (unsigned int)ret < sizeof(expand_buffer.buffer)); 7436 if (rte_log_can_log(mlx5_logtype, RTE_LOG_DEBUG)) { 7437 for (i = 0; i < buf->entries; ++i) 7438 mlx5_dbg__print_pattern(buf->entry[i].pattern); 7439 } 7440 } else { 7441 ret = mlx5_flow_expand_sqn((struct mlx5_flow_expand_sqn *)buf, 7442 sizeof(expand_buffer.buffer), 7443 items, sq_specs); 7444 if (ret) { 7445 rte_flow_error_set(error, ENOMEM, RTE_FLOW_ERROR_TYPE_HANDLE, 7446 NULL, "not enough memory for rte_flow"); 7447 goto error; 7448 } 7449 if (buf->entries == 0) { 7450 buf->entries = 1; 7451 buf->entry[0].pattern = (void *)(uintptr_t)items; 7452 } 7453 } 7454 rss_desc->shared_rss = flow_get_shared_rss_action(dev, indir_actions, 7455 indir_actions_n); 7456 for (i = 0; i < buf->entries; ++i) { 7457 /* Initialize flow split data. */ 7458 flow_split_info.prefix_layers = 0; 7459 flow_split_info.prefix_mark = 0; 7460 flow_split_info.skip_scale = 0; 7461 /* 7462 * The splitter may create multiple dev_flows, 7463 * depending on configuration. In the simplest 7464 * case it just creates unmodified original flow. 7465 */ 7466 ret = flow_create_split_outer(dev, flow, attr, 7467 buf->entry[i].pattern, 7468 p_actions_rx, &flow_split_info, 7469 error); 7470 if (ret < 0) 7471 goto error; 7472 if (is_flow_tunnel_steer_rule(wks->flows[0].tof_type)) { 7473 ret = flow_tunnel_add_default_miss(dev, flow, attr, 7474 p_actions_rx, 7475 idx, 7476 wks->flows[0].tunnel, 7477 &default_miss_ctx, 7478 error); 7479 if (ret < 0) { 7480 mlx5_free(default_miss_ctx.queue); 7481 goto error; 7482 } 7483 } 7484 } 7485 /* Create the tx flow. */ 7486 if (hairpin_flow) { 7487 attr_tx.group = MLX5_HAIRPIN_TX_TABLE; 7488 attr_tx.ingress = 0; 7489 attr_tx.egress = 1; 7490 dev_flow = flow_drv_prepare(dev, flow, &attr_tx, items_tx.items, 7491 actions_hairpin_tx.actions, 7492 idx, error); 7493 if (!dev_flow) 7494 goto error; 7495 dev_flow->flow = flow; 7496 dev_flow->external = 0; 7497 SILIST_INSERT(&flow->dev_handles, dev_flow->handle_idx, 7498 dev_flow->handle, next); 7499 ret = flow_drv_translate(dev, dev_flow, &attr_tx, 7500 items_tx.items, 7501 actions_hairpin_tx.actions, error); 7502 if (ret < 0) 7503 goto error; 7504 } 7505 /* 7506 * Update the metadata register copy table. If extensive 7507 * metadata feature is enabled and registers are supported 7508 * we might create the extra rte_flow for each unique 7509 * MARK/FLAG action ID. 7510 * 7511 * The table is updated for ingress and transfer flows only, because 7512 * the egress Flows belong to the different device and 7513 * copy table should be updated in peer NIC Rx domain. 7514 */ 7515 if ((attr->ingress || attr->transfer) && 7516 (external || attr->group != MLX5_FLOW_MREG_CP_TABLE_GROUP)) { 7517 ret = flow_mreg_update_copy_table(dev, flow, actions, error); 7518 if (ret) 7519 goto error; 7520 } 7521 /* 7522 * If the flow is external (from application) OR device is started, 7523 * OR mreg discover, then apply immediately. 7524 */ 7525 if (external || dev->data->dev_started || 7526 (attr->group == MLX5_FLOW_MREG_CP_TABLE_GROUP && 7527 attr->priority == MLX5_FLOW_LOWEST_PRIO_INDICATOR)) { 7528 ret = flow_drv_apply(dev, flow, error); 7529 if (ret < 0) 7530 goto error; 7531 } 7532 flow->type = type; 7533 flow_rxq_flags_set(dev, flow); 7534 rte_free(translated_actions); 7535 tunnel = flow_tunnel_from_rule(wks->flows); 7536 if (tunnel) { 7537 flow->tunnel = 1; 7538 flow->tunnel_id = tunnel->tunnel_id; 7539 __atomic_fetch_add(&tunnel->refctn, 1, __ATOMIC_RELAXED); 7540 mlx5_free(default_miss_ctx.queue); 7541 } 7542 mlx5_flow_pop_thread_workspace(); 7543 return idx; 7544 error: 7545 MLX5_ASSERT(flow); 7546 ret = rte_errno; /* Save rte_errno before cleanup. */ 7547 flow_mreg_del_copy_action(dev, flow); 7548 flow_drv_destroy(dev, flow); 7549 if (rss_desc->shared_rss) 7550 __atomic_fetch_sub(&((struct mlx5_shared_action_rss *) 7551 mlx5_ipool_get 7552 (priv->sh->ipool[MLX5_IPOOL_RSS_SHARED_ACTIONS], 7553 rss_desc->shared_rss))->refcnt, 1, __ATOMIC_RELAXED); 7554 mlx5_ipool_free(priv->flows[type], idx); 7555 rte_errno = ret; /* Restore rte_errno. */ 7556 ret = rte_errno; 7557 rte_errno = ret; 7558 error_before_hairpin_split: 7559 mlx5_flow_pop_thread_workspace(); 7560 rte_free(translated_actions); 7561 return 0; 7562 } 7563 7564 /** 7565 * Create a dedicated flow rule on e-switch table 0 (root table), to direct all 7566 * incoming packets to table 1. 7567 * 7568 * Other flow rules, requested for group n, will be created in 7569 * e-switch table n+1. 7570 * Jump action to e-switch group n will be created to group n+1. 7571 * 7572 * Used when working in switchdev mode, to utilise advantages of table 1 7573 * and above. 7574 * 7575 * @param dev 7576 * Pointer to Ethernet device. 7577 * 7578 * @return 7579 * Pointer to flow on success, NULL otherwise and rte_errno is set. 7580 */ 7581 struct rte_flow * 7582 mlx5_flow_create_esw_table_zero_flow(struct rte_eth_dev *dev) 7583 { 7584 const struct rte_flow_attr attr = { 7585 .group = 0, 7586 .priority = 0, 7587 .ingress = 0, 7588 .egress = 0, 7589 .transfer = 1, 7590 }; 7591 const struct rte_flow_item pattern = { 7592 .type = RTE_FLOW_ITEM_TYPE_END, 7593 }; 7594 struct rte_flow_action_jump jump = { 7595 .group = 1, 7596 }; 7597 const struct rte_flow_action actions[] = { 7598 { 7599 .type = RTE_FLOW_ACTION_TYPE_JUMP, 7600 .conf = &jump, 7601 }, 7602 { 7603 .type = RTE_FLOW_ACTION_TYPE_END, 7604 }, 7605 }; 7606 struct rte_flow_error error; 7607 7608 return (void *)(uintptr_t)flow_list_create(dev, MLX5_FLOW_TYPE_CTL, 7609 &attr, &pattern, 7610 actions, false, &error); 7611 } 7612 7613 /** 7614 * Create a dedicated flow rule on e-switch table 1, matches ESW manager 7615 * and sq number, directs all packets to peer vport. 7616 * 7617 * @param dev 7618 * Pointer to Ethernet device. 7619 * @param sq_num 7620 * SQ number. 7621 * 7622 * @return 7623 * Flow ID on success, 0 otherwise and rte_errno is set. 7624 */ 7625 uint32_t 7626 mlx5_flow_create_devx_sq_miss_flow(struct rte_eth_dev *dev, uint32_t sq_num) 7627 { 7628 struct rte_flow_attr attr = { 7629 .group = 0, 7630 .priority = MLX5_FLOW_LOWEST_PRIO_INDICATOR, 7631 .ingress = 0, 7632 .egress = 0, 7633 .transfer = 1, 7634 }; 7635 struct rte_flow_item_port_id port_spec = { 7636 .id = MLX5_PORT_ESW_MGR, 7637 }; 7638 struct mlx5_rte_flow_item_sq sq_spec = { 7639 .queue = sq_num, 7640 }; 7641 struct rte_flow_item pattern[] = { 7642 { 7643 .type = RTE_FLOW_ITEM_TYPE_PORT_ID, 7644 .spec = &port_spec, 7645 }, 7646 { 7647 .type = (enum rte_flow_item_type) 7648 MLX5_RTE_FLOW_ITEM_TYPE_SQ, 7649 .spec = &sq_spec, 7650 }, 7651 { 7652 .type = RTE_FLOW_ITEM_TYPE_END, 7653 }, 7654 }; 7655 struct rte_flow_action_jump jump = { 7656 .group = 1, 7657 }; 7658 struct rte_flow_action_port_id port = { 7659 .id = dev->data->port_id, 7660 }; 7661 struct rte_flow_action actions[] = { 7662 { 7663 .type = RTE_FLOW_ACTION_TYPE_JUMP, 7664 .conf = &jump, 7665 }, 7666 { 7667 .type = RTE_FLOW_ACTION_TYPE_END, 7668 }, 7669 }; 7670 struct rte_flow_error error; 7671 7672 /* 7673 * Creates group 0, highest priority jump flow. 7674 * Matches txq to bypass kernel packets. 7675 */ 7676 if (flow_list_create(dev, MLX5_FLOW_TYPE_CTL, &attr, pattern, actions, 7677 false, &error) == 0) 7678 return 0; 7679 /* Create group 1, lowest priority redirect flow for txq. */ 7680 attr.group = 1; 7681 actions[0].conf = &port; 7682 actions[0].type = RTE_FLOW_ACTION_TYPE_PORT_ID; 7683 return flow_list_create(dev, MLX5_FLOW_TYPE_CTL, &attr, pattern, 7684 actions, false, &error); 7685 } 7686 7687 /** 7688 * Validate a flow supported by the NIC. 7689 * 7690 * @see rte_flow_validate() 7691 * @see rte_flow_ops 7692 */ 7693 int 7694 mlx5_flow_validate(struct rte_eth_dev *dev, 7695 const struct rte_flow_attr *attr, 7696 const struct rte_flow_item items[], 7697 const struct rte_flow_action original_actions[], 7698 struct rte_flow_error *error) 7699 { 7700 int hairpin_flow; 7701 struct mlx5_translated_action_handle 7702 indir_actions[MLX5_MAX_INDIRECT_ACTIONS]; 7703 int indir_actions_n = MLX5_MAX_INDIRECT_ACTIONS; 7704 const struct rte_flow_action *actions; 7705 struct rte_flow_action *translated_actions = NULL; 7706 int ret = flow_action_handles_translate(dev, original_actions, 7707 indir_actions, 7708 &indir_actions_n, 7709 &translated_actions, error); 7710 7711 if (ret) 7712 return ret; 7713 actions = translated_actions ? translated_actions : original_actions; 7714 hairpin_flow = flow_check_hairpin_split(dev, attr, actions); 7715 ret = flow_drv_validate(dev, attr, items, actions, 7716 true, hairpin_flow, error); 7717 rte_free(translated_actions); 7718 return ret; 7719 } 7720 7721 static int 7722 mlx5_flow_cache_flow_info(struct rte_eth_dev *dev, 7723 const struct rte_flow_attr *attr, 7724 const uint32_t orig_prio, 7725 const struct rte_flow_item *items, 7726 const struct rte_flow_action *actions, 7727 uint32_t flow_idx) 7728 { 7729 struct mlx5_priv *priv = dev->data->dev_private; 7730 struct mlx5_flow_engine_mode_info *mode_info = &priv->mode_info; 7731 struct mlx5_dv_flow_info *flow_info, *tmp_info; 7732 struct rte_flow_error error; 7733 int len, ret; 7734 7735 flow_info = mlx5_malloc(MLX5_MEM_ZERO, sizeof(*flow_info), 0, SOCKET_ID_ANY); 7736 if (!flow_info) { 7737 DRV_LOG(ERR, "No enough memory for flow_info caching."); 7738 return -1; 7739 } 7740 flow_info->orig_prio = orig_prio; 7741 flow_info->attr = *attr; 7742 /* Standby mode rule awlays saves it in low priority entry. */ 7743 flow_info->flow_idx_low_prio = flow_idx; 7744 7745 /* Store matching items. */ 7746 ret = rte_flow_conv(RTE_FLOW_CONV_OP_PATTERN, NULL, 0, items, &error); 7747 if (ret <= 0) { 7748 DRV_LOG(ERR, "Can't get items length."); 7749 goto end; 7750 } 7751 len = RTE_ALIGN(ret, 16); 7752 flow_info->items = mlx5_malloc(MLX5_MEM_ZERO, len, 0, SOCKET_ID_ANY); 7753 if (!flow_info->items) { 7754 DRV_LOG(ERR, "No enough memory for items caching."); 7755 goto end; 7756 } 7757 ret = rte_flow_conv(RTE_FLOW_CONV_OP_PATTERN, flow_info->items, ret, items, &error); 7758 if (ret <= 0) { 7759 DRV_LOG(ERR, "Can't duplicate items."); 7760 goto end; 7761 } 7762 7763 /* Store flow actions. */ 7764 ret = rte_flow_conv(RTE_FLOW_CONV_OP_ACTIONS, NULL, 0, actions, &error); 7765 if (ret <= 0) { 7766 DRV_LOG(ERR, "Can't get actions length."); 7767 goto end; 7768 } 7769 len = RTE_ALIGN(ret, 16); 7770 flow_info->actions = mlx5_malloc(MLX5_MEM_ZERO, len, 0, SOCKET_ID_ANY); 7771 if (!flow_info->actions) { 7772 DRV_LOG(ERR, "No enough memory for actions caching."); 7773 goto end; 7774 } 7775 ret = rte_flow_conv(RTE_FLOW_CONV_OP_ACTIONS, flow_info->actions, ret, actions, &error); 7776 if (ret <= 0) { 7777 DRV_LOG(ERR, "Can't duplicate actions."); 7778 goto end; 7779 } 7780 7781 /* Insert to the list end. */ 7782 if (LIST_EMPTY(&mode_info->hot_upgrade)) { 7783 LIST_INSERT_HEAD(&mode_info->hot_upgrade, flow_info, next); 7784 } else { 7785 tmp_info = LIST_FIRST(&mode_info->hot_upgrade); 7786 while (LIST_NEXT(tmp_info, next)) 7787 tmp_info = LIST_NEXT(tmp_info, next); 7788 LIST_INSERT_AFTER(tmp_info, flow_info, next); 7789 } 7790 return 0; 7791 end: 7792 if (flow_info->items) 7793 mlx5_free(flow_info->items); 7794 if (flow_info->actions) 7795 mlx5_free(flow_info->actions); 7796 mlx5_free(flow_info); 7797 return -1; 7798 } 7799 7800 static int 7801 mlx5_flow_cache_flow_toggle(struct rte_eth_dev *dev, bool orig_prio) 7802 { 7803 struct mlx5_priv *priv = dev->data->dev_private; 7804 struct mlx5_flow_engine_mode_info *mode_info = &priv->mode_info; 7805 struct mlx5_dv_flow_info *flow_info; 7806 struct rte_flow_attr attr; 7807 struct rte_flow_error error; 7808 struct rte_flow *high, *low; 7809 7810 flow_info = LIST_FIRST(&mode_info->hot_upgrade); 7811 while (flow_info) { 7812 /* DUP flow may have the same priority. */ 7813 if (flow_info->orig_prio != flow_info->attr.priority) { 7814 attr = flow_info->attr; 7815 if (orig_prio) 7816 attr.priority = flow_info->orig_prio; 7817 flow_info->flow_idx_high_prio = flow_list_create(dev, MLX5_FLOW_TYPE_GEN, 7818 &attr, flow_info->items, flow_info->actions, 7819 true, &error); 7820 if (!flow_info->flow_idx_high_prio) { 7821 DRV_LOG(ERR, "Priority toggle failed internally."); 7822 goto err; 7823 } 7824 } 7825 flow_info = LIST_NEXT(flow_info, next); 7826 } 7827 /* Delete the low priority rules and swap the flow handle. */ 7828 flow_info = LIST_FIRST(&mode_info->hot_upgrade); 7829 while (flow_info) { 7830 MLX5_ASSERT(flow_info->flow_idx_low_prio); 7831 if (flow_info->orig_prio != flow_info->attr.priority) { 7832 high = mlx5_ipool_get(priv->flows[MLX5_FLOW_TYPE_GEN], 7833 flow_info->flow_idx_high_prio); 7834 low = mlx5_ipool_get(priv->flows[MLX5_FLOW_TYPE_GEN], 7835 flow_info->flow_idx_low_prio); 7836 if (high && low) { 7837 RTE_SWAP(*low, *high); 7838 flow_list_destroy(dev, MLX5_FLOW_TYPE_GEN, 7839 flow_info->flow_idx_low_prio); 7840 flow_info->flow_idx_high_prio = 0; 7841 } 7842 } 7843 flow_info = LIST_NEXT(flow_info, next); 7844 } 7845 return 0; 7846 err: 7847 /* Destroy preceding successful high priority rules. */ 7848 flow_info = LIST_FIRST(&mode_info->hot_upgrade); 7849 while (flow_info) { 7850 if (flow_info->orig_prio != flow_info->attr.priority) { 7851 if (flow_info->flow_idx_high_prio) 7852 flow_list_destroy(dev, MLX5_FLOW_TYPE_GEN, 7853 flow_info->flow_idx_high_prio); 7854 else 7855 break; 7856 flow_info->flow_idx_high_prio = 0; 7857 } 7858 flow_info = LIST_NEXT(flow_info, next); 7859 } 7860 return -1; 7861 } 7862 7863 /** 7864 * Set the mode of the flow engine of a process to active or standby during live migration. 7865 * 7866 * @param[in] mode 7867 * MLX5 flow engine mode, @see `enum mlx5_flow_engine_mode`. 7868 * @param[in] flags 7869 * Flow engine mode specific flags. 7870 * 7871 * @return 7872 * Negative value on error, positive on success. 7873 */ 7874 int 7875 rte_pmd_mlx5_flow_engine_set_mode(enum mlx5_flow_engine_mode mode, uint32_t flags) 7876 { 7877 struct mlx5_priv *priv; 7878 struct mlx5_flow_engine_mode_info *mode_info; 7879 struct mlx5_dv_flow_info *flow_info, *tmp_info; 7880 uint16_t port, port_id; 7881 uint16_t toggle_num = 0; 7882 struct rte_eth_dev *dev; 7883 enum mlx5_flow_engine_mode orig_mode; 7884 uint32_t orig_flags; 7885 bool need_toggle = false; 7886 7887 /* Check if flags combinations are supported. */ 7888 if (flags && flags != MLX5_FLOW_ENGINE_FLAG_STANDBY_DUP_INGRESS) { 7889 DRV_LOG(ERR, "Doesn't support such flags %u", flags); 7890 return -1; 7891 } 7892 MLX5_ETH_FOREACH_DEV(port, NULL) { 7893 dev = &rte_eth_devices[port]; 7894 priv = dev->data->dev_private; 7895 mode_info = &priv->mode_info; 7896 /* No mode change. Assume all devices hold the same mode. */ 7897 if (mode_info->mode == mode) { 7898 DRV_LOG(INFO, "Process flow engine has been in mode %u", mode); 7899 if (mode_info->mode_flag != flags && !LIST_EMPTY(&mode_info->hot_upgrade)) { 7900 DRV_LOG(ERR, "Port %u has rule cache with different flag %u\n", 7901 port, mode_info->mode_flag); 7902 orig_mode = mode_info->mode; 7903 orig_flags = mode_info->mode_flag; 7904 goto err; 7905 } 7906 mode_info->mode_flag = flags; 7907 toggle_num++; 7908 continue; 7909 } 7910 /* Active -> standby. */ 7911 if (mode == MLX5_FLOW_ENGINE_MODE_STANDBY) { 7912 if (!LIST_EMPTY(&mode_info->hot_upgrade)) { 7913 DRV_LOG(ERR, "Cached rule existed"); 7914 orig_mode = mode_info->mode; 7915 orig_flags = mode_info->mode_flag; 7916 goto err; 7917 } 7918 mode_info->mode_flag = flags; 7919 mode_info->mode = mode; 7920 toggle_num++; 7921 /* Standby -> active. */ 7922 } else if (mode == MLX5_FLOW_ENGINE_MODE_ACTIVE) { 7923 if (LIST_EMPTY(&mode_info->hot_upgrade)) { 7924 DRV_LOG(INFO, "No cached rule existed"); 7925 } else { 7926 if (mlx5_flow_cache_flow_toggle(dev, true)) { 7927 orig_mode = mode_info->mode; 7928 orig_flags = mode_info->mode_flag; 7929 need_toggle = true; 7930 goto err; 7931 } 7932 } 7933 toggle_num++; 7934 } 7935 } 7936 if (mode == MLX5_FLOW_ENGINE_MODE_ACTIVE) { 7937 /* Clear cache flow rules. */ 7938 MLX5_ETH_FOREACH_DEV(port, NULL) { 7939 priv = rte_eth_devices[port].data->dev_private; 7940 mode_info = &priv->mode_info; 7941 flow_info = LIST_FIRST(&mode_info->hot_upgrade); 7942 while (flow_info) { 7943 tmp_info = LIST_NEXT(flow_info, next); 7944 LIST_REMOVE(flow_info, next); 7945 mlx5_free(flow_info->actions); 7946 mlx5_free(flow_info->items); 7947 mlx5_free(flow_info); 7948 flow_info = tmp_info; 7949 } 7950 MLX5_ASSERT(LIST_EMPTY(&mode_info->hot_upgrade)); 7951 } 7952 } 7953 return toggle_num; 7954 err: 7955 /* Rollback all preceding successful ports. */ 7956 MLX5_ETH_FOREACH_DEV(port_id, NULL) { 7957 if (port_id == port) 7958 break; 7959 priv = rte_eth_devices[port_id].data->dev_private; 7960 mode_info = &priv->mode_info; 7961 if (need_toggle && !LIST_EMPTY(&mode_info->hot_upgrade) && 7962 mlx5_flow_cache_flow_toggle(dev, false)) 7963 return -EPERM; 7964 mode_info->mode = orig_mode; 7965 mode_info->mode_flag = orig_flags; 7966 } 7967 return -EINVAL; 7968 } 7969 /** 7970 * Create a flow. 7971 * 7972 * @see rte_flow_create() 7973 * @see rte_flow_ops 7974 */ 7975 struct rte_flow * 7976 mlx5_flow_create(struct rte_eth_dev *dev, 7977 const struct rte_flow_attr *attr, 7978 const struct rte_flow_item items[], 7979 const struct rte_flow_action actions[], 7980 struct rte_flow_error *error) 7981 { 7982 struct mlx5_priv *priv = dev->data->dev_private; 7983 struct rte_flow_attr *new_attr = (void *)(uintptr_t)attr; 7984 uint32_t prio = attr->priority; 7985 uint32_t flow_idx; 7986 7987 if (priv->sh->config.dv_flow_en == 2) { 7988 rte_flow_error_set(error, ENOTSUP, 7989 RTE_FLOW_ERROR_TYPE_UNSPECIFIED, 7990 NULL, 7991 "Flow non-Q creation not supported"); 7992 return NULL; 7993 } 7994 /* 7995 * If the device is not started yet, it is not allowed to created a 7996 * flow from application. PMD default flows and traffic control flows 7997 * are not affected. 7998 */ 7999 if (unlikely(!dev->data->dev_started)) { 8000 DRV_LOG(DEBUG, "port %u is not started when " 8001 "inserting a flow", dev->data->port_id); 8002 rte_flow_error_set(error, ENODEV, 8003 RTE_FLOW_ERROR_TYPE_UNSPECIFIED, 8004 NULL, 8005 "port not started"); 8006 return NULL; 8007 } 8008 if (unlikely(mlx5_need_cache_flow(priv, attr))) { 8009 if (attr->transfer || 8010 (attr->ingress && 8011 !(priv->mode_info.mode_flag & MLX5_FLOW_ENGINE_FLAG_STANDBY_DUP_INGRESS))) 8012 new_attr->priority += 1; 8013 } 8014 flow_idx = flow_list_create(dev, MLX5_FLOW_TYPE_GEN, attr, items, actions, true, error); 8015 if (!flow_idx) 8016 return NULL; 8017 if (unlikely(mlx5_need_cache_flow(priv, attr))) { 8018 if (mlx5_flow_cache_flow_info(dev, attr, prio, items, actions, flow_idx)) { 8019 flow_list_destroy(dev, MLX5_FLOW_TYPE_GEN, flow_idx); 8020 flow_idx = 0; 8021 } 8022 } 8023 return (void *)(uintptr_t)flow_idx; 8024 } 8025 8026 /** 8027 * Destroy a flow in a list. 8028 * 8029 * @param dev 8030 * Pointer to Ethernet device. 8031 * @param[in] flow_idx 8032 * Index of flow to destroy. 8033 */ 8034 static void 8035 flow_list_destroy(struct rte_eth_dev *dev, enum mlx5_flow_type type, 8036 uint32_t flow_idx) 8037 { 8038 struct mlx5_priv *priv = dev->data->dev_private; 8039 struct rte_flow *flow = mlx5_ipool_get(priv->flows[type], flow_idx); 8040 8041 if (!flow) 8042 return; 8043 MLX5_ASSERT(flow->type == type); 8044 /* 8045 * Update RX queue flags only if port is started, otherwise it is 8046 * already clean. 8047 */ 8048 if (dev->data->dev_started) 8049 flow_rxq_flags_trim(dev, flow); 8050 flow_drv_destroy(dev, flow); 8051 if (flow->tunnel) { 8052 struct mlx5_flow_tunnel *tunnel; 8053 8054 tunnel = mlx5_find_tunnel_id(dev, flow->tunnel_id); 8055 RTE_VERIFY(tunnel); 8056 if (!(__atomic_fetch_sub(&tunnel->refctn, 1, __ATOMIC_RELAXED) - 1)) 8057 mlx5_flow_tunnel_free(dev, tunnel); 8058 } 8059 flow_mreg_del_copy_action(dev, flow); 8060 mlx5_ipool_free(priv->flows[type], flow_idx); 8061 } 8062 8063 /** 8064 * Destroy all flows. 8065 * 8066 * @param dev 8067 * Pointer to Ethernet device. 8068 * @param type 8069 * Flow type to be flushed. 8070 * @param active 8071 * If flushing is called actively. 8072 */ 8073 void 8074 mlx5_flow_list_flush(struct rte_eth_dev *dev, enum mlx5_flow_type type, 8075 bool active) 8076 { 8077 struct mlx5_priv *priv = dev->data->dev_private; 8078 uint32_t num_flushed = 0, fidx = 1; 8079 struct rte_flow *flow; 8080 struct mlx5_flow_engine_mode_info *mode_info = &priv->mode_info; 8081 struct mlx5_dv_flow_info *flow_info; 8082 8083 #ifdef HAVE_IBV_FLOW_DV_SUPPORT 8084 if (priv->sh->config.dv_flow_en == 2 && 8085 type == MLX5_FLOW_TYPE_GEN) { 8086 flow_hw_q_flow_flush(dev, NULL); 8087 return; 8088 } 8089 #endif 8090 8091 MLX5_IPOOL_FOREACH(priv->flows[type], fidx, flow) { 8092 flow_list_destroy(dev, type, fidx); 8093 if (unlikely(mlx5_need_cache_flow(priv, NULL) && type == MLX5_FLOW_TYPE_GEN)) { 8094 flow_info = LIST_FIRST(&mode_info->hot_upgrade); 8095 while (flow_info) { 8096 /* Romove the cache flow info. */ 8097 if (flow_info->flow_idx_low_prio == (uint32_t)(uintptr_t)fidx) { 8098 MLX5_ASSERT(!flow_info->flow_idx_high_prio); 8099 LIST_REMOVE(flow_info, next); 8100 mlx5_free(flow_info->items); 8101 mlx5_free(flow_info->actions); 8102 mlx5_free(flow_info); 8103 break; 8104 } 8105 flow_info = LIST_NEXT(flow_info, next); 8106 } 8107 } 8108 num_flushed++; 8109 } 8110 if (active) { 8111 DRV_LOG(INFO, "port %u: %u flows flushed before stopping", 8112 dev->data->port_id, num_flushed); 8113 } 8114 } 8115 8116 /** 8117 * Stop all default actions for flows. 8118 * 8119 * @param dev 8120 * Pointer to Ethernet device. 8121 */ 8122 void 8123 mlx5_flow_stop_default(struct rte_eth_dev *dev) 8124 { 8125 flow_mreg_del_default_copy_action(dev); 8126 flow_rxq_flags_clear(dev); 8127 } 8128 8129 /** 8130 * Set rxq flag. 8131 * 8132 * @param[in] dev 8133 * Pointer to the rte_eth_dev structure. 8134 * @param[in] enable 8135 * Flag to enable or not. 8136 */ 8137 void 8138 flow_hw_rxq_flag_set(struct rte_eth_dev *dev, bool enable) 8139 { 8140 struct mlx5_priv *priv = dev->data->dev_private; 8141 unsigned int i; 8142 8143 if ((!priv->mark_enabled && !enable) || 8144 (priv->mark_enabled && enable)) 8145 return; 8146 for (i = 0; i < priv->rxqs_n; ++i) { 8147 struct mlx5_rxq_ctrl *rxq_ctrl = mlx5_rxq_ctrl_get(dev, i); 8148 8149 /* With RXQ start/stop feature, RXQ might be stopped. */ 8150 if (!rxq_ctrl) 8151 continue; 8152 rxq_ctrl->rxq.mark = enable; 8153 } 8154 priv->mark_enabled = enable; 8155 } 8156 8157 /** 8158 * Start all default actions for flows. 8159 * 8160 * @param dev 8161 * Pointer to Ethernet device. 8162 * @return 8163 * 0 on success, a negative errno value otherwise and rte_errno is set. 8164 */ 8165 int 8166 mlx5_flow_start_default(struct rte_eth_dev *dev) 8167 { 8168 struct rte_flow_error error; 8169 8170 /* Make sure default copy action (reg_c[0] -> reg_b) is created. */ 8171 return flow_mreg_add_default_copy_action(dev, &error); 8172 } 8173 8174 /** 8175 * Release key of thread specific flow workspace data. 8176 */ 8177 void 8178 flow_release_workspace(void *data) 8179 { 8180 struct mlx5_flow_workspace *wks = data; 8181 struct mlx5_flow_workspace *next; 8182 8183 while (wks) { 8184 next = wks->next; 8185 free(wks); 8186 wks = next; 8187 } 8188 } 8189 8190 static struct mlx5_flow_workspace *gc_head; 8191 static rte_spinlock_t mlx5_flow_workspace_lock = RTE_SPINLOCK_INITIALIZER; 8192 8193 static void 8194 mlx5_flow_workspace_gc_add(struct mlx5_flow_workspace *ws) 8195 { 8196 rte_spinlock_lock(&mlx5_flow_workspace_lock); 8197 ws->gc = gc_head; 8198 gc_head = ws; 8199 rte_spinlock_unlock(&mlx5_flow_workspace_lock); 8200 } 8201 8202 void 8203 mlx5_flow_workspace_gc_release(void) 8204 { 8205 while (gc_head) { 8206 struct mlx5_flow_workspace *wks = gc_head; 8207 8208 gc_head = wks->gc; 8209 flow_release_workspace(wks); 8210 } 8211 } 8212 8213 /** 8214 * Get thread specific current flow workspace. 8215 * 8216 * @return pointer to thread specific flow workspace data, NULL on error. 8217 */ 8218 struct mlx5_flow_workspace* 8219 mlx5_flow_get_thread_workspace(void) 8220 { 8221 struct mlx5_flow_workspace *data; 8222 8223 data = mlx5_flow_os_get_specific_workspace(); 8224 MLX5_ASSERT(data && data->inuse); 8225 if (!data || !data->inuse) 8226 DRV_LOG(ERR, "flow workspace not initialized."); 8227 return data; 8228 } 8229 8230 /** 8231 * Allocate and init new flow workspace. 8232 * 8233 * @return pointer to flow workspace data, NULL on error. 8234 */ 8235 static struct mlx5_flow_workspace* 8236 flow_alloc_thread_workspace(void) 8237 { 8238 size_t data_size = RTE_ALIGN(sizeof(struct mlx5_flow_workspace), sizeof(long)); 8239 size_t rss_queue_array_size = sizeof(uint16_t) * RTE_ETH_RSS_RETA_SIZE_512; 8240 struct mlx5_flow_workspace *data = calloc(1, data_size + 8241 rss_queue_array_size); 8242 8243 if (!data) { 8244 DRV_LOG(ERR, "Failed to allocate flow workspace memory."); 8245 return NULL; 8246 } 8247 data->rss_desc.queue = RTE_PTR_ADD(data, data_size); 8248 return data; 8249 } 8250 8251 /** 8252 * Get new thread specific flow workspace. 8253 * 8254 * If current workspace inuse, create new one and set as current. 8255 * 8256 * @return pointer to thread specific flow workspace data, NULL on error. 8257 */ 8258 struct mlx5_flow_workspace* 8259 mlx5_flow_push_thread_workspace(void) 8260 { 8261 struct mlx5_flow_workspace *curr; 8262 struct mlx5_flow_workspace *data; 8263 8264 curr = mlx5_flow_os_get_specific_workspace(); 8265 if (!curr) { 8266 data = flow_alloc_thread_workspace(); 8267 if (!data) 8268 return NULL; 8269 mlx5_flow_workspace_gc_add(data); 8270 } else if (!curr->inuse) { 8271 data = curr; 8272 } else if (curr->next) { 8273 data = curr->next; 8274 } else { 8275 data = flow_alloc_thread_workspace(); 8276 if (!data) 8277 return NULL; 8278 curr->next = data; 8279 data->prev = curr; 8280 } 8281 data->inuse = 1; 8282 data->flow_idx = 0; 8283 /* Set as current workspace */ 8284 if (mlx5_flow_os_set_specific_workspace(data)) 8285 DRV_LOG(ERR, "Failed to set flow workspace to thread."); 8286 return data; 8287 } 8288 8289 /** 8290 * Close current thread specific flow workspace. 8291 * 8292 * If previous workspace available, set it as current. 8293 * 8294 * @return pointer to thread specific flow workspace data, NULL on error. 8295 */ 8296 void 8297 mlx5_flow_pop_thread_workspace(void) 8298 { 8299 struct mlx5_flow_workspace *data = mlx5_flow_get_thread_workspace(); 8300 8301 if (!data) 8302 return; 8303 if (!data->inuse) { 8304 DRV_LOG(ERR, "Failed to close unused flow workspace."); 8305 return; 8306 } 8307 data->inuse = 0; 8308 if (!data->prev) 8309 return; 8310 if (mlx5_flow_os_set_specific_workspace(data->prev)) 8311 DRV_LOG(ERR, "Failed to set flow workspace to thread."); 8312 } 8313 8314 /** 8315 * Verify the flow list is empty 8316 * 8317 * @param dev 8318 * Pointer to Ethernet device. 8319 * 8320 * @return the number of flows not released. 8321 */ 8322 int 8323 mlx5_flow_verify(struct rte_eth_dev *dev __rte_unused) 8324 { 8325 struct mlx5_priv *priv = dev->data->dev_private; 8326 struct rte_flow *flow; 8327 uint32_t idx = 0; 8328 int ret = 0, i; 8329 8330 for (i = 0; i < MLX5_FLOW_TYPE_MAXI; i++) { 8331 MLX5_IPOOL_FOREACH(priv->flows[i], idx, flow) { 8332 DRV_LOG(DEBUG, "port %u flow %p still referenced", 8333 dev->data->port_id, (void *)flow); 8334 ret++; 8335 } 8336 } 8337 return ret; 8338 } 8339 8340 /** 8341 * Enable default hairpin egress flow. 8342 * 8343 * @param dev 8344 * Pointer to Ethernet device. 8345 * @param sq_num 8346 * The SQ hw number. 8347 * 8348 * @return 8349 * 0 on success, a negative errno value otherwise and rte_errno is set. 8350 */ 8351 int 8352 mlx5_ctrl_flow_source_queue(struct rte_eth_dev *dev, 8353 uint32_t sq_num) 8354 { 8355 const struct rte_flow_attr attr = { 8356 .egress = 1, 8357 .priority = 0, 8358 }; 8359 struct mlx5_rte_flow_item_sq queue_spec = { 8360 .queue = sq_num, 8361 }; 8362 struct mlx5_rte_flow_item_sq queue_mask = { 8363 .queue = UINT32_MAX, 8364 }; 8365 struct rte_flow_item items[] = { 8366 { 8367 .type = (enum rte_flow_item_type) 8368 MLX5_RTE_FLOW_ITEM_TYPE_SQ, 8369 .spec = &queue_spec, 8370 .last = NULL, 8371 .mask = &queue_mask, 8372 }, 8373 { 8374 .type = RTE_FLOW_ITEM_TYPE_END, 8375 }, 8376 }; 8377 struct rte_flow_action_jump jump = { 8378 .group = MLX5_HAIRPIN_TX_TABLE, 8379 }; 8380 struct rte_flow_action actions[2]; 8381 uint32_t flow_idx; 8382 struct rte_flow_error error; 8383 8384 actions[0].type = RTE_FLOW_ACTION_TYPE_JUMP; 8385 actions[0].conf = &jump; 8386 actions[1].type = RTE_FLOW_ACTION_TYPE_END; 8387 flow_idx = flow_list_create(dev, MLX5_FLOW_TYPE_CTL, 8388 &attr, items, actions, false, &error); 8389 if (!flow_idx) { 8390 DRV_LOG(DEBUG, 8391 "Failed to create ctrl flow: rte_errno(%d)," 8392 " type(%d), message(%s)", 8393 rte_errno, error.type, 8394 error.message ? error.message : " (no stated reason)"); 8395 return -rte_errno; 8396 } 8397 return 0; 8398 } 8399 8400 /** 8401 * Enable a control flow configured from the control plane. 8402 * 8403 * @param dev 8404 * Pointer to Ethernet device. 8405 * @param eth_spec 8406 * An Ethernet flow spec to apply. 8407 * @param eth_mask 8408 * An Ethernet flow mask to apply. 8409 * @param vlan_spec 8410 * A VLAN flow spec to apply. 8411 * @param vlan_mask 8412 * A VLAN flow mask to apply. 8413 * 8414 * @return 8415 * 0 on success, a negative errno value otherwise and rte_errno is set. 8416 */ 8417 int 8418 mlx5_ctrl_flow_vlan(struct rte_eth_dev *dev, 8419 struct rte_flow_item_eth *eth_spec, 8420 struct rte_flow_item_eth *eth_mask, 8421 struct rte_flow_item_vlan *vlan_spec, 8422 struct rte_flow_item_vlan *vlan_mask) 8423 { 8424 struct mlx5_priv *priv = dev->data->dev_private; 8425 const struct rte_flow_attr attr = { 8426 .ingress = 1, 8427 .priority = MLX5_FLOW_LOWEST_PRIO_INDICATOR, 8428 }; 8429 struct rte_flow_item items[] = { 8430 { 8431 .type = RTE_FLOW_ITEM_TYPE_ETH, 8432 .spec = eth_spec, 8433 .last = NULL, 8434 .mask = eth_mask, 8435 }, 8436 { 8437 .type = (vlan_spec) ? RTE_FLOW_ITEM_TYPE_VLAN : 8438 RTE_FLOW_ITEM_TYPE_END, 8439 .spec = vlan_spec, 8440 .last = NULL, 8441 .mask = vlan_mask, 8442 }, 8443 { 8444 .type = RTE_FLOW_ITEM_TYPE_END, 8445 }, 8446 }; 8447 uint16_t queue[priv->reta_idx_n]; 8448 struct rte_flow_action_rss action_rss = { 8449 .func = RTE_ETH_HASH_FUNCTION_DEFAULT, 8450 .level = 0, 8451 .types = priv->rss_conf.rss_hf, 8452 .key_len = priv->rss_conf.rss_key_len, 8453 .queue_num = priv->reta_idx_n, 8454 .key = priv->rss_conf.rss_key, 8455 .queue = queue, 8456 }; 8457 struct rte_flow_action actions[] = { 8458 { 8459 .type = RTE_FLOW_ACTION_TYPE_RSS, 8460 .conf = &action_rss, 8461 }, 8462 { 8463 .type = RTE_FLOW_ACTION_TYPE_END, 8464 }, 8465 }; 8466 uint32_t flow_idx; 8467 struct rte_flow_error error; 8468 unsigned int i; 8469 8470 if (!priv->reta_idx_n || !priv->rxqs_n) { 8471 return 0; 8472 } 8473 if (!(dev->data->dev_conf.rxmode.mq_mode & RTE_ETH_MQ_RX_RSS_FLAG)) 8474 action_rss.types = 0; 8475 for (i = 0; i != priv->reta_idx_n; ++i) 8476 queue[i] = (*priv->reta_idx)[i]; 8477 flow_idx = flow_list_create(dev, MLX5_FLOW_TYPE_CTL, 8478 &attr, items, actions, false, &error); 8479 if (!flow_idx) 8480 return -rte_errno; 8481 return 0; 8482 } 8483 8484 /** 8485 * Enable a flow control configured from the control plane. 8486 * 8487 * @param dev 8488 * Pointer to Ethernet device. 8489 * @param eth_spec 8490 * An Ethernet flow spec to apply. 8491 * @param eth_mask 8492 * An Ethernet flow mask to apply. 8493 * 8494 * @return 8495 * 0 on success, a negative errno value otherwise and rte_errno is set. 8496 */ 8497 int 8498 mlx5_ctrl_flow(struct rte_eth_dev *dev, 8499 struct rte_flow_item_eth *eth_spec, 8500 struct rte_flow_item_eth *eth_mask) 8501 { 8502 return mlx5_ctrl_flow_vlan(dev, eth_spec, eth_mask, NULL, NULL); 8503 } 8504 8505 /** 8506 * Create default miss flow rule matching lacp traffic 8507 * 8508 * @param dev 8509 * Pointer to Ethernet device. 8510 * @param eth_spec 8511 * An Ethernet flow spec to apply. 8512 * 8513 * @return 8514 * 0 on success, a negative errno value otherwise and rte_errno is set. 8515 */ 8516 int 8517 mlx5_flow_lacp_miss(struct rte_eth_dev *dev) 8518 { 8519 /* 8520 * The LACP matching is done by only using ether type since using 8521 * a multicast dst mac causes kernel to give low priority to this flow. 8522 */ 8523 static const struct rte_flow_item_eth lacp_spec = { 8524 .hdr.ether_type = RTE_BE16(0x8809), 8525 }; 8526 static const struct rte_flow_item_eth lacp_mask = { 8527 .hdr.ether_type = 0xffff, 8528 }; 8529 const struct rte_flow_attr attr = { 8530 .ingress = 1, 8531 }; 8532 struct rte_flow_item items[] = { 8533 { 8534 .type = RTE_FLOW_ITEM_TYPE_ETH, 8535 .spec = &lacp_spec, 8536 .mask = &lacp_mask, 8537 }, 8538 { 8539 .type = RTE_FLOW_ITEM_TYPE_END, 8540 }, 8541 }; 8542 struct rte_flow_action actions[] = { 8543 { 8544 .type = (enum rte_flow_action_type) 8545 MLX5_RTE_FLOW_ACTION_TYPE_DEFAULT_MISS, 8546 }, 8547 { 8548 .type = RTE_FLOW_ACTION_TYPE_END, 8549 }, 8550 }; 8551 struct rte_flow_error error; 8552 uint32_t flow_idx = flow_list_create(dev, MLX5_FLOW_TYPE_CTL, 8553 &attr, items, actions, 8554 false, &error); 8555 8556 if (!flow_idx) 8557 return -rte_errno; 8558 return 0; 8559 } 8560 8561 /** 8562 * Destroy a flow. 8563 * 8564 * @see rte_flow_destroy() 8565 * @see rte_flow_ops 8566 */ 8567 int 8568 mlx5_flow_destroy(struct rte_eth_dev *dev, 8569 struct rte_flow *flow, 8570 struct rte_flow_error *error __rte_unused) 8571 { 8572 struct mlx5_priv *priv = dev->data->dev_private; 8573 struct mlx5_flow_engine_mode_info *mode_info = &priv->mode_info; 8574 struct mlx5_dv_flow_info *flow_info; 8575 8576 if (priv->sh->config.dv_flow_en == 2) 8577 return rte_flow_error_set(error, ENOTSUP, 8578 RTE_FLOW_ERROR_TYPE_UNSPECIFIED, 8579 NULL, 8580 "Flow non-Q destruction not supported"); 8581 flow_list_destroy(dev, MLX5_FLOW_TYPE_GEN, 8582 (uintptr_t)(void *)flow); 8583 if (unlikely(mlx5_need_cache_flow(priv, NULL))) { 8584 flow_info = LIST_FIRST(&mode_info->hot_upgrade); 8585 while (flow_info) { 8586 /* Romove the cache flow info. */ 8587 if (flow_info->flow_idx_low_prio == (uint32_t)(uintptr_t)flow) { 8588 MLX5_ASSERT(!flow_info->flow_idx_high_prio); 8589 LIST_REMOVE(flow_info, next); 8590 mlx5_free(flow_info->items); 8591 mlx5_free(flow_info->actions); 8592 mlx5_free(flow_info); 8593 break; 8594 } 8595 flow_info = LIST_NEXT(flow_info, next); 8596 } 8597 } 8598 return 0; 8599 } 8600 8601 /** 8602 * Destroy all flows. 8603 * 8604 * @see rte_flow_flush() 8605 * @see rte_flow_ops 8606 */ 8607 int 8608 mlx5_flow_flush(struct rte_eth_dev *dev, 8609 struct rte_flow_error *error __rte_unused) 8610 { 8611 mlx5_flow_list_flush(dev, MLX5_FLOW_TYPE_GEN, false); 8612 return 0; 8613 } 8614 8615 /** 8616 * Isolated mode. 8617 * 8618 * @see rte_flow_isolate() 8619 * @see rte_flow_ops 8620 */ 8621 int 8622 mlx5_flow_isolate(struct rte_eth_dev *dev, 8623 int enable, 8624 struct rte_flow_error *error) 8625 { 8626 struct mlx5_priv *priv = dev->data->dev_private; 8627 8628 if (dev->data->dev_started) { 8629 rte_flow_error_set(error, EBUSY, 8630 RTE_FLOW_ERROR_TYPE_UNSPECIFIED, 8631 NULL, 8632 "port must be stopped first"); 8633 return -rte_errno; 8634 } 8635 if (!enable && !priv->sh->config.repr_matching) 8636 return rte_flow_error_set(error, ENOTSUP, RTE_FLOW_ERROR_TYPE_UNSPECIFIED, NULL, 8637 "isolated mode cannot be disabled when " 8638 "representor matching is disabled"); 8639 priv->isolated = !!enable; 8640 if (enable) 8641 dev->dev_ops = &mlx5_dev_ops_isolate; 8642 else 8643 dev->dev_ops = &mlx5_dev_ops; 8644 8645 dev->rx_descriptor_status = mlx5_rx_descriptor_status; 8646 dev->tx_descriptor_status = mlx5_tx_descriptor_status; 8647 8648 return 0; 8649 } 8650 8651 /** 8652 * Query a flow. 8653 * 8654 * @see rte_flow_query() 8655 * @see rte_flow_ops 8656 */ 8657 static int 8658 flow_drv_query(struct rte_eth_dev *dev, 8659 struct rte_flow *eflow, 8660 const struct rte_flow_action *actions, 8661 void *data, 8662 struct rte_flow_error *error) 8663 { 8664 struct mlx5_priv *priv = dev->data->dev_private; 8665 const struct mlx5_flow_driver_ops *fops; 8666 struct rte_flow *flow = NULL; 8667 enum mlx5_flow_drv_type ftype = MLX5_FLOW_TYPE_MIN; 8668 8669 if (priv->sh->config.dv_flow_en == 2) { 8670 #ifdef HAVE_MLX5_HWS_SUPPORT 8671 flow = eflow; 8672 ftype = MLX5_FLOW_TYPE_HW; 8673 #endif 8674 } else { 8675 flow = (struct rte_flow *)mlx5_ipool_get(priv->flows[MLX5_FLOW_TYPE_GEN], 8676 (uintptr_t)(void *)eflow); 8677 } 8678 if (!flow) { 8679 return rte_flow_error_set(error, ENOENT, 8680 RTE_FLOW_ERROR_TYPE_UNSPECIFIED, 8681 NULL, 8682 "invalid flow handle"); 8683 } 8684 if (ftype == MLX5_FLOW_TYPE_MIN) 8685 ftype = flow->drv_type; 8686 MLX5_ASSERT(ftype > MLX5_FLOW_TYPE_MIN && ftype < MLX5_FLOW_TYPE_MAX); 8687 fops = flow_get_drv_ops(ftype); 8688 8689 return fops->query(dev, flow, actions, data, error); 8690 } 8691 8692 /** 8693 * Query a flow. 8694 * 8695 * @see rte_flow_query() 8696 * @see rte_flow_ops 8697 */ 8698 int 8699 mlx5_flow_query(struct rte_eth_dev *dev, 8700 struct rte_flow *flow, 8701 const struct rte_flow_action *actions, 8702 void *data, 8703 struct rte_flow_error *error) 8704 { 8705 int ret; 8706 8707 ret = flow_drv_query(dev, flow, actions, data, 8708 error); 8709 if (ret < 0) 8710 return ret; 8711 return 0; 8712 } 8713 8714 /** 8715 * Get rte_flow callbacks. 8716 * 8717 * @param dev 8718 * Pointer to Ethernet device structure. 8719 * @param ops 8720 * Pointer to operation-specific structure. 8721 * 8722 * @return 0 8723 */ 8724 int 8725 mlx5_flow_ops_get(struct rte_eth_dev *dev __rte_unused, 8726 const struct rte_flow_ops **ops) 8727 { 8728 *ops = &mlx5_flow_ops; 8729 return 0; 8730 } 8731 8732 /** 8733 * Validate meter policy actions. 8734 * Dispatcher for action type specific validation. 8735 * 8736 * @param[in] dev 8737 * Pointer to the Ethernet device structure. 8738 * @param[in] action 8739 * The meter policy action object to validate. 8740 * @param[in] attr 8741 * Attributes of flow to determine steering domain. 8742 * @param[out] is_rss 8743 * Is RSS or not. 8744 * @param[out] domain_bitmap 8745 * Domain bitmap. 8746 * @param[out] is_def_policy 8747 * Is default policy or not. 8748 * @param[out] error 8749 * Perform verbose error reporting if not NULL. Initialized in case of 8750 * error only. 8751 * 8752 * @return 8753 * 0 on success, otherwise negative errno value. 8754 */ 8755 int 8756 mlx5_flow_validate_mtr_acts(struct rte_eth_dev *dev, 8757 const struct rte_flow_action *actions[RTE_COLORS], 8758 struct rte_flow_attr *attr, 8759 bool *is_rss, 8760 uint8_t *domain_bitmap, 8761 uint8_t *policy_mode, 8762 struct rte_mtr_error *error) 8763 { 8764 const struct mlx5_flow_driver_ops *fops; 8765 8766 fops = flow_get_drv_ops(MLX5_FLOW_TYPE_DV); 8767 return fops->validate_mtr_acts(dev, actions, attr, is_rss, 8768 domain_bitmap, policy_mode, error); 8769 } 8770 8771 /** 8772 * Destroy the meter table set. 8773 * 8774 * @param[in] dev 8775 * Pointer to Ethernet device. 8776 * @param[in] mtr_policy 8777 * Meter policy struct. 8778 */ 8779 void 8780 mlx5_flow_destroy_mtr_acts(struct rte_eth_dev *dev, 8781 struct mlx5_flow_meter_policy *mtr_policy) 8782 { 8783 const struct mlx5_flow_driver_ops *fops; 8784 8785 fops = flow_get_drv_ops(MLX5_FLOW_TYPE_DV); 8786 fops->destroy_mtr_acts(dev, mtr_policy); 8787 } 8788 8789 /** 8790 * Create policy action, lock free, 8791 * (mutex should be acquired by caller). 8792 * Dispatcher for action type specific call. 8793 * 8794 * @param[in] dev 8795 * Pointer to the Ethernet device structure. 8796 * @param[in] mtr_policy 8797 * Meter policy struct. 8798 * @param[in] action 8799 * Action specification used to create meter actions. 8800 * @param[in] attr 8801 * Flow rule attributes. 8802 * @param[out] error 8803 * Perform verbose error reporting if not NULL. Initialized in case of 8804 * error only. 8805 * 8806 * @return 8807 * 0 on success, otherwise negative errno value. 8808 */ 8809 int 8810 mlx5_flow_create_mtr_acts(struct rte_eth_dev *dev, 8811 struct mlx5_flow_meter_policy *mtr_policy, 8812 const struct rte_flow_action *actions[RTE_COLORS], 8813 struct rte_flow_attr *attr, 8814 struct rte_mtr_error *error) 8815 { 8816 const struct mlx5_flow_driver_ops *fops; 8817 8818 fops = flow_get_drv_ops(MLX5_FLOW_TYPE_DV); 8819 return fops->create_mtr_acts(dev, mtr_policy, actions, attr, error); 8820 } 8821 8822 /** 8823 * Create policy rules, lock free, 8824 * (mutex should be acquired by caller). 8825 * Dispatcher for action type specific call. 8826 * 8827 * @param[in] dev 8828 * Pointer to the Ethernet device structure. 8829 * @param[in] mtr_policy 8830 * Meter policy struct. 8831 * 8832 * @return 8833 * 0 on success, -1 otherwise. 8834 */ 8835 int 8836 mlx5_flow_create_policy_rules(struct rte_eth_dev *dev, 8837 struct mlx5_flow_meter_policy *mtr_policy) 8838 { 8839 const struct mlx5_flow_driver_ops *fops; 8840 8841 fops = flow_get_drv_ops(MLX5_FLOW_TYPE_DV); 8842 return fops->create_policy_rules(dev, mtr_policy); 8843 } 8844 8845 /** 8846 * Destroy policy rules, lock free, 8847 * (mutex should be acquired by caller). 8848 * Dispatcher for action type specific call. 8849 * 8850 * @param[in] dev 8851 * Pointer to the Ethernet device structure. 8852 * @param[in] mtr_policy 8853 * Meter policy struct. 8854 */ 8855 void 8856 mlx5_flow_destroy_policy_rules(struct rte_eth_dev *dev, 8857 struct mlx5_flow_meter_policy *mtr_policy) 8858 { 8859 const struct mlx5_flow_driver_ops *fops; 8860 8861 fops = flow_get_drv_ops(MLX5_FLOW_TYPE_DV); 8862 fops->destroy_policy_rules(dev, mtr_policy); 8863 } 8864 8865 /** 8866 * Destroy the default policy table set. 8867 * 8868 * @param[in] dev 8869 * Pointer to Ethernet device. 8870 */ 8871 void 8872 mlx5_flow_destroy_def_policy(struct rte_eth_dev *dev) 8873 { 8874 const struct mlx5_flow_driver_ops *fops; 8875 8876 fops = flow_get_drv_ops(MLX5_FLOW_TYPE_DV); 8877 fops->destroy_def_policy(dev); 8878 } 8879 8880 /** 8881 * Destroy the default policy table set. 8882 * 8883 * @param[in] dev 8884 * Pointer to Ethernet device. 8885 * 8886 * @return 8887 * 0 on success, -1 otherwise. 8888 */ 8889 int 8890 mlx5_flow_create_def_policy(struct rte_eth_dev *dev) 8891 { 8892 const struct mlx5_flow_driver_ops *fops; 8893 8894 fops = flow_get_drv_ops(MLX5_FLOW_TYPE_DV); 8895 return fops->create_def_policy(dev); 8896 } 8897 8898 /** 8899 * Create the needed meter and suffix tables. 8900 * 8901 * @param[in] dev 8902 * Pointer to Ethernet device. 8903 * 8904 * @return 8905 * 0 on success, -1 otherwise. 8906 */ 8907 int 8908 mlx5_flow_create_mtr_tbls(struct rte_eth_dev *dev, 8909 struct mlx5_flow_meter_info *fm, 8910 uint32_t mtr_idx, 8911 uint8_t domain_bitmap) 8912 { 8913 const struct mlx5_flow_driver_ops *fops; 8914 8915 fops = flow_get_drv_ops(MLX5_FLOW_TYPE_DV); 8916 return fops->create_mtr_tbls(dev, fm, mtr_idx, domain_bitmap); 8917 } 8918 8919 /** 8920 * Destroy the meter table set. 8921 * 8922 * @param[in] dev 8923 * Pointer to Ethernet device. 8924 * @param[in] tbl 8925 * Pointer to the meter table set. 8926 */ 8927 void 8928 mlx5_flow_destroy_mtr_tbls(struct rte_eth_dev *dev, 8929 struct mlx5_flow_meter_info *fm) 8930 { 8931 const struct mlx5_flow_driver_ops *fops; 8932 8933 fops = flow_get_drv_ops(MLX5_FLOW_TYPE_DV); 8934 fops->destroy_mtr_tbls(dev, fm); 8935 } 8936 8937 /** 8938 * Destroy the global meter drop table. 8939 * 8940 * @param[in] dev 8941 * Pointer to Ethernet device. 8942 */ 8943 void 8944 mlx5_flow_destroy_mtr_drop_tbls(struct rte_eth_dev *dev) 8945 { 8946 const struct mlx5_flow_driver_ops *fops; 8947 8948 fops = flow_get_drv_ops(MLX5_FLOW_TYPE_DV); 8949 fops->destroy_mtr_drop_tbls(dev); 8950 } 8951 8952 /** 8953 * Destroy the sub policy table with RX queue. 8954 * 8955 * @param[in] dev 8956 * Pointer to Ethernet device. 8957 * @param[in] mtr_policy 8958 * Pointer to meter policy table. 8959 */ 8960 void 8961 mlx5_flow_destroy_sub_policy_with_rxq(struct rte_eth_dev *dev, 8962 struct mlx5_flow_meter_policy *mtr_policy) 8963 { 8964 const struct mlx5_flow_driver_ops *fops; 8965 8966 fops = flow_get_drv_ops(MLX5_FLOW_TYPE_DV); 8967 fops->destroy_sub_policy_with_rxq(dev, mtr_policy); 8968 } 8969 8970 /** 8971 * Allocate the needed aso flow meter id. 8972 * 8973 * @param[in] dev 8974 * Pointer to Ethernet device. 8975 * 8976 * @return 8977 * Index to aso flow meter on success, NULL otherwise. 8978 */ 8979 uint32_t 8980 mlx5_flow_mtr_alloc(struct rte_eth_dev *dev) 8981 { 8982 const struct mlx5_flow_driver_ops *fops; 8983 8984 fops = flow_get_drv_ops(MLX5_FLOW_TYPE_DV); 8985 return fops->create_meter(dev); 8986 } 8987 8988 /** 8989 * Free the aso flow meter id. 8990 * 8991 * @param[in] dev 8992 * Pointer to Ethernet device. 8993 * @param[in] mtr_idx 8994 * Index to aso flow meter to be free. 8995 * 8996 * @return 8997 * 0 on success. 8998 */ 8999 void 9000 mlx5_flow_mtr_free(struct rte_eth_dev *dev, uint32_t mtr_idx) 9001 { 9002 const struct mlx5_flow_driver_ops *fops; 9003 9004 fops = flow_get_drv_ops(MLX5_FLOW_TYPE_DV); 9005 fops->free_meter(dev, mtr_idx); 9006 } 9007 9008 /** 9009 * Allocate a counter. 9010 * 9011 * @param[in] dev 9012 * Pointer to Ethernet device structure. 9013 * 9014 * @return 9015 * Index to allocated counter on success, 0 otherwise. 9016 */ 9017 uint32_t 9018 mlx5_counter_alloc(struct rte_eth_dev *dev) 9019 { 9020 struct rte_flow_attr attr = { .transfer = 0 }; 9021 9022 return flow_get_drv_ops(flow_get_drv_type(dev, &attr))->counter_alloc 9023 (dev); 9024 } 9025 9026 /** 9027 * Free a counter. 9028 * 9029 * @param[in] dev 9030 * Pointer to Ethernet device structure. 9031 * @param[in] cnt 9032 * Index to counter to be free. 9033 */ 9034 void 9035 mlx5_counter_free(struct rte_eth_dev *dev, uint32_t cnt) 9036 { 9037 struct rte_flow_attr attr = { .transfer = 0 }; 9038 9039 flow_get_drv_ops(flow_get_drv_type(dev, &attr))->counter_free(dev, cnt); 9040 } 9041 9042 /** 9043 * Query counter statistics. 9044 * 9045 * @param[in] dev 9046 * Pointer to Ethernet device structure. 9047 * @param[in] cnt 9048 * Index to counter to query. 9049 * @param[in] clear 9050 * Set to clear counter statistics. 9051 * @param[out] pkts 9052 * The counter hits packets number to save. 9053 * @param[out] bytes 9054 * The counter hits bytes number to save. 9055 * 9056 * @return 9057 * 0 on success, a negative errno value otherwise. 9058 */ 9059 int 9060 mlx5_counter_query(struct rte_eth_dev *dev, uint32_t cnt, 9061 bool clear, uint64_t *pkts, uint64_t *bytes, void **action) 9062 { 9063 struct rte_flow_attr attr = { .transfer = 0 }; 9064 9065 return flow_get_drv_ops(flow_get_drv_type(dev, &attr))->counter_query 9066 (dev, cnt, clear, pkts, bytes, action); 9067 } 9068 9069 /** 9070 * Get information about HWS pre-configurable resources. 9071 * 9072 * @param[in] dev 9073 * Pointer to the rte_eth_dev structure. 9074 * @param[out] port_info 9075 * Pointer to port information. 9076 * @param[out] queue_info 9077 * Pointer to queue information. 9078 * @param[out] error 9079 * Pointer to error structure. 9080 * 9081 * @return 9082 * 0 on success, a negative errno value otherwise and rte_errno is set. 9083 */ 9084 static int 9085 mlx5_flow_info_get(struct rte_eth_dev *dev, 9086 struct rte_flow_port_info *port_info, 9087 struct rte_flow_queue_info *queue_info, 9088 struct rte_flow_error *error) 9089 { 9090 const struct mlx5_flow_driver_ops *fops; 9091 struct rte_flow_attr attr = {0}; 9092 9093 if (flow_get_drv_type(dev, &attr) != MLX5_FLOW_TYPE_HW) 9094 return rte_flow_error_set(error, ENOTSUP, 9095 RTE_FLOW_ERROR_TYPE_UNSPECIFIED, 9096 NULL, 9097 "info get with incorrect steering mode"); 9098 fops = flow_get_drv_ops(MLX5_FLOW_TYPE_HW); 9099 return fops->info_get(dev, port_info, queue_info, error); 9100 } 9101 9102 /** 9103 * Configure port HWS resources. 9104 * 9105 * @param[in] dev 9106 * Pointer to the rte_eth_dev structure. 9107 * @param[in] port_attr 9108 * Port configuration attributes. 9109 * @param[in] nb_queue 9110 * Number of queue. 9111 * @param[in] queue_attr 9112 * Array that holds attributes for each flow queue. 9113 * @param[out] error 9114 * Pointer to error structure. 9115 * 9116 * @return 9117 * 0 on success, a negative errno value otherwise and rte_errno is set. 9118 */ 9119 static int 9120 mlx5_flow_port_configure(struct rte_eth_dev *dev, 9121 const struct rte_flow_port_attr *port_attr, 9122 uint16_t nb_queue, 9123 const struct rte_flow_queue_attr *queue_attr[], 9124 struct rte_flow_error *error) 9125 { 9126 const struct mlx5_flow_driver_ops *fops; 9127 struct rte_flow_attr attr = {0}; 9128 9129 if (flow_get_drv_type(dev, &attr) != MLX5_FLOW_TYPE_HW) 9130 return rte_flow_error_set(error, ENOTSUP, 9131 RTE_FLOW_ERROR_TYPE_UNSPECIFIED, 9132 NULL, 9133 "port configure with incorrect steering mode"); 9134 fops = flow_get_drv_ops(MLX5_FLOW_TYPE_HW); 9135 return fops->configure(dev, port_attr, nb_queue, queue_attr, error); 9136 } 9137 9138 /** 9139 * Validate item template. 9140 * 9141 * @param[in] dev 9142 * Pointer to the rte_eth_dev structure. 9143 * @param[in] attr 9144 * Pointer to the item template attributes. 9145 * @param[in] items 9146 * The template item pattern. 9147 * @param[out] error 9148 * Pointer to error structure. 9149 * 9150 * @return 9151 * 0 on success, a negative errno value otherwise and rte_errno is set. 9152 */ 9153 int 9154 mlx5_flow_pattern_validate(struct rte_eth_dev *dev, 9155 const struct rte_flow_pattern_template_attr *attr, 9156 const struct rte_flow_item items[], 9157 struct rte_flow_error *error) 9158 { 9159 const struct mlx5_flow_driver_ops *fops; 9160 struct rte_flow_attr fattr = {0}; 9161 9162 if (flow_get_drv_type(dev, &fattr) != MLX5_FLOW_TYPE_HW) { 9163 rte_flow_error_set(error, ENOTSUP, 9164 RTE_FLOW_ERROR_TYPE_UNSPECIFIED, NULL, 9165 "pattern validate with incorrect steering mode"); 9166 return -ENOTSUP; 9167 } 9168 fops = flow_get_drv_ops(MLX5_FLOW_TYPE_HW); 9169 return fops->pattern_validate(dev, attr, items, error); 9170 } 9171 9172 /** 9173 * Create flow item template. 9174 * 9175 * @param[in] dev 9176 * Pointer to the rte_eth_dev structure. 9177 * @param[in] attr 9178 * Pointer to the item template attributes. 9179 * @param[in] items 9180 * The template item pattern. 9181 * @param[out] error 9182 * Pointer to error structure. 9183 * 9184 * @return 9185 * 0 on success, a negative errno value otherwise and rte_errno is set. 9186 */ 9187 static struct rte_flow_pattern_template * 9188 mlx5_flow_pattern_template_create(struct rte_eth_dev *dev, 9189 const struct rte_flow_pattern_template_attr *attr, 9190 const struct rte_flow_item items[], 9191 struct rte_flow_error *error) 9192 { 9193 const struct mlx5_flow_driver_ops *fops; 9194 struct rte_flow_attr fattr = {0}; 9195 9196 if (flow_get_drv_type(dev, &fattr) != MLX5_FLOW_TYPE_HW) { 9197 rte_flow_error_set(error, ENOTSUP, 9198 RTE_FLOW_ERROR_TYPE_UNSPECIFIED, 9199 NULL, 9200 "pattern create with incorrect steering mode"); 9201 return NULL; 9202 } 9203 fops = flow_get_drv_ops(MLX5_FLOW_TYPE_HW); 9204 return fops->pattern_template_create(dev, attr, items, error); 9205 } 9206 9207 /** 9208 * Destroy flow item template. 9209 * 9210 * @param[in] dev 9211 * Pointer to the rte_eth_dev structure. 9212 * @param[in] template 9213 * Pointer to the item template to be destroyed. 9214 * @param[out] error 9215 * Pointer to error structure. 9216 * 9217 * @return 9218 * 0 on success, a negative errno value otherwise and rte_errno is set. 9219 */ 9220 static int 9221 mlx5_flow_pattern_template_destroy(struct rte_eth_dev *dev, 9222 struct rte_flow_pattern_template *template, 9223 struct rte_flow_error *error) 9224 { 9225 const struct mlx5_flow_driver_ops *fops; 9226 struct rte_flow_attr attr = {0}; 9227 9228 if (flow_get_drv_type(dev, &attr) != MLX5_FLOW_TYPE_HW) 9229 return rte_flow_error_set(error, ENOTSUP, 9230 RTE_FLOW_ERROR_TYPE_UNSPECIFIED, 9231 NULL, 9232 "pattern destroy with incorrect steering mode"); 9233 fops = flow_get_drv_ops(MLX5_FLOW_TYPE_HW); 9234 return fops->pattern_template_destroy(dev, template, error); 9235 } 9236 9237 /** 9238 * Validate flow actions template. 9239 * 9240 * @param[in] dev 9241 * Pointer to the rte_eth_dev structure. 9242 * @param[in] attr 9243 * Pointer to the action template attributes. 9244 * @param[in] actions 9245 * Associated actions (list terminated by the END action). 9246 * @param[in] masks 9247 * List of actions that marks which of the action's member is constant. 9248 * @param[out] error 9249 * Pointer to error structure. 9250 * 9251 * @return 9252 * 0 on success, a negative errno value otherwise and rte_errno is set. 9253 */ 9254 int 9255 mlx5_flow_actions_validate(struct rte_eth_dev *dev, 9256 const struct rte_flow_actions_template_attr *attr, 9257 const struct rte_flow_action actions[], 9258 const struct rte_flow_action masks[], 9259 struct rte_flow_error *error) 9260 { 9261 const struct mlx5_flow_driver_ops *fops; 9262 struct rte_flow_attr fattr = {0}; 9263 9264 if (flow_get_drv_type(dev, &fattr) != MLX5_FLOW_TYPE_HW) { 9265 rte_flow_error_set(error, ENOTSUP, 9266 RTE_FLOW_ERROR_TYPE_UNSPECIFIED, NULL, 9267 "actions validate with incorrect steering mode"); 9268 return -ENOTSUP; 9269 } 9270 fops = flow_get_drv_ops(MLX5_FLOW_TYPE_HW); 9271 return fops->actions_validate(dev, attr, actions, masks, error); 9272 } 9273 9274 /** 9275 * Create flow item template. 9276 * 9277 * @param[in] dev 9278 * Pointer to the rte_eth_dev structure. 9279 * @param[in] attr 9280 * Pointer to the action template attributes. 9281 * @param[in] actions 9282 * Associated actions (list terminated by the END action). 9283 * @param[in] masks 9284 * List of actions that marks which of the action's member is constant. 9285 * @param[out] error 9286 * Pointer to error structure. 9287 * 9288 * @return 9289 * 0 on success, a negative errno value otherwise and rte_errno is set. 9290 */ 9291 static struct rte_flow_actions_template * 9292 mlx5_flow_actions_template_create(struct rte_eth_dev *dev, 9293 const struct rte_flow_actions_template_attr *attr, 9294 const struct rte_flow_action actions[], 9295 const struct rte_flow_action masks[], 9296 struct rte_flow_error *error) 9297 { 9298 const struct mlx5_flow_driver_ops *fops; 9299 struct rte_flow_attr fattr = {0}; 9300 9301 if (flow_get_drv_type(dev, &fattr) != MLX5_FLOW_TYPE_HW) { 9302 rte_flow_error_set(error, ENOTSUP, 9303 RTE_FLOW_ERROR_TYPE_UNSPECIFIED, 9304 NULL, 9305 "action create with incorrect steering mode"); 9306 return NULL; 9307 } 9308 fops = flow_get_drv_ops(MLX5_FLOW_TYPE_HW); 9309 return fops->actions_template_create(dev, attr, actions, masks, error); 9310 } 9311 9312 /** 9313 * Destroy flow action template. 9314 * 9315 * @param[in] dev 9316 * Pointer to the rte_eth_dev structure. 9317 * @param[in] template 9318 * Pointer to the action template to be destroyed. 9319 * @param[out] error 9320 * Pointer to error structure. 9321 * 9322 * @return 9323 * 0 on success, a negative errno value otherwise and rte_errno is set. 9324 */ 9325 static int 9326 mlx5_flow_actions_template_destroy(struct rte_eth_dev *dev, 9327 struct rte_flow_actions_template *template, 9328 struct rte_flow_error *error) 9329 { 9330 const struct mlx5_flow_driver_ops *fops; 9331 struct rte_flow_attr attr = {0}; 9332 9333 if (flow_get_drv_type(dev, &attr) != MLX5_FLOW_TYPE_HW) 9334 return rte_flow_error_set(error, ENOTSUP, 9335 RTE_FLOW_ERROR_TYPE_UNSPECIFIED, 9336 NULL, 9337 "action destroy with incorrect steering mode"); 9338 fops = flow_get_drv_ops(MLX5_FLOW_TYPE_HW); 9339 return fops->actions_template_destroy(dev, template, error); 9340 } 9341 9342 /** 9343 * Create flow table. 9344 * 9345 * @param[in] dev 9346 * Pointer to the rte_eth_dev structure. 9347 * @param[in] attr 9348 * Pointer to the table attributes. 9349 * @param[in] item_templates 9350 * Item template array to be binded to the table. 9351 * @param[in] nb_item_templates 9352 * Number of item template. 9353 * @param[in] action_templates 9354 * Action template array to be binded to the table. 9355 * @param[in] nb_action_templates 9356 * Number of action template. 9357 * @param[out] error 9358 * Pointer to error structure. 9359 * 9360 * @return 9361 * Table on success, NULL otherwise and rte_errno is set. 9362 */ 9363 static struct rte_flow_template_table * 9364 mlx5_flow_table_create(struct rte_eth_dev *dev, 9365 const struct rte_flow_template_table_attr *attr, 9366 struct rte_flow_pattern_template *item_templates[], 9367 uint8_t nb_item_templates, 9368 struct rte_flow_actions_template *action_templates[], 9369 uint8_t nb_action_templates, 9370 struct rte_flow_error *error) 9371 { 9372 const struct mlx5_flow_driver_ops *fops; 9373 struct rte_flow_attr fattr = {0}; 9374 9375 if (flow_get_drv_type(dev, &fattr) != MLX5_FLOW_TYPE_HW) { 9376 rte_flow_error_set(error, ENOTSUP, 9377 RTE_FLOW_ERROR_TYPE_UNSPECIFIED, 9378 NULL, 9379 "table create with incorrect steering mode"); 9380 return NULL; 9381 } 9382 fops = flow_get_drv_ops(MLX5_FLOW_TYPE_HW); 9383 return fops->template_table_create(dev, 9384 attr, 9385 item_templates, 9386 nb_item_templates, 9387 action_templates, 9388 nb_action_templates, 9389 error); 9390 } 9391 9392 /** 9393 * PMD destroy flow table. 9394 * 9395 * @param[in] dev 9396 * Pointer to the rte_eth_dev structure. 9397 * @param[in] table 9398 * Pointer to the table to be destroyed. 9399 * @param[out] error 9400 * Pointer to error structure. 9401 * 9402 * @return 9403 * 0 on success, a negative errno value otherwise and rte_errno is set. 9404 */ 9405 static int 9406 mlx5_flow_table_destroy(struct rte_eth_dev *dev, 9407 struct rte_flow_template_table *table, 9408 struct rte_flow_error *error) 9409 { 9410 const struct mlx5_flow_driver_ops *fops; 9411 struct rte_flow_attr attr = {0}; 9412 9413 if (flow_get_drv_type(dev, &attr) != MLX5_FLOW_TYPE_HW) 9414 return rte_flow_error_set(error, ENOTSUP, 9415 RTE_FLOW_ERROR_TYPE_UNSPECIFIED, 9416 NULL, 9417 "table destroy with incorrect steering mode"); 9418 fops = flow_get_drv_ops(MLX5_FLOW_TYPE_HW); 9419 return fops->template_table_destroy(dev, table, error); 9420 } 9421 9422 /** 9423 * PMD group set miss actions. 9424 * 9425 * @param[in] dev 9426 * Pointer to the rte_eth_dev structure. 9427 * @param[in] attr 9428 * Pointer to group attributes 9429 * @param[in] actions 9430 * Array of actions 9431 * @param[out] error 9432 * Pointer to error structure. 9433 * 9434 * @return 9435 * 0 on success, a negative errno value otherwise and rte_errno is set. 9436 */ 9437 static int 9438 mlx5_flow_group_set_miss_actions(struct rte_eth_dev *dev, 9439 uint32_t group_id, 9440 const struct rte_flow_group_attr *attr, 9441 const struct rte_flow_action actions[], 9442 struct rte_flow_error *error) 9443 { 9444 const struct mlx5_flow_driver_ops *fops; 9445 struct rte_flow_attr fattr = {0}; 9446 9447 if (flow_get_drv_type(dev, &fattr) != MLX5_FLOW_TYPE_HW) 9448 return rte_flow_error_set(error, ENOTSUP, 9449 RTE_FLOW_ERROR_TYPE_UNSPECIFIED, 9450 NULL, 9451 "group set miss actions with incorrect steering mode"); 9452 fops = flow_get_drv_ops(MLX5_FLOW_TYPE_HW); 9453 return fops->group_set_miss_actions(dev, group_id, attr, actions, error); 9454 } 9455 9456 /** 9457 * Enqueue flow creation. 9458 * 9459 * @param[in] dev 9460 * Pointer to the rte_eth_dev structure. 9461 * @param[in] queue_id 9462 * The queue to create the flow. 9463 * @param[in] attr 9464 * Pointer to the flow operation attributes. 9465 * @param[in] items 9466 * Items with flow spec value. 9467 * @param[in] pattern_template_index 9468 * The item pattern flow follows from the table. 9469 * @param[in] actions 9470 * Action with flow spec value. 9471 * @param[in] action_template_index 9472 * The action pattern flow follows from the table. 9473 * @param[in] user_data 9474 * Pointer to the user_data. 9475 * @param[out] error 9476 * Pointer to error structure. 9477 * 9478 * @return 9479 * Flow pointer on success, NULL otherwise and rte_errno is set. 9480 */ 9481 static struct rte_flow * 9482 mlx5_flow_async_flow_create(struct rte_eth_dev *dev, 9483 uint32_t queue_id, 9484 const struct rte_flow_op_attr *attr, 9485 struct rte_flow_template_table *table, 9486 const struct rte_flow_item items[], 9487 uint8_t pattern_template_index, 9488 const struct rte_flow_action actions[], 9489 uint8_t action_template_index, 9490 void *user_data, 9491 struct rte_flow_error *error) 9492 { 9493 const struct mlx5_flow_driver_ops *fops; 9494 struct rte_flow_attr fattr = {0}; 9495 9496 if (flow_get_drv_type(dev, &fattr) != MLX5_FLOW_TYPE_HW) { 9497 rte_flow_error_set(error, ENOTSUP, 9498 RTE_FLOW_ERROR_TYPE_UNSPECIFIED, 9499 NULL, 9500 "flow_q create with incorrect steering mode"); 9501 return NULL; 9502 } 9503 fops = flow_get_drv_ops(MLX5_FLOW_TYPE_HW); 9504 return fops->async_flow_create(dev, queue_id, attr, table, 9505 items, pattern_template_index, 9506 actions, action_template_index, 9507 user_data, error); 9508 } 9509 9510 /** 9511 * Enqueue flow creation by index. 9512 * 9513 * @param[in] dev 9514 * Pointer to the rte_eth_dev structure. 9515 * @param[in] queue_id 9516 * The queue to create the flow. 9517 * @param[in] attr 9518 * Pointer to the flow operation attributes. 9519 * @param[in] rule_index 9520 * The item pattern flow follows from the table. 9521 * @param[in] actions 9522 * Action with flow spec value. 9523 * @param[in] action_template_index 9524 * The action pattern flow follows from the table. 9525 * @param[in] user_data 9526 * Pointer to the user_data. 9527 * @param[out] error 9528 * Pointer to error structure. 9529 * 9530 * @return 9531 * Flow pointer on success, NULL otherwise and rte_errno is set. 9532 */ 9533 static struct rte_flow * 9534 mlx5_flow_async_flow_create_by_index(struct rte_eth_dev *dev, 9535 uint32_t queue_id, 9536 const struct rte_flow_op_attr *attr, 9537 struct rte_flow_template_table *table, 9538 uint32_t rule_index, 9539 const struct rte_flow_action actions[], 9540 uint8_t action_template_index, 9541 void *user_data, 9542 struct rte_flow_error *error) 9543 { 9544 const struct mlx5_flow_driver_ops *fops; 9545 struct rte_flow_attr fattr = {0}; 9546 9547 if (flow_get_drv_type(dev, &fattr) != MLX5_FLOW_TYPE_HW) { 9548 rte_flow_error_set(error, ENOTSUP, 9549 RTE_FLOW_ERROR_TYPE_UNSPECIFIED, 9550 NULL, 9551 "flow_q create with incorrect steering mode"); 9552 return NULL; 9553 } 9554 fops = flow_get_drv_ops(MLX5_FLOW_TYPE_HW); 9555 return fops->async_flow_create_by_index(dev, queue_id, attr, table, 9556 rule_index, actions, action_template_index, 9557 user_data, error); 9558 } 9559 9560 /** 9561 * Enqueue flow update. 9562 * 9563 * @param[in] dev 9564 * Pointer to the rte_eth_dev structure. 9565 * @param[in] queue 9566 * The queue to destroy the flow. 9567 * @param[in] attr 9568 * Pointer to the flow operation attributes. 9569 * @param[in] flow 9570 * Pointer to the flow to be destroyed. 9571 * @param[in] actions 9572 * Action with flow spec value. 9573 * @param[in] action_template_index 9574 * The action pattern flow follows from the table. 9575 * @param[in] user_data 9576 * Pointer to the user_data. 9577 * @param[out] error 9578 * Pointer to error structure. 9579 * 9580 * @return 9581 * 0 on success, negative value otherwise and rte_errno is set. 9582 */ 9583 static int 9584 mlx5_flow_async_flow_update(struct rte_eth_dev *dev, 9585 uint32_t queue, 9586 const struct rte_flow_op_attr *attr, 9587 struct rte_flow *flow, 9588 const struct rte_flow_action actions[], 9589 uint8_t action_template_index, 9590 void *user_data, 9591 struct rte_flow_error *error) 9592 { 9593 const struct mlx5_flow_driver_ops *fops; 9594 struct rte_flow_attr fattr = {0}; 9595 9596 if (flow_get_drv_type(dev, &fattr) != MLX5_FLOW_TYPE_HW) 9597 return rte_flow_error_set(error, ENOTSUP, 9598 RTE_FLOW_ERROR_TYPE_UNSPECIFIED, 9599 NULL, 9600 "flow_q update with incorrect steering mode"); 9601 fops = flow_get_drv_ops(MLX5_FLOW_TYPE_HW); 9602 return fops->async_flow_update(dev, queue, attr, flow, 9603 actions, action_template_index, user_data, error); 9604 } 9605 9606 /** 9607 * Enqueue flow destruction. 9608 * 9609 * @param[in] dev 9610 * Pointer to the rte_eth_dev structure. 9611 * @param[in] queue 9612 * The queue to destroy the flow. 9613 * @param[in] attr 9614 * Pointer to the flow operation attributes. 9615 * @param[in] flow 9616 * Pointer to the flow to be destroyed. 9617 * @param[in] user_data 9618 * Pointer to the user_data. 9619 * @param[out] error 9620 * Pointer to error structure. 9621 * 9622 * @return 9623 * 0 on success, negative value otherwise and rte_errno is set. 9624 */ 9625 static int 9626 mlx5_flow_async_flow_destroy(struct rte_eth_dev *dev, 9627 uint32_t queue, 9628 const struct rte_flow_op_attr *attr, 9629 struct rte_flow *flow, 9630 void *user_data, 9631 struct rte_flow_error *error) 9632 { 9633 const struct mlx5_flow_driver_ops *fops; 9634 struct rte_flow_attr fattr = {0}; 9635 9636 if (flow_get_drv_type(dev, &fattr) != MLX5_FLOW_TYPE_HW) 9637 return rte_flow_error_set(error, ENOTSUP, 9638 RTE_FLOW_ERROR_TYPE_UNSPECIFIED, 9639 NULL, 9640 "flow_q destroy with incorrect steering mode"); 9641 fops = flow_get_drv_ops(MLX5_FLOW_TYPE_HW); 9642 return fops->async_flow_destroy(dev, queue, attr, flow, 9643 user_data, error); 9644 } 9645 9646 /** 9647 * Pull the enqueued flows. 9648 * 9649 * @param[in] dev 9650 * Pointer to the rte_eth_dev structure. 9651 * @param[in] queue 9652 * The queue to pull the result. 9653 * @param[in/out] res 9654 * Array to save the results. 9655 * @param[in] n_res 9656 * Available result with the array. 9657 * @param[out] error 9658 * Pointer to error structure. 9659 * 9660 * @return 9661 * Result number on success, negative value otherwise and rte_errno is set. 9662 */ 9663 static int 9664 mlx5_flow_pull(struct rte_eth_dev *dev, 9665 uint32_t queue, 9666 struct rte_flow_op_result res[], 9667 uint16_t n_res, 9668 struct rte_flow_error *error) 9669 { 9670 const struct mlx5_flow_driver_ops *fops; 9671 struct rte_flow_attr attr = {0}; 9672 9673 if (flow_get_drv_type(dev, &attr) != MLX5_FLOW_TYPE_HW) 9674 return rte_flow_error_set(error, ENOTSUP, 9675 RTE_FLOW_ERROR_TYPE_UNSPECIFIED, 9676 NULL, 9677 "flow_q pull with incorrect steering mode"); 9678 fops = flow_get_drv_ops(MLX5_FLOW_TYPE_HW); 9679 return fops->pull(dev, queue, res, n_res, error); 9680 } 9681 9682 /** 9683 * Push the enqueued flows. 9684 * 9685 * @param[in] dev 9686 * Pointer to the rte_eth_dev structure. 9687 * @param[in] queue 9688 * The queue to push the flows. 9689 * @param[out] error 9690 * Pointer to error structure. 9691 * 9692 * @return 9693 * 0 on success, negative value otherwise and rte_errno is set. 9694 */ 9695 static int 9696 mlx5_flow_push(struct rte_eth_dev *dev, 9697 uint32_t queue, 9698 struct rte_flow_error *error) 9699 { 9700 const struct mlx5_flow_driver_ops *fops; 9701 struct rte_flow_attr attr = {0}; 9702 9703 if (flow_get_drv_type(dev, &attr) != MLX5_FLOW_TYPE_HW) 9704 return rte_flow_error_set(error, ENOTSUP, 9705 RTE_FLOW_ERROR_TYPE_UNSPECIFIED, 9706 NULL, 9707 "flow_q push with incorrect steering mode"); 9708 fops = flow_get_drv_ops(MLX5_FLOW_TYPE_HW); 9709 return fops->push(dev, queue, error); 9710 } 9711 9712 /** 9713 * Create shared action. 9714 * 9715 * @param[in] dev 9716 * Pointer to the rte_eth_dev structure. 9717 * @param[in] queue 9718 * Which queue to be used.. 9719 * @param[in] attr 9720 * Operation attribute. 9721 * @param[in] conf 9722 * Indirect action configuration. 9723 * @param[in] action 9724 * rte_flow action detail. 9725 * @param[in] user_data 9726 * Pointer to the user_data. 9727 * @param[out] error 9728 * Pointer to error structure. 9729 * 9730 * @return 9731 * Action handle on success, NULL otherwise and rte_errno is set. 9732 */ 9733 static struct rte_flow_action_handle * 9734 mlx5_flow_async_action_handle_create(struct rte_eth_dev *dev, uint32_t queue, 9735 const struct rte_flow_op_attr *attr, 9736 const struct rte_flow_indir_action_conf *conf, 9737 const struct rte_flow_action *action, 9738 void *user_data, 9739 struct rte_flow_error *error) 9740 { 9741 const struct mlx5_flow_driver_ops *fops = 9742 flow_get_drv_ops(MLX5_FLOW_TYPE_HW); 9743 9744 return fops->async_action_create(dev, queue, attr, conf, action, 9745 user_data, error); 9746 } 9747 9748 /** 9749 * Update shared action. 9750 * 9751 * @param[in] dev 9752 * Pointer to the rte_eth_dev structure. 9753 * @param[in] queue 9754 * Which queue to be used.. 9755 * @param[in] attr 9756 * Operation attribute. 9757 * @param[in] handle 9758 * Action handle to be updated. 9759 * @param[in] update 9760 * Update value. 9761 * @param[in] user_data 9762 * Pointer to the user_data. 9763 * @param[out] error 9764 * Pointer to error structure. 9765 * 9766 * @return 9767 * 0 on success, negative value otherwise and rte_errno is set. 9768 */ 9769 static int 9770 mlx5_flow_async_action_handle_update(struct rte_eth_dev *dev, uint32_t queue, 9771 const struct rte_flow_op_attr *attr, 9772 struct rte_flow_action_handle *handle, 9773 const void *update, 9774 void *user_data, 9775 struct rte_flow_error *error) 9776 { 9777 const struct mlx5_flow_driver_ops *fops = 9778 flow_get_drv_ops(MLX5_FLOW_TYPE_HW); 9779 9780 return fops->async_action_update(dev, queue, attr, handle, 9781 update, user_data, error); 9782 } 9783 9784 static int 9785 mlx5_flow_async_action_handle_query_update 9786 (struct rte_eth_dev *dev, uint32_t queue_id, 9787 const struct rte_flow_op_attr *op_attr, 9788 struct rte_flow_action_handle *action_handle, 9789 const void *update, void *query, 9790 enum rte_flow_query_update_mode qu_mode, 9791 void *user_data, struct rte_flow_error *error) 9792 { 9793 const struct mlx5_flow_driver_ops *fops = 9794 flow_get_drv_ops(MLX5_FLOW_TYPE_HW); 9795 9796 if (!fops || !fops->async_action_query_update) 9797 return rte_flow_error_set(error, ENOTSUP, 9798 RTE_FLOW_ERROR_TYPE_ACTION, NULL, 9799 "async query_update not supported"); 9800 return fops->async_action_query_update 9801 (dev, queue_id, op_attr, action_handle, 9802 update, query, qu_mode, user_data, error); 9803 } 9804 9805 /** 9806 * Query shared action. 9807 * 9808 * @param[in] dev 9809 * Pointer to the rte_eth_dev structure. 9810 * @param[in] queue 9811 * Which queue to be used.. 9812 * @param[in] attr 9813 * Operation attribute. 9814 * @param[in] handle 9815 * Action handle to be updated. 9816 * @param[in] data 9817 * Pointer query result data. 9818 * @param[in] user_data 9819 * Pointer to the user_data. 9820 * @param[out] error 9821 * Pointer to error structure. 9822 * 9823 * @return 9824 * 0 on success, negative value otherwise and rte_errno is set. 9825 */ 9826 static int 9827 mlx5_flow_async_action_handle_query(struct rte_eth_dev *dev, uint32_t queue, 9828 const struct rte_flow_op_attr *attr, 9829 const struct rte_flow_action_handle *handle, 9830 void *data, 9831 void *user_data, 9832 struct rte_flow_error *error) 9833 { 9834 const struct mlx5_flow_driver_ops *fops = 9835 flow_get_drv_ops(MLX5_FLOW_TYPE_HW); 9836 9837 return fops->async_action_query(dev, queue, attr, handle, 9838 data, user_data, error); 9839 } 9840 9841 /** 9842 * Destroy shared action. 9843 * 9844 * @param[in] dev 9845 * Pointer to the rte_eth_dev structure. 9846 * @param[in] queue 9847 * Which queue to be used.. 9848 * @param[in] attr 9849 * Operation attribute. 9850 * @param[in] handle 9851 * Action handle to be destroyed. 9852 * @param[in] user_data 9853 * Pointer to the user_data. 9854 * @param[out] error 9855 * Pointer to error structure. 9856 * 9857 * @return 9858 * 0 on success, negative value otherwise and rte_errno is set. 9859 */ 9860 static int 9861 mlx5_flow_async_action_handle_destroy(struct rte_eth_dev *dev, uint32_t queue, 9862 const struct rte_flow_op_attr *attr, 9863 struct rte_flow_action_handle *handle, 9864 void *user_data, 9865 struct rte_flow_error *error) 9866 { 9867 const struct mlx5_flow_driver_ops *fops = 9868 flow_get_drv_ops(MLX5_FLOW_TYPE_HW); 9869 9870 return fops->async_action_destroy(dev, queue, attr, handle, 9871 user_data, error); 9872 } 9873 9874 /** 9875 * Allocate a new memory for the counter values wrapped by all the needed 9876 * management. 9877 * 9878 * @param[in] sh 9879 * Pointer to mlx5_dev_ctx_shared object. 9880 * 9881 * @return 9882 * 0 on success, a negative errno value otherwise. 9883 */ 9884 static int 9885 mlx5_flow_create_counter_stat_mem_mng(struct mlx5_dev_ctx_shared *sh) 9886 { 9887 struct mlx5_counter_stats_mem_mng *mem_mng; 9888 volatile struct flow_counter_stats *raw_data; 9889 int raws_n = MLX5_CNT_MR_ALLOC_BULK + MLX5_MAX_PENDING_QUERIES; 9890 int size = (sizeof(struct flow_counter_stats) * 9891 MLX5_COUNTERS_PER_POOL + 9892 sizeof(struct mlx5_counter_stats_raw)) * raws_n + 9893 sizeof(struct mlx5_counter_stats_mem_mng); 9894 size_t pgsize = rte_mem_page_size(); 9895 uint8_t *mem; 9896 int ret; 9897 int i; 9898 9899 if (pgsize == (size_t)-1) { 9900 DRV_LOG(ERR, "Failed to get mem page size"); 9901 rte_errno = ENOMEM; 9902 return -ENOMEM; 9903 } 9904 mem = mlx5_malloc(MLX5_MEM_ZERO, size, pgsize, SOCKET_ID_ANY); 9905 if (!mem) { 9906 rte_errno = ENOMEM; 9907 return -ENOMEM; 9908 } 9909 mem_mng = (struct mlx5_counter_stats_mem_mng *)(mem + size) - 1; 9910 size = sizeof(*raw_data) * MLX5_COUNTERS_PER_POOL * raws_n; 9911 ret = mlx5_os_wrapped_mkey_create(sh->cdev->ctx, sh->cdev->pd, 9912 sh->cdev->pdn, mem, size, 9913 &mem_mng->wm); 9914 if (ret) { 9915 rte_errno = errno; 9916 mlx5_free(mem); 9917 return -rte_errno; 9918 } 9919 mem_mng->raws = (struct mlx5_counter_stats_raw *)(mem + size); 9920 raw_data = (volatile struct flow_counter_stats *)mem; 9921 for (i = 0; i < raws_n; ++i) { 9922 mem_mng->raws[i].mem_mng = mem_mng; 9923 mem_mng->raws[i].data = raw_data + i * MLX5_COUNTERS_PER_POOL; 9924 } 9925 for (i = 0; i < MLX5_MAX_PENDING_QUERIES; ++i) 9926 LIST_INSERT_HEAD(&sh->sws_cmng.free_stat_raws, 9927 mem_mng->raws + MLX5_CNT_MR_ALLOC_BULK + i, 9928 next); 9929 LIST_INSERT_HEAD(&sh->sws_cmng.mem_mngs, mem_mng, next); 9930 sh->sws_cmng.mem_mng = mem_mng; 9931 return 0; 9932 } 9933 9934 /** 9935 * Set the statistic memory to the new counter pool. 9936 * 9937 * @param[in] sh 9938 * Pointer to mlx5_dev_ctx_shared object. 9939 * @param[in] pool 9940 * Pointer to the pool to set the statistic memory. 9941 * 9942 * @return 9943 * 0 on success, a negative errno value otherwise. 9944 */ 9945 static int 9946 mlx5_flow_set_counter_stat_mem(struct mlx5_dev_ctx_shared *sh, 9947 struct mlx5_flow_counter_pool *pool) 9948 { 9949 struct mlx5_flow_counter_mng *cmng = &sh->sws_cmng; 9950 /* Resize statistic memory once used out. */ 9951 if (!(pool->index % MLX5_CNT_MR_ALLOC_BULK) && 9952 mlx5_flow_create_counter_stat_mem_mng(sh)) { 9953 DRV_LOG(ERR, "Cannot resize counter stat mem."); 9954 return -1; 9955 } 9956 rte_spinlock_lock(&pool->sl); 9957 pool->raw = cmng->mem_mng->raws + pool->index % MLX5_CNT_MR_ALLOC_BULK; 9958 rte_spinlock_unlock(&pool->sl); 9959 pool->raw_hw = NULL; 9960 return 0; 9961 } 9962 9963 #define MLX5_POOL_QUERY_FREQ_US 1000000 9964 9965 /** 9966 * Set the periodic procedure for triggering asynchronous batch queries for all 9967 * the counter pools. 9968 * 9969 * @param[in] sh 9970 * Pointer to mlx5_dev_ctx_shared object. 9971 */ 9972 void 9973 mlx5_set_query_alarm(struct mlx5_dev_ctx_shared *sh) 9974 { 9975 uint32_t pools_n, us; 9976 9977 pools_n = __atomic_load_n(&sh->sws_cmng.n_valid, __ATOMIC_RELAXED); 9978 us = MLX5_POOL_QUERY_FREQ_US / pools_n; 9979 DRV_LOG(DEBUG, "Set alarm for %u pools each %u us", pools_n, us); 9980 if (rte_eal_alarm_set(us, mlx5_flow_query_alarm, sh)) { 9981 sh->sws_cmng.query_thread_on = 0; 9982 DRV_LOG(ERR, "Cannot reinitialize query alarm"); 9983 } else { 9984 sh->sws_cmng.query_thread_on = 1; 9985 } 9986 } 9987 9988 /** 9989 * The periodic procedure for triggering asynchronous batch queries for all the 9990 * counter pools. This function is probably called by the host thread. 9991 * 9992 * @param[in] arg 9993 * The parameter for the alarm process. 9994 */ 9995 void 9996 mlx5_flow_query_alarm(void *arg) 9997 { 9998 struct mlx5_dev_ctx_shared *sh = arg; 9999 struct mlx5_flow_counter_mng *cmng = &sh->sws_cmng; 10000 uint16_t pool_index = cmng->pool_index; 10001 struct mlx5_flow_counter_pool *pool; 10002 uint16_t n_valid; 10003 int ret; 10004 10005 if (cmng->pending_queries >= MLX5_MAX_PENDING_QUERIES) 10006 goto set_alarm; 10007 rte_spinlock_lock(&cmng->pool_update_sl); 10008 pool = cmng->pools[pool_index]; 10009 n_valid = cmng->n_valid; 10010 rte_spinlock_unlock(&cmng->pool_update_sl); 10011 /* Set the statistic memory to the new created pool. */ 10012 if ((!pool->raw && mlx5_flow_set_counter_stat_mem(sh, pool))) 10013 goto set_alarm; 10014 if (pool->raw_hw) 10015 /* There is a pool query in progress. */ 10016 goto set_alarm; 10017 pool->raw_hw = LIST_FIRST(&cmng->free_stat_raws); 10018 if (!pool->raw_hw) 10019 /* No free counter statistics raw memory. */ 10020 goto set_alarm; 10021 /* 10022 * Identify the counters released between query trigger and query 10023 * handle more efficiently. The counter released in this gap period 10024 * should wait for a new round of query as the new arrived packets 10025 * will not be taken into account. 10026 */ 10027 pool->query_gen++; 10028 ret = mlx5_devx_cmd_flow_counter_query(pool->min_dcs, 0, 10029 MLX5_COUNTERS_PER_POOL, 10030 NULL, NULL, 10031 pool->raw_hw->mem_mng->wm.lkey, 10032 (void *)(uintptr_t) 10033 pool->raw_hw->data, 10034 sh->devx_comp, 10035 (uint64_t)(uintptr_t)pool); 10036 if (ret) { 10037 DRV_LOG(ERR, "Failed to trigger asynchronous query for dcs ID" 10038 " %d", pool->min_dcs->id); 10039 pool->raw_hw = NULL; 10040 goto set_alarm; 10041 } 10042 LIST_REMOVE(pool->raw_hw, next); 10043 cmng->pending_queries++; 10044 pool_index++; 10045 if (pool_index >= n_valid) 10046 pool_index = 0; 10047 set_alarm: 10048 cmng->pool_index = pool_index; 10049 mlx5_set_query_alarm(sh); 10050 } 10051 10052 /** 10053 * Check and callback event for new aged flow in the counter pool 10054 * 10055 * @param[in] sh 10056 * Pointer to mlx5_dev_ctx_shared object. 10057 * @param[in] pool 10058 * Pointer to Current counter pool. 10059 */ 10060 static void 10061 mlx5_flow_aging_check(struct mlx5_dev_ctx_shared *sh, 10062 struct mlx5_flow_counter_pool *pool) 10063 { 10064 struct mlx5_priv *priv; 10065 struct mlx5_flow_counter *cnt; 10066 struct mlx5_age_info *age_info; 10067 struct mlx5_age_param *age_param; 10068 struct mlx5_counter_stats_raw *cur = pool->raw_hw; 10069 struct mlx5_counter_stats_raw *prev = pool->raw; 10070 const uint64_t curr_time = MLX5_CURR_TIME_SEC; 10071 const uint32_t time_delta = curr_time - pool->time_of_last_age_check; 10072 uint16_t expected = AGE_CANDIDATE; 10073 uint32_t i; 10074 10075 pool->time_of_last_age_check = curr_time; 10076 for (i = 0; i < MLX5_COUNTERS_PER_POOL; ++i) { 10077 cnt = MLX5_POOL_GET_CNT(pool, i); 10078 age_param = MLX5_CNT_TO_AGE(cnt); 10079 if (__atomic_load_n(&age_param->state, 10080 __ATOMIC_RELAXED) != AGE_CANDIDATE) 10081 continue; 10082 if (cur->data[i].hits != prev->data[i].hits) { 10083 __atomic_store_n(&age_param->sec_since_last_hit, 0, 10084 __ATOMIC_RELAXED); 10085 continue; 10086 } 10087 if (__atomic_fetch_add(&age_param->sec_since_last_hit, 10088 time_delta, 10089 __ATOMIC_RELAXED) + time_delta <= age_param->timeout) 10090 continue; 10091 /** 10092 * Hold the lock first, or if between the 10093 * state AGE_TMOUT and tailq operation the 10094 * release happened, the release procedure 10095 * may delete a non-existent tailq node. 10096 */ 10097 priv = rte_eth_devices[age_param->port_id].data->dev_private; 10098 age_info = GET_PORT_AGE_INFO(priv); 10099 rte_spinlock_lock(&age_info->aged_sl); 10100 if (__atomic_compare_exchange_n(&age_param->state, &expected, 10101 AGE_TMOUT, false, 10102 __ATOMIC_RELAXED, 10103 __ATOMIC_RELAXED)) { 10104 TAILQ_INSERT_TAIL(&age_info->aged_counters, cnt, next); 10105 MLX5_AGE_SET(age_info, MLX5_AGE_EVENT_NEW); 10106 } 10107 rte_spinlock_unlock(&age_info->aged_sl); 10108 } 10109 mlx5_age_event_prepare(sh); 10110 } 10111 10112 /** 10113 * Handler for the HW respond about ready values from an asynchronous batch 10114 * query. This function is probably called by the host thread. 10115 * 10116 * @param[in] sh 10117 * The pointer to the shared device context. 10118 * @param[in] async_id 10119 * The Devx async ID. 10120 * @param[in] status 10121 * The status of the completion. 10122 */ 10123 void 10124 mlx5_flow_async_pool_query_handle(struct mlx5_dev_ctx_shared *sh, 10125 uint64_t async_id, int status) 10126 { 10127 struct mlx5_flow_counter_pool *pool = 10128 (struct mlx5_flow_counter_pool *)(uintptr_t)async_id; 10129 struct mlx5_counter_stats_raw *raw_to_free; 10130 uint8_t query_gen = pool->query_gen ^ 1; 10131 struct mlx5_flow_counter_mng *cmng = &sh->sws_cmng; 10132 enum mlx5_counter_type cnt_type = 10133 pool->is_aged ? MLX5_COUNTER_TYPE_AGE : 10134 MLX5_COUNTER_TYPE_ORIGIN; 10135 10136 if (unlikely(status)) { 10137 raw_to_free = pool->raw_hw; 10138 } else { 10139 raw_to_free = pool->raw; 10140 if (pool->is_aged) 10141 mlx5_flow_aging_check(sh, pool); 10142 rte_spinlock_lock(&pool->sl); 10143 pool->raw = pool->raw_hw; 10144 rte_spinlock_unlock(&pool->sl); 10145 /* Be sure the new raw counters data is updated in memory. */ 10146 rte_io_wmb(); 10147 if (!TAILQ_EMPTY(&pool->counters[query_gen])) { 10148 rte_spinlock_lock(&cmng->csl[cnt_type]); 10149 TAILQ_CONCAT(&cmng->counters[cnt_type], 10150 &pool->counters[query_gen], next); 10151 rte_spinlock_unlock(&cmng->csl[cnt_type]); 10152 } 10153 } 10154 LIST_INSERT_HEAD(&sh->sws_cmng.free_stat_raws, raw_to_free, next); 10155 pool->raw_hw = NULL; 10156 sh->sws_cmng.pending_queries--; 10157 } 10158 10159 static int 10160 flow_group_to_table(uint32_t port_id, uint32_t group, uint32_t *table, 10161 const struct flow_grp_info *grp_info, 10162 struct rte_flow_error *error) 10163 { 10164 if (grp_info->transfer && grp_info->external && 10165 grp_info->fdb_def_rule) { 10166 if (group == UINT32_MAX) 10167 return rte_flow_error_set 10168 (error, EINVAL, 10169 RTE_FLOW_ERROR_TYPE_ATTR_GROUP, 10170 NULL, 10171 "group index not supported"); 10172 *table = group + 1; 10173 } else { 10174 *table = group; 10175 } 10176 DRV_LOG(DEBUG, "port %u group=%#x table=%#x", port_id, group, *table); 10177 return 0; 10178 } 10179 10180 /** 10181 * Translate the rte_flow group index to HW table value. 10182 * 10183 * If tunnel offload is disabled, all group ids converted to flow table 10184 * id using the standard method. 10185 * If tunnel offload is enabled, group id can be converted using the 10186 * standard or tunnel conversion method. Group conversion method 10187 * selection depends on flags in `grp_info` parameter: 10188 * - Internal (grp_info.external == 0) groups conversion uses the 10189 * standard method. 10190 * - Group ids in JUMP action converted with the tunnel conversion. 10191 * - Group id in rule attribute conversion depends on a rule type and 10192 * group id value: 10193 * ** non zero group attributes converted with the tunnel method 10194 * ** zero group attribute in non-tunnel rule is converted using the 10195 * standard method - there's only one root table 10196 * ** zero group attribute in steer tunnel rule is converted with the 10197 * standard method - single root table 10198 * ** zero group attribute in match tunnel rule is a special OvS 10199 * case: that value is used for portability reasons. That group 10200 * id is converted with the tunnel conversion method. 10201 * 10202 * @param[in] dev 10203 * Port device 10204 * @param[in] tunnel 10205 * PMD tunnel offload object 10206 * @param[in] group 10207 * rte_flow group index value. 10208 * @param[out] table 10209 * HW table value. 10210 * @param[in] grp_info 10211 * flags used for conversion 10212 * @param[out] error 10213 * Pointer to error structure. 10214 * 10215 * @return 10216 * 0 on success, a negative errno value otherwise and rte_errno is set. 10217 */ 10218 int 10219 mlx5_flow_group_to_table(struct rte_eth_dev *dev, 10220 const struct mlx5_flow_tunnel *tunnel, 10221 uint32_t group, uint32_t *table, 10222 const struct flow_grp_info *grp_info, 10223 struct rte_flow_error *error) 10224 { 10225 int ret; 10226 bool standard_translation; 10227 10228 if (!grp_info->skip_scale && grp_info->external && 10229 group < MLX5_MAX_TABLES_EXTERNAL) 10230 group *= MLX5_FLOW_TABLE_FACTOR; 10231 if (is_tunnel_offload_active(dev)) { 10232 standard_translation = !grp_info->external || 10233 grp_info->std_tbl_fix; 10234 } else { 10235 standard_translation = true; 10236 } 10237 DRV_LOG(DEBUG, 10238 "port %u group=%u transfer=%d external=%d fdb_def_rule=%d translate=%s", 10239 dev->data->port_id, group, grp_info->transfer, 10240 grp_info->external, grp_info->fdb_def_rule, 10241 standard_translation ? "STANDARD" : "TUNNEL"); 10242 if (standard_translation) 10243 ret = flow_group_to_table(dev->data->port_id, group, table, 10244 grp_info, error); 10245 else 10246 ret = tunnel_flow_group_to_flow_table(dev, tunnel, group, 10247 table, error); 10248 10249 return ret; 10250 } 10251 10252 /** 10253 * Discover availability of metadata reg_c's. 10254 * 10255 * Iteratively use test flows to check availability. 10256 * 10257 * @param[in] dev 10258 * Pointer to the Ethernet device structure. 10259 * 10260 * @return 10261 * 0 on success, a negative errno value otherwise and rte_errno is set. 10262 */ 10263 int 10264 mlx5_flow_discover_mreg_c(struct rte_eth_dev *dev) 10265 { 10266 struct mlx5_priv *priv = dev->data->dev_private; 10267 enum modify_reg idx; 10268 int n = 0; 10269 10270 /* reg_c[0] and reg_c[1] are reserved. */ 10271 priv->sh->flow_mreg_c[n++] = REG_C_0; 10272 priv->sh->flow_mreg_c[n++] = REG_C_1; 10273 /* Discover availability of other reg_c's. */ 10274 for (idx = REG_C_2; idx <= REG_C_7; ++idx) { 10275 struct rte_flow_attr attr = { 10276 .group = MLX5_FLOW_MREG_CP_TABLE_GROUP, 10277 .priority = MLX5_FLOW_LOWEST_PRIO_INDICATOR, 10278 .ingress = 1, 10279 }; 10280 struct rte_flow_item items[] = { 10281 [0] = { 10282 .type = RTE_FLOW_ITEM_TYPE_END, 10283 }, 10284 }; 10285 struct rte_flow_action actions[] = { 10286 [0] = { 10287 .type = (enum rte_flow_action_type) 10288 MLX5_RTE_FLOW_ACTION_TYPE_COPY_MREG, 10289 .conf = &(struct mlx5_flow_action_copy_mreg){ 10290 .src = REG_C_1, 10291 .dst = idx, 10292 }, 10293 }, 10294 [1] = { 10295 .type = RTE_FLOW_ACTION_TYPE_JUMP, 10296 .conf = &(struct rte_flow_action_jump){ 10297 .group = MLX5_FLOW_MREG_ACT_TABLE_GROUP, 10298 }, 10299 }, 10300 [2] = { 10301 .type = RTE_FLOW_ACTION_TYPE_END, 10302 }, 10303 }; 10304 uint32_t flow_idx; 10305 struct rte_flow *flow; 10306 struct rte_flow_error error; 10307 10308 if (!priv->sh->config.dv_flow_en) 10309 break; 10310 /* Create internal flow, validation skips copy action. */ 10311 flow_idx = flow_list_create(dev, MLX5_FLOW_TYPE_GEN, &attr, 10312 items, actions, false, &error); 10313 flow = mlx5_ipool_get(priv->flows[MLX5_FLOW_TYPE_GEN], 10314 flow_idx); 10315 if (!flow) 10316 continue; 10317 priv->sh->flow_mreg_c[n++] = idx; 10318 flow_list_destroy(dev, MLX5_FLOW_TYPE_GEN, flow_idx); 10319 } 10320 for (; n < MLX5_MREG_C_NUM; ++n) 10321 priv->sh->flow_mreg_c[n] = REG_NON; 10322 priv->sh->metadata_regc_check_flag = 1; 10323 return 0; 10324 } 10325 10326 int 10327 save_dump_file(const uint8_t *data, uint32_t size, 10328 uint32_t type, uint64_t id, void *arg, FILE *file) 10329 { 10330 char line[BUF_SIZE]; 10331 uint32_t out = 0; 10332 uint32_t k; 10333 uint32_t actions_num; 10334 struct rte_flow_query_count *count; 10335 10336 memset(line, 0, BUF_SIZE); 10337 switch (type) { 10338 case DR_DUMP_REC_TYPE_PMD_MODIFY_HDR: 10339 actions_num = *(uint32_t *)(arg); 10340 out += snprintf(line + out, BUF_SIZE - out, "%d,0x%" PRIx64 ",%d,", 10341 type, id, actions_num); 10342 break; 10343 case DR_DUMP_REC_TYPE_PMD_PKT_REFORMAT: 10344 out += snprintf(line + out, BUF_SIZE - out, "%d,0x%" PRIx64 ",", 10345 type, id); 10346 break; 10347 case DR_DUMP_REC_TYPE_PMD_COUNTER: 10348 count = (struct rte_flow_query_count *)arg; 10349 fprintf(file, 10350 "%d,0x%" PRIx64 ",%" PRIu64 ",%" PRIu64 "\n", 10351 type, id, count->hits, count->bytes); 10352 return 0; 10353 default: 10354 return -1; 10355 } 10356 10357 for (k = 0; k < size; k++) { 10358 /* Make sure we do not overrun the line buffer length. */ 10359 if (out >= BUF_SIZE - 4) { 10360 line[out] = '\0'; 10361 break; 10362 } 10363 out += snprintf(line + out, BUF_SIZE - out, "%02x", 10364 (data[k]) & 0xff); 10365 } 10366 fprintf(file, "%s\n", line); 10367 return 0; 10368 } 10369 10370 int 10371 mlx5_flow_query_counter(struct rte_eth_dev *dev, struct rte_flow *flow, 10372 struct rte_flow_query_count *count, struct rte_flow_error *error) 10373 { 10374 struct rte_flow_action action[2]; 10375 enum mlx5_flow_drv_type ftype; 10376 const struct mlx5_flow_driver_ops *fops; 10377 10378 if (!flow) { 10379 return rte_flow_error_set(error, ENOENT, 10380 RTE_FLOW_ERROR_TYPE_UNSPECIFIED, 10381 NULL, 10382 "invalid flow handle"); 10383 } 10384 action[0].type = RTE_FLOW_ACTION_TYPE_COUNT; 10385 action[1].type = RTE_FLOW_ACTION_TYPE_END; 10386 if (flow->counter) { 10387 memset(count, 0, sizeof(struct rte_flow_query_count)); 10388 ftype = (enum mlx5_flow_drv_type)(flow->drv_type); 10389 MLX5_ASSERT(ftype > MLX5_FLOW_TYPE_MIN && 10390 ftype < MLX5_FLOW_TYPE_MAX); 10391 fops = flow_get_drv_ops(ftype); 10392 return fops->query(dev, flow, action, count, error); 10393 } 10394 return -1; 10395 } 10396 10397 #ifdef HAVE_IBV_FLOW_DV_SUPPORT 10398 /** 10399 * Dump flow ipool data to file 10400 * 10401 * @param[in] dev 10402 * The pointer to Ethernet device. 10403 * @param[in] file 10404 * A pointer to a file for output. 10405 * @param[out] error 10406 * Perform verbose error reporting if not NULL. PMDs initialize this 10407 * structure in case of error only. 10408 * @return 10409 * 0 on success, a negative value otherwise. 10410 */ 10411 int 10412 mlx5_flow_dev_dump_ipool(struct rte_eth_dev *dev, 10413 struct rte_flow *flow, FILE *file, 10414 struct rte_flow_error *error) 10415 { 10416 struct mlx5_priv *priv = dev->data->dev_private; 10417 struct mlx5_flow_dv_modify_hdr_resource *modify_hdr; 10418 struct mlx5_flow_dv_encap_decap_resource *encap_decap; 10419 uint32_t handle_idx; 10420 struct mlx5_flow_handle *dh; 10421 struct rte_flow_query_count count; 10422 uint32_t actions_num; 10423 const uint8_t *data; 10424 size_t size; 10425 uint64_t id; 10426 uint32_t type; 10427 void *action = NULL; 10428 10429 if (!flow) { 10430 return rte_flow_error_set(error, ENOENT, 10431 RTE_FLOW_ERROR_TYPE_UNSPECIFIED, 10432 NULL, 10433 "invalid flow handle"); 10434 } 10435 handle_idx = flow->dev_handles; 10436 /* query counter */ 10437 if (flow->counter && 10438 (!mlx5_counter_query(dev, flow->counter, false, 10439 &count.hits, &count.bytes, &action)) && action) { 10440 id = (uint64_t)(uintptr_t)action; 10441 type = DR_DUMP_REC_TYPE_PMD_COUNTER; 10442 save_dump_file(NULL, 0, type, 10443 id, (void *)&count, file); 10444 } 10445 10446 while (handle_idx) { 10447 dh = mlx5_ipool_get(priv->sh->ipool 10448 [MLX5_IPOOL_MLX5_FLOW], handle_idx); 10449 if (!dh) 10450 continue; 10451 handle_idx = dh->next.next; 10452 10453 /* Get modify_hdr and encap_decap buf from ipools. */ 10454 encap_decap = NULL; 10455 modify_hdr = dh->dvh.modify_hdr; 10456 10457 if (dh->dvh.rix_encap_decap) { 10458 encap_decap = mlx5_ipool_get(priv->sh->ipool 10459 [MLX5_IPOOL_DECAP_ENCAP], 10460 dh->dvh.rix_encap_decap); 10461 } 10462 if (modify_hdr) { 10463 data = (const uint8_t *)modify_hdr->actions; 10464 size = (size_t)(modify_hdr->actions_num) * 8; 10465 id = (uint64_t)(uintptr_t)modify_hdr->action; 10466 actions_num = modify_hdr->actions_num; 10467 type = DR_DUMP_REC_TYPE_PMD_MODIFY_HDR; 10468 save_dump_file(data, size, type, id, 10469 (void *)(&actions_num), file); 10470 } 10471 if (encap_decap) { 10472 data = encap_decap->buf; 10473 size = encap_decap->size; 10474 id = (uint64_t)(uintptr_t)encap_decap->action; 10475 type = DR_DUMP_REC_TYPE_PMD_PKT_REFORMAT; 10476 save_dump_file(data, size, type, 10477 id, NULL, file); 10478 } 10479 } 10480 return 0; 10481 } 10482 10483 /** 10484 * Dump all flow's encap_decap/modify_hdr/counter data to file 10485 * 10486 * @param[in] dev 10487 * The pointer to Ethernet device. 10488 * @param[in] file 10489 * A pointer to a file for output. 10490 * @param[out] error 10491 * Perform verbose error reporting if not NULL. PMDs initialize this 10492 * structure in case of error only. 10493 * @return 10494 * 0 on success, a negative value otherwise. 10495 */ 10496 static int 10497 mlx5_flow_dev_dump_sh_all(struct rte_eth_dev *dev, 10498 FILE *file, struct rte_flow_error *error __rte_unused) 10499 { 10500 struct mlx5_priv *priv = dev->data->dev_private; 10501 struct mlx5_dev_ctx_shared *sh = priv->sh; 10502 struct mlx5_hlist *h; 10503 struct mlx5_flow_dv_modify_hdr_resource *modify_hdr; 10504 struct mlx5_flow_dv_encap_decap_resource *encap_decap; 10505 struct rte_flow_query_count count; 10506 uint32_t actions_num; 10507 const uint8_t *data; 10508 size_t size; 10509 uint64_t id; 10510 uint32_t type; 10511 uint32_t i; 10512 uint32_t j; 10513 struct mlx5_list_inconst *l_inconst; 10514 struct mlx5_list_entry *e; 10515 int lcore_index; 10516 struct mlx5_flow_counter_mng *cmng = &priv->sh->sws_cmng; 10517 uint32_t max; 10518 void *action; 10519 10520 /* encap_decap hlist is lcore_share, get global core cache. */ 10521 i = MLX5_LIST_GLOBAL; 10522 h = sh->encaps_decaps; 10523 if (h) { 10524 for (j = 0; j <= h->mask; j++) { 10525 l_inconst = &h->buckets[j].l; 10526 if (!l_inconst || !l_inconst->cache[i]) 10527 continue; 10528 10529 e = LIST_FIRST(&l_inconst->cache[i]->h); 10530 while (e) { 10531 encap_decap = 10532 (struct mlx5_flow_dv_encap_decap_resource *)e; 10533 data = encap_decap->buf; 10534 size = encap_decap->size; 10535 id = (uint64_t)(uintptr_t)encap_decap->action; 10536 type = DR_DUMP_REC_TYPE_PMD_PKT_REFORMAT; 10537 save_dump_file(data, size, type, 10538 id, NULL, file); 10539 e = LIST_NEXT(e, next); 10540 } 10541 } 10542 } 10543 10544 /* get modify_hdr */ 10545 h = sh->modify_cmds; 10546 if (h) { 10547 lcore_index = rte_lcore_index(rte_lcore_id()); 10548 if (unlikely(lcore_index == -1)) { 10549 lcore_index = MLX5_LIST_NLCORE; 10550 rte_spinlock_lock(&h->l_const.lcore_lock); 10551 } 10552 i = lcore_index; 10553 10554 if (lcore_index == MLX5_LIST_NLCORE) { 10555 for (i = 0; i <= (uint32_t)lcore_index; i++) { 10556 for (j = 0; j <= h->mask; j++) { 10557 l_inconst = &h->buckets[j].l; 10558 if (!l_inconst || !l_inconst->cache[i]) 10559 continue; 10560 10561 e = LIST_FIRST(&l_inconst->cache[i]->h); 10562 while (e) { 10563 modify_hdr = 10564 (struct mlx5_flow_dv_modify_hdr_resource *)e; 10565 data = (const uint8_t *)modify_hdr->actions; 10566 size = (size_t)(modify_hdr->actions_num) * 8; 10567 actions_num = modify_hdr->actions_num; 10568 id = (uint64_t)(uintptr_t)modify_hdr->action; 10569 type = DR_DUMP_REC_TYPE_PMD_MODIFY_HDR; 10570 save_dump_file(data, size, type, id, 10571 (void *)(&actions_num), file); 10572 e = LIST_NEXT(e, next); 10573 } 10574 } 10575 } 10576 } else { 10577 for (j = 0; j <= h->mask; j++) { 10578 l_inconst = &h->buckets[j].l; 10579 if (!l_inconst || !l_inconst->cache[i]) 10580 continue; 10581 10582 e = LIST_FIRST(&l_inconst->cache[i]->h); 10583 while (e) { 10584 modify_hdr = 10585 (struct mlx5_flow_dv_modify_hdr_resource *)e; 10586 data = (const uint8_t *)modify_hdr->actions; 10587 size = (size_t)(modify_hdr->actions_num) * 8; 10588 actions_num = modify_hdr->actions_num; 10589 id = (uint64_t)(uintptr_t)modify_hdr->action; 10590 type = DR_DUMP_REC_TYPE_PMD_MODIFY_HDR; 10591 save_dump_file(data, size, type, id, 10592 (void *)(&actions_num), file); 10593 e = LIST_NEXT(e, next); 10594 } 10595 } 10596 } 10597 10598 if (unlikely(lcore_index == MLX5_LIST_NLCORE)) 10599 rte_spinlock_unlock(&h->l_const.lcore_lock); 10600 } 10601 10602 /* get counter */ 10603 MLX5_ASSERT(cmng->n_valid <= MLX5_COUNTER_POOLS_MAX_NUM); 10604 max = MLX5_COUNTERS_PER_POOL * cmng->n_valid; 10605 for (j = 1; j <= max; j++) { 10606 action = NULL; 10607 if ((!mlx5_counter_query(dev, j, false, &count.hits, 10608 &count.bytes, &action)) && action) { 10609 id = (uint64_t)(uintptr_t)action; 10610 type = DR_DUMP_REC_TYPE_PMD_COUNTER; 10611 save_dump_file(NULL, 0, type, 10612 id, (void *)&count, file); 10613 } 10614 } 10615 return 0; 10616 } 10617 #endif 10618 10619 /** 10620 * Dump flow raw hw data to file 10621 * 10622 * @param[in] dev 10623 * The pointer to Ethernet device. 10624 * @param[in] file 10625 * A pointer to a file for output. 10626 * @param[out] error 10627 * Perform verbose error reporting if not NULL. PMDs initialize this 10628 * structure in case of error only. 10629 * @return 10630 * 0 on success, a negative value otherwise. 10631 */ 10632 int 10633 mlx5_flow_dev_dump(struct rte_eth_dev *dev, struct rte_flow *flow_idx, 10634 FILE *file, 10635 struct rte_flow_error *error __rte_unused) 10636 { 10637 struct mlx5_priv *priv = dev->data->dev_private; 10638 struct mlx5_dev_ctx_shared *sh = priv->sh; 10639 uint32_t handle_idx; 10640 int ret; 10641 struct mlx5_flow_handle *dh; 10642 struct rte_flow *flow; 10643 10644 if (!sh->config.dv_flow_en) { 10645 if (fputs("device dv flow disabled\n", file) <= 0) 10646 return -errno; 10647 return -ENOTSUP; 10648 } 10649 10650 /* dump all */ 10651 if (!flow_idx) { 10652 #ifdef HAVE_IBV_FLOW_DV_SUPPORT 10653 if (mlx5_flow_dev_dump_sh_all(dev, file, error)) 10654 return -EINVAL; 10655 10656 if (sh->config.dv_flow_en == 2) 10657 return mlx5dr_debug_dump(priv->dr_ctx, file); 10658 #endif 10659 return mlx5_devx_cmd_flow_dump(sh->fdb_domain, 10660 sh->rx_domain, 10661 sh->tx_domain, file); 10662 } 10663 /* dump one */ 10664 flow = mlx5_ipool_get(priv->flows[MLX5_FLOW_TYPE_GEN], 10665 (uintptr_t)(void *)flow_idx); 10666 if (!flow) 10667 return -EINVAL; 10668 10669 #ifdef HAVE_IBV_FLOW_DV_SUPPORT 10670 mlx5_flow_dev_dump_ipool(dev, flow, file, error); 10671 #endif 10672 handle_idx = flow->dev_handles; 10673 while (handle_idx) { 10674 dh = mlx5_ipool_get(priv->sh->ipool[MLX5_IPOOL_MLX5_FLOW], 10675 handle_idx); 10676 if (!dh) 10677 return -ENOENT; 10678 if (dh->drv_flow) { 10679 if (sh->config.dv_flow_en == 2) 10680 return -ENOTSUP; 10681 10682 ret = mlx5_devx_cmd_flow_single_dump(dh->drv_flow, 10683 file); 10684 if (ret) 10685 return -ENOENT; 10686 } 10687 handle_idx = dh->next.next; 10688 } 10689 return 0; 10690 } 10691 10692 /** 10693 * Get aged-out flows. 10694 * 10695 * @param[in] dev 10696 * Pointer to the Ethernet device structure. 10697 * @param[in] context 10698 * The address of an array of pointers to the aged-out flows contexts. 10699 * @param[in] nb_countexts 10700 * The length of context array pointers. 10701 * @param[out] error 10702 * Perform verbose error reporting if not NULL. Initialized in case of 10703 * error only. 10704 * 10705 * @return 10706 * how many contexts get in success, otherwise negative errno value. 10707 * if nb_contexts is 0, return the amount of all aged contexts. 10708 * if nb_contexts is not 0 , return the amount of aged flows reported 10709 * in the context array. 10710 */ 10711 int 10712 mlx5_flow_get_aged_flows(struct rte_eth_dev *dev, void **contexts, 10713 uint32_t nb_contexts, struct rte_flow_error *error) 10714 { 10715 struct rte_flow_attr attr = { .transfer = 0 }; 10716 10717 return flow_get_drv_ops(flow_get_drv_type(dev, &attr))->get_aged_flows 10718 (dev, contexts, nb_contexts, error); 10719 } 10720 10721 /** 10722 * Get aged-out flows per HWS queue. 10723 * 10724 * @param[in] dev 10725 * Pointer to the Ethernet device structure. 10726 * @param[in] queue_id 10727 * Flow queue to query. 10728 * @param[in] context 10729 * The address of an array of pointers to the aged-out flows contexts. 10730 * @param[in] nb_countexts 10731 * The length of context array pointers. 10732 * @param[out] error 10733 * Perform verbose error reporting if not NULL. Initialized in case of 10734 * error only. 10735 * 10736 * @return 10737 * how many contexts get in success, otherwise negative errno value. 10738 * if nb_contexts is 0, return the amount of all aged contexts. 10739 * if nb_contexts is not 0 , return the amount of aged flows reported 10740 * in the context array. 10741 */ 10742 int 10743 mlx5_flow_get_q_aged_flows(struct rte_eth_dev *dev, uint32_t queue_id, 10744 void **contexts, uint32_t nb_contexts, 10745 struct rte_flow_error *error) 10746 { 10747 const struct mlx5_flow_driver_ops *fops; 10748 struct rte_flow_attr attr = { 0 }; 10749 10750 if (flow_get_drv_type(dev, &attr) == MLX5_FLOW_TYPE_HW) { 10751 fops = flow_get_drv_ops(MLX5_FLOW_TYPE_HW); 10752 return fops->get_q_aged_flows(dev, queue_id, contexts, 10753 nb_contexts, error); 10754 } 10755 DRV_LOG(ERR, "port %u queue %u get aged flows is not supported.", 10756 dev->data->port_id, queue_id); 10757 return rte_flow_error_set(error, ENOTSUP, 10758 RTE_FLOW_ERROR_TYPE_UNSPECIFIED, NULL, 10759 "get Q aged flows with incorrect steering mode"); 10760 } 10761 10762 /* Wrapper for driver action_validate op callback */ 10763 static int 10764 flow_drv_action_validate(struct rte_eth_dev *dev, 10765 const struct rte_flow_indir_action_conf *conf, 10766 const struct rte_flow_action *action, 10767 const struct mlx5_flow_driver_ops *fops, 10768 struct rte_flow_error *error) 10769 { 10770 static const char err_msg[] = "indirect action validation unsupported"; 10771 10772 if (!fops->action_validate) { 10773 DRV_LOG(ERR, "port %u %s.", dev->data->port_id, err_msg); 10774 rte_flow_error_set(error, ENOTSUP, RTE_FLOW_ERROR_TYPE_ACTION, 10775 NULL, err_msg); 10776 return -rte_errno; 10777 } 10778 return fops->action_validate(dev, conf, action, error); 10779 } 10780 10781 /** 10782 * Destroys the shared action by handle. 10783 * 10784 * @param dev 10785 * Pointer to Ethernet device structure. 10786 * @param[in] handle 10787 * Handle for the indirect action object to be destroyed. 10788 * @param[out] error 10789 * Perform verbose error reporting if not NULL. PMDs initialize this 10790 * structure in case of error only. 10791 * 10792 * @return 10793 * 0 on success, a negative errno value otherwise and rte_errno is set. 10794 * 10795 * @note: wrapper for driver action_create op callback. 10796 */ 10797 static int 10798 mlx5_action_handle_destroy(struct rte_eth_dev *dev, 10799 struct rte_flow_action_handle *handle, 10800 struct rte_flow_error *error) 10801 { 10802 static const char err_msg[] = "indirect action destruction unsupported"; 10803 struct rte_flow_attr attr = { .transfer = 0 }; 10804 const struct mlx5_flow_driver_ops *fops = 10805 flow_get_drv_ops(flow_get_drv_type(dev, &attr)); 10806 10807 if (!fops->action_destroy) { 10808 DRV_LOG(ERR, "port %u %s.", dev->data->port_id, err_msg); 10809 rte_flow_error_set(error, ENOTSUP, RTE_FLOW_ERROR_TYPE_ACTION, 10810 NULL, err_msg); 10811 return -rte_errno; 10812 } 10813 return fops->action_destroy(dev, handle, error); 10814 } 10815 10816 /* Wrapper for driver action_destroy op callback */ 10817 static int 10818 flow_drv_action_update(struct rte_eth_dev *dev, 10819 struct rte_flow_action_handle *handle, 10820 const void *update, 10821 const struct mlx5_flow_driver_ops *fops, 10822 struct rte_flow_error *error) 10823 { 10824 static const char err_msg[] = "indirect action update unsupported"; 10825 10826 if (!fops->action_update) { 10827 DRV_LOG(ERR, "port %u %s.", dev->data->port_id, err_msg); 10828 rte_flow_error_set(error, ENOTSUP, RTE_FLOW_ERROR_TYPE_ACTION, 10829 NULL, err_msg); 10830 return -rte_errno; 10831 } 10832 return fops->action_update(dev, handle, update, error); 10833 } 10834 10835 /* Wrapper for driver action_destroy op callback */ 10836 static int 10837 flow_drv_action_query(struct rte_eth_dev *dev, 10838 const struct rte_flow_action_handle *handle, 10839 void *data, 10840 const struct mlx5_flow_driver_ops *fops, 10841 struct rte_flow_error *error) 10842 { 10843 static const char err_msg[] = "indirect action query unsupported"; 10844 10845 if (!fops->action_query) { 10846 DRV_LOG(ERR, "port %u %s.", dev->data->port_id, err_msg); 10847 rte_flow_error_set(error, ENOTSUP, RTE_FLOW_ERROR_TYPE_ACTION, 10848 NULL, err_msg); 10849 return -rte_errno; 10850 } 10851 return fops->action_query(dev, handle, data, error); 10852 } 10853 10854 /** 10855 * Create indirect action for reuse in multiple flow rules. 10856 * 10857 * @param dev 10858 * Pointer to Ethernet device structure. 10859 * @param conf 10860 * Pointer to indirect action object configuration. 10861 * @param[in] action 10862 * Action configuration for indirect action object creation. 10863 * @param[out] error 10864 * Perform verbose error reporting if not NULL. PMDs initialize this 10865 * structure in case of error only. 10866 * @return 10867 * A valid handle in case of success, NULL otherwise and rte_errno is set. 10868 */ 10869 static struct rte_flow_action_handle * 10870 mlx5_action_handle_create(struct rte_eth_dev *dev, 10871 const struct rte_flow_indir_action_conf *conf, 10872 const struct rte_flow_action *action, 10873 struct rte_flow_error *error) 10874 { 10875 static const char err_msg[] = "indirect action creation unsupported"; 10876 struct rte_flow_attr attr = { .transfer = 0 }; 10877 const struct mlx5_flow_driver_ops *fops = 10878 flow_get_drv_ops(flow_get_drv_type(dev, &attr)); 10879 10880 if (flow_drv_action_validate(dev, conf, action, fops, error)) 10881 return NULL; 10882 if (!fops->action_create) { 10883 DRV_LOG(ERR, "port %u %s.", dev->data->port_id, err_msg); 10884 rte_flow_error_set(error, ENOTSUP, RTE_FLOW_ERROR_TYPE_ACTION, 10885 NULL, err_msg); 10886 return NULL; 10887 } 10888 return fops->action_create(dev, conf, action, error); 10889 } 10890 10891 /** 10892 * Updates inplace the indirect action configuration pointed by *handle* 10893 * with the configuration provided as *update* argument. 10894 * The update of the indirect action configuration effects all flow rules 10895 * reusing the action via handle. 10896 * 10897 * @param dev 10898 * Pointer to Ethernet device structure. 10899 * @param[in] handle 10900 * Handle for the indirect action to be updated. 10901 * @param[in] update 10902 * Action specification used to modify the action pointed by handle. 10903 * *update* could be of same type with the action pointed by the *handle* 10904 * handle argument, or some other structures like a wrapper, depending on 10905 * the indirect action type. 10906 * @param[out] error 10907 * Perform verbose error reporting if not NULL. PMDs initialize this 10908 * structure in case of error only. 10909 * 10910 * @return 10911 * 0 on success, a negative errno value otherwise and rte_errno is set. 10912 */ 10913 static int 10914 mlx5_action_handle_update(struct rte_eth_dev *dev, 10915 struct rte_flow_action_handle *handle, 10916 const void *update, 10917 struct rte_flow_error *error) 10918 { 10919 struct rte_flow_attr attr = { .transfer = 0 }; 10920 const struct mlx5_flow_driver_ops *fops = 10921 flow_get_drv_ops(flow_get_drv_type(dev, &attr)); 10922 int ret; 10923 uint32_t act_idx = (uint32_t)(uintptr_t)handle; 10924 uint32_t type = act_idx >> MLX5_INDIRECT_ACTION_TYPE_OFFSET; 10925 10926 switch (type) { 10927 case MLX5_INDIRECT_ACTION_TYPE_CT: 10928 case MLX5_INDIRECT_ACTION_TYPE_METER_MARK: 10929 ret = 0; 10930 break; 10931 default: 10932 ret = flow_drv_action_validate(dev, NULL, 10933 (const struct rte_flow_action *)update, 10934 fops, error); 10935 } 10936 if (ret) 10937 return ret; 10938 return flow_drv_action_update(dev, handle, update, fops, 10939 error); 10940 } 10941 10942 /** 10943 * Query the indirect action by handle. 10944 * 10945 * This function allows retrieving action-specific data such as counters. 10946 * Data is gathered by special action which may be present/referenced in 10947 * more than one flow rule definition. 10948 * 10949 * see @RTE_FLOW_ACTION_TYPE_COUNT 10950 * 10951 * @param dev 10952 * Pointer to Ethernet device structure. 10953 * @param[in] handle 10954 * Handle for the indirect action to query. 10955 * @param[in, out] data 10956 * Pointer to storage for the associated query data type. 10957 * @param[out] error 10958 * Perform verbose error reporting if not NULL. PMDs initialize this 10959 * structure in case of error only. 10960 * 10961 * @return 10962 * 0 on success, a negative errno value otherwise and rte_errno is set. 10963 */ 10964 static int 10965 mlx5_action_handle_query(struct rte_eth_dev *dev, 10966 const struct rte_flow_action_handle *handle, 10967 void *data, 10968 struct rte_flow_error *error) 10969 { 10970 struct rte_flow_attr attr = { .transfer = 0 }; 10971 const struct mlx5_flow_driver_ops *fops = 10972 flow_get_drv_ops(flow_get_drv_type(dev, &attr)); 10973 10974 return flow_drv_action_query(dev, handle, data, fops, error); 10975 } 10976 10977 static int 10978 mlx5_action_handle_query_update(struct rte_eth_dev *dev, 10979 struct rte_flow_action_handle *handle, 10980 const void *update, void *query, 10981 enum rte_flow_query_update_mode qu_mode, 10982 struct rte_flow_error *error) 10983 { 10984 struct rte_flow_attr attr = { .transfer = 0 }; 10985 enum mlx5_flow_drv_type drv_type = flow_get_drv_type(dev, &attr); 10986 const struct mlx5_flow_driver_ops *fops; 10987 10988 if (drv_type == MLX5_FLOW_TYPE_MIN || drv_type == MLX5_FLOW_TYPE_MAX) 10989 return rte_flow_error_set(error, ENOTSUP, 10990 RTE_FLOW_ERROR_TYPE_ACTION, 10991 NULL, "invalid driver type"); 10992 fops = flow_get_drv_ops(drv_type); 10993 if (!fops || !fops->action_query_update) 10994 return rte_flow_error_set(error, ENOTSUP, 10995 RTE_FLOW_ERROR_TYPE_ACTION, 10996 NULL, "no query_update handler"); 10997 return fops->action_query_update(dev, handle, update, 10998 query, qu_mode, error); 10999 } 11000 11001 11002 #define MLX5_DRV_FOPS_OR_ERR(dev, fops, drv_cb, ret) \ 11003 { \ 11004 struct rte_flow_attr attr = { .transfer = 0 }; \ 11005 enum mlx5_flow_drv_type drv_type = flow_get_drv_type((dev), &attr); \ 11006 if (drv_type == MLX5_FLOW_TYPE_MIN || \ 11007 drv_type == MLX5_FLOW_TYPE_MAX) { \ 11008 rte_flow_error_set(error, ENOTSUP, \ 11009 RTE_FLOW_ERROR_TYPE_ACTION, \ 11010 NULL, "invalid driver type"); \ 11011 return ret; \ 11012 } \ 11013 (fops) = flow_get_drv_ops(drv_type); \ 11014 if (!(fops) || !(fops)->drv_cb) { \ 11015 rte_flow_error_set(error, ENOTSUP, RTE_FLOW_ERROR_TYPE_ACTION, \ 11016 NULL, "no action_list handler"); \ 11017 return ret; \ 11018 } \ 11019 } 11020 11021 static struct rte_flow_action_list_handle * 11022 mlx5_action_list_handle_create(struct rte_eth_dev *dev, 11023 const struct rte_flow_indir_action_conf *conf, 11024 const struct rte_flow_action *actions, 11025 struct rte_flow_error *error) 11026 { 11027 const struct mlx5_flow_driver_ops *fops; 11028 11029 MLX5_DRV_FOPS_OR_ERR(dev, fops, action_list_handle_create, NULL); 11030 return fops->action_list_handle_create(dev, conf, actions, error); 11031 } 11032 11033 static int 11034 mlx5_action_list_handle_destroy(struct rte_eth_dev *dev, 11035 struct rte_flow_action_list_handle *handle, 11036 struct rte_flow_error *error) 11037 { 11038 const struct mlx5_flow_driver_ops *fops; 11039 11040 MLX5_DRV_FOPS_OR_ERR(dev, fops, action_list_handle_destroy, ENOTSUP); 11041 return fops->action_list_handle_destroy(dev, handle, error); 11042 } 11043 11044 static struct rte_flow_action_list_handle * 11045 mlx5_flow_async_action_list_handle_create(struct rte_eth_dev *dev, 11046 uint32_t queue_id, 11047 const struct 11048 rte_flow_op_attr *op_attr, 11049 const struct 11050 rte_flow_indir_action_conf *conf, 11051 const struct rte_flow_action *actions, 11052 void *user_data, 11053 struct rte_flow_error *error) 11054 { 11055 const struct mlx5_flow_driver_ops *fops; 11056 11057 MLX5_DRV_FOPS_OR_ERR(dev, fops, async_action_list_handle_create, NULL); 11058 return fops->async_action_list_handle_create(dev, queue_id, op_attr, 11059 conf, actions, user_data, 11060 error); 11061 } 11062 11063 static int 11064 mlx5_flow_async_action_list_handle_destroy 11065 (struct rte_eth_dev *dev, uint32_t queue_id, 11066 const struct rte_flow_op_attr *op_attr, 11067 struct rte_flow_action_list_handle *action_handle, 11068 void *user_data, struct rte_flow_error *error) 11069 { 11070 const struct mlx5_flow_driver_ops *fops; 11071 11072 MLX5_DRV_FOPS_OR_ERR(dev, fops, 11073 async_action_list_handle_destroy, ENOTSUP); 11074 return fops->async_action_list_handle_destroy(dev, queue_id, op_attr, 11075 action_handle, user_data, 11076 error); 11077 } 11078 11079 static int 11080 mlx5_flow_action_list_handle_query_update(struct rte_eth_dev *dev, 11081 const 11082 struct rte_flow_action_list_handle *handle, 11083 const void **update, void **query, 11084 enum rte_flow_query_update_mode mode, 11085 struct rte_flow_error *error) 11086 { 11087 const struct mlx5_flow_driver_ops *fops; 11088 11089 MLX5_DRV_FOPS_OR_ERR(dev, fops, 11090 action_list_handle_query_update, ENOTSUP); 11091 return fops->action_list_handle_query_update(dev, handle, update, query, 11092 mode, error); 11093 } 11094 11095 static int 11096 mlx5_flow_async_action_list_handle_query_update(struct rte_eth_dev *dev, 11097 uint32_t queue_id, 11098 const 11099 struct rte_flow_op_attr *op_attr, 11100 const struct 11101 rte_flow_action_list_handle *handle, 11102 const void **update, 11103 void **query, 11104 enum 11105 rte_flow_query_update_mode mode, 11106 void *user_data, 11107 struct rte_flow_error *error) 11108 { 11109 const struct mlx5_flow_driver_ops *fops; 11110 11111 MLX5_DRV_FOPS_OR_ERR(dev, fops, 11112 async_action_list_handle_query_update, ENOTSUP); 11113 return fops->async_action_list_handle_query_update(dev, queue_id, op_attr, 11114 handle, update, 11115 query, mode, 11116 user_data, error); 11117 } 11118 11119 11120 /** 11121 * Destroy all indirect actions (shared RSS). 11122 * 11123 * @param dev 11124 * Pointer to Ethernet device. 11125 * 11126 * @return 11127 * 0 on success, a negative errno value otherwise and rte_errno is set. 11128 */ 11129 int 11130 mlx5_action_handle_flush(struct rte_eth_dev *dev) 11131 { 11132 struct rte_flow_error error; 11133 struct mlx5_priv *priv = dev->data->dev_private; 11134 struct mlx5_shared_action_rss *shared_rss; 11135 int ret = 0; 11136 uint32_t idx; 11137 11138 ILIST_FOREACH(priv->sh->ipool[MLX5_IPOOL_RSS_SHARED_ACTIONS], 11139 priv->rss_shared_actions, idx, shared_rss, next) { 11140 ret |= mlx5_action_handle_destroy(dev, 11141 (struct rte_flow_action_handle *)(uintptr_t)idx, &error); 11142 } 11143 return ret; 11144 } 11145 11146 /** 11147 * Validate existing indirect actions against current device configuration 11148 * and attach them to device resources. 11149 * 11150 * @param dev 11151 * Pointer to Ethernet device. 11152 * 11153 * @return 11154 * 0 on success, a negative errno value otherwise and rte_errno is set. 11155 */ 11156 int 11157 mlx5_action_handle_attach(struct rte_eth_dev *dev) 11158 { 11159 struct mlx5_priv *priv = dev->data->dev_private; 11160 int ret = 0; 11161 struct mlx5_ind_table_obj *ind_tbl, *ind_tbl_last; 11162 11163 LIST_FOREACH(ind_tbl, &priv->standalone_ind_tbls, next) { 11164 const char *message; 11165 uint32_t queue_idx; 11166 11167 ret = mlx5_validate_rss_queues(dev, ind_tbl->queues, 11168 ind_tbl->queues_n, 11169 &message, &queue_idx); 11170 if (ret != 0) { 11171 DRV_LOG(ERR, "Port %u cannot use queue %u in RSS: %s", 11172 dev->data->port_id, ind_tbl->queues[queue_idx], 11173 message); 11174 break; 11175 } 11176 } 11177 if (ret != 0) 11178 return ret; 11179 LIST_FOREACH(ind_tbl, &priv->standalone_ind_tbls, next) { 11180 ret = mlx5_ind_table_obj_attach(dev, ind_tbl); 11181 if (ret != 0) { 11182 DRV_LOG(ERR, "Port %u could not attach " 11183 "indirection table obj %p", 11184 dev->data->port_id, (void *)ind_tbl); 11185 goto error; 11186 } 11187 } 11188 11189 return 0; 11190 error: 11191 ind_tbl_last = ind_tbl; 11192 LIST_FOREACH(ind_tbl, &priv->standalone_ind_tbls, next) { 11193 if (ind_tbl == ind_tbl_last) 11194 break; 11195 if (mlx5_ind_table_obj_detach(dev, ind_tbl) != 0) 11196 DRV_LOG(CRIT, "Port %u could not detach " 11197 "indirection table obj %p on rollback", 11198 dev->data->port_id, (void *)ind_tbl); 11199 } 11200 return ret; 11201 } 11202 11203 /** 11204 * Detach indirect actions of the device from its resources. 11205 * 11206 * @param dev 11207 * Pointer to Ethernet device. 11208 * 11209 * @return 11210 * 0 on success, a negative errno value otherwise and rte_errno is set. 11211 */ 11212 int 11213 mlx5_action_handle_detach(struct rte_eth_dev *dev) 11214 { 11215 struct mlx5_priv *priv = dev->data->dev_private; 11216 int ret = 0; 11217 struct mlx5_ind_table_obj *ind_tbl, *ind_tbl_last; 11218 11219 LIST_FOREACH(ind_tbl, &priv->standalone_ind_tbls, next) { 11220 ret = mlx5_ind_table_obj_detach(dev, ind_tbl); 11221 if (ret != 0) { 11222 DRV_LOG(ERR, "Port %u could not detach " 11223 "indirection table obj %p", 11224 dev->data->port_id, (void *)ind_tbl); 11225 goto error; 11226 } 11227 } 11228 return 0; 11229 error: 11230 ind_tbl_last = ind_tbl; 11231 LIST_FOREACH(ind_tbl, &priv->standalone_ind_tbls, next) { 11232 if (ind_tbl == ind_tbl_last) 11233 break; 11234 if (mlx5_ind_table_obj_attach(dev, ind_tbl) != 0) 11235 DRV_LOG(CRIT, "Port %u could not attach " 11236 "indirection table obj %p on rollback", 11237 dev->data->port_id, (void *)ind_tbl); 11238 } 11239 return ret; 11240 } 11241 11242 #ifndef HAVE_MLX5DV_DR 11243 #define MLX5_DOMAIN_SYNC_FLOW ((1 << 0) | (1 << 1)) 11244 #else 11245 #define MLX5_DOMAIN_SYNC_FLOW \ 11246 (MLX5DV_DR_DOMAIN_SYNC_FLAGS_SW | MLX5DV_DR_DOMAIN_SYNC_FLAGS_HW) 11247 #endif 11248 11249 int rte_pmd_mlx5_sync_flow(uint16_t port_id, uint32_t domains) 11250 { 11251 struct rte_eth_dev *dev = &rte_eth_devices[port_id]; 11252 const struct mlx5_flow_driver_ops *fops; 11253 int ret; 11254 struct rte_flow_attr attr = { .transfer = 0 }; 11255 11256 fops = flow_get_drv_ops(flow_get_drv_type(dev, &attr)); 11257 ret = fops->sync_domain(dev, domains, MLX5_DOMAIN_SYNC_FLOW); 11258 if (ret > 0) 11259 ret = -ret; 11260 return ret; 11261 } 11262 11263 const struct mlx5_flow_tunnel * 11264 mlx5_get_tof(const struct rte_flow_item *item, 11265 const struct rte_flow_action *action, 11266 enum mlx5_tof_rule_type *rule_type) 11267 { 11268 for (; item->type != RTE_FLOW_ITEM_TYPE_END; item++) { 11269 if (item->type == (typeof(item->type)) 11270 MLX5_RTE_FLOW_ITEM_TYPE_TUNNEL) { 11271 *rule_type = MLX5_TUNNEL_OFFLOAD_MATCH_RULE; 11272 return flow_items_to_tunnel(item); 11273 } 11274 } 11275 for (; action->conf != RTE_FLOW_ACTION_TYPE_END; action++) { 11276 if (action->type == (typeof(action->type)) 11277 MLX5_RTE_FLOW_ACTION_TYPE_TUNNEL_SET) { 11278 *rule_type = MLX5_TUNNEL_OFFLOAD_SET_RULE; 11279 return flow_actions_to_tunnel(action); 11280 } 11281 } 11282 return NULL; 11283 } 11284 11285 /** 11286 * tunnel offload functionality is defined for DV environment only 11287 */ 11288 #ifdef HAVE_IBV_FLOW_DV_SUPPORT 11289 __extension__ 11290 union tunnel_offload_mark { 11291 uint32_t val; 11292 struct { 11293 uint32_t app_reserve:8; 11294 uint32_t table_id:15; 11295 uint32_t transfer:1; 11296 uint32_t _unused_:8; 11297 }; 11298 }; 11299 11300 static bool 11301 mlx5_access_tunnel_offload_db 11302 (struct rte_eth_dev *dev, 11303 bool (*match)(struct rte_eth_dev *, 11304 struct mlx5_flow_tunnel *, const void *), 11305 void (*hit)(struct rte_eth_dev *, struct mlx5_flow_tunnel *, void *), 11306 void (*miss)(struct rte_eth_dev *, void *), 11307 void *ctx, bool lock_op); 11308 11309 static int 11310 flow_tunnel_add_default_miss(struct rte_eth_dev *dev, 11311 struct rte_flow *flow, 11312 const struct rte_flow_attr *attr, 11313 const struct rte_flow_action *app_actions, 11314 uint32_t flow_idx, 11315 const struct mlx5_flow_tunnel *tunnel, 11316 struct tunnel_default_miss_ctx *ctx, 11317 struct rte_flow_error *error) 11318 { 11319 struct mlx5_priv *priv = dev->data->dev_private; 11320 struct mlx5_flow *dev_flow; 11321 struct rte_flow_attr miss_attr = *attr; 11322 const struct rte_flow_item miss_items[2] = { 11323 { 11324 .type = RTE_FLOW_ITEM_TYPE_ETH, 11325 .spec = NULL, 11326 .last = NULL, 11327 .mask = NULL 11328 }, 11329 { 11330 .type = RTE_FLOW_ITEM_TYPE_END, 11331 .spec = NULL, 11332 .last = NULL, 11333 .mask = NULL 11334 } 11335 }; 11336 union tunnel_offload_mark mark_id; 11337 struct rte_flow_action_mark miss_mark; 11338 struct rte_flow_action miss_actions[3] = { 11339 [0] = { .type = RTE_FLOW_ACTION_TYPE_MARK, .conf = &miss_mark }, 11340 [2] = { .type = RTE_FLOW_ACTION_TYPE_END, .conf = NULL } 11341 }; 11342 const struct rte_flow_action_jump *jump_data; 11343 uint32_t i, flow_table = 0; /* prevent compilation warning */ 11344 struct flow_grp_info grp_info = { 11345 .external = 1, 11346 .transfer = attr->transfer, 11347 .fdb_def_rule = !!priv->fdb_def_rule, 11348 .std_tbl_fix = 0, 11349 }; 11350 int ret; 11351 11352 if (!attr->transfer) { 11353 uint32_t q_size; 11354 11355 miss_actions[1].type = RTE_FLOW_ACTION_TYPE_RSS; 11356 q_size = priv->reta_idx_n * sizeof(ctx->queue[0]); 11357 ctx->queue = mlx5_malloc(MLX5_MEM_SYS | MLX5_MEM_ZERO, q_size, 11358 0, SOCKET_ID_ANY); 11359 if (!ctx->queue) 11360 return rte_flow_error_set 11361 (error, ENOMEM, 11362 RTE_FLOW_ERROR_TYPE_ACTION_CONF, 11363 NULL, "invalid default miss RSS"); 11364 ctx->action_rss.func = RTE_ETH_HASH_FUNCTION_DEFAULT, 11365 ctx->action_rss.level = 0, 11366 ctx->action_rss.types = priv->rss_conf.rss_hf, 11367 ctx->action_rss.key_len = priv->rss_conf.rss_key_len, 11368 ctx->action_rss.queue_num = priv->reta_idx_n, 11369 ctx->action_rss.key = priv->rss_conf.rss_key, 11370 ctx->action_rss.queue = ctx->queue; 11371 if (!priv->reta_idx_n || !priv->rxqs_n) 11372 return rte_flow_error_set 11373 (error, EINVAL, 11374 RTE_FLOW_ERROR_TYPE_ACTION_CONF, 11375 NULL, "invalid port configuration"); 11376 if (!(dev->data->dev_conf.rxmode.mq_mode & RTE_ETH_MQ_RX_RSS_FLAG)) 11377 ctx->action_rss.types = 0; 11378 for (i = 0; i != priv->reta_idx_n; ++i) 11379 ctx->queue[i] = (*priv->reta_idx)[i]; 11380 } else { 11381 miss_actions[1].type = RTE_FLOW_ACTION_TYPE_JUMP; 11382 ctx->miss_jump.group = MLX5_TNL_MISS_FDB_JUMP_GRP; 11383 } 11384 miss_actions[1].conf = (typeof(miss_actions[1].conf))ctx->raw; 11385 for (; app_actions->type != RTE_FLOW_ACTION_TYPE_JUMP; app_actions++); 11386 jump_data = app_actions->conf; 11387 miss_attr.priority = MLX5_TNL_MISS_RULE_PRIORITY; 11388 miss_attr.group = jump_data->group; 11389 ret = mlx5_flow_group_to_table(dev, tunnel, jump_data->group, 11390 &flow_table, &grp_info, error); 11391 if (ret) 11392 return rte_flow_error_set(error, EINVAL, 11393 RTE_FLOW_ERROR_TYPE_ACTION_CONF, 11394 NULL, "invalid tunnel id"); 11395 mark_id.app_reserve = 0; 11396 mark_id.table_id = tunnel_flow_tbl_to_id(flow_table); 11397 mark_id.transfer = !!attr->transfer; 11398 mark_id._unused_ = 0; 11399 miss_mark.id = mark_id.val; 11400 dev_flow = flow_drv_prepare(dev, flow, &miss_attr, 11401 miss_items, miss_actions, flow_idx, error); 11402 if (!dev_flow) 11403 return -rte_errno; 11404 dev_flow->flow = flow; 11405 dev_flow->external = true; 11406 dev_flow->tunnel = tunnel; 11407 dev_flow->tof_type = MLX5_TUNNEL_OFFLOAD_MISS_RULE; 11408 /* Subflow object was created, we must include one in the list. */ 11409 SILIST_INSERT(&flow->dev_handles, dev_flow->handle_idx, 11410 dev_flow->handle, next); 11411 DRV_LOG(DEBUG, 11412 "port %u tunnel type=%d id=%u miss rule priority=%u group=%u", 11413 dev->data->port_id, tunnel->app_tunnel.type, 11414 tunnel->tunnel_id, miss_attr.priority, miss_attr.group); 11415 ret = flow_drv_translate(dev, dev_flow, &miss_attr, miss_items, 11416 miss_actions, error); 11417 if (!ret) 11418 ret = flow_mreg_update_copy_table(dev, flow, miss_actions, 11419 error); 11420 11421 return ret; 11422 } 11423 11424 static const struct mlx5_flow_tbl_data_entry * 11425 tunnel_mark_decode(struct rte_eth_dev *dev, uint32_t mark) 11426 { 11427 struct mlx5_priv *priv = dev->data->dev_private; 11428 struct mlx5_dev_ctx_shared *sh = priv->sh; 11429 struct mlx5_list_entry *he; 11430 union tunnel_offload_mark mbits = { .val = mark }; 11431 union mlx5_flow_tbl_key table_key = { 11432 { 11433 .level = tunnel_id_to_flow_tbl(mbits.table_id), 11434 .id = 0, 11435 .reserved = 0, 11436 .dummy = 0, 11437 .is_fdb = !!mbits.transfer, 11438 .is_egress = 0, 11439 } 11440 }; 11441 struct mlx5_flow_cb_ctx ctx = { 11442 .data = &table_key.v64, 11443 }; 11444 11445 he = mlx5_hlist_lookup(sh->flow_tbls, table_key.v64, &ctx); 11446 return he ? 11447 container_of(he, struct mlx5_flow_tbl_data_entry, entry) : NULL; 11448 } 11449 11450 static void 11451 mlx5_flow_tunnel_grp2tbl_remove_cb(void *tool_ctx, 11452 struct mlx5_list_entry *entry) 11453 { 11454 struct mlx5_dev_ctx_shared *sh = tool_ctx; 11455 struct tunnel_tbl_entry *tte = container_of(entry, typeof(*tte), hash); 11456 11457 mlx5_ipool_free(sh->ipool[MLX5_IPOOL_TNL_TBL_ID], 11458 tunnel_flow_tbl_to_id(tte->flow_table)); 11459 mlx5_free(tte); 11460 } 11461 11462 static int 11463 mlx5_flow_tunnel_grp2tbl_match_cb(void *tool_ctx __rte_unused, 11464 struct mlx5_list_entry *entry, void *cb_ctx) 11465 { 11466 struct mlx5_flow_cb_ctx *ctx = cb_ctx; 11467 union tunnel_tbl_key tbl = { 11468 .val = *(uint64_t *)(ctx->data), 11469 }; 11470 struct tunnel_tbl_entry *tte = container_of(entry, typeof(*tte), hash); 11471 11472 return tbl.tunnel_id != tte->tunnel_id || tbl.group != tte->group; 11473 } 11474 11475 static struct mlx5_list_entry * 11476 mlx5_flow_tunnel_grp2tbl_create_cb(void *tool_ctx, void *cb_ctx) 11477 { 11478 struct mlx5_dev_ctx_shared *sh = tool_ctx; 11479 struct mlx5_flow_cb_ctx *ctx = cb_ctx; 11480 struct tunnel_tbl_entry *tte; 11481 union tunnel_tbl_key tbl = { 11482 .val = *(uint64_t *)(ctx->data), 11483 }; 11484 11485 tte = mlx5_malloc(MLX5_MEM_SYS | MLX5_MEM_ZERO, 11486 sizeof(*tte), 0, 11487 SOCKET_ID_ANY); 11488 if (!tte) 11489 goto err; 11490 mlx5_ipool_malloc(sh->ipool[MLX5_IPOOL_TNL_TBL_ID], 11491 &tte->flow_table); 11492 if (tte->flow_table >= MLX5_MAX_TABLES) { 11493 DRV_LOG(ERR, "Tunnel TBL ID %d exceed max limit.", 11494 tte->flow_table); 11495 mlx5_ipool_free(sh->ipool[MLX5_IPOOL_TNL_TBL_ID], 11496 tte->flow_table); 11497 goto err; 11498 } else if (!tte->flow_table) { 11499 goto err; 11500 } 11501 tte->flow_table = tunnel_id_to_flow_tbl(tte->flow_table); 11502 tte->tunnel_id = tbl.tunnel_id; 11503 tte->group = tbl.group; 11504 return &tte->hash; 11505 err: 11506 if (tte) 11507 mlx5_free(tte); 11508 return NULL; 11509 } 11510 11511 static struct mlx5_list_entry * 11512 mlx5_flow_tunnel_grp2tbl_clone_cb(void *tool_ctx __rte_unused, 11513 struct mlx5_list_entry *oentry, 11514 void *cb_ctx __rte_unused) 11515 { 11516 struct tunnel_tbl_entry *tte = mlx5_malloc(MLX5_MEM_SYS, sizeof(*tte), 11517 0, SOCKET_ID_ANY); 11518 11519 if (!tte) 11520 return NULL; 11521 memcpy(tte, oentry, sizeof(*tte)); 11522 return &tte->hash; 11523 } 11524 11525 static void 11526 mlx5_flow_tunnel_grp2tbl_clone_free_cb(void *tool_ctx __rte_unused, 11527 struct mlx5_list_entry *entry) 11528 { 11529 struct tunnel_tbl_entry *tte = container_of(entry, typeof(*tte), hash); 11530 11531 mlx5_free(tte); 11532 } 11533 11534 static uint32_t 11535 tunnel_flow_group_to_flow_table(struct rte_eth_dev *dev, 11536 const struct mlx5_flow_tunnel *tunnel, 11537 uint32_t group, uint32_t *table, 11538 struct rte_flow_error *error) 11539 { 11540 struct mlx5_list_entry *he; 11541 struct tunnel_tbl_entry *tte; 11542 union tunnel_tbl_key key = { 11543 .tunnel_id = tunnel ? tunnel->tunnel_id : 0, 11544 .group = group 11545 }; 11546 struct mlx5_flow_tunnel_hub *thub = mlx5_tunnel_hub(dev); 11547 struct mlx5_hlist *group_hash; 11548 struct mlx5_flow_cb_ctx ctx = { 11549 .data = &key.val, 11550 }; 11551 11552 group_hash = tunnel ? tunnel->groups : thub->groups; 11553 he = mlx5_hlist_register(group_hash, key.val, &ctx); 11554 if (!he) 11555 return rte_flow_error_set(error, EINVAL, 11556 RTE_FLOW_ERROR_TYPE_ATTR_GROUP, 11557 NULL, 11558 "tunnel group index not supported"); 11559 tte = container_of(he, typeof(*tte), hash); 11560 *table = tte->flow_table; 11561 DRV_LOG(DEBUG, "port %u tunnel %u group=%#x table=%#x", 11562 dev->data->port_id, key.tunnel_id, group, *table); 11563 return 0; 11564 } 11565 11566 static void 11567 mlx5_flow_tunnel_free(struct rte_eth_dev *dev, 11568 struct mlx5_flow_tunnel *tunnel) 11569 { 11570 struct mlx5_priv *priv = dev->data->dev_private; 11571 struct mlx5_indexed_pool *ipool; 11572 11573 DRV_LOG(DEBUG, "port %u release pmd tunnel id=0x%x", 11574 dev->data->port_id, tunnel->tunnel_id); 11575 LIST_REMOVE(tunnel, chain); 11576 mlx5_hlist_destroy(tunnel->groups); 11577 ipool = priv->sh->ipool[MLX5_IPOOL_TUNNEL_ID]; 11578 mlx5_ipool_free(ipool, tunnel->tunnel_id); 11579 } 11580 11581 static bool 11582 mlx5_access_tunnel_offload_db 11583 (struct rte_eth_dev *dev, 11584 bool (*match)(struct rte_eth_dev *, 11585 struct mlx5_flow_tunnel *, const void *), 11586 void (*hit)(struct rte_eth_dev *, struct mlx5_flow_tunnel *, void *), 11587 void (*miss)(struct rte_eth_dev *, void *), 11588 void *ctx, bool lock_op) 11589 { 11590 bool verdict = false; 11591 struct mlx5_flow_tunnel_hub *thub = mlx5_tunnel_hub(dev); 11592 struct mlx5_flow_tunnel *tunnel; 11593 11594 rte_spinlock_lock(&thub->sl); 11595 LIST_FOREACH(tunnel, &thub->tunnels, chain) { 11596 verdict = match(dev, tunnel, (const void *)ctx); 11597 if (verdict) 11598 break; 11599 } 11600 if (!lock_op) 11601 rte_spinlock_unlock(&thub->sl); 11602 if (verdict && hit) 11603 hit(dev, tunnel, ctx); 11604 if (!verdict && miss) 11605 miss(dev, ctx); 11606 if (lock_op) 11607 rte_spinlock_unlock(&thub->sl); 11608 11609 return verdict; 11610 } 11611 11612 struct tunnel_db_find_tunnel_id_ctx { 11613 uint32_t tunnel_id; 11614 struct mlx5_flow_tunnel *tunnel; 11615 }; 11616 11617 static bool 11618 find_tunnel_id_match(struct rte_eth_dev *dev, 11619 struct mlx5_flow_tunnel *tunnel, const void *x) 11620 { 11621 const struct tunnel_db_find_tunnel_id_ctx *ctx = x; 11622 11623 RTE_SET_USED(dev); 11624 return tunnel->tunnel_id == ctx->tunnel_id; 11625 } 11626 11627 static void 11628 find_tunnel_id_hit(struct rte_eth_dev *dev, 11629 struct mlx5_flow_tunnel *tunnel, void *x) 11630 { 11631 struct tunnel_db_find_tunnel_id_ctx *ctx = x; 11632 RTE_SET_USED(dev); 11633 ctx->tunnel = tunnel; 11634 } 11635 11636 static struct mlx5_flow_tunnel * 11637 mlx5_find_tunnel_id(struct rte_eth_dev *dev, uint32_t id) 11638 { 11639 struct tunnel_db_find_tunnel_id_ctx ctx = { 11640 .tunnel_id = id, 11641 }; 11642 11643 mlx5_access_tunnel_offload_db(dev, find_tunnel_id_match, 11644 find_tunnel_id_hit, NULL, &ctx, true); 11645 11646 return ctx.tunnel; 11647 } 11648 11649 static struct mlx5_flow_tunnel * 11650 mlx5_flow_tunnel_allocate(struct rte_eth_dev *dev, 11651 const struct rte_flow_tunnel *app_tunnel) 11652 { 11653 struct mlx5_priv *priv = dev->data->dev_private; 11654 struct mlx5_indexed_pool *ipool; 11655 struct mlx5_flow_tunnel *tunnel; 11656 uint32_t id; 11657 11658 ipool = priv->sh->ipool[MLX5_IPOOL_TUNNEL_ID]; 11659 tunnel = mlx5_ipool_zmalloc(ipool, &id); 11660 if (!tunnel) 11661 return NULL; 11662 if (id >= MLX5_MAX_TUNNELS) { 11663 mlx5_ipool_free(ipool, id); 11664 DRV_LOG(ERR, "Tunnel ID %d exceed max limit.", id); 11665 return NULL; 11666 } 11667 tunnel->groups = mlx5_hlist_create("tunnel groups", 64, false, true, 11668 priv->sh, 11669 mlx5_flow_tunnel_grp2tbl_create_cb, 11670 mlx5_flow_tunnel_grp2tbl_match_cb, 11671 mlx5_flow_tunnel_grp2tbl_remove_cb, 11672 mlx5_flow_tunnel_grp2tbl_clone_cb, 11673 mlx5_flow_tunnel_grp2tbl_clone_free_cb); 11674 if (!tunnel->groups) { 11675 mlx5_ipool_free(ipool, id); 11676 return NULL; 11677 } 11678 /* initiate new PMD tunnel */ 11679 memcpy(&tunnel->app_tunnel, app_tunnel, sizeof(*app_tunnel)); 11680 tunnel->tunnel_id = id; 11681 tunnel->action.type = (typeof(tunnel->action.type)) 11682 MLX5_RTE_FLOW_ACTION_TYPE_TUNNEL_SET; 11683 tunnel->action.conf = tunnel; 11684 tunnel->item.type = (typeof(tunnel->item.type)) 11685 MLX5_RTE_FLOW_ITEM_TYPE_TUNNEL; 11686 tunnel->item.spec = tunnel; 11687 tunnel->item.last = NULL; 11688 tunnel->item.mask = NULL; 11689 11690 DRV_LOG(DEBUG, "port %u new pmd tunnel id=0x%x", 11691 dev->data->port_id, tunnel->tunnel_id); 11692 11693 return tunnel; 11694 } 11695 11696 struct tunnel_db_get_tunnel_ctx { 11697 const struct rte_flow_tunnel *app_tunnel; 11698 struct mlx5_flow_tunnel *tunnel; 11699 }; 11700 11701 static bool get_tunnel_match(struct rte_eth_dev *dev, 11702 struct mlx5_flow_tunnel *tunnel, const void *x) 11703 { 11704 const struct tunnel_db_get_tunnel_ctx *ctx = x; 11705 11706 RTE_SET_USED(dev); 11707 return !memcmp(ctx->app_tunnel, &tunnel->app_tunnel, 11708 sizeof(*ctx->app_tunnel)); 11709 } 11710 11711 static void get_tunnel_hit(struct rte_eth_dev *dev, 11712 struct mlx5_flow_tunnel *tunnel, void *x) 11713 { 11714 /* called under tunnel spinlock protection */ 11715 struct tunnel_db_get_tunnel_ctx *ctx = x; 11716 11717 RTE_SET_USED(dev); 11718 tunnel->refctn++; 11719 ctx->tunnel = tunnel; 11720 } 11721 11722 static void get_tunnel_miss(struct rte_eth_dev *dev, void *x) 11723 { 11724 /* called under tunnel spinlock protection */ 11725 struct mlx5_flow_tunnel_hub *thub = mlx5_tunnel_hub(dev); 11726 struct tunnel_db_get_tunnel_ctx *ctx = x; 11727 11728 rte_spinlock_unlock(&thub->sl); 11729 ctx->tunnel = mlx5_flow_tunnel_allocate(dev, ctx->app_tunnel); 11730 rte_spinlock_lock(&thub->sl); 11731 if (ctx->tunnel) { 11732 ctx->tunnel->refctn = 1; 11733 LIST_INSERT_HEAD(&thub->tunnels, ctx->tunnel, chain); 11734 } 11735 } 11736 11737 11738 static int 11739 mlx5_get_flow_tunnel(struct rte_eth_dev *dev, 11740 const struct rte_flow_tunnel *app_tunnel, 11741 struct mlx5_flow_tunnel **tunnel) 11742 { 11743 struct tunnel_db_get_tunnel_ctx ctx = { 11744 .app_tunnel = app_tunnel, 11745 }; 11746 11747 mlx5_access_tunnel_offload_db(dev, get_tunnel_match, get_tunnel_hit, 11748 get_tunnel_miss, &ctx, true); 11749 *tunnel = ctx.tunnel; 11750 return ctx.tunnel ? 0 : -ENOMEM; 11751 } 11752 11753 void mlx5_release_tunnel_hub(struct mlx5_dev_ctx_shared *sh, uint16_t port_id) 11754 { 11755 struct mlx5_flow_tunnel_hub *thub = sh->tunnel_hub; 11756 11757 if (!thub) 11758 return; 11759 if (!LIST_EMPTY(&thub->tunnels)) 11760 DRV_LOG(WARNING, "port %u tunnels present", port_id); 11761 mlx5_hlist_destroy(thub->groups); 11762 mlx5_free(thub); 11763 } 11764 11765 int mlx5_alloc_tunnel_hub(struct mlx5_dev_ctx_shared *sh) 11766 { 11767 int err; 11768 struct mlx5_flow_tunnel_hub *thub; 11769 11770 thub = mlx5_malloc(MLX5_MEM_SYS | MLX5_MEM_ZERO, sizeof(*thub), 11771 0, SOCKET_ID_ANY); 11772 if (!thub) 11773 return -ENOMEM; 11774 LIST_INIT(&thub->tunnels); 11775 rte_spinlock_init(&thub->sl); 11776 thub->groups = mlx5_hlist_create("flow groups", 64, 11777 false, true, sh, 11778 mlx5_flow_tunnel_grp2tbl_create_cb, 11779 mlx5_flow_tunnel_grp2tbl_match_cb, 11780 mlx5_flow_tunnel_grp2tbl_remove_cb, 11781 mlx5_flow_tunnel_grp2tbl_clone_cb, 11782 mlx5_flow_tunnel_grp2tbl_clone_free_cb); 11783 if (!thub->groups) { 11784 err = -rte_errno; 11785 goto err; 11786 } 11787 sh->tunnel_hub = thub; 11788 11789 return 0; 11790 11791 err: 11792 if (thub->groups) 11793 mlx5_hlist_destroy(thub->groups); 11794 if (thub) 11795 mlx5_free(thub); 11796 return err; 11797 } 11798 11799 static inline int 11800 mlx5_flow_tunnel_validate(struct rte_eth_dev *dev, 11801 struct rte_flow_tunnel *tunnel, 11802 struct rte_flow_error *error) 11803 { 11804 struct mlx5_priv *priv = dev->data->dev_private; 11805 11806 if (!priv->sh->config.dv_flow_en) 11807 return rte_flow_error_set(error, ENOTSUP, 11808 RTE_FLOW_ERROR_TYPE_ACTION_CONF, NULL, 11809 "flow DV interface is off"); 11810 if (!is_tunnel_offload_active(dev)) 11811 return rte_flow_error_set(error, ENOTSUP, 11812 RTE_FLOW_ERROR_TYPE_ACTION_CONF, NULL, 11813 "tunnel offload was not activated, consider setting dv_xmeta_en=3"); 11814 if (!tunnel) 11815 return rte_flow_error_set(error, EINVAL, 11816 RTE_FLOW_ERROR_TYPE_ACTION_CONF, NULL, 11817 "no application tunnel"); 11818 switch (tunnel->type) { 11819 default: 11820 return rte_flow_error_set(error, EINVAL, 11821 RTE_FLOW_ERROR_TYPE_ACTION_CONF, NULL, 11822 "unsupported tunnel type"); 11823 case RTE_FLOW_ITEM_TYPE_VXLAN: 11824 case RTE_FLOW_ITEM_TYPE_GRE: 11825 case RTE_FLOW_ITEM_TYPE_NVGRE: 11826 case RTE_FLOW_ITEM_TYPE_GENEVE: 11827 break; 11828 } 11829 return 0; 11830 } 11831 11832 static int 11833 mlx5_flow_tunnel_decap_set(struct rte_eth_dev *dev, 11834 struct rte_flow_tunnel *app_tunnel, 11835 struct rte_flow_action **actions, 11836 uint32_t *num_of_actions, 11837 struct rte_flow_error *error) 11838 { 11839 struct mlx5_flow_tunnel *tunnel; 11840 int ret = mlx5_flow_tunnel_validate(dev, app_tunnel, error); 11841 11842 if (ret) 11843 return ret; 11844 ret = mlx5_get_flow_tunnel(dev, app_tunnel, &tunnel); 11845 if (ret < 0) { 11846 return rte_flow_error_set(error, ret, 11847 RTE_FLOW_ERROR_TYPE_ACTION_CONF, NULL, 11848 "failed to initialize pmd tunnel"); 11849 } 11850 *actions = &tunnel->action; 11851 *num_of_actions = 1; 11852 return 0; 11853 } 11854 11855 static int 11856 mlx5_flow_tunnel_match(struct rte_eth_dev *dev, 11857 struct rte_flow_tunnel *app_tunnel, 11858 struct rte_flow_item **items, 11859 uint32_t *num_of_items, 11860 struct rte_flow_error *error) 11861 { 11862 struct mlx5_flow_tunnel *tunnel; 11863 int ret = mlx5_flow_tunnel_validate(dev, app_tunnel, error); 11864 11865 if (ret) 11866 return ret; 11867 ret = mlx5_get_flow_tunnel(dev, app_tunnel, &tunnel); 11868 if (ret < 0) { 11869 return rte_flow_error_set(error, ret, 11870 RTE_FLOW_ERROR_TYPE_HANDLE, NULL, 11871 "failed to initialize pmd tunnel"); 11872 } 11873 *items = &tunnel->item; 11874 *num_of_items = 1; 11875 return 0; 11876 } 11877 11878 struct tunnel_db_element_release_ctx { 11879 struct rte_flow_item *items; 11880 struct rte_flow_action *actions; 11881 uint32_t num_elements; 11882 struct rte_flow_error *error; 11883 int ret; 11884 }; 11885 11886 static bool 11887 tunnel_element_release_match(struct rte_eth_dev *dev, 11888 struct mlx5_flow_tunnel *tunnel, const void *x) 11889 { 11890 const struct tunnel_db_element_release_ctx *ctx = x; 11891 11892 RTE_SET_USED(dev); 11893 if (ctx->num_elements != 1) 11894 return false; 11895 else if (ctx->items) 11896 return ctx->items == &tunnel->item; 11897 else if (ctx->actions) 11898 return ctx->actions == &tunnel->action; 11899 11900 return false; 11901 } 11902 11903 static void 11904 tunnel_element_release_hit(struct rte_eth_dev *dev, 11905 struct mlx5_flow_tunnel *tunnel, void *x) 11906 { 11907 struct tunnel_db_element_release_ctx *ctx = x; 11908 ctx->ret = 0; 11909 if (!(__atomic_fetch_sub(&tunnel->refctn, 1, __ATOMIC_RELAXED) - 1)) 11910 mlx5_flow_tunnel_free(dev, tunnel); 11911 } 11912 11913 static void 11914 tunnel_element_release_miss(struct rte_eth_dev *dev, void *x) 11915 { 11916 struct tunnel_db_element_release_ctx *ctx = x; 11917 RTE_SET_USED(dev); 11918 ctx->ret = rte_flow_error_set(ctx->error, EINVAL, 11919 RTE_FLOW_ERROR_TYPE_HANDLE, NULL, 11920 "invalid argument"); 11921 } 11922 11923 static int 11924 mlx5_flow_tunnel_item_release(struct rte_eth_dev *dev, 11925 struct rte_flow_item *pmd_items, 11926 uint32_t num_items, struct rte_flow_error *err) 11927 { 11928 struct tunnel_db_element_release_ctx ctx = { 11929 .items = pmd_items, 11930 .actions = NULL, 11931 .num_elements = num_items, 11932 .error = err, 11933 }; 11934 11935 mlx5_access_tunnel_offload_db(dev, tunnel_element_release_match, 11936 tunnel_element_release_hit, 11937 tunnel_element_release_miss, &ctx, false); 11938 11939 return ctx.ret; 11940 } 11941 11942 static int 11943 mlx5_flow_tunnel_action_release(struct rte_eth_dev *dev, 11944 struct rte_flow_action *pmd_actions, 11945 uint32_t num_actions, struct rte_flow_error *err) 11946 { 11947 struct tunnel_db_element_release_ctx ctx = { 11948 .items = NULL, 11949 .actions = pmd_actions, 11950 .num_elements = num_actions, 11951 .error = err, 11952 }; 11953 11954 mlx5_access_tunnel_offload_db(dev, tunnel_element_release_match, 11955 tunnel_element_release_hit, 11956 tunnel_element_release_miss, &ctx, false); 11957 11958 return ctx.ret; 11959 } 11960 11961 static int 11962 mlx5_flow_tunnel_get_restore_info(struct rte_eth_dev *dev, 11963 struct rte_mbuf *m, 11964 struct rte_flow_restore_info *info, 11965 struct rte_flow_error *err) 11966 { 11967 uint64_t ol_flags = m->ol_flags; 11968 const struct mlx5_flow_tbl_data_entry *tble; 11969 const uint64_t mask = RTE_MBUF_F_RX_FDIR | RTE_MBUF_F_RX_FDIR_ID; 11970 struct mlx5_priv *priv = dev->data->dev_private; 11971 11972 if (priv->tunnel_enabled == 0) 11973 goto err; 11974 if ((ol_flags & mask) != mask) 11975 goto err; 11976 tble = tunnel_mark_decode(dev, m->hash.fdir.hi); 11977 if (!tble) { 11978 DRV_LOG(DEBUG, "port %u invalid miss tunnel mark %#x", 11979 dev->data->port_id, m->hash.fdir.hi); 11980 goto err; 11981 } 11982 MLX5_ASSERT(tble->tunnel); 11983 memcpy(&info->tunnel, &tble->tunnel->app_tunnel, sizeof(info->tunnel)); 11984 info->group_id = tble->group_id; 11985 info->flags = RTE_FLOW_RESTORE_INFO_TUNNEL | 11986 RTE_FLOW_RESTORE_INFO_GROUP_ID | 11987 RTE_FLOW_RESTORE_INFO_ENCAPSULATED; 11988 11989 return 0; 11990 11991 err: 11992 return rte_flow_error_set(err, EINVAL, 11993 RTE_FLOW_ERROR_TYPE_UNSPECIFIED, NULL, 11994 "failed to get restore info"); 11995 } 11996 11997 #else /* HAVE_IBV_FLOW_DV_SUPPORT */ 11998 static int 11999 mlx5_flow_tunnel_decap_set(__rte_unused struct rte_eth_dev *dev, 12000 __rte_unused struct rte_flow_tunnel *app_tunnel, 12001 __rte_unused struct rte_flow_action **actions, 12002 __rte_unused uint32_t *num_of_actions, 12003 __rte_unused struct rte_flow_error *error) 12004 { 12005 return -ENOTSUP; 12006 } 12007 12008 static int 12009 mlx5_flow_tunnel_match(__rte_unused struct rte_eth_dev *dev, 12010 __rte_unused struct rte_flow_tunnel *app_tunnel, 12011 __rte_unused struct rte_flow_item **items, 12012 __rte_unused uint32_t *num_of_items, 12013 __rte_unused struct rte_flow_error *error) 12014 { 12015 return -ENOTSUP; 12016 } 12017 12018 static int 12019 mlx5_flow_tunnel_item_release(__rte_unused struct rte_eth_dev *dev, 12020 __rte_unused struct rte_flow_item *pmd_items, 12021 __rte_unused uint32_t num_items, 12022 __rte_unused struct rte_flow_error *err) 12023 { 12024 return -ENOTSUP; 12025 } 12026 12027 static int 12028 mlx5_flow_tunnel_action_release(__rte_unused struct rte_eth_dev *dev, 12029 __rte_unused struct rte_flow_action *pmd_action, 12030 __rte_unused uint32_t num_actions, 12031 __rte_unused struct rte_flow_error *err) 12032 { 12033 return -ENOTSUP; 12034 } 12035 12036 static int 12037 mlx5_flow_tunnel_get_restore_info(__rte_unused struct rte_eth_dev *dev, 12038 __rte_unused struct rte_mbuf *m, 12039 __rte_unused struct rte_flow_restore_info *i, 12040 __rte_unused struct rte_flow_error *err) 12041 { 12042 return -ENOTSUP; 12043 } 12044 12045 static int 12046 flow_tunnel_add_default_miss(__rte_unused struct rte_eth_dev *dev, 12047 __rte_unused struct rte_flow *flow, 12048 __rte_unused const struct rte_flow_attr *attr, 12049 __rte_unused const struct rte_flow_action *actions, 12050 __rte_unused uint32_t flow_idx, 12051 __rte_unused const struct mlx5_flow_tunnel *tunnel, 12052 __rte_unused struct tunnel_default_miss_ctx *ctx, 12053 __rte_unused struct rte_flow_error *error) 12054 { 12055 return -ENOTSUP; 12056 } 12057 12058 static struct mlx5_flow_tunnel * 12059 mlx5_find_tunnel_id(__rte_unused struct rte_eth_dev *dev, 12060 __rte_unused uint32_t id) 12061 { 12062 return NULL; 12063 } 12064 12065 static void 12066 mlx5_flow_tunnel_free(__rte_unused struct rte_eth_dev *dev, 12067 __rte_unused struct mlx5_flow_tunnel *tunnel) 12068 { 12069 } 12070 12071 static uint32_t 12072 tunnel_flow_group_to_flow_table(__rte_unused struct rte_eth_dev *dev, 12073 __rte_unused const struct mlx5_flow_tunnel *t, 12074 __rte_unused uint32_t group, 12075 __rte_unused uint32_t *table, 12076 struct rte_flow_error *error) 12077 { 12078 return rte_flow_error_set(error, ENOTSUP, 12079 RTE_FLOW_ERROR_TYPE_UNSPECIFIED, NULL, 12080 "tunnel offload requires DV support"); 12081 } 12082 12083 void 12084 mlx5_release_tunnel_hub(__rte_unused struct mlx5_dev_ctx_shared *sh, 12085 __rte_unused uint16_t port_id) 12086 { 12087 } 12088 #endif /* HAVE_IBV_FLOW_DV_SUPPORT */ 12089 12090 /* Flex flow item API */ 12091 static struct rte_flow_item_flex_handle * 12092 mlx5_flow_flex_item_create(struct rte_eth_dev *dev, 12093 const struct rte_flow_item_flex_conf *conf, 12094 struct rte_flow_error *error) 12095 { 12096 static const char err_msg[] = "flex item creation unsupported"; 12097 struct mlx5_priv *priv = dev->data->dev_private; 12098 struct rte_flow_attr attr = { .transfer = 0 }; 12099 const struct mlx5_flow_driver_ops *fops = 12100 flow_get_drv_ops(flow_get_drv_type(dev, &attr)); 12101 12102 if (!priv->pci_dev) { 12103 rte_flow_error_set(error, ENOTSUP, 12104 RTE_FLOW_ERROR_TYPE_UNSPECIFIED, NULL, 12105 "create flex item on PF only"); 12106 return NULL; 12107 } 12108 switch (priv->pci_dev->id.device_id) { 12109 case PCI_DEVICE_ID_MELLANOX_BLUEFIELD2: 12110 case PCI_DEVICE_ID_MELLANOX_BLUEFIELD3: 12111 break; 12112 default: 12113 rte_flow_error_set(error, ENOTSUP, 12114 RTE_FLOW_ERROR_TYPE_UNSPECIFIED, NULL, 12115 "flex item available on BlueField ports only"); 12116 return NULL; 12117 } 12118 if (!fops->item_create) { 12119 DRV_LOG(ERR, "port %u %s.", dev->data->port_id, err_msg); 12120 rte_flow_error_set(error, ENOTSUP, RTE_FLOW_ERROR_TYPE_ACTION, 12121 NULL, err_msg); 12122 return NULL; 12123 } 12124 return fops->item_create(dev, conf, error); 12125 } 12126 12127 static int 12128 mlx5_flow_flex_item_release(struct rte_eth_dev *dev, 12129 const struct rte_flow_item_flex_handle *handle, 12130 struct rte_flow_error *error) 12131 { 12132 static const char err_msg[] = "flex item release unsupported"; 12133 struct rte_flow_attr attr = { .transfer = 0 }; 12134 const struct mlx5_flow_driver_ops *fops = 12135 flow_get_drv_ops(flow_get_drv_type(dev, &attr)); 12136 12137 if (!fops->item_release) { 12138 DRV_LOG(ERR, "port %u %s.", dev->data->port_id, err_msg); 12139 rte_flow_error_set(error, ENOTSUP, RTE_FLOW_ERROR_TYPE_ACTION, 12140 NULL, err_msg); 12141 return -rte_errno; 12142 } 12143 return fops->item_release(dev, handle, error); 12144 } 12145 12146 static void 12147 mlx5_dbg__print_pattern(const struct rte_flow_item *item) 12148 { 12149 int ret; 12150 struct rte_flow_error error; 12151 12152 for (; item->type != RTE_FLOW_ITEM_TYPE_END; item++) { 12153 char *item_name; 12154 ret = rte_flow_conv(RTE_FLOW_CONV_OP_ITEM_NAME_PTR, &item_name, 12155 sizeof(item_name), 12156 (void *)(uintptr_t)item->type, &error); 12157 if (ret > 0) 12158 printf("%s ", item_name); 12159 else 12160 printf("%d\n", (int)item->type); 12161 } 12162 printf("END\n"); 12163 } 12164 12165 static int 12166 mlx5_flow_is_std_vxlan_port(const struct rte_flow_item *udp_item) 12167 { 12168 const struct rte_flow_item_udp *spec = udp_item->spec; 12169 const struct rte_flow_item_udp *mask = udp_item->mask; 12170 uint16_t udp_dport = 0; 12171 12172 if (spec != NULL) { 12173 if (!mask) 12174 mask = &rte_flow_item_udp_mask; 12175 udp_dport = rte_be_to_cpu_16(spec->hdr.dst_port & 12176 mask->hdr.dst_port); 12177 } 12178 return (!udp_dport || udp_dport == MLX5_UDP_PORT_VXLAN); 12179 } 12180 12181 static const struct mlx5_flow_expand_node * 12182 mlx5_flow_expand_rss_adjust_node(const struct rte_flow_item *pattern, 12183 unsigned int item_idx, 12184 const struct mlx5_flow_expand_node graph[], 12185 const struct mlx5_flow_expand_node *node) 12186 { 12187 const struct rte_flow_item *item = pattern + item_idx, *prev_item; 12188 12189 if (item->type == RTE_FLOW_ITEM_TYPE_VXLAN && 12190 node != NULL && 12191 node->type == RTE_FLOW_ITEM_TYPE_VXLAN) { 12192 /* 12193 * The expansion node is VXLAN and it is also the last 12194 * expandable item in the pattern, so need to continue 12195 * expansion of the inner tunnel. 12196 */ 12197 MLX5_ASSERT(item_idx > 0); 12198 prev_item = pattern + item_idx - 1; 12199 MLX5_ASSERT(prev_item->type == RTE_FLOW_ITEM_TYPE_UDP); 12200 if (mlx5_flow_is_std_vxlan_port(prev_item)) 12201 return &graph[MLX5_EXPANSION_STD_VXLAN]; 12202 return &graph[MLX5_EXPANSION_L3_VXLAN]; 12203 } 12204 return node; 12205 } 12206 12207 /* Map of Verbs to Flow priority with 8 Verbs priorities. */ 12208 static const uint32_t priority_map_3[][MLX5_PRIORITY_MAP_MAX] = { 12209 { 0, 1, 2 }, { 2, 3, 4 }, { 5, 6, 7 }, 12210 }; 12211 12212 /* Map of Verbs to Flow priority with 16 Verbs priorities. */ 12213 static const uint32_t priority_map_5[][MLX5_PRIORITY_MAP_MAX] = { 12214 { 0, 1, 2 }, { 3, 4, 5 }, { 6, 7, 8 }, 12215 { 9, 10, 11 }, { 12, 13, 14 }, 12216 }; 12217 12218 /** 12219 * Discover the number of available flow priorities. 12220 * 12221 * @param dev 12222 * Ethernet device. 12223 * 12224 * @return 12225 * On success, number of available flow priorities. 12226 * On failure, a negative errno-style code and rte_errno is set. 12227 */ 12228 int 12229 mlx5_flow_discover_priorities(struct rte_eth_dev *dev) 12230 { 12231 static const uint16_t vprio[] = {8, 16}; 12232 const struct mlx5_priv *priv = dev->data->dev_private; 12233 const struct mlx5_flow_driver_ops *fops; 12234 enum mlx5_flow_drv_type type; 12235 int ret; 12236 12237 type = mlx5_flow_os_get_type(); 12238 if (type == MLX5_FLOW_TYPE_MAX) { 12239 type = MLX5_FLOW_TYPE_VERBS; 12240 if (priv->sh->cdev->config.devx && priv->sh->config.dv_flow_en) 12241 type = MLX5_FLOW_TYPE_DV; 12242 } 12243 fops = flow_get_drv_ops(type); 12244 if (fops->discover_priorities == NULL) { 12245 DRV_LOG(ERR, "Priority discovery not supported"); 12246 rte_errno = ENOTSUP; 12247 return -rte_errno; 12248 } 12249 ret = fops->discover_priorities(dev, vprio, RTE_DIM(vprio)); 12250 if (ret < 0) 12251 return ret; 12252 switch (ret) { 12253 case 8: 12254 ret = RTE_DIM(priority_map_3); 12255 break; 12256 case 16: 12257 ret = RTE_DIM(priority_map_5); 12258 break; 12259 default: 12260 rte_errno = ENOTSUP; 12261 DRV_LOG(ERR, 12262 "port %u maximum priority: %d expected 8/16", 12263 dev->data->port_id, ret); 12264 return -rte_errno; 12265 } 12266 DRV_LOG(INFO, "port %u supported flow priorities:" 12267 " 0-%d for ingress or egress root table," 12268 " 0-%d for non-root table or transfer root table.", 12269 dev->data->port_id, ret - 2, 12270 MLX5_NON_ROOT_FLOW_MAX_PRIO - 1); 12271 return ret; 12272 } 12273 12274 /** 12275 * Adjust flow priority based on the highest layer and the request priority. 12276 * 12277 * @param[in] dev 12278 * Pointer to the Ethernet device structure. 12279 * @param[in] priority 12280 * The rule base priority. 12281 * @param[in] subpriority 12282 * The priority based on the items. 12283 * 12284 * @return 12285 * The new priority. 12286 */ 12287 uint32_t 12288 mlx5_flow_adjust_priority(struct rte_eth_dev *dev, int32_t priority, 12289 uint32_t subpriority) 12290 { 12291 uint32_t res = 0; 12292 struct mlx5_priv *priv = dev->data->dev_private; 12293 12294 switch (priv->sh->flow_max_priority) { 12295 case RTE_DIM(priority_map_3): 12296 res = priority_map_3[priority][subpriority]; 12297 break; 12298 case RTE_DIM(priority_map_5): 12299 res = priority_map_5[priority][subpriority]; 12300 break; 12301 } 12302 return res; 12303 } 12304 12305 /** 12306 * Get the priority for sending traffic to kernel table. 12307 * 12308 * @param[in] dev 12309 * Pointer to the Ethernet device structure. 12310 * 12311 * @return 12312 * On success: the value of priority for sending traffic to kernel table 12313 * On failure: -1 12314 */ 12315 uint32_t 12316 mlx5_get_send_to_kernel_priority(struct rte_eth_dev *dev) 12317 { 12318 struct mlx5_priv *priv = dev->data->dev_private; 12319 uint32_t res; 12320 12321 switch (priv->sh->flow_max_priority) { 12322 case RTE_DIM(priority_map_5): 12323 res = 15; 12324 break; 12325 case RTE_DIM(priority_map_3): 12326 res = 7; 12327 break; 12328 default: 12329 DRV_LOG(ERR, 12330 "port %u maximum priority: %d expected 8/16", 12331 dev->data->port_id, priv->sh->flow_max_priority); 12332 res = (uint32_t)-1; 12333 } 12334 return res; 12335 } 12336 12337 /** 12338 * Get the E-Switch Manager vport id. 12339 * 12340 * @param[in] dev 12341 * Pointer to the Ethernet device structure. 12342 * 12343 * @return 12344 * The vport id. 12345 */ 12346 int16_t mlx5_flow_get_esw_manager_vport_id(struct rte_eth_dev *dev) 12347 { 12348 struct mlx5_priv *priv = dev->data->dev_private; 12349 struct mlx5_common_device *cdev = priv->sh->cdev; 12350 12351 /* New FW exposes E-Switch Manager vport ID, can use it directly. */ 12352 if (cdev->config.hca_attr.esw_mgr_vport_id_valid) 12353 return (int16_t)cdev->config.hca_attr.esw_mgr_vport_id; 12354 12355 if (priv->pci_dev == NULL) 12356 return 0; 12357 switch (priv->pci_dev->id.device_id) { 12358 case PCI_DEVICE_ID_MELLANOX_BLUEFIELD: 12359 case PCI_DEVICE_ID_MELLANOX_BLUEFIELD2: 12360 case PCI_DEVICE_ID_MELLANOX_BLUEFIELD3: 12361 /* 12362 * In old FW which doesn't expose the E-Switch Manager vport ID in the capability, 12363 * only the BF embedded CPUs control the E-Switch Manager port. Hence, 12364 * ECPF vport ID is selected and not the host port (0) in any BF case. 12365 */ 12366 return (int16_t)MLX5_ECPF_VPORT_ID; 12367 default: 12368 return MLX5_PF_VPORT_ID; 12369 } 12370 } 12371 12372 /** 12373 * Parse item to get the vport id. 12374 * 12375 * @param[in] dev 12376 * Pointer to the Ethernet device structure. 12377 * @param[in] item 12378 * The src port id match item. 12379 * @param[out] vport_id 12380 * Pointer to put the vport id. 12381 * @param[out] all_ports 12382 * Indicate if the item matches all ports. 12383 * @param[out] error 12384 * Pointer to error structure. 12385 * 12386 * @return 12387 * 0 on success, a negative errno value otherwise and rte_errno is set. 12388 */ 12389 int mlx5_flow_get_item_vport_id(struct rte_eth_dev *dev, 12390 const struct rte_flow_item *item, 12391 uint16_t *vport_id, 12392 bool *all_ports, 12393 struct rte_flow_error *error) 12394 { 12395 struct mlx5_priv *port_priv; 12396 const struct rte_flow_item_port_id *pid_v = NULL; 12397 const struct rte_flow_item_ethdev *dev_v = NULL; 12398 uint32_t esw_mgr_port; 12399 uint32_t src_port; 12400 12401 if (all_ports) 12402 *all_ports = false; 12403 switch (item->type) { 12404 case RTE_FLOW_ITEM_TYPE_PORT_ID: 12405 pid_v = item->spec; 12406 if (!pid_v) 12407 return 0; 12408 src_port = pid_v->id; 12409 esw_mgr_port = MLX5_PORT_ESW_MGR; 12410 break; 12411 case RTE_FLOW_ITEM_TYPE_REPRESENTED_PORT: 12412 dev_v = item->spec; 12413 if (!dev_v) { 12414 if (all_ports) 12415 *all_ports = true; 12416 return 0; 12417 } 12418 src_port = dev_v->port_id; 12419 esw_mgr_port = MLX5_REPRESENTED_PORT_ESW_MGR; 12420 break; 12421 case RTE_FLOW_ITEM_TYPE_PORT_REPRESENTOR: 12422 src_port = MLX5_REPRESENTED_PORT_ESW_MGR; 12423 esw_mgr_port = MLX5_REPRESENTED_PORT_ESW_MGR; 12424 break; 12425 default: 12426 return rte_flow_error_set(error, EINVAL, RTE_FLOW_ERROR_TYPE_ITEM_SPEC, 12427 NULL, "Incorrect item type."); 12428 } 12429 if (src_port == esw_mgr_port) { 12430 *vport_id = mlx5_flow_get_esw_manager_vport_id(dev); 12431 } else { 12432 port_priv = mlx5_port_to_eswitch_info(src_port, false); 12433 if (!port_priv) 12434 return rte_flow_error_set(error, EINVAL, RTE_FLOW_ERROR_TYPE_ITEM_SPEC, 12435 NULL, "Failed to get port info."); 12436 *vport_id = port_priv->representor_id; 12437 } 12438 12439 return 0; 12440 } 12441 12442 int 12443 mlx5_flow_pick_transfer_proxy(struct rte_eth_dev *dev, 12444 uint16_t *proxy_port_id, 12445 struct rte_flow_error *error) 12446 { 12447 const struct mlx5_priv *priv = dev->data->dev_private; 12448 uint16_t port_id; 12449 12450 if (!priv->sh->config.dv_esw_en) 12451 return rte_flow_error_set(error, EINVAL, 12452 RTE_FLOW_ERROR_TYPE_UNSPECIFIED, 12453 NULL, 12454 "unable to provide a proxy port" 12455 " without E-Switch configured"); 12456 if (!priv->master && !priv->representor) 12457 return rte_flow_error_set(error, EINVAL, 12458 RTE_FLOW_ERROR_TYPE_UNSPECIFIED, 12459 NULL, 12460 "unable to provide a proxy port" 12461 " for port which is not a master" 12462 " or a representor port"); 12463 if (priv->master) { 12464 *proxy_port_id = dev->data->port_id; 12465 return 0; 12466 } 12467 MLX5_ETH_FOREACH_DEV(port_id, dev->device) { 12468 const struct rte_eth_dev *port_dev = &rte_eth_devices[port_id]; 12469 const struct mlx5_priv *port_priv = port_dev->data->dev_private; 12470 12471 if (port_priv->master && 12472 port_priv->domain_id == priv->domain_id) { 12473 *proxy_port_id = port_id; 12474 return 0; 12475 } 12476 } 12477 return rte_flow_error_set(error, ENODEV, 12478 RTE_FLOW_ERROR_TYPE_UNSPECIFIED, 12479 NULL, "unable to find a proxy port"); 12480 } 12481