1 /* SPDX-License-Identifier: BSD-3-Clause 2 * Copyright 2016 6WIND S.A. 3 * Copyright 2016 Mellanox Technologies, Ltd 4 */ 5 6 #include <netinet/in.h> 7 #include <sys/queue.h> 8 #include <stdalign.h> 9 #include <stdint.h> 10 #include <string.h> 11 #include <stdbool.h> 12 13 #include <rte_common.h> 14 #include <rte_ether.h> 15 #include <rte_ethdev_driver.h> 16 #include <rte_eal_paging.h> 17 #include <rte_flow.h> 18 #include <rte_cycles.h> 19 #include <rte_flow_driver.h> 20 #include <rte_malloc.h> 21 #include <rte_ip.h> 22 23 #include <mlx5_glue.h> 24 #include <mlx5_devx_cmds.h> 25 #include <mlx5_prm.h> 26 #include <mlx5_malloc.h> 27 28 #include "mlx5_defs.h" 29 #include "mlx5.h" 30 #include "mlx5_flow.h" 31 #include "mlx5_flow_os.h" 32 #include "mlx5_rxtx.h" 33 #include "mlx5_common_os.h" 34 #include "rte_pmd_mlx5.h" 35 36 struct tunnel_default_miss_ctx { 37 uint16_t *queue; 38 __extension__ 39 union { 40 struct rte_flow_action_rss action_rss; 41 struct rte_flow_action_queue miss_queue; 42 struct rte_flow_action_jump miss_jump; 43 uint8_t raw[0]; 44 }; 45 }; 46 47 static int 48 flow_tunnel_add_default_miss(struct rte_eth_dev *dev, 49 struct rte_flow *flow, 50 const struct rte_flow_attr *attr, 51 const struct rte_flow_action *app_actions, 52 uint32_t flow_idx, 53 struct tunnel_default_miss_ctx *ctx, 54 struct rte_flow_error *error); 55 static struct mlx5_flow_tunnel * 56 mlx5_find_tunnel_id(struct rte_eth_dev *dev, uint32_t id); 57 static void 58 mlx5_flow_tunnel_free(struct rte_eth_dev *dev, struct mlx5_flow_tunnel *tunnel); 59 static uint32_t 60 tunnel_flow_group_to_flow_table(struct rte_eth_dev *dev, 61 const struct mlx5_flow_tunnel *tunnel, 62 uint32_t group, uint32_t *table, 63 struct rte_flow_error *error); 64 65 static struct mlx5_flow_workspace *mlx5_flow_push_thread_workspace(void); 66 static void mlx5_flow_pop_thread_workspace(void); 67 68 69 /** Device flow drivers. */ 70 extern const struct mlx5_flow_driver_ops mlx5_flow_verbs_drv_ops; 71 72 const struct mlx5_flow_driver_ops mlx5_flow_null_drv_ops; 73 74 const struct mlx5_flow_driver_ops *flow_drv_ops[] = { 75 [MLX5_FLOW_TYPE_MIN] = &mlx5_flow_null_drv_ops, 76 #if defined(HAVE_IBV_FLOW_DV_SUPPORT) || !defined(HAVE_INFINIBAND_VERBS_H) 77 [MLX5_FLOW_TYPE_DV] = &mlx5_flow_dv_drv_ops, 78 #endif 79 [MLX5_FLOW_TYPE_VERBS] = &mlx5_flow_verbs_drv_ops, 80 [MLX5_FLOW_TYPE_MAX] = &mlx5_flow_null_drv_ops 81 }; 82 83 /** Helper macro to build input graph for mlx5_flow_expand_rss(). */ 84 #define MLX5_FLOW_EXPAND_RSS_NEXT(...) \ 85 (const int []){ \ 86 __VA_ARGS__, 0, \ 87 } 88 89 /** Node object of input graph for mlx5_flow_expand_rss(). */ 90 struct mlx5_flow_expand_node { 91 const int *const next; 92 /**< 93 * List of next node indexes. Index 0 is interpreted as a terminator. 94 */ 95 const enum rte_flow_item_type type; 96 /**< Pattern item type of current node. */ 97 uint64_t rss_types; 98 /**< 99 * RSS types bit-field associated with this node 100 * (see ETH_RSS_* definitions). 101 */ 102 }; 103 104 /** Object returned by mlx5_flow_expand_rss(). */ 105 struct mlx5_flow_expand_rss { 106 uint32_t entries; 107 /**< Number of entries @p patterns and @p priorities. */ 108 struct { 109 struct rte_flow_item *pattern; /**< Expanded pattern array. */ 110 uint32_t priority; /**< Priority offset for each expansion. */ 111 } entry[]; 112 }; 113 114 static enum rte_flow_item_type 115 mlx5_flow_expand_rss_item_complete(const struct rte_flow_item *item) 116 { 117 enum rte_flow_item_type ret = RTE_FLOW_ITEM_TYPE_VOID; 118 uint16_t ether_type = 0; 119 uint16_t ether_type_m; 120 uint8_t ip_next_proto = 0; 121 uint8_t ip_next_proto_m; 122 123 if (item == NULL || item->spec == NULL) 124 return ret; 125 switch (item->type) { 126 case RTE_FLOW_ITEM_TYPE_ETH: 127 if (item->mask) 128 ether_type_m = ((const struct rte_flow_item_eth *) 129 (item->mask))->type; 130 else 131 ether_type_m = rte_flow_item_eth_mask.type; 132 if (ether_type_m != RTE_BE16(0xFFFF)) 133 break; 134 ether_type = ((const struct rte_flow_item_eth *) 135 (item->spec))->type; 136 if (rte_be_to_cpu_16(ether_type) == RTE_ETHER_TYPE_IPV4) 137 ret = RTE_FLOW_ITEM_TYPE_IPV4; 138 else if (rte_be_to_cpu_16(ether_type) == RTE_ETHER_TYPE_IPV6) 139 ret = RTE_FLOW_ITEM_TYPE_IPV6; 140 else if (rte_be_to_cpu_16(ether_type) == RTE_ETHER_TYPE_VLAN) 141 ret = RTE_FLOW_ITEM_TYPE_VLAN; 142 else 143 ret = RTE_FLOW_ITEM_TYPE_END; 144 break; 145 case RTE_FLOW_ITEM_TYPE_VLAN: 146 if (item->mask) 147 ether_type_m = ((const struct rte_flow_item_vlan *) 148 (item->mask))->inner_type; 149 else 150 ether_type_m = rte_flow_item_vlan_mask.inner_type; 151 if (ether_type_m != RTE_BE16(0xFFFF)) 152 break; 153 ether_type = ((const struct rte_flow_item_vlan *) 154 (item->spec))->inner_type; 155 if (rte_be_to_cpu_16(ether_type) == RTE_ETHER_TYPE_IPV4) 156 ret = RTE_FLOW_ITEM_TYPE_IPV4; 157 else if (rte_be_to_cpu_16(ether_type) == RTE_ETHER_TYPE_IPV6) 158 ret = RTE_FLOW_ITEM_TYPE_IPV6; 159 else if (rte_be_to_cpu_16(ether_type) == RTE_ETHER_TYPE_VLAN) 160 ret = RTE_FLOW_ITEM_TYPE_VLAN; 161 else 162 ret = RTE_FLOW_ITEM_TYPE_END; 163 break; 164 case RTE_FLOW_ITEM_TYPE_IPV4: 165 if (item->mask) 166 ip_next_proto_m = ((const struct rte_flow_item_ipv4 *) 167 (item->mask))->hdr.next_proto_id; 168 else 169 ip_next_proto_m = 170 rte_flow_item_ipv4_mask.hdr.next_proto_id; 171 if (ip_next_proto_m != 0xFF) 172 break; 173 ip_next_proto = ((const struct rte_flow_item_ipv4 *) 174 (item->spec))->hdr.next_proto_id; 175 if (ip_next_proto == IPPROTO_UDP) 176 ret = RTE_FLOW_ITEM_TYPE_UDP; 177 else if (ip_next_proto == IPPROTO_TCP) 178 ret = RTE_FLOW_ITEM_TYPE_TCP; 179 else if (ip_next_proto == IPPROTO_IP) 180 ret = RTE_FLOW_ITEM_TYPE_IPV4; 181 else if (ip_next_proto == IPPROTO_IPV6) 182 ret = RTE_FLOW_ITEM_TYPE_IPV6; 183 else 184 ret = RTE_FLOW_ITEM_TYPE_END; 185 break; 186 case RTE_FLOW_ITEM_TYPE_IPV6: 187 if (item->mask) 188 ip_next_proto_m = ((const struct rte_flow_item_ipv6 *) 189 (item->mask))->hdr.proto; 190 else 191 ip_next_proto_m = 192 rte_flow_item_ipv6_mask.hdr.proto; 193 if (ip_next_proto_m != 0xFF) 194 break; 195 ip_next_proto = ((const struct rte_flow_item_ipv6 *) 196 (item->spec))->hdr.proto; 197 if (ip_next_proto == IPPROTO_UDP) 198 ret = RTE_FLOW_ITEM_TYPE_UDP; 199 else if (ip_next_proto == IPPROTO_TCP) 200 ret = RTE_FLOW_ITEM_TYPE_TCP; 201 else if (ip_next_proto == IPPROTO_IP) 202 ret = RTE_FLOW_ITEM_TYPE_IPV4; 203 else if (ip_next_proto == IPPROTO_IPV6) 204 ret = RTE_FLOW_ITEM_TYPE_IPV6; 205 else 206 ret = RTE_FLOW_ITEM_TYPE_END; 207 break; 208 default: 209 ret = RTE_FLOW_ITEM_TYPE_VOID; 210 break; 211 } 212 return ret; 213 } 214 215 #define MLX5_RSS_EXP_ELT_N 8 216 217 /** 218 * Expand RSS flows into several possible flows according to the RSS hash 219 * fields requested and the driver capabilities. 220 * 221 * @param[out] buf 222 * Buffer to store the result expansion. 223 * @param[in] size 224 * Buffer size in bytes. If 0, @p buf can be NULL. 225 * @param[in] pattern 226 * User flow pattern. 227 * @param[in] types 228 * RSS types to expand (see ETH_RSS_* definitions). 229 * @param[in] graph 230 * Input graph to expand @p pattern according to @p types. 231 * @param[in] graph_root_index 232 * Index of root node in @p graph, typically 0. 233 * 234 * @return 235 * A positive value representing the size of @p buf in bytes regardless of 236 * @p size on success, a negative errno value otherwise and rte_errno is 237 * set, the following errors are defined: 238 * 239 * -E2BIG: graph-depth @p graph is too deep. 240 */ 241 static int 242 mlx5_flow_expand_rss(struct mlx5_flow_expand_rss *buf, size_t size, 243 const struct rte_flow_item *pattern, uint64_t types, 244 const struct mlx5_flow_expand_node graph[], 245 int graph_root_index) 246 { 247 const struct rte_flow_item *item; 248 const struct mlx5_flow_expand_node *node = &graph[graph_root_index]; 249 const int *next_node; 250 const int *stack[MLX5_RSS_EXP_ELT_N]; 251 int stack_pos = 0; 252 struct rte_flow_item flow_items[MLX5_RSS_EXP_ELT_N]; 253 unsigned int i; 254 size_t lsize; 255 size_t user_pattern_size = 0; 256 void *addr = NULL; 257 const struct mlx5_flow_expand_node *next = NULL; 258 struct rte_flow_item missed_item; 259 int missed = 0; 260 int elt = 0; 261 const struct rte_flow_item *last_item = NULL; 262 263 memset(&missed_item, 0, sizeof(missed_item)); 264 lsize = offsetof(struct mlx5_flow_expand_rss, entry) + 265 MLX5_RSS_EXP_ELT_N * sizeof(buf->entry[0]); 266 if (lsize <= size) { 267 buf->entry[0].priority = 0; 268 buf->entry[0].pattern = (void *)&buf->entry[MLX5_RSS_EXP_ELT_N]; 269 buf->entries = 0; 270 addr = buf->entry[0].pattern; 271 } 272 for (item = pattern; item->type != RTE_FLOW_ITEM_TYPE_END; item++) { 273 if (item->type != RTE_FLOW_ITEM_TYPE_VOID) 274 last_item = item; 275 for (i = 0; node->next && node->next[i]; ++i) { 276 next = &graph[node->next[i]]; 277 if (next->type == item->type) 278 break; 279 } 280 if (next) 281 node = next; 282 user_pattern_size += sizeof(*item); 283 } 284 user_pattern_size += sizeof(*item); /* Handle END item. */ 285 lsize += user_pattern_size; 286 /* Copy the user pattern in the first entry of the buffer. */ 287 if (lsize <= size) { 288 rte_memcpy(addr, pattern, user_pattern_size); 289 addr = (void *)(((uintptr_t)addr) + user_pattern_size); 290 buf->entries = 1; 291 } 292 /* Start expanding. */ 293 memset(flow_items, 0, sizeof(flow_items)); 294 user_pattern_size -= sizeof(*item); 295 /* 296 * Check if the last valid item has spec set, need complete pattern, 297 * and the pattern can be used for expansion. 298 */ 299 missed_item.type = mlx5_flow_expand_rss_item_complete(last_item); 300 if (missed_item.type == RTE_FLOW_ITEM_TYPE_END) { 301 /* Item type END indicates expansion is not required. */ 302 return lsize; 303 } 304 if (missed_item.type != RTE_FLOW_ITEM_TYPE_VOID) { 305 next = NULL; 306 missed = 1; 307 for (i = 0; node->next && node->next[i]; ++i) { 308 next = &graph[node->next[i]]; 309 if (next->type == missed_item.type) { 310 flow_items[0].type = missed_item.type; 311 flow_items[1].type = RTE_FLOW_ITEM_TYPE_END; 312 break; 313 } 314 next = NULL; 315 } 316 } 317 if (next && missed) { 318 elt = 2; /* missed item + item end. */ 319 node = next; 320 lsize += elt * sizeof(*item) + user_pattern_size; 321 if ((node->rss_types & types) && lsize <= size) { 322 buf->entry[buf->entries].priority = 1; 323 buf->entry[buf->entries].pattern = addr; 324 buf->entries++; 325 rte_memcpy(addr, buf->entry[0].pattern, 326 user_pattern_size); 327 addr = (void *)(((uintptr_t)addr) + user_pattern_size); 328 rte_memcpy(addr, flow_items, elt * sizeof(*item)); 329 addr = (void *)(((uintptr_t)addr) + 330 elt * sizeof(*item)); 331 } 332 } 333 memset(flow_items, 0, sizeof(flow_items)); 334 next_node = node->next; 335 stack[stack_pos] = next_node; 336 node = next_node ? &graph[*next_node] : NULL; 337 while (node) { 338 flow_items[stack_pos].type = node->type; 339 if (node->rss_types & types) { 340 /* 341 * compute the number of items to copy from the 342 * expansion and copy it. 343 * When the stack_pos is 0, there are 1 element in it, 344 * plus the addition END item. 345 */ 346 elt = stack_pos + 2; 347 flow_items[stack_pos + 1].type = RTE_FLOW_ITEM_TYPE_END; 348 lsize += elt * sizeof(*item) + user_pattern_size; 349 if (lsize <= size) { 350 size_t n = elt * sizeof(*item); 351 352 buf->entry[buf->entries].priority = 353 stack_pos + 1 + missed; 354 buf->entry[buf->entries].pattern = addr; 355 buf->entries++; 356 rte_memcpy(addr, buf->entry[0].pattern, 357 user_pattern_size); 358 addr = (void *)(((uintptr_t)addr) + 359 user_pattern_size); 360 rte_memcpy(addr, &missed_item, 361 missed * sizeof(*item)); 362 addr = (void *)(((uintptr_t)addr) + 363 missed * sizeof(*item)); 364 rte_memcpy(addr, flow_items, n); 365 addr = (void *)(((uintptr_t)addr) + n); 366 } 367 } 368 /* Go deeper. */ 369 if (node->next) { 370 next_node = node->next; 371 if (stack_pos++ == MLX5_RSS_EXP_ELT_N) { 372 rte_errno = E2BIG; 373 return -rte_errno; 374 } 375 stack[stack_pos] = next_node; 376 } else if (*(next_node + 1)) { 377 /* Follow up with the next possibility. */ 378 ++next_node; 379 } else { 380 /* Move to the next path. */ 381 if (stack_pos) 382 next_node = stack[--stack_pos]; 383 next_node++; 384 stack[stack_pos] = next_node; 385 } 386 node = *next_node ? &graph[*next_node] : NULL; 387 }; 388 /* no expanded flows but we have missed item, create one rule for it */ 389 if (buf->entries == 1 && missed != 0) { 390 elt = 2; 391 lsize += elt * sizeof(*item) + user_pattern_size; 392 if (lsize <= size) { 393 buf->entry[buf->entries].priority = 1; 394 buf->entry[buf->entries].pattern = addr; 395 buf->entries++; 396 flow_items[0].type = missed_item.type; 397 flow_items[1].type = RTE_FLOW_ITEM_TYPE_END; 398 rte_memcpy(addr, buf->entry[0].pattern, 399 user_pattern_size); 400 addr = (void *)(((uintptr_t)addr) + user_pattern_size); 401 rte_memcpy(addr, flow_items, elt * sizeof(*item)); 402 } 403 } 404 return lsize; 405 } 406 407 enum mlx5_expansion { 408 MLX5_EXPANSION_ROOT, 409 MLX5_EXPANSION_ROOT_OUTER, 410 MLX5_EXPANSION_ROOT_ETH_VLAN, 411 MLX5_EXPANSION_ROOT_OUTER_ETH_VLAN, 412 MLX5_EXPANSION_OUTER_ETH, 413 MLX5_EXPANSION_OUTER_ETH_VLAN, 414 MLX5_EXPANSION_OUTER_VLAN, 415 MLX5_EXPANSION_OUTER_IPV4, 416 MLX5_EXPANSION_OUTER_IPV4_UDP, 417 MLX5_EXPANSION_OUTER_IPV4_TCP, 418 MLX5_EXPANSION_OUTER_IPV6, 419 MLX5_EXPANSION_OUTER_IPV6_UDP, 420 MLX5_EXPANSION_OUTER_IPV6_TCP, 421 MLX5_EXPANSION_VXLAN, 422 MLX5_EXPANSION_VXLAN_GPE, 423 MLX5_EXPANSION_GRE, 424 MLX5_EXPANSION_MPLS, 425 MLX5_EXPANSION_ETH, 426 MLX5_EXPANSION_ETH_VLAN, 427 MLX5_EXPANSION_VLAN, 428 MLX5_EXPANSION_IPV4, 429 MLX5_EXPANSION_IPV4_UDP, 430 MLX5_EXPANSION_IPV4_TCP, 431 MLX5_EXPANSION_IPV6, 432 MLX5_EXPANSION_IPV6_UDP, 433 MLX5_EXPANSION_IPV6_TCP, 434 }; 435 436 /** Supported expansion of items. */ 437 static const struct mlx5_flow_expand_node mlx5_support_expansion[] = { 438 [MLX5_EXPANSION_ROOT] = { 439 .next = MLX5_FLOW_EXPAND_RSS_NEXT(MLX5_EXPANSION_ETH, 440 MLX5_EXPANSION_IPV4, 441 MLX5_EXPANSION_IPV6), 442 .type = RTE_FLOW_ITEM_TYPE_END, 443 }, 444 [MLX5_EXPANSION_ROOT_OUTER] = { 445 .next = MLX5_FLOW_EXPAND_RSS_NEXT(MLX5_EXPANSION_OUTER_ETH, 446 MLX5_EXPANSION_OUTER_IPV4, 447 MLX5_EXPANSION_OUTER_IPV6), 448 .type = RTE_FLOW_ITEM_TYPE_END, 449 }, 450 [MLX5_EXPANSION_ROOT_ETH_VLAN] = { 451 .next = MLX5_FLOW_EXPAND_RSS_NEXT(MLX5_EXPANSION_ETH_VLAN), 452 .type = RTE_FLOW_ITEM_TYPE_END, 453 }, 454 [MLX5_EXPANSION_ROOT_OUTER_ETH_VLAN] = { 455 .next = MLX5_FLOW_EXPAND_RSS_NEXT 456 (MLX5_EXPANSION_OUTER_ETH_VLAN), 457 .type = RTE_FLOW_ITEM_TYPE_END, 458 }, 459 [MLX5_EXPANSION_OUTER_ETH] = { 460 .next = MLX5_FLOW_EXPAND_RSS_NEXT(MLX5_EXPANSION_OUTER_IPV4, 461 MLX5_EXPANSION_OUTER_IPV6, 462 MLX5_EXPANSION_MPLS), 463 .type = RTE_FLOW_ITEM_TYPE_ETH, 464 .rss_types = 0, 465 }, 466 [MLX5_EXPANSION_OUTER_ETH_VLAN] = { 467 .next = MLX5_FLOW_EXPAND_RSS_NEXT(MLX5_EXPANSION_OUTER_VLAN), 468 .type = RTE_FLOW_ITEM_TYPE_ETH, 469 .rss_types = 0, 470 }, 471 [MLX5_EXPANSION_OUTER_VLAN] = { 472 .next = MLX5_FLOW_EXPAND_RSS_NEXT(MLX5_EXPANSION_OUTER_IPV4, 473 MLX5_EXPANSION_OUTER_IPV6), 474 .type = RTE_FLOW_ITEM_TYPE_VLAN, 475 }, 476 [MLX5_EXPANSION_OUTER_IPV4] = { 477 .next = MLX5_FLOW_EXPAND_RSS_NEXT 478 (MLX5_EXPANSION_OUTER_IPV4_UDP, 479 MLX5_EXPANSION_OUTER_IPV4_TCP, 480 MLX5_EXPANSION_GRE, 481 MLX5_EXPANSION_IPV4, 482 MLX5_EXPANSION_IPV6), 483 .type = RTE_FLOW_ITEM_TYPE_IPV4, 484 .rss_types = ETH_RSS_IPV4 | ETH_RSS_FRAG_IPV4 | 485 ETH_RSS_NONFRAG_IPV4_OTHER, 486 }, 487 [MLX5_EXPANSION_OUTER_IPV4_UDP] = { 488 .next = MLX5_FLOW_EXPAND_RSS_NEXT(MLX5_EXPANSION_VXLAN, 489 MLX5_EXPANSION_VXLAN_GPE), 490 .type = RTE_FLOW_ITEM_TYPE_UDP, 491 .rss_types = ETH_RSS_NONFRAG_IPV4_UDP, 492 }, 493 [MLX5_EXPANSION_OUTER_IPV4_TCP] = { 494 .type = RTE_FLOW_ITEM_TYPE_TCP, 495 .rss_types = ETH_RSS_NONFRAG_IPV4_TCP, 496 }, 497 [MLX5_EXPANSION_OUTER_IPV6] = { 498 .next = MLX5_FLOW_EXPAND_RSS_NEXT 499 (MLX5_EXPANSION_OUTER_IPV6_UDP, 500 MLX5_EXPANSION_OUTER_IPV6_TCP, 501 MLX5_EXPANSION_IPV4, 502 MLX5_EXPANSION_IPV6), 503 .type = RTE_FLOW_ITEM_TYPE_IPV6, 504 .rss_types = ETH_RSS_IPV6 | ETH_RSS_FRAG_IPV6 | 505 ETH_RSS_NONFRAG_IPV6_OTHER, 506 }, 507 [MLX5_EXPANSION_OUTER_IPV6_UDP] = { 508 .next = MLX5_FLOW_EXPAND_RSS_NEXT(MLX5_EXPANSION_VXLAN, 509 MLX5_EXPANSION_VXLAN_GPE), 510 .type = RTE_FLOW_ITEM_TYPE_UDP, 511 .rss_types = ETH_RSS_NONFRAG_IPV6_UDP, 512 }, 513 [MLX5_EXPANSION_OUTER_IPV6_TCP] = { 514 .type = RTE_FLOW_ITEM_TYPE_TCP, 515 .rss_types = ETH_RSS_NONFRAG_IPV6_TCP, 516 }, 517 [MLX5_EXPANSION_VXLAN] = { 518 .next = MLX5_FLOW_EXPAND_RSS_NEXT(MLX5_EXPANSION_ETH, 519 MLX5_EXPANSION_IPV4, 520 MLX5_EXPANSION_IPV6), 521 .type = RTE_FLOW_ITEM_TYPE_VXLAN, 522 }, 523 [MLX5_EXPANSION_VXLAN_GPE] = { 524 .next = MLX5_FLOW_EXPAND_RSS_NEXT(MLX5_EXPANSION_ETH, 525 MLX5_EXPANSION_IPV4, 526 MLX5_EXPANSION_IPV6), 527 .type = RTE_FLOW_ITEM_TYPE_VXLAN_GPE, 528 }, 529 [MLX5_EXPANSION_GRE] = { 530 .next = MLX5_FLOW_EXPAND_RSS_NEXT(MLX5_EXPANSION_IPV4), 531 .type = RTE_FLOW_ITEM_TYPE_GRE, 532 }, 533 [MLX5_EXPANSION_MPLS] = { 534 .next = MLX5_FLOW_EXPAND_RSS_NEXT(MLX5_EXPANSION_IPV4, 535 MLX5_EXPANSION_IPV6), 536 .type = RTE_FLOW_ITEM_TYPE_MPLS, 537 }, 538 [MLX5_EXPANSION_ETH] = { 539 .next = MLX5_FLOW_EXPAND_RSS_NEXT(MLX5_EXPANSION_IPV4, 540 MLX5_EXPANSION_IPV6), 541 .type = RTE_FLOW_ITEM_TYPE_ETH, 542 }, 543 [MLX5_EXPANSION_ETH_VLAN] = { 544 .next = MLX5_FLOW_EXPAND_RSS_NEXT(MLX5_EXPANSION_VLAN), 545 .type = RTE_FLOW_ITEM_TYPE_ETH, 546 }, 547 [MLX5_EXPANSION_VLAN] = { 548 .next = MLX5_FLOW_EXPAND_RSS_NEXT(MLX5_EXPANSION_IPV4, 549 MLX5_EXPANSION_IPV6), 550 .type = RTE_FLOW_ITEM_TYPE_VLAN, 551 }, 552 [MLX5_EXPANSION_IPV4] = { 553 .next = MLX5_FLOW_EXPAND_RSS_NEXT(MLX5_EXPANSION_IPV4_UDP, 554 MLX5_EXPANSION_IPV4_TCP), 555 .type = RTE_FLOW_ITEM_TYPE_IPV4, 556 .rss_types = ETH_RSS_IPV4 | ETH_RSS_FRAG_IPV4 | 557 ETH_RSS_NONFRAG_IPV4_OTHER, 558 }, 559 [MLX5_EXPANSION_IPV4_UDP] = { 560 .type = RTE_FLOW_ITEM_TYPE_UDP, 561 .rss_types = ETH_RSS_NONFRAG_IPV4_UDP, 562 }, 563 [MLX5_EXPANSION_IPV4_TCP] = { 564 .type = RTE_FLOW_ITEM_TYPE_TCP, 565 .rss_types = ETH_RSS_NONFRAG_IPV4_TCP, 566 }, 567 [MLX5_EXPANSION_IPV6] = { 568 .next = MLX5_FLOW_EXPAND_RSS_NEXT(MLX5_EXPANSION_IPV6_UDP, 569 MLX5_EXPANSION_IPV6_TCP), 570 .type = RTE_FLOW_ITEM_TYPE_IPV6, 571 .rss_types = ETH_RSS_IPV6 | ETH_RSS_FRAG_IPV6 | 572 ETH_RSS_NONFRAG_IPV6_OTHER, 573 }, 574 [MLX5_EXPANSION_IPV6_UDP] = { 575 .type = RTE_FLOW_ITEM_TYPE_UDP, 576 .rss_types = ETH_RSS_NONFRAG_IPV6_UDP, 577 }, 578 [MLX5_EXPANSION_IPV6_TCP] = { 579 .type = RTE_FLOW_ITEM_TYPE_TCP, 580 .rss_types = ETH_RSS_NONFRAG_IPV6_TCP, 581 }, 582 }; 583 584 static struct rte_flow_shared_action * 585 mlx5_shared_action_create(struct rte_eth_dev *dev, 586 const struct rte_flow_shared_action_conf *conf, 587 const struct rte_flow_action *action, 588 struct rte_flow_error *error); 589 static int mlx5_shared_action_destroy 590 (struct rte_eth_dev *dev, 591 struct rte_flow_shared_action *shared_action, 592 struct rte_flow_error *error); 593 static int mlx5_shared_action_update 594 (struct rte_eth_dev *dev, 595 struct rte_flow_shared_action *shared_action, 596 const struct rte_flow_action *action, 597 struct rte_flow_error *error); 598 static int mlx5_shared_action_query 599 (struct rte_eth_dev *dev, 600 const struct rte_flow_shared_action *action, 601 void *data, 602 struct rte_flow_error *error); 603 static int 604 mlx5_flow_tunnel_decap_set(struct rte_eth_dev *dev, 605 struct rte_flow_tunnel *app_tunnel, 606 struct rte_flow_action **actions, 607 uint32_t *num_of_actions, 608 struct rte_flow_error *error); 609 static int 610 mlx5_flow_tunnel_match(struct rte_eth_dev *dev, 611 struct rte_flow_tunnel *app_tunnel, 612 struct rte_flow_item **items, 613 uint32_t *num_of_items, 614 struct rte_flow_error *error); 615 static int 616 mlx5_flow_tunnel_item_release(struct rte_eth_dev *dev, 617 struct rte_flow_item *pmd_items, 618 uint32_t num_items, struct rte_flow_error *err); 619 static int 620 mlx5_flow_tunnel_action_release(struct rte_eth_dev *dev, 621 struct rte_flow_action *pmd_actions, 622 uint32_t num_actions, 623 struct rte_flow_error *err); 624 static int 625 mlx5_flow_tunnel_get_restore_info(struct rte_eth_dev *dev, 626 struct rte_mbuf *m, 627 struct rte_flow_restore_info *info, 628 struct rte_flow_error *err); 629 630 static const struct rte_flow_ops mlx5_flow_ops = { 631 .validate = mlx5_flow_validate, 632 .create = mlx5_flow_create, 633 .destroy = mlx5_flow_destroy, 634 .flush = mlx5_flow_flush, 635 .isolate = mlx5_flow_isolate, 636 .query = mlx5_flow_query, 637 .dev_dump = mlx5_flow_dev_dump, 638 .get_aged_flows = mlx5_flow_get_aged_flows, 639 .shared_action_create = mlx5_shared_action_create, 640 .shared_action_destroy = mlx5_shared_action_destroy, 641 .shared_action_update = mlx5_shared_action_update, 642 .shared_action_query = mlx5_shared_action_query, 643 .tunnel_decap_set = mlx5_flow_tunnel_decap_set, 644 .tunnel_match = mlx5_flow_tunnel_match, 645 .tunnel_action_decap_release = mlx5_flow_tunnel_action_release, 646 .tunnel_item_release = mlx5_flow_tunnel_item_release, 647 .get_restore_info = mlx5_flow_tunnel_get_restore_info, 648 }; 649 650 /* Tunnel information. */ 651 struct mlx5_flow_tunnel_info { 652 uint64_t tunnel; /**< Tunnel bit (see MLX5_FLOW_*). */ 653 uint32_t ptype; /**< Tunnel Ptype (see RTE_PTYPE_*). */ 654 }; 655 656 static struct mlx5_flow_tunnel_info tunnels_info[] = { 657 { 658 .tunnel = MLX5_FLOW_LAYER_VXLAN, 659 .ptype = RTE_PTYPE_TUNNEL_VXLAN | RTE_PTYPE_L4_UDP, 660 }, 661 { 662 .tunnel = MLX5_FLOW_LAYER_GENEVE, 663 .ptype = RTE_PTYPE_TUNNEL_GENEVE | RTE_PTYPE_L4_UDP, 664 }, 665 { 666 .tunnel = MLX5_FLOW_LAYER_VXLAN_GPE, 667 .ptype = RTE_PTYPE_TUNNEL_VXLAN_GPE | RTE_PTYPE_L4_UDP, 668 }, 669 { 670 .tunnel = MLX5_FLOW_LAYER_GRE, 671 .ptype = RTE_PTYPE_TUNNEL_GRE, 672 }, 673 { 674 .tunnel = MLX5_FLOW_LAYER_MPLS | MLX5_FLOW_LAYER_OUTER_L4_UDP, 675 .ptype = RTE_PTYPE_TUNNEL_MPLS_IN_UDP | RTE_PTYPE_L4_UDP, 676 }, 677 { 678 .tunnel = MLX5_FLOW_LAYER_MPLS, 679 .ptype = RTE_PTYPE_TUNNEL_MPLS_IN_GRE, 680 }, 681 { 682 .tunnel = MLX5_FLOW_LAYER_NVGRE, 683 .ptype = RTE_PTYPE_TUNNEL_NVGRE, 684 }, 685 { 686 .tunnel = MLX5_FLOW_LAYER_IPIP, 687 .ptype = RTE_PTYPE_TUNNEL_IP, 688 }, 689 { 690 .tunnel = MLX5_FLOW_LAYER_IPV6_ENCAP, 691 .ptype = RTE_PTYPE_TUNNEL_IP, 692 }, 693 { 694 .tunnel = MLX5_FLOW_LAYER_GTP, 695 .ptype = RTE_PTYPE_TUNNEL_GTPU, 696 }, 697 }; 698 699 700 701 /** 702 * Translate tag ID to register. 703 * 704 * @param[in] dev 705 * Pointer to the Ethernet device structure. 706 * @param[in] feature 707 * The feature that request the register. 708 * @param[in] id 709 * The request register ID. 710 * @param[out] error 711 * Error description in case of any. 712 * 713 * @return 714 * The request register on success, a negative errno 715 * value otherwise and rte_errno is set. 716 */ 717 int 718 mlx5_flow_get_reg_id(struct rte_eth_dev *dev, 719 enum mlx5_feature_name feature, 720 uint32_t id, 721 struct rte_flow_error *error) 722 { 723 struct mlx5_priv *priv = dev->data->dev_private; 724 struct mlx5_dev_config *config = &priv->config; 725 enum modify_reg start_reg; 726 bool skip_mtr_reg = false; 727 728 switch (feature) { 729 case MLX5_HAIRPIN_RX: 730 return REG_B; 731 case MLX5_HAIRPIN_TX: 732 return REG_A; 733 case MLX5_METADATA_RX: 734 switch (config->dv_xmeta_en) { 735 case MLX5_XMETA_MODE_LEGACY: 736 return REG_B; 737 case MLX5_XMETA_MODE_META16: 738 return REG_C_0; 739 case MLX5_XMETA_MODE_META32: 740 return REG_C_1; 741 } 742 break; 743 case MLX5_METADATA_TX: 744 return REG_A; 745 case MLX5_METADATA_FDB: 746 switch (config->dv_xmeta_en) { 747 case MLX5_XMETA_MODE_LEGACY: 748 return REG_NON; 749 case MLX5_XMETA_MODE_META16: 750 return REG_C_0; 751 case MLX5_XMETA_MODE_META32: 752 return REG_C_1; 753 } 754 break; 755 case MLX5_FLOW_MARK: 756 switch (config->dv_xmeta_en) { 757 case MLX5_XMETA_MODE_LEGACY: 758 return REG_NON; 759 case MLX5_XMETA_MODE_META16: 760 return REG_C_1; 761 case MLX5_XMETA_MODE_META32: 762 return REG_C_0; 763 } 764 break; 765 case MLX5_MTR_SFX: 766 /* 767 * If meter color and flow match share one register, flow match 768 * should use the meter color register for match. 769 */ 770 if (priv->mtr_reg_share) 771 return priv->mtr_color_reg; 772 else 773 return priv->mtr_color_reg != REG_C_2 ? REG_C_2 : 774 REG_C_3; 775 case MLX5_MTR_COLOR: 776 case MLX5_ASO_FLOW_HIT: /* Both features use the same REG_C. */ 777 MLX5_ASSERT(priv->mtr_color_reg != REG_NON); 778 return priv->mtr_color_reg; 779 case MLX5_COPY_MARK: 780 /* 781 * Metadata COPY_MARK register using is in meter suffix sub 782 * flow while with meter. It's safe to share the same register. 783 */ 784 return priv->mtr_color_reg != REG_C_2 ? REG_C_2 : REG_C_3; 785 case MLX5_APP_TAG: 786 /* 787 * If meter is enable, it will engage the register for color 788 * match and flow match. If meter color match is not using the 789 * REG_C_2, need to skip the REG_C_x be used by meter color 790 * match. 791 * If meter is disable, free to use all available registers. 792 */ 793 start_reg = priv->mtr_color_reg != REG_C_2 ? REG_C_2 : 794 (priv->mtr_reg_share ? REG_C_3 : REG_C_4); 795 skip_mtr_reg = !!(priv->mtr_en && start_reg == REG_C_2); 796 if (id > (uint32_t)(REG_C_7 - start_reg)) 797 return rte_flow_error_set(error, EINVAL, 798 RTE_FLOW_ERROR_TYPE_ITEM, 799 NULL, "invalid tag id"); 800 if (config->flow_mreg_c[id + start_reg - REG_C_0] == REG_NON) 801 return rte_flow_error_set(error, ENOTSUP, 802 RTE_FLOW_ERROR_TYPE_ITEM, 803 NULL, "unsupported tag id"); 804 /* 805 * This case means meter is using the REG_C_x great than 2. 806 * Take care not to conflict with meter color REG_C_x. 807 * If the available index REG_C_y >= REG_C_x, skip the 808 * color register. 809 */ 810 if (skip_mtr_reg && config->flow_mreg_c 811 [id + start_reg - REG_C_0] >= priv->mtr_color_reg) { 812 if (id >= (uint32_t)(REG_C_7 - start_reg)) 813 return rte_flow_error_set(error, EINVAL, 814 RTE_FLOW_ERROR_TYPE_ITEM, 815 NULL, "invalid tag id"); 816 if (config->flow_mreg_c 817 [id + 1 + start_reg - REG_C_0] != REG_NON) 818 return config->flow_mreg_c 819 [id + 1 + start_reg - REG_C_0]; 820 return rte_flow_error_set(error, ENOTSUP, 821 RTE_FLOW_ERROR_TYPE_ITEM, 822 NULL, "unsupported tag id"); 823 } 824 return config->flow_mreg_c[id + start_reg - REG_C_0]; 825 } 826 MLX5_ASSERT(false); 827 return rte_flow_error_set(error, EINVAL, 828 RTE_FLOW_ERROR_TYPE_UNSPECIFIED, 829 NULL, "invalid feature name"); 830 } 831 832 /** 833 * Check extensive flow metadata register support. 834 * 835 * @param dev 836 * Pointer to rte_eth_dev structure. 837 * 838 * @return 839 * True if device supports extensive flow metadata register, otherwise false. 840 */ 841 bool 842 mlx5_flow_ext_mreg_supported(struct rte_eth_dev *dev) 843 { 844 struct mlx5_priv *priv = dev->data->dev_private; 845 struct mlx5_dev_config *config = &priv->config; 846 847 /* 848 * Having available reg_c can be regarded inclusively as supporting 849 * extensive flow metadata register, which could mean, 850 * - metadata register copy action by modify header. 851 * - 16 modify header actions is supported. 852 * - reg_c's are preserved across different domain (FDB and NIC) on 853 * packet loopback by flow lookup miss. 854 */ 855 return config->flow_mreg_c[2] != REG_NON; 856 } 857 858 /** 859 * Verify the @p item specifications (spec, last, mask) are compatible with the 860 * NIC capabilities. 861 * 862 * @param[in] item 863 * Item specification. 864 * @param[in] mask 865 * @p item->mask or flow default bit-masks. 866 * @param[in] nic_mask 867 * Bit-masks covering supported fields by the NIC to compare with user mask. 868 * @param[in] size 869 * Bit-masks size in bytes. 870 * @param[in] range_accepted 871 * True if range of values is accepted for specific fields, false otherwise. 872 * @param[out] error 873 * Pointer to error structure. 874 * 875 * @return 876 * 0 on success, a negative errno value otherwise and rte_errno is set. 877 */ 878 int 879 mlx5_flow_item_acceptable(const struct rte_flow_item *item, 880 const uint8_t *mask, 881 const uint8_t *nic_mask, 882 unsigned int size, 883 bool range_accepted, 884 struct rte_flow_error *error) 885 { 886 unsigned int i; 887 888 MLX5_ASSERT(nic_mask); 889 for (i = 0; i < size; ++i) 890 if ((nic_mask[i] | mask[i]) != nic_mask[i]) 891 return rte_flow_error_set(error, ENOTSUP, 892 RTE_FLOW_ERROR_TYPE_ITEM, 893 item, 894 "mask enables non supported" 895 " bits"); 896 if (!item->spec && (item->mask || item->last)) 897 return rte_flow_error_set(error, EINVAL, 898 RTE_FLOW_ERROR_TYPE_ITEM, item, 899 "mask/last without a spec is not" 900 " supported"); 901 if (item->spec && item->last && !range_accepted) { 902 uint8_t spec[size]; 903 uint8_t last[size]; 904 unsigned int i; 905 int ret; 906 907 for (i = 0; i < size; ++i) { 908 spec[i] = ((const uint8_t *)item->spec)[i] & mask[i]; 909 last[i] = ((const uint8_t *)item->last)[i] & mask[i]; 910 } 911 ret = memcmp(spec, last, size); 912 if (ret != 0) 913 return rte_flow_error_set(error, EINVAL, 914 RTE_FLOW_ERROR_TYPE_ITEM, 915 item, 916 "range is not valid"); 917 } 918 return 0; 919 } 920 921 /** 922 * Adjust the hash fields according to the @p flow information. 923 * 924 * @param[in] dev_flow. 925 * Pointer to the mlx5_flow. 926 * @param[in] tunnel 927 * 1 when the hash field is for a tunnel item. 928 * @param[in] layer_types 929 * ETH_RSS_* types. 930 * @param[in] hash_fields 931 * Item hash fields. 932 * 933 * @return 934 * The hash fields that should be used. 935 */ 936 uint64_t 937 mlx5_flow_hashfields_adjust(struct mlx5_flow_rss_desc *rss_desc, 938 int tunnel __rte_unused, uint64_t layer_types, 939 uint64_t hash_fields) 940 { 941 #ifdef HAVE_IBV_DEVICE_TUNNEL_SUPPORT 942 int rss_request_inner = rss_desc->level >= 2; 943 944 /* Check RSS hash level for tunnel. */ 945 if (tunnel && rss_request_inner) 946 hash_fields |= IBV_RX_HASH_INNER; 947 else if (tunnel || rss_request_inner) 948 return 0; 949 #endif 950 /* Check if requested layer matches RSS hash fields. */ 951 if (!(rss_desc->types & layer_types)) 952 return 0; 953 return hash_fields; 954 } 955 956 /** 957 * Lookup and set the ptype in the data Rx part. A single Ptype can be used, 958 * if several tunnel rules are used on this queue, the tunnel ptype will be 959 * cleared. 960 * 961 * @param rxq_ctrl 962 * Rx queue to update. 963 */ 964 static void 965 flow_rxq_tunnel_ptype_update(struct mlx5_rxq_ctrl *rxq_ctrl) 966 { 967 unsigned int i; 968 uint32_t tunnel_ptype = 0; 969 970 /* Look up for the ptype to use. */ 971 for (i = 0; i != MLX5_FLOW_TUNNEL; ++i) { 972 if (!rxq_ctrl->flow_tunnels_n[i]) 973 continue; 974 if (!tunnel_ptype) { 975 tunnel_ptype = tunnels_info[i].ptype; 976 } else { 977 tunnel_ptype = 0; 978 break; 979 } 980 } 981 rxq_ctrl->rxq.tunnel = tunnel_ptype; 982 } 983 984 /** 985 * Set the Rx queue flags (Mark/Flag and Tunnel Ptypes) according to the devive 986 * flow. 987 * 988 * @param[in] dev 989 * Pointer to the Ethernet device structure. 990 * @param[in] dev_handle 991 * Pointer to device flow handle structure. 992 */ 993 static void 994 flow_drv_rxq_flags_set(struct rte_eth_dev *dev, 995 struct mlx5_flow_handle *dev_handle) 996 { 997 struct mlx5_priv *priv = dev->data->dev_private; 998 const int mark = dev_handle->mark; 999 const int tunnel = !!(dev_handle->layers & MLX5_FLOW_LAYER_TUNNEL); 1000 struct mlx5_ind_table_obj *ind_tbl = NULL; 1001 unsigned int i; 1002 1003 if (dev_handle->fate_action == MLX5_FLOW_FATE_QUEUE) { 1004 struct mlx5_hrxq *hrxq; 1005 1006 hrxq = mlx5_ipool_get(priv->sh->ipool[MLX5_IPOOL_HRXQ], 1007 dev_handle->rix_hrxq); 1008 if (hrxq) 1009 ind_tbl = hrxq->ind_table; 1010 } else if (dev_handle->fate_action == MLX5_FLOW_FATE_SHARED_RSS) { 1011 struct mlx5_shared_action_rss *shared_rss; 1012 1013 shared_rss = mlx5_ipool_get 1014 (priv->sh->ipool[MLX5_IPOOL_RSS_SHARED_ACTIONS], 1015 dev_handle->rix_srss); 1016 if (shared_rss) 1017 ind_tbl = shared_rss->ind_tbl; 1018 } 1019 if (!ind_tbl) 1020 return; 1021 for (i = 0; i != ind_tbl->queues_n; ++i) { 1022 int idx = ind_tbl->queues[i]; 1023 struct mlx5_rxq_ctrl *rxq_ctrl = 1024 container_of((*priv->rxqs)[idx], 1025 struct mlx5_rxq_ctrl, rxq); 1026 1027 /* 1028 * To support metadata register copy on Tx loopback, 1029 * this must be always enabled (metadata may arive 1030 * from other port - not from local flows only. 1031 */ 1032 if (priv->config.dv_flow_en && 1033 priv->config.dv_xmeta_en != MLX5_XMETA_MODE_LEGACY && 1034 mlx5_flow_ext_mreg_supported(dev)) { 1035 rxq_ctrl->rxq.mark = 1; 1036 rxq_ctrl->flow_mark_n = 1; 1037 } else if (mark) { 1038 rxq_ctrl->rxq.mark = 1; 1039 rxq_ctrl->flow_mark_n++; 1040 } 1041 if (tunnel) { 1042 unsigned int j; 1043 1044 /* Increase the counter matching the flow. */ 1045 for (j = 0; j != MLX5_FLOW_TUNNEL; ++j) { 1046 if ((tunnels_info[j].tunnel & 1047 dev_handle->layers) == 1048 tunnels_info[j].tunnel) { 1049 rxq_ctrl->flow_tunnels_n[j]++; 1050 break; 1051 } 1052 } 1053 flow_rxq_tunnel_ptype_update(rxq_ctrl); 1054 } 1055 } 1056 } 1057 1058 /** 1059 * Set the Rx queue flags (Mark/Flag and Tunnel Ptypes) for a flow 1060 * 1061 * @param[in] dev 1062 * Pointer to the Ethernet device structure. 1063 * @param[in] flow 1064 * Pointer to flow structure. 1065 */ 1066 static void 1067 flow_rxq_flags_set(struct rte_eth_dev *dev, struct rte_flow *flow) 1068 { 1069 struct mlx5_priv *priv = dev->data->dev_private; 1070 uint32_t handle_idx; 1071 struct mlx5_flow_handle *dev_handle; 1072 1073 SILIST_FOREACH(priv->sh->ipool[MLX5_IPOOL_MLX5_FLOW], flow->dev_handles, 1074 handle_idx, dev_handle, next) 1075 flow_drv_rxq_flags_set(dev, dev_handle); 1076 } 1077 1078 /** 1079 * Clear the Rx queue flags (Mark/Flag and Tunnel Ptype) associated with the 1080 * device flow if no other flow uses it with the same kind of request. 1081 * 1082 * @param dev 1083 * Pointer to Ethernet device. 1084 * @param[in] dev_handle 1085 * Pointer to the device flow handle structure. 1086 */ 1087 static void 1088 flow_drv_rxq_flags_trim(struct rte_eth_dev *dev, 1089 struct mlx5_flow_handle *dev_handle) 1090 { 1091 struct mlx5_priv *priv = dev->data->dev_private; 1092 const int mark = dev_handle->mark; 1093 const int tunnel = !!(dev_handle->layers & MLX5_FLOW_LAYER_TUNNEL); 1094 struct mlx5_ind_table_obj *ind_tbl = NULL; 1095 unsigned int i; 1096 1097 if (dev_handle->fate_action == MLX5_FLOW_FATE_QUEUE) { 1098 struct mlx5_hrxq *hrxq; 1099 1100 hrxq = mlx5_ipool_get(priv->sh->ipool[MLX5_IPOOL_HRXQ], 1101 dev_handle->rix_hrxq); 1102 if (hrxq) 1103 ind_tbl = hrxq->ind_table; 1104 } else if (dev_handle->fate_action == MLX5_FLOW_FATE_SHARED_RSS) { 1105 struct mlx5_shared_action_rss *shared_rss; 1106 1107 shared_rss = mlx5_ipool_get 1108 (priv->sh->ipool[MLX5_IPOOL_RSS_SHARED_ACTIONS], 1109 dev_handle->rix_srss); 1110 if (shared_rss) 1111 ind_tbl = shared_rss->ind_tbl; 1112 } 1113 if (!ind_tbl) 1114 return; 1115 MLX5_ASSERT(dev->data->dev_started); 1116 for (i = 0; i != ind_tbl->queues_n; ++i) { 1117 int idx = ind_tbl->queues[i]; 1118 struct mlx5_rxq_ctrl *rxq_ctrl = 1119 container_of((*priv->rxqs)[idx], 1120 struct mlx5_rxq_ctrl, rxq); 1121 1122 if (priv->config.dv_flow_en && 1123 priv->config.dv_xmeta_en != MLX5_XMETA_MODE_LEGACY && 1124 mlx5_flow_ext_mreg_supported(dev)) { 1125 rxq_ctrl->rxq.mark = 1; 1126 rxq_ctrl->flow_mark_n = 1; 1127 } else if (mark) { 1128 rxq_ctrl->flow_mark_n--; 1129 rxq_ctrl->rxq.mark = !!rxq_ctrl->flow_mark_n; 1130 } 1131 if (tunnel) { 1132 unsigned int j; 1133 1134 /* Decrease the counter matching the flow. */ 1135 for (j = 0; j != MLX5_FLOW_TUNNEL; ++j) { 1136 if ((tunnels_info[j].tunnel & 1137 dev_handle->layers) == 1138 tunnels_info[j].tunnel) { 1139 rxq_ctrl->flow_tunnels_n[j]--; 1140 break; 1141 } 1142 } 1143 flow_rxq_tunnel_ptype_update(rxq_ctrl); 1144 } 1145 } 1146 } 1147 1148 /** 1149 * Clear the Rx queue flags (Mark/Flag and Tunnel Ptype) associated with the 1150 * @p flow if no other flow uses it with the same kind of request. 1151 * 1152 * @param dev 1153 * Pointer to Ethernet device. 1154 * @param[in] flow 1155 * Pointer to the flow. 1156 */ 1157 static void 1158 flow_rxq_flags_trim(struct rte_eth_dev *dev, struct rte_flow *flow) 1159 { 1160 struct mlx5_priv *priv = dev->data->dev_private; 1161 uint32_t handle_idx; 1162 struct mlx5_flow_handle *dev_handle; 1163 1164 SILIST_FOREACH(priv->sh->ipool[MLX5_IPOOL_MLX5_FLOW], flow->dev_handles, 1165 handle_idx, dev_handle, next) 1166 flow_drv_rxq_flags_trim(dev, dev_handle); 1167 } 1168 1169 /** 1170 * Clear the Mark/Flag and Tunnel ptype information in all Rx queues. 1171 * 1172 * @param dev 1173 * Pointer to Ethernet device. 1174 */ 1175 static void 1176 flow_rxq_flags_clear(struct rte_eth_dev *dev) 1177 { 1178 struct mlx5_priv *priv = dev->data->dev_private; 1179 unsigned int i; 1180 1181 for (i = 0; i != priv->rxqs_n; ++i) { 1182 struct mlx5_rxq_ctrl *rxq_ctrl; 1183 unsigned int j; 1184 1185 if (!(*priv->rxqs)[i]) 1186 continue; 1187 rxq_ctrl = container_of((*priv->rxqs)[i], 1188 struct mlx5_rxq_ctrl, rxq); 1189 rxq_ctrl->flow_mark_n = 0; 1190 rxq_ctrl->rxq.mark = 0; 1191 for (j = 0; j != MLX5_FLOW_TUNNEL; ++j) 1192 rxq_ctrl->flow_tunnels_n[j] = 0; 1193 rxq_ctrl->rxq.tunnel = 0; 1194 } 1195 } 1196 1197 /** 1198 * Set the Rx queue dynamic metadata (mask and offset) for a flow 1199 * 1200 * @param[in] dev 1201 * Pointer to the Ethernet device structure. 1202 */ 1203 void 1204 mlx5_flow_rxq_dynf_metadata_set(struct rte_eth_dev *dev) 1205 { 1206 struct mlx5_priv *priv = dev->data->dev_private; 1207 struct mlx5_rxq_data *data; 1208 unsigned int i; 1209 1210 for (i = 0; i != priv->rxqs_n; ++i) { 1211 if (!(*priv->rxqs)[i]) 1212 continue; 1213 data = (*priv->rxqs)[i]; 1214 if (!rte_flow_dynf_metadata_avail()) { 1215 data->dynf_meta = 0; 1216 data->flow_meta_mask = 0; 1217 data->flow_meta_offset = -1; 1218 } else { 1219 data->dynf_meta = 1; 1220 data->flow_meta_mask = rte_flow_dynf_metadata_mask; 1221 data->flow_meta_offset = rte_flow_dynf_metadata_offs; 1222 } 1223 } 1224 } 1225 1226 /* 1227 * return a pointer to the desired action in the list of actions. 1228 * 1229 * @param[in] actions 1230 * The list of actions to search the action in. 1231 * @param[in] action 1232 * The action to find. 1233 * 1234 * @return 1235 * Pointer to the action in the list, if found. NULL otherwise. 1236 */ 1237 const struct rte_flow_action * 1238 mlx5_flow_find_action(const struct rte_flow_action *actions, 1239 enum rte_flow_action_type action) 1240 { 1241 if (actions == NULL) 1242 return NULL; 1243 for (; actions->type != RTE_FLOW_ACTION_TYPE_END; actions++) 1244 if (actions->type == action) 1245 return actions; 1246 return NULL; 1247 } 1248 1249 /* 1250 * Validate the flag action. 1251 * 1252 * @param[in] action_flags 1253 * Bit-fields that holds the actions detected until now. 1254 * @param[in] attr 1255 * Attributes of flow that includes this action. 1256 * @param[out] error 1257 * Pointer to error structure. 1258 * 1259 * @return 1260 * 0 on success, a negative errno value otherwise and rte_errno is set. 1261 */ 1262 int 1263 mlx5_flow_validate_action_flag(uint64_t action_flags, 1264 const struct rte_flow_attr *attr, 1265 struct rte_flow_error *error) 1266 { 1267 if (action_flags & MLX5_FLOW_ACTION_MARK) 1268 return rte_flow_error_set(error, EINVAL, 1269 RTE_FLOW_ERROR_TYPE_ACTION, NULL, 1270 "can't mark and flag in same flow"); 1271 if (action_flags & MLX5_FLOW_ACTION_FLAG) 1272 return rte_flow_error_set(error, EINVAL, 1273 RTE_FLOW_ERROR_TYPE_ACTION, NULL, 1274 "can't have 2 flag" 1275 " actions in same flow"); 1276 if (attr->egress) 1277 return rte_flow_error_set(error, ENOTSUP, 1278 RTE_FLOW_ERROR_TYPE_ATTR_EGRESS, NULL, 1279 "flag action not supported for " 1280 "egress"); 1281 return 0; 1282 } 1283 1284 /* 1285 * Validate the mark action. 1286 * 1287 * @param[in] action 1288 * Pointer to the queue action. 1289 * @param[in] action_flags 1290 * Bit-fields that holds the actions detected until now. 1291 * @param[in] attr 1292 * Attributes of flow that includes this action. 1293 * @param[out] error 1294 * Pointer to error structure. 1295 * 1296 * @return 1297 * 0 on success, a negative errno value otherwise and rte_errno is set. 1298 */ 1299 int 1300 mlx5_flow_validate_action_mark(const struct rte_flow_action *action, 1301 uint64_t action_flags, 1302 const struct rte_flow_attr *attr, 1303 struct rte_flow_error *error) 1304 { 1305 const struct rte_flow_action_mark *mark = action->conf; 1306 1307 if (!mark) 1308 return rte_flow_error_set(error, EINVAL, 1309 RTE_FLOW_ERROR_TYPE_ACTION, 1310 action, 1311 "configuration cannot be null"); 1312 if (mark->id >= MLX5_FLOW_MARK_MAX) 1313 return rte_flow_error_set(error, EINVAL, 1314 RTE_FLOW_ERROR_TYPE_ACTION_CONF, 1315 &mark->id, 1316 "mark id must in 0 <= id < " 1317 RTE_STR(MLX5_FLOW_MARK_MAX)); 1318 if (action_flags & MLX5_FLOW_ACTION_FLAG) 1319 return rte_flow_error_set(error, EINVAL, 1320 RTE_FLOW_ERROR_TYPE_ACTION, NULL, 1321 "can't flag and mark in same flow"); 1322 if (action_flags & MLX5_FLOW_ACTION_MARK) 1323 return rte_flow_error_set(error, EINVAL, 1324 RTE_FLOW_ERROR_TYPE_ACTION, NULL, 1325 "can't have 2 mark actions in same" 1326 " flow"); 1327 if (attr->egress) 1328 return rte_flow_error_set(error, ENOTSUP, 1329 RTE_FLOW_ERROR_TYPE_ATTR_EGRESS, NULL, 1330 "mark action not supported for " 1331 "egress"); 1332 return 0; 1333 } 1334 1335 /* 1336 * Validate the drop action. 1337 * 1338 * @param[in] action_flags 1339 * Bit-fields that holds the actions detected until now. 1340 * @param[in] attr 1341 * Attributes of flow that includes this action. 1342 * @param[out] error 1343 * Pointer to error structure. 1344 * 1345 * @return 1346 * 0 on success, a negative errno value otherwise and rte_errno is set. 1347 */ 1348 int 1349 mlx5_flow_validate_action_drop(uint64_t action_flags __rte_unused, 1350 const struct rte_flow_attr *attr, 1351 struct rte_flow_error *error) 1352 { 1353 if (attr->egress) 1354 return rte_flow_error_set(error, ENOTSUP, 1355 RTE_FLOW_ERROR_TYPE_ATTR_EGRESS, NULL, 1356 "drop action not supported for " 1357 "egress"); 1358 return 0; 1359 } 1360 1361 /* 1362 * Validate the queue action. 1363 * 1364 * @param[in] action 1365 * Pointer to the queue action. 1366 * @param[in] action_flags 1367 * Bit-fields that holds the actions detected until now. 1368 * @param[in] dev 1369 * Pointer to the Ethernet device structure. 1370 * @param[in] attr 1371 * Attributes of flow that includes this action. 1372 * @param[out] error 1373 * Pointer to error structure. 1374 * 1375 * @return 1376 * 0 on success, a negative errno value otherwise and rte_errno is set. 1377 */ 1378 int 1379 mlx5_flow_validate_action_queue(const struct rte_flow_action *action, 1380 uint64_t action_flags, 1381 struct rte_eth_dev *dev, 1382 const struct rte_flow_attr *attr, 1383 struct rte_flow_error *error) 1384 { 1385 struct mlx5_priv *priv = dev->data->dev_private; 1386 const struct rte_flow_action_queue *queue = action->conf; 1387 1388 if (action_flags & MLX5_FLOW_FATE_ACTIONS) 1389 return rte_flow_error_set(error, EINVAL, 1390 RTE_FLOW_ERROR_TYPE_ACTION, NULL, 1391 "can't have 2 fate actions in" 1392 " same flow"); 1393 if (!priv->rxqs_n) 1394 return rte_flow_error_set(error, EINVAL, 1395 RTE_FLOW_ERROR_TYPE_ACTION_CONF, 1396 NULL, "No Rx queues configured"); 1397 if (queue->index >= priv->rxqs_n) 1398 return rte_flow_error_set(error, EINVAL, 1399 RTE_FLOW_ERROR_TYPE_ACTION_CONF, 1400 &queue->index, 1401 "queue index out of range"); 1402 if (!(*priv->rxqs)[queue->index]) 1403 return rte_flow_error_set(error, EINVAL, 1404 RTE_FLOW_ERROR_TYPE_ACTION_CONF, 1405 &queue->index, 1406 "queue is not configured"); 1407 if (attr->egress) 1408 return rte_flow_error_set(error, ENOTSUP, 1409 RTE_FLOW_ERROR_TYPE_ATTR_EGRESS, NULL, 1410 "queue action not supported for " 1411 "egress"); 1412 return 0; 1413 } 1414 1415 /* 1416 * Validate the rss action. 1417 * 1418 * @param[in] dev 1419 * Pointer to the Ethernet device structure. 1420 * @param[in] action 1421 * Pointer to the queue action. 1422 * @param[out] error 1423 * Pointer to error structure. 1424 * 1425 * @return 1426 * 0 on success, a negative errno value otherwise and rte_errno is set. 1427 */ 1428 int 1429 mlx5_validate_action_rss(struct rte_eth_dev *dev, 1430 const struct rte_flow_action *action, 1431 struct rte_flow_error *error) 1432 { 1433 struct mlx5_priv *priv = dev->data->dev_private; 1434 const struct rte_flow_action_rss *rss = action->conf; 1435 enum mlx5_rxq_type rxq_type = MLX5_RXQ_TYPE_UNDEFINED; 1436 unsigned int i; 1437 1438 if (rss->func != RTE_ETH_HASH_FUNCTION_DEFAULT && 1439 rss->func != RTE_ETH_HASH_FUNCTION_TOEPLITZ) 1440 return rte_flow_error_set(error, ENOTSUP, 1441 RTE_FLOW_ERROR_TYPE_ACTION_CONF, 1442 &rss->func, 1443 "RSS hash function not supported"); 1444 #ifdef HAVE_IBV_DEVICE_TUNNEL_SUPPORT 1445 if (rss->level > 2) 1446 #else 1447 if (rss->level > 1) 1448 #endif 1449 return rte_flow_error_set(error, ENOTSUP, 1450 RTE_FLOW_ERROR_TYPE_ACTION_CONF, 1451 &rss->level, 1452 "tunnel RSS is not supported"); 1453 /* allow RSS key_len 0 in case of NULL (default) RSS key. */ 1454 if (rss->key_len == 0 && rss->key != NULL) 1455 return rte_flow_error_set(error, ENOTSUP, 1456 RTE_FLOW_ERROR_TYPE_ACTION_CONF, 1457 &rss->key_len, 1458 "RSS hash key length 0"); 1459 if (rss->key_len > 0 && rss->key_len < MLX5_RSS_HASH_KEY_LEN) 1460 return rte_flow_error_set(error, ENOTSUP, 1461 RTE_FLOW_ERROR_TYPE_ACTION_CONF, 1462 &rss->key_len, 1463 "RSS hash key too small"); 1464 if (rss->key_len > MLX5_RSS_HASH_KEY_LEN) 1465 return rte_flow_error_set(error, ENOTSUP, 1466 RTE_FLOW_ERROR_TYPE_ACTION_CONF, 1467 &rss->key_len, 1468 "RSS hash key too large"); 1469 if (rss->queue_num > priv->config.ind_table_max_size) 1470 return rte_flow_error_set(error, ENOTSUP, 1471 RTE_FLOW_ERROR_TYPE_ACTION_CONF, 1472 &rss->queue_num, 1473 "number of queues too large"); 1474 if (rss->types & MLX5_RSS_HF_MASK) 1475 return rte_flow_error_set(error, ENOTSUP, 1476 RTE_FLOW_ERROR_TYPE_ACTION_CONF, 1477 &rss->types, 1478 "some RSS protocols are not" 1479 " supported"); 1480 if ((rss->types & (ETH_RSS_L3_SRC_ONLY | ETH_RSS_L3_DST_ONLY)) && 1481 !(rss->types & ETH_RSS_IP)) 1482 return rte_flow_error_set(error, EINVAL, 1483 RTE_FLOW_ERROR_TYPE_ACTION_CONF, NULL, 1484 "L3 partial RSS requested but L3 RSS" 1485 " type not specified"); 1486 if ((rss->types & (ETH_RSS_L4_SRC_ONLY | ETH_RSS_L4_DST_ONLY)) && 1487 !(rss->types & (ETH_RSS_UDP | ETH_RSS_TCP))) 1488 return rte_flow_error_set(error, EINVAL, 1489 RTE_FLOW_ERROR_TYPE_ACTION_CONF, NULL, 1490 "L4 partial RSS requested but L4 RSS" 1491 " type not specified"); 1492 if (!priv->rxqs_n) 1493 return rte_flow_error_set(error, EINVAL, 1494 RTE_FLOW_ERROR_TYPE_ACTION_CONF, 1495 NULL, "No Rx queues configured"); 1496 if (!rss->queue_num) 1497 return rte_flow_error_set(error, EINVAL, 1498 RTE_FLOW_ERROR_TYPE_ACTION_CONF, 1499 NULL, "No queues configured"); 1500 for (i = 0; i != rss->queue_num; ++i) { 1501 struct mlx5_rxq_ctrl *rxq_ctrl; 1502 1503 if (rss->queue[i] >= priv->rxqs_n) 1504 return rte_flow_error_set 1505 (error, EINVAL, 1506 RTE_FLOW_ERROR_TYPE_ACTION_CONF, 1507 &rss->queue[i], "queue index out of range"); 1508 if (!(*priv->rxqs)[rss->queue[i]]) 1509 return rte_flow_error_set 1510 (error, EINVAL, RTE_FLOW_ERROR_TYPE_ACTION_CONF, 1511 &rss->queue[i], "queue is not configured"); 1512 rxq_ctrl = container_of((*priv->rxqs)[rss->queue[i]], 1513 struct mlx5_rxq_ctrl, rxq); 1514 if (i == 0) 1515 rxq_type = rxq_ctrl->type; 1516 if (rxq_type != rxq_ctrl->type) 1517 return rte_flow_error_set 1518 (error, ENOTSUP, RTE_FLOW_ERROR_TYPE_ACTION_CONF, 1519 &rss->queue[i], 1520 "combining hairpin and regular RSS queues is not supported"); 1521 } 1522 return 0; 1523 } 1524 1525 /* 1526 * Validate the rss action. 1527 * 1528 * @param[in] action 1529 * Pointer to the queue action. 1530 * @param[in] action_flags 1531 * Bit-fields that holds the actions detected until now. 1532 * @param[in] dev 1533 * Pointer to the Ethernet device structure. 1534 * @param[in] attr 1535 * Attributes of flow that includes this action. 1536 * @param[in] item_flags 1537 * Items that were detected. 1538 * @param[out] error 1539 * Pointer to error structure. 1540 * 1541 * @return 1542 * 0 on success, a negative errno value otherwise and rte_errno is set. 1543 */ 1544 int 1545 mlx5_flow_validate_action_rss(const struct rte_flow_action *action, 1546 uint64_t action_flags, 1547 struct rte_eth_dev *dev, 1548 const struct rte_flow_attr *attr, 1549 uint64_t item_flags, 1550 struct rte_flow_error *error) 1551 { 1552 const struct rte_flow_action_rss *rss = action->conf; 1553 int tunnel = !!(item_flags & MLX5_FLOW_LAYER_TUNNEL); 1554 int ret; 1555 1556 if (action_flags & MLX5_FLOW_FATE_ACTIONS) 1557 return rte_flow_error_set(error, EINVAL, 1558 RTE_FLOW_ERROR_TYPE_ACTION, NULL, 1559 "can't have 2 fate actions" 1560 " in same flow"); 1561 ret = mlx5_validate_action_rss(dev, action, error); 1562 if (ret) 1563 return ret; 1564 if (attr->egress) 1565 return rte_flow_error_set(error, ENOTSUP, 1566 RTE_FLOW_ERROR_TYPE_ATTR_EGRESS, NULL, 1567 "rss action not supported for " 1568 "egress"); 1569 if (rss->level > 1 && !tunnel) 1570 return rte_flow_error_set(error, EINVAL, 1571 RTE_FLOW_ERROR_TYPE_ACTION_CONF, NULL, 1572 "inner RSS is not supported for " 1573 "non-tunnel flows"); 1574 if ((item_flags & MLX5_FLOW_LAYER_ECPRI) && 1575 !(item_flags & MLX5_FLOW_LAYER_INNER_L4_UDP)) { 1576 return rte_flow_error_set(error, EINVAL, 1577 RTE_FLOW_ERROR_TYPE_ACTION_CONF, NULL, 1578 "RSS on eCPRI is not supported now"); 1579 } 1580 return 0; 1581 } 1582 1583 /* 1584 * Validate the default miss action. 1585 * 1586 * @param[in] action_flags 1587 * Bit-fields that holds the actions detected until now. 1588 * @param[out] error 1589 * Pointer to error structure. 1590 * 1591 * @return 1592 * 0 on success, a negative errno value otherwise and rte_errno is set. 1593 */ 1594 int 1595 mlx5_flow_validate_action_default_miss(uint64_t action_flags, 1596 const struct rte_flow_attr *attr, 1597 struct rte_flow_error *error) 1598 { 1599 if (action_flags & MLX5_FLOW_FATE_ACTIONS) 1600 return rte_flow_error_set(error, EINVAL, 1601 RTE_FLOW_ERROR_TYPE_ACTION, NULL, 1602 "can't have 2 fate actions in" 1603 " same flow"); 1604 if (attr->egress) 1605 return rte_flow_error_set(error, ENOTSUP, 1606 RTE_FLOW_ERROR_TYPE_ATTR_EGRESS, NULL, 1607 "default miss action not supported " 1608 "for egress"); 1609 if (attr->group) 1610 return rte_flow_error_set(error, ENOTSUP, 1611 RTE_FLOW_ERROR_TYPE_ATTR_GROUP, NULL, 1612 "only group 0 is supported"); 1613 if (attr->transfer) 1614 return rte_flow_error_set(error, ENOTSUP, 1615 RTE_FLOW_ERROR_TYPE_ATTR_TRANSFER, 1616 NULL, "transfer is not supported"); 1617 return 0; 1618 } 1619 1620 /* 1621 * Validate the count action. 1622 * 1623 * @param[in] dev 1624 * Pointer to the Ethernet device structure. 1625 * @param[in] attr 1626 * Attributes of flow that includes this action. 1627 * @param[out] error 1628 * Pointer to error structure. 1629 * 1630 * @return 1631 * 0 on success, a negative errno value otherwise and rte_errno is set. 1632 */ 1633 int 1634 mlx5_flow_validate_action_count(struct rte_eth_dev *dev __rte_unused, 1635 const struct rte_flow_attr *attr, 1636 struct rte_flow_error *error) 1637 { 1638 if (attr->egress) 1639 return rte_flow_error_set(error, ENOTSUP, 1640 RTE_FLOW_ERROR_TYPE_ATTR_EGRESS, NULL, 1641 "count action not supported for " 1642 "egress"); 1643 return 0; 1644 } 1645 1646 /** 1647 * Verify the @p attributes will be correctly understood by the NIC and store 1648 * them in the @p flow if everything is correct. 1649 * 1650 * @param[in] dev 1651 * Pointer to the Ethernet device structure. 1652 * @param[in] attributes 1653 * Pointer to flow attributes 1654 * @param[out] error 1655 * Pointer to error structure. 1656 * 1657 * @return 1658 * 0 on success, a negative errno value otherwise and rte_errno is set. 1659 */ 1660 int 1661 mlx5_flow_validate_attributes(struct rte_eth_dev *dev, 1662 const struct rte_flow_attr *attributes, 1663 struct rte_flow_error *error) 1664 { 1665 struct mlx5_priv *priv = dev->data->dev_private; 1666 uint32_t priority_max = priv->config.flow_prio - 1; 1667 1668 if (attributes->group) 1669 return rte_flow_error_set(error, ENOTSUP, 1670 RTE_FLOW_ERROR_TYPE_ATTR_GROUP, 1671 NULL, "groups is not supported"); 1672 if (attributes->priority != MLX5_FLOW_PRIO_RSVD && 1673 attributes->priority >= priority_max) 1674 return rte_flow_error_set(error, ENOTSUP, 1675 RTE_FLOW_ERROR_TYPE_ATTR_PRIORITY, 1676 NULL, "priority out of range"); 1677 if (attributes->egress) 1678 return rte_flow_error_set(error, ENOTSUP, 1679 RTE_FLOW_ERROR_TYPE_ATTR_EGRESS, NULL, 1680 "egress is not supported"); 1681 if (attributes->transfer && !priv->config.dv_esw_en) 1682 return rte_flow_error_set(error, ENOTSUP, 1683 RTE_FLOW_ERROR_TYPE_ATTR_TRANSFER, 1684 NULL, "transfer is not supported"); 1685 if (!attributes->ingress) 1686 return rte_flow_error_set(error, EINVAL, 1687 RTE_FLOW_ERROR_TYPE_ATTR_INGRESS, 1688 NULL, 1689 "ingress attribute is mandatory"); 1690 return 0; 1691 } 1692 1693 /** 1694 * Validate ICMP6 item. 1695 * 1696 * @param[in] item 1697 * Item specification. 1698 * @param[in] item_flags 1699 * Bit-fields that holds the items detected until now. 1700 * @param[in] ext_vlan_sup 1701 * Whether extended VLAN features are supported or not. 1702 * @param[out] error 1703 * Pointer to error structure. 1704 * 1705 * @return 1706 * 0 on success, a negative errno value otherwise and rte_errno is set. 1707 */ 1708 int 1709 mlx5_flow_validate_item_icmp6(const struct rte_flow_item *item, 1710 uint64_t item_flags, 1711 uint8_t target_protocol, 1712 struct rte_flow_error *error) 1713 { 1714 const struct rte_flow_item_icmp6 *mask = item->mask; 1715 const int tunnel = !!(item_flags & MLX5_FLOW_LAYER_TUNNEL); 1716 const uint64_t l3m = tunnel ? MLX5_FLOW_LAYER_INNER_L3_IPV6 : 1717 MLX5_FLOW_LAYER_OUTER_L3_IPV6; 1718 const uint64_t l4m = tunnel ? MLX5_FLOW_LAYER_INNER_L4 : 1719 MLX5_FLOW_LAYER_OUTER_L4; 1720 int ret; 1721 1722 if (target_protocol != 0xFF && target_protocol != IPPROTO_ICMPV6) 1723 return rte_flow_error_set(error, EINVAL, 1724 RTE_FLOW_ERROR_TYPE_ITEM, item, 1725 "protocol filtering not compatible" 1726 " with ICMP6 layer"); 1727 if (!(item_flags & l3m)) 1728 return rte_flow_error_set(error, EINVAL, 1729 RTE_FLOW_ERROR_TYPE_ITEM, item, 1730 "IPv6 is mandatory to filter on" 1731 " ICMP6"); 1732 if (item_flags & l4m) 1733 return rte_flow_error_set(error, EINVAL, 1734 RTE_FLOW_ERROR_TYPE_ITEM, item, 1735 "multiple L4 layers not supported"); 1736 if (!mask) 1737 mask = &rte_flow_item_icmp6_mask; 1738 ret = mlx5_flow_item_acceptable 1739 (item, (const uint8_t *)mask, 1740 (const uint8_t *)&rte_flow_item_icmp6_mask, 1741 sizeof(struct rte_flow_item_icmp6), 1742 MLX5_ITEM_RANGE_NOT_ACCEPTED, error); 1743 if (ret < 0) 1744 return ret; 1745 return 0; 1746 } 1747 1748 /** 1749 * Validate ICMP item. 1750 * 1751 * @param[in] item 1752 * Item specification. 1753 * @param[in] item_flags 1754 * Bit-fields that holds the items detected until now. 1755 * @param[out] error 1756 * Pointer to error structure. 1757 * 1758 * @return 1759 * 0 on success, a negative errno value otherwise and rte_errno is set. 1760 */ 1761 int 1762 mlx5_flow_validate_item_icmp(const struct rte_flow_item *item, 1763 uint64_t item_flags, 1764 uint8_t target_protocol, 1765 struct rte_flow_error *error) 1766 { 1767 const struct rte_flow_item_icmp *mask = item->mask; 1768 const struct rte_flow_item_icmp nic_mask = { 1769 .hdr.icmp_type = 0xff, 1770 .hdr.icmp_code = 0xff, 1771 .hdr.icmp_ident = RTE_BE16(0xffff), 1772 .hdr.icmp_seq_nb = RTE_BE16(0xffff), 1773 }; 1774 const int tunnel = !!(item_flags & MLX5_FLOW_LAYER_TUNNEL); 1775 const uint64_t l3m = tunnel ? MLX5_FLOW_LAYER_INNER_L3_IPV4 : 1776 MLX5_FLOW_LAYER_OUTER_L3_IPV4; 1777 const uint64_t l4m = tunnel ? MLX5_FLOW_LAYER_INNER_L4 : 1778 MLX5_FLOW_LAYER_OUTER_L4; 1779 int ret; 1780 1781 if (target_protocol != 0xFF && target_protocol != IPPROTO_ICMP) 1782 return rte_flow_error_set(error, EINVAL, 1783 RTE_FLOW_ERROR_TYPE_ITEM, item, 1784 "protocol filtering not compatible" 1785 " with ICMP layer"); 1786 if (!(item_flags & l3m)) 1787 return rte_flow_error_set(error, EINVAL, 1788 RTE_FLOW_ERROR_TYPE_ITEM, item, 1789 "IPv4 is mandatory to filter" 1790 " on ICMP"); 1791 if (item_flags & l4m) 1792 return rte_flow_error_set(error, EINVAL, 1793 RTE_FLOW_ERROR_TYPE_ITEM, item, 1794 "multiple L4 layers not supported"); 1795 if (!mask) 1796 mask = &nic_mask; 1797 ret = mlx5_flow_item_acceptable 1798 (item, (const uint8_t *)mask, 1799 (const uint8_t *)&nic_mask, 1800 sizeof(struct rte_flow_item_icmp), 1801 MLX5_ITEM_RANGE_NOT_ACCEPTED, error); 1802 if (ret < 0) 1803 return ret; 1804 return 0; 1805 } 1806 1807 /** 1808 * Validate Ethernet item. 1809 * 1810 * @param[in] item 1811 * Item specification. 1812 * @param[in] item_flags 1813 * Bit-fields that holds the items detected until now. 1814 * @param[out] error 1815 * Pointer to error structure. 1816 * 1817 * @return 1818 * 0 on success, a negative errno value otherwise and rte_errno is set. 1819 */ 1820 int 1821 mlx5_flow_validate_item_eth(const struct rte_flow_item *item, 1822 uint64_t item_flags, bool ext_vlan_sup, 1823 struct rte_flow_error *error) 1824 { 1825 const struct rte_flow_item_eth *mask = item->mask; 1826 const struct rte_flow_item_eth nic_mask = { 1827 .dst.addr_bytes = "\xff\xff\xff\xff\xff\xff", 1828 .src.addr_bytes = "\xff\xff\xff\xff\xff\xff", 1829 .type = RTE_BE16(0xffff), 1830 .has_vlan = ext_vlan_sup ? 1 : 0, 1831 }; 1832 int ret; 1833 int tunnel = !!(item_flags & MLX5_FLOW_LAYER_TUNNEL); 1834 const uint64_t ethm = tunnel ? MLX5_FLOW_LAYER_INNER_L2 : 1835 MLX5_FLOW_LAYER_OUTER_L2; 1836 1837 if (item_flags & ethm) 1838 return rte_flow_error_set(error, ENOTSUP, 1839 RTE_FLOW_ERROR_TYPE_ITEM, item, 1840 "multiple L2 layers not supported"); 1841 if ((!tunnel && (item_flags & MLX5_FLOW_LAYER_OUTER_L3)) || 1842 (tunnel && (item_flags & MLX5_FLOW_LAYER_INNER_L3))) 1843 return rte_flow_error_set(error, EINVAL, 1844 RTE_FLOW_ERROR_TYPE_ITEM, item, 1845 "L2 layer should not follow " 1846 "L3 layers"); 1847 if ((!tunnel && (item_flags & MLX5_FLOW_LAYER_OUTER_VLAN)) || 1848 (tunnel && (item_flags & MLX5_FLOW_LAYER_INNER_VLAN))) 1849 return rte_flow_error_set(error, EINVAL, 1850 RTE_FLOW_ERROR_TYPE_ITEM, item, 1851 "L2 layer should not follow VLAN"); 1852 if (!mask) 1853 mask = &rte_flow_item_eth_mask; 1854 ret = mlx5_flow_item_acceptable(item, (const uint8_t *)mask, 1855 (const uint8_t *)&nic_mask, 1856 sizeof(struct rte_flow_item_eth), 1857 MLX5_ITEM_RANGE_NOT_ACCEPTED, error); 1858 return ret; 1859 } 1860 1861 /** 1862 * Validate VLAN item. 1863 * 1864 * @param[in] item 1865 * Item specification. 1866 * @param[in] item_flags 1867 * Bit-fields that holds the items detected until now. 1868 * @param[in] dev 1869 * Ethernet device flow is being created on. 1870 * @param[out] error 1871 * Pointer to error structure. 1872 * 1873 * @return 1874 * 0 on success, a negative errno value otherwise and rte_errno is set. 1875 */ 1876 int 1877 mlx5_flow_validate_item_vlan(const struct rte_flow_item *item, 1878 uint64_t item_flags, 1879 struct rte_eth_dev *dev, 1880 struct rte_flow_error *error) 1881 { 1882 const struct rte_flow_item_vlan *spec = item->spec; 1883 const struct rte_flow_item_vlan *mask = item->mask; 1884 const struct rte_flow_item_vlan nic_mask = { 1885 .tci = RTE_BE16(UINT16_MAX), 1886 .inner_type = RTE_BE16(UINT16_MAX), 1887 }; 1888 uint16_t vlan_tag = 0; 1889 const int tunnel = !!(item_flags & MLX5_FLOW_LAYER_TUNNEL); 1890 int ret; 1891 const uint64_t l34m = tunnel ? (MLX5_FLOW_LAYER_INNER_L3 | 1892 MLX5_FLOW_LAYER_INNER_L4) : 1893 (MLX5_FLOW_LAYER_OUTER_L3 | 1894 MLX5_FLOW_LAYER_OUTER_L4); 1895 const uint64_t vlanm = tunnel ? MLX5_FLOW_LAYER_INNER_VLAN : 1896 MLX5_FLOW_LAYER_OUTER_VLAN; 1897 1898 if (item_flags & vlanm) 1899 return rte_flow_error_set(error, EINVAL, 1900 RTE_FLOW_ERROR_TYPE_ITEM, item, 1901 "multiple VLAN layers not supported"); 1902 else if ((item_flags & l34m) != 0) 1903 return rte_flow_error_set(error, EINVAL, 1904 RTE_FLOW_ERROR_TYPE_ITEM, item, 1905 "VLAN cannot follow L3/L4 layer"); 1906 if (!mask) 1907 mask = &rte_flow_item_vlan_mask; 1908 ret = mlx5_flow_item_acceptable(item, (const uint8_t *)mask, 1909 (const uint8_t *)&nic_mask, 1910 sizeof(struct rte_flow_item_vlan), 1911 MLX5_ITEM_RANGE_NOT_ACCEPTED, error); 1912 if (ret) 1913 return ret; 1914 if (!tunnel && mask->tci != RTE_BE16(0x0fff)) { 1915 struct mlx5_priv *priv = dev->data->dev_private; 1916 1917 if (priv->vmwa_context) { 1918 /* 1919 * Non-NULL context means we have a virtual machine 1920 * and SR-IOV enabled, we have to create VLAN interface 1921 * to make hypervisor to setup E-Switch vport 1922 * context correctly. We avoid creating the multiple 1923 * VLAN interfaces, so we cannot support VLAN tag mask. 1924 */ 1925 return rte_flow_error_set(error, EINVAL, 1926 RTE_FLOW_ERROR_TYPE_ITEM, 1927 item, 1928 "VLAN tag mask is not" 1929 " supported in virtual" 1930 " environment"); 1931 } 1932 } 1933 if (spec) { 1934 vlan_tag = spec->tci; 1935 vlan_tag &= mask->tci; 1936 } 1937 /* 1938 * From verbs perspective an empty VLAN is equivalent 1939 * to a packet without VLAN layer. 1940 */ 1941 if (!vlan_tag) 1942 return rte_flow_error_set(error, EINVAL, 1943 RTE_FLOW_ERROR_TYPE_ITEM_SPEC, 1944 item->spec, 1945 "VLAN cannot be empty"); 1946 return 0; 1947 } 1948 1949 /** 1950 * Validate IPV4 item. 1951 * 1952 * @param[in] item 1953 * Item specification. 1954 * @param[in] item_flags 1955 * Bit-fields that holds the items detected until now. 1956 * @param[in] last_item 1957 * Previous validated item in the pattern items. 1958 * @param[in] ether_type 1959 * Type in the ethernet layer header (including dot1q). 1960 * @param[in] acc_mask 1961 * Acceptable mask, if NULL default internal default mask 1962 * will be used to check whether item fields are supported. 1963 * @param[in] range_accepted 1964 * True if range of values is accepted for specific fields, false otherwise. 1965 * @param[out] error 1966 * Pointer to error structure. 1967 * 1968 * @return 1969 * 0 on success, a negative errno value otherwise and rte_errno is set. 1970 */ 1971 int 1972 mlx5_flow_validate_item_ipv4(const struct rte_flow_item *item, 1973 uint64_t item_flags, 1974 uint64_t last_item, 1975 uint16_t ether_type, 1976 const struct rte_flow_item_ipv4 *acc_mask, 1977 bool range_accepted, 1978 struct rte_flow_error *error) 1979 { 1980 const struct rte_flow_item_ipv4 *mask = item->mask; 1981 const struct rte_flow_item_ipv4 *spec = item->spec; 1982 const struct rte_flow_item_ipv4 nic_mask = { 1983 .hdr = { 1984 .src_addr = RTE_BE32(0xffffffff), 1985 .dst_addr = RTE_BE32(0xffffffff), 1986 .type_of_service = 0xff, 1987 .next_proto_id = 0xff, 1988 }, 1989 }; 1990 const int tunnel = !!(item_flags & MLX5_FLOW_LAYER_TUNNEL); 1991 const uint64_t l3m = tunnel ? MLX5_FLOW_LAYER_INNER_L3 : 1992 MLX5_FLOW_LAYER_OUTER_L3; 1993 const uint64_t l4m = tunnel ? MLX5_FLOW_LAYER_INNER_L4 : 1994 MLX5_FLOW_LAYER_OUTER_L4; 1995 int ret; 1996 uint8_t next_proto = 0xFF; 1997 const uint64_t l2_vlan = (MLX5_FLOW_LAYER_L2 | 1998 MLX5_FLOW_LAYER_OUTER_VLAN | 1999 MLX5_FLOW_LAYER_INNER_VLAN); 2000 2001 if ((last_item & l2_vlan) && ether_type && 2002 ether_type != RTE_ETHER_TYPE_IPV4) 2003 return rte_flow_error_set(error, EINVAL, 2004 RTE_FLOW_ERROR_TYPE_ITEM, item, 2005 "IPv4 cannot follow L2/VLAN layer " 2006 "which ether type is not IPv4"); 2007 if (item_flags & MLX5_FLOW_LAYER_IPIP) { 2008 if (mask && spec) 2009 next_proto = mask->hdr.next_proto_id & 2010 spec->hdr.next_proto_id; 2011 if (next_proto == IPPROTO_IPIP || next_proto == IPPROTO_IPV6) 2012 return rte_flow_error_set(error, EINVAL, 2013 RTE_FLOW_ERROR_TYPE_ITEM, 2014 item, 2015 "multiple tunnel " 2016 "not supported"); 2017 } 2018 if (item_flags & MLX5_FLOW_LAYER_IPV6_ENCAP) 2019 return rte_flow_error_set(error, EINVAL, 2020 RTE_FLOW_ERROR_TYPE_ITEM, item, 2021 "wrong tunnel type - IPv6 specified " 2022 "but IPv4 item provided"); 2023 if (item_flags & l3m) 2024 return rte_flow_error_set(error, ENOTSUP, 2025 RTE_FLOW_ERROR_TYPE_ITEM, item, 2026 "multiple L3 layers not supported"); 2027 else if (item_flags & l4m) 2028 return rte_flow_error_set(error, EINVAL, 2029 RTE_FLOW_ERROR_TYPE_ITEM, item, 2030 "L3 cannot follow an L4 layer."); 2031 else if ((item_flags & MLX5_FLOW_LAYER_NVGRE) && 2032 !(item_flags & MLX5_FLOW_LAYER_INNER_L2)) 2033 return rte_flow_error_set(error, EINVAL, 2034 RTE_FLOW_ERROR_TYPE_ITEM, item, 2035 "L3 cannot follow an NVGRE layer."); 2036 if (!mask) 2037 mask = &rte_flow_item_ipv4_mask; 2038 else if (mask->hdr.next_proto_id != 0 && 2039 mask->hdr.next_proto_id != 0xff) 2040 return rte_flow_error_set(error, EINVAL, 2041 RTE_FLOW_ERROR_TYPE_ITEM_MASK, mask, 2042 "partial mask is not supported" 2043 " for protocol"); 2044 ret = mlx5_flow_item_acceptable(item, (const uint8_t *)mask, 2045 acc_mask ? (const uint8_t *)acc_mask 2046 : (const uint8_t *)&nic_mask, 2047 sizeof(struct rte_flow_item_ipv4), 2048 range_accepted, error); 2049 if (ret < 0) 2050 return ret; 2051 return 0; 2052 } 2053 2054 /** 2055 * Validate IPV6 item. 2056 * 2057 * @param[in] item 2058 * Item specification. 2059 * @param[in] item_flags 2060 * Bit-fields that holds the items detected until now. 2061 * @param[in] last_item 2062 * Previous validated item in the pattern items. 2063 * @param[in] ether_type 2064 * Type in the ethernet layer header (including dot1q). 2065 * @param[in] acc_mask 2066 * Acceptable mask, if NULL default internal default mask 2067 * will be used to check whether item fields are supported. 2068 * @param[out] error 2069 * Pointer to error structure. 2070 * 2071 * @return 2072 * 0 on success, a negative errno value otherwise and rte_errno is set. 2073 */ 2074 int 2075 mlx5_flow_validate_item_ipv6(const struct rte_flow_item *item, 2076 uint64_t item_flags, 2077 uint64_t last_item, 2078 uint16_t ether_type, 2079 const struct rte_flow_item_ipv6 *acc_mask, 2080 struct rte_flow_error *error) 2081 { 2082 const struct rte_flow_item_ipv6 *mask = item->mask; 2083 const struct rte_flow_item_ipv6 *spec = item->spec; 2084 const struct rte_flow_item_ipv6 nic_mask = { 2085 .hdr = { 2086 .src_addr = 2087 "\xff\xff\xff\xff\xff\xff\xff\xff" 2088 "\xff\xff\xff\xff\xff\xff\xff\xff", 2089 .dst_addr = 2090 "\xff\xff\xff\xff\xff\xff\xff\xff" 2091 "\xff\xff\xff\xff\xff\xff\xff\xff", 2092 .vtc_flow = RTE_BE32(0xffffffff), 2093 .proto = 0xff, 2094 }, 2095 }; 2096 const int tunnel = !!(item_flags & MLX5_FLOW_LAYER_TUNNEL); 2097 const uint64_t l3m = tunnel ? MLX5_FLOW_LAYER_INNER_L3 : 2098 MLX5_FLOW_LAYER_OUTER_L3; 2099 const uint64_t l4m = tunnel ? MLX5_FLOW_LAYER_INNER_L4 : 2100 MLX5_FLOW_LAYER_OUTER_L4; 2101 int ret; 2102 uint8_t next_proto = 0xFF; 2103 const uint64_t l2_vlan = (MLX5_FLOW_LAYER_L2 | 2104 MLX5_FLOW_LAYER_OUTER_VLAN | 2105 MLX5_FLOW_LAYER_INNER_VLAN); 2106 2107 if ((last_item & l2_vlan) && ether_type && 2108 ether_type != RTE_ETHER_TYPE_IPV6) 2109 return rte_flow_error_set(error, EINVAL, 2110 RTE_FLOW_ERROR_TYPE_ITEM, item, 2111 "IPv6 cannot follow L2/VLAN layer " 2112 "which ether type is not IPv6"); 2113 if (mask && mask->hdr.proto == UINT8_MAX && spec) 2114 next_proto = spec->hdr.proto; 2115 if (item_flags & MLX5_FLOW_LAYER_IPV6_ENCAP) { 2116 if (next_proto == IPPROTO_IPIP || next_proto == IPPROTO_IPV6) 2117 return rte_flow_error_set(error, EINVAL, 2118 RTE_FLOW_ERROR_TYPE_ITEM, 2119 item, 2120 "multiple tunnel " 2121 "not supported"); 2122 } 2123 if (next_proto == IPPROTO_HOPOPTS || 2124 next_proto == IPPROTO_ROUTING || 2125 next_proto == IPPROTO_FRAGMENT || 2126 next_proto == IPPROTO_ESP || 2127 next_proto == IPPROTO_AH || 2128 next_proto == IPPROTO_DSTOPTS) 2129 return rte_flow_error_set(error, EINVAL, 2130 RTE_FLOW_ERROR_TYPE_ITEM, item, 2131 "IPv6 proto (next header) should " 2132 "not be set as extension header"); 2133 if (item_flags & MLX5_FLOW_LAYER_IPIP) 2134 return rte_flow_error_set(error, EINVAL, 2135 RTE_FLOW_ERROR_TYPE_ITEM, item, 2136 "wrong tunnel type - IPv4 specified " 2137 "but IPv6 item provided"); 2138 if (item_flags & l3m) 2139 return rte_flow_error_set(error, ENOTSUP, 2140 RTE_FLOW_ERROR_TYPE_ITEM, item, 2141 "multiple L3 layers not supported"); 2142 else if (item_flags & l4m) 2143 return rte_flow_error_set(error, EINVAL, 2144 RTE_FLOW_ERROR_TYPE_ITEM, item, 2145 "L3 cannot follow an L4 layer."); 2146 else if ((item_flags & MLX5_FLOW_LAYER_NVGRE) && 2147 !(item_flags & MLX5_FLOW_LAYER_INNER_L2)) 2148 return rte_flow_error_set(error, EINVAL, 2149 RTE_FLOW_ERROR_TYPE_ITEM, item, 2150 "L3 cannot follow an NVGRE layer."); 2151 if (!mask) 2152 mask = &rte_flow_item_ipv6_mask; 2153 ret = mlx5_flow_item_acceptable(item, (const uint8_t *)mask, 2154 acc_mask ? (const uint8_t *)acc_mask 2155 : (const uint8_t *)&nic_mask, 2156 sizeof(struct rte_flow_item_ipv6), 2157 MLX5_ITEM_RANGE_NOT_ACCEPTED, error); 2158 if (ret < 0) 2159 return ret; 2160 return 0; 2161 } 2162 2163 /** 2164 * Validate UDP item. 2165 * 2166 * @param[in] item 2167 * Item specification. 2168 * @param[in] item_flags 2169 * Bit-fields that holds the items detected until now. 2170 * @param[in] target_protocol 2171 * The next protocol in the previous item. 2172 * @param[in] flow_mask 2173 * mlx5 flow-specific (DV, verbs, etc.) supported header fields mask. 2174 * @param[out] error 2175 * Pointer to error structure. 2176 * 2177 * @return 2178 * 0 on success, a negative errno value otherwise and rte_errno is set. 2179 */ 2180 int 2181 mlx5_flow_validate_item_udp(const struct rte_flow_item *item, 2182 uint64_t item_flags, 2183 uint8_t target_protocol, 2184 struct rte_flow_error *error) 2185 { 2186 const struct rte_flow_item_udp *mask = item->mask; 2187 const int tunnel = !!(item_flags & MLX5_FLOW_LAYER_TUNNEL); 2188 const uint64_t l3m = tunnel ? MLX5_FLOW_LAYER_INNER_L3 : 2189 MLX5_FLOW_LAYER_OUTER_L3; 2190 const uint64_t l4m = tunnel ? MLX5_FLOW_LAYER_INNER_L4 : 2191 MLX5_FLOW_LAYER_OUTER_L4; 2192 int ret; 2193 2194 if (target_protocol != 0xff && target_protocol != IPPROTO_UDP) 2195 return rte_flow_error_set(error, EINVAL, 2196 RTE_FLOW_ERROR_TYPE_ITEM, item, 2197 "protocol filtering not compatible" 2198 " with UDP layer"); 2199 if (!(item_flags & l3m)) 2200 return rte_flow_error_set(error, EINVAL, 2201 RTE_FLOW_ERROR_TYPE_ITEM, item, 2202 "L3 is mandatory to filter on L4"); 2203 if (item_flags & l4m) 2204 return rte_flow_error_set(error, EINVAL, 2205 RTE_FLOW_ERROR_TYPE_ITEM, item, 2206 "multiple L4 layers not supported"); 2207 if (!mask) 2208 mask = &rte_flow_item_udp_mask; 2209 ret = mlx5_flow_item_acceptable 2210 (item, (const uint8_t *)mask, 2211 (const uint8_t *)&rte_flow_item_udp_mask, 2212 sizeof(struct rte_flow_item_udp), MLX5_ITEM_RANGE_NOT_ACCEPTED, 2213 error); 2214 if (ret < 0) 2215 return ret; 2216 return 0; 2217 } 2218 2219 /** 2220 * Validate TCP item. 2221 * 2222 * @param[in] item 2223 * Item specification. 2224 * @param[in] item_flags 2225 * Bit-fields that holds the items detected until now. 2226 * @param[in] target_protocol 2227 * The next protocol in the previous item. 2228 * @param[out] error 2229 * Pointer to error structure. 2230 * 2231 * @return 2232 * 0 on success, a negative errno value otherwise and rte_errno is set. 2233 */ 2234 int 2235 mlx5_flow_validate_item_tcp(const struct rte_flow_item *item, 2236 uint64_t item_flags, 2237 uint8_t target_protocol, 2238 const struct rte_flow_item_tcp *flow_mask, 2239 struct rte_flow_error *error) 2240 { 2241 const struct rte_flow_item_tcp *mask = item->mask; 2242 const int tunnel = !!(item_flags & MLX5_FLOW_LAYER_TUNNEL); 2243 const uint64_t l3m = tunnel ? MLX5_FLOW_LAYER_INNER_L3 : 2244 MLX5_FLOW_LAYER_OUTER_L3; 2245 const uint64_t l4m = tunnel ? MLX5_FLOW_LAYER_INNER_L4 : 2246 MLX5_FLOW_LAYER_OUTER_L4; 2247 int ret; 2248 2249 MLX5_ASSERT(flow_mask); 2250 if (target_protocol != 0xff && target_protocol != IPPROTO_TCP) 2251 return rte_flow_error_set(error, EINVAL, 2252 RTE_FLOW_ERROR_TYPE_ITEM, item, 2253 "protocol filtering not compatible" 2254 " with TCP layer"); 2255 if (!(item_flags & l3m)) 2256 return rte_flow_error_set(error, EINVAL, 2257 RTE_FLOW_ERROR_TYPE_ITEM, item, 2258 "L3 is mandatory to filter on L4"); 2259 if (item_flags & l4m) 2260 return rte_flow_error_set(error, EINVAL, 2261 RTE_FLOW_ERROR_TYPE_ITEM, item, 2262 "multiple L4 layers not supported"); 2263 if (!mask) 2264 mask = &rte_flow_item_tcp_mask; 2265 ret = mlx5_flow_item_acceptable 2266 (item, (const uint8_t *)mask, 2267 (const uint8_t *)flow_mask, 2268 sizeof(struct rte_flow_item_tcp), MLX5_ITEM_RANGE_NOT_ACCEPTED, 2269 error); 2270 if (ret < 0) 2271 return ret; 2272 return 0; 2273 } 2274 2275 /** 2276 * Validate VXLAN item. 2277 * 2278 * @param[in] item 2279 * Item specification. 2280 * @param[in] item_flags 2281 * Bit-fields that holds the items detected until now. 2282 * @param[in] target_protocol 2283 * The next protocol in the previous item. 2284 * @param[out] error 2285 * Pointer to error structure. 2286 * 2287 * @return 2288 * 0 on success, a negative errno value otherwise and rte_errno is set. 2289 */ 2290 int 2291 mlx5_flow_validate_item_vxlan(const struct rte_flow_item *item, 2292 uint64_t item_flags, 2293 struct rte_flow_error *error) 2294 { 2295 const struct rte_flow_item_vxlan *spec = item->spec; 2296 const struct rte_flow_item_vxlan *mask = item->mask; 2297 int ret; 2298 union vni { 2299 uint32_t vlan_id; 2300 uint8_t vni[4]; 2301 } id = { .vlan_id = 0, }; 2302 2303 2304 if (item_flags & MLX5_FLOW_LAYER_TUNNEL) 2305 return rte_flow_error_set(error, ENOTSUP, 2306 RTE_FLOW_ERROR_TYPE_ITEM, item, 2307 "multiple tunnel layers not" 2308 " supported"); 2309 /* 2310 * Verify only UDPv4 is present as defined in 2311 * https://tools.ietf.org/html/rfc7348 2312 */ 2313 if (!(item_flags & MLX5_FLOW_LAYER_OUTER_L4_UDP)) 2314 return rte_flow_error_set(error, EINVAL, 2315 RTE_FLOW_ERROR_TYPE_ITEM, item, 2316 "no outer UDP layer found"); 2317 if (!mask) 2318 mask = &rte_flow_item_vxlan_mask; 2319 ret = mlx5_flow_item_acceptable 2320 (item, (const uint8_t *)mask, 2321 (const uint8_t *)&rte_flow_item_vxlan_mask, 2322 sizeof(struct rte_flow_item_vxlan), 2323 MLX5_ITEM_RANGE_NOT_ACCEPTED, error); 2324 if (ret < 0) 2325 return ret; 2326 if (spec) { 2327 memcpy(&id.vni[1], spec->vni, 3); 2328 memcpy(&id.vni[1], mask->vni, 3); 2329 } 2330 if (!(item_flags & MLX5_FLOW_LAYER_OUTER)) 2331 return rte_flow_error_set(error, ENOTSUP, 2332 RTE_FLOW_ERROR_TYPE_ITEM, item, 2333 "VXLAN tunnel must be fully defined"); 2334 return 0; 2335 } 2336 2337 /** 2338 * Validate VXLAN_GPE item. 2339 * 2340 * @param[in] item 2341 * Item specification. 2342 * @param[in] item_flags 2343 * Bit-fields that holds the items detected until now. 2344 * @param[in] priv 2345 * Pointer to the private data structure. 2346 * @param[in] target_protocol 2347 * The next protocol in the previous item. 2348 * @param[out] error 2349 * Pointer to error structure. 2350 * 2351 * @return 2352 * 0 on success, a negative errno value otherwise and rte_errno is set. 2353 */ 2354 int 2355 mlx5_flow_validate_item_vxlan_gpe(const struct rte_flow_item *item, 2356 uint64_t item_flags, 2357 struct rte_eth_dev *dev, 2358 struct rte_flow_error *error) 2359 { 2360 struct mlx5_priv *priv = dev->data->dev_private; 2361 const struct rte_flow_item_vxlan_gpe *spec = item->spec; 2362 const struct rte_flow_item_vxlan_gpe *mask = item->mask; 2363 int ret; 2364 union vni { 2365 uint32_t vlan_id; 2366 uint8_t vni[4]; 2367 } id = { .vlan_id = 0, }; 2368 2369 if (!priv->config.l3_vxlan_en) 2370 return rte_flow_error_set(error, ENOTSUP, 2371 RTE_FLOW_ERROR_TYPE_ITEM, item, 2372 "L3 VXLAN is not enabled by device" 2373 " parameter and/or not configured in" 2374 " firmware"); 2375 if (item_flags & MLX5_FLOW_LAYER_TUNNEL) 2376 return rte_flow_error_set(error, ENOTSUP, 2377 RTE_FLOW_ERROR_TYPE_ITEM, item, 2378 "multiple tunnel layers not" 2379 " supported"); 2380 /* 2381 * Verify only UDPv4 is present as defined in 2382 * https://tools.ietf.org/html/rfc7348 2383 */ 2384 if (!(item_flags & MLX5_FLOW_LAYER_OUTER_L4_UDP)) 2385 return rte_flow_error_set(error, EINVAL, 2386 RTE_FLOW_ERROR_TYPE_ITEM, item, 2387 "no outer UDP layer found"); 2388 if (!mask) 2389 mask = &rte_flow_item_vxlan_gpe_mask; 2390 ret = mlx5_flow_item_acceptable 2391 (item, (const uint8_t *)mask, 2392 (const uint8_t *)&rte_flow_item_vxlan_gpe_mask, 2393 sizeof(struct rte_flow_item_vxlan_gpe), 2394 MLX5_ITEM_RANGE_NOT_ACCEPTED, error); 2395 if (ret < 0) 2396 return ret; 2397 if (spec) { 2398 if (spec->protocol) 2399 return rte_flow_error_set(error, ENOTSUP, 2400 RTE_FLOW_ERROR_TYPE_ITEM, 2401 item, 2402 "VxLAN-GPE protocol" 2403 " not supported"); 2404 memcpy(&id.vni[1], spec->vni, 3); 2405 memcpy(&id.vni[1], mask->vni, 3); 2406 } 2407 if (!(item_flags & MLX5_FLOW_LAYER_OUTER)) 2408 return rte_flow_error_set(error, ENOTSUP, 2409 RTE_FLOW_ERROR_TYPE_ITEM, item, 2410 "VXLAN-GPE tunnel must be fully" 2411 " defined"); 2412 return 0; 2413 } 2414 /** 2415 * Validate GRE Key item. 2416 * 2417 * @param[in] item 2418 * Item specification. 2419 * @param[in] item_flags 2420 * Bit flags to mark detected items. 2421 * @param[in] gre_item 2422 * Pointer to gre_item 2423 * @param[out] error 2424 * Pointer to error structure. 2425 * 2426 * @return 2427 * 0 on success, a negative errno value otherwise and rte_errno is set. 2428 */ 2429 int 2430 mlx5_flow_validate_item_gre_key(const struct rte_flow_item *item, 2431 uint64_t item_flags, 2432 const struct rte_flow_item *gre_item, 2433 struct rte_flow_error *error) 2434 { 2435 const rte_be32_t *mask = item->mask; 2436 int ret = 0; 2437 rte_be32_t gre_key_default_mask = RTE_BE32(UINT32_MAX); 2438 const struct rte_flow_item_gre *gre_spec; 2439 const struct rte_flow_item_gre *gre_mask; 2440 2441 if (item_flags & MLX5_FLOW_LAYER_GRE_KEY) 2442 return rte_flow_error_set(error, ENOTSUP, 2443 RTE_FLOW_ERROR_TYPE_ITEM, item, 2444 "Multiple GRE key not support"); 2445 if (!(item_flags & MLX5_FLOW_LAYER_GRE)) 2446 return rte_flow_error_set(error, ENOTSUP, 2447 RTE_FLOW_ERROR_TYPE_ITEM, item, 2448 "No preceding GRE header"); 2449 if (item_flags & MLX5_FLOW_LAYER_INNER) 2450 return rte_flow_error_set(error, ENOTSUP, 2451 RTE_FLOW_ERROR_TYPE_ITEM, item, 2452 "GRE key following a wrong item"); 2453 gre_mask = gre_item->mask; 2454 if (!gre_mask) 2455 gre_mask = &rte_flow_item_gre_mask; 2456 gre_spec = gre_item->spec; 2457 if (gre_spec && (gre_mask->c_rsvd0_ver & RTE_BE16(0x2000)) && 2458 !(gre_spec->c_rsvd0_ver & RTE_BE16(0x2000))) 2459 return rte_flow_error_set(error, EINVAL, 2460 RTE_FLOW_ERROR_TYPE_ITEM, item, 2461 "Key bit must be on"); 2462 2463 if (!mask) 2464 mask = &gre_key_default_mask; 2465 ret = mlx5_flow_item_acceptable 2466 (item, (const uint8_t *)mask, 2467 (const uint8_t *)&gre_key_default_mask, 2468 sizeof(rte_be32_t), MLX5_ITEM_RANGE_NOT_ACCEPTED, error); 2469 return ret; 2470 } 2471 2472 /** 2473 * Validate GRE item. 2474 * 2475 * @param[in] item 2476 * Item specification. 2477 * @param[in] item_flags 2478 * Bit flags to mark detected items. 2479 * @param[in] target_protocol 2480 * The next protocol in the previous item. 2481 * @param[out] error 2482 * Pointer to error structure. 2483 * 2484 * @return 2485 * 0 on success, a negative errno value otherwise and rte_errno is set. 2486 */ 2487 int 2488 mlx5_flow_validate_item_gre(const struct rte_flow_item *item, 2489 uint64_t item_flags, 2490 uint8_t target_protocol, 2491 struct rte_flow_error *error) 2492 { 2493 const struct rte_flow_item_gre *spec __rte_unused = item->spec; 2494 const struct rte_flow_item_gre *mask = item->mask; 2495 int ret; 2496 const struct rte_flow_item_gre nic_mask = { 2497 .c_rsvd0_ver = RTE_BE16(0xB000), 2498 .protocol = RTE_BE16(UINT16_MAX), 2499 }; 2500 2501 if (target_protocol != 0xff && target_protocol != IPPROTO_GRE) 2502 return rte_flow_error_set(error, EINVAL, 2503 RTE_FLOW_ERROR_TYPE_ITEM, item, 2504 "protocol filtering not compatible" 2505 " with this GRE layer"); 2506 if (item_flags & MLX5_FLOW_LAYER_TUNNEL) 2507 return rte_flow_error_set(error, ENOTSUP, 2508 RTE_FLOW_ERROR_TYPE_ITEM, item, 2509 "multiple tunnel layers not" 2510 " supported"); 2511 if (!(item_flags & MLX5_FLOW_LAYER_OUTER_L3)) 2512 return rte_flow_error_set(error, ENOTSUP, 2513 RTE_FLOW_ERROR_TYPE_ITEM, item, 2514 "L3 Layer is missing"); 2515 if (!mask) 2516 mask = &rte_flow_item_gre_mask; 2517 ret = mlx5_flow_item_acceptable 2518 (item, (const uint8_t *)mask, 2519 (const uint8_t *)&nic_mask, 2520 sizeof(struct rte_flow_item_gre), MLX5_ITEM_RANGE_NOT_ACCEPTED, 2521 error); 2522 if (ret < 0) 2523 return ret; 2524 #ifndef HAVE_MLX5DV_DR 2525 #ifndef HAVE_IBV_DEVICE_MPLS_SUPPORT 2526 if (spec && (spec->protocol & mask->protocol)) 2527 return rte_flow_error_set(error, ENOTSUP, 2528 RTE_FLOW_ERROR_TYPE_ITEM, item, 2529 "without MPLS support the" 2530 " specification cannot be used for" 2531 " filtering"); 2532 #endif 2533 #endif 2534 return 0; 2535 } 2536 2537 /** 2538 * Validate Geneve item. 2539 * 2540 * @param[in] item 2541 * Item specification. 2542 * @param[in] itemFlags 2543 * Bit-fields that holds the items detected until now. 2544 * @param[in] enPriv 2545 * Pointer to the private data structure. 2546 * @param[out] error 2547 * Pointer to error structure. 2548 * 2549 * @return 2550 * 0 on success, a negative errno value otherwise and rte_errno is set. 2551 */ 2552 2553 int 2554 mlx5_flow_validate_item_geneve(const struct rte_flow_item *item, 2555 uint64_t item_flags, 2556 struct rte_eth_dev *dev, 2557 struct rte_flow_error *error) 2558 { 2559 struct mlx5_priv *priv = dev->data->dev_private; 2560 const struct rte_flow_item_geneve *spec = item->spec; 2561 const struct rte_flow_item_geneve *mask = item->mask; 2562 int ret; 2563 uint16_t gbhdr; 2564 uint8_t opt_len = priv->config.hca_attr.geneve_max_opt_len ? 2565 MLX5_GENEVE_OPT_LEN_1 : MLX5_GENEVE_OPT_LEN_0; 2566 const struct rte_flow_item_geneve nic_mask = { 2567 .ver_opt_len_o_c_rsvd0 = RTE_BE16(0x3f80), 2568 .vni = "\xff\xff\xff", 2569 .protocol = RTE_BE16(UINT16_MAX), 2570 }; 2571 2572 if (!priv->config.hca_attr.tunnel_stateless_geneve_rx) 2573 return rte_flow_error_set(error, ENOTSUP, 2574 RTE_FLOW_ERROR_TYPE_ITEM, item, 2575 "L3 Geneve is not enabled by device" 2576 " parameter and/or not configured in" 2577 " firmware"); 2578 if (item_flags & MLX5_FLOW_LAYER_TUNNEL) 2579 return rte_flow_error_set(error, ENOTSUP, 2580 RTE_FLOW_ERROR_TYPE_ITEM, item, 2581 "multiple tunnel layers not" 2582 " supported"); 2583 /* 2584 * Verify only UDPv4 is present as defined in 2585 * https://tools.ietf.org/html/rfc7348 2586 */ 2587 if (!(item_flags & MLX5_FLOW_LAYER_OUTER_L4_UDP)) 2588 return rte_flow_error_set(error, EINVAL, 2589 RTE_FLOW_ERROR_TYPE_ITEM, item, 2590 "no outer UDP layer found"); 2591 if (!mask) 2592 mask = &rte_flow_item_geneve_mask; 2593 ret = mlx5_flow_item_acceptable 2594 (item, (const uint8_t *)mask, 2595 (const uint8_t *)&nic_mask, 2596 sizeof(struct rte_flow_item_geneve), 2597 MLX5_ITEM_RANGE_NOT_ACCEPTED, error); 2598 if (ret) 2599 return ret; 2600 if (spec) { 2601 gbhdr = rte_be_to_cpu_16(spec->ver_opt_len_o_c_rsvd0); 2602 if (MLX5_GENEVE_VER_VAL(gbhdr) || 2603 MLX5_GENEVE_CRITO_VAL(gbhdr) || 2604 MLX5_GENEVE_RSVD_VAL(gbhdr) || spec->rsvd1) 2605 return rte_flow_error_set(error, ENOTSUP, 2606 RTE_FLOW_ERROR_TYPE_ITEM, 2607 item, 2608 "Geneve protocol unsupported" 2609 " fields are being used"); 2610 if (MLX5_GENEVE_OPTLEN_VAL(gbhdr) > opt_len) 2611 return rte_flow_error_set 2612 (error, ENOTSUP, 2613 RTE_FLOW_ERROR_TYPE_ITEM, 2614 item, 2615 "Unsupported Geneve options length"); 2616 } 2617 if (!(item_flags & MLX5_FLOW_LAYER_OUTER)) 2618 return rte_flow_error_set 2619 (error, ENOTSUP, 2620 RTE_FLOW_ERROR_TYPE_ITEM, item, 2621 "Geneve tunnel must be fully defined"); 2622 return 0; 2623 } 2624 2625 /** 2626 * Validate Geneve TLV option item. 2627 * 2628 * @param[in] item 2629 * Item specification. 2630 * @param[in] last_item 2631 * Previous validated item in the pattern items. 2632 * @param[in] geneve_item 2633 * Previous GENEVE item specification. 2634 * @param[in] dev 2635 * Pointer to the rte_eth_dev structure. 2636 * @param[out] error 2637 * Pointer to error structure. 2638 * 2639 * @return 2640 * 0 on success, a negative errno value otherwise and rte_errno is set. 2641 */ 2642 int 2643 mlx5_flow_validate_item_geneve_opt(const struct rte_flow_item *item, 2644 uint64_t last_item, 2645 const struct rte_flow_item *geneve_item, 2646 struct rte_eth_dev *dev, 2647 struct rte_flow_error *error) 2648 { 2649 struct mlx5_priv *priv = dev->data->dev_private; 2650 struct mlx5_dev_ctx_shared *sh = priv->sh; 2651 struct mlx5_geneve_tlv_option_resource *geneve_opt_resource; 2652 struct mlx5_hca_attr *hca_attr = &priv->config.hca_attr; 2653 uint8_t data_max_supported = 2654 hca_attr->max_geneve_tlv_option_data_len * 4; 2655 struct mlx5_dev_config *config = &priv->config; 2656 const struct rte_flow_item_geneve *geneve_spec; 2657 const struct rte_flow_item_geneve *geneve_mask; 2658 const struct rte_flow_item_geneve_opt *spec = item->spec; 2659 const struct rte_flow_item_geneve_opt *mask = item->mask; 2660 unsigned int i; 2661 unsigned int data_len; 2662 uint8_t tlv_option_len; 2663 uint16_t optlen_m, optlen_v; 2664 const struct rte_flow_item_geneve_opt full_mask = { 2665 .option_class = RTE_BE16(0xffff), 2666 .option_type = 0xff, 2667 .option_len = 0x1f, 2668 }; 2669 2670 if (!mask) 2671 mask = &rte_flow_item_geneve_opt_mask; 2672 if (!spec) 2673 return rte_flow_error_set 2674 (error, ENOTSUP, RTE_FLOW_ERROR_TYPE_ITEM, item, 2675 "Geneve TLV opt class/type/length must be specified"); 2676 if ((uint32_t)spec->option_len > MLX5_GENEVE_OPTLEN_MASK) 2677 return rte_flow_error_set 2678 (error, ENOTSUP, RTE_FLOW_ERROR_TYPE_ITEM, item, 2679 "Geneve TLV opt length exceeeds the limit (31)"); 2680 /* Check if class type and length masks are full. */ 2681 if (full_mask.option_class != mask->option_class || 2682 full_mask.option_type != mask->option_type || 2683 full_mask.option_len != (mask->option_len & full_mask.option_len)) 2684 return rte_flow_error_set 2685 (error, ENOTSUP, RTE_FLOW_ERROR_TYPE_ITEM, item, 2686 "Geneve TLV opt class/type/length masks must be full"); 2687 /* Check if length is supported */ 2688 if ((uint32_t)spec->option_len > 2689 config->hca_attr.max_geneve_tlv_option_data_len) 2690 return rte_flow_error_set 2691 (error, ENOTSUP, RTE_FLOW_ERROR_TYPE_ITEM, item, 2692 "Geneve TLV opt length not supported"); 2693 if (config->hca_attr.max_geneve_tlv_options > 1) 2694 DRV_LOG(DEBUG, 2695 "max_geneve_tlv_options supports more than 1 option"); 2696 /* Check GENEVE item preceding. */ 2697 if (!geneve_item || !(last_item & MLX5_FLOW_LAYER_GENEVE)) 2698 return rte_flow_error_set 2699 (error, ENOTSUP, RTE_FLOW_ERROR_TYPE_ITEM, item, 2700 "Geneve opt item must be preceded with Geneve item"); 2701 geneve_spec = geneve_item->spec; 2702 geneve_mask = geneve_item->mask ? geneve_item->mask : 2703 &rte_flow_item_geneve_mask; 2704 /* Check if GENEVE TLV option size doesn't exceed option length */ 2705 if (geneve_spec && (geneve_mask->ver_opt_len_o_c_rsvd0 || 2706 geneve_spec->ver_opt_len_o_c_rsvd0)) { 2707 tlv_option_len = spec->option_len & mask->option_len; 2708 optlen_v = rte_be_to_cpu_16(geneve_spec->ver_opt_len_o_c_rsvd0); 2709 optlen_v = MLX5_GENEVE_OPTLEN_VAL(optlen_v); 2710 optlen_m = rte_be_to_cpu_16(geneve_mask->ver_opt_len_o_c_rsvd0); 2711 optlen_m = MLX5_GENEVE_OPTLEN_VAL(optlen_m); 2712 if ((optlen_v & optlen_m) <= tlv_option_len) 2713 return rte_flow_error_set 2714 (error, ENOTSUP, RTE_FLOW_ERROR_TYPE_ITEM, item, 2715 "GENEVE TLV option length exceeds optlen"); 2716 } 2717 /* Check if length is 0 or data is 0. */ 2718 if (spec->data == NULL || spec->option_len == 0) 2719 return rte_flow_error_set 2720 (error, ENOTSUP, RTE_FLOW_ERROR_TYPE_ITEM, item, 2721 "Geneve TLV opt with zero data/length not supported"); 2722 /* Check not all data & mask are 0. */ 2723 data_len = spec->option_len * 4; 2724 if (mask->data == NULL) { 2725 for (i = 0; i < data_len; i++) 2726 if (spec->data[i]) 2727 break; 2728 if (i == data_len) 2729 return rte_flow_error_set(error, ENOTSUP, 2730 RTE_FLOW_ERROR_TYPE_ITEM, item, 2731 "Can't match on Geneve option data 0"); 2732 } else { 2733 for (i = 0; i < data_len; i++) 2734 if (spec->data[i] & mask->data[i]) 2735 break; 2736 if (i == data_len) 2737 return rte_flow_error_set(error, ENOTSUP, 2738 RTE_FLOW_ERROR_TYPE_ITEM, item, 2739 "Can't match on Geneve option data and mask 0"); 2740 /* Check data mask supported. */ 2741 for (i = data_max_supported; i < data_len ; i++) 2742 if (mask->data[i]) 2743 return rte_flow_error_set(error, ENOTSUP, 2744 RTE_FLOW_ERROR_TYPE_ITEM, item, 2745 "Data mask is of unsupported size"); 2746 } 2747 /* Check GENEVE option is supported in NIC. */ 2748 if (!config->hca_attr.geneve_tlv_opt) 2749 return rte_flow_error_set 2750 (error, ENOTSUP, RTE_FLOW_ERROR_TYPE_ITEM, item, 2751 "Geneve TLV opt not supported"); 2752 /* Check if we already have geneve option with different type/class. */ 2753 rte_spinlock_lock(&sh->geneve_tlv_opt_sl); 2754 geneve_opt_resource = sh->geneve_tlv_option_resource; 2755 if (geneve_opt_resource != NULL) 2756 if (geneve_opt_resource->option_class != spec->option_class || 2757 geneve_opt_resource->option_type != spec->option_type || 2758 geneve_opt_resource->length != spec->option_len) { 2759 rte_spinlock_unlock(&sh->geneve_tlv_opt_sl); 2760 return rte_flow_error_set(error, ENOTSUP, 2761 RTE_FLOW_ERROR_TYPE_ITEM, item, 2762 "Only one Geneve TLV option supported"); 2763 } 2764 rte_spinlock_unlock(&sh->geneve_tlv_opt_sl); 2765 return 0; 2766 } 2767 2768 /** 2769 * Validate MPLS item. 2770 * 2771 * @param[in] dev 2772 * Pointer to the rte_eth_dev structure. 2773 * @param[in] item 2774 * Item specification. 2775 * @param[in] item_flags 2776 * Bit-fields that holds the items detected until now. 2777 * @param[in] prev_layer 2778 * The protocol layer indicated in previous item. 2779 * @param[out] error 2780 * Pointer to error structure. 2781 * 2782 * @return 2783 * 0 on success, a negative errno value otherwise and rte_errno is set. 2784 */ 2785 int 2786 mlx5_flow_validate_item_mpls(struct rte_eth_dev *dev __rte_unused, 2787 const struct rte_flow_item *item __rte_unused, 2788 uint64_t item_flags __rte_unused, 2789 uint64_t prev_layer __rte_unused, 2790 struct rte_flow_error *error) 2791 { 2792 #ifdef HAVE_IBV_DEVICE_MPLS_SUPPORT 2793 const struct rte_flow_item_mpls *mask = item->mask; 2794 struct mlx5_priv *priv = dev->data->dev_private; 2795 int ret; 2796 2797 if (!priv->config.mpls_en) 2798 return rte_flow_error_set(error, ENOTSUP, 2799 RTE_FLOW_ERROR_TYPE_ITEM, item, 2800 "MPLS not supported or" 2801 " disabled in firmware" 2802 " configuration."); 2803 /* MPLS over IP, UDP, GRE is allowed */ 2804 if (!(prev_layer & (MLX5_FLOW_LAYER_OUTER_L3 | 2805 MLX5_FLOW_LAYER_OUTER_L4_UDP | 2806 MLX5_FLOW_LAYER_GRE | 2807 MLX5_FLOW_LAYER_GRE_KEY))) 2808 return rte_flow_error_set(error, EINVAL, 2809 RTE_FLOW_ERROR_TYPE_ITEM, item, 2810 "protocol filtering not compatible" 2811 " with MPLS layer"); 2812 /* Multi-tunnel isn't allowed but MPLS over GRE is an exception. */ 2813 if ((item_flags & MLX5_FLOW_LAYER_TUNNEL) && 2814 !(item_flags & MLX5_FLOW_LAYER_GRE)) 2815 return rte_flow_error_set(error, ENOTSUP, 2816 RTE_FLOW_ERROR_TYPE_ITEM, item, 2817 "multiple tunnel layers not" 2818 " supported"); 2819 if (!mask) 2820 mask = &rte_flow_item_mpls_mask; 2821 ret = mlx5_flow_item_acceptable 2822 (item, (const uint8_t *)mask, 2823 (const uint8_t *)&rte_flow_item_mpls_mask, 2824 sizeof(struct rte_flow_item_mpls), 2825 MLX5_ITEM_RANGE_NOT_ACCEPTED, error); 2826 if (ret < 0) 2827 return ret; 2828 return 0; 2829 #else 2830 return rte_flow_error_set(error, ENOTSUP, 2831 RTE_FLOW_ERROR_TYPE_ITEM, item, 2832 "MPLS is not supported by Verbs, please" 2833 " update."); 2834 #endif 2835 } 2836 2837 /** 2838 * Validate NVGRE item. 2839 * 2840 * @param[in] item 2841 * Item specification. 2842 * @param[in] item_flags 2843 * Bit flags to mark detected items. 2844 * @param[in] target_protocol 2845 * The next protocol in the previous item. 2846 * @param[out] error 2847 * Pointer to error structure. 2848 * 2849 * @return 2850 * 0 on success, a negative errno value otherwise and rte_errno is set. 2851 */ 2852 int 2853 mlx5_flow_validate_item_nvgre(const struct rte_flow_item *item, 2854 uint64_t item_flags, 2855 uint8_t target_protocol, 2856 struct rte_flow_error *error) 2857 { 2858 const struct rte_flow_item_nvgre *mask = item->mask; 2859 int ret; 2860 2861 if (target_protocol != 0xff && target_protocol != IPPROTO_GRE) 2862 return rte_flow_error_set(error, EINVAL, 2863 RTE_FLOW_ERROR_TYPE_ITEM, item, 2864 "protocol filtering not compatible" 2865 " with this GRE layer"); 2866 if (item_flags & MLX5_FLOW_LAYER_TUNNEL) 2867 return rte_flow_error_set(error, ENOTSUP, 2868 RTE_FLOW_ERROR_TYPE_ITEM, item, 2869 "multiple tunnel layers not" 2870 " supported"); 2871 if (!(item_flags & MLX5_FLOW_LAYER_OUTER_L3)) 2872 return rte_flow_error_set(error, ENOTSUP, 2873 RTE_FLOW_ERROR_TYPE_ITEM, item, 2874 "L3 Layer is missing"); 2875 if (!mask) 2876 mask = &rte_flow_item_nvgre_mask; 2877 ret = mlx5_flow_item_acceptable 2878 (item, (const uint8_t *)mask, 2879 (const uint8_t *)&rte_flow_item_nvgre_mask, 2880 sizeof(struct rte_flow_item_nvgre), 2881 MLX5_ITEM_RANGE_NOT_ACCEPTED, error); 2882 if (ret < 0) 2883 return ret; 2884 return 0; 2885 } 2886 2887 /** 2888 * Validate eCPRI item. 2889 * 2890 * @param[in] item 2891 * Item specification. 2892 * @param[in] item_flags 2893 * Bit-fields that holds the items detected until now. 2894 * @param[in] last_item 2895 * Previous validated item in the pattern items. 2896 * @param[in] ether_type 2897 * Type in the ethernet layer header (including dot1q). 2898 * @param[in] acc_mask 2899 * Acceptable mask, if NULL default internal default mask 2900 * will be used to check whether item fields are supported. 2901 * @param[out] error 2902 * Pointer to error structure. 2903 * 2904 * @return 2905 * 0 on success, a negative errno value otherwise and rte_errno is set. 2906 */ 2907 int 2908 mlx5_flow_validate_item_ecpri(const struct rte_flow_item *item, 2909 uint64_t item_flags, 2910 uint64_t last_item, 2911 uint16_t ether_type, 2912 const struct rte_flow_item_ecpri *acc_mask, 2913 struct rte_flow_error *error) 2914 { 2915 const struct rte_flow_item_ecpri *mask = item->mask; 2916 const struct rte_flow_item_ecpri nic_mask = { 2917 .hdr = { 2918 .common = { 2919 .u32 = 2920 RTE_BE32(((const struct rte_ecpri_common_hdr) { 2921 .type = 0xFF, 2922 }).u32), 2923 }, 2924 .dummy[0] = 0xFFFFFFFF, 2925 }, 2926 }; 2927 const uint64_t outer_l2_vlan = (MLX5_FLOW_LAYER_OUTER_L2 | 2928 MLX5_FLOW_LAYER_OUTER_VLAN); 2929 struct rte_flow_item_ecpri mask_lo; 2930 2931 if (!(last_item & outer_l2_vlan) && 2932 last_item != MLX5_FLOW_LAYER_OUTER_L4_UDP) 2933 return rte_flow_error_set(error, EINVAL, 2934 RTE_FLOW_ERROR_TYPE_ITEM, item, 2935 "eCPRI can only follow L2/VLAN layer or UDP layer"); 2936 if ((last_item & outer_l2_vlan) && ether_type && 2937 ether_type != RTE_ETHER_TYPE_ECPRI) 2938 return rte_flow_error_set(error, EINVAL, 2939 RTE_FLOW_ERROR_TYPE_ITEM, item, 2940 "eCPRI cannot follow L2/VLAN layer which ether type is not 0xAEFE"); 2941 if (item_flags & MLX5_FLOW_LAYER_TUNNEL) 2942 return rte_flow_error_set(error, EINVAL, 2943 RTE_FLOW_ERROR_TYPE_ITEM, item, 2944 "eCPRI with tunnel is not supported right now"); 2945 if (item_flags & MLX5_FLOW_LAYER_OUTER_L3) 2946 return rte_flow_error_set(error, ENOTSUP, 2947 RTE_FLOW_ERROR_TYPE_ITEM, item, 2948 "multiple L3 layers not supported"); 2949 else if (item_flags & MLX5_FLOW_LAYER_OUTER_L4_TCP) 2950 return rte_flow_error_set(error, EINVAL, 2951 RTE_FLOW_ERROR_TYPE_ITEM, item, 2952 "eCPRI cannot coexist with a TCP layer"); 2953 /* In specification, eCPRI could be over UDP layer. */ 2954 else if (item_flags & MLX5_FLOW_LAYER_OUTER_L4_UDP) 2955 return rte_flow_error_set(error, EINVAL, 2956 RTE_FLOW_ERROR_TYPE_ITEM, item, 2957 "eCPRI over UDP layer is not yet supported right now"); 2958 /* Mask for type field in common header could be zero. */ 2959 if (!mask) 2960 mask = &rte_flow_item_ecpri_mask; 2961 mask_lo.hdr.common.u32 = rte_be_to_cpu_32(mask->hdr.common.u32); 2962 /* Input mask is in big-endian format. */ 2963 if (mask_lo.hdr.common.type != 0 && mask_lo.hdr.common.type != 0xff) 2964 return rte_flow_error_set(error, EINVAL, 2965 RTE_FLOW_ERROR_TYPE_ITEM_MASK, mask, 2966 "partial mask is not supported for protocol"); 2967 else if (mask_lo.hdr.common.type == 0 && mask->hdr.dummy[0] != 0) 2968 return rte_flow_error_set(error, EINVAL, 2969 RTE_FLOW_ERROR_TYPE_ITEM_MASK, mask, 2970 "message header mask must be after a type mask"); 2971 return mlx5_flow_item_acceptable(item, (const uint8_t *)mask, 2972 acc_mask ? (const uint8_t *)acc_mask 2973 : (const uint8_t *)&nic_mask, 2974 sizeof(struct rte_flow_item_ecpri), 2975 MLX5_ITEM_RANGE_NOT_ACCEPTED, error); 2976 } 2977 2978 /** 2979 * Release resource related QUEUE/RSS action split. 2980 * 2981 * @param dev 2982 * Pointer to Ethernet device. 2983 * @param flow 2984 * Flow to release id's from. 2985 */ 2986 static void 2987 flow_mreg_split_qrss_release(struct rte_eth_dev *dev, 2988 struct rte_flow *flow) 2989 { 2990 struct mlx5_priv *priv = dev->data->dev_private; 2991 uint32_t handle_idx; 2992 struct mlx5_flow_handle *dev_handle; 2993 2994 SILIST_FOREACH(priv->sh->ipool[MLX5_IPOOL_MLX5_FLOW], flow->dev_handles, 2995 handle_idx, dev_handle, next) 2996 if (dev_handle->split_flow_id) 2997 mlx5_ipool_free(priv->sh->ipool 2998 [MLX5_IPOOL_RSS_EXPANTION_FLOW_ID], 2999 dev_handle->split_flow_id); 3000 } 3001 3002 static int 3003 flow_null_validate(struct rte_eth_dev *dev __rte_unused, 3004 const struct rte_flow_attr *attr __rte_unused, 3005 const struct rte_flow_item items[] __rte_unused, 3006 const struct rte_flow_action actions[] __rte_unused, 3007 bool external __rte_unused, 3008 int hairpin __rte_unused, 3009 struct rte_flow_error *error) 3010 { 3011 return rte_flow_error_set(error, ENOTSUP, 3012 RTE_FLOW_ERROR_TYPE_UNSPECIFIED, NULL, NULL); 3013 } 3014 3015 static struct mlx5_flow * 3016 flow_null_prepare(struct rte_eth_dev *dev __rte_unused, 3017 const struct rte_flow_attr *attr __rte_unused, 3018 const struct rte_flow_item items[] __rte_unused, 3019 const struct rte_flow_action actions[] __rte_unused, 3020 struct rte_flow_error *error) 3021 { 3022 rte_flow_error_set(error, ENOTSUP, 3023 RTE_FLOW_ERROR_TYPE_UNSPECIFIED, NULL, NULL); 3024 return NULL; 3025 } 3026 3027 static int 3028 flow_null_translate(struct rte_eth_dev *dev __rte_unused, 3029 struct mlx5_flow *dev_flow __rte_unused, 3030 const struct rte_flow_attr *attr __rte_unused, 3031 const struct rte_flow_item items[] __rte_unused, 3032 const struct rte_flow_action actions[] __rte_unused, 3033 struct rte_flow_error *error) 3034 { 3035 return rte_flow_error_set(error, ENOTSUP, 3036 RTE_FLOW_ERROR_TYPE_UNSPECIFIED, NULL, NULL); 3037 } 3038 3039 static int 3040 flow_null_apply(struct rte_eth_dev *dev __rte_unused, 3041 struct rte_flow *flow __rte_unused, 3042 struct rte_flow_error *error) 3043 { 3044 return rte_flow_error_set(error, ENOTSUP, 3045 RTE_FLOW_ERROR_TYPE_UNSPECIFIED, NULL, NULL); 3046 } 3047 3048 static void 3049 flow_null_remove(struct rte_eth_dev *dev __rte_unused, 3050 struct rte_flow *flow __rte_unused) 3051 { 3052 } 3053 3054 static void 3055 flow_null_destroy(struct rte_eth_dev *dev __rte_unused, 3056 struct rte_flow *flow __rte_unused) 3057 { 3058 } 3059 3060 static int 3061 flow_null_query(struct rte_eth_dev *dev __rte_unused, 3062 struct rte_flow *flow __rte_unused, 3063 const struct rte_flow_action *actions __rte_unused, 3064 void *data __rte_unused, 3065 struct rte_flow_error *error) 3066 { 3067 return rte_flow_error_set(error, ENOTSUP, 3068 RTE_FLOW_ERROR_TYPE_UNSPECIFIED, NULL, NULL); 3069 } 3070 3071 static int 3072 flow_null_sync_domain(struct rte_eth_dev *dev __rte_unused, 3073 uint32_t domains __rte_unused, 3074 uint32_t flags __rte_unused) 3075 { 3076 return 0; 3077 } 3078 3079 /* Void driver to protect from null pointer reference. */ 3080 const struct mlx5_flow_driver_ops mlx5_flow_null_drv_ops = { 3081 .validate = flow_null_validate, 3082 .prepare = flow_null_prepare, 3083 .translate = flow_null_translate, 3084 .apply = flow_null_apply, 3085 .remove = flow_null_remove, 3086 .destroy = flow_null_destroy, 3087 .query = flow_null_query, 3088 .sync_domain = flow_null_sync_domain, 3089 }; 3090 3091 /** 3092 * Select flow driver type according to flow attributes and device 3093 * configuration. 3094 * 3095 * @param[in] dev 3096 * Pointer to the dev structure. 3097 * @param[in] attr 3098 * Pointer to the flow attributes. 3099 * 3100 * @return 3101 * flow driver type, MLX5_FLOW_TYPE_MAX otherwise. 3102 */ 3103 static enum mlx5_flow_drv_type 3104 flow_get_drv_type(struct rte_eth_dev *dev, const struct rte_flow_attr *attr) 3105 { 3106 struct mlx5_priv *priv = dev->data->dev_private; 3107 /* The OS can determine first a specific flow type (DV, VERBS) */ 3108 enum mlx5_flow_drv_type type = mlx5_flow_os_get_type(); 3109 3110 if (type != MLX5_FLOW_TYPE_MAX) 3111 return type; 3112 /* If no OS specific type - continue with DV/VERBS selection */ 3113 if (attr->transfer && priv->config.dv_esw_en) 3114 type = MLX5_FLOW_TYPE_DV; 3115 if (!attr->transfer) 3116 type = priv->config.dv_flow_en ? MLX5_FLOW_TYPE_DV : 3117 MLX5_FLOW_TYPE_VERBS; 3118 return type; 3119 } 3120 3121 #define flow_get_drv_ops(type) flow_drv_ops[type] 3122 3123 /** 3124 * Flow driver validation API. This abstracts calling driver specific functions. 3125 * The type of flow driver is determined according to flow attributes. 3126 * 3127 * @param[in] dev 3128 * Pointer to the dev structure. 3129 * @param[in] attr 3130 * Pointer to the flow attributes. 3131 * @param[in] items 3132 * Pointer to the list of items. 3133 * @param[in] actions 3134 * Pointer to the list of actions. 3135 * @param[in] external 3136 * This flow rule is created by request external to PMD. 3137 * @param[in] hairpin 3138 * Number of hairpin TX actions, 0 means classic flow. 3139 * @param[out] error 3140 * Pointer to the error structure. 3141 * 3142 * @return 3143 * 0 on success, a negative errno value otherwise and rte_errno is set. 3144 */ 3145 static inline int 3146 flow_drv_validate(struct rte_eth_dev *dev, 3147 const struct rte_flow_attr *attr, 3148 const struct rte_flow_item items[], 3149 const struct rte_flow_action actions[], 3150 bool external, int hairpin, struct rte_flow_error *error) 3151 { 3152 const struct mlx5_flow_driver_ops *fops; 3153 enum mlx5_flow_drv_type type = flow_get_drv_type(dev, attr); 3154 3155 fops = flow_get_drv_ops(type); 3156 return fops->validate(dev, attr, items, actions, external, 3157 hairpin, error); 3158 } 3159 3160 /** 3161 * Flow driver preparation API. This abstracts calling driver specific 3162 * functions. Parent flow (rte_flow) should have driver type (drv_type). It 3163 * calculates the size of memory required for device flow, allocates the memory, 3164 * initializes the device flow and returns the pointer. 3165 * 3166 * @note 3167 * This function initializes device flow structure such as dv or verbs in 3168 * struct mlx5_flow. However, it is caller's responsibility to initialize the 3169 * rest. For example, adding returning device flow to flow->dev_flow list and 3170 * setting backward reference to the flow should be done out of this function. 3171 * layers field is not filled either. 3172 * 3173 * @param[in] dev 3174 * Pointer to the dev structure. 3175 * @param[in] attr 3176 * Pointer to the flow attributes. 3177 * @param[in] items 3178 * Pointer to the list of items. 3179 * @param[in] actions 3180 * Pointer to the list of actions. 3181 * @param[in] flow_idx 3182 * This memory pool index to the flow. 3183 * @param[out] error 3184 * Pointer to the error structure. 3185 * 3186 * @return 3187 * Pointer to device flow on success, otherwise NULL and rte_errno is set. 3188 */ 3189 static inline struct mlx5_flow * 3190 flow_drv_prepare(struct rte_eth_dev *dev, 3191 const struct rte_flow *flow, 3192 const struct rte_flow_attr *attr, 3193 const struct rte_flow_item items[], 3194 const struct rte_flow_action actions[], 3195 uint32_t flow_idx, 3196 struct rte_flow_error *error) 3197 { 3198 const struct mlx5_flow_driver_ops *fops; 3199 enum mlx5_flow_drv_type type = flow->drv_type; 3200 struct mlx5_flow *mlx5_flow = NULL; 3201 3202 MLX5_ASSERT(type > MLX5_FLOW_TYPE_MIN && type < MLX5_FLOW_TYPE_MAX); 3203 fops = flow_get_drv_ops(type); 3204 mlx5_flow = fops->prepare(dev, attr, items, actions, error); 3205 if (mlx5_flow) 3206 mlx5_flow->flow_idx = flow_idx; 3207 return mlx5_flow; 3208 } 3209 3210 /** 3211 * Flow driver translation API. This abstracts calling driver specific 3212 * functions. Parent flow (rte_flow) should have driver type (drv_type). It 3213 * translates a generic flow into a driver flow. flow_drv_prepare() must 3214 * precede. 3215 * 3216 * @note 3217 * dev_flow->layers could be filled as a result of parsing during translation 3218 * if needed by flow_drv_apply(). dev_flow->flow->actions can also be filled 3219 * if necessary. As a flow can have multiple dev_flows by RSS flow expansion, 3220 * flow->actions could be overwritten even though all the expanded dev_flows 3221 * have the same actions. 3222 * 3223 * @param[in] dev 3224 * Pointer to the rte dev structure. 3225 * @param[in, out] dev_flow 3226 * Pointer to the mlx5 flow. 3227 * @param[in] attr 3228 * Pointer to the flow attributes. 3229 * @param[in] items 3230 * Pointer to the list of items. 3231 * @param[in] actions 3232 * Pointer to the list of actions. 3233 * @param[out] error 3234 * Pointer to the error structure. 3235 * 3236 * @return 3237 * 0 on success, a negative errno value otherwise and rte_errno is set. 3238 */ 3239 static inline int 3240 flow_drv_translate(struct rte_eth_dev *dev, struct mlx5_flow *dev_flow, 3241 const struct rte_flow_attr *attr, 3242 const struct rte_flow_item items[], 3243 const struct rte_flow_action actions[], 3244 struct rte_flow_error *error) 3245 { 3246 const struct mlx5_flow_driver_ops *fops; 3247 enum mlx5_flow_drv_type type = dev_flow->flow->drv_type; 3248 3249 MLX5_ASSERT(type > MLX5_FLOW_TYPE_MIN && type < MLX5_FLOW_TYPE_MAX); 3250 fops = flow_get_drv_ops(type); 3251 return fops->translate(dev, dev_flow, attr, items, actions, error); 3252 } 3253 3254 /** 3255 * Flow driver apply API. This abstracts calling driver specific functions. 3256 * Parent flow (rte_flow) should have driver type (drv_type). It applies 3257 * translated driver flows on to device. flow_drv_translate() must precede. 3258 * 3259 * @param[in] dev 3260 * Pointer to Ethernet device structure. 3261 * @param[in, out] flow 3262 * Pointer to flow structure. 3263 * @param[out] error 3264 * Pointer to error structure. 3265 * 3266 * @return 3267 * 0 on success, a negative errno value otherwise and rte_errno is set. 3268 */ 3269 static inline int 3270 flow_drv_apply(struct rte_eth_dev *dev, struct rte_flow *flow, 3271 struct rte_flow_error *error) 3272 { 3273 const struct mlx5_flow_driver_ops *fops; 3274 enum mlx5_flow_drv_type type = flow->drv_type; 3275 3276 MLX5_ASSERT(type > MLX5_FLOW_TYPE_MIN && type < MLX5_FLOW_TYPE_MAX); 3277 fops = flow_get_drv_ops(type); 3278 return fops->apply(dev, flow, error); 3279 } 3280 3281 /** 3282 * Flow driver destroy API. This abstracts calling driver specific functions. 3283 * Parent flow (rte_flow) should have driver type (drv_type). It removes a flow 3284 * on device and releases resources of the flow. 3285 * 3286 * @param[in] dev 3287 * Pointer to Ethernet device. 3288 * @param[in, out] flow 3289 * Pointer to flow structure. 3290 */ 3291 static inline void 3292 flow_drv_destroy(struct rte_eth_dev *dev, struct rte_flow *flow) 3293 { 3294 const struct mlx5_flow_driver_ops *fops; 3295 enum mlx5_flow_drv_type type = flow->drv_type; 3296 3297 flow_mreg_split_qrss_release(dev, flow); 3298 MLX5_ASSERT(type > MLX5_FLOW_TYPE_MIN && type < MLX5_FLOW_TYPE_MAX); 3299 fops = flow_get_drv_ops(type); 3300 fops->destroy(dev, flow); 3301 } 3302 3303 /** 3304 * Get RSS action from the action list. 3305 * 3306 * @param[in] actions 3307 * Pointer to the list of actions. 3308 * 3309 * @return 3310 * Pointer to the RSS action if exist, else return NULL. 3311 */ 3312 static const struct rte_flow_action_rss* 3313 flow_get_rss_action(const struct rte_flow_action actions[]) 3314 { 3315 for (; actions->type != RTE_FLOW_ACTION_TYPE_END; actions++) { 3316 switch (actions->type) { 3317 case RTE_FLOW_ACTION_TYPE_RSS: 3318 return (const struct rte_flow_action_rss *) 3319 actions->conf; 3320 default: 3321 break; 3322 } 3323 } 3324 return NULL; 3325 } 3326 3327 /** 3328 * Get ASO age action by index. 3329 * 3330 * @param[in] dev 3331 * Pointer to the Ethernet device structure. 3332 * @param[in] age_idx 3333 * Index to the ASO age action. 3334 * 3335 * @return 3336 * The specified ASO age action. 3337 */ 3338 struct mlx5_aso_age_action* 3339 flow_aso_age_get_by_idx(struct rte_eth_dev *dev, uint32_t age_idx) 3340 { 3341 uint16_t pool_idx = age_idx & UINT16_MAX; 3342 uint16_t offset = (age_idx >> 16) & UINT16_MAX; 3343 struct mlx5_priv *priv = dev->data->dev_private; 3344 struct mlx5_aso_age_mng *mng = priv->sh->aso_age_mng; 3345 struct mlx5_aso_age_pool *pool = mng->pools[pool_idx]; 3346 3347 return &pool->actions[offset - 1]; 3348 } 3349 3350 /* maps shared action to translated non shared in some actions array */ 3351 struct mlx5_translated_shared_action { 3352 struct rte_flow_shared_action *action; /**< Shared action */ 3353 int index; /**< Index in related array of rte_flow_action */ 3354 }; 3355 3356 /** 3357 * Translates actions of type RTE_FLOW_ACTION_TYPE_SHARED to related 3358 * non shared action if translation possible. 3359 * This functionality used to run same execution path for both shared & non 3360 * shared actions on flow create. All necessary preparations for shared 3361 * action handling should be preformed on *shared* actions list returned 3362 * from this call. 3363 * 3364 * @param[in] dev 3365 * Pointer to Ethernet device. 3366 * @param[in] actions 3367 * List of actions to translate. 3368 * @param[out] shared 3369 * List to store translated shared actions. 3370 * @param[in, out] shared_n 3371 * Size of *shared* array. On return should be updated with number of shared 3372 * actions retrieved from the *actions* list. 3373 * @param[out] translated_actions 3374 * List of actions where all shared actions were translated to non shared 3375 * if possible. NULL if no translation took place. 3376 * @param[out] error 3377 * Pointer to the error structure. 3378 * 3379 * @return 3380 * 0 on success, a negative errno value otherwise and rte_errno is set. 3381 */ 3382 static int 3383 flow_shared_actions_translate(struct rte_eth_dev *dev, 3384 const struct rte_flow_action actions[], 3385 struct mlx5_translated_shared_action *shared, 3386 int *shared_n, 3387 struct rte_flow_action **translated_actions, 3388 struct rte_flow_error *error) 3389 { 3390 struct mlx5_priv *priv = dev->data->dev_private; 3391 struct rte_flow_action *translated = NULL; 3392 size_t actions_size; 3393 int n; 3394 int copied_n = 0; 3395 struct mlx5_translated_shared_action *shared_end = NULL; 3396 3397 for (n = 0; actions[n].type != RTE_FLOW_ACTION_TYPE_END; n++) { 3398 if (actions[n].type != RTE_FLOW_ACTION_TYPE_SHARED) 3399 continue; 3400 if (copied_n == *shared_n) { 3401 return rte_flow_error_set 3402 (error, EINVAL, RTE_FLOW_ERROR_TYPE_ACTION_NUM, 3403 NULL, "too many shared actions"); 3404 } 3405 rte_memcpy(&shared[copied_n].action, &actions[n].conf, 3406 sizeof(actions[n].conf)); 3407 shared[copied_n].index = n; 3408 copied_n++; 3409 } 3410 n++; 3411 *shared_n = copied_n; 3412 if (!copied_n) 3413 return 0; 3414 actions_size = sizeof(struct rte_flow_action) * n; 3415 translated = mlx5_malloc(MLX5_MEM_ZERO, actions_size, 0, SOCKET_ID_ANY); 3416 if (!translated) { 3417 rte_errno = ENOMEM; 3418 return -ENOMEM; 3419 } 3420 memcpy(translated, actions, actions_size); 3421 for (shared_end = shared + copied_n; shared < shared_end; shared++) { 3422 struct mlx5_shared_action_rss *shared_rss; 3423 uint32_t act_idx = (uint32_t)(uintptr_t)shared->action; 3424 uint32_t type = act_idx >> MLX5_SHARED_ACTION_TYPE_OFFSET; 3425 uint32_t idx = act_idx & ((1u << MLX5_SHARED_ACTION_TYPE_OFFSET) 3426 - 1); 3427 3428 switch (type) { 3429 case MLX5_SHARED_ACTION_TYPE_RSS: 3430 shared_rss = mlx5_ipool_get 3431 (priv->sh->ipool[MLX5_IPOOL_RSS_SHARED_ACTIONS], idx); 3432 translated[shared->index].type = 3433 RTE_FLOW_ACTION_TYPE_RSS; 3434 translated[shared->index].conf = 3435 &shared_rss->origin; 3436 break; 3437 case MLX5_SHARED_ACTION_TYPE_AGE: 3438 if (priv->sh->flow_hit_aso_en) { 3439 translated[shared->index].type = 3440 (enum rte_flow_action_type) 3441 MLX5_RTE_FLOW_ACTION_TYPE_AGE; 3442 translated[shared->index].conf = 3443 (void *)(uintptr_t)idx; 3444 break; 3445 } 3446 /* Fall-through */ 3447 default: 3448 mlx5_free(translated); 3449 return rte_flow_error_set 3450 (error, EINVAL, RTE_FLOW_ERROR_TYPE_ACTION, 3451 NULL, "invalid shared action type"); 3452 } 3453 } 3454 *translated_actions = translated; 3455 return 0; 3456 } 3457 3458 /** 3459 * Get Shared RSS action from the action list. 3460 * 3461 * @param[in] dev 3462 * Pointer to Ethernet device. 3463 * @param[in] shared 3464 * Pointer to the list of actions. 3465 * @param[in] shared_n 3466 * Actions list length. 3467 * 3468 * @return 3469 * The MLX5 RSS action ID if exists, otherwise return 0. 3470 */ 3471 static uint32_t 3472 flow_get_shared_rss_action(struct rte_eth_dev *dev, 3473 struct mlx5_translated_shared_action *shared, 3474 int shared_n) 3475 { 3476 struct mlx5_translated_shared_action *shared_end; 3477 struct mlx5_priv *priv = dev->data->dev_private; 3478 struct mlx5_shared_action_rss *shared_rss; 3479 3480 3481 for (shared_end = shared + shared_n; shared < shared_end; shared++) { 3482 uint32_t act_idx = (uint32_t)(uintptr_t)shared->action; 3483 uint32_t type = act_idx >> MLX5_SHARED_ACTION_TYPE_OFFSET; 3484 uint32_t idx = act_idx & 3485 ((1u << MLX5_SHARED_ACTION_TYPE_OFFSET) - 1); 3486 switch (type) { 3487 case MLX5_SHARED_ACTION_TYPE_RSS: 3488 shared_rss = mlx5_ipool_get 3489 (priv->sh->ipool[MLX5_IPOOL_RSS_SHARED_ACTIONS], 3490 idx); 3491 __atomic_add_fetch(&shared_rss->refcnt, 1, 3492 __ATOMIC_RELAXED); 3493 return idx; 3494 default: 3495 break; 3496 } 3497 } 3498 return 0; 3499 } 3500 3501 static unsigned int 3502 find_graph_root(const struct rte_flow_item pattern[], uint32_t rss_level) 3503 { 3504 const struct rte_flow_item *item; 3505 unsigned int has_vlan = 0; 3506 3507 for (item = pattern; item->type != RTE_FLOW_ITEM_TYPE_END; item++) { 3508 if (item->type == RTE_FLOW_ITEM_TYPE_VLAN) { 3509 has_vlan = 1; 3510 break; 3511 } 3512 } 3513 if (has_vlan) 3514 return rss_level < 2 ? MLX5_EXPANSION_ROOT_ETH_VLAN : 3515 MLX5_EXPANSION_ROOT_OUTER_ETH_VLAN; 3516 return rss_level < 2 ? MLX5_EXPANSION_ROOT : 3517 MLX5_EXPANSION_ROOT_OUTER; 3518 } 3519 3520 /** 3521 * Get layer flags from the prefix flow. 3522 * 3523 * Some flows may be split to several subflows, the prefix subflow gets the 3524 * match items and the suffix sub flow gets the actions. 3525 * Some actions need the user defined match item flags to get the detail for 3526 * the action. 3527 * This function helps the suffix flow to get the item layer flags from prefix 3528 * subflow. 3529 * 3530 * @param[in] dev_flow 3531 * Pointer the created preifx subflow. 3532 * 3533 * @return 3534 * The layers get from prefix subflow. 3535 */ 3536 static inline uint64_t 3537 flow_get_prefix_layer_flags(struct mlx5_flow *dev_flow) 3538 { 3539 uint64_t layers = 0; 3540 3541 /* 3542 * Layers bits could be localization, but usually the compiler will 3543 * help to do the optimization work for source code. 3544 * If no decap actions, use the layers directly. 3545 */ 3546 if (!(dev_flow->act_flags & MLX5_FLOW_ACTION_DECAP)) 3547 return dev_flow->handle->layers; 3548 /* Convert L3 layers with decap action. */ 3549 if (dev_flow->handle->layers & MLX5_FLOW_LAYER_INNER_L3_IPV4) 3550 layers |= MLX5_FLOW_LAYER_OUTER_L3_IPV4; 3551 else if (dev_flow->handle->layers & MLX5_FLOW_LAYER_INNER_L3_IPV6) 3552 layers |= MLX5_FLOW_LAYER_OUTER_L3_IPV6; 3553 /* Convert L4 layers with decap action. */ 3554 if (dev_flow->handle->layers & MLX5_FLOW_LAYER_INNER_L4_TCP) 3555 layers |= MLX5_FLOW_LAYER_OUTER_L4_TCP; 3556 else if (dev_flow->handle->layers & MLX5_FLOW_LAYER_INNER_L4_UDP) 3557 layers |= MLX5_FLOW_LAYER_OUTER_L4_UDP; 3558 return layers; 3559 } 3560 3561 /** 3562 * Get metadata split action information. 3563 * 3564 * @param[in] actions 3565 * Pointer to the list of actions. 3566 * @param[out] qrss 3567 * Pointer to the return pointer. 3568 * @param[out] qrss_type 3569 * Pointer to the action type to return. RTE_FLOW_ACTION_TYPE_END is returned 3570 * if no QUEUE/RSS is found. 3571 * @param[out] encap_idx 3572 * Pointer to the index of the encap action if exists, otherwise the last 3573 * action index. 3574 * 3575 * @return 3576 * Total number of actions. 3577 */ 3578 static int 3579 flow_parse_metadata_split_actions_info(const struct rte_flow_action actions[], 3580 const struct rte_flow_action **qrss, 3581 int *encap_idx) 3582 { 3583 const struct rte_flow_action_raw_encap *raw_encap; 3584 int actions_n = 0; 3585 int raw_decap_idx = -1; 3586 3587 *encap_idx = -1; 3588 for (; actions->type != RTE_FLOW_ACTION_TYPE_END; actions++) { 3589 switch (actions->type) { 3590 case RTE_FLOW_ACTION_TYPE_VXLAN_ENCAP: 3591 case RTE_FLOW_ACTION_TYPE_NVGRE_ENCAP: 3592 *encap_idx = actions_n; 3593 break; 3594 case RTE_FLOW_ACTION_TYPE_RAW_DECAP: 3595 raw_decap_idx = actions_n; 3596 break; 3597 case RTE_FLOW_ACTION_TYPE_RAW_ENCAP: 3598 raw_encap = actions->conf; 3599 if (raw_encap->size > MLX5_ENCAPSULATION_DECISION_SIZE) 3600 *encap_idx = raw_decap_idx != -1 ? 3601 raw_decap_idx : actions_n; 3602 break; 3603 case RTE_FLOW_ACTION_TYPE_QUEUE: 3604 case RTE_FLOW_ACTION_TYPE_RSS: 3605 *qrss = actions; 3606 break; 3607 default: 3608 break; 3609 } 3610 actions_n++; 3611 } 3612 if (*encap_idx == -1) 3613 *encap_idx = actions_n; 3614 /* Count RTE_FLOW_ACTION_TYPE_END. */ 3615 return actions_n + 1; 3616 } 3617 3618 /** 3619 * Check meter action from the action list. 3620 * 3621 * @param[in] actions 3622 * Pointer to the list of actions. 3623 * @param[out] mtr 3624 * Pointer to the meter exist flag. 3625 * 3626 * @return 3627 * Total number of actions. 3628 */ 3629 static int 3630 flow_check_meter_action(const struct rte_flow_action actions[], uint32_t *mtr) 3631 { 3632 int actions_n = 0; 3633 3634 MLX5_ASSERT(mtr); 3635 *mtr = 0; 3636 for (; actions->type != RTE_FLOW_ACTION_TYPE_END; actions++) { 3637 switch (actions->type) { 3638 case RTE_FLOW_ACTION_TYPE_METER: 3639 *mtr = 1; 3640 break; 3641 default: 3642 break; 3643 } 3644 actions_n++; 3645 } 3646 /* Count RTE_FLOW_ACTION_TYPE_END. */ 3647 return actions_n + 1; 3648 } 3649 3650 /** 3651 * Check if the flow should be split due to hairpin. 3652 * The reason for the split is that in current HW we can't 3653 * support encap and push-vlan on Rx, so if a flow contains 3654 * these actions we move it to Tx. 3655 * 3656 * @param dev 3657 * Pointer to Ethernet device. 3658 * @param[in] attr 3659 * Flow rule attributes. 3660 * @param[in] actions 3661 * Associated actions (list terminated by the END action). 3662 * 3663 * @return 3664 * > 0 the number of actions and the flow should be split, 3665 * 0 when no split required. 3666 */ 3667 static int 3668 flow_check_hairpin_split(struct rte_eth_dev *dev, 3669 const struct rte_flow_attr *attr, 3670 const struct rte_flow_action actions[]) 3671 { 3672 int queue_action = 0; 3673 int action_n = 0; 3674 int split = 0; 3675 const struct rte_flow_action_queue *queue; 3676 const struct rte_flow_action_rss *rss; 3677 const struct rte_flow_action_raw_encap *raw_encap; 3678 const struct rte_eth_hairpin_conf *conf; 3679 3680 if (!attr->ingress) 3681 return 0; 3682 for (; actions->type != RTE_FLOW_ACTION_TYPE_END; actions++) { 3683 switch (actions->type) { 3684 case RTE_FLOW_ACTION_TYPE_QUEUE: 3685 queue = actions->conf; 3686 if (queue == NULL) 3687 return 0; 3688 conf = mlx5_rxq_get_hairpin_conf(dev, queue->index); 3689 if (conf == NULL || conf->tx_explicit != 0) 3690 return 0; 3691 queue_action = 1; 3692 action_n++; 3693 break; 3694 case RTE_FLOW_ACTION_TYPE_RSS: 3695 rss = actions->conf; 3696 if (rss == NULL || rss->queue_num == 0) 3697 return 0; 3698 conf = mlx5_rxq_get_hairpin_conf(dev, rss->queue[0]); 3699 if (conf == NULL || conf->tx_explicit != 0) 3700 return 0; 3701 queue_action = 1; 3702 action_n++; 3703 break; 3704 case RTE_FLOW_ACTION_TYPE_VXLAN_ENCAP: 3705 case RTE_FLOW_ACTION_TYPE_NVGRE_ENCAP: 3706 case RTE_FLOW_ACTION_TYPE_OF_PUSH_VLAN: 3707 case RTE_FLOW_ACTION_TYPE_OF_SET_VLAN_VID: 3708 case RTE_FLOW_ACTION_TYPE_OF_SET_VLAN_PCP: 3709 split++; 3710 action_n++; 3711 break; 3712 case RTE_FLOW_ACTION_TYPE_RAW_ENCAP: 3713 raw_encap = actions->conf; 3714 if (raw_encap->size > MLX5_ENCAPSULATION_DECISION_SIZE) 3715 split++; 3716 action_n++; 3717 break; 3718 default: 3719 action_n++; 3720 break; 3721 } 3722 } 3723 if (split && queue_action) 3724 return action_n; 3725 return 0; 3726 } 3727 3728 /* Declare flow create/destroy prototype in advance. */ 3729 static uint32_t 3730 flow_list_create(struct rte_eth_dev *dev, uint32_t *list, 3731 const struct rte_flow_attr *attr, 3732 const struct rte_flow_item items[], 3733 const struct rte_flow_action actions[], 3734 bool external, struct rte_flow_error *error); 3735 3736 static void 3737 flow_list_destroy(struct rte_eth_dev *dev, uint32_t *list, 3738 uint32_t flow_idx); 3739 3740 int 3741 flow_dv_mreg_match_cb(struct mlx5_hlist *list __rte_unused, 3742 struct mlx5_hlist_entry *entry, 3743 uint64_t key, void *cb_ctx __rte_unused) 3744 { 3745 struct mlx5_flow_mreg_copy_resource *mcp_res = 3746 container_of(entry, typeof(*mcp_res), hlist_ent); 3747 3748 return mcp_res->mark_id != key; 3749 } 3750 3751 struct mlx5_hlist_entry * 3752 flow_dv_mreg_create_cb(struct mlx5_hlist *list, uint64_t key, 3753 void *cb_ctx) 3754 { 3755 struct rte_eth_dev *dev = list->ctx; 3756 struct mlx5_priv *priv = dev->data->dev_private; 3757 struct mlx5_flow_cb_ctx *ctx = cb_ctx; 3758 struct mlx5_flow_mreg_copy_resource *mcp_res; 3759 struct rte_flow_error *error = ctx->error; 3760 uint32_t idx = 0; 3761 int ret; 3762 uint32_t mark_id = key; 3763 struct rte_flow_attr attr = { 3764 .group = MLX5_FLOW_MREG_CP_TABLE_GROUP, 3765 .ingress = 1, 3766 }; 3767 struct mlx5_rte_flow_item_tag tag_spec = { 3768 .data = mark_id, 3769 }; 3770 struct rte_flow_item items[] = { 3771 [1] = { .type = RTE_FLOW_ITEM_TYPE_END, }, 3772 }; 3773 struct rte_flow_action_mark ftag = { 3774 .id = mark_id, 3775 }; 3776 struct mlx5_flow_action_copy_mreg cp_mreg = { 3777 .dst = REG_B, 3778 .src = REG_NON, 3779 }; 3780 struct rte_flow_action_jump jump = { 3781 .group = MLX5_FLOW_MREG_ACT_TABLE_GROUP, 3782 }; 3783 struct rte_flow_action actions[] = { 3784 [3] = { .type = RTE_FLOW_ACTION_TYPE_END, }, 3785 }; 3786 3787 /* Fill the register fileds in the flow. */ 3788 ret = mlx5_flow_get_reg_id(dev, MLX5_FLOW_MARK, 0, error); 3789 if (ret < 0) 3790 return NULL; 3791 tag_spec.id = ret; 3792 ret = mlx5_flow_get_reg_id(dev, MLX5_METADATA_RX, 0, error); 3793 if (ret < 0) 3794 return NULL; 3795 cp_mreg.src = ret; 3796 /* Provide the full width of FLAG specific value. */ 3797 if (mark_id == (priv->sh->dv_regc0_mask & MLX5_FLOW_MARK_DEFAULT)) 3798 tag_spec.data = MLX5_FLOW_MARK_DEFAULT; 3799 /* Build a new flow. */ 3800 if (mark_id != MLX5_DEFAULT_COPY_ID) { 3801 items[0] = (struct rte_flow_item){ 3802 .type = (enum rte_flow_item_type) 3803 MLX5_RTE_FLOW_ITEM_TYPE_TAG, 3804 .spec = &tag_spec, 3805 }; 3806 items[1] = (struct rte_flow_item){ 3807 .type = RTE_FLOW_ITEM_TYPE_END, 3808 }; 3809 actions[0] = (struct rte_flow_action){ 3810 .type = (enum rte_flow_action_type) 3811 MLX5_RTE_FLOW_ACTION_TYPE_MARK, 3812 .conf = &ftag, 3813 }; 3814 actions[1] = (struct rte_flow_action){ 3815 .type = (enum rte_flow_action_type) 3816 MLX5_RTE_FLOW_ACTION_TYPE_COPY_MREG, 3817 .conf = &cp_mreg, 3818 }; 3819 actions[2] = (struct rte_flow_action){ 3820 .type = RTE_FLOW_ACTION_TYPE_JUMP, 3821 .conf = &jump, 3822 }; 3823 actions[3] = (struct rte_flow_action){ 3824 .type = RTE_FLOW_ACTION_TYPE_END, 3825 }; 3826 } else { 3827 /* Default rule, wildcard match. */ 3828 attr.priority = MLX5_FLOW_PRIO_RSVD; 3829 items[0] = (struct rte_flow_item){ 3830 .type = RTE_FLOW_ITEM_TYPE_END, 3831 }; 3832 actions[0] = (struct rte_flow_action){ 3833 .type = (enum rte_flow_action_type) 3834 MLX5_RTE_FLOW_ACTION_TYPE_COPY_MREG, 3835 .conf = &cp_mreg, 3836 }; 3837 actions[1] = (struct rte_flow_action){ 3838 .type = RTE_FLOW_ACTION_TYPE_JUMP, 3839 .conf = &jump, 3840 }; 3841 actions[2] = (struct rte_flow_action){ 3842 .type = RTE_FLOW_ACTION_TYPE_END, 3843 }; 3844 } 3845 /* Build a new entry. */ 3846 mcp_res = mlx5_ipool_zmalloc(priv->sh->ipool[MLX5_IPOOL_MCP], &idx); 3847 if (!mcp_res) { 3848 rte_errno = ENOMEM; 3849 return NULL; 3850 } 3851 mcp_res->idx = idx; 3852 mcp_res->mark_id = mark_id; 3853 /* 3854 * The copy Flows are not included in any list. There 3855 * ones are referenced from other Flows and can not 3856 * be applied, removed, deleted in ardbitrary order 3857 * by list traversing. 3858 */ 3859 mcp_res->rix_flow = flow_list_create(dev, NULL, &attr, items, 3860 actions, false, error); 3861 if (!mcp_res->rix_flow) { 3862 mlx5_ipool_free(priv->sh->ipool[MLX5_IPOOL_MCP], idx); 3863 return NULL; 3864 } 3865 return &mcp_res->hlist_ent; 3866 } 3867 3868 /** 3869 * Add a flow of copying flow metadata registers in RX_CP_TBL. 3870 * 3871 * As mark_id is unique, if there's already a registered flow for the mark_id, 3872 * return by increasing the reference counter of the resource. Otherwise, create 3873 * the resource (mcp_res) and flow. 3874 * 3875 * Flow looks like, 3876 * - If ingress port is ANY and reg_c[1] is mark_id, 3877 * flow_tag := mark_id, reg_b := reg_c[0] and jump to RX_ACT_TBL. 3878 * 3879 * For default flow (zero mark_id), flow is like, 3880 * - If ingress port is ANY, 3881 * reg_b := reg_c[0] and jump to RX_ACT_TBL. 3882 * 3883 * @param dev 3884 * Pointer to Ethernet device. 3885 * @param mark_id 3886 * ID of MARK action, zero means default flow for META. 3887 * @param[out] error 3888 * Perform verbose error reporting if not NULL. 3889 * 3890 * @return 3891 * Associated resource on success, NULL otherwise and rte_errno is set. 3892 */ 3893 static struct mlx5_flow_mreg_copy_resource * 3894 flow_mreg_add_copy_action(struct rte_eth_dev *dev, uint32_t mark_id, 3895 struct rte_flow_error *error) 3896 { 3897 struct mlx5_priv *priv = dev->data->dev_private; 3898 struct mlx5_hlist_entry *entry; 3899 struct mlx5_flow_cb_ctx ctx = { 3900 .dev = dev, 3901 .error = error, 3902 }; 3903 3904 /* Check if already registered. */ 3905 MLX5_ASSERT(priv->mreg_cp_tbl); 3906 entry = mlx5_hlist_register(priv->mreg_cp_tbl, mark_id, &ctx); 3907 if (!entry) 3908 return NULL; 3909 return container_of(entry, struct mlx5_flow_mreg_copy_resource, 3910 hlist_ent); 3911 } 3912 3913 void 3914 flow_dv_mreg_remove_cb(struct mlx5_hlist *list, struct mlx5_hlist_entry *entry) 3915 { 3916 struct mlx5_flow_mreg_copy_resource *mcp_res = 3917 container_of(entry, typeof(*mcp_res), hlist_ent); 3918 struct rte_eth_dev *dev = list->ctx; 3919 struct mlx5_priv *priv = dev->data->dev_private; 3920 3921 MLX5_ASSERT(mcp_res->rix_flow); 3922 flow_list_destroy(dev, NULL, mcp_res->rix_flow); 3923 mlx5_ipool_free(priv->sh->ipool[MLX5_IPOOL_MCP], mcp_res->idx); 3924 } 3925 3926 /** 3927 * Release flow in RX_CP_TBL. 3928 * 3929 * @param dev 3930 * Pointer to Ethernet device. 3931 * @flow 3932 * Parent flow for wich copying is provided. 3933 */ 3934 static void 3935 flow_mreg_del_copy_action(struct rte_eth_dev *dev, 3936 struct rte_flow *flow) 3937 { 3938 struct mlx5_flow_mreg_copy_resource *mcp_res; 3939 struct mlx5_priv *priv = dev->data->dev_private; 3940 3941 if (!flow->rix_mreg_copy) 3942 return; 3943 mcp_res = mlx5_ipool_get(priv->sh->ipool[MLX5_IPOOL_MCP], 3944 flow->rix_mreg_copy); 3945 if (!mcp_res || !priv->mreg_cp_tbl) 3946 return; 3947 MLX5_ASSERT(mcp_res->rix_flow); 3948 mlx5_hlist_unregister(priv->mreg_cp_tbl, &mcp_res->hlist_ent); 3949 flow->rix_mreg_copy = 0; 3950 } 3951 3952 /** 3953 * Remove the default copy action from RX_CP_TBL. 3954 * 3955 * This functions is called in the mlx5_dev_start(). No thread safe 3956 * is guaranteed. 3957 * 3958 * @param dev 3959 * Pointer to Ethernet device. 3960 */ 3961 static void 3962 flow_mreg_del_default_copy_action(struct rte_eth_dev *dev) 3963 { 3964 struct mlx5_hlist_entry *entry; 3965 struct mlx5_priv *priv = dev->data->dev_private; 3966 3967 /* Check if default flow is registered. */ 3968 if (!priv->mreg_cp_tbl) 3969 return; 3970 entry = mlx5_hlist_lookup(priv->mreg_cp_tbl, 3971 MLX5_DEFAULT_COPY_ID, NULL); 3972 if (!entry) 3973 return; 3974 mlx5_hlist_unregister(priv->mreg_cp_tbl, entry); 3975 } 3976 3977 /** 3978 * Add the default copy action in in RX_CP_TBL. 3979 * 3980 * This functions is called in the mlx5_dev_start(). No thread safe 3981 * is guaranteed. 3982 * 3983 * @param dev 3984 * Pointer to Ethernet device. 3985 * @param[out] error 3986 * Perform verbose error reporting if not NULL. 3987 * 3988 * @return 3989 * 0 for success, negative value otherwise and rte_errno is set. 3990 */ 3991 static int 3992 flow_mreg_add_default_copy_action(struct rte_eth_dev *dev, 3993 struct rte_flow_error *error) 3994 { 3995 struct mlx5_priv *priv = dev->data->dev_private; 3996 struct mlx5_flow_mreg_copy_resource *mcp_res; 3997 3998 /* Check whether extensive metadata feature is engaged. */ 3999 if (!priv->config.dv_flow_en || 4000 priv->config.dv_xmeta_en == MLX5_XMETA_MODE_LEGACY || 4001 !mlx5_flow_ext_mreg_supported(dev) || 4002 !priv->sh->dv_regc0_mask) 4003 return 0; 4004 /* 4005 * Add default mreg copy flow may be called multiple time, but 4006 * only be called once in stop. Avoid register it twice. 4007 */ 4008 if (mlx5_hlist_lookup(priv->mreg_cp_tbl, MLX5_DEFAULT_COPY_ID, NULL)) 4009 return 0; 4010 mcp_res = flow_mreg_add_copy_action(dev, MLX5_DEFAULT_COPY_ID, error); 4011 if (!mcp_res) 4012 return -rte_errno; 4013 return 0; 4014 } 4015 4016 /** 4017 * Add a flow of copying flow metadata registers in RX_CP_TBL. 4018 * 4019 * All the flow having Q/RSS action should be split by 4020 * flow_mreg_split_qrss_prep() to pass by RX_CP_TBL. A flow in the RX_CP_TBL 4021 * performs the following, 4022 * - CQE->flow_tag := reg_c[1] (MARK) 4023 * - CQE->flow_table_metadata (reg_b) := reg_c[0] (META) 4024 * As CQE's flow_tag is not a register, it can't be simply copied from reg_c[1] 4025 * but there should be a flow per each MARK ID set by MARK action. 4026 * 4027 * For the aforementioned reason, if there's a MARK action in flow's action 4028 * list, a corresponding flow should be added to the RX_CP_TBL in order to copy 4029 * the MARK ID to CQE's flow_tag like, 4030 * - If reg_c[1] is mark_id, 4031 * flow_tag := mark_id, reg_b := reg_c[0] and jump to RX_ACT_TBL. 4032 * 4033 * For SET_META action which stores value in reg_c[0], as the destination is 4034 * also a flow metadata register (reg_b), adding a default flow is enough. Zero 4035 * MARK ID means the default flow. The default flow looks like, 4036 * - For all flow, reg_b := reg_c[0] and jump to RX_ACT_TBL. 4037 * 4038 * @param dev 4039 * Pointer to Ethernet device. 4040 * @param flow 4041 * Pointer to flow structure. 4042 * @param[in] actions 4043 * Pointer to the list of actions. 4044 * @param[out] error 4045 * Perform verbose error reporting if not NULL. 4046 * 4047 * @return 4048 * 0 on success, negative value otherwise and rte_errno is set. 4049 */ 4050 static int 4051 flow_mreg_update_copy_table(struct rte_eth_dev *dev, 4052 struct rte_flow *flow, 4053 const struct rte_flow_action *actions, 4054 struct rte_flow_error *error) 4055 { 4056 struct mlx5_priv *priv = dev->data->dev_private; 4057 struct mlx5_dev_config *config = &priv->config; 4058 struct mlx5_flow_mreg_copy_resource *mcp_res; 4059 const struct rte_flow_action_mark *mark; 4060 4061 /* Check whether extensive metadata feature is engaged. */ 4062 if (!config->dv_flow_en || 4063 config->dv_xmeta_en == MLX5_XMETA_MODE_LEGACY || 4064 !mlx5_flow_ext_mreg_supported(dev) || 4065 !priv->sh->dv_regc0_mask) 4066 return 0; 4067 /* Find MARK action. */ 4068 for (; actions->type != RTE_FLOW_ACTION_TYPE_END; actions++) { 4069 switch (actions->type) { 4070 case RTE_FLOW_ACTION_TYPE_FLAG: 4071 mcp_res = flow_mreg_add_copy_action 4072 (dev, MLX5_FLOW_MARK_DEFAULT, error); 4073 if (!mcp_res) 4074 return -rte_errno; 4075 flow->rix_mreg_copy = mcp_res->idx; 4076 return 0; 4077 case RTE_FLOW_ACTION_TYPE_MARK: 4078 mark = (const struct rte_flow_action_mark *) 4079 actions->conf; 4080 mcp_res = 4081 flow_mreg_add_copy_action(dev, mark->id, error); 4082 if (!mcp_res) 4083 return -rte_errno; 4084 flow->rix_mreg_copy = mcp_res->idx; 4085 return 0; 4086 default: 4087 break; 4088 } 4089 } 4090 return 0; 4091 } 4092 4093 #define MLX5_MAX_SPLIT_ACTIONS 24 4094 #define MLX5_MAX_SPLIT_ITEMS 24 4095 4096 /** 4097 * Split the hairpin flow. 4098 * Since HW can't support encap and push-vlan on Rx, we move these 4099 * actions to Tx. 4100 * If the count action is after the encap then we also 4101 * move the count action. in this case the count will also measure 4102 * the outer bytes. 4103 * 4104 * @param dev 4105 * Pointer to Ethernet device. 4106 * @param[in] actions 4107 * Associated actions (list terminated by the END action). 4108 * @param[out] actions_rx 4109 * Rx flow actions. 4110 * @param[out] actions_tx 4111 * Tx flow actions.. 4112 * @param[out] pattern_tx 4113 * The pattern items for the Tx flow. 4114 * @param[out] flow_id 4115 * The flow ID connected to this flow. 4116 * 4117 * @return 4118 * 0 on success. 4119 */ 4120 static int 4121 flow_hairpin_split(struct rte_eth_dev *dev, 4122 const struct rte_flow_action actions[], 4123 struct rte_flow_action actions_rx[], 4124 struct rte_flow_action actions_tx[], 4125 struct rte_flow_item pattern_tx[], 4126 uint32_t flow_id) 4127 { 4128 const struct rte_flow_action_raw_encap *raw_encap; 4129 const struct rte_flow_action_raw_decap *raw_decap; 4130 struct mlx5_rte_flow_action_set_tag *set_tag; 4131 struct rte_flow_action *tag_action; 4132 struct mlx5_rte_flow_item_tag *tag_item; 4133 struct rte_flow_item *item; 4134 char *addr; 4135 int encap = 0; 4136 4137 for (; actions->type != RTE_FLOW_ACTION_TYPE_END; actions++) { 4138 switch (actions->type) { 4139 case RTE_FLOW_ACTION_TYPE_VXLAN_ENCAP: 4140 case RTE_FLOW_ACTION_TYPE_NVGRE_ENCAP: 4141 case RTE_FLOW_ACTION_TYPE_OF_PUSH_VLAN: 4142 case RTE_FLOW_ACTION_TYPE_OF_SET_VLAN_VID: 4143 case RTE_FLOW_ACTION_TYPE_OF_SET_VLAN_PCP: 4144 rte_memcpy(actions_tx, actions, 4145 sizeof(struct rte_flow_action)); 4146 actions_tx++; 4147 break; 4148 case RTE_FLOW_ACTION_TYPE_COUNT: 4149 if (encap) { 4150 rte_memcpy(actions_tx, actions, 4151 sizeof(struct rte_flow_action)); 4152 actions_tx++; 4153 } else { 4154 rte_memcpy(actions_rx, actions, 4155 sizeof(struct rte_flow_action)); 4156 actions_rx++; 4157 } 4158 break; 4159 case RTE_FLOW_ACTION_TYPE_RAW_ENCAP: 4160 raw_encap = actions->conf; 4161 if (raw_encap->size > MLX5_ENCAPSULATION_DECISION_SIZE) { 4162 memcpy(actions_tx, actions, 4163 sizeof(struct rte_flow_action)); 4164 actions_tx++; 4165 encap = 1; 4166 } else { 4167 rte_memcpy(actions_rx, actions, 4168 sizeof(struct rte_flow_action)); 4169 actions_rx++; 4170 } 4171 break; 4172 case RTE_FLOW_ACTION_TYPE_RAW_DECAP: 4173 raw_decap = actions->conf; 4174 if (raw_decap->size < MLX5_ENCAPSULATION_DECISION_SIZE) { 4175 memcpy(actions_tx, actions, 4176 sizeof(struct rte_flow_action)); 4177 actions_tx++; 4178 } else { 4179 rte_memcpy(actions_rx, actions, 4180 sizeof(struct rte_flow_action)); 4181 actions_rx++; 4182 } 4183 break; 4184 default: 4185 rte_memcpy(actions_rx, actions, 4186 sizeof(struct rte_flow_action)); 4187 actions_rx++; 4188 break; 4189 } 4190 } 4191 /* Add set meta action and end action for the Rx flow. */ 4192 tag_action = actions_rx; 4193 tag_action->type = (enum rte_flow_action_type) 4194 MLX5_RTE_FLOW_ACTION_TYPE_TAG; 4195 actions_rx++; 4196 rte_memcpy(actions_rx, actions, sizeof(struct rte_flow_action)); 4197 actions_rx++; 4198 set_tag = (void *)actions_rx; 4199 set_tag->id = mlx5_flow_get_reg_id(dev, MLX5_HAIRPIN_RX, 0, NULL); 4200 MLX5_ASSERT(set_tag->id > REG_NON); 4201 set_tag->data = flow_id; 4202 tag_action->conf = set_tag; 4203 /* Create Tx item list. */ 4204 rte_memcpy(actions_tx, actions, sizeof(struct rte_flow_action)); 4205 addr = (void *)&pattern_tx[2]; 4206 item = pattern_tx; 4207 item->type = (enum rte_flow_item_type) 4208 MLX5_RTE_FLOW_ITEM_TYPE_TAG; 4209 tag_item = (void *)addr; 4210 tag_item->data = flow_id; 4211 tag_item->id = mlx5_flow_get_reg_id(dev, MLX5_HAIRPIN_TX, 0, NULL); 4212 MLX5_ASSERT(set_tag->id > REG_NON); 4213 item->spec = tag_item; 4214 addr += sizeof(struct mlx5_rte_flow_item_tag); 4215 tag_item = (void *)addr; 4216 tag_item->data = UINT32_MAX; 4217 tag_item->id = UINT16_MAX; 4218 item->mask = tag_item; 4219 item->last = NULL; 4220 item++; 4221 item->type = RTE_FLOW_ITEM_TYPE_END; 4222 return 0; 4223 } 4224 4225 /** 4226 * The last stage of splitting chain, just creates the subflow 4227 * without any modification. 4228 * 4229 * @param[in] dev 4230 * Pointer to Ethernet device. 4231 * @param[in] flow 4232 * Parent flow structure pointer. 4233 * @param[in, out] sub_flow 4234 * Pointer to return the created subflow, may be NULL. 4235 * @param[in] attr 4236 * Flow rule attributes. 4237 * @param[in] items 4238 * Pattern specification (list terminated by the END pattern item). 4239 * @param[in] actions 4240 * Associated actions (list terminated by the END action). 4241 * @param[in] flow_split_info 4242 * Pointer to flow split info structure. 4243 * @param[out] error 4244 * Perform verbose error reporting if not NULL. 4245 * @return 4246 * 0 on success, negative value otherwise 4247 */ 4248 static int 4249 flow_create_split_inner(struct rte_eth_dev *dev, 4250 struct rte_flow *flow, 4251 struct mlx5_flow **sub_flow, 4252 const struct rte_flow_attr *attr, 4253 const struct rte_flow_item items[], 4254 const struct rte_flow_action actions[], 4255 struct mlx5_flow_split_info *flow_split_info, 4256 struct rte_flow_error *error) 4257 { 4258 struct mlx5_flow *dev_flow; 4259 4260 dev_flow = flow_drv_prepare(dev, flow, attr, items, actions, 4261 flow_split_info->flow_idx, error); 4262 if (!dev_flow) 4263 return -rte_errno; 4264 dev_flow->flow = flow; 4265 dev_flow->external = flow_split_info->external; 4266 dev_flow->skip_scale = flow_split_info->skip_scale; 4267 /* Subflow object was created, we must include one in the list. */ 4268 SILIST_INSERT(&flow->dev_handles, dev_flow->handle_idx, 4269 dev_flow->handle, next); 4270 /* 4271 * If dev_flow is as one of the suffix flow, some actions in suffix 4272 * flow may need some user defined item layer flags, and pass the 4273 * Metadate rxq mark flag to suffix flow as well. 4274 */ 4275 if (flow_split_info->prefix_layers) 4276 dev_flow->handle->layers = flow_split_info->prefix_layers; 4277 if (flow_split_info->prefix_mark) 4278 dev_flow->handle->mark = 1; 4279 if (sub_flow) 4280 *sub_flow = dev_flow; 4281 return flow_drv_translate(dev, dev_flow, attr, items, actions, error); 4282 } 4283 4284 /** 4285 * Split the meter flow. 4286 * 4287 * As meter flow will split to three sub flow, other than meter 4288 * action, the other actions make sense to only meter accepts 4289 * the packet. If it need to be dropped, no other additional 4290 * actions should be take. 4291 * 4292 * One kind of special action which decapsulates the L3 tunnel 4293 * header will be in the prefix sub flow, as not to take the 4294 * L3 tunnel header into account. 4295 * 4296 * @param dev 4297 * Pointer to Ethernet device. 4298 * @param[in] items 4299 * Pattern specification (list terminated by the END pattern item). 4300 * @param[out] sfx_items 4301 * Suffix flow match items (list terminated by the END pattern item). 4302 * @param[in] actions 4303 * Associated actions (list terminated by the END action). 4304 * @param[out] actions_sfx 4305 * Suffix flow actions. 4306 * @param[out] actions_pre 4307 * Prefix flow actions. 4308 * @param[out] pattern_sfx 4309 * The pattern items for the suffix flow. 4310 * @param[out] tag_sfx 4311 * Pointer to suffix flow tag. 4312 * 4313 * @return 4314 * 0 on success. 4315 */ 4316 static int 4317 flow_meter_split_prep(struct rte_eth_dev *dev, 4318 const struct rte_flow_item items[], 4319 struct rte_flow_item sfx_items[], 4320 const struct rte_flow_action actions[], 4321 struct rte_flow_action actions_sfx[], 4322 struct rte_flow_action actions_pre[]) 4323 { 4324 struct mlx5_priv *priv = dev->data->dev_private; 4325 struct rte_flow_action *tag_action = NULL; 4326 struct rte_flow_item *tag_item; 4327 struct mlx5_rte_flow_action_set_tag *set_tag; 4328 struct rte_flow_error error; 4329 const struct rte_flow_action_raw_encap *raw_encap; 4330 const struct rte_flow_action_raw_decap *raw_decap; 4331 struct mlx5_rte_flow_item_tag *tag_spec; 4332 struct mlx5_rte_flow_item_tag *tag_mask; 4333 uint32_t tag_id = 0; 4334 bool copy_vlan = false; 4335 4336 /* Prepare the actions for prefix and suffix flow. */ 4337 for (; actions->type != RTE_FLOW_ACTION_TYPE_END; actions++) { 4338 struct rte_flow_action **action_cur = NULL; 4339 4340 switch (actions->type) { 4341 case RTE_FLOW_ACTION_TYPE_METER: 4342 /* Add the extra tag action first. */ 4343 tag_action = actions_pre; 4344 tag_action->type = (enum rte_flow_action_type) 4345 MLX5_RTE_FLOW_ACTION_TYPE_TAG; 4346 actions_pre++; 4347 action_cur = &actions_pre; 4348 break; 4349 case RTE_FLOW_ACTION_TYPE_VXLAN_DECAP: 4350 case RTE_FLOW_ACTION_TYPE_NVGRE_DECAP: 4351 action_cur = &actions_pre; 4352 break; 4353 case RTE_FLOW_ACTION_TYPE_RAW_ENCAP: 4354 raw_encap = actions->conf; 4355 if (raw_encap->size < MLX5_ENCAPSULATION_DECISION_SIZE) 4356 action_cur = &actions_pre; 4357 break; 4358 case RTE_FLOW_ACTION_TYPE_RAW_DECAP: 4359 raw_decap = actions->conf; 4360 if (raw_decap->size > MLX5_ENCAPSULATION_DECISION_SIZE) 4361 action_cur = &actions_pre; 4362 break; 4363 case RTE_FLOW_ACTION_TYPE_OF_PUSH_VLAN: 4364 case RTE_FLOW_ACTION_TYPE_OF_SET_VLAN_VID: 4365 copy_vlan = true; 4366 break; 4367 default: 4368 break; 4369 } 4370 if (!action_cur) 4371 action_cur = &actions_sfx; 4372 memcpy(*action_cur, actions, sizeof(struct rte_flow_action)); 4373 (*action_cur)++; 4374 } 4375 /* Add end action to the actions. */ 4376 actions_sfx->type = RTE_FLOW_ACTION_TYPE_END; 4377 actions_pre->type = RTE_FLOW_ACTION_TYPE_END; 4378 actions_pre++; 4379 /* Set the tag. */ 4380 set_tag = (void *)actions_pre; 4381 set_tag->id = mlx5_flow_get_reg_id(dev, MLX5_MTR_SFX, 0, &error); 4382 mlx5_ipool_malloc(priv->sh->ipool[MLX5_IPOOL_RSS_EXPANTION_FLOW_ID], 4383 &tag_id); 4384 if (tag_id >= (1 << (sizeof(tag_id) * 8 - MLX5_MTR_COLOR_BITS))) { 4385 DRV_LOG(ERR, "Port %u meter flow id exceed max limit.", 4386 dev->data->port_id); 4387 mlx5_ipool_free(priv->sh->ipool 4388 [MLX5_IPOOL_RSS_EXPANTION_FLOW_ID], tag_id); 4389 return 0; 4390 } else if (!tag_id) { 4391 return 0; 4392 } 4393 set_tag->data = tag_id << MLX5_MTR_COLOR_BITS; 4394 assert(tag_action); 4395 tag_action->conf = set_tag; 4396 /* Prepare the suffix subflow items. */ 4397 tag_item = sfx_items++; 4398 for (; items->type != RTE_FLOW_ITEM_TYPE_END; items++) { 4399 int item_type = items->type; 4400 4401 switch (item_type) { 4402 case RTE_FLOW_ITEM_TYPE_PORT_ID: 4403 memcpy(sfx_items, items, sizeof(*sfx_items)); 4404 sfx_items++; 4405 break; 4406 case RTE_FLOW_ITEM_TYPE_VLAN: 4407 if (copy_vlan) { 4408 memcpy(sfx_items, items, sizeof(*sfx_items)); 4409 /* 4410 * Convert to internal match item, it is used 4411 * for vlan push and set vid. 4412 */ 4413 sfx_items->type = (enum rte_flow_item_type) 4414 MLX5_RTE_FLOW_ITEM_TYPE_VLAN; 4415 sfx_items++; 4416 } 4417 break; 4418 default: 4419 break; 4420 } 4421 } 4422 sfx_items->type = RTE_FLOW_ITEM_TYPE_END; 4423 sfx_items++; 4424 tag_spec = (struct mlx5_rte_flow_item_tag *)sfx_items; 4425 tag_spec->data = tag_id << MLX5_MTR_COLOR_BITS; 4426 tag_spec->id = mlx5_flow_get_reg_id(dev, MLX5_MTR_SFX, 0, &error); 4427 tag_mask = tag_spec + 1; 4428 tag_mask->data = 0xffffff00; 4429 tag_item->type = (enum rte_flow_item_type) 4430 MLX5_RTE_FLOW_ITEM_TYPE_TAG; 4431 tag_item->spec = tag_spec; 4432 tag_item->last = NULL; 4433 tag_item->mask = tag_mask; 4434 return tag_id; 4435 } 4436 4437 /** 4438 * Split action list having QUEUE/RSS for metadata register copy. 4439 * 4440 * Once Q/RSS action is detected in user's action list, the flow action 4441 * should be split in order to copy metadata registers, which will happen in 4442 * RX_CP_TBL like, 4443 * - CQE->flow_tag := reg_c[1] (MARK) 4444 * - CQE->flow_table_metadata (reg_b) := reg_c[0] (META) 4445 * The Q/RSS action will be performed on RX_ACT_TBL after passing by RX_CP_TBL. 4446 * This is because the last action of each flow must be a terminal action 4447 * (QUEUE, RSS or DROP). 4448 * 4449 * Flow ID must be allocated to identify actions in the RX_ACT_TBL and it is 4450 * stored and kept in the mlx5_flow structure per each sub_flow. 4451 * 4452 * The Q/RSS action is replaced with, 4453 * - SET_TAG, setting the allocated flow ID to reg_c[2]. 4454 * And the following JUMP action is added at the end, 4455 * - JUMP, to RX_CP_TBL. 4456 * 4457 * A flow to perform remained Q/RSS action will be created in RX_ACT_TBL by 4458 * flow_create_split_metadata() routine. The flow will look like, 4459 * - If flow ID matches (reg_c[2]), perform Q/RSS. 4460 * 4461 * @param dev 4462 * Pointer to Ethernet device. 4463 * @param[out] split_actions 4464 * Pointer to store split actions to jump to CP_TBL. 4465 * @param[in] actions 4466 * Pointer to the list of original flow actions. 4467 * @param[in] qrss 4468 * Pointer to the Q/RSS action. 4469 * @param[in] actions_n 4470 * Number of original actions. 4471 * @param[out] error 4472 * Perform verbose error reporting if not NULL. 4473 * 4474 * @return 4475 * non-zero unique flow_id on success, otherwise 0 and 4476 * error/rte_error are set. 4477 */ 4478 static uint32_t 4479 flow_mreg_split_qrss_prep(struct rte_eth_dev *dev, 4480 struct rte_flow_action *split_actions, 4481 const struct rte_flow_action *actions, 4482 const struct rte_flow_action *qrss, 4483 int actions_n, struct rte_flow_error *error) 4484 { 4485 struct mlx5_priv *priv = dev->data->dev_private; 4486 struct mlx5_rte_flow_action_set_tag *set_tag; 4487 struct rte_flow_action_jump *jump; 4488 const int qrss_idx = qrss - actions; 4489 uint32_t flow_id = 0; 4490 int ret = 0; 4491 4492 /* 4493 * Given actions will be split 4494 * - Replace QUEUE/RSS action with SET_TAG to set flow ID. 4495 * - Add jump to mreg CP_TBL. 4496 * As a result, there will be one more action. 4497 */ 4498 ++actions_n; 4499 memcpy(split_actions, actions, sizeof(*split_actions) * actions_n); 4500 set_tag = (void *)(split_actions + actions_n); 4501 /* 4502 * If tag action is not set to void(it means we are not the meter 4503 * suffix flow), add the tag action. Since meter suffix flow already 4504 * has the tag added. 4505 */ 4506 if (split_actions[qrss_idx].type != RTE_FLOW_ACTION_TYPE_VOID) { 4507 /* 4508 * Allocate the new subflow ID. This one is unique within 4509 * device and not shared with representors. Otherwise, 4510 * we would have to resolve multi-thread access synch 4511 * issue. Each flow on the shared device is appended 4512 * with source vport identifier, so the resulting 4513 * flows will be unique in the shared (by master and 4514 * representors) domain even if they have coinciding 4515 * IDs. 4516 */ 4517 mlx5_ipool_malloc(priv->sh->ipool 4518 [MLX5_IPOOL_RSS_EXPANTION_FLOW_ID], &flow_id); 4519 if (!flow_id) 4520 return rte_flow_error_set(error, ENOMEM, 4521 RTE_FLOW_ERROR_TYPE_ACTION, 4522 NULL, "can't allocate id " 4523 "for split Q/RSS subflow"); 4524 /* Internal SET_TAG action to set flow ID. */ 4525 *set_tag = (struct mlx5_rte_flow_action_set_tag){ 4526 .data = flow_id, 4527 }; 4528 ret = mlx5_flow_get_reg_id(dev, MLX5_COPY_MARK, 0, error); 4529 if (ret < 0) 4530 return ret; 4531 set_tag->id = ret; 4532 /* Construct new actions array. */ 4533 /* Replace QUEUE/RSS action. */ 4534 split_actions[qrss_idx] = (struct rte_flow_action){ 4535 .type = (enum rte_flow_action_type) 4536 MLX5_RTE_FLOW_ACTION_TYPE_TAG, 4537 .conf = set_tag, 4538 }; 4539 } 4540 /* JUMP action to jump to mreg copy table (CP_TBL). */ 4541 jump = (void *)(set_tag + 1); 4542 *jump = (struct rte_flow_action_jump){ 4543 .group = MLX5_FLOW_MREG_CP_TABLE_GROUP, 4544 }; 4545 split_actions[actions_n - 2] = (struct rte_flow_action){ 4546 .type = RTE_FLOW_ACTION_TYPE_JUMP, 4547 .conf = jump, 4548 }; 4549 split_actions[actions_n - 1] = (struct rte_flow_action){ 4550 .type = RTE_FLOW_ACTION_TYPE_END, 4551 }; 4552 return flow_id; 4553 } 4554 4555 /** 4556 * Extend the given action list for Tx metadata copy. 4557 * 4558 * Copy the given action list to the ext_actions and add flow metadata register 4559 * copy action in order to copy reg_a set by WQE to reg_c[0]. 4560 * 4561 * @param[out] ext_actions 4562 * Pointer to the extended action list. 4563 * @param[in] actions 4564 * Pointer to the list of actions. 4565 * @param[in] actions_n 4566 * Number of actions in the list. 4567 * @param[out] error 4568 * Perform verbose error reporting if not NULL. 4569 * @param[in] encap_idx 4570 * The encap action inndex. 4571 * 4572 * @return 4573 * 0 on success, negative value otherwise 4574 */ 4575 static int 4576 flow_mreg_tx_copy_prep(struct rte_eth_dev *dev, 4577 struct rte_flow_action *ext_actions, 4578 const struct rte_flow_action *actions, 4579 int actions_n, struct rte_flow_error *error, 4580 int encap_idx) 4581 { 4582 struct mlx5_flow_action_copy_mreg *cp_mreg = 4583 (struct mlx5_flow_action_copy_mreg *) 4584 (ext_actions + actions_n + 1); 4585 int ret; 4586 4587 ret = mlx5_flow_get_reg_id(dev, MLX5_METADATA_RX, 0, error); 4588 if (ret < 0) 4589 return ret; 4590 cp_mreg->dst = ret; 4591 ret = mlx5_flow_get_reg_id(dev, MLX5_METADATA_TX, 0, error); 4592 if (ret < 0) 4593 return ret; 4594 cp_mreg->src = ret; 4595 if (encap_idx != 0) 4596 memcpy(ext_actions, actions, sizeof(*ext_actions) * encap_idx); 4597 if (encap_idx == actions_n - 1) { 4598 ext_actions[actions_n - 1] = (struct rte_flow_action){ 4599 .type = (enum rte_flow_action_type) 4600 MLX5_RTE_FLOW_ACTION_TYPE_COPY_MREG, 4601 .conf = cp_mreg, 4602 }; 4603 ext_actions[actions_n] = (struct rte_flow_action){ 4604 .type = RTE_FLOW_ACTION_TYPE_END, 4605 }; 4606 } else { 4607 ext_actions[encap_idx] = (struct rte_flow_action){ 4608 .type = (enum rte_flow_action_type) 4609 MLX5_RTE_FLOW_ACTION_TYPE_COPY_MREG, 4610 .conf = cp_mreg, 4611 }; 4612 memcpy(ext_actions + encap_idx + 1, actions + encap_idx, 4613 sizeof(*ext_actions) * (actions_n - encap_idx)); 4614 } 4615 return 0; 4616 } 4617 4618 /** 4619 * Check the match action from the action list. 4620 * 4621 * @param[in] actions 4622 * Pointer to the list of actions. 4623 * @param[in] attr 4624 * Flow rule attributes. 4625 * @param[in] action 4626 * The action to be check if exist. 4627 * @param[out] match_action_pos 4628 * Pointer to the position of the matched action if exists, otherwise is -1. 4629 * @param[out] qrss_action_pos 4630 * Pointer to the position of the Queue/RSS action if exists, otherwise is -1. 4631 * 4632 * @return 4633 * > 0 the total number of actions. 4634 * 0 if not found match action in action list. 4635 */ 4636 static int 4637 flow_check_match_action(const struct rte_flow_action actions[], 4638 const struct rte_flow_attr *attr, 4639 enum rte_flow_action_type action, 4640 int *match_action_pos, int *qrss_action_pos) 4641 { 4642 const struct rte_flow_action_sample *sample; 4643 int actions_n = 0; 4644 int jump_flag = 0; 4645 uint32_t ratio = 0; 4646 int sub_type = 0; 4647 int flag = 0; 4648 4649 *match_action_pos = -1; 4650 *qrss_action_pos = -1; 4651 for (; actions->type != RTE_FLOW_ACTION_TYPE_END; actions++) { 4652 if (actions->type == action) { 4653 flag = 1; 4654 *match_action_pos = actions_n; 4655 } 4656 if (actions->type == RTE_FLOW_ACTION_TYPE_QUEUE || 4657 actions->type == RTE_FLOW_ACTION_TYPE_RSS) 4658 *qrss_action_pos = actions_n; 4659 if (actions->type == RTE_FLOW_ACTION_TYPE_JUMP) 4660 jump_flag = 1; 4661 if (actions->type == RTE_FLOW_ACTION_TYPE_SAMPLE) { 4662 sample = actions->conf; 4663 ratio = sample->ratio; 4664 sub_type = ((const struct rte_flow_action *) 4665 (sample->actions))->type; 4666 } 4667 actions_n++; 4668 } 4669 if (flag && action == RTE_FLOW_ACTION_TYPE_SAMPLE && attr->transfer) { 4670 if (ratio == 1) { 4671 /* JUMP Action not support for Mirroring; 4672 * Mirroring support multi-destination; 4673 */ 4674 if (!jump_flag && sub_type != RTE_FLOW_ACTION_TYPE_END) 4675 flag = 0; 4676 } 4677 } 4678 /* Count RTE_FLOW_ACTION_TYPE_END. */ 4679 return flag ? actions_n + 1 : 0; 4680 } 4681 4682 #define SAMPLE_SUFFIX_ITEM 2 4683 4684 /** 4685 * Split the sample flow. 4686 * 4687 * As sample flow will split to two sub flow, sample flow with 4688 * sample action, the other actions will move to new suffix flow. 4689 * 4690 * Also add unique tag id with tag action in the sample flow, 4691 * the same tag id will be as match in the suffix flow. 4692 * 4693 * @param dev 4694 * Pointer to Ethernet device. 4695 * @param[in] fdb_tx 4696 * FDB egress flow flag. 4697 * @param[out] sfx_items 4698 * Suffix flow match items (list terminated by the END pattern item). 4699 * @param[in] actions 4700 * Associated actions (list terminated by the END action). 4701 * @param[out] actions_sfx 4702 * Suffix flow actions. 4703 * @param[out] actions_pre 4704 * Prefix flow actions. 4705 * @param[in] actions_n 4706 * The total number of actions. 4707 * @param[in] sample_action_pos 4708 * The sample action position. 4709 * @param[in] qrss_action_pos 4710 * The Queue/RSS action position. 4711 * @param[out] error 4712 * Perform verbose error reporting if not NULL. 4713 * 4714 * @return 4715 * 0 on success, or unique flow_id, a negative errno value 4716 * otherwise and rte_errno is set. 4717 */ 4718 static int 4719 flow_sample_split_prep(struct rte_eth_dev *dev, 4720 uint32_t fdb_tx, 4721 struct rte_flow_item sfx_items[], 4722 const struct rte_flow_action actions[], 4723 struct rte_flow_action actions_sfx[], 4724 struct rte_flow_action actions_pre[], 4725 int actions_n, 4726 int sample_action_pos, 4727 int qrss_action_pos, 4728 struct rte_flow_error *error) 4729 { 4730 struct mlx5_priv *priv = dev->data->dev_private; 4731 struct mlx5_rte_flow_action_set_tag *set_tag; 4732 struct mlx5_rte_flow_item_tag *tag_spec; 4733 struct mlx5_rte_flow_item_tag *tag_mask; 4734 uint32_t tag_id = 0; 4735 int index; 4736 int ret; 4737 4738 if (sample_action_pos < 0) 4739 return rte_flow_error_set(error, EINVAL, 4740 RTE_FLOW_ERROR_TYPE_ACTION, 4741 NULL, "invalid position of sample " 4742 "action in list"); 4743 if (!fdb_tx) { 4744 /* Prepare the prefix tag action. */ 4745 set_tag = (void *)(actions_pre + actions_n + 1); 4746 ret = mlx5_flow_get_reg_id(dev, MLX5_APP_TAG, 0, error); 4747 if (ret < 0) 4748 return ret; 4749 set_tag->id = ret; 4750 mlx5_ipool_malloc(priv->sh->ipool 4751 [MLX5_IPOOL_RSS_EXPANTION_FLOW_ID], &tag_id); 4752 set_tag->data = tag_id; 4753 /* Prepare the suffix subflow items. */ 4754 tag_spec = (void *)(sfx_items + SAMPLE_SUFFIX_ITEM); 4755 tag_spec->data = tag_id; 4756 tag_spec->id = set_tag->id; 4757 tag_mask = tag_spec + 1; 4758 tag_mask->data = UINT32_MAX; 4759 sfx_items[0] = (struct rte_flow_item){ 4760 .type = (enum rte_flow_item_type) 4761 MLX5_RTE_FLOW_ITEM_TYPE_TAG, 4762 .spec = tag_spec, 4763 .last = NULL, 4764 .mask = tag_mask, 4765 }; 4766 sfx_items[1] = (struct rte_flow_item){ 4767 .type = (enum rte_flow_item_type) 4768 RTE_FLOW_ITEM_TYPE_END, 4769 }; 4770 } 4771 /* Prepare the actions for prefix and suffix flow. */ 4772 if (qrss_action_pos >= 0 && qrss_action_pos < sample_action_pos) { 4773 index = qrss_action_pos; 4774 /* Put the preceding the Queue/RSS action into prefix flow. */ 4775 if (index != 0) 4776 memcpy(actions_pre, actions, 4777 sizeof(struct rte_flow_action) * index); 4778 /* Put others preceding the sample action into prefix flow. */ 4779 if (sample_action_pos > index + 1) 4780 memcpy(actions_pre + index, actions + index + 1, 4781 sizeof(struct rte_flow_action) * 4782 (sample_action_pos - index - 1)); 4783 index = sample_action_pos - 1; 4784 /* Put Queue/RSS action into Suffix flow. */ 4785 memcpy(actions_sfx, actions + qrss_action_pos, 4786 sizeof(struct rte_flow_action)); 4787 actions_sfx++; 4788 } else { 4789 index = sample_action_pos; 4790 if (index != 0) 4791 memcpy(actions_pre, actions, 4792 sizeof(struct rte_flow_action) * index); 4793 } 4794 /* Add the extra tag action for NIC-RX and E-Switch ingress. */ 4795 if (!fdb_tx) { 4796 actions_pre[index++] = 4797 (struct rte_flow_action){ 4798 .type = (enum rte_flow_action_type) 4799 MLX5_RTE_FLOW_ACTION_TYPE_TAG, 4800 .conf = set_tag, 4801 }; 4802 } 4803 memcpy(actions_pre + index, actions + sample_action_pos, 4804 sizeof(struct rte_flow_action)); 4805 index += 1; 4806 actions_pre[index] = (struct rte_flow_action){ 4807 .type = (enum rte_flow_action_type) 4808 RTE_FLOW_ACTION_TYPE_END, 4809 }; 4810 /* Put the actions after sample into Suffix flow. */ 4811 memcpy(actions_sfx, actions + sample_action_pos + 1, 4812 sizeof(struct rte_flow_action) * 4813 (actions_n - sample_action_pos - 1)); 4814 return tag_id; 4815 } 4816 4817 /** 4818 * The splitting for metadata feature. 4819 * 4820 * - Q/RSS action on NIC Rx should be split in order to pass by 4821 * the mreg copy table (RX_CP_TBL) and then it jumps to the 4822 * action table (RX_ACT_TBL) which has the split Q/RSS action. 4823 * 4824 * - All the actions on NIC Tx should have a mreg copy action to 4825 * copy reg_a from WQE to reg_c[0]. 4826 * 4827 * @param dev 4828 * Pointer to Ethernet device. 4829 * @param[in] flow 4830 * Parent flow structure pointer. 4831 * @param[in] attr 4832 * Flow rule attributes. 4833 * @param[in] items 4834 * Pattern specification (list terminated by the END pattern item). 4835 * @param[in] actions 4836 * Associated actions (list terminated by the END action). 4837 * @param[in] flow_split_info 4838 * Pointer to flow split info structure. 4839 * @param[out] error 4840 * Perform verbose error reporting if not NULL. 4841 * @return 4842 * 0 on success, negative value otherwise 4843 */ 4844 static int 4845 flow_create_split_metadata(struct rte_eth_dev *dev, 4846 struct rte_flow *flow, 4847 const struct rte_flow_attr *attr, 4848 const struct rte_flow_item items[], 4849 const struct rte_flow_action actions[], 4850 struct mlx5_flow_split_info *flow_split_info, 4851 struct rte_flow_error *error) 4852 { 4853 struct mlx5_priv *priv = dev->data->dev_private; 4854 struct mlx5_dev_config *config = &priv->config; 4855 const struct rte_flow_action *qrss = NULL; 4856 struct rte_flow_action *ext_actions = NULL; 4857 struct mlx5_flow *dev_flow = NULL; 4858 uint32_t qrss_id = 0; 4859 int mtr_sfx = 0; 4860 size_t act_size; 4861 int actions_n; 4862 int encap_idx; 4863 int ret; 4864 4865 /* Check whether extensive metadata feature is engaged. */ 4866 if (!config->dv_flow_en || 4867 config->dv_xmeta_en == MLX5_XMETA_MODE_LEGACY || 4868 !mlx5_flow_ext_mreg_supported(dev)) 4869 return flow_create_split_inner(dev, flow, NULL, attr, items, 4870 actions, flow_split_info, error); 4871 actions_n = flow_parse_metadata_split_actions_info(actions, &qrss, 4872 &encap_idx); 4873 if (qrss) { 4874 /* Exclude hairpin flows from splitting. */ 4875 if (qrss->type == RTE_FLOW_ACTION_TYPE_QUEUE) { 4876 const struct rte_flow_action_queue *queue; 4877 4878 queue = qrss->conf; 4879 if (mlx5_rxq_get_type(dev, queue->index) == 4880 MLX5_RXQ_TYPE_HAIRPIN) 4881 qrss = NULL; 4882 } else if (qrss->type == RTE_FLOW_ACTION_TYPE_RSS) { 4883 const struct rte_flow_action_rss *rss; 4884 4885 rss = qrss->conf; 4886 if (mlx5_rxq_get_type(dev, rss->queue[0]) == 4887 MLX5_RXQ_TYPE_HAIRPIN) 4888 qrss = NULL; 4889 } 4890 } 4891 if (qrss) { 4892 /* Check if it is in meter suffix table. */ 4893 mtr_sfx = attr->group == (attr->transfer ? 4894 (MLX5_FLOW_TABLE_LEVEL_SUFFIX - 1) : 4895 MLX5_FLOW_TABLE_LEVEL_SUFFIX); 4896 /* 4897 * Q/RSS action on NIC Rx should be split in order to pass by 4898 * the mreg copy table (RX_CP_TBL) and then it jumps to the 4899 * action table (RX_ACT_TBL) which has the split Q/RSS action. 4900 */ 4901 act_size = sizeof(struct rte_flow_action) * (actions_n + 1) + 4902 sizeof(struct rte_flow_action_set_tag) + 4903 sizeof(struct rte_flow_action_jump); 4904 ext_actions = mlx5_malloc(MLX5_MEM_ZERO, act_size, 0, 4905 SOCKET_ID_ANY); 4906 if (!ext_actions) 4907 return rte_flow_error_set(error, ENOMEM, 4908 RTE_FLOW_ERROR_TYPE_ACTION, 4909 NULL, "no memory to split " 4910 "metadata flow"); 4911 /* 4912 * If we are the suffix flow of meter, tag already exist. 4913 * Set the tag action to void. 4914 */ 4915 if (mtr_sfx) 4916 ext_actions[qrss - actions].type = 4917 RTE_FLOW_ACTION_TYPE_VOID; 4918 else 4919 ext_actions[qrss - actions].type = 4920 (enum rte_flow_action_type) 4921 MLX5_RTE_FLOW_ACTION_TYPE_TAG; 4922 /* 4923 * Create the new actions list with removed Q/RSS action 4924 * and appended set tag and jump to register copy table 4925 * (RX_CP_TBL). We should preallocate unique tag ID here 4926 * in advance, because it is needed for set tag action. 4927 */ 4928 qrss_id = flow_mreg_split_qrss_prep(dev, ext_actions, actions, 4929 qrss, actions_n, error); 4930 if (!mtr_sfx && !qrss_id) { 4931 ret = -rte_errno; 4932 goto exit; 4933 } 4934 } else if (attr->egress && !attr->transfer) { 4935 /* 4936 * All the actions on NIC Tx should have a metadata register 4937 * copy action to copy reg_a from WQE to reg_c[meta] 4938 */ 4939 act_size = sizeof(struct rte_flow_action) * (actions_n + 1) + 4940 sizeof(struct mlx5_flow_action_copy_mreg); 4941 ext_actions = mlx5_malloc(MLX5_MEM_ZERO, act_size, 0, 4942 SOCKET_ID_ANY); 4943 if (!ext_actions) 4944 return rte_flow_error_set(error, ENOMEM, 4945 RTE_FLOW_ERROR_TYPE_ACTION, 4946 NULL, "no memory to split " 4947 "metadata flow"); 4948 /* Create the action list appended with copy register. */ 4949 ret = flow_mreg_tx_copy_prep(dev, ext_actions, actions, 4950 actions_n, error, encap_idx); 4951 if (ret < 0) 4952 goto exit; 4953 } 4954 /* Add the unmodified original or prefix subflow. */ 4955 ret = flow_create_split_inner(dev, flow, &dev_flow, attr, 4956 items, ext_actions ? ext_actions : 4957 actions, flow_split_info, error); 4958 if (ret < 0) 4959 goto exit; 4960 MLX5_ASSERT(dev_flow); 4961 if (qrss) { 4962 const struct rte_flow_attr q_attr = { 4963 .group = MLX5_FLOW_MREG_ACT_TABLE_GROUP, 4964 .ingress = 1, 4965 }; 4966 /* Internal PMD action to set register. */ 4967 struct mlx5_rte_flow_item_tag q_tag_spec = { 4968 .data = qrss_id, 4969 .id = REG_NON, 4970 }; 4971 struct rte_flow_item q_items[] = { 4972 { 4973 .type = (enum rte_flow_item_type) 4974 MLX5_RTE_FLOW_ITEM_TYPE_TAG, 4975 .spec = &q_tag_spec, 4976 .last = NULL, 4977 .mask = NULL, 4978 }, 4979 { 4980 .type = RTE_FLOW_ITEM_TYPE_END, 4981 }, 4982 }; 4983 struct rte_flow_action q_actions[] = { 4984 { 4985 .type = qrss->type, 4986 .conf = qrss->conf, 4987 }, 4988 { 4989 .type = RTE_FLOW_ACTION_TYPE_END, 4990 }, 4991 }; 4992 uint64_t layers = flow_get_prefix_layer_flags(dev_flow); 4993 4994 /* 4995 * Configure the tag item only if there is no meter subflow. 4996 * Since tag is already marked in the meter suffix subflow 4997 * we can just use the meter suffix items as is. 4998 */ 4999 if (qrss_id) { 5000 /* Not meter subflow. */ 5001 MLX5_ASSERT(!mtr_sfx); 5002 /* 5003 * Put unique id in prefix flow due to it is destroyed 5004 * after suffix flow and id will be freed after there 5005 * is no actual flows with this id and identifier 5006 * reallocation becomes possible (for example, for 5007 * other flows in other threads). 5008 */ 5009 dev_flow->handle->split_flow_id = qrss_id; 5010 ret = mlx5_flow_get_reg_id(dev, MLX5_COPY_MARK, 0, 5011 error); 5012 if (ret < 0) 5013 goto exit; 5014 q_tag_spec.id = ret; 5015 } 5016 dev_flow = NULL; 5017 /* Add suffix subflow to execute Q/RSS. */ 5018 flow_split_info->prefix_layers = layers; 5019 flow_split_info->prefix_mark = 0; 5020 ret = flow_create_split_inner(dev, flow, &dev_flow, 5021 &q_attr, mtr_sfx ? items : 5022 q_items, q_actions, 5023 flow_split_info, error); 5024 if (ret < 0) 5025 goto exit; 5026 /* qrss ID should be freed if failed. */ 5027 qrss_id = 0; 5028 MLX5_ASSERT(dev_flow); 5029 } 5030 5031 exit: 5032 /* 5033 * We do not destroy the partially created sub_flows in case of error. 5034 * These ones are included into parent flow list and will be destroyed 5035 * by flow_drv_destroy. 5036 */ 5037 mlx5_ipool_free(priv->sh->ipool[MLX5_IPOOL_RSS_EXPANTION_FLOW_ID], 5038 qrss_id); 5039 mlx5_free(ext_actions); 5040 return ret; 5041 } 5042 5043 /** 5044 * The splitting for meter feature. 5045 * 5046 * - The meter flow will be split to two flows as prefix and 5047 * suffix flow. The packets make sense only it pass the prefix 5048 * meter action. 5049 * 5050 * - Reg_C_5 is used for the packet to match betweend prefix and 5051 * suffix flow. 5052 * 5053 * @param dev 5054 * Pointer to Ethernet device. 5055 * @param[in] flow 5056 * Parent flow structure pointer. 5057 * @param[in] attr 5058 * Flow rule attributes. 5059 * @param[in] items 5060 * Pattern specification (list terminated by the END pattern item). 5061 * @param[in] actions 5062 * Associated actions (list terminated by the END action). 5063 * @param[in] flow_split_info 5064 * Pointer to flow split info structure. 5065 * @param[out] error 5066 * Perform verbose error reporting if not NULL. 5067 * @return 5068 * 0 on success, negative value otherwise 5069 */ 5070 static int 5071 flow_create_split_meter(struct rte_eth_dev *dev, 5072 struct rte_flow *flow, 5073 const struct rte_flow_attr *attr, 5074 const struct rte_flow_item items[], 5075 const struct rte_flow_action actions[], 5076 struct mlx5_flow_split_info *flow_split_info, 5077 struct rte_flow_error *error) 5078 { 5079 struct mlx5_priv *priv = dev->data->dev_private; 5080 struct rte_flow_action *sfx_actions = NULL; 5081 struct rte_flow_action *pre_actions = NULL; 5082 struct rte_flow_item *sfx_items = NULL; 5083 struct mlx5_flow *dev_flow = NULL; 5084 struct rte_flow_attr sfx_attr = *attr; 5085 uint32_t mtr = 0; 5086 uint32_t mtr_tag_id = 0; 5087 size_t act_size; 5088 size_t item_size; 5089 int actions_n = 0; 5090 int ret; 5091 5092 if (priv->mtr_en) 5093 actions_n = flow_check_meter_action(actions, &mtr); 5094 if (mtr) { 5095 /* The five prefix actions: meter, decap, encap, tag, end. */ 5096 act_size = sizeof(struct rte_flow_action) * (actions_n + 5) + 5097 sizeof(struct mlx5_rte_flow_action_set_tag); 5098 /* tag, vlan, port id, end. */ 5099 #define METER_SUFFIX_ITEM 4 5100 item_size = sizeof(struct rte_flow_item) * METER_SUFFIX_ITEM + 5101 sizeof(struct mlx5_rte_flow_item_tag) * 2; 5102 sfx_actions = mlx5_malloc(MLX5_MEM_ZERO, (act_size + item_size), 5103 0, SOCKET_ID_ANY); 5104 if (!sfx_actions) 5105 return rte_flow_error_set(error, ENOMEM, 5106 RTE_FLOW_ERROR_TYPE_ACTION, 5107 NULL, "no memory to split " 5108 "meter flow"); 5109 sfx_items = (struct rte_flow_item *)((char *)sfx_actions + 5110 act_size); 5111 pre_actions = sfx_actions + actions_n; 5112 mtr_tag_id = flow_meter_split_prep(dev, items, sfx_items, 5113 actions, sfx_actions, 5114 pre_actions); 5115 if (!mtr_tag_id) { 5116 ret = -rte_errno; 5117 goto exit; 5118 } 5119 /* Add the prefix subflow. */ 5120 flow_split_info->prefix_mark = 0; 5121 ret = flow_create_split_inner(dev, flow, &dev_flow, 5122 attr, items, pre_actions, 5123 flow_split_info, error); 5124 if (ret) { 5125 ret = -rte_errno; 5126 goto exit; 5127 } 5128 dev_flow->handle->split_flow_id = mtr_tag_id; 5129 /* Setting the sfx group atrr. */ 5130 sfx_attr.group = sfx_attr.transfer ? 5131 (MLX5_FLOW_TABLE_LEVEL_SUFFIX - 1) : 5132 MLX5_FLOW_TABLE_LEVEL_SUFFIX; 5133 flow_split_info->prefix_layers = 5134 flow_get_prefix_layer_flags(dev_flow); 5135 flow_split_info->prefix_mark = dev_flow->handle->mark; 5136 } 5137 /* Add the prefix subflow. */ 5138 ret = flow_create_split_metadata(dev, flow, 5139 &sfx_attr, sfx_items ? 5140 sfx_items : items, 5141 sfx_actions ? sfx_actions : actions, 5142 flow_split_info, error); 5143 exit: 5144 if (sfx_actions) 5145 mlx5_free(sfx_actions); 5146 return ret; 5147 } 5148 5149 /** 5150 * The splitting for sample feature. 5151 * 5152 * Once Sample action is detected in the action list, the flow actions should 5153 * be split into prefix sub flow and suffix sub flow. 5154 * 5155 * The original items remain in the prefix sub flow, all actions preceding the 5156 * sample action and the sample action itself will be copied to the prefix 5157 * sub flow, the actions following the sample action will be copied to the 5158 * suffix sub flow, Queue action always be located in the suffix sub flow. 5159 * 5160 * In order to make the packet from prefix sub flow matches with suffix sub 5161 * flow, an extra tag action be added into prefix sub flow, and the suffix sub 5162 * flow uses tag item with the unique flow id. 5163 * 5164 * @param dev 5165 * Pointer to Ethernet device. 5166 * @param[in] flow 5167 * Parent flow structure pointer. 5168 * @param[in] attr 5169 * Flow rule attributes. 5170 * @param[in] items 5171 * Pattern specification (list terminated by the END pattern item). 5172 * @param[in] actions 5173 * Associated actions (list terminated by the END action). 5174 * @param[in] flow_split_info 5175 * Pointer to flow split info structure. 5176 * @param[out] error 5177 * Perform verbose error reporting if not NULL. 5178 * @return 5179 * 0 on success, negative value otherwise 5180 */ 5181 static int 5182 flow_create_split_sample(struct rte_eth_dev *dev, 5183 struct rte_flow *flow, 5184 const struct rte_flow_attr *attr, 5185 const struct rte_flow_item items[], 5186 const struct rte_flow_action actions[], 5187 struct mlx5_flow_split_info *flow_split_info, 5188 struct rte_flow_error *error) 5189 { 5190 struct mlx5_priv *priv = dev->data->dev_private; 5191 struct rte_flow_action *sfx_actions = NULL; 5192 struct rte_flow_action *pre_actions = NULL; 5193 struct rte_flow_item *sfx_items = NULL; 5194 struct mlx5_flow *dev_flow = NULL; 5195 struct rte_flow_attr sfx_attr = *attr; 5196 #ifdef HAVE_IBV_FLOW_DV_SUPPORT 5197 struct mlx5_flow_dv_sample_resource *sample_res; 5198 struct mlx5_flow_tbl_data_entry *sfx_tbl_data; 5199 struct mlx5_flow_tbl_resource *sfx_tbl; 5200 #endif 5201 size_t act_size; 5202 size_t item_size; 5203 uint32_t fdb_tx = 0; 5204 int32_t tag_id = 0; 5205 int actions_n = 0; 5206 int sample_action_pos; 5207 int qrss_action_pos; 5208 int ret = 0; 5209 5210 if (priv->sampler_en) 5211 actions_n = flow_check_match_action(actions, attr, 5212 RTE_FLOW_ACTION_TYPE_SAMPLE, 5213 &sample_action_pos, &qrss_action_pos); 5214 if (actions_n) { 5215 /* The prefix actions must includes sample, tag, end. */ 5216 act_size = sizeof(struct rte_flow_action) * (actions_n * 2 + 1) 5217 + sizeof(struct mlx5_rte_flow_action_set_tag); 5218 item_size = sizeof(struct rte_flow_item) * SAMPLE_SUFFIX_ITEM + 5219 sizeof(struct mlx5_rte_flow_item_tag) * 2; 5220 sfx_actions = mlx5_malloc(MLX5_MEM_ZERO, (act_size + 5221 item_size), 0, SOCKET_ID_ANY); 5222 if (!sfx_actions) 5223 return rte_flow_error_set(error, ENOMEM, 5224 RTE_FLOW_ERROR_TYPE_ACTION, 5225 NULL, "no memory to split " 5226 "sample flow"); 5227 /* The representor_id is -1 for uplink. */ 5228 fdb_tx = (attr->transfer && priv->representor_id != -1); 5229 if (!fdb_tx) 5230 sfx_items = (struct rte_flow_item *)((char *)sfx_actions 5231 + act_size); 5232 pre_actions = sfx_actions + actions_n; 5233 tag_id = flow_sample_split_prep(dev, fdb_tx, sfx_items, 5234 actions, sfx_actions, 5235 pre_actions, actions_n, 5236 sample_action_pos, 5237 qrss_action_pos, error); 5238 if (tag_id < 0 || (!fdb_tx && !tag_id)) { 5239 ret = -rte_errno; 5240 goto exit; 5241 } 5242 /* Add the prefix subflow. */ 5243 ret = flow_create_split_inner(dev, flow, &dev_flow, attr, 5244 items, pre_actions, 5245 flow_split_info, error); 5246 if (ret) { 5247 ret = -rte_errno; 5248 goto exit; 5249 } 5250 dev_flow->handle->split_flow_id = tag_id; 5251 #ifdef HAVE_IBV_FLOW_DV_SUPPORT 5252 /* Set the sfx group attr. */ 5253 sample_res = (struct mlx5_flow_dv_sample_resource *) 5254 dev_flow->dv.sample_res; 5255 sfx_tbl = (struct mlx5_flow_tbl_resource *) 5256 sample_res->normal_path_tbl; 5257 sfx_tbl_data = container_of(sfx_tbl, 5258 struct mlx5_flow_tbl_data_entry, tbl); 5259 sfx_attr.group = sfx_attr.transfer ? 5260 (sfx_tbl_data->table_id - 1) : 5261 sfx_tbl_data->table_id; 5262 flow_split_info->prefix_layers = 5263 flow_get_prefix_layer_flags(dev_flow); 5264 flow_split_info->prefix_mark = dev_flow->handle->mark; 5265 /* Suffix group level already be scaled with factor, set 5266 * skip_scale to 1 to avoid scale again in translation. 5267 */ 5268 flow_split_info->skip_scale = 1; 5269 #endif 5270 } 5271 /* Add the suffix subflow. */ 5272 ret = flow_create_split_meter(dev, flow, &sfx_attr, 5273 sfx_items ? sfx_items : items, 5274 sfx_actions ? sfx_actions : actions, 5275 flow_split_info, error); 5276 exit: 5277 if (sfx_actions) 5278 mlx5_free(sfx_actions); 5279 return ret; 5280 } 5281 5282 /** 5283 * Split the flow to subflow set. The splitters might be linked 5284 * in the chain, like this: 5285 * flow_create_split_outer() calls: 5286 * flow_create_split_meter() calls: 5287 * flow_create_split_metadata(meter_subflow_0) calls: 5288 * flow_create_split_inner(metadata_subflow_0) 5289 * flow_create_split_inner(metadata_subflow_1) 5290 * flow_create_split_inner(metadata_subflow_2) 5291 * flow_create_split_metadata(meter_subflow_1) calls: 5292 * flow_create_split_inner(metadata_subflow_0) 5293 * flow_create_split_inner(metadata_subflow_1) 5294 * flow_create_split_inner(metadata_subflow_2) 5295 * 5296 * This provide flexible way to add new levels of flow splitting. 5297 * The all of successfully created subflows are included to the 5298 * parent flow dev_flow list. 5299 * 5300 * @param dev 5301 * Pointer to Ethernet device. 5302 * @param[in] flow 5303 * Parent flow structure pointer. 5304 * @param[in] attr 5305 * Flow rule attributes. 5306 * @param[in] items 5307 * Pattern specification (list terminated by the END pattern item). 5308 * @param[in] actions 5309 * Associated actions (list terminated by the END action). 5310 * @param[in] flow_split_info 5311 * Pointer to flow split info structure. 5312 * @param[out] error 5313 * Perform verbose error reporting if not NULL. 5314 * @return 5315 * 0 on success, negative value otherwise 5316 */ 5317 static int 5318 flow_create_split_outer(struct rte_eth_dev *dev, 5319 struct rte_flow *flow, 5320 const struct rte_flow_attr *attr, 5321 const struct rte_flow_item items[], 5322 const struct rte_flow_action actions[], 5323 struct mlx5_flow_split_info *flow_split_info, 5324 struct rte_flow_error *error) 5325 { 5326 int ret; 5327 5328 ret = flow_create_split_sample(dev, flow, attr, items, 5329 actions, flow_split_info, error); 5330 MLX5_ASSERT(ret <= 0); 5331 return ret; 5332 } 5333 5334 static struct mlx5_flow_tunnel * 5335 flow_tunnel_from_rule(struct rte_eth_dev *dev, 5336 const struct rte_flow_attr *attr, 5337 const struct rte_flow_item items[], 5338 const struct rte_flow_action actions[]) 5339 { 5340 struct mlx5_flow_tunnel *tunnel; 5341 5342 #pragma GCC diagnostic push 5343 #pragma GCC diagnostic ignored "-Wcast-qual" 5344 if (is_flow_tunnel_match_rule(dev, attr, items, actions)) 5345 tunnel = (struct mlx5_flow_tunnel *)items[0].spec; 5346 else if (is_flow_tunnel_steer_rule(dev, attr, items, actions)) 5347 tunnel = (struct mlx5_flow_tunnel *)actions[0].conf; 5348 else 5349 tunnel = NULL; 5350 #pragma GCC diagnostic pop 5351 5352 return tunnel; 5353 } 5354 5355 /** 5356 * Adjust flow RSS workspace if needed. 5357 * 5358 * @param wks 5359 * Pointer to thread flow work space. 5360 * @param rss_desc 5361 * Pointer to RSS descriptor. 5362 * @param[in] nrssq_num 5363 * New RSS queue number. 5364 * 5365 * @return 5366 * 0 on success, -1 otherwise and rte_errno is set. 5367 */ 5368 static int 5369 flow_rss_workspace_adjust(struct mlx5_flow_workspace *wks, 5370 struct mlx5_flow_rss_desc *rss_desc, 5371 uint32_t nrssq_num) 5372 { 5373 if (likely(nrssq_num <= wks->rssq_num)) 5374 return 0; 5375 rss_desc->queue = realloc(rss_desc->queue, 5376 sizeof(*rss_desc->queue) * RTE_ALIGN(nrssq_num, 2)); 5377 if (!rss_desc->queue) { 5378 rte_errno = ENOMEM; 5379 return -1; 5380 } 5381 wks->rssq_num = RTE_ALIGN(nrssq_num, 2); 5382 return 0; 5383 } 5384 5385 /** 5386 * Create a flow and add it to @p list. 5387 * 5388 * @param dev 5389 * Pointer to Ethernet device. 5390 * @param list 5391 * Pointer to a TAILQ flow list. If this parameter NULL, 5392 * no list insertion occurred, flow is just created, 5393 * this is caller's responsibility to track the 5394 * created flow. 5395 * @param[in] attr 5396 * Flow rule attributes. 5397 * @param[in] items 5398 * Pattern specification (list terminated by the END pattern item). 5399 * @param[in] actions 5400 * Associated actions (list terminated by the END action). 5401 * @param[in] external 5402 * This flow rule is created by request external to PMD. 5403 * @param[out] error 5404 * Perform verbose error reporting if not NULL. 5405 * 5406 * @return 5407 * A flow index on success, 0 otherwise and rte_errno is set. 5408 */ 5409 static uint32_t 5410 flow_list_create(struct rte_eth_dev *dev, uint32_t *list, 5411 const struct rte_flow_attr *attr, 5412 const struct rte_flow_item items[], 5413 const struct rte_flow_action original_actions[], 5414 bool external, struct rte_flow_error *error) 5415 { 5416 struct mlx5_priv *priv = dev->data->dev_private; 5417 struct rte_flow *flow = NULL; 5418 struct mlx5_flow *dev_flow; 5419 const struct rte_flow_action_rss *rss = NULL; 5420 struct mlx5_translated_shared_action 5421 shared_actions[MLX5_MAX_SHARED_ACTIONS]; 5422 int shared_actions_n = MLX5_MAX_SHARED_ACTIONS; 5423 union { 5424 struct mlx5_flow_expand_rss buf; 5425 uint8_t buffer[2048]; 5426 } expand_buffer; 5427 union { 5428 struct rte_flow_action actions[MLX5_MAX_SPLIT_ACTIONS]; 5429 uint8_t buffer[2048]; 5430 } actions_rx; 5431 union { 5432 struct rte_flow_action actions[MLX5_MAX_SPLIT_ACTIONS]; 5433 uint8_t buffer[2048]; 5434 } actions_hairpin_tx; 5435 union { 5436 struct rte_flow_item items[MLX5_MAX_SPLIT_ITEMS]; 5437 uint8_t buffer[2048]; 5438 } items_tx; 5439 struct mlx5_flow_expand_rss *buf = &expand_buffer.buf; 5440 struct mlx5_flow_rss_desc *rss_desc; 5441 const struct rte_flow_action *p_actions_rx; 5442 uint32_t i; 5443 uint32_t idx = 0; 5444 int hairpin_flow; 5445 struct rte_flow_attr attr_tx = { .priority = 0 }; 5446 const struct rte_flow_action *actions; 5447 struct rte_flow_action *translated_actions = NULL; 5448 struct mlx5_flow_tunnel *tunnel; 5449 struct tunnel_default_miss_ctx default_miss_ctx = { 0, }; 5450 struct mlx5_flow_workspace *wks = mlx5_flow_push_thread_workspace(); 5451 struct mlx5_flow_split_info flow_split_info = { 5452 .external = !!external, 5453 .skip_scale = 0, 5454 .flow_idx = 0, 5455 .prefix_mark = 0, 5456 .prefix_layers = 0 5457 }; 5458 int ret; 5459 5460 MLX5_ASSERT(wks); 5461 rss_desc = &wks->rss_desc; 5462 ret = flow_shared_actions_translate(dev, original_actions, 5463 shared_actions, 5464 &shared_actions_n, 5465 &translated_actions, error); 5466 if (ret < 0) { 5467 MLX5_ASSERT(translated_actions == NULL); 5468 return 0; 5469 } 5470 actions = translated_actions ? translated_actions : original_actions; 5471 p_actions_rx = actions; 5472 hairpin_flow = flow_check_hairpin_split(dev, attr, actions); 5473 ret = flow_drv_validate(dev, attr, items, p_actions_rx, 5474 external, hairpin_flow, error); 5475 if (ret < 0) 5476 goto error_before_hairpin_split; 5477 flow = mlx5_ipool_zmalloc(priv->sh->ipool[MLX5_IPOOL_RTE_FLOW], &idx); 5478 if (!flow) { 5479 rte_errno = ENOMEM; 5480 goto error_before_hairpin_split; 5481 } 5482 if (hairpin_flow > 0) { 5483 if (hairpin_flow > MLX5_MAX_SPLIT_ACTIONS) { 5484 rte_errno = EINVAL; 5485 goto error_before_hairpin_split; 5486 } 5487 flow_hairpin_split(dev, actions, actions_rx.actions, 5488 actions_hairpin_tx.actions, items_tx.items, 5489 idx); 5490 p_actions_rx = actions_rx.actions; 5491 } 5492 flow_split_info.flow_idx = idx; 5493 flow->drv_type = flow_get_drv_type(dev, attr); 5494 MLX5_ASSERT(flow->drv_type > MLX5_FLOW_TYPE_MIN && 5495 flow->drv_type < MLX5_FLOW_TYPE_MAX); 5496 memset(rss_desc, 0, offsetof(struct mlx5_flow_rss_desc, queue)); 5497 /* RSS Action only works on NIC RX domain */ 5498 if (attr->ingress && !attr->transfer) 5499 rss = flow_get_rss_action(p_actions_rx); 5500 if (rss) { 5501 if (flow_rss_workspace_adjust(wks, rss_desc, rss->queue_num)) 5502 return 0; 5503 /* 5504 * The following information is required by 5505 * mlx5_flow_hashfields_adjust() in advance. 5506 */ 5507 rss_desc->level = rss->level; 5508 /* RSS type 0 indicates default RSS type (ETH_RSS_IP). */ 5509 rss_desc->types = !rss->types ? ETH_RSS_IP : rss->types; 5510 } 5511 flow->dev_handles = 0; 5512 if (rss && rss->types) { 5513 unsigned int graph_root; 5514 5515 graph_root = find_graph_root(items, rss->level); 5516 ret = mlx5_flow_expand_rss(buf, sizeof(expand_buffer.buffer), 5517 items, rss->types, 5518 mlx5_support_expansion, graph_root); 5519 MLX5_ASSERT(ret > 0 && 5520 (unsigned int)ret < sizeof(expand_buffer.buffer)); 5521 } else { 5522 buf->entries = 1; 5523 buf->entry[0].pattern = (void *)(uintptr_t)items; 5524 } 5525 rss_desc->shared_rss = flow_get_shared_rss_action(dev, shared_actions, 5526 shared_actions_n); 5527 for (i = 0; i < buf->entries; ++i) { 5528 /* Initialize flow split data. */ 5529 flow_split_info.prefix_layers = 0; 5530 flow_split_info.prefix_mark = 0; 5531 flow_split_info.skip_scale = 0; 5532 /* 5533 * The splitter may create multiple dev_flows, 5534 * depending on configuration. In the simplest 5535 * case it just creates unmodified original flow. 5536 */ 5537 ret = flow_create_split_outer(dev, flow, attr, 5538 buf->entry[i].pattern, 5539 p_actions_rx, &flow_split_info, 5540 error); 5541 if (ret < 0) 5542 goto error; 5543 if (is_flow_tunnel_steer_rule(dev, attr, 5544 buf->entry[i].pattern, 5545 p_actions_rx)) { 5546 ret = flow_tunnel_add_default_miss(dev, flow, attr, 5547 p_actions_rx, 5548 idx, 5549 &default_miss_ctx, 5550 error); 5551 if (ret < 0) { 5552 mlx5_free(default_miss_ctx.queue); 5553 goto error; 5554 } 5555 } 5556 } 5557 /* Create the tx flow. */ 5558 if (hairpin_flow) { 5559 attr_tx.group = MLX5_HAIRPIN_TX_TABLE; 5560 attr_tx.ingress = 0; 5561 attr_tx.egress = 1; 5562 dev_flow = flow_drv_prepare(dev, flow, &attr_tx, items_tx.items, 5563 actions_hairpin_tx.actions, 5564 idx, error); 5565 if (!dev_flow) 5566 goto error; 5567 dev_flow->flow = flow; 5568 dev_flow->external = 0; 5569 SILIST_INSERT(&flow->dev_handles, dev_flow->handle_idx, 5570 dev_flow->handle, next); 5571 ret = flow_drv_translate(dev, dev_flow, &attr_tx, 5572 items_tx.items, 5573 actions_hairpin_tx.actions, error); 5574 if (ret < 0) 5575 goto error; 5576 } 5577 /* 5578 * Update the metadata register copy table. If extensive 5579 * metadata feature is enabled and registers are supported 5580 * we might create the extra rte_flow for each unique 5581 * MARK/FLAG action ID. 5582 * 5583 * The table is updated for ingress Flows only, because 5584 * the egress Flows belong to the different device and 5585 * copy table should be updated in peer NIC Rx domain. 5586 */ 5587 if (attr->ingress && 5588 (external || attr->group != MLX5_FLOW_MREG_CP_TABLE_GROUP)) { 5589 ret = flow_mreg_update_copy_table(dev, flow, actions, error); 5590 if (ret) 5591 goto error; 5592 } 5593 /* 5594 * If the flow is external (from application) OR device is started, 5595 * OR mreg discover, then apply immediately. 5596 */ 5597 if (external || dev->data->dev_started || 5598 (attr->group == MLX5_FLOW_MREG_CP_TABLE_GROUP && 5599 attr->priority == MLX5_FLOW_PRIO_RSVD)) { 5600 ret = flow_drv_apply(dev, flow, error); 5601 if (ret < 0) 5602 goto error; 5603 } 5604 if (list) { 5605 rte_spinlock_lock(&priv->flow_list_lock); 5606 ILIST_INSERT(priv->sh->ipool[MLX5_IPOOL_RTE_FLOW], list, idx, 5607 flow, next); 5608 rte_spinlock_unlock(&priv->flow_list_lock); 5609 } 5610 flow_rxq_flags_set(dev, flow); 5611 rte_free(translated_actions); 5612 tunnel = flow_tunnel_from_rule(dev, attr, items, actions); 5613 if (tunnel) { 5614 flow->tunnel = 1; 5615 flow->tunnel_id = tunnel->tunnel_id; 5616 __atomic_add_fetch(&tunnel->refctn, 1, __ATOMIC_RELAXED); 5617 mlx5_free(default_miss_ctx.queue); 5618 } 5619 mlx5_flow_pop_thread_workspace(); 5620 return idx; 5621 error: 5622 MLX5_ASSERT(flow); 5623 ret = rte_errno; /* Save rte_errno before cleanup. */ 5624 flow_mreg_del_copy_action(dev, flow); 5625 flow_drv_destroy(dev, flow); 5626 if (rss_desc->shared_rss) 5627 __atomic_sub_fetch(&((struct mlx5_shared_action_rss *) 5628 mlx5_ipool_get 5629 (priv->sh->ipool[MLX5_IPOOL_RSS_SHARED_ACTIONS], 5630 rss_desc->shared_rss))->refcnt, 1, __ATOMIC_RELAXED); 5631 mlx5_ipool_free(priv->sh->ipool[MLX5_IPOOL_RTE_FLOW], idx); 5632 rte_errno = ret; /* Restore rte_errno. */ 5633 ret = rte_errno; 5634 rte_errno = ret; 5635 mlx5_flow_pop_thread_workspace(); 5636 error_before_hairpin_split: 5637 rte_free(translated_actions); 5638 return 0; 5639 } 5640 5641 /** 5642 * Create a dedicated flow rule on e-switch table 0 (root table), to direct all 5643 * incoming packets to table 1. 5644 * 5645 * Other flow rules, requested for group n, will be created in 5646 * e-switch table n+1. 5647 * Jump action to e-switch group n will be created to group n+1. 5648 * 5649 * Used when working in switchdev mode, to utilise advantages of table 1 5650 * and above. 5651 * 5652 * @param dev 5653 * Pointer to Ethernet device. 5654 * 5655 * @return 5656 * Pointer to flow on success, NULL otherwise and rte_errno is set. 5657 */ 5658 struct rte_flow * 5659 mlx5_flow_create_esw_table_zero_flow(struct rte_eth_dev *dev) 5660 { 5661 const struct rte_flow_attr attr = { 5662 .group = 0, 5663 .priority = 0, 5664 .ingress = 1, 5665 .egress = 0, 5666 .transfer = 1, 5667 }; 5668 const struct rte_flow_item pattern = { 5669 .type = RTE_FLOW_ITEM_TYPE_END, 5670 }; 5671 struct rte_flow_action_jump jump = { 5672 .group = 1, 5673 }; 5674 const struct rte_flow_action actions[] = { 5675 { 5676 .type = RTE_FLOW_ACTION_TYPE_JUMP, 5677 .conf = &jump, 5678 }, 5679 { 5680 .type = RTE_FLOW_ACTION_TYPE_END, 5681 }, 5682 }; 5683 struct mlx5_priv *priv = dev->data->dev_private; 5684 struct rte_flow_error error; 5685 5686 return (void *)(uintptr_t)flow_list_create(dev, &priv->ctrl_flows, 5687 &attr, &pattern, 5688 actions, false, &error); 5689 } 5690 5691 /** 5692 * Validate a flow supported by the NIC. 5693 * 5694 * @see rte_flow_validate() 5695 * @see rte_flow_ops 5696 */ 5697 int 5698 mlx5_flow_validate(struct rte_eth_dev *dev, 5699 const struct rte_flow_attr *attr, 5700 const struct rte_flow_item items[], 5701 const struct rte_flow_action original_actions[], 5702 struct rte_flow_error *error) 5703 { 5704 int hairpin_flow; 5705 struct mlx5_translated_shared_action 5706 shared_actions[MLX5_MAX_SHARED_ACTIONS]; 5707 int shared_actions_n = MLX5_MAX_SHARED_ACTIONS; 5708 const struct rte_flow_action *actions; 5709 struct rte_flow_action *translated_actions = NULL; 5710 int ret = flow_shared_actions_translate(dev, original_actions, 5711 shared_actions, 5712 &shared_actions_n, 5713 &translated_actions, error); 5714 5715 if (ret) 5716 return ret; 5717 actions = translated_actions ? translated_actions : original_actions; 5718 hairpin_flow = flow_check_hairpin_split(dev, attr, actions); 5719 ret = flow_drv_validate(dev, attr, items, actions, 5720 true, hairpin_flow, error); 5721 rte_free(translated_actions); 5722 return ret; 5723 } 5724 5725 /** 5726 * Create a flow. 5727 * 5728 * @see rte_flow_create() 5729 * @see rte_flow_ops 5730 */ 5731 struct rte_flow * 5732 mlx5_flow_create(struct rte_eth_dev *dev, 5733 const struct rte_flow_attr *attr, 5734 const struct rte_flow_item items[], 5735 const struct rte_flow_action actions[], 5736 struct rte_flow_error *error) 5737 { 5738 struct mlx5_priv *priv = dev->data->dev_private; 5739 5740 /* 5741 * If the device is not started yet, it is not allowed to created a 5742 * flow from application. PMD default flows and traffic control flows 5743 * are not affected. 5744 */ 5745 if (unlikely(!dev->data->dev_started)) { 5746 DRV_LOG(DEBUG, "port %u is not started when " 5747 "inserting a flow", dev->data->port_id); 5748 rte_flow_error_set(error, ENODEV, 5749 RTE_FLOW_ERROR_TYPE_UNSPECIFIED, 5750 NULL, 5751 "port not started"); 5752 return NULL; 5753 } 5754 5755 return (void *)(uintptr_t)flow_list_create(dev, &priv->flows, 5756 attr, items, actions, true, error); 5757 } 5758 5759 /** 5760 * Destroy a flow in a list. 5761 * 5762 * @param dev 5763 * Pointer to Ethernet device. 5764 * @param list 5765 * Pointer to the Indexed flow list. If this parameter NULL, 5766 * there is no flow removal from the list. Be noted that as 5767 * flow is add to the indexed list, memory of the indexed 5768 * list points to maybe changed as flow destroyed. 5769 * @param[in] flow_idx 5770 * Index of flow to destroy. 5771 */ 5772 static void 5773 flow_list_destroy(struct rte_eth_dev *dev, uint32_t *list, 5774 uint32_t flow_idx) 5775 { 5776 struct mlx5_priv *priv = dev->data->dev_private; 5777 struct rte_flow *flow = mlx5_ipool_get(priv->sh->ipool 5778 [MLX5_IPOOL_RTE_FLOW], flow_idx); 5779 5780 if (!flow) 5781 return; 5782 /* 5783 * Update RX queue flags only if port is started, otherwise it is 5784 * already clean. 5785 */ 5786 if (dev->data->dev_started) 5787 flow_rxq_flags_trim(dev, flow); 5788 flow_drv_destroy(dev, flow); 5789 if (list) { 5790 rte_spinlock_lock(&priv->flow_list_lock); 5791 ILIST_REMOVE(priv->sh->ipool[MLX5_IPOOL_RTE_FLOW], list, 5792 flow_idx, flow, next); 5793 rte_spinlock_unlock(&priv->flow_list_lock); 5794 } 5795 if (flow->tunnel) { 5796 struct mlx5_flow_tunnel *tunnel; 5797 5798 tunnel = mlx5_find_tunnel_id(dev, flow->tunnel_id); 5799 RTE_VERIFY(tunnel); 5800 if (!__atomic_sub_fetch(&tunnel->refctn, 1, __ATOMIC_RELAXED)) 5801 mlx5_flow_tunnel_free(dev, tunnel); 5802 } 5803 flow_mreg_del_copy_action(dev, flow); 5804 mlx5_ipool_free(priv->sh->ipool[MLX5_IPOOL_RTE_FLOW], flow_idx); 5805 } 5806 5807 /** 5808 * Destroy all flows. 5809 * 5810 * @param dev 5811 * Pointer to Ethernet device. 5812 * @param list 5813 * Pointer to the Indexed flow list. 5814 * @param active 5815 * If flushing is called avtively. 5816 */ 5817 void 5818 mlx5_flow_list_flush(struct rte_eth_dev *dev, uint32_t *list, bool active) 5819 { 5820 uint32_t num_flushed = 0; 5821 5822 while (*list) { 5823 flow_list_destroy(dev, list, *list); 5824 num_flushed++; 5825 } 5826 if (active) { 5827 DRV_LOG(INFO, "port %u: %u flows flushed before stopping", 5828 dev->data->port_id, num_flushed); 5829 } 5830 } 5831 5832 /** 5833 * Stop all default actions for flows. 5834 * 5835 * @param dev 5836 * Pointer to Ethernet device. 5837 */ 5838 void 5839 mlx5_flow_stop_default(struct rte_eth_dev *dev) 5840 { 5841 flow_mreg_del_default_copy_action(dev); 5842 flow_rxq_flags_clear(dev); 5843 } 5844 5845 /** 5846 * Start all default actions for flows. 5847 * 5848 * @param dev 5849 * Pointer to Ethernet device. 5850 * @return 5851 * 0 on success, a negative errno value otherwise and rte_errno is set. 5852 */ 5853 int 5854 mlx5_flow_start_default(struct rte_eth_dev *dev) 5855 { 5856 struct rte_flow_error error; 5857 5858 /* Make sure default copy action (reg_c[0] -> reg_b) is created. */ 5859 return flow_mreg_add_default_copy_action(dev, &error); 5860 } 5861 5862 /** 5863 * Release key of thread specific flow workspace data. 5864 */ 5865 void 5866 flow_release_workspace(void *data) 5867 { 5868 struct mlx5_flow_workspace *wks = data; 5869 struct mlx5_flow_workspace *next; 5870 5871 while (wks) { 5872 next = wks->next; 5873 free(wks->rss_desc.queue); 5874 free(wks); 5875 wks = next; 5876 } 5877 } 5878 5879 /** 5880 * Get thread specific current flow workspace. 5881 * 5882 * @return pointer to thread specific flow workspace data, NULL on error. 5883 */ 5884 struct mlx5_flow_workspace* 5885 mlx5_flow_get_thread_workspace(void) 5886 { 5887 struct mlx5_flow_workspace *data; 5888 5889 data = mlx5_flow_os_get_specific_workspace(); 5890 MLX5_ASSERT(data && data->inuse); 5891 if (!data || !data->inuse) 5892 DRV_LOG(ERR, "flow workspace not initialized."); 5893 return data; 5894 } 5895 5896 /** 5897 * Allocate and init new flow workspace. 5898 * 5899 * @return pointer to flow workspace data, NULL on error. 5900 */ 5901 static struct mlx5_flow_workspace* 5902 flow_alloc_thread_workspace(void) 5903 { 5904 struct mlx5_flow_workspace *data = calloc(1, sizeof(*data)); 5905 5906 if (!data) { 5907 DRV_LOG(ERR, "Failed to allocate flow workspace " 5908 "memory."); 5909 return NULL; 5910 } 5911 data->rss_desc.queue = calloc(1, 5912 sizeof(uint16_t) * MLX5_RSSQ_DEFAULT_NUM); 5913 if (!data->rss_desc.queue) 5914 goto err; 5915 data->rssq_num = MLX5_RSSQ_DEFAULT_NUM; 5916 return data; 5917 err: 5918 if (data->rss_desc.queue) 5919 free(data->rss_desc.queue); 5920 free(data); 5921 return NULL; 5922 } 5923 5924 /** 5925 * Get new thread specific flow workspace. 5926 * 5927 * If current workspace inuse, create new one and set as current. 5928 * 5929 * @return pointer to thread specific flow workspace data, NULL on error. 5930 */ 5931 static struct mlx5_flow_workspace* 5932 mlx5_flow_push_thread_workspace(void) 5933 { 5934 struct mlx5_flow_workspace *curr; 5935 struct mlx5_flow_workspace *data; 5936 5937 curr = mlx5_flow_os_get_specific_workspace(); 5938 if (!curr) { 5939 data = flow_alloc_thread_workspace(); 5940 if (!data) 5941 return NULL; 5942 } else if (!curr->inuse) { 5943 data = curr; 5944 } else if (curr->next) { 5945 data = curr->next; 5946 } else { 5947 data = flow_alloc_thread_workspace(); 5948 if (!data) 5949 return NULL; 5950 curr->next = data; 5951 data->prev = curr; 5952 } 5953 data->inuse = 1; 5954 data->flow_idx = 0; 5955 /* Set as current workspace */ 5956 if (mlx5_flow_os_set_specific_workspace(data)) 5957 DRV_LOG(ERR, "Failed to set flow workspace to thread."); 5958 return data; 5959 } 5960 5961 /** 5962 * Close current thread specific flow workspace. 5963 * 5964 * If previous workspace available, set it as current. 5965 * 5966 * @return pointer to thread specific flow workspace data, NULL on error. 5967 */ 5968 static void 5969 mlx5_flow_pop_thread_workspace(void) 5970 { 5971 struct mlx5_flow_workspace *data = mlx5_flow_get_thread_workspace(); 5972 5973 if (!data) 5974 return; 5975 if (!data->inuse) { 5976 DRV_LOG(ERR, "Failed to close unused flow workspace."); 5977 return; 5978 } 5979 data->inuse = 0; 5980 if (!data->prev) 5981 return; 5982 if (mlx5_flow_os_set_specific_workspace(data->prev)) 5983 DRV_LOG(ERR, "Failed to set flow workspace to thread."); 5984 } 5985 5986 /** 5987 * Verify the flow list is empty 5988 * 5989 * @param dev 5990 * Pointer to Ethernet device. 5991 * 5992 * @return the number of flows not released. 5993 */ 5994 int 5995 mlx5_flow_verify(struct rte_eth_dev *dev) 5996 { 5997 struct mlx5_priv *priv = dev->data->dev_private; 5998 struct rte_flow *flow; 5999 uint32_t idx; 6000 int ret = 0; 6001 6002 ILIST_FOREACH(priv->sh->ipool[MLX5_IPOOL_RTE_FLOW], priv->flows, idx, 6003 flow, next) { 6004 DRV_LOG(DEBUG, "port %u flow %p still referenced", 6005 dev->data->port_id, (void *)flow); 6006 ++ret; 6007 } 6008 return ret; 6009 } 6010 6011 /** 6012 * Enable default hairpin egress flow. 6013 * 6014 * @param dev 6015 * Pointer to Ethernet device. 6016 * @param queue 6017 * The queue index. 6018 * 6019 * @return 6020 * 0 on success, a negative errno value otherwise and rte_errno is set. 6021 */ 6022 int 6023 mlx5_ctrl_flow_source_queue(struct rte_eth_dev *dev, 6024 uint32_t queue) 6025 { 6026 struct mlx5_priv *priv = dev->data->dev_private; 6027 const struct rte_flow_attr attr = { 6028 .egress = 1, 6029 .priority = 0, 6030 }; 6031 struct mlx5_rte_flow_item_tx_queue queue_spec = { 6032 .queue = queue, 6033 }; 6034 struct mlx5_rte_flow_item_tx_queue queue_mask = { 6035 .queue = UINT32_MAX, 6036 }; 6037 struct rte_flow_item items[] = { 6038 { 6039 .type = (enum rte_flow_item_type) 6040 MLX5_RTE_FLOW_ITEM_TYPE_TX_QUEUE, 6041 .spec = &queue_spec, 6042 .last = NULL, 6043 .mask = &queue_mask, 6044 }, 6045 { 6046 .type = RTE_FLOW_ITEM_TYPE_END, 6047 }, 6048 }; 6049 struct rte_flow_action_jump jump = { 6050 .group = MLX5_HAIRPIN_TX_TABLE, 6051 }; 6052 struct rte_flow_action actions[2]; 6053 uint32_t flow_idx; 6054 struct rte_flow_error error; 6055 6056 actions[0].type = RTE_FLOW_ACTION_TYPE_JUMP; 6057 actions[0].conf = &jump; 6058 actions[1].type = RTE_FLOW_ACTION_TYPE_END; 6059 flow_idx = flow_list_create(dev, &priv->ctrl_flows, 6060 &attr, items, actions, false, &error); 6061 if (!flow_idx) { 6062 DRV_LOG(DEBUG, 6063 "Failed to create ctrl flow: rte_errno(%d)," 6064 " type(%d), message(%s)", 6065 rte_errno, error.type, 6066 error.message ? error.message : " (no stated reason)"); 6067 return -rte_errno; 6068 } 6069 return 0; 6070 } 6071 6072 /** 6073 * Enable a control flow configured from the control plane. 6074 * 6075 * @param dev 6076 * Pointer to Ethernet device. 6077 * @param eth_spec 6078 * An Ethernet flow spec to apply. 6079 * @param eth_mask 6080 * An Ethernet flow mask to apply. 6081 * @param vlan_spec 6082 * A VLAN flow spec to apply. 6083 * @param vlan_mask 6084 * A VLAN flow mask to apply. 6085 * 6086 * @return 6087 * 0 on success, a negative errno value otherwise and rte_errno is set. 6088 */ 6089 int 6090 mlx5_ctrl_flow_vlan(struct rte_eth_dev *dev, 6091 struct rte_flow_item_eth *eth_spec, 6092 struct rte_flow_item_eth *eth_mask, 6093 struct rte_flow_item_vlan *vlan_spec, 6094 struct rte_flow_item_vlan *vlan_mask) 6095 { 6096 struct mlx5_priv *priv = dev->data->dev_private; 6097 const struct rte_flow_attr attr = { 6098 .ingress = 1, 6099 .priority = MLX5_FLOW_PRIO_RSVD, 6100 }; 6101 struct rte_flow_item items[] = { 6102 { 6103 .type = RTE_FLOW_ITEM_TYPE_ETH, 6104 .spec = eth_spec, 6105 .last = NULL, 6106 .mask = eth_mask, 6107 }, 6108 { 6109 .type = (vlan_spec) ? RTE_FLOW_ITEM_TYPE_VLAN : 6110 RTE_FLOW_ITEM_TYPE_END, 6111 .spec = vlan_spec, 6112 .last = NULL, 6113 .mask = vlan_mask, 6114 }, 6115 { 6116 .type = RTE_FLOW_ITEM_TYPE_END, 6117 }, 6118 }; 6119 uint16_t queue[priv->reta_idx_n]; 6120 struct rte_flow_action_rss action_rss = { 6121 .func = RTE_ETH_HASH_FUNCTION_DEFAULT, 6122 .level = 0, 6123 .types = priv->rss_conf.rss_hf, 6124 .key_len = priv->rss_conf.rss_key_len, 6125 .queue_num = priv->reta_idx_n, 6126 .key = priv->rss_conf.rss_key, 6127 .queue = queue, 6128 }; 6129 struct rte_flow_action actions[] = { 6130 { 6131 .type = RTE_FLOW_ACTION_TYPE_RSS, 6132 .conf = &action_rss, 6133 }, 6134 { 6135 .type = RTE_FLOW_ACTION_TYPE_END, 6136 }, 6137 }; 6138 uint32_t flow_idx; 6139 struct rte_flow_error error; 6140 unsigned int i; 6141 6142 if (!priv->reta_idx_n || !priv->rxqs_n) { 6143 return 0; 6144 } 6145 if (!(dev->data->dev_conf.rxmode.mq_mode & ETH_MQ_RX_RSS_FLAG)) 6146 action_rss.types = 0; 6147 for (i = 0; i != priv->reta_idx_n; ++i) 6148 queue[i] = (*priv->reta_idx)[i]; 6149 flow_idx = flow_list_create(dev, &priv->ctrl_flows, 6150 &attr, items, actions, false, &error); 6151 if (!flow_idx) 6152 return -rte_errno; 6153 return 0; 6154 } 6155 6156 /** 6157 * Enable a flow control configured from the control plane. 6158 * 6159 * @param dev 6160 * Pointer to Ethernet device. 6161 * @param eth_spec 6162 * An Ethernet flow spec to apply. 6163 * @param eth_mask 6164 * An Ethernet flow mask to apply. 6165 * 6166 * @return 6167 * 0 on success, a negative errno value otherwise and rte_errno is set. 6168 */ 6169 int 6170 mlx5_ctrl_flow(struct rte_eth_dev *dev, 6171 struct rte_flow_item_eth *eth_spec, 6172 struct rte_flow_item_eth *eth_mask) 6173 { 6174 return mlx5_ctrl_flow_vlan(dev, eth_spec, eth_mask, NULL, NULL); 6175 } 6176 6177 /** 6178 * Create default miss flow rule matching lacp traffic 6179 * 6180 * @param dev 6181 * Pointer to Ethernet device. 6182 * @param eth_spec 6183 * An Ethernet flow spec to apply. 6184 * 6185 * @return 6186 * 0 on success, a negative errno value otherwise and rte_errno is set. 6187 */ 6188 int 6189 mlx5_flow_lacp_miss(struct rte_eth_dev *dev) 6190 { 6191 struct mlx5_priv *priv = dev->data->dev_private; 6192 /* 6193 * The LACP matching is done by only using ether type since using 6194 * a multicast dst mac causes kernel to give low priority to this flow. 6195 */ 6196 static const struct rte_flow_item_eth lacp_spec = { 6197 .type = RTE_BE16(0x8809), 6198 }; 6199 static const struct rte_flow_item_eth lacp_mask = { 6200 .type = 0xffff, 6201 }; 6202 const struct rte_flow_attr attr = { 6203 .ingress = 1, 6204 }; 6205 struct rte_flow_item items[] = { 6206 { 6207 .type = RTE_FLOW_ITEM_TYPE_ETH, 6208 .spec = &lacp_spec, 6209 .mask = &lacp_mask, 6210 }, 6211 { 6212 .type = RTE_FLOW_ITEM_TYPE_END, 6213 }, 6214 }; 6215 struct rte_flow_action actions[] = { 6216 { 6217 .type = (enum rte_flow_action_type) 6218 MLX5_RTE_FLOW_ACTION_TYPE_DEFAULT_MISS, 6219 }, 6220 { 6221 .type = RTE_FLOW_ACTION_TYPE_END, 6222 }, 6223 }; 6224 struct rte_flow_error error; 6225 uint32_t flow_idx = flow_list_create(dev, &priv->ctrl_flows, 6226 &attr, items, actions, false, &error); 6227 6228 if (!flow_idx) 6229 return -rte_errno; 6230 return 0; 6231 } 6232 6233 /** 6234 * Destroy a flow. 6235 * 6236 * @see rte_flow_destroy() 6237 * @see rte_flow_ops 6238 */ 6239 int 6240 mlx5_flow_destroy(struct rte_eth_dev *dev, 6241 struct rte_flow *flow, 6242 struct rte_flow_error *error __rte_unused) 6243 { 6244 struct mlx5_priv *priv = dev->data->dev_private; 6245 6246 flow_list_destroy(dev, &priv->flows, (uintptr_t)(void *)flow); 6247 return 0; 6248 } 6249 6250 /** 6251 * Destroy all flows. 6252 * 6253 * @see rte_flow_flush() 6254 * @see rte_flow_ops 6255 */ 6256 int 6257 mlx5_flow_flush(struct rte_eth_dev *dev, 6258 struct rte_flow_error *error __rte_unused) 6259 { 6260 struct mlx5_priv *priv = dev->data->dev_private; 6261 6262 mlx5_flow_list_flush(dev, &priv->flows, false); 6263 return 0; 6264 } 6265 6266 /** 6267 * Isolated mode. 6268 * 6269 * @see rte_flow_isolate() 6270 * @see rte_flow_ops 6271 */ 6272 int 6273 mlx5_flow_isolate(struct rte_eth_dev *dev, 6274 int enable, 6275 struct rte_flow_error *error) 6276 { 6277 struct mlx5_priv *priv = dev->data->dev_private; 6278 6279 if (dev->data->dev_started) { 6280 rte_flow_error_set(error, EBUSY, 6281 RTE_FLOW_ERROR_TYPE_UNSPECIFIED, 6282 NULL, 6283 "port must be stopped first"); 6284 return -rte_errno; 6285 } 6286 priv->isolated = !!enable; 6287 if (enable) 6288 dev->dev_ops = &mlx5_dev_ops_isolate; 6289 else 6290 dev->dev_ops = &mlx5_dev_ops; 6291 6292 dev->rx_descriptor_status = mlx5_rx_descriptor_status; 6293 dev->tx_descriptor_status = mlx5_tx_descriptor_status; 6294 6295 return 0; 6296 } 6297 6298 /** 6299 * Query a flow. 6300 * 6301 * @see rte_flow_query() 6302 * @see rte_flow_ops 6303 */ 6304 static int 6305 flow_drv_query(struct rte_eth_dev *dev, 6306 uint32_t flow_idx, 6307 const struct rte_flow_action *actions, 6308 void *data, 6309 struct rte_flow_error *error) 6310 { 6311 struct mlx5_priv *priv = dev->data->dev_private; 6312 const struct mlx5_flow_driver_ops *fops; 6313 struct rte_flow *flow = mlx5_ipool_get(priv->sh->ipool 6314 [MLX5_IPOOL_RTE_FLOW], 6315 flow_idx); 6316 enum mlx5_flow_drv_type ftype; 6317 6318 if (!flow) { 6319 return rte_flow_error_set(error, ENOENT, 6320 RTE_FLOW_ERROR_TYPE_UNSPECIFIED, 6321 NULL, 6322 "invalid flow handle"); 6323 } 6324 ftype = flow->drv_type; 6325 MLX5_ASSERT(ftype > MLX5_FLOW_TYPE_MIN && ftype < MLX5_FLOW_TYPE_MAX); 6326 fops = flow_get_drv_ops(ftype); 6327 6328 return fops->query(dev, flow, actions, data, error); 6329 } 6330 6331 /** 6332 * Query a flow. 6333 * 6334 * @see rte_flow_query() 6335 * @see rte_flow_ops 6336 */ 6337 int 6338 mlx5_flow_query(struct rte_eth_dev *dev, 6339 struct rte_flow *flow, 6340 const struct rte_flow_action *actions, 6341 void *data, 6342 struct rte_flow_error *error) 6343 { 6344 int ret; 6345 6346 ret = flow_drv_query(dev, (uintptr_t)(void *)flow, actions, data, 6347 error); 6348 if (ret < 0) 6349 return ret; 6350 return 0; 6351 } 6352 6353 /** 6354 * Manage filter operations. 6355 * 6356 * @param dev 6357 * Pointer to Ethernet device structure. 6358 * @param filter_type 6359 * Filter type. 6360 * @param filter_op 6361 * Operation to perform. 6362 * @param arg 6363 * Pointer to operation-specific structure. 6364 * 6365 * @return 6366 * 0 on success, a negative errno value otherwise and rte_errno is set. 6367 */ 6368 int 6369 mlx5_dev_filter_ctrl(struct rte_eth_dev *dev, 6370 enum rte_filter_type filter_type, 6371 enum rte_filter_op filter_op, 6372 void *arg) 6373 { 6374 switch (filter_type) { 6375 case RTE_ETH_FILTER_GENERIC: 6376 if (filter_op != RTE_ETH_FILTER_GET) { 6377 rte_errno = EINVAL; 6378 return -rte_errno; 6379 } 6380 *(const void **)arg = &mlx5_flow_ops; 6381 return 0; 6382 default: 6383 DRV_LOG(ERR, "port %u filter type (%d) not supported", 6384 dev->data->port_id, filter_type); 6385 rte_errno = ENOTSUP; 6386 return -rte_errno; 6387 } 6388 return 0; 6389 } 6390 6391 /** 6392 * Create the needed meter and suffix tables. 6393 * 6394 * @param[in] dev 6395 * Pointer to Ethernet device. 6396 * @param[in] fm 6397 * Pointer to the flow meter. 6398 * 6399 * @return 6400 * Pointer to table set on success, NULL otherwise. 6401 */ 6402 struct mlx5_meter_domains_infos * 6403 mlx5_flow_create_mtr_tbls(struct rte_eth_dev *dev, 6404 const struct mlx5_flow_meter *fm) 6405 { 6406 const struct mlx5_flow_driver_ops *fops; 6407 6408 fops = flow_get_drv_ops(MLX5_FLOW_TYPE_DV); 6409 return fops->create_mtr_tbls(dev, fm); 6410 } 6411 6412 /** 6413 * Destroy the meter table set. 6414 * 6415 * @param[in] dev 6416 * Pointer to Ethernet device. 6417 * @param[in] tbl 6418 * Pointer to the meter table set. 6419 * 6420 * @return 6421 * 0 on success. 6422 */ 6423 int 6424 mlx5_flow_destroy_mtr_tbls(struct rte_eth_dev *dev, 6425 struct mlx5_meter_domains_infos *tbls) 6426 { 6427 const struct mlx5_flow_driver_ops *fops; 6428 6429 fops = flow_get_drv_ops(MLX5_FLOW_TYPE_DV); 6430 return fops->destroy_mtr_tbls(dev, tbls); 6431 } 6432 6433 /** 6434 * Create policer rules. 6435 * 6436 * @param[in] dev 6437 * Pointer to Ethernet device. 6438 * @param[in] fm 6439 * Pointer to flow meter structure. 6440 * @param[in] attr 6441 * Pointer to flow attributes. 6442 * 6443 * @return 6444 * 0 on success, -1 otherwise. 6445 */ 6446 int 6447 mlx5_flow_create_policer_rules(struct rte_eth_dev *dev, 6448 struct mlx5_flow_meter *fm, 6449 const struct rte_flow_attr *attr) 6450 { 6451 const struct mlx5_flow_driver_ops *fops; 6452 6453 fops = flow_get_drv_ops(MLX5_FLOW_TYPE_DV); 6454 return fops->create_policer_rules(dev, fm, attr); 6455 } 6456 6457 /** 6458 * Destroy policer rules. 6459 * 6460 * @param[in] fm 6461 * Pointer to flow meter structure. 6462 * @param[in] attr 6463 * Pointer to flow attributes. 6464 * 6465 * @return 6466 * 0 on success, -1 otherwise. 6467 */ 6468 int 6469 mlx5_flow_destroy_policer_rules(struct rte_eth_dev *dev, 6470 struct mlx5_flow_meter *fm, 6471 const struct rte_flow_attr *attr) 6472 { 6473 const struct mlx5_flow_driver_ops *fops; 6474 6475 fops = flow_get_drv_ops(MLX5_FLOW_TYPE_DV); 6476 return fops->destroy_policer_rules(dev, fm, attr); 6477 } 6478 6479 /** 6480 * Allocate a counter. 6481 * 6482 * @param[in] dev 6483 * Pointer to Ethernet device structure. 6484 * 6485 * @return 6486 * Index to allocated counter on success, 0 otherwise. 6487 */ 6488 uint32_t 6489 mlx5_counter_alloc(struct rte_eth_dev *dev) 6490 { 6491 const struct mlx5_flow_driver_ops *fops; 6492 struct rte_flow_attr attr = { .transfer = 0 }; 6493 6494 if (flow_get_drv_type(dev, &attr) == MLX5_FLOW_TYPE_DV) { 6495 fops = flow_get_drv_ops(MLX5_FLOW_TYPE_DV); 6496 return fops->counter_alloc(dev); 6497 } 6498 DRV_LOG(ERR, 6499 "port %u counter allocate is not supported.", 6500 dev->data->port_id); 6501 return 0; 6502 } 6503 6504 /** 6505 * Free a counter. 6506 * 6507 * @param[in] dev 6508 * Pointer to Ethernet device structure. 6509 * @param[in] cnt 6510 * Index to counter to be free. 6511 */ 6512 void 6513 mlx5_counter_free(struct rte_eth_dev *dev, uint32_t cnt) 6514 { 6515 const struct mlx5_flow_driver_ops *fops; 6516 struct rte_flow_attr attr = { .transfer = 0 }; 6517 6518 if (flow_get_drv_type(dev, &attr) == MLX5_FLOW_TYPE_DV) { 6519 fops = flow_get_drv_ops(MLX5_FLOW_TYPE_DV); 6520 fops->counter_free(dev, cnt); 6521 return; 6522 } 6523 DRV_LOG(ERR, 6524 "port %u counter free is not supported.", 6525 dev->data->port_id); 6526 } 6527 6528 /** 6529 * Query counter statistics. 6530 * 6531 * @param[in] dev 6532 * Pointer to Ethernet device structure. 6533 * @param[in] cnt 6534 * Index to counter to query. 6535 * @param[in] clear 6536 * Set to clear counter statistics. 6537 * @param[out] pkts 6538 * The counter hits packets number to save. 6539 * @param[out] bytes 6540 * The counter hits bytes number to save. 6541 * 6542 * @return 6543 * 0 on success, a negative errno value otherwise. 6544 */ 6545 int 6546 mlx5_counter_query(struct rte_eth_dev *dev, uint32_t cnt, 6547 bool clear, uint64_t *pkts, uint64_t *bytes) 6548 { 6549 const struct mlx5_flow_driver_ops *fops; 6550 struct rte_flow_attr attr = { .transfer = 0 }; 6551 6552 if (flow_get_drv_type(dev, &attr) == MLX5_FLOW_TYPE_DV) { 6553 fops = flow_get_drv_ops(MLX5_FLOW_TYPE_DV); 6554 return fops->counter_query(dev, cnt, clear, pkts, bytes); 6555 } 6556 DRV_LOG(ERR, 6557 "port %u counter query is not supported.", 6558 dev->data->port_id); 6559 return -ENOTSUP; 6560 } 6561 6562 /** 6563 * Allocate a new memory for the counter values wrapped by all the needed 6564 * management. 6565 * 6566 * @param[in] sh 6567 * Pointer to mlx5_dev_ctx_shared object. 6568 * 6569 * @return 6570 * 0 on success, a negative errno value otherwise. 6571 */ 6572 static int 6573 mlx5_flow_create_counter_stat_mem_mng(struct mlx5_dev_ctx_shared *sh) 6574 { 6575 struct mlx5_devx_mkey_attr mkey_attr; 6576 struct mlx5_counter_stats_mem_mng *mem_mng; 6577 volatile struct flow_counter_stats *raw_data; 6578 int raws_n = MLX5_CNT_CONTAINER_RESIZE + MLX5_MAX_PENDING_QUERIES; 6579 int size = (sizeof(struct flow_counter_stats) * 6580 MLX5_COUNTERS_PER_POOL + 6581 sizeof(struct mlx5_counter_stats_raw)) * raws_n + 6582 sizeof(struct mlx5_counter_stats_mem_mng); 6583 size_t pgsize = rte_mem_page_size(); 6584 uint8_t *mem; 6585 int i; 6586 6587 if (pgsize == (size_t)-1) { 6588 DRV_LOG(ERR, "Failed to get mem page size"); 6589 rte_errno = ENOMEM; 6590 return -ENOMEM; 6591 } 6592 mem = mlx5_malloc(MLX5_MEM_ZERO, size, pgsize, SOCKET_ID_ANY); 6593 if (!mem) { 6594 rte_errno = ENOMEM; 6595 return -ENOMEM; 6596 } 6597 mem_mng = (struct mlx5_counter_stats_mem_mng *)(mem + size) - 1; 6598 size = sizeof(*raw_data) * MLX5_COUNTERS_PER_POOL * raws_n; 6599 mem_mng->umem = mlx5_os_umem_reg(sh->ctx, mem, size, 6600 IBV_ACCESS_LOCAL_WRITE); 6601 if (!mem_mng->umem) { 6602 rte_errno = errno; 6603 mlx5_free(mem); 6604 return -rte_errno; 6605 } 6606 mkey_attr.addr = (uintptr_t)mem; 6607 mkey_attr.size = size; 6608 mkey_attr.umem_id = mlx5_os_get_umem_id(mem_mng->umem); 6609 mkey_attr.pd = sh->pdn; 6610 mkey_attr.log_entity_size = 0; 6611 mkey_attr.pg_access = 0; 6612 mkey_attr.klm_array = NULL; 6613 mkey_attr.klm_num = 0; 6614 mkey_attr.relaxed_ordering_write = sh->cmng.relaxed_ordering_write; 6615 mkey_attr.relaxed_ordering_read = sh->cmng.relaxed_ordering_read; 6616 mem_mng->dm = mlx5_devx_cmd_mkey_create(sh->ctx, &mkey_attr); 6617 if (!mem_mng->dm) { 6618 mlx5_os_umem_dereg(mem_mng->umem); 6619 rte_errno = errno; 6620 mlx5_free(mem); 6621 return -rte_errno; 6622 } 6623 mem_mng->raws = (struct mlx5_counter_stats_raw *)(mem + size); 6624 raw_data = (volatile struct flow_counter_stats *)mem; 6625 for (i = 0; i < raws_n; ++i) { 6626 mem_mng->raws[i].mem_mng = mem_mng; 6627 mem_mng->raws[i].data = raw_data + i * MLX5_COUNTERS_PER_POOL; 6628 } 6629 for (i = 0; i < MLX5_MAX_PENDING_QUERIES; ++i) 6630 LIST_INSERT_HEAD(&sh->cmng.free_stat_raws, 6631 mem_mng->raws + MLX5_CNT_CONTAINER_RESIZE + i, 6632 next); 6633 LIST_INSERT_HEAD(&sh->cmng.mem_mngs, mem_mng, next); 6634 sh->cmng.mem_mng = mem_mng; 6635 return 0; 6636 } 6637 6638 /** 6639 * Set the statistic memory to the new counter pool. 6640 * 6641 * @param[in] sh 6642 * Pointer to mlx5_dev_ctx_shared object. 6643 * @param[in] pool 6644 * Pointer to the pool to set the statistic memory. 6645 * 6646 * @return 6647 * 0 on success, a negative errno value otherwise. 6648 */ 6649 static int 6650 mlx5_flow_set_counter_stat_mem(struct mlx5_dev_ctx_shared *sh, 6651 struct mlx5_flow_counter_pool *pool) 6652 { 6653 struct mlx5_flow_counter_mng *cmng = &sh->cmng; 6654 /* Resize statistic memory once used out. */ 6655 if (!(pool->index % MLX5_CNT_CONTAINER_RESIZE) && 6656 mlx5_flow_create_counter_stat_mem_mng(sh)) { 6657 DRV_LOG(ERR, "Cannot resize counter stat mem."); 6658 return -1; 6659 } 6660 rte_spinlock_lock(&pool->sl); 6661 pool->raw = cmng->mem_mng->raws + pool->index % 6662 MLX5_CNT_CONTAINER_RESIZE; 6663 rte_spinlock_unlock(&pool->sl); 6664 pool->raw_hw = NULL; 6665 return 0; 6666 } 6667 6668 #define MLX5_POOL_QUERY_FREQ_US 1000000 6669 6670 /** 6671 * Set the periodic procedure for triggering asynchronous batch queries for all 6672 * the counter pools. 6673 * 6674 * @param[in] sh 6675 * Pointer to mlx5_dev_ctx_shared object. 6676 */ 6677 void 6678 mlx5_set_query_alarm(struct mlx5_dev_ctx_shared *sh) 6679 { 6680 uint32_t pools_n, us; 6681 6682 pools_n = __atomic_load_n(&sh->cmng.n_valid, __ATOMIC_RELAXED); 6683 us = MLX5_POOL_QUERY_FREQ_US / pools_n; 6684 DRV_LOG(DEBUG, "Set alarm for %u pools each %u us", pools_n, us); 6685 if (rte_eal_alarm_set(us, mlx5_flow_query_alarm, sh)) { 6686 sh->cmng.query_thread_on = 0; 6687 DRV_LOG(ERR, "Cannot reinitialize query alarm"); 6688 } else { 6689 sh->cmng.query_thread_on = 1; 6690 } 6691 } 6692 6693 /** 6694 * The periodic procedure for triggering asynchronous batch queries for all the 6695 * counter pools. This function is probably called by the host thread. 6696 * 6697 * @param[in] arg 6698 * The parameter for the alarm process. 6699 */ 6700 void 6701 mlx5_flow_query_alarm(void *arg) 6702 { 6703 struct mlx5_dev_ctx_shared *sh = arg; 6704 int ret; 6705 uint16_t pool_index = sh->cmng.pool_index; 6706 struct mlx5_flow_counter_mng *cmng = &sh->cmng; 6707 struct mlx5_flow_counter_pool *pool; 6708 uint16_t n_valid; 6709 6710 if (sh->cmng.pending_queries >= MLX5_MAX_PENDING_QUERIES) 6711 goto set_alarm; 6712 rte_spinlock_lock(&cmng->pool_update_sl); 6713 pool = cmng->pools[pool_index]; 6714 n_valid = cmng->n_valid; 6715 rte_spinlock_unlock(&cmng->pool_update_sl); 6716 /* Set the statistic memory to the new created pool. */ 6717 if ((!pool->raw && mlx5_flow_set_counter_stat_mem(sh, pool))) 6718 goto set_alarm; 6719 if (pool->raw_hw) 6720 /* There is a pool query in progress. */ 6721 goto set_alarm; 6722 pool->raw_hw = 6723 LIST_FIRST(&sh->cmng.free_stat_raws); 6724 if (!pool->raw_hw) 6725 /* No free counter statistics raw memory. */ 6726 goto set_alarm; 6727 /* 6728 * Identify the counters released between query trigger and query 6729 * handle more efficiently. The counter released in this gap period 6730 * should wait for a new round of query as the new arrived packets 6731 * will not be taken into account. 6732 */ 6733 pool->query_gen++; 6734 ret = mlx5_devx_cmd_flow_counter_query(pool->min_dcs, 0, 6735 MLX5_COUNTERS_PER_POOL, 6736 NULL, NULL, 6737 pool->raw_hw->mem_mng->dm->id, 6738 (void *)(uintptr_t) 6739 pool->raw_hw->data, 6740 sh->devx_comp, 6741 (uint64_t)(uintptr_t)pool); 6742 if (ret) { 6743 DRV_LOG(ERR, "Failed to trigger asynchronous query for dcs ID" 6744 " %d", pool->min_dcs->id); 6745 pool->raw_hw = NULL; 6746 goto set_alarm; 6747 } 6748 LIST_REMOVE(pool->raw_hw, next); 6749 sh->cmng.pending_queries++; 6750 pool_index++; 6751 if (pool_index >= n_valid) 6752 pool_index = 0; 6753 set_alarm: 6754 sh->cmng.pool_index = pool_index; 6755 mlx5_set_query_alarm(sh); 6756 } 6757 6758 /** 6759 * Check and callback event for new aged flow in the counter pool 6760 * 6761 * @param[in] sh 6762 * Pointer to mlx5_dev_ctx_shared object. 6763 * @param[in] pool 6764 * Pointer to Current counter pool. 6765 */ 6766 static void 6767 mlx5_flow_aging_check(struct mlx5_dev_ctx_shared *sh, 6768 struct mlx5_flow_counter_pool *pool) 6769 { 6770 struct mlx5_priv *priv; 6771 struct mlx5_flow_counter *cnt; 6772 struct mlx5_age_info *age_info; 6773 struct mlx5_age_param *age_param; 6774 struct mlx5_counter_stats_raw *cur = pool->raw_hw; 6775 struct mlx5_counter_stats_raw *prev = pool->raw; 6776 const uint64_t curr_time = MLX5_CURR_TIME_SEC; 6777 const uint32_t time_delta = curr_time - pool->time_of_last_age_check; 6778 uint16_t expected = AGE_CANDIDATE; 6779 uint32_t i; 6780 6781 pool->time_of_last_age_check = curr_time; 6782 for (i = 0; i < MLX5_COUNTERS_PER_POOL; ++i) { 6783 cnt = MLX5_POOL_GET_CNT(pool, i); 6784 age_param = MLX5_CNT_TO_AGE(cnt); 6785 if (__atomic_load_n(&age_param->state, 6786 __ATOMIC_RELAXED) != AGE_CANDIDATE) 6787 continue; 6788 if (cur->data[i].hits != prev->data[i].hits) { 6789 __atomic_store_n(&age_param->sec_since_last_hit, 0, 6790 __ATOMIC_RELAXED); 6791 continue; 6792 } 6793 if (__atomic_add_fetch(&age_param->sec_since_last_hit, 6794 time_delta, 6795 __ATOMIC_RELAXED) <= age_param->timeout) 6796 continue; 6797 /** 6798 * Hold the lock first, or if between the 6799 * state AGE_TMOUT and tailq operation the 6800 * release happened, the release procedure 6801 * may delete a non-existent tailq node. 6802 */ 6803 priv = rte_eth_devices[age_param->port_id].data->dev_private; 6804 age_info = GET_PORT_AGE_INFO(priv); 6805 rte_spinlock_lock(&age_info->aged_sl); 6806 if (__atomic_compare_exchange_n(&age_param->state, &expected, 6807 AGE_TMOUT, false, 6808 __ATOMIC_RELAXED, 6809 __ATOMIC_RELAXED)) { 6810 TAILQ_INSERT_TAIL(&age_info->aged_counters, cnt, next); 6811 MLX5_AGE_SET(age_info, MLX5_AGE_EVENT_NEW); 6812 } 6813 rte_spinlock_unlock(&age_info->aged_sl); 6814 } 6815 mlx5_age_event_prepare(sh); 6816 } 6817 6818 /** 6819 * Handler for the HW respond about ready values from an asynchronous batch 6820 * query. This function is probably called by the host thread. 6821 * 6822 * @param[in] sh 6823 * The pointer to the shared device context. 6824 * @param[in] async_id 6825 * The Devx async ID. 6826 * @param[in] status 6827 * The status of the completion. 6828 */ 6829 void 6830 mlx5_flow_async_pool_query_handle(struct mlx5_dev_ctx_shared *sh, 6831 uint64_t async_id, int status) 6832 { 6833 struct mlx5_flow_counter_pool *pool = 6834 (struct mlx5_flow_counter_pool *)(uintptr_t)async_id; 6835 struct mlx5_counter_stats_raw *raw_to_free; 6836 uint8_t query_gen = pool->query_gen ^ 1; 6837 struct mlx5_flow_counter_mng *cmng = &sh->cmng; 6838 enum mlx5_counter_type cnt_type = 6839 pool->is_aged ? MLX5_COUNTER_TYPE_AGE : 6840 MLX5_COUNTER_TYPE_ORIGIN; 6841 6842 if (unlikely(status)) { 6843 raw_to_free = pool->raw_hw; 6844 } else { 6845 raw_to_free = pool->raw; 6846 if (pool->is_aged) 6847 mlx5_flow_aging_check(sh, pool); 6848 rte_spinlock_lock(&pool->sl); 6849 pool->raw = pool->raw_hw; 6850 rte_spinlock_unlock(&pool->sl); 6851 /* Be sure the new raw counters data is updated in memory. */ 6852 rte_io_wmb(); 6853 if (!TAILQ_EMPTY(&pool->counters[query_gen])) { 6854 rte_spinlock_lock(&cmng->csl[cnt_type]); 6855 TAILQ_CONCAT(&cmng->counters[cnt_type], 6856 &pool->counters[query_gen], next); 6857 rte_spinlock_unlock(&cmng->csl[cnt_type]); 6858 } 6859 } 6860 LIST_INSERT_HEAD(&sh->cmng.free_stat_raws, raw_to_free, next); 6861 pool->raw_hw = NULL; 6862 sh->cmng.pending_queries--; 6863 } 6864 6865 static int 6866 flow_group_to_table(uint32_t port_id, uint32_t group, uint32_t *table, 6867 const struct flow_grp_info *grp_info, 6868 struct rte_flow_error *error) 6869 { 6870 if (grp_info->transfer && grp_info->external && 6871 grp_info->fdb_def_rule) { 6872 if (group == UINT32_MAX) 6873 return rte_flow_error_set 6874 (error, EINVAL, 6875 RTE_FLOW_ERROR_TYPE_ATTR_GROUP, 6876 NULL, 6877 "group index not supported"); 6878 *table = group + 1; 6879 } else { 6880 *table = group; 6881 } 6882 DRV_LOG(DEBUG, "port %u group=%#x table=%#x", port_id, group, *table); 6883 return 0; 6884 } 6885 6886 /** 6887 * Translate the rte_flow group index to HW table value. 6888 * 6889 * If tunnel offload is disabled, all group ids converted to flow table 6890 * id using the standard method. 6891 * If tunnel offload is enabled, group id can be converted using the 6892 * standard or tunnel conversion method. Group conversion method 6893 * selection depends on flags in `grp_info` parameter: 6894 * - Internal (grp_info.external == 0) groups conversion uses the 6895 * standard method. 6896 * - Group ids in JUMP action converted with the tunnel conversion. 6897 * - Group id in rule attribute conversion depends on a rule type and 6898 * group id value: 6899 * ** non zero group attributes converted with the tunnel method 6900 * ** zero group attribute in non-tunnel rule is converted using the 6901 * standard method - there's only one root table 6902 * ** zero group attribute in steer tunnel rule is converted with the 6903 * standard method - single root table 6904 * ** zero group attribute in match tunnel rule is a special OvS 6905 * case: that value is used for portability reasons. That group 6906 * id is converted with the tunnel conversion method. 6907 * 6908 * @param[in] dev 6909 * Port device 6910 * @param[in] tunnel 6911 * PMD tunnel offload object 6912 * @param[in] group 6913 * rte_flow group index value. 6914 * @param[out] table 6915 * HW table value. 6916 * @param[in] grp_info 6917 * flags used for conversion 6918 * @param[out] error 6919 * Pointer to error structure. 6920 * 6921 * @return 6922 * 0 on success, a negative errno value otherwise and rte_errno is set. 6923 */ 6924 int 6925 mlx5_flow_group_to_table(struct rte_eth_dev *dev, 6926 const struct mlx5_flow_tunnel *tunnel, 6927 uint32_t group, uint32_t *table, 6928 const struct flow_grp_info *grp_info, 6929 struct rte_flow_error *error) 6930 { 6931 int ret; 6932 bool standard_translation; 6933 6934 if (!grp_info->skip_scale && grp_info->external && 6935 group < MLX5_MAX_TABLES_EXTERNAL) 6936 group *= MLX5_FLOW_TABLE_FACTOR; 6937 if (is_tunnel_offload_active(dev)) { 6938 standard_translation = !grp_info->external || 6939 grp_info->std_tbl_fix; 6940 } else { 6941 standard_translation = true; 6942 } 6943 DRV_LOG(DEBUG, 6944 "port %u group=%u transfer=%d external=%d fdb_def_rule=%d translate=%s", 6945 dev->data->port_id, group, grp_info->transfer, 6946 grp_info->external, grp_info->fdb_def_rule, 6947 standard_translation ? "STANDARD" : "TUNNEL"); 6948 if (standard_translation) 6949 ret = flow_group_to_table(dev->data->port_id, group, table, 6950 grp_info, error); 6951 else 6952 ret = tunnel_flow_group_to_flow_table(dev, tunnel, group, 6953 table, error); 6954 6955 return ret; 6956 } 6957 6958 /** 6959 * Discover availability of metadata reg_c's. 6960 * 6961 * Iteratively use test flows to check availability. 6962 * 6963 * @param[in] dev 6964 * Pointer to the Ethernet device structure. 6965 * 6966 * @return 6967 * 0 on success, a negative errno value otherwise and rte_errno is set. 6968 */ 6969 int 6970 mlx5_flow_discover_mreg_c(struct rte_eth_dev *dev) 6971 { 6972 struct mlx5_priv *priv = dev->data->dev_private; 6973 struct mlx5_dev_config *config = &priv->config; 6974 enum modify_reg idx; 6975 int n = 0; 6976 6977 /* reg_c[0] and reg_c[1] are reserved. */ 6978 config->flow_mreg_c[n++] = REG_C_0; 6979 config->flow_mreg_c[n++] = REG_C_1; 6980 /* Discover availability of other reg_c's. */ 6981 for (idx = REG_C_2; idx <= REG_C_7; ++idx) { 6982 struct rte_flow_attr attr = { 6983 .group = MLX5_FLOW_MREG_CP_TABLE_GROUP, 6984 .priority = MLX5_FLOW_PRIO_RSVD, 6985 .ingress = 1, 6986 }; 6987 struct rte_flow_item items[] = { 6988 [0] = { 6989 .type = RTE_FLOW_ITEM_TYPE_END, 6990 }, 6991 }; 6992 struct rte_flow_action actions[] = { 6993 [0] = { 6994 .type = (enum rte_flow_action_type) 6995 MLX5_RTE_FLOW_ACTION_TYPE_COPY_MREG, 6996 .conf = &(struct mlx5_flow_action_copy_mreg){ 6997 .src = REG_C_1, 6998 .dst = idx, 6999 }, 7000 }, 7001 [1] = { 7002 .type = RTE_FLOW_ACTION_TYPE_JUMP, 7003 .conf = &(struct rte_flow_action_jump){ 7004 .group = MLX5_FLOW_MREG_ACT_TABLE_GROUP, 7005 }, 7006 }, 7007 [2] = { 7008 .type = RTE_FLOW_ACTION_TYPE_END, 7009 }, 7010 }; 7011 uint32_t flow_idx; 7012 struct rte_flow *flow; 7013 struct rte_flow_error error; 7014 7015 if (!config->dv_flow_en) 7016 break; 7017 /* Create internal flow, validation skips copy action. */ 7018 flow_idx = flow_list_create(dev, NULL, &attr, items, 7019 actions, false, &error); 7020 flow = mlx5_ipool_get(priv->sh->ipool[MLX5_IPOOL_RTE_FLOW], 7021 flow_idx); 7022 if (!flow) 7023 continue; 7024 config->flow_mreg_c[n++] = idx; 7025 flow_list_destroy(dev, NULL, flow_idx); 7026 } 7027 for (; n < MLX5_MREG_C_NUM; ++n) 7028 config->flow_mreg_c[n] = REG_NON; 7029 return 0; 7030 } 7031 7032 /** 7033 * Dump flow raw hw data to file 7034 * 7035 * @param[in] dev 7036 * The pointer to Ethernet device. 7037 * @param[in] file 7038 * A pointer to a file for output. 7039 * @param[out] error 7040 * Perform verbose error reporting if not NULL. PMDs initialize this 7041 * structure in case of error only. 7042 * @return 7043 * 0 on success, a nagative value otherwise. 7044 */ 7045 int 7046 mlx5_flow_dev_dump(struct rte_eth_dev *dev, 7047 FILE *file, 7048 struct rte_flow_error *error __rte_unused) 7049 { 7050 struct mlx5_priv *priv = dev->data->dev_private; 7051 struct mlx5_dev_ctx_shared *sh = priv->sh; 7052 7053 if (!priv->config.dv_flow_en) { 7054 if (fputs("device dv flow disabled\n", file) <= 0) 7055 return -errno; 7056 return -ENOTSUP; 7057 } 7058 return mlx5_devx_cmd_flow_dump(sh->fdb_domain, sh->rx_domain, 7059 sh->tx_domain, file); 7060 } 7061 7062 /** 7063 * Get aged-out flows. 7064 * 7065 * @param[in] dev 7066 * Pointer to the Ethernet device structure. 7067 * @param[in] context 7068 * The address of an array of pointers to the aged-out flows contexts. 7069 * @param[in] nb_countexts 7070 * The length of context array pointers. 7071 * @param[out] error 7072 * Perform verbose error reporting if not NULL. Initialized in case of 7073 * error only. 7074 * 7075 * @return 7076 * how many contexts get in success, otherwise negative errno value. 7077 * if nb_contexts is 0, return the amount of all aged contexts. 7078 * if nb_contexts is not 0 , return the amount of aged flows reported 7079 * in the context array. 7080 */ 7081 int 7082 mlx5_flow_get_aged_flows(struct rte_eth_dev *dev, void **contexts, 7083 uint32_t nb_contexts, struct rte_flow_error *error) 7084 { 7085 const struct mlx5_flow_driver_ops *fops; 7086 struct rte_flow_attr attr = { .transfer = 0 }; 7087 7088 if (flow_get_drv_type(dev, &attr) == MLX5_FLOW_TYPE_DV) { 7089 fops = flow_get_drv_ops(MLX5_FLOW_TYPE_DV); 7090 return fops->get_aged_flows(dev, contexts, nb_contexts, 7091 error); 7092 } 7093 DRV_LOG(ERR, 7094 "port %u get aged flows is not supported.", 7095 dev->data->port_id); 7096 return -ENOTSUP; 7097 } 7098 7099 /* Wrapper for driver action_validate op callback */ 7100 static int 7101 flow_drv_action_validate(struct rte_eth_dev *dev, 7102 const struct rte_flow_shared_action_conf *conf, 7103 const struct rte_flow_action *action, 7104 const struct mlx5_flow_driver_ops *fops, 7105 struct rte_flow_error *error) 7106 { 7107 static const char err_msg[] = "shared action validation unsupported"; 7108 7109 if (!fops->action_validate) { 7110 DRV_LOG(ERR, "port %u %s.", dev->data->port_id, err_msg); 7111 rte_flow_error_set(error, ENOTSUP, RTE_FLOW_ERROR_TYPE_ACTION, 7112 NULL, err_msg); 7113 return -rte_errno; 7114 } 7115 return fops->action_validate(dev, conf, action, error); 7116 } 7117 7118 /** 7119 * Destroys the shared action by handle. 7120 * 7121 * @param dev 7122 * Pointer to Ethernet device structure. 7123 * @param[in] action 7124 * Handle for the shared action to be destroyed. 7125 * @param[out] error 7126 * Perform verbose error reporting if not NULL. PMDs initialize this 7127 * structure in case of error only. 7128 * 7129 * @return 7130 * 0 on success, a negative errno value otherwise and rte_errno is set. 7131 * 7132 * @note: wrapper for driver action_create op callback. 7133 */ 7134 static int 7135 mlx5_shared_action_destroy(struct rte_eth_dev *dev, 7136 struct rte_flow_shared_action *action, 7137 struct rte_flow_error *error) 7138 { 7139 static const char err_msg[] = "shared action destruction unsupported"; 7140 struct rte_flow_attr attr = { .transfer = 0 }; 7141 const struct mlx5_flow_driver_ops *fops = 7142 flow_get_drv_ops(flow_get_drv_type(dev, &attr)); 7143 7144 if (!fops->action_destroy) { 7145 DRV_LOG(ERR, "port %u %s.", dev->data->port_id, err_msg); 7146 rte_flow_error_set(error, ENOTSUP, RTE_FLOW_ERROR_TYPE_ACTION, 7147 NULL, err_msg); 7148 return -rte_errno; 7149 } 7150 return fops->action_destroy(dev, action, error); 7151 } 7152 7153 /* Wrapper for driver action_destroy op callback */ 7154 static int 7155 flow_drv_action_update(struct rte_eth_dev *dev, 7156 struct rte_flow_shared_action *action, 7157 const void *action_conf, 7158 const struct mlx5_flow_driver_ops *fops, 7159 struct rte_flow_error *error) 7160 { 7161 static const char err_msg[] = "shared action update unsupported"; 7162 7163 if (!fops->action_update) { 7164 DRV_LOG(ERR, "port %u %s.", dev->data->port_id, err_msg); 7165 rte_flow_error_set(error, ENOTSUP, RTE_FLOW_ERROR_TYPE_ACTION, 7166 NULL, err_msg); 7167 return -rte_errno; 7168 } 7169 return fops->action_update(dev, action, action_conf, error); 7170 } 7171 7172 /* Wrapper for driver action_destroy op callback */ 7173 static int 7174 flow_drv_action_query(struct rte_eth_dev *dev, 7175 const struct rte_flow_shared_action *action, 7176 void *data, 7177 const struct mlx5_flow_driver_ops *fops, 7178 struct rte_flow_error *error) 7179 { 7180 static const char err_msg[] = "shared action query unsupported"; 7181 7182 if (!fops->action_query) { 7183 DRV_LOG(ERR, "port %u %s.", dev->data->port_id, err_msg); 7184 rte_flow_error_set(error, ENOTSUP, RTE_FLOW_ERROR_TYPE_ACTION, 7185 NULL, err_msg); 7186 return -rte_errno; 7187 } 7188 return fops->action_query(dev, action, data, error); 7189 } 7190 7191 /** 7192 * Create shared action for reuse in multiple flow rules. 7193 * 7194 * @param dev 7195 * Pointer to Ethernet device structure. 7196 * @param[in] action 7197 * Action configuration for shared action creation. 7198 * @param[out] error 7199 * Perform verbose error reporting if not NULL. PMDs initialize this 7200 * structure in case of error only. 7201 * @return 7202 * A valid handle in case of success, NULL otherwise and rte_errno is set. 7203 */ 7204 static struct rte_flow_shared_action * 7205 mlx5_shared_action_create(struct rte_eth_dev *dev, 7206 const struct rte_flow_shared_action_conf *conf, 7207 const struct rte_flow_action *action, 7208 struct rte_flow_error *error) 7209 { 7210 static const char err_msg[] = "shared action creation unsupported"; 7211 struct rte_flow_attr attr = { .transfer = 0 }; 7212 const struct mlx5_flow_driver_ops *fops = 7213 flow_get_drv_ops(flow_get_drv_type(dev, &attr)); 7214 7215 if (flow_drv_action_validate(dev, conf, action, fops, error)) 7216 return NULL; 7217 if (!fops->action_create) { 7218 DRV_LOG(ERR, "port %u %s.", dev->data->port_id, err_msg); 7219 rte_flow_error_set(error, ENOTSUP, RTE_FLOW_ERROR_TYPE_ACTION, 7220 NULL, err_msg); 7221 return NULL; 7222 } 7223 return fops->action_create(dev, conf, action, error); 7224 } 7225 7226 /** 7227 * Updates inplace the shared action configuration pointed by *action* handle 7228 * with the configuration provided as *action* argument. 7229 * The update of the shared action configuration effects all flow rules reusing 7230 * the action via handle. 7231 * 7232 * @param dev 7233 * Pointer to Ethernet device structure. 7234 * @param[in] shared_action 7235 * Handle for the shared action to be updated. 7236 * @param[in] action 7237 * Action specification used to modify the action pointed by handle. 7238 * *action* should be of same type with the action pointed by the *action* 7239 * handle argument, otherwise considered as invalid. 7240 * @param[out] error 7241 * Perform verbose error reporting if not NULL. PMDs initialize this 7242 * structure in case of error only. 7243 * 7244 * @return 7245 * 0 on success, a negative errno value otherwise and rte_errno is set. 7246 */ 7247 static int 7248 mlx5_shared_action_update(struct rte_eth_dev *dev, 7249 struct rte_flow_shared_action *shared_action, 7250 const struct rte_flow_action *action, 7251 struct rte_flow_error *error) 7252 { 7253 struct rte_flow_attr attr = { .transfer = 0 }; 7254 const struct mlx5_flow_driver_ops *fops = 7255 flow_get_drv_ops(flow_get_drv_type(dev, &attr)); 7256 int ret; 7257 7258 ret = flow_drv_action_validate(dev, NULL, action, fops, error); 7259 if (ret) 7260 return ret; 7261 return flow_drv_action_update(dev, shared_action, action->conf, fops, 7262 error); 7263 } 7264 7265 /** 7266 * Query the shared action by handle. 7267 * 7268 * This function allows retrieving action-specific data such as counters. 7269 * Data is gathered by special action which may be present/referenced in 7270 * more than one flow rule definition. 7271 * 7272 * \see RTE_FLOW_ACTION_TYPE_COUNT 7273 * 7274 * @param dev 7275 * Pointer to Ethernet device structure. 7276 * @param[in] action 7277 * Handle for the shared action to query. 7278 * @param[in, out] data 7279 * Pointer to storage for the associated query data type. 7280 * @param[out] error 7281 * Perform verbose error reporting if not NULL. PMDs initialize this 7282 * structure in case of error only. 7283 * 7284 * @return 7285 * 0 on success, a negative errno value otherwise and rte_errno is set. 7286 */ 7287 static int 7288 mlx5_shared_action_query(struct rte_eth_dev *dev, 7289 const struct rte_flow_shared_action *action, 7290 void *data, 7291 struct rte_flow_error *error) 7292 { 7293 struct rte_flow_attr attr = { .transfer = 0 }; 7294 const struct mlx5_flow_driver_ops *fops = 7295 flow_get_drv_ops(flow_get_drv_type(dev, &attr)); 7296 7297 return flow_drv_action_query(dev, action, data, fops, error); 7298 } 7299 7300 /** 7301 * Destroy all shared actions. 7302 * 7303 * @param dev 7304 * Pointer to Ethernet device. 7305 * 7306 * @return 7307 * 0 on success, a negative errno value otherwise and rte_errno is set. 7308 */ 7309 int 7310 mlx5_shared_action_flush(struct rte_eth_dev *dev) 7311 { 7312 struct rte_flow_error error; 7313 struct mlx5_priv *priv = dev->data->dev_private; 7314 struct mlx5_shared_action_rss *action; 7315 int ret = 0; 7316 uint32_t idx; 7317 7318 ILIST_FOREACH(priv->sh->ipool[MLX5_IPOOL_RSS_SHARED_ACTIONS], 7319 priv->rss_shared_actions, idx, action, next) { 7320 ret |= mlx5_shared_action_destroy(dev, 7321 (struct rte_flow_shared_action *)(uintptr_t)idx, &error); 7322 } 7323 return ret; 7324 } 7325 7326 #ifndef HAVE_MLX5DV_DR 7327 #define MLX5_DOMAIN_SYNC_FLOW ((1 << 0) | (1 << 1)) 7328 #else 7329 #define MLX5_DOMAIN_SYNC_FLOW \ 7330 (MLX5DV_DR_DOMAIN_SYNC_FLAGS_SW | MLX5DV_DR_DOMAIN_SYNC_FLAGS_HW) 7331 #endif 7332 7333 int rte_pmd_mlx5_sync_flow(uint16_t port_id, uint32_t domains) 7334 { 7335 struct rte_eth_dev *dev = &rte_eth_devices[port_id]; 7336 const struct mlx5_flow_driver_ops *fops; 7337 int ret; 7338 struct rte_flow_attr attr = { .transfer = 0 }; 7339 7340 fops = flow_get_drv_ops(flow_get_drv_type(dev, &attr)); 7341 ret = fops->sync_domain(dev, domains, MLX5_DOMAIN_SYNC_FLOW); 7342 if (ret > 0) 7343 ret = -ret; 7344 return ret; 7345 } 7346 7347 /** 7348 * tunnel offload functionalilty is defined for DV environment only 7349 */ 7350 #ifdef HAVE_IBV_FLOW_DV_SUPPORT 7351 __extension__ 7352 union tunnel_offload_mark { 7353 uint32_t val; 7354 struct { 7355 uint32_t app_reserve:8; 7356 uint32_t table_id:15; 7357 uint32_t transfer:1; 7358 uint32_t _unused_:8; 7359 }; 7360 }; 7361 7362 static bool 7363 mlx5_access_tunnel_offload_db 7364 (struct rte_eth_dev *dev, 7365 bool (*match)(struct rte_eth_dev *, 7366 struct mlx5_flow_tunnel *, const void *), 7367 void (*hit)(struct rte_eth_dev *, struct mlx5_flow_tunnel *, void *), 7368 void (*miss)(struct rte_eth_dev *, void *), 7369 void *ctx, bool lock_op); 7370 7371 static int 7372 flow_tunnel_add_default_miss(struct rte_eth_dev *dev, 7373 struct rte_flow *flow, 7374 const struct rte_flow_attr *attr, 7375 const struct rte_flow_action *app_actions, 7376 uint32_t flow_idx, 7377 struct tunnel_default_miss_ctx *ctx, 7378 struct rte_flow_error *error) 7379 { 7380 struct mlx5_priv *priv = dev->data->dev_private; 7381 struct mlx5_flow *dev_flow; 7382 struct rte_flow_attr miss_attr = *attr; 7383 const struct mlx5_flow_tunnel *tunnel = app_actions[0].conf; 7384 const struct rte_flow_item miss_items[2] = { 7385 { 7386 .type = RTE_FLOW_ITEM_TYPE_ETH, 7387 .spec = NULL, 7388 .last = NULL, 7389 .mask = NULL 7390 }, 7391 { 7392 .type = RTE_FLOW_ITEM_TYPE_END, 7393 .spec = NULL, 7394 .last = NULL, 7395 .mask = NULL 7396 } 7397 }; 7398 union tunnel_offload_mark mark_id; 7399 struct rte_flow_action_mark miss_mark; 7400 struct rte_flow_action miss_actions[3] = { 7401 [0] = { .type = RTE_FLOW_ACTION_TYPE_MARK, .conf = &miss_mark }, 7402 [2] = { .type = RTE_FLOW_ACTION_TYPE_END, .conf = NULL } 7403 }; 7404 const struct rte_flow_action_jump *jump_data; 7405 uint32_t i, flow_table = 0; /* prevent compilation warning */ 7406 struct flow_grp_info grp_info = { 7407 .external = 1, 7408 .transfer = attr->transfer, 7409 .fdb_def_rule = !!priv->fdb_def_rule, 7410 .std_tbl_fix = 0, 7411 }; 7412 int ret; 7413 7414 if (!attr->transfer) { 7415 uint32_t q_size; 7416 7417 miss_actions[1].type = RTE_FLOW_ACTION_TYPE_RSS; 7418 q_size = priv->reta_idx_n * sizeof(ctx->queue[0]); 7419 ctx->queue = mlx5_malloc(MLX5_MEM_SYS | MLX5_MEM_ZERO, q_size, 7420 0, SOCKET_ID_ANY); 7421 if (!ctx->queue) 7422 return rte_flow_error_set 7423 (error, ENOMEM, 7424 RTE_FLOW_ERROR_TYPE_ACTION_CONF, 7425 NULL, "invalid default miss RSS"); 7426 ctx->action_rss.func = RTE_ETH_HASH_FUNCTION_DEFAULT, 7427 ctx->action_rss.level = 0, 7428 ctx->action_rss.types = priv->rss_conf.rss_hf, 7429 ctx->action_rss.key_len = priv->rss_conf.rss_key_len, 7430 ctx->action_rss.queue_num = priv->reta_idx_n, 7431 ctx->action_rss.key = priv->rss_conf.rss_key, 7432 ctx->action_rss.queue = ctx->queue; 7433 if (!priv->reta_idx_n || !priv->rxqs_n) 7434 return rte_flow_error_set 7435 (error, EINVAL, 7436 RTE_FLOW_ERROR_TYPE_ACTION_CONF, 7437 NULL, "invalid port configuration"); 7438 if (!(dev->data->dev_conf.rxmode.mq_mode & ETH_MQ_RX_RSS_FLAG)) 7439 ctx->action_rss.types = 0; 7440 for (i = 0; i != priv->reta_idx_n; ++i) 7441 ctx->queue[i] = (*priv->reta_idx)[i]; 7442 } else { 7443 miss_actions[1].type = RTE_FLOW_ACTION_TYPE_JUMP; 7444 ctx->miss_jump.group = MLX5_TNL_MISS_FDB_JUMP_GRP; 7445 } 7446 miss_actions[1].conf = (typeof(miss_actions[1].conf))ctx->raw; 7447 for (; app_actions->type != RTE_FLOW_ACTION_TYPE_JUMP; app_actions++); 7448 jump_data = app_actions->conf; 7449 miss_attr.priority = MLX5_TNL_MISS_RULE_PRIORITY; 7450 miss_attr.group = jump_data->group; 7451 ret = mlx5_flow_group_to_table(dev, tunnel, jump_data->group, 7452 &flow_table, &grp_info, error); 7453 if (ret) 7454 return rte_flow_error_set(error, EINVAL, 7455 RTE_FLOW_ERROR_TYPE_ACTION_CONF, 7456 NULL, "invalid tunnel id"); 7457 mark_id.app_reserve = 0; 7458 mark_id.table_id = tunnel_flow_tbl_to_id(flow_table); 7459 mark_id.transfer = !!attr->transfer; 7460 mark_id._unused_ = 0; 7461 miss_mark.id = mark_id.val; 7462 dev_flow = flow_drv_prepare(dev, flow, &miss_attr, 7463 miss_items, miss_actions, flow_idx, error); 7464 if (!dev_flow) 7465 return -rte_errno; 7466 dev_flow->flow = flow; 7467 dev_flow->external = true; 7468 dev_flow->tunnel = tunnel; 7469 /* Subflow object was created, we must include one in the list. */ 7470 SILIST_INSERT(&flow->dev_handles, dev_flow->handle_idx, 7471 dev_flow->handle, next); 7472 DRV_LOG(DEBUG, 7473 "port %u tunnel type=%d id=%u miss rule priority=%u group=%u", 7474 dev->data->port_id, tunnel->app_tunnel.type, 7475 tunnel->tunnel_id, miss_attr.priority, miss_attr.group); 7476 ret = flow_drv_translate(dev, dev_flow, &miss_attr, miss_items, 7477 miss_actions, error); 7478 if (!ret) 7479 ret = flow_mreg_update_copy_table(dev, flow, miss_actions, 7480 error); 7481 7482 return ret; 7483 } 7484 7485 static const struct mlx5_flow_tbl_data_entry * 7486 tunnel_mark_decode(struct rte_eth_dev *dev, uint32_t mark) 7487 { 7488 struct mlx5_priv *priv = dev->data->dev_private; 7489 struct mlx5_dev_ctx_shared *sh = priv->sh; 7490 struct mlx5_hlist_entry *he; 7491 union tunnel_offload_mark mbits = { .val = mark }; 7492 union mlx5_flow_tbl_key table_key = { 7493 { 7494 .table_id = tunnel_id_to_flow_tbl(mbits.table_id), 7495 .dummy = 0, 7496 .domain = !!mbits.transfer, 7497 .direction = 0, 7498 } 7499 }; 7500 he = mlx5_hlist_lookup(sh->flow_tbls, table_key.v64, NULL); 7501 return he ? 7502 container_of(he, struct mlx5_flow_tbl_data_entry, entry) : NULL; 7503 } 7504 7505 static void 7506 mlx5_flow_tunnel_grp2tbl_remove_cb(struct mlx5_hlist *list, 7507 struct mlx5_hlist_entry *entry) 7508 { 7509 struct mlx5_dev_ctx_shared *sh = list->ctx; 7510 struct tunnel_tbl_entry *tte = container_of(entry, typeof(*tte), hash); 7511 7512 mlx5_ipool_free(sh->ipool[MLX5_IPOOL_TNL_TBL_ID], 7513 tunnel_flow_tbl_to_id(tte->flow_table)); 7514 mlx5_free(tte); 7515 } 7516 7517 static int 7518 mlx5_flow_tunnel_grp2tbl_match_cb(struct mlx5_hlist *list __rte_unused, 7519 struct mlx5_hlist_entry *entry, 7520 uint64_t key, void *cb_ctx __rte_unused) 7521 { 7522 union tunnel_tbl_key tbl = { 7523 .val = key, 7524 }; 7525 struct tunnel_tbl_entry *tte = container_of(entry, typeof(*tte), hash); 7526 7527 return tbl.tunnel_id != tte->tunnel_id || tbl.group != tte->group; 7528 } 7529 7530 static struct mlx5_hlist_entry * 7531 mlx5_flow_tunnel_grp2tbl_create_cb(struct mlx5_hlist *list, uint64_t key, 7532 void *ctx __rte_unused) 7533 { 7534 struct mlx5_dev_ctx_shared *sh = list->ctx; 7535 struct tunnel_tbl_entry *tte; 7536 union tunnel_tbl_key tbl = { 7537 .val = key, 7538 }; 7539 7540 tte = mlx5_malloc(MLX5_MEM_SYS | MLX5_MEM_ZERO, 7541 sizeof(*tte), 0, 7542 SOCKET_ID_ANY); 7543 if (!tte) 7544 goto err; 7545 mlx5_ipool_malloc(sh->ipool[MLX5_IPOOL_TNL_TBL_ID], 7546 &tte->flow_table); 7547 if (tte->flow_table >= MLX5_MAX_TABLES) { 7548 DRV_LOG(ERR, "Tunnel TBL ID %d exceed max limit.", 7549 tte->flow_table); 7550 mlx5_ipool_free(sh->ipool[MLX5_IPOOL_TNL_TBL_ID], 7551 tte->flow_table); 7552 goto err; 7553 } else if (!tte->flow_table) { 7554 goto err; 7555 } 7556 tte->flow_table = tunnel_id_to_flow_tbl(tte->flow_table); 7557 tte->tunnel_id = tbl.tunnel_id; 7558 tte->group = tbl.group; 7559 return &tte->hash; 7560 err: 7561 if (tte) 7562 mlx5_free(tte); 7563 return NULL; 7564 } 7565 7566 static uint32_t 7567 tunnel_flow_group_to_flow_table(struct rte_eth_dev *dev, 7568 const struct mlx5_flow_tunnel *tunnel, 7569 uint32_t group, uint32_t *table, 7570 struct rte_flow_error *error) 7571 { 7572 struct mlx5_hlist_entry *he; 7573 struct tunnel_tbl_entry *tte; 7574 union tunnel_tbl_key key = { 7575 .tunnel_id = tunnel ? tunnel->tunnel_id : 0, 7576 .group = group 7577 }; 7578 struct mlx5_flow_tunnel_hub *thub = mlx5_tunnel_hub(dev); 7579 struct mlx5_hlist *group_hash; 7580 7581 group_hash = tunnel ? tunnel->groups : thub->groups; 7582 he = mlx5_hlist_register(group_hash, key.val, NULL); 7583 if (!he) 7584 return rte_flow_error_set(error, EINVAL, 7585 RTE_FLOW_ERROR_TYPE_ATTR_GROUP, 7586 NULL, 7587 "tunnel group index not supported"); 7588 tte = container_of(he, typeof(*tte), hash); 7589 *table = tte->flow_table; 7590 DRV_LOG(DEBUG, "port %u tunnel %u group=%#x table=%#x", 7591 dev->data->port_id, key.tunnel_id, group, *table); 7592 return 0; 7593 } 7594 7595 static void 7596 mlx5_flow_tunnel_free(struct rte_eth_dev *dev, 7597 struct mlx5_flow_tunnel *tunnel) 7598 { 7599 struct mlx5_priv *priv = dev->data->dev_private; 7600 struct mlx5_indexed_pool *ipool; 7601 7602 DRV_LOG(DEBUG, "port %u release pmd tunnel id=0x%x", 7603 dev->data->port_id, tunnel->tunnel_id); 7604 LIST_REMOVE(tunnel, chain); 7605 mlx5_hlist_destroy(tunnel->groups); 7606 ipool = priv->sh->ipool[MLX5_IPOOL_TUNNEL_ID]; 7607 mlx5_ipool_free(ipool, tunnel->tunnel_id); 7608 } 7609 7610 static bool 7611 mlx5_access_tunnel_offload_db 7612 (struct rte_eth_dev *dev, 7613 bool (*match)(struct rte_eth_dev *, 7614 struct mlx5_flow_tunnel *, const void *), 7615 void (*hit)(struct rte_eth_dev *, struct mlx5_flow_tunnel *, void *), 7616 void (*miss)(struct rte_eth_dev *, void *), 7617 void *ctx, bool lock_op) 7618 { 7619 bool verdict = false; 7620 struct mlx5_flow_tunnel_hub *thub = mlx5_tunnel_hub(dev); 7621 struct mlx5_flow_tunnel *tunnel; 7622 7623 rte_spinlock_lock(&thub->sl); 7624 LIST_FOREACH(tunnel, &thub->tunnels, chain) { 7625 verdict = match(dev, tunnel, (const void *)ctx); 7626 if (verdict) 7627 break; 7628 } 7629 if (!lock_op) 7630 rte_spinlock_unlock(&thub->sl); 7631 if (verdict && hit) 7632 hit(dev, tunnel, ctx); 7633 if (!verdict && miss) 7634 miss(dev, ctx); 7635 if (lock_op) 7636 rte_spinlock_unlock(&thub->sl); 7637 7638 return verdict; 7639 } 7640 7641 struct tunnel_db_find_tunnel_id_ctx { 7642 uint32_t tunnel_id; 7643 struct mlx5_flow_tunnel *tunnel; 7644 }; 7645 7646 static bool 7647 find_tunnel_id_match(struct rte_eth_dev *dev, 7648 struct mlx5_flow_tunnel *tunnel, const void *x) 7649 { 7650 const struct tunnel_db_find_tunnel_id_ctx *ctx = x; 7651 7652 RTE_SET_USED(dev); 7653 return tunnel->tunnel_id == ctx->tunnel_id; 7654 } 7655 7656 static void 7657 find_tunnel_id_hit(struct rte_eth_dev *dev, 7658 struct mlx5_flow_tunnel *tunnel, void *x) 7659 { 7660 struct tunnel_db_find_tunnel_id_ctx *ctx = x; 7661 RTE_SET_USED(dev); 7662 ctx->tunnel = tunnel; 7663 } 7664 7665 static struct mlx5_flow_tunnel * 7666 mlx5_find_tunnel_id(struct rte_eth_dev *dev, uint32_t id) 7667 { 7668 struct tunnel_db_find_tunnel_id_ctx ctx = { 7669 .tunnel_id = id, 7670 }; 7671 7672 mlx5_access_tunnel_offload_db(dev, find_tunnel_id_match, 7673 find_tunnel_id_hit, NULL, &ctx, true); 7674 7675 return ctx.tunnel; 7676 } 7677 7678 static struct mlx5_flow_tunnel * 7679 mlx5_flow_tunnel_allocate(struct rte_eth_dev *dev, 7680 const struct rte_flow_tunnel *app_tunnel) 7681 { 7682 struct mlx5_priv *priv = dev->data->dev_private; 7683 struct mlx5_indexed_pool *ipool; 7684 struct mlx5_flow_tunnel *tunnel; 7685 uint32_t id; 7686 7687 ipool = priv->sh->ipool[MLX5_IPOOL_TUNNEL_ID]; 7688 tunnel = mlx5_ipool_zmalloc(ipool, &id); 7689 if (!tunnel) 7690 return NULL; 7691 if (id >= MLX5_MAX_TUNNELS) { 7692 mlx5_ipool_free(ipool, id); 7693 DRV_LOG(ERR, "Tunnel ID %d exceed max limit.", id); 7694 return NULL; 7695 } 7696 tunnel->groups = mlx5_hlist_create("tunnel groups", 1024, 0, 0, 7697 mlx5_flow_tunnel_grp2tbl_create_cb, 7698 mlx5_flow_tunnel_grp2tbl_match_cb, 7699 mlx5_flow_tunnel_grp2tbl_remove_cb); 7700 if (!tunnel->groups) { 7701 mlx5_ipool_free(ipool, id); 7702 return NULL; 7703 } 7704 tunnel->groups->ctx = priv->sh; 7705 /* initiate new PMD tunnel */ 7706 memcpy(&tunnel->app_tunnel, app_tunnel, sizeof(*app_tunnel)); 7707 tunnel->tunnel_id = id; 7708 tunnel->action.type = (typeof(tunnel->action.type)) 7709 MLX5_RTE_FLOW_ACTION_TYPE_TUNNEL_SET; 7710 tunnel->action.conf = tunnel; 7711 tunnel->item.type = (typeof(tunnel->item.type)) 7712 MLX5_RTE_FLOW_ITEM_TYPE_TUNNEL; 7713 tunnel->item.spec = tunnel; 7714 tunnel->item.last = NULL; 7715 tunnel->item.mask = NULL; 7716 7717 DRV_LOG(DEBUG, "port %u new pmd tunnel id=0x%x", 7718 dev->data->port_id, tunnel->tunnel_id); 7719 7720 return tunnel; 7721 } 7722 7723 struct tunnel_db_get_tunnel_ctx { 7724 const struct rte_flow_tunnel *app_tunnel; 7725 struct mlx5_flow_tunnel *tunnel; 7726 }; 7727 7728 static bool get_tunnel_match(struct rte_eth_dev *dev, 7729 struct mlx5_flow_tunnel *tunnel, const void *x) 7730 { 7731 const struct tunnel_db_get_tunnel_ctx *ctx = x; 7732 7733 RTE_SET_USED(dev); 7734 return !memcmp(ctx->app_tunnel, &tunnel->app_tunnel, 7735 sizeof(*ctx->app_tunnel)); 7736 } 7737 7738 static void get_tunnel_hit(struct rte_eth_dev *dev, 7739 struct mlx5_flow_tunnel *tunnel, void *x) 7740 { 7741 /* called under tunnel spinlock protection */ 7742 struct tunnel_db_get_tunnel_ctx *ctx = x; 7743 7744 RTE_SET_USED(dev); 7745 tunnel->refctn++; 7746 ctx->tunnel = tunnel; 7747 } 7748 7749 static void get_tunnel_miss(struct rte_eth_dev *dev, void *x) 7750 { 7751 /* called under tunnel spinlock protection */ 7752 struct mlx5_flow_tunnel_hub *thub = mlx5_tunnel_hub(dev); 7753 struct tunnel_db_get_tunnel_ctx *ctx = x; 7754 7755 rte_spinlock_unlock(&thub->sl); 7756 ctx->tunnel = mlx5_flow_tunnel_allocate(dev, ctx->app_tunnel); 7757 ctx->tunnel->refctn = 1; 7758 rte_spinlock_lock(&thub->sl); 7759 if (ctx->tunnel) 7760 LIST_INSERT_HEAD(&thub->tunnels, ctx->tunnel, chain); 7761 } 7762 7763 7764 static int 7765 mlx5_get_flow_tunnel(struct rte_eth_dev *dev, 7766 const struct rte_flow_tunnel *app_tunnel, 7767 struct mlx5_flow_tunnel **tunnel) 7768 { 7769 struct tunnel_db_get_tunnel_ctx ctx = { 7770 .app_tunnel = app_tunnel, 7771 }; 7772 7773 mlx5_access_tunnel_offload_db(dev, get_tunnel_match, get_tunnel_hit, 7774 get_tunnel_miss, &ctx, true); 7775 *tunnel = ctx.tunnel; 7776 return ctx.tunnel ? 0 : -ENOMEM; 7777 } 7778 7779 void mlx5_release_tunnel_hub(struct mlx5_dev_ctx_shared *sh, uint16_t port_id) 7780 { 7781 struct mlx5_flow_tunnel_hub *thub = sh->tunnel_hub; 7782 7783 if (!thub) 7784 return; 7785 if (!LIST_EMPTY(&thub->tunnels)) 7786 DRV_LOG(WARNING, "port %u tunnels present\n", port_id); 7787 mlx5_hlist_destroy(thub->groups); 7788 mlx5_free(thub); 7789 } 7790 7791 int mlx5_alloc_tunnel_hub(struct mlx5_dev_ctx_shared *sh) 7792 { 7793 int err; 7794 struct mlx5_flow_tunnel_hub *thub; 7795 7796 thub = mlx5_malloc(MLX5_MEM_SYS | MLX5_MEM_ZERO, sizeof(*thub), 7797 0, SOCKET_ID_ANY); 7798 if (!thub) 7799 return -ENOMEM; 7800 LIST_INIT(&thub->tunnels); 7801 rte_spinlock_init(&thub->sl); 7802 thub->groups = mlx5_hlist_create("flow groups", MLX5_MAX_TABLES, 0, 7803 0, mlx5_flow_tunnel_grp2tbl_create_cb, 7804 mlx5_flow_tunnel_grp2tbl_match_cb, 7805 mlx5_flow_tunnel_grp2tbl_remove_cb); 7806 if (!thub->groups) { 7807 err = -rte_errno; 7808 goto err; 7809 } 7810 thub->groups->ctx = sh; 7811 sh->tunnel_hub = thub; 7812 7813 return 0; 7814 7815 err: 7816 if (thub->groups) 7817 mlx5_hlist_destroy(thub->groups); 7818 if (thub) 7819 mlx5_free(thub); 7820 return err; 7821 } 7822 7823 static inline bool 7824 mlx5_flow_tunnel_validate(struct rte_eth_dev *dev, 7825 struct rte_flow_tunnel *tunnel, 7826 const char *err_msg) 7827 { 7828 err_msg = NULL; 7829 if (!is_tunnel_offload_active(dev)) { 7830 err_msg = "tunnel offload was not activated"; 7831 goto out; 7832 } else if (!tunnel) { 7833 err_msg = "no application tunnel"; 7834 goto out; 7835 } 7836 7837 switch (tunnel->type) { 7838 default: 7839 err_msg = "unsupported tunnel type"; 7840 goto out; 7841 case RTE_FLOW_ITEM_TYPE_VXLAN: 7842 break; 7843 } 7844 7845 out: 7846 return !err_msg; 7847 } 7848 7849 static int 7850 mlx5_flow_tunnel_decap_set(struct rte_eth_dev *dev, 7851 struct rte_flow_tunnel *app_tunnel, 7852 struct rte_flow_action **actions, 7853 uint32_t *num_of_actions, 7854 struct rte_flow_error *error) 7855 { 7856 int ret; 7857 struct mlx5_flow_tunnel *tunnel; 7858 const char *err_msg = NULL; 7859 bool verdict = mlx5_flow_tunnel_validate(dev, app_tunnel, err_msg); 7860 7861 if (!verdict) 7862 return rte_flow_error_set(error, EINVAL, 7863 RTE_FLOW_ERROR_TYPE_ACTION_CONF, NULL, 7864 err_msg); 7865 ret = mlx5_get_flow_tunnel(dev, app_tunnel, &tunnel); 7866 if (ret < 0) { 7867 return rte_flow_error_set(error, ret, 7868 RTE_FLOW_ERROR_TYPE_ACTION_CONF, NULL, 7869 "failed to initialize pmd tunnel"); 7870 } 7871 *actions = &tunnel->action; 7872 *num_of_actions = 1; 7873 return 0; 7874 } 7875 7876 static int 7877 mlx5_flow_tunnel_match(struct rte_eth_dev *dev, 7878 struct rte_flow_tunnel *app_tunnel, 7879 struct rte_flow_item **items, 7880 uint32_t *num_of_items, 7881 struct rte_flow_error *error) 7882 { 7883 int ret; 7884 struct mlx5_flow_tunnel *tunnel; 7885 const char *err_msg = NULL; 7886 bool verdict = mlx5_flow_tunnel_validate(dev, app_tunnel, err_msg); 7887 7888 if (!verdict) 7889 return rte_flow_error_set(error, EINVAL, 7890 RTE_FLOW_ERROR_TYPE_HANDLE, NULL, 7891 err_msg); 7892 ret = mlx5_get_flow_tunnel(dev, app_tunnel, &tunnel); 7893 if (ret < 0) { 7894 return rte_flow_error_set(error, ret, 7895 RTE_FLOW_ERROR_TYPE_HANDLE, NULL, 7896 "failed to initialize pmd tunnel"); 7897 } 7898 *items = &tunnel->item; 7899 *num_of_items = 1; 7900 return 0; 7901 } 7902 7903 struct tunnel_db_element_release_ctx { 7904 struct rte_flow_item *items; 7905 struct rte_flow_action *actions; 7906 uint32_t num_elements; 7907 struct rte_flow_error *error; 7908 int ret; 7909 }; 7910 7911 static bool 7912 tunnel_element_release_match(struct rte_eth_dev *dev, 7913 struct mlx5_flow_tunnel *tunnel, const void *x) 7914 { 7915 const struct tunnel_db_element_release_ctx *ctx = x; 7916 7917 RTE_SET_USED(dev); 7918 if (ctx->num_elements != 1) 7919 return false; 7920 else if (ctx->items) 7921 return ctx->items == &tunnel->item; 7922 else if (ctx->actions) 7923 return ctx->actions == &tunnel->action; 7924 7925 return false; 7926 } 7927 7928 static void 7929 tunnel_element_release_hit(struct rte_eth_dev *dev, 7930 struct mlx5_flow_tunnel *tunnel, void *x) 7931 { 7932 struct tunnel_db_element_release_ctx *ctx = x; 7933 ctx->ret = 0; 7934 if (!__atomic_sub_fetch(&tunnel->refctn, 1, __ATOMIC_RELAXED)) 7935 mlx5_flow_tunnel_free(dev, tunnel); 7936 } 7937 7938 static void 7939 tunnel_element_release_miss(struct rte_eth_dev *dev, void *x) 7940 { 7941 struct tunnel_db_element_release_ctx *ctx = x; 7942 RTE_SET_USED(dev); 7943 ctx->ret = rte_flow_error_set(ctx->error, EINVAL, 7944 RTE_FLOW_ERROR_TYPE_HANDLE, NULL, 7945 "invalid argument"); 7946 } 7947 7948 static int 7949 mlx5_flow_tunnel_item_release(struct rte_eth_dev *dev, 7950 struct rte_flow_item *pmd_items, 7951 uint32_t num_items, struct rte_flow_error *err) 7952 { 7953 struct tunnel_db_element_release_ctx ctx = { 7954 .items = pmd_items, 7955 .actions = NULL, 7956 .num_elements = num_items, 7957 .error = err, 7958 }; 7959 7960 mlx5_access_tunnel_offload_db(dev, tunnel_element_release_match, 7961 tunnel_element_release_hit, 7962 tunnel_element_release_miss, &ctx, false); 7963 7964 return ctx.ret; 7965 } 7966 7967 static int 7968 mlx5_flow_tunnel_action_release(struct rte_eth_dev *dev, 7969 struct rte_flow_action *pmd_actions, 7970 uint32_t num_actions, struct rte_flow_error *err) 7971 { 7972 struct tunnel_db_element_release_ctx ctx = { 7973 .items = NULL, 7974 .actions = pmd_actions, 7975 .num_elements = num_actions, 7976 .error = err, 7977 }; 7978 7979 mlx5_access_tunnel_offload_db(dev, tunnel_element_release_match, 7980 tunnel_element_release_hit, 7981 tunnel_element_release_miss, &ctx, false); 7982 7983 return ctx.ret; 7984 } 7985 7986 static int 7987 mlx5_flow_tunnel_get_restore_info(struct rte_eth_dev *dev, 7988 struct rte_mbuf *m, 7989 struct rte_flow_restore_info *info, 7990 struct rte_flow_error *err) 7991 { 7992 uint64_t ol_flags = m->ol_flags; 7993 const struct mlx5_flow_tbl_data_entry *tble; 7994 const uint64_t mask = PKT_RX_FDIR | PKT_RX_FDIR_ID; 7995 7996 if (!is_tunnel_offload_active(dev)) { 7997 info->flags = 0; 7998 return 0; 7999 } 8000 8001 if ((ol_flags & mask) != mask) 8002 goto err; 8003 tble = tunnel_mark_decode(dev, m->hash.fdir.hi); 8004 if (!tble) { 8005 DRV_LOG(DEBUG, "port %u invalid miss tunnel mark %#x", 8006 dev->data->port_id, m->hash.fdir.hi); 8007 goto err; 8008 } 8009 MLX5_ASSERT(tble->tunnel); 8010 memcpy(&info->tunnel, &tble->tunnel->app_tunnel, sizeof(info->tunnel)); 8011 info->group_id = tble->group_id; 8012 info->flags = RTE_FLOW_RESTORE_INFO_TUNNEL | 8013 RTE_FLOW_RESTORE_INFO_GROUP_ID | 8014 RTE_FLOW_RESTORE_INFO_ENCAPSULATED; 8015 8016 return 0; 8017 8018 err: 8019 return rte_flow_error_set(err, EINVAL, 8020 RTE_FLOW_ERROR_TYPE_UNSPECIFIED, NULL, 8021 "failed to get restore info"); 8022 } 8023 8024 #else /* HAVE_IBV_FLOW_DV_SUPPORT */ 8025 static int 8026 mlx5_flow_tunnel_decap_set(__rte_unused struct rte_eth_dev *dev, 8027 __rte_unused struct rte_flow_tunnel *app_tunnel, 8028 __rte_unused struct rte_flow_action **actions, 8029 __rte_unused uint32_t *num_of_actions, 8030 __rte_unused struct rte_flow_error *error) 8031 { 8032 return -ENOTSUP; 8033 } 8034 8035 static int 8036 mlx5_flow_tunnel_match(__rte_unused struct rte_eth_dev *dev, 8037 __rte_unused struct rte_flow_tunnel *app_tunnel, 8038 __rte_unused struct rte_flow_item **items, 8039 __rte_unused uint32_t *num_of_items, 8040 __rte_unused struct rte_flow_error *error) 8041 { 8042 return -ENOTSUP; 8043 } 8044 8045 static int 8046 mlx5_flow_tunnel_item_release(__rte_unused struct rte_eth_dev *dev, 8047 __rte_unused struct rte_flow_item *pmd_items, 8048 __rte_unused uint32_t num_items, 8049 __rte_unused struct rte_flow_error *err) 8050 { 8051 return -ENOTSUP; 8052 } 8053 8054 static int 8055 mlx5_flow_tunnel_action_release(__rte_unused struct rte_eth_dev *dev, 8056 __rte_unused struct rte_flow_action *pmd_action, 8057 __rte_unused uint32_t num_actions, 8058 __rte_unused struct rte_flow_error *err) 8059 { 8060 return -ENOTSUP; 8061 } 8062 8063 static int 8064 mlx5_flow_tunnel_get_restore_info(__rte_unused struct rte_eth_dev *dev, 8065 __rte_unused struct rte_mbuf *m, 8066 __rte_unused struct rte_flow_restore_info *i, 8067 __rte_unused struct rte_flow_error *err) 8068 { 8069 return -ENOTSUP; 8070 } 8071 8072 static int 8073 flow_tunnel_add_default_miss(__rte_unused struct rte_eth_dev *dev, 8074 __rte_unused struct rte_flow *flow, 8075 __rte_unused const struct rte_flow_attr *attr, 8076 __rte_unused const struct rte_flow_action *actions, 8077 __rte_unused uint32_t flow_idx, 8078 __rte_unused struct tunnel_default_miss_ctx *ctx, 8079 __rte_unused struct rte_flow_error *error) 8080 { 8081 return -ENOTSUP; 8082 } 8083 8084 static struct mlx5_flow_tunnel * 8085 mlx5_find_tunnel_id(__rte_unused struct rte_eth_dev *dev, 8086 __rte_unused uint32_t id) 8087 { 8088 return NULL; 8089 } 8090 8091 static void 8092 mlx5_flow_tunnel_free(__rte_unused struct rte_eth_dev *dev, 8093 __rte_unused struct mlx5_flow_tunnel *tunnel) 8094 { 8095 } 8096 8097 static uint32_t 8098 tunnel_flow_group_to_flow_table(__rte_unused struct rte_eth_dev *dev, 8099 __rte_unused const struct mlx5_flow_tunnel *t, 8100 __rte_unused uint32_t group, 8101 __rte_unused uint32_t *table, 8102 struct rte_flow_error *error) 8103 { 8104 return rte_flow_error_set(error, ENOTSUP, 8105 RTE_FLOW_ERROR_TYPE_UNSPECIFIED, NULL, 8106 "tunnel offload requires DV support"); 8107 } 8108 8109 void 8110 mlx5_release_tunnel_hub(__rte_unused struct mlx5_dev_ctx_shared *sh, 8111 __rte_unused uint16_t port_id) 8112 { 8113 } 8114 #endif /* HAVE_IBV_FLOW_DV_SUPPORT */ 8115 8116