1 /* SPDX-License-Identifier: BSD-3-Clause 2 * Copyright 2016 6WIND S.A. 3 * Copyright 2016 Mellanox Technologies, Ltd 4 */ 5 6 #include <netinet/in.h> 7 #include <sys/queue.h> 8 #include <stdalign.h> 9 #include <stdint.h> 10 #include <string.h> 11 #include <stdbool.h> 12 13 #include <rte_common.h> 14 #include <rte_ether.h> 15 #include <ethdev_driver.h> 16 #include <rte_eal_paging.h> 17 #include <rte_flow.h> 18 #include <rte_cycles.h> 19 #include <rte_flow_driver.h> 20 #include <rte_malloc.h> 21 #include <rte_ip.h> 22 23 #include <mlx5_glue.h> 24 #include <mlx5_devx_cmds.h> 25 #include <mlx5_prm.h> 26 #include <mlx5_malloc.h> 27 28 #include "mlx5_defs.h" 29 #include "mlx5.h" 30 #include "mlx5_flow.h" 31 #include "mlx5_flow_os.h" 32 #include "mlx5_rxtx.h" 33 #include "mlx5_common_os.h" 34 #include "rte_pmd_mlx5.h" 35 36 struct tunnel_default_miss_ctx { 37 uint16_t *queue; 38 __extension__ 39 union { 40 struct rte_flow_action_rss action_rss; 41 struct rte_flow_action_queue miss_queue; 42 struct rte_flow_action_jump miss_jump; 43 uint8_t raw[0]; 44 }; 45 }; 46 47 static int 48 flow_tunnel_add_default_miss(struct rte_eth_dev *dev, 49 struct rte_flow *flow, 50 const struct rte_flow_attr *attr, 51 const struct rte_flow_action *app_actions, 52 uint32_t flow_idx, 53 struct tunnel_default_miss_ctx *ctx, 54 struct rte_flow_error *error); 55 static struct mlx5_flow_tunnel * 56 mlx5_find_tunnel_id(struct rte_eth_dev *dev, uint32_t id); 57 static void 58 mlx5_flow_tunnel_free(struct rte_eth_dev *dev, struct mlx5_flow_tunnel *tunnel); 59 static uint32_t 60 tunnel_flow_group_to_flow_table(struct rte_eth_dev *dev, 61 const struct mlx5_flow_tunnel *tunnel, 62 uint32_t group, uint32_t *table, 63 struct rte_flow_error *error); 64 65 static struct mlx5_flow_workspace *mlx5_flow_push_thread_workspace(void); 66 static void mlx5_flow_pop_thread_workspace(void); 67 68 69 /** Device flow drivers. */ 70 extern const struct mlx5_flow_driver_ops mlx5_flow_verbs_drv_ops; 71 72 const struct mlx5_flow_driver_ops mlx5_flow_null_drv_ops; 73 74 const struct mlx5_flow_driver_ops *flow_drv_ops[] = { 75 [MLX5_FLOW_TYPE_MIN] = &mlx5_flow_null_drv_ops, 76 #if defined(HAVE_IBV_FLOW_DV_SUPPORT) || !defined(HAVE_INFINIBAND_VERBS_H) 77 [MLX5_FLOW_TYPE_DV] = &mlx5_flow_dv_drv_ops, 78 #endif 79 [MLX5_FLOW_TYPE_VERBS] = &mlx5_flow_verbs_drv_ops, 80 [MLX5_FLOW_TYPE_MAX] = &mlx5_flow_null_drv_ops 81 }; 82 83 /** Helper macro to build input graph for mlx5_flow_expand_rss(). */ 84 #define MLX5_FLOW_EXPAND_RSS_NEXT(...) \ 85 (const int []){ \ 86 __VA_ARGS__, 0, \ 87 } 88 89 /** Node object of input graph for mlx5_flow_expand_rss(). */ 90 struct mlx5_flow_expand_node { 91 const int *const next; 92 /**< 93 * List of next node indexes. Index 0 is interpreted as a terminator. 94 */ 95 const enum rte_flow_item_type type; 96 /**< Pattern item type of current node. */ 97 uint64_t rss_types; 98 /**< 99 * RSS types bit-field associated with this node 100 * (see ETH_RSS_* definitions). 101 */ 102 }; 103 104 /** Object returned by mlx5_flow_expand_rss(). */ 105 struct mlx5_flow_expand_rss { 106 uint32_t entries; 107 /**< Number of entries @p patterns and @p priorities. */ 108 struct { 109 struct rte_flow_item *pattern; /**< Expanded pattern array. */ 110 uint32_t priority; /**< Priority offset for each expansion. */ 111 } entry[]; 112 }; 113 114 static enum rte_flow_item_type 115 mlx5_flow_expand_rss_item_complete(const struct rte_flow_item *item) 116 { 117 enum rte_flow_item_type ret = RTE_FLOW_ITEM_TYPE_VOID; 118 uint16_t ether_type = 0; 119 uint16_t ether_type_m; 120 uint8_t ip_next_proto = 0; 121 uint8_t ip_next_proto_m; 122 123 if (item == NULL || item->spec == NULL) 124 return ret; 125 switch (item->type) { 126 case RTE_FLOW_ITEM_TYPE_ETH: 127 if (item->mask) 128 ether_type_m = ((const struct rte_flow_item_eth *) 129 (item->mask))->type; 130 else 131 ether_type_m = rte_flow_item_eth_mask.type; 132 if (ether_type_m != RTE_BE16(0xFFFF)) 133 break; 134 ether_type = ((const struct rte_flow_item_eth *) 135 (item->spec))->type; 136 if (rte_be_to_cpu_16(ether_type) == RTE_ETHER_TYPE_IPV4) 137 ret = RTE_FLOW_ITEM_TYPE_IPV4; 138 else if (rte_be_to_cpu_16(ether_type) == RTE_ETHER_TYPE_IPV6) 139 ret = RTE_FLOW_ITEM_TYPE_IPV6; 140 else if (rte_be_to_cpu_16(ether_type) == RTE_ETHER_TYPE_VLAN) 141 ret = RTE_FLOW_ITEM_TYPE_VLAN; 142 else 143 ret = RTE_FLOW_ITEM_TYPE_END; 144 break; 145 case RTE_FLOW_ITEM_TYPE_VLAN: 146 if (item->mask) 147 ether_type_m = ((const struct rte_flow_item_vlan *) 148 (item->mask))->inner_type; 149 else 150 ether_type_m = rte_flow_item_vlan_mask.inner_type; 151 if (ether_type_m != RTE_BE16(0xFFFF)) 152 break; 153 ether_type = ((const struct rte_flow_item_vlan *) 154 (item->spec))->inner_type; 155 if (rte_be_to_cpu_16(ether_type) == RTE_ETHER_TYPE_IPV4) 156 ret = RTE_FLOW_ITEM_TYPE_IPV4; 157 else if (rte_be_to_cpu_16(ether_type) == RTE_ETHER_TYPE_IPV6) 158 ret = RTE_FLOW_ITEM_TYPE_IPV6; 159 else if (rte_be_to_cpu_16(ether_type) == RTE_ETHER_TYPE_VLAN) 160 ret = RTE_FLOW_ITEM_TYPE_VLAN; 161 else 162 ret = RTE_FLOW_ITEM_TYPE_END; 163 break; 164 case RTE_FLOW_ITEM_TYPE_IPV4: 165 if (item->mask) 166 ip_next_proto_m = ((const struct rte_flow_item_ipv4 *) 167 (item->mask))->hdr.next_proto_id; 168 else 169 ip_next_proto_m = 170 rte_flow_item_ipv4_mask.hdr.next_proto_id; 171 if (ip_next_proto_m != 0xFF) 172 break; 173 ip_next_proto = ((const struct rte_flow_item_ipv4 *) 174 (item->spec))->hdr.next_proto_id; 175 if (ip_next_proto == IPPROTO_UDP) 176 ret = RTE_FLOW_ITEM_TYPE_UDP; 177 else if (ip_next_proto == IPPROTO_TCP) 178 ret = RTE_FLOW_ITEM_TYPE_TCP; 179 else if (ip_next_proto == IPPROTO_IP) 180 ret = RTE_FLOW_ITEM_TYPE_IPV4; 181 else if (ip_next_proto == IPPROTO_IPV6) 182 ret = RTE_FLOW_ITEM_TYPE_IPV6; 183 else 184 ret = RTE_FLOW_ITEM_TYPE_END; 185 break; 186 case RTE_FLOW_ITEM_TYPE_IPV6: 187 if (item->mask) 188 ip_next_proto_m = ((const struct rte_flow_item_ipv6 *) 189 (item->mask))->hdr.proto; 190 else 191 ip_next_proto_m = 192 rte_flow_item_ipv6_mask.hdr.proto; 193 if (ip_next_proto_m != 0xFF) 194 break; 195 ip_next_proto = ((const struct rte_flow_item_ipv6 *) 196 (item->spec))->hdr.proto; 197 if (ip_next_proto == IPPROTO_UDP) 198 ret = RTE_FLOW_ITEM_TYPE_UDP; 199 else if (ip_next_proto == IPPROTO_TCP) 200 ret = RTE_FLOW_ITEM_TYPE_TCP; 201 else if (ip_next_proto == IPPROTO_IP) 202 ret = RTE_FLOW_ITEM_TYPE_IPV4; 203 else if (ip_next_proto == IPPROTO_IPV6) 204 ret = RTE_FLOW_ITEM_TYPE_IPV6; 205 else 206 ret = RTE_FLOW_ITEM_TYPE_END; 207 break; 208 default: 209 ret = RTE_FLOW_ITEM_TYPE_VOID; 210 break; 211 } 212 return ret; 213 } 214 215 #define MLX5_RSS_EXP_ELT_N 8 216 217 /** 218 * Expand RSS flows into several possible flows according to the RSS hash 219 * fields requested and the driver capabilities. 220 * 221 * @param[out] buf 222 * Buffer to store the result expansion. 223 * @param[in] size 224 * Buffer size in bytes. If 0, @p buf can be NULL. 225 * @param[in] pattern 226 * User flow pattern. 227 * @param[in] types 228 * RSS types to expand (see ETH_RSS_* definitions). 229 * @param[in] graph 230 * Input graph to expand @p pattern according to @p types. 231 * @param[in] graph_root_index 232 * Index of root node in @p graph, typically 0. 233 * 234 * @return 235 * A positive value representing the size of @p buf in bytes regardless of 236 * @p size on success, a negative errno value otherwise and rte_errno is 237 * set, the following errors are defined: 238 * 239 * -E2BIG: graph-depth @p graph is too deep. 240 */ 241 static int 242 mlx5_flow_expand_rss(struct mlx5_flow_expand_rss *buf, size_t size, 243 const struct rte_flow_item *pattern, uint64_t types, 244 const struct mlx5_flow_expand_node graph[], 245 int graph_root_index) 246 { 247 const struct rte_flow_item *item; 248 const struct mlx5_flow_expand_node *node = &graph[graph_root_index]; 249 const int *next_node; 250 const int *stack[MLX5_RSS_EXP_ELT_N]; 251 int stack_pos = 0; 252 struct rte_flow_item flow_items[MLX5_RSS_EXP_ELT_N]; 253 unsigned int i; 254 size_t lsize; 255 size_t user_pattern_size = 0; 256 void *addr = NULL; 257 const struct mlx5_flow_expand_node *next = NULL; 258 struct rte_flow_item missed_item; 259 int missed = 0; 260 int elt = 0; 261 const struct rte_flow_item *last_item = NULL; 262 263 memset(&missed_item, 0, sizeof(missed_item)); 264 lsize = offsetof(struct mlx5_flow_expand_rss, entry) + 265 MLX5_RSS_EXP_ELT_N * sizeof(buf->entry[0]); 266 if (lsize <= size) { 267 buf->entry[0].priority = 0; 268 buf->entry[0].pattern = (void *)&buf->entry[MLX5_RSS_EXP_ELT_N]; 269 buf->entries = 0; 270 addr = buf->entry[0].pattern; 271 } 272 for (item = pattern; item->type != RTE_FLOW_ITEM_TYPE_END; item++) { 273 if (item->type != RTE_FLOW_ITEM_TYPE_VOID) 274 last_item = item; 275 for (i = 0; node->next && node->next[i]; ++i) { 276 next = &graph[node->next[i]]; 277 if (next->type == item->type) 278 break; 279 } 280 if (next) 281 node = next; 282 user_pattern_size += sizeof(*item); 283 } 284 user_pattern_size += sizeof(*item); /* Handle END item. */ 285 lsize += user_pattern_size; 286 /* Copy the user pattern in the first entry of the buffer. */ 287 if (lsize <= size) { 288 rte_memcpy(addr, pattern, user_pattern_size); 289 addr = (void *)(((uintptr_t)addr) + user_pattern_size); 290 buf->entries = 1; 291 } 292 /* Start expanding. */ 293 memset(flow_items, 0, sizeof(flow_items)); 294 user_pattern_size -= sizeof(*item); 295 /* 296 * Check if the last valid item has spec set, need complete pattern, 297 * and the pattern can be used for expansion. 298 */ 299 missed_item.type = mlx5_flow_expand_rss_item_complete(last_item); 300 if (missed_item.type == RTE_FLOW_ITEM_TYPE_END) { 301 /* Item type END indicates expansion is not required. */ 302 return lsize; 303 } 304 if (missed_item.type != RTE_FLOW_ITEM_TYPE_VOID) { 305 next = NULL; 306 missed = 1; 307 for (i = 0; node->next && node->next[i]; ++i) { 308 next = &graph[node->next[i]]; 309 if (next->type == missed_item.type) { 310 flow_items[0].type = missed_item.type; 311 flow_items[1].type = RTE_FLOW_ITEM_TYPE_END; 312 break; 313 } 314 next = NULL; 315 } 316 } 317 if (next && missed) { 318 elt = 2; /* missed item + item end. */ 319 node = next; 320 lsize += elt * sizeof(*item) + user_pattern_size; 321 if ((node->rss_types & types) && lsize <= size) { 322 buf->entry[buf->entries].priority = 1; 323 buf->entry[buf->entries].pattern = addr; 324 buf->entries++; 325 rte_memcpy(addr, buf->entry[0].pattern, 326 user_pattern_size); 327 addr = (void *)(((uintptr_t)addr) + user_pattern_size); 328 rte_memcpy(addr, flow_items, elt * sizeof(*item)); 329 addr = (void *)(((uintptr_t)addr) + 330 elt * sizeof(*item)); 331 } 332 } 333 memset(flow_items, 0, sizeof(flow_items)); 334 next_node = node->next; 335 stack[stack_pos] = next_node; 336 node = next_node ? &graph[*next_node] : NULL; 337 while (node) { 338 flow_items[stack_pos].type = node->type; 339 if (node->rss_types & types) { 340 /* 341 * compute the number of items to copy from the 342 * expansion and copy it. 343 * When the stack_pos is 0, there are 1 element in it, 344 * plus the addition END item. 345 */ 346 elt = stack_pos + 2; 347 flow_items[stack_pos + 1].type = RTE_FLOW_ITEM_TYPE_END; 348 lsize += elt * sizeof(*item) + user_pattern_size; 349 if (lsize <= size) { 350 size_t n = elt * sizeof(*item); 351 352 buf->entry[buf->entries].priority = 353 stack_pos + 1 + missed; 354 buf->entry[buf->entries].pattern = addr; 355 buf->entries++; 356 rte_memcpy(addr, buf->entry[0].pattern, 357 user_pattern_size); 358 addr = (void *)(((uintptr_t)addr) + 359 user_pattern_size); 360 rte_memcpy(addr, &missed_item, 361 missed * sizeof(*item)); 362 addr = (void *)(((uintptr_t)addr) + 363 missed * sizeof(*item)); 364 rte_memcpy(addr, flow_items, n); 365 addr = (void *)(((uintptr_t)addr) + n); 366 } 367 } 368 /* Go deeper. */ 369 if (node->next) { 370 next_node = node->next; 371 if (stack_pos++ == MLX5_RSS_EXP_ELT_N) { 372 rte_errno = E2BIG; 373 return -rte_errno; 374 } 375 stack[stack_pos] = next_node; 376 } else if (*(next_node + 1)) { 377 /* Follow up with the next possibility. */ 378 ++next_node; 379 } else { 380 /* Move to the next path. */ 381 if (stack_pos) 382 next_node = stack[--stack_pos]; 383 next_node++; 384 stack[stack_pos] = next_node; 385 } 386 node = *next_node ? &graph[*next_node] : NULL; 387 }; 388 /* no expanded flows but we have missed item, create one rule for it */ 389 if (buf->entries == 1 && missed != 0) { 390 elt = 2; 391 lsize += elt * sizeof(*item) + user_pattern_size; 392 if (lsize <= size) { 393 buf->entry[buf->entries].priority = 1; 394 buf->entry[buf->entries].pattern = addr; 395 buf->entries++; 396 flow_items[0].type = missed_item.type; 397 flow_items[1].type = RTE_FLOW_ITEM_TYPE_END; 398 rte_memcpy(addr, buf->entry[0].pattern, 399 user_pattern_size); 400 addr = (void *)(((uintptr_t)addr) + user_pattern_size); 401 rte_memcpy(addr, flow_items, elt * sizeof(*item)); 402 } 403 } 404 return lsize; 405 } 406 407 enum mlx5_expansion { 408 MLX5_EXPANSION_ROOT, 409 MLX5_EXPANSION_ROOT_OUTER, 410 MLX5_EXPANSION_ROOT_ETH_VLAN, 411 MLX5_EXPANSION_ROOT_OUTER_ETH_VLAN, 412 MLX5_EXPANSION_OUTER_ETH, 413 MLX5_EXPANSION_OUTER_ETH_VLAN, 414 MLX5_EXPANSION_OUTER_VLAN, 415 MLX5_EXPANSION_OUTER_IPV4, 416 MLX5_EXPANSION_OUTER_IPV4_UDP, 417 MLX5_EXPANSION_OUTER_IPV4_TCP, 418 MLX5_EXPANSION_OUTER_IPV6, 419 MLX5_EXPANSION_OUTER_IPV6_UDP, 420 MLX5_EXPANSION_OUTER_IPV6_TCP, 421 MLX5_EXPANSION_VXLAN, 422 MLX5_EXPANSION_VXLAN_GPE, 423 MLX5_EXPANSION_GRE, 424 MLX5_EXPANSION_MPLS, 425 MLX5_EXPANSION_ETH, 426 MLX5_EXPANSION_ETH_VLAN, 427 MLX5_EXPANSION_VLAN, 428 MLX5_EXPANSION_IPV4, 429 MLX5_EXPANSION_IPV4_UDP, 430 MLX5_EXPANSION_IPV4_TCP, 431 MLX5_EXPANSION_IPV6, 432 MLX5_EXPANSION_IPV6_UDP, 433 MLX5_EXPANSION_IPV6_TCP, 434 }; 435 436 /** Supported expansion of items. */ 437 static const struct mlx5_flow_expand_node mlx5_support_expansion[] = { 438 [MLX5_EXPANSION_ROOT] = { 439 .next = MLX5_FLOW_EXPAND_RSS_NEXT(MLX5_EXPANSION_ETH, 440 MLX5_EXPANSION_IPV4, 441 MLX5_EXPANSION_IPV6), 442 .type = RTE_FLOW_ITEM_TYPE_END, 443 }, 444 [MLX5_EXPANSION_ROOT_OUTER] = { 445 .next = MLX5_FLOW_EXPAND_RSS_NEXT(MLX5_EXPANSION_OUTER_ETH, 446 MLX5_EXPANSION_OUTER_IPV4, 447 MLX5_EXPANSION_OUTER_IPV6), 448 .type = RTE_FLOW_ITEM_TYPE_END, 449 }, 450 [MLX5_EXPANSION_ROOT_ETH_VLAN] = { 451 .next = MLX5_FLOW_EXPAND_RSS_NEXT(MLX5_EXPANSION_ETH_VLAN), 452 .type = RTE_FLOW_ITEM_TYPE_END, 453 }, 454 [MLX5_EXPANSION_ROOT_OUTER_ETH_VLAN] = { 455 .next = MLX5_FLOW_EXPAND_RSS_NEXT 456 (MLX5_EXPANSION_OUTER_ETH_VLAN), 457 .type = RTE_FLOW_ITEM_TYPE_END, 458 }, 459 [MLX5_EXPANSION_OUTER_ETH] = { 460 .next = MLX5_FLOW_EXPAND_RSS_NEXT(MLX5_EXPANSION_OUTER_IPV4, 461 MLX5_EXPANSION_OUTER_IPV6, 462 MLX5_EXPANSION_MPLS), 463 .type = RTE_FLOW_ITEM_TYPE_ETH, 464 .rss_types = 0, 465 }, 466 [MLX5_EXPANSION_OUTER_ETH_VLAN] = { 467 .next = MLX5_FLOW_EXPAND_RSS_NEXT(MLX5_EXPANSION_OUTER_VLAN), 468 .type = RTE_FLOW_ITEM_TYPE_ETH, 469 .rss_types = 0, 470 }, 471 [MLX5_EXPANSION_OUTER_VLAN] = { 472 .next = MLX5_FLOW_EXPAND_RSS_NEXT(MLX5_EXPANSION_OUTER_IPV4, 473 MLX5_EXPANSION_OUTER_IPV6), 474 .type = RTE_FLOW_ITEM_TYPE_VLAN, 475 }, 476 [MLX5_EXPANSION_OUTER_IPV4] = { 477 .next = MLX5_FLOW_EXPAND_RSS_NEXT 478 (MLX5_EXPANSION_OUTER_IPV4_UDP, 479 MLX5_EXPANSION_OUTER_IPV4_TCP, 480 MLX5_EXPANSION_GRE, 481 MLX5_EXPANSION_IPV4, 482 MLX5_EXPANSION_IPV6), 483 .type = RTE_FLOW_ITEM_TYPE_IPV4, 484 .rss_types = ETH_RSS_IPV4 | ETH_RSS_FRAG_IPV4 | 485 ETH_RSS_NONFRAG_IPV4_OTHER, 486 }, 487 [MLX5_EXPANSION_OUTER_IPV4_UDP] = { 488 .next = MLX5_FLOW_EXPAND_RSS_NEXT(MLX5_EXPANSION_VXLAN, 489 MLX5_EXPANSION_VXLAN_GPE), 490 .type = RTE_FLOW_ITEM_TYPE_UDP, 491 .rss_types = ETH_RSS_NONFRAG_IPV4_UDP, 492 }, 493 [MLX5_EXPANSION_OUTER_IPV4_TCP] = { 494 .type = RTE_FLOW_ITEM_TYPE_TCP, 495 .rss_types = ETH_RSS_NONFRAG_IPV4_TCP, 496 }, 497 [MLX5_EXPANSION_OUTER_IPV6] = { 498 .next = MLX5_FLOW_EXPAND_RSS_NEXT 499 (MLX5_EXPANSION_OUTER_IPV6_UDP, 500 MLX5_EXPANSION_OUTER_IPV6_TCP, 501 MLX5_EXPANSION_IPV4, 502 MLX5_EXPANSION_IPV6, 503 MLX5_EXPANSION_GRE), 504 .type = RTE_FLOW_ITEM_TYPE_IPV6, 505 .rss_types = ETH_RSS_IPV6 | ETH_RSS_FRAG_IPV6 | 506 ETH_RSS_NONFRAG_IPV6_OTHER, 507 }, 508 [MLX5_EXPANSION_OUTER_IPV6_UDP] = { 509 .next = MLX5_FLOW_EXPAND_RSS_NEXT(MLX5_EXPANSION_VXLAN, 510 MLX5_EXPANSION_VXLAN_GPE), 511 .type = RTE_FLOW_ITEM_TYPE_UDP, 512 .rss_types = ETH_RSS_NONFRAG_IPV6_UDP, 513 }, 514 [MLX5_EXPANSION_OUTER_IPV6_TCP] = { 515 .type = RTE_FLOW_ITEM_TYPE_TCP, 516 .rss_types = ETH_RSS_NONFRAG_IPV6_TCP, 517 }, 518 [MLX5_EXPANSION_VXLAN] = { 519 .next = MLX5_FLOW_EXPAND_RSS_NEXT(MLX5_EXPANSION_ETH, 520 MLX5_EXPANSION_IPV4, 521 MLX5_EXPANSION_IPV6), 522 .type = RTE_FLOW_ITEM_TYPE_VXLAN, 523 }, 524 [MLX5_EXPANSION_VXLAN_GPE] = { 525 .next = MLX5_FLOW_EXPAND_RSS_NEXT(MLX5_EXPANSION_ETH, 526 MLX5_EXPANSION_IPV4, 527 MLX5_EXPANSION_IPV6), 528 .type = RTE_FLOW_ITEM_TYPE_VXLAN_GPE, 529 }, 530 [MLX5_EXPANSION_GRE] = { 531 .next = MLX5_FLOW_EXPAND_RSS_NEXT(MLX5_EXPANSION_IPV4, 532 MLX5_EXPANSION_IPV6), 533 .type = RTE_FLOW_ITEM_TYPE_GRE, 534 }, 535 [MLX5_EXPANSION_MPLS] = { 536 .next = MLX5_FLOW_EXPAND_RSS_NEXT(MLX5_EXPANSION_IPV4, 537 MLX5_EXPANSION_IPV6), 538 .type = RTE_FLOW_ITEM_TYPE_MPLS, 539 }, 540 [MLX5_EXPANSION_ETH] = { 541 .next = MLX5_FLOW_EXPAND_RSS_NEXT(MLX5_EXPANSION_IPV4, 542 MLX5_EXPANSION_IPV6), 543 .type = RTE_FLOW_ITEM_TYPE_ETH, 544 }, 545 [MLX5_EXPANSION_ETH_VLAN] = { 546 .next = MLX5_FLOW_EXPAND_RSS_NEXT(MLX5_EXPANSION_VLAN), 547 .type = RTE_FLOW_ITEM_TYPE_ETH, 548 }, 549 [MLX5_EXPANSION_VLAN] = { 550 .next = MLX5_FLOW_EXPAND_RSS_NEXT(MLX5_EXPANSION_IPV4, 551 MLX5_EXPANSION_IPV6), 552 .type = RTE_FLOW_ITEM_TYPE_VLAN, 553 }, 554 [MLX5_EXPANSION_IPV4] = { 555 .next = MLX5_FLOW_EXPAND_RSS_NEXT(MLX5_EXPANSION_IPV4_UDP, 556 MLX5_EXPANSION_IPV4_TCP), 557 .type = RTE_FLOW_ITEM_TYPE_IPV4, 558 .rss_types = ETH_RSS_IPV4 | ETH_RSS_FRAG_IPV4 | 559 ETH_RSS_NONFRAG_IPV4_OTHER, 560 }, 561 [MLX5_EXPANSION_IPV4_UDP] = { 562 .type = RTE_FLOW_ITEM_TYPE_UDP, 563 .rss_types = ETH_RSS_NONFRAG_IPV4_UDP, 564 }, 565 [MLX5_EXPANSION_IPV4_TCP] = { 566 .type = RTE_FLOW_ITEM_TYPE_TCP, 567 .rss_types = ETH_RSS_NONFRAG_IPV4_TCP, 568 }, 569 [MLX5_EXPANSION_IPV6] = { 570 .next = MLX5_FLOW_EXPAND_RSS_NEXT(MLX5_EXPANSION_IPV6_UDP, 571 MLX5_EXPANSION_IPV6_TCP), 572 .type = RTE_FLOW_ITEM_TYPE_IPV6, 573 .rss_types = ETH_RSS_IPV6 | ETH_RSS_FRAG_IPV6 | 574 ETH_RSS_NONFRAG_IPV6_OTHER, 575 }, 576 [MLX5_EXPANSION_IPV6_UDP] = { 577 .type = RTE_FLOW_ITEM_TYPE_UDP, 578 .rss_types = ETH_RSS_NONFRAG_IPV6_UDP, 579 }, 580 [MLX5_EXPANSION_IPV6_TCP] = { 581 .type = RTE_FLOW_ITEM_TYPE_TCP, 582 .rss_types = ETH_RSS_NONFRAG_IPV6_TCP, 583 }, 584 }; 585 586 static struct rte_flow_shared_action * 587 mlx5_shared_action_create(struct rte_eth_dev *dev, 588 const struct rte_flow_shared_action_conf *conf, 589 const struct rte_flow_action *action, 590 struct rte_flow_error *error); 591 static int mlx5_shared_action_destroy 592 (struct rte_eth_dev *dev, 593 struct rte_flow_shared_action *shared_action, 594 struct rte_flow_error *error); 595 static int mlx5_shared_action_update 596 (struct rte_eth_dev *dev, 597 struct rte_flow_shared_action *shared_action, 598 const struct rte_flow_action *action, 599 struct rte_flow_error *error); 600 static int mlx5_shared_action_query 601 (struct rte_eth_dev *dev, 602 const struct rte_flow_shared_action *action, 603 void *data, 604 struct rte_flow_error *error); 605 static int 606 mlx5_flow_tunnel_decap_set(struct rte_eth_dev *dev, 607 struct rte_flow_tunnel *app_tunnel, 608 struct rte_flow_action **actions, 609 uint32_t *num_of_actions, 610 struct rte_flow_error *error); 611 static int 612 mlx5_flow_tunnel_match(struct rte_eth_dev *dev, 613 struct rte_flow_tunnel *app_tunnel, 614 struct rte_flow_item **items, 615 uint32_t *num_of_items, 616 struct rte_flow_error *error); 617 static int 618 mlx5_flow_tunnel_item_release(struct rte_eth_dev *dev, 619 struct rte_flow_item *pmd_items, 620 uint32_t num_items, struct rte_flow_error *err); 621 static int 622 mlx5_flow_tunnel_action_release(struct rte_eth_dev *dev, 623 struct rte_flow_action *pmd_actions, 624 uint32_t num_actions, 625 struct rte_flow_error *err); 626 static int 627 mlx5_flow_tunnel_get_restore_info(struct rte_eth_dev *dev, 628 struct rte_mbuf *m, 629 struct rte_flow_restore_info *info, 630 struct rte_flow_error *err); 631 632 static const struct rte_flow_ops mlx5_flow_ops = { 633 .validate = mlx5_flow_validate, 634 .create = mlx5_flow_create, 635 .destroy = mlx5_flow_destroy, 636 .flush = mlx5_flow_flush, 637 .isolate = mlx5_flow_isolate, 638 .query = mlx5_flow_query, 639 .dev_dump = mlx5_flow_dev_dump, 640 .get_aged_flows = mlx5_flow_get_aged_flows, 641 .shared_action_create = mlx5_shared_action_create, 642 .shared_action_destroy = mlx5_shared_action_destroy, 643 .shared_action_update = mlx5_shared_action_update, 644 .shared_action_query = mlx5_shared_action_query, 645 .tunnel_decap_set = mlx5_flow_tunnel_decap_set, 646 .tunnel_match = mlx5_flow_tunnel_match, 647 .tunnel_action_decap_release = mlx5_flow_tunnel_action_release, 648 .tunnel_item_release = mlx5_flow_tunnel_item_release, 649 .get_restore_info = mlx5_flow_tunnel_get_restore_info, 650 }; 651 652 /* Tunnel information. */ 653 struct mlx5_flow_tunnel_info { 654 uint64_t tunnel; /**< Tunnel bit (see MLX5_FLOW_*). */ 655 uint32_t ptype; /**< Tunnel Ptype (see RTE_PTYPE_*). */ 656 }; 657 658 static struct mlx5_flow_tunnel_info tunnels_info[] = { 659 { 660 .tunnel = MLX5_FLOW_LAYER_VXLAN, 661 .ptype = RTE_PTYPE_TUNNEL_VXLAN | RTE_PTYPE_L4_UDP, 662 }, 663 { 664 .tunnel = MLX5_FLOW_LAYER_GENEVE, 665 .ptype = RTE_PTYPE_TUNNEL_GENEVE | RTE_PTYPE_L4_UDP, 666 }, 667 { 668 .tunnel = MLX5_FLOW_LAYER_VXLAN_GPE, 669 .ptype = RTE_PTYPE_TUNNEL_VXLAN_GPE | RTE_PTYPE_L4_UDP, 670 }, 671 { 672 .tunnel = MLX5_FLOW_LAYER_GRE, 673 .ptype = RTE_PTYPE_TUNNEL_GRE, 674 }, 675 { 676 .tunnel = MLX5_FLOW_LAYER_MPLS | MLX5_FLOW_LAYER_OUTER_L4_UDP, 677 .ptype = RTE_PTYPE_TUNNEL_MPLS_IN_UDP | RTE_PTYPE_L4_UDP, 678 }, 679 { 680 .tunnel = MLX5_FLOW_LAYER_MPLS, 681 .ptype = RTE_PTYPE_TUNNEL_MPLS_IN_GRE, 682 }, 683 { 684 .tunnel = MLX5_FLOW_LAYER_NVGRE, 685 .ptype = RTE_PTYPE_TUNNEL_NVGRE, 686 }, 687 { 688 .tunnel = MLX5_FLOW_LAYER_IPIP, 689 .ptype = RTE_PTYPE_TUNNEL_IP, 690 }, 691 { 692 .tunnel = MLX5_FLOW_LAYER_IPV6_ENCAP, 693 .ptype = RTE_PTYPE_TUNNEL_IP, 694 }, 695 { 696 .tunnel = MLX5_FLOW_LAYER_GTP, 697 .ptype = RTE_PTYPE_TUNNEL_GTPU, 698 }, 699 }; 700 701 702 703 /** 704 * Translate tag ID to register. 705 * 706 * @param[in] dev 707 * Pointer to the Ethernet device structure. 708 * @param[in] feature 709 * The feature that request the register. 710 * @param[in] id 711 * The request register ID. 712 * @param[out] error 713 * Error description in case of any. 714 * 715 * @return 716 * The request register on success, a negative errno 717 * value otherwise and rte_errno is set. 718 */ 719 int 720 mlx5_flow_get_reg_id(struct rte_eth_dev *dev, 721 enum mlx5_feature_name feature, 722 uint32_t id, 723 struct rte_flow_error *error) 724 { 725 struct mlx5_priv *priv = dev->data->dev_private; 726 struct mlx5_dev_config *config = &priv->config; 727 enum modify_reg start_reg; 728 bool skip_mtr_reg = false; 729 730 switch (feature) { 731 case MLX5_HAIRPIN_RX: 732 return REG_B; 733 case MLX5_HAIRPIN_TX: 734 return REG_A; 735 case MLX5_METADATA_RX: 736 switch (config->dv_xmeta_en) { 737 case MLX5_XMETA_MODE_LEGACY: 738 return REG_B; 739 case MLX5_XMETA_MODE_META16: 740 return REG_C_0; 741 case MLX5_XMETA_MODE_META32: 742 return REG_C_1; 743 } 744 break; 745 case MLX5_METADATA_TX: 746 return REG_A; 747 case MLX5_METADATA_FDB: 748 switch (config->dv_xmeta_en) { 749 case MLX5_XMETA_MODE_LEGACY: 750 return REG_NON; 751 case MLX5_XMETA_MODE_META16: 752 return REG_C_0; 753 case MLX5_XMETA_MODE_META32: 754 return REG_C_1; 755 } 756 break; 757 case MLX5_FLOW_MARK: 758 switch (config->dv_xmeta_en) { 759 case MLX5_XMETA_MODE_LEGACY: 760 return REG_NON; 761 case MLX5_XMETA_MODE_META16: 762 return REG_C_1; 763 case MLX5_XMETA_MODE_META32: 764 return REG_C_0; 765 } 766 break; 767 case MLX5_MTR_SFX: 768 /* 769 * If meter color and flow match share one register, flow match 770 * should use the meter color register for match. 771 */ 772 if (priv->mtr_reg_share) 773 return priv->mtr_color_reg; 774 else 775 return priv->mtr_color_reg != REG_C_2 ? REG_C_2 : 776 REG_C_3; 777 case MLX5_MTR_COLOR: 778 case MLX5_ASO_FLOW_HIT: /* Both features use the same REG_C. */ 779 MLX5_ASSERT(priv->mtr_color_reg != REG_NON); 780 return priv->mtr_color_reg; 781 case MLX5_COPY_MARK: 782 /* 783 * Metadata COPY_MARK register using is in meter suffix sub 784 * flow while with meter. It's safe to share the same register. 785 */ 786 return priv->mtr_color_reg != REG_C_2 ? REG_C_2 : REG_C_3; 787 case MLX5_APP_TAG: 788 /* 789 * If meter is enable, it will engage the register for color 790 * match and flow match. If meter color match is not using the 791 * REG_C_2, need to skip the REG_C_x be used by meter color 792 * match. 793 * If meter is disable, free to use all available registers. 794 */ 795 start_reg = priv->mtr_color_reg != REG_C_2 ? REG_C_2 : 796 (priv->mtr_reg_share ? REG_C_3 : REG_C_4); 797 skip_mtr_reg = !!(priv->mtr_en && start_reg == REG_C_2); 798 if (id > (uint32_t)(REG_C_7 - start_reg)) 799 return rte_flow_error_set(error, EINVAL, 800 RTE_FLOW_ERROR_TYPE_ITEM, 801 NULL, "invalid tag id"); 802 if (config->flow_mreg_c[id + start_reg - REG_C_0] == REG_NON) 803 return rte_flow_error_set(error, ENOTSUP, 804 RTE_FLOW_ERROR_TYPE_ITEM, 805 NULL, "unsupported tag id"); 806 /* 807 * This case means meter is using the REG_C_x great than 2. 808 * Take care not to conflict with meter color REG_C_x. 809 * If the available index REG_C_y >= REG_C_x, skip the 810 * color register. 811 */ 812 if (skip_mtr_reg && config->flow_mreg_c 813 [id + start_reg - REG_C_0] >= priv->mtr_color_reg) { 814 if (id >= (uint32_t)(REG_C_7 - start_reg)) 815 return rte_flow_error_set(error, EINVAL, 816 RTE_FLOW_ERROR_TYPE_ITEM, 817 NULL, "invalid tag id"); 818 if (config->flow_mreg_c 819 [id + 1 + start_reg - REG_C_0] != REG_NON) 820 return config->flow_mreg_c 821 [id + 1 + start_reg - REG_C_0]; 822 return rte_flow_error_set(error, ENOTSUP, 823 RTE_FLOW_ERROR_TYPE_ITEM, 824 NULL, "unsupported tag id"); 825 } 826 return config->flow_mreg_c[id + start_reg - REG_C_0]; 827 } 828 MLX5_ASSERT(false); 829 return rte_flow_error_set(error, EINVAL, 830 RTE_FLOW_ERROR_TYPE_UNSPECIFIED, 831 NULL, "invalid feature name"); 832 } 833 834 /** 835 * Check extensive flow metadata register support. 836 * 837 * @param dev 838 * Pointer to rte_eth_dev structure. 839 * 840 * @return 841 * True if device supports extensive flow metadata register, otherwise false. 842 */ 843 bool 844 mlx5_flow_ext_mreg_supported(struct rte_eth_dev *dev) 845 { 846 struct mlx5_priv *priv = dev->data->dev_private; 847 struct mlx5_dev_config *config = &priv->config; 848 849 /* 850 * Having available reg_c can be regarded inclusively as supporting 851 * extensive flow metadata register, which could mean, 852 * - metadata register copy action by modify header. 853 * - 16 modify header actions is supported. 854 * - reg_c's are preserved across different domain (FDB and NIC) on 855 * packet loopback by flow lookup miss. 856 */ 857 return config->flow_mreg_c[2] != REG_NON; 858 } 859 860 /** 861 * Get the lowest priority. 862 * 863 * @param[in] dev 864 * Pointer to the Ethernet device structure. 865 * @param[in] attributes 866 * Pointer to device flow rule attributes. 867 * 868 * @return 869 * The value of lowest priority of flow. 870 */ 871 uint32_t 872 mlx5_get_lowest_priority(struct rte_eth_dev *dev, 873 const struct rte_flow_attr *attr) 874 { 875 struct mlx5_priv *priv = dev->data->dev_private; 876 877 if (!attr->group && !attr->transfer) 878 return priv->config.flow_prio - 2; 879 return MLX5_NON_ROOT_FLOW_MAX_PRIO - 1; 880 } 881 882 /** 883 * Calculate matcher priority of the flow. 884 * 885 * @param[in] dev 886 * Pointer to the Ethernet device structure. 887 * @param[in] attr 888 * Pointer to device flow rule attributes. 889 * @param[in] subpriority 890 * The priority based on the items. 891 * @return 892 * The matcher priority of the flow. 893 */ 894 uint16_t 895 mlx5_get_matcher_priority(struct rte_eth_dev *dev, 896 const struct rte_flow_attr *attr, 897 uint32_t subpriority) 898 { 899 uint16_t priority = (uint16_t)attr->priority; 900 struct mlx5_priv *priv = dev->data->dev_private; 901 902 if (!attr->group && !attr->transfer) { 903 if (attr->priority == MLX5_FLOW_LOWEST_PRIO_INDICATOR) 904 priority = priv->config.flow_prio - 1; 905 return mlx5_os_flow_adjust_priority(dev, priority, subpriority); 906 } 907 if (attr->priority == MLX5_FLOW_LOWEST_PRIO_INDICATOR) 908 priority = MLX5_NON_ROOT_FLOW_MAX_PRIO; 909 return priority * 3 + subpriority; 910 } 911 912 /** 913 * Verify the @p item specifications (spec, last, mask) are compatible with the 914 * NIC capabilities. 915 * 916 * @param[in] item 917 * Item specification. 918 * @param[in] mask 919 * @p item->mask or flow default bit-masks. 920 * @param[in] nic_mask 921 * Bit-masks covering supported fields by the NIC to compare with user mask. 922 * @param[in] size 923 * Bit-masks size in bytes. 924 * @param[in] range_accepted 925 * True if range of values is accepted for specific fields, false otherwise. 926 * @param[out] error 927 * Pointer to error structure. 928 * 929 * @return 930 * 0 on success, a negative errno value otherwise and rte_errno is set. 931 */ 932 int 933 mlx5_flow_item_acceptable(const struct rte_flow_item *item, 934 const uint8_t *mask, 935 const uint8_t *nic_mask, 936 unsigned int size, 937 bool range_accepted, 938 struct rte_flow_error *error) 939 { 940 unsigned int i; 941 942 MLX5_ASSERT(nic_mask); 943 for (i = 0; i < size; ++i) 944 if ((nic_mask[i] | mask[i]) != nic_mask[i]) 945 return rte_flow_error_set(error, ENOTSUP, 946 RTE_FLOW_ERROR_TYPE_ITEM, 947 item, 948 "mask enables non supported" 949 " bits"); 950 if (!item->spec && (item->mask || item->last)) 951 return rte_flow_error_set(error, EINVAL, 952 RTE_FLOW_ERROR_TYPE_ITEM, item, 953 "mask/last without a spec is not" 954 " supported"); 955 if (item->spec && item->last && !range_accepted) { 956 uint8_t spec[size]; 957 uint8_t last[size]; 958 unsigned int i; 959 int ret; 960 961 for (i = 0; i < size; ++i) { 962 spec[i] = ((const uint8_t *)item->spec)[i] & mask[i]; 963 last[i] = ((const uint8_t *)item->last)[i] & mask[i]; 964 } 965 ret = memcmp(spec, last, size); 966 if (ret != 0) 967 return rte_flow_error_set(error, EINVAL, 968 RTE_FLOW_ERROR_TYPE_ITEM, 969 item, 970 "range is not valid"); 971 } 972 return 0; 973 } 974 975 /** 976 * Adjust the hash fields according to the @p flow information. 977 * 978 * @param[in] dev_flow. 979 * Pointer to the mlx5_flow. 980 * @param[in] tunnel 981 * 1 when the hash field is for a tunnel item. 982 * @param[in] layer_types 983 * ETH_RSS_* types. 984 * @param[in] hash_fields 985 * Item hash fields. 986 * 987 * @return 988 * The hash fields that should be used. 989 */ 990 uint64_t 991 mlx5_flow_hashfields_adjust(struct mlx5_flow_rss_desc *rss_desc, 992 int tunnel __rte_unused, uint64_t layer_types, 993 uint64_t hash_fields) 994 { 995 #ifdef HAVE_IBV_DEVICE_TUNNEL_SUPPORT 996 int rss_request_inner = rss_desc->level >= 2; 997 998 /* Check RSS hash level for tunnel. */ 999 if (tunnel && rss_request_inner) 1000 hash_fields |= IBV_RX_HASH_INNER; 1001 else if (tunnel || rss_request_inner) 1002 return 0; 1003 #endif 1004 /* Check if requested layer matches RSS hash fields. */ 1005 if (!(rss_desc->types & layer_types)) 1006 return 0; 1007 return hash_fields; 1008 } 1009 1010 /** 1011 * Lookup and set the ptype in the data Rx part. A single Ptype can be used, 1012 * if several tunnel rules are used on this queue, the tunnel ptype will be 1013 * cleared. 1014 * 1015 * @param rxq_ctrl 1016 * Rx queue to update. 1017 */ 1018 static void 1019 flow_rxq_tunnel_ptype_update(struct mlx5_rxq_ctrl *rxq_ctrl) 1020 { 1021 unsigned int i; 1022 uint32_t tunnel_ptype = 0; 1023 1024 /* Look up for the ptype to use. */ 1025 for (i = 0; i != MLX5_FLOW_TUNNEL; ++i) { 1026 if (!rxq_ctrl->flow_tunnels_n[i]) 1027 continue; 1028 if (!tunnel_ptype) { 1029 tunnel_ptype = tunnels_info[i].ptype; 1030 } else { 1031 tunnel_ptype = 0; 1032 break; 1033 } 1034 } 1035 rxq_ctrl->rxq.tunnel = tunnel_ptype; 1036 } 1037 1038 /** 1039 * Set the Rx queue flags (Mark/Flag and Tunnel Ptypes) according to the devive 1040 * flow. 1041 * 1042 * @param[in] dev 1043 * Pointer to the Ethernet device structure. 1044 * @param[in] dev_handle 1045 * Pointer to device flow handle structure. 1046 */ 1047 static void 1048 flow_drv_rxq_flags_set(struct rte_eth_dev *dev, 1049 struct mlx5_flow_handle *dev_handle) 1050 { 1051 struct mlx5_priv *priv = dev->data->dev_private; 1052 const int mark = dev_handle->mark; 1053 const int tunnel = !!(dev_handle->layers & MLX5_FLOW_LAYER_TUNNEL); 1054 struct mlx5_ind_table_obj *ind_tbl = NULL; 1055 unsigned int i; 1056 1057 if (dev_handle->fate_action == MLX5_FLOW_FATE_QUEUE) { 1058 struct mlx5_hrxq *hrxq; 1059 1060 hrxq = mlx5_ipool_get(priv->sh->ipool[MLX5_IPOOL_HRXQ], 1061 dev_handle->rix_hrxq); 1062 if (hrxq) 1063 ind_tbl = hrxq->ind_table; 1064 } else if (dev_handle->fate_action == MLX5_FLOW_FATE_SHARED_RSS) { 1065 struct mlx5_shared_action_rss *shared_rss; 1066 1067 shared_rss = mlx5_ipool_get 1068 (priv->sh->ipool[MLX5_IPOOL_RSS_SHARED_ACTIONS], 1069 dev_handle->rix_srss); 1070 if (shared_rss) 1071 ind_tbl = shared_rss->ind_tbl; 1072 } 1073 if (!ind_tbl) 1074 return; 1075 for (i = 0; i != ind_tbl->queues_n; ++i) { 1076 int idx = ind_tbl->queues[i]; 1077 struct mlx5_rxq_ctrl *rxq_ctrl = 1078 container_of((*priv->rxqs)[idx], 1079 struct mlx5_rxq_ctrl, rxq); 1080 1081 /* 1082 * To support metadata register copy on Tx loopback, 1083 * this must be always enabled (metadata may arive 1084 * from other port - not from local flows only. 1085 */ 1086 if (priv->config.dv_flow_en && 1087 priv->config.dv_xmeta_en != MLX5_XMETA_MODE_LEGACY && 1088 mlx5_flow_ext_mreg_supported(dev)) { 1089 rxq_ctrl->rxq.mark = 1; 1090 rxq_ctrl->flow_mark_n = 1; 1091 } else if (mark) { 1092 rxq_ctrl->rxq.mark = 1; 1093 rxq_ctrl->flow_mark_n++; 1094 } 1095 if (tunnel) { 1096 unsigned int j; 1097 1098 /* Increase the counter matching the flow. */ 1099 for (j = 0; j != MLX5_FLOW_TUNNEL; ++j) { 1100 if ((tunnels_info[j].tunnel & 1101 dev_handle->layers) == 1102 tunnels_info[j].tunnel) { 1103 rxq_ctrl->flow_tunnels_n[j]++; 1104 break; 1105 } 1106 } 1107 flow_rxq_tunnel_ptype_update(rxq_ctrl); 1108 } 1109 } 1110 } 1111 1112 /** 1113 * Set the Rx queue flags (Mark/Flag and Tunnel Ptypes) for a flow 1114 * 1115 * @param[in] dev 1116 * Pointer to the Ethernet device structure. 1117 * @param[in] flow 1118 * Pointer to flow structure. 1119 */ 1120 static void 1121 flow_rxq_flags_set(struct rte_eth_dev *dev, struct rte_flow *flow) 1122 { 1123 struct mlx5_priv *priv = dev->data->dev_private; 1124 uint32_t handle_idx; 1125 struct mlx5_flow_handle *dev_handle; 1126 1127 SILIST_FOREACH(priv->sh->ipool[MLX5_IPOOL_MLX5_FLOW], flow->dev_handles, 1128 handle_idx, dev_handle, next) 1129 flow_drv_rxq_flags_set(dev, dev_handle); 1130 } 1131 1132 /** 1133 * Clear the Rx queue flags (Mark/Flag and Tunnel Ptype) associated with the 1134 * device flow if no other flow uses it with the same kind of request. 1135 * 1136 * @param dev 1137 * Pointer to Ethernet device. 1138 * @param[in] dev_handle 1139 * Pointer to the device flow handle structure. 1140 */ 1141 static void 1142 flow_drv_rxq_flags_trim(struct rte_eth_dev *dev, 1143 struct mlx5_flow_handle *dev_handle) 1144 { 1145 struct mlx5_priv *priv = dev->data->dev_private; 1146 const int mark = dev_handle->mark; 1147 const int tunnel = !!(dev_handle->layers & MLX5_FLOW_LAYER_TUNNEL); 1148 struct mlx5_ind_table_obj *ind_tbl = NULL; 1149 unsigned int i; 1150 1151 if (dev_handle->fate_action == MLX5_FLOW_FATE_QUEUE) { 1152 struct mlx5_hrxq *hrxq; 1153 1154 hrxq = mlx5_ipool_get(priv->sh->ipool[MLX5_IPOOL_HRXQ], 1155 dev_handle->rix_hrxq); 1156 if (hrxq) 1157 ind_tbl = hrxq->ind_table; 1158 } else if (dev_handle->fate_action == MLX5_FLOW_FATE_SHARED_RSS) { 1159 struct mlx5_shared_action_rss *shared_rss; 1160 1161 shared_rss = mlx5_ipool_get 1162 (priv->sh->ipool[MLX5_IPOOL_RSS_SHARED_ACTIONS], 1163 dev_handle->rix_srss); 1164 if (shared_rss) 1165 ind_tbl = shared_rss->ind_tbl; 1166 } 1167 if (!ind_tbl) 1168 return; 1169 MLX5_ASSERT(dev->data->dev_started); 1170 for (i = 0; i != ind_tbl->queues_n; ++i) { 1171 int idx = ind_tbl->queues[i]; 1172 struct mlx5_rxq_ctrl *rxq_ctrl = 1173 container_of((*priv->rxqs)[idx], 1174 struct mlx5_rxq_ctrl, rxq); 1175 1176 if (priv->config.dv_flow_en && 1177 priv->config.dv_xmeta_en != MLX5_XMETA_MODE_LEGACY && 1178 mlx5_flow_ext_mreg_supported(dev)) { 1179 rxq_ctrl->rxq.mark = 1; 1180 rxq_ctrl->flow_mark_n = 1; 1181 } else if (mark) { 1182 rxq_ctrl->flow_mark_n--; 1183 rxq_ctrl->rxq.mark = !!rxq_ctrl->flow_mark_n; 1184 } 1185 if (tunnel) { 1186 unsigned int j; 1187 1188 /* Decrease the counter matching the flow. */ 1189 for (j = 0; j != MLX5_FLOW_TUNNEL; ++j) { 1190 if ((tunnels_info[j].tunnel & 1191 dev_handle->layers) == 1192 tunnels_info[j].tunnel) { 1193 rxq_ctrl->flow_tunnels_n[j]--; 1194 break; 1195 } 1196 } 1197 flow_rxq_tunnel_ptype_update(rxq_ctrl); 1198 } 1199 } 1200 } 1201 1202 /** 1203 * Clear the Rx queue flags (Mark/Flag and Tunnel Ptype) associated with the 1204 * @p flow if no other flow uses it with the same kind of request. 1205 * 1206 * @param dev 1207 * Pointer to Ethernet device. 1208 * @param[in] flow 1209 * Pointer to the flow. 1210 */ 1211 static void 1212 flow_rxq_flags_trim(struct rte_eth_dev *dev, struct rte_flow *flow) 1213 { 1214 struct mlx5_priv *priv = dev->data->dev_private; 1215 uint32_t handle_idx; 1216 struct mlx5_flow_handle *dev_handle; 1217 1218 SILIST_FOREACH(priv->sh->ipool[MLX5_IPOOL_MLX5_FLOW], flow->dev_handles, 1219 handle_idx, dev_handle, next) 1220 flow_drv_rxq_flags_trim(dev, dev_handle); 1221 } 1222 1223 /** 1224 * Clear the Mark/Flag and Tunnel ptype information in all Rx queues. 1225 * 1226 * @param dev 1227 * Pointer to Ethernet device. 1228 */ 1229 static void 1230 flow_rxq_flags_clear(struct rte_eth_dev *dev) 1231 { 1232 struct mlx5_priv *priv = dev->data->dev_private; 1233 unsigned int i; 1234 1235 for (i = 0; i != priv->rxqs_n; ++i) { 1236 struct mlx5_rxq_ctrl *rxq_ctrl; 1237 unsigned int j; 1238 1239 if (!(*priv->rxqs)[i]) 1240 continue; 1241 rxq_ctrl = container_of((*priv->rxqs)[i], 1242 struct mlx5_rxq_ctrl, rxq); 1243 rxq_ctrl->flow_mark_n = 0; 1244 rxq_ctrl->rxq.mark = 0; 1245 for (j = 0; j != MLX5_FLOW_TUNNEL; ++j) 1246 rxq_ctrl->flow_tunnels_n[j] = 0; 1247 rxq_ctrl->rxq.tunnel = 0; 1248 } 1249 } 1250 1251 /** 1252 * Set the Rx queue dynamic metadata (mask and offset) for a flow 1253 * 1254 * @param[in] dev 1255 * Pointer to the Ethernet device structure. 1256 */ 1257 void 1258 mlx5_flow_rxq_dynf_metadata_set(struct rte_eth_dev *dev) 1259 { 1260 struct mlx5_priv *priv = dev->data->dev_private; 1261 struct mlx5_rxq_data *data; 1262 unsigned int i; 1263 1264 for (i = 0; i != priv->rxqs_n; ++i) { 1265 if (!(*priv->rxqs)[i]) 1266 continue; 1267 data = (*priv->rxqs)[i]; 1268 if (!rte_flow_dynf_metadata_avail()) { 1269 data->dynf_meta = 0; 1270 data->flow_meta_mask = 0; 1271 data->flow_meta_offset = -1; 1272 data->flow_meta_port_mask = 0; 1273 } else { 1274 data->dynf_meta = 1; 1275 data->flow_meta_mask = rte_flow_dynf_metadata_mask; 1276 data->flow_meta_offset = rte_flow_dynf_metadata_offs; 1277 data->flow_meta_port_mask = (uint32_t)~0; 1278 if (priv->config.dv_xmeta_en == MLX5_XMETA_MODE_META16) 1279 data->flow_meta_port_mask >>= 16; 1280 } 1281 } 1282 } 1283 1284 /* 1285 * return a pointer to the desired action in the list of actions. 1286 * 1287 * @param[in] actions 1288 * The list of actions to search the action in. 1289 * @param[in] action 1290 * The action to find. 1291 * 1292 * @return 1293 * Pointer to the action in the list, if found. NULL otherwise. 1294 */ 1295 const struct rte_flow_action * 1296 mlx5_flow_find_action(const struct rte_flow_action *actions, 1297 enum rte_flow_action_type action) 1298 { 1299 if (actions == NULL) 1300 return NULL; 1301 for (; actions->type != RTE_FLOW_ACTION_TYPE_END; actions++) 1302 if (actions->type == action) 1303 return actions; 1304 return NULL; 1305 } 1306 1307 /* 1308 * Validate the flag action. 1309 * 1310 * @param[in] action_flags 1311 * Bit-fields that holds the actions detected until now. 1312 * @param[in] attr 1313 * Attributes of flow that includes this action. 1314 * @param[out] error 1315 * Pointer to error structure. 1316 * 1317 * @return 1318 * 0 on success, a negative errno value otherwise and rte_errno is set. 1319 */ 1320 int 1321 mlx5_flow_validate_action_flag(uint64_t action_flags, 1322 const struct rte_flow_attr *attr, 1323 struct rte_flow_error *error) 1324 { 1325 if (action_flags & MLX5_FLOW_ACTION_MARK) 1326 return rte_flow_error_set(error, EINVAL, 1327 RTE_FLOW_ERROR_TYPE_ACTION, NULL, 1328 "can't mark and flag in same flow"); 1329 if (action_flags & MLX5_FLOW_ACTION_FLAG) 1330 return rte_flow_error_set(error, EINVAL, 1331 RTE_FLOW_ERROR_TYPE_ACTION, NULL, 1332 "can't have 2 flag" 1333 " actions in same flow"); 1334 if (attr->egress) 1335 return rte_flow_error_set(error, ENOTSUP, 1336 RTE_FLOW_ERROR_TYPE_ATTR_EGRESS, NULL, 1337 "flag action not supported for " 1338 "egress"); 1339 return 0; 1340 } 1341 1342 /* 1343 * Validate the mark action. 1344 * 1345 * @param[in] action 1346 * Pointer to the queue action. 1347 * @param[in] action_flags 1348 * Bit-fields that holds the actions detected until now. 1349 * @param[in] attr 1350 * Attributes of flow that includes this action. 1351 * @param[out] error 1352 * Pointer to error structure. 1353 * 1354 * @return 1355 * 0 on success, a negative errno value otherwise and rte_errno is set. 1356 */ 1357 int 1358 mlx5_flow_validate_action_mark(const struct rte_flow_action *action, 1359 uint64_t action_flags, 1360 const struct rte_flow_attr *attr, 1361 struct rte_flow_error *error) 1362 { 1363 const struct rte_flow_action_mark *mark = action->conf; 1364 1365 if (!mark) 1366 return rte_flow_error_set(error, EINVAL, 1367 RTE_FLOW_ERROR_TYPE_ACTION, 1368 action, 1369 "configuration cannot be null"); 1370 if (mark->id >= MLX5_FLOW_MARK_MAX) 1371 return rte_flow_error_set(error, EINVAL, 1372 RTE_FLOW_ERROR_TYPE_ACTION_CONF, 1373 &mark->id, 1374 "mark id must in 0 <= id < " 1375 RTE_STR(MLX5_FLOW_MARK_MAX)); 1376 if (action_flags & MLX5_FLOW_ACTION_FLAG) 1377 return rte_flow_error_set(error, EINVAL, 1378 RTE_FLOW_ERROR_TYPE_ACTION, NULL, 1379 "can't flag and mark in same flow"); 1380 if (action_flags & MLX5_FLOW_ACTION_MARK) 1381 return rte_flow_error_set(error, EINVAL, 1382 RTE_FLOW_ERROR_TYPE_ACTION, NULL, 1383 "can't have 2 mark actions in same" 1384 " flow"); 1385 if (attr->egress) 1386 return rte_flow_error_set(error, ENOTSUP, 1387 RTE_FLOW_ERROR_TYPE_ATTR_EGRESS, NULL, 1388 "mark action not supported for " 1389 "egress"); 1390 return 0; 1391 } 1392 1393 /* 1394 * Validate the drop action. 1395 * 1396 * @param[in] action_flags 1397 * Bit-fields that holds the actions detected until now. 1398 * @param[in] attr 1399 * Attributes of flow that includes this action. 1400 * @param[out] error 1401 * Pointer to error structure. 1402 * 1403 * @return 1404 * 0 on success, a negative errno value otherwise and rte_errno is set. 1405 */ 1406 int 1407 mlx5_flow_validate_action_drop(uint64_t action_flags __rte_unused, 1408 const struct rte_flow_attr *attr, 1409 struct rte_flow_error *error) 1410 { 1411 if (attr->egress) 1412 return rte_flow_error_set(error, ENOTSUP, 1413 RTE_FLOW_ERROR_TYPE_ATTR_EGRESS, NULL, 1414 "drop action not supported for " 1415 "egress"); 1416 return 0; 1417 } 1418 1419 /* 1420 * Validate the queue action. 1421 * 1422 * @param[in] action 1423 * Pointer to the queue action. 1424 * @param[in] action_flags 1425 * Bit-fields that holds the actions detected until now. 1426 * @param[in] dev 1427 * Pointer to the Ethernet device structure. 1428 * @param[in] attr 1429 * Attributes of flow that includes this action. 1430 * @param[out] error 1431 * Pointer to error structure. 1432 * 1433 * @return 1434 * 0 on success, a negative errno value otherwise and rte_errno is set. 1435 */ 1436 int 1437 mlx5_flow_validate_action_queue(const struct rte_flow_action *action, 1438 uint64_t action_flags, 1439 struct rte_eth_dev *dev, 1440 const struct rte_flow_attr *attr, 1441 struct rte_flow_error *error) 1442 { 1443 struct mlx5_priv *priv = dev->data->dev_private; 1444 const struct rte_flow_action_queue *queue = action->conf; 1445 1446 if (action_flags & MLX5_FLOW_FATE_ACTIONS) 1447 return rte_flow_error_set(error, EINVAL, 1448 RTE_FLOW_ERROR_TYPE_ACTION, NULL, 1449 "can't have 2 fate actions in" 1450 " same flow"); 1451 if (!priv->rxqs_n) 1452 return rte_flow_error_set(error, EINVAL, 1453 RTE_FLOW_ERROR_TYPE_ACTION_CONF, 1454 NULL, "No Rx queues configured"); 1455 if (queue->index >= priv->rxqs_n) 1456 return rte_flow_error_set(error, EINVAL, 1457 RTE_FLOW_ERROR_TYPE_ACTION_CONF, 1458 &queue->index, 1459 "queue index out of range"); 1460 if (!(*priv->rxqs)[queue->index]) 1461 return rte_flow_error_set(error, EINVAL, 1462 RTE_FLOW_ERROR_TYPE_ACTION_CONF, 1463 &queue->index, 1464 "queue is not configured"); 1465 if (attr->egress) 1466 return rte_flow_error_set(error, ENOTSUP, 1467 RTE_FLOW_ERROR_TYPE_ATTR_EGRESS, NULL, 1468 "queue action not supported for " 1469 "egress"); 1470 return 0; 1471 } 1472 1473 /* 1474 * Validate the rss action. 1475 * 1476 * @param[in] dev 1477 * Pointer to the Ethernet device structure. 1478 * @param[in] action 1479 * Pointer to the queue action. 1480 * @param[out] error 1481 * Pointer to error structure. 1482 * 1483 * @return 1484 * 0 on success, a negative errno value otherwise and rte_errno is set. 1485 */ 1486 int 1487 mlx5_validate_action_rss(struct rte_eth_dev *dev, 1488 const struct rte_flow_action *action, 1489 struct rte_flow_error *error) 1490 { 1491 struct mlx5_priv *priv = dev->data->dev_private; 1492 const struct rte_flow_action_rss *rss = action->conf; 1493 enum mlx5_rxq_type rxq_type = MLX5_RXQ_TYPE_UNDEFINED; 1494 unsigned int i; 1495 1496 if (rss->func != RTE_ETH_HASH_FUNCTION_DEFAULT && 1497 rss->func != RTE_ETH_HASH_FUNCTION_TOEPLITZ) 1498 return rte_flow_error_set(error, ENOTSUP, 1499 RTE_FLOW_ERROR_TYPE_ACTION_CONF, 1500 &rss->func, 1501 "RSS hash function not supported"); 1502 #ifdef HAVE_IBV_DEVICE_TUNNEL_SUPPORT 1503 if (rss->level > 2) 1504 #else 1505 if (rss->level > 1) 1506 #endif 1507 return rte_flow_error_set(error, ENOTSUP, 1508 RTE_FLOW_ERROR_TYPE_ACTION_CONF, 1509 &rss->level, 1510 "tunnel RSS is not supported"); 1511 /* allow RSS key_len 0 in case of NULL (default) RSS key. */ 1512 if (rss->key_len == 0 && rss->key != NULL) 1513 return rte_flow_error_set(error, ENOTSUP, 1514 RTE_FLOW_ERROR_TYPE_ACTION_CONF, 1515 &rss->key_len, 1516 "RSS hash key length 0"); 1517 if (rss->key_len > 0 && rss->key_len < MLX5_RSS_HASH_KEY_LEN) 1518 return rte_flow_error_set(error, ENOTSUP, 1519 RTE_FLOW_ERROR_TYPE_ACTION_CONF, 1520 &rss->key_len, 1521 "RSS hash key too small"); 1522 if (rss->key_len > MLX5_RSS_HASH_KEY_LEN) 1523 return rte_flow_error_set(error, ENOTSUP, 1524 RTE_FLOW_ERROR_TYPE_ACTION_CONF, 1525 &rss->key_len, 1526 "RSS hash key too large"); 1527 if (rss->queue_num > priv->config.ind_table_max_size) 1528 return rte_flow_error_set(error, ENOTSUP, 1529 RTE_FLOW_ERROR_TYPE_ACTION_CONF, 1530 &rss->queue_num, 1531 "number of queues too large"); 1532 if (rss->types & MLX5_RSS_HF_MASK) 1533 return rte_flow_error_set(error, ENOTSUP, 1534 RTE_FLOW_ERROR_TYPE_ACTION_CONF, 1535 &rss->types, 1536 "some RSS protocols are not" 1537 " supported"); 1538 if ((rss->types & (ETH_RSS_L3_SRC_ONLY | ETH_RSS_L3_DST_ONLY)) && 1539 !(rss->types & ETH_RSS_IP)) 1540 return rte_flow_error_set(error, EINVAL, 1541 RTE_FLOW_ERROR_TYPE_ACTION_CONF, NULL, 1542 "L3 partial RSS requested but L3 RSS" 1543 " type not specified"); 1544 if ((rss->types & (ETH_RSS_L4_SRC_ONLY | ETH_RSS_L4_DST_ONLY)) && 1545 !(rss->types & (ETH_RSS_UDP | ETH_RSS_TCP))) 1546 return rte_flow_error_set(error, EINVAL, 1547 RTE_FLOW_ERROR_TYPE_ACTION_CONF, NULL, 1548 "L4 partial RSS requested but L4 RSS" 1549 " type not specified"); 1550 if (!priv->rxqs_n) 1551 return rte_flow_error_set(error, EINVAL, 1552 RTE_FLOW_ERROR_TYPE_ACTION_CONF, 1553 NULL, "No Rx queues configured"); 1554 if (!rss->queue_num) 1555 return rte_flow_error_set(error, EINVAL, 1556 RTE_FLOW_ERROR_TYPE_ACTION_CONF, 1557 NULL, "No queues configured"); 1558 for (i = 0; i != rss->queue_num; ++i) { 1559 struct mlx5_rxq_ctrl *rxq_ctrl; 1560 1561 if (rss->queue[i] >= priv->rxqs_n) 1562 return rte_flow_error_set 1563 (error, EINVAL, 1564 RTE_FLOW_ERROR_TYPE_ACTION_CONF, 1565 &rss->queue[i], "queue index out of range"); 1566 if (!(*priv->rxqs)[rss->queue[i]]) 1567 return rte_flow_error_set 1568 (error, EINVAL, RTE_FLOW_ERROR_TYPE_ACTION_CONF, 1569 &rss->queue[i], "queue is not configured"); 1570 rxq_ctrl = container_of((*priv->rxqs)[rss->queue[i]], 1571 struct mlx5_rxq_ctrl, rxq); 1572 if (i == 0) 1573 rxq_type = rxq_ctrl->type; 1574 if (rxq_type != rxq_ctrl->type) 1575 return rte_flow_error_set 1576 (error, ENOTSUP, RTE_FLOW_ERROR_TYPE_ACTION_CONF, 1577 &rss->queue[i], 1578 "combining hairpin and regular RSS queues is not supported"); 1579 } 1580 return 0; 1581 } 1582 1583 /* 1584 * Validate the rss action. 1585 * 1586 * @param[in] action 1587 * Pointer to the queue action. 1588 * @param[in] action_flags 1589 * Bit-fields that holds the actions detected until now. 1590 * @param[in] dev 1591 * Pointer to the Ethernet device structure. 1592 * @param[in] attr 1593 * Attributes of flow that includes this action. 1594 * @param[in] item_flags 1595 * Items that were detected. 1596 * @param[out] error 1597 * Pointer to error structure. 1598 * 1599 * @return 1600 * 0 on success, a negative errno value otherwise and rte_errno is set. 1601 */ 1602 int 1603 mlx5_flow_validate_action_rss(const struct rte_flow_action *action, 1604 uint64_t action_flags, 1605 struct rte_eth_dev *dev, 1606 const struct rte_flow_attr *attr, 1607 uint64_t item_flags, 1608 struct rte_flow_error *error) 1609 { 1610 const struct rte_flow_action_rss *rss = action->conf; 1611 int tunnel = !!(item_flags & MLX5_FLOW_LAYER_TUNNEL); 1612 int ret; 1613 1614 if (action_flags & MLX5_FLOW_FATE_ACTIONS) 1615 return rte_flow_error_set(error, EINVAL, 1616 RTE_FLOW_ERROR_TYPE_ACTION, NULL, 1617 "can't have 2 fate actions" 1618 " in same flow"); 1619 ret = mlx5_validate_action_rss(dev, action, error); 1620 if (ret) 1621 return ret; 1622 if (attr->egress) 1623 return rte_flow_error_set(error, ENOTSUP, 1624 RTE_FLOW_ERROR_TYPE_ATTR_EGRESS, NULL, 1625 "rss action not supported for " 1626 "egress"); 1627 if (rss->level > 1 && !tunnel) 1628 return rte_flow_error_set(error, EINVAL, 1629 RTE_FLOW_ERROR_TYPE_ACTION_CONF, NULL, 1630 "inner RSS is not supported for " 1631 "non-tunnel flows"); 1632 if ((item_flags & MLX5_FLOW_LAYER_ECPRI) && 1633 !(item_flags & MLX5_FLOW_LAYER_INNER_L4_UDP)) { 1634 return rte_flow_error_set(error, EINVAL, 1635 RTE_FLOW_ERROR_TYPE_ACTION_CONF, NULL, 1636 "RSS on eCPRI is not supported now"); 1637 } 1638 return 0; 1639 } 1640 1641 /* 1642 * Validate the default miss action. 1643 * 1644 * @param[in] action_flags 1645 * Bit-fields that holds the actions detected until now. 1646 * @param[out] error 1647 * Pointer to error structure. 1648 * 1649 * @return 1650 * 0 on success, a negative errno value otherwise and rte_errno is set. 1651 */ 1652 int 1653 mlx5_flow_validate_action_default_miss(uint64_t action_flags, 1654 const struct rte_flow_attr *attr, 1655 struct rte_flow_error *error) 1656 { 1657 if (action_flags & MLX5_FLOW_FATE_ACTIONS) 1658 return rte_flow_error_set(error, EINVAL, 1659 RTE_FLOW_ERROR_TYPE_ACTION, NULL, 1660 "can't have 2 fate actions in" 1661 " same flow"); 1662 if (attr->egress) 1663 return rte_flow_error_set(error, ENOTSUP, 1664 RTE_FLOW_ERROR_TYPE_ATTR_EGRESS, NULL, 1665 "default miss action not supported " 1666 "for egress"); 1667 if (attr->group) 1668 return rte_flow_error_set(error, ENOTSUP, 1669 RTE_FLOW_ERROR_TYPE_ATTR_GROUP, NULL, 1670 "only group 0 is supported"); 1671 if (attr->transfer) 1672 return rte_flow_error_set(error, ENOTSUP, 1673 RTE_FLOW_ERROR_TYPE_ATTR_TRANSFER, 1674 NULL, "transfer is not supported"); 1675 return 0; 1676 } 1677 1678 /* 1679 * Validate the count action. 1680 * 1681 * @param[in] dev 1682 * Pointer to the Ethernet device structure. 1683 * @param[in] attr 1684 * Attributes of flow that includes this action. 1685 * @param[out] error 1686 * Pointer to error structure. 1687 * 1688 * @return 1689 * 0 on success, a negative errno value otherwise and rte_errno is set. 1690 */ 1691 int 1692 mlx5_flow_validate_action_count(struct rte_eth_dev *dev __rte_unused, 1693 const struct rte_flow_attr *attr, 1694 struct rte_flow_error *error) 1695 { 1696 if (attr->egress) 1697 return rte_flow_error_set(error, ENOTSUP, 1698 RTE_FLOW_ERROR_TYPE_ATTR_EGRESS, NULL, 1699 "count action not supported for " 1700 "egress"); 1701 return 0; 1702 } 1703 1704 /** 1705 * Verify the @p attributes will be correctly understood by the NIC and store 1706 * them in the @p flow if everything is correct. 1707 * 1708 * @param[in] dev 1709 * Pointer to the Ethernet device structure. 1710 * @param[in] attributes 1711 * Pointer to flow attributes 1712 * @param[out] error 1713 * Pointer to error structure. 1714 * 1715 * @return 1716 * 0 on success, a negative errno value otherwise and rte_errno is set. 1717 */ 1718 int 1719 mlx5_flow_validate_attributes(struct rte_eth_dev *dev, 1720 const struct rte_flow_attr *attributes, 1721 struct rte_flow_error *error) 1722 { 1723 struct mlx5_priv *priv = dev->data->dev_private; 1724 uint32_t priority_max = priv->config.flow_prio - 1; 1725 1726 if (attributes->group) 1727 return rte_flow_error_set(error, ENOTSUP, 1728 RTE_FLOW_ERROR_TYPE_ATTR_GROUP, 1729 NULL, "groups is not supported"); 1730 if (attributes->priority != MLX5_FLOW_LOWEST_PRIO_INDICATOR && 1731 attributes->priority >= priority_max) 1732 return rte_flow_error_set(error, ENOTSUP, 1733 RTE_FLOW_ERROR_TYPE_ATTR_PRIORITY, 1734 NULL, "priority out of range"); 1735 if (attributes->egress) 1736 return rte_flow_error_set(error, ENOTSUP, 1737 RTE_FLOW_ERROR_TYPE_ATTR_EGRESS, NULL, 1738 "egress is not supported"); 1739 if (attributes->transfer && !priv->config.dv_esw_en) 1740 return rte_flow_error_set(error, ENOTSUP, 1741 RTE_FLOW_ERROR_TYPE_ATTR_TRANSFER, 1742 NULL, "transfer is not supported"); 1743 if (!attributes->ingress) 1744 return rte_flow_error_set(error, EINVAL, 1745 RTE_FLOW_ERROR_TYPE_ATTR_INGRESS, 1746 NULL, 1747 "ingress attribute is mandatory"); 1748 return 0; 1749 } 1750 1751 /** 1752 * Validate ICMP6 item. 1753 * 1754 * @param[in] item 1755 * Item specification. 1756 * @param[in] item_flags 1757 * Bit-fields that holds the items detected until now. 1758 * @param[in] ext_vlan_sup 1759 * Whether extended VLAN features are supported or not. 1760 * @param[out] error 1761 * Pointer to error structure. 1762 * 1763 * @return 1764 * 0 on success, a negative errno value otherwise and rte_errno is set. 1765 */ 1766 int 1767 mlx5_flow_validate_item_icmp6(const struct rte_flow_item *item, 1768 uint64_t item_flags, 1769 uint8_t target_protocol, 1770 struct rte_flow_error *error) 1771 { 1772 const struct rte_flow_item_icmp6 *mask = item->mask; 1773 const int tunnel = !!(item_flags & MLX5_FLOW_LAYER_TUNNEL); 1774 const uint64_t l3m = tunnel ? MLX5_FLOW_LAYER_INNER_L3_IPV6 : 1775 MLX5_FLOW_LAYER_OUTER_L3_IPV6; 1776 const uint64_t l4m = tunnel ? MLX5_FLOW_LAYER_INNER_L4 : 1777 MLX5_FLOW_LAYER_OUTER_L4; 1778 int ret; 1779 1780 if (target_protocol != 0xFF && target_protocol != IPPROTO_ICMPV6) 1781 return rte_flow_error_set(error, EINVAL, 1782 RTE_FLOW_ERROR_TYPE_ITEM, item, 1783 "protocol filtering not compatible" 1784 " with ICMP6 layer"); 1785 if (!(item_flags & l3m)) 1786 return rte_flow_error_set(error, EINVAL, 1787 RTE_FLOW_ERROR_TYPE_ITEM, item, 1788 "IPv6 is mandatory to filter on" 1789 " ICMP6"); 1790 if (item_flags & l4m) 1791 return rte_flow_error_set(error, EINVAL, 1792 RTE_FLOW_ERROR_TYPE_ITEM, item, 1793 "multiple L4 layers not supported"); 1794 if (!mask) 1795 mask = &rte_flow_item_icmp6_mask; 1796 ret = mlx5_flow_item_acceptable 1797 (item, (const uint8_t *)mask, 1798 (const uint8_t *)&rte_flow_item_icmp6_mask, 1799 sizeof(struct rte_flow_item_icmp6), 1800 MLX5_ITEM_RANGE_NOT_ACCEPTED, error); 1801 if (ret < 0) 1802 return ret; 1803 return 0; 1804 } 1805 1806 /** 1807 * Validate ICMP item. 1808 * 1809 * @param[in] item 1810 * Item specification. 1811 * @param[in] item_flags 1812 * Bit-fields that holds the items detected until now. 1813 * @param[out] error 1814 * Pointer to error structure. 1815 * 1816 * @return 1817 * 0 on success, a negative errno value otherwise and rte_errno is set. 1818 */ 1819 int 1820 mlx5_flow_validate_item_icmp(const struct rte_flow_item *item, 1821 uint64_t item_flags, 1822 uint8_t target_protocol, 1823 struct rte_flow_error *error) 1824 { 1825 const struct rte_flow_item_icmp *mask = item->mask; 1826 const struct rte_flow_item_icmp nic_mask = { 1827 .hdr.icmp_type = 0xff, 1828 .hdr.icmp_code = 0xff, 1829 .hdr.icmp_ident = RTE_BE16(0xffff), 1830 .hdr.icmp_seq_nb = RTE_BE16(0xffff), 1831 }; 1832 const int tunnel = !!(item_flags & MLX5_FLOW_LAYER_TUNNEL); 1833 const uint64_t l3m = tunnel ? MLX5_FLOW_LAYER_INNER_L3_IPV4 : 1834 MLX5_FLOW_LAYER_OUTER_L3_IPV4; 1835 const uint64_t l4m = tunnel ? MLX5_FLOW_LAYER_INNER_L4 : 1836 MLX5_FLOW_LAYER_OUTER_L4; 1837 int ret; 1838 1839 if (target_protocol != 0xFF && target_protocol != IPPROTO_ICMP) 1840 return rte_flow_error_set(error, EINVAL, 1841 RTE_FLOW_ERROR_TYPE_ITEM, item, 1842 "protocol filtering not compatible" 1843 " with ICMP layer"); 1844 if (!(item_flags & l3m)) 1845 return rte_flow_error_set(error, EINVAL, 1846 RTE_FLOW_ERROR_TYPE_ITEM, item, 1847 "IPv4 is mandatory to filter" 1848 " on ICMP"); 1849 if (item_flags & l4m) 1850 return rte_flow_error_set(error, EINVAL, 1851 RTE_FLOW_ERROR_TYPE_ITEM, item, 1852 "multiple L4 layers not supported"); 1853 if (!mask) 1854 mask = &nic_mask; 1855 ret = mlx5_flow_item_acceptable 1856 (item, (const uint8_t *)mask, 1857 (const uint8_t *)&nic_mask, 1858 sizeof(struct rte_flow_item_icmp), 1859 MLX5_ITEM_RANGE_NOT_ACCEPTED, error); 1860 if (ret < 0) 1861 return ret; 1862 return 0; 1863 } 1864 1865 /** 1866 * Validate Ethernet item. 1867 * 1868 * @param[in] item 1869 * Item specification. 1870 * @param[in] item_flags 1871 * Bit-fields that holds the items detected until now. 1872 * @param[out] error 1873 * Pointer to error structure. 1874 * 1875 * @return 1876 * 0 on success, a negative errno value otherwise and rte_errno is set. 1877 */ 1878 int 1879 mlx5_flow_validate_item_eth(const struct rte_flow_item *item, 1880 uint64_t item_flags, bool ext_vlan_sup, 1881 struct rte_flow_error *error) 1882 { 1883 const struct rte_flow_item_eth *mask = item->mask; 1884 const struct rte_flow_item_eth nic_mask = { 1885 .dst.addr_bytes = "\xff\xff\xff\xff\xff\xff", 1886 .src.addr_bytes = "\xff\xff\xff\xff\xff\xff", 1887 .type = RTE_BE16(0xffff), 1888 .has_vlan = ext_vlan_sup ? 1 : 0, 1889 }; 1890 int ret; 1891 int tunnel = !!(item_flags & MLX5_FLOW_LAYER_TUNNEL); 1892 const uint64_t ethm = tunnel ? MLX5_FLOW_LAYER_INNER_L2 : 1893 MLX5_FLOW_LAYER_OUTER_L2; 1894 1895 if (item_flags & ethm) 1896 return rte_flow_error_set(error, ENOTSUP, 1897 RTE_FLOW_ERROR_TYPE_ITEM, item, 1898 "multiple L2 layers not supported"); 1899 if ((!tunnel && (item_flags & MLX5_FLOW_LAYER_OUTER_L3)) || 1900 (tunnel && (item_flags & MLX5_FLOW_LAYER_INNER_L3))) 1901 return rte_flow_error_set(error, EINVAL, 1902 RTE_FLOW_ERROR_TYPE_ITEM, item, 1903 "L2 layer should not follow " 1904 "L3 layers"); 1905 if ((!tunnel && (item_flags & MLX5_FLOW_LAYER_OUTER_VLAN)) || 1906 (tunnel && (item_flags & MLX5_FLOW_LAYER_INNER_VLAN))) 1907 return rte_flow_error_set(error, EINVAL, 1908 RTE_FLOW_ERROR_TYPE_ITEM, item, 1909 "L2 layer should not follow VLAN"); 1910 if (!mask) 1911 mask = &rte_flow_item_eth_mask; 1912 ret = mlx5_flow_item_acceptable(item, (const uint8_t *)mask, 1913 (const uint8_t *)&nic_mask, 1914 sizeof(struct rte_flow_item_eth), 1915 MLX5_ITEM_RANGE_NOT_ACCEPTED, error); 1916 return ret; 1917 } 1918 1919 /** 1920 * Validate VLAN item. 1921 * 1922 * @param[in] item 1923 * Item specification. 1924 * @param[in] item_flags 1925 * Bit-fields that holds the items detected until now. 1926 * @param[in] dev 1927 * Ethernet device flow is being created on. 1928 * @param[out] error 1929 * Pointer to error structure. 1930 * 1931 * @return 1932 * 0 on success, a negative errno value otherwise and rte_errno is set. 1933 */ 1934 int 1935 mlx5_flow_validate_item_vlan(const struct rte_flow_item *item, 1936 uint64_t item_flags, 1937 struct rte_eth_dev *dev, 1938 struct rte_flow_error *error) 1939 { 1940 const struct rte_flow_item_vlan *spec = item->spec; 1941 const struct rte_flow_item_vlan *mask = item->mask; 1942 const struct rte_flow_item_vlan nic_mask = { 1943 .tci = RTE_BE16(UINT16_MAX), 1944 .inner_type = RTE_BE16(UINT16_MAX), 1945 }; 1946 uint16_t vlan_tag = 0; 1947 const int tunnel = !!(item_flags & MLX5_FLOW_LAYER_TUNNEL); 1948 int ret; 1949 const uint64_t l34m = tunnel ? (MLX5_FLOW_LAYER_INNER_L3 | 1950 MLX5_FLOW_LAYER_INNER_L4) : 1951 (MLX5_FLOW_LAYER_OUTER_L3 | 1952 MLX5_FLOW_LAYER_OUTER_L4); 1953 const uint64_t vlanm = tunnel ? MLX5_FLOW_LAYER_INNER_VLAN : 1954 MLX5_FLOW_LAYER_OUTER_VLAN; 1955 1956 if (item_flags & vlanm) 1957 return rte_flow_error_set(error, EINVAL, 1958 RTE_FLOW_ERROR_TYPE_ITEM, item, 1959 "multiple VLAN layers not supported"); 1960 else if ((item_flags & l34m) != 0) 1961 return rte_flow_error_set(error, EINVAL, 1962 RTE_FLOW_ERROR_TYPE_ITEM, item, 1963 "VLAN cannot follow L3/L4 layer"); 1964 if (!mask) 1965 mask = &rte_flow_item_vlan_mask; 1966 ret = mlx5_flow_item_acceptable(item, (const uint8_t *)mask, 1967 (const uint8_t *)&nic_mask, 1968 sizeof(struct rte_flow_item_vlan), 1969 MLX5_ITEM_RANGE_NOT_ACCEPTED, error); 1970 if (ret) 1971 return ret; 1972 if (!tunnel && mask->tci != RTE_BE16(0x0fff)) { 1973 struct mlx5_priv *priv = dev->data->dev_private; 1974 1975 if (priv->vmwa_context) { 1976 /* 1977 * Non-NULL context means we have a virtual machine 1978 * and SR-IOV enabled, we have to create VLAN interface 1979 * to make hypervisor to setup E-Switch vport 1980 * context correctly. We avoid creating the multiple 1981 * VLAN interfaces, so we cannot support VLAN tag mask. 1982 */ 1983 return rte_flow_error_set(error, EINVAL, 1984 RTE_FLOW_ERROR_TYPE_ITEM, 1985 item, 1986 "VLAN tag mask is not" 1987 " supported in virtual" 1988 " environment"); 1989 } 1990 } 1991 if (spec) { 1992 vlan_tag = spec->tci; 1993 vlan_tag &= mask->tci; 1994 } 1995 /* 1996 * From verbs perspective an empty VLAN is equivalent 1997 * to a packet without VLAN layer. 1998 */ 1999 if (!vlan_tag) 2000 return rte_flow_error_set(error, EINVAL, 2001 RTE_FLOW_ERROR_TYPE_ITEM_SPEC, 2002 item->spec, 2003 "VLAN cannot be empty"); 2004 return 0; 2005 } 2006 2007 /** 2008 * Validate IPV4 item. 2009 * 2010 * @param[in] item 2011 * Item specification. 2012 * @param[in] item_flags 2013 * Bit-fields that holds the items detected until now. 2014 * @param[in] last_item 2015 * Previous validated item in the pattern items. 2016 * @param[in] ether_type 2017 * Type in the ethernet layer header (including dot1q). 2018 * @param[in] acc_mask 2019 * Acceptable mask, if NULL default internal default mask 2020 * will be used to check whether item fields are supported. 2021 * @param[in] range_accepted 2022 * True if range of values is accepted for specific fields, false otherwise. 2023 * @param[out] error 2024 * Pointer to error structure. 2025 * 2026 * @return 2027 * 0 on success, a negative errno value otherwise and rte_errno is set. 2028 */ 2029 int 2030 mlx5_flow_validate_item_ipv4(const struct rte_flow_item *item, 2031 uint64_t item_flags, 2032 uint64_t last_item, 2033 uint16_t ether_type, 2034 const struct rte_flow_item_ipv4 *acc_mask, 2035 bool range_accepted, 2036 struct rte_flow_error *error) 2037 { 2038 const struct rte_flow_item_ipv4 *mask = item->mask; 2039 const struct rte_flow_item_ipv4 *spec = item->spec; 2040 const struct rte_flow_item_ipv4 nic_mask = { 2041 .hdr = { 2042 .src_addr = RTE_BE32(0xffffffff), 2043 .dst_addr = RTE_BE32(0xffffffff), 2044 .type_of_service = 0xff, 2045 .next_proto_id = 0xff, 2046 }, 2047 }; 2048 const int tunnel = !!(item_flags & MLX5_FLOW_LAYER_TUNNEL); 2049 const uint64_t l3m = tunnel ? MLX5_FLOW_LAYER_INNER_L3 : 2050 MLX5_FLOW_LAYER_OUTER_L3; 2051 const uint64_t l4m = tunnel ? MLX5_FLOW_LAYER_INNER_L4 : 2052 MLX5_FLOW_LAYER_OUTER_L4; 2053 int ret; 2054 uint8_t next_proto = 0xFF; 2055 const uint64_t l2_vlan = (MLX5_FLOW_LAYER_L2 | 2056 MLX5_FLOW_LAYER_OUTER_VLAN | 2057 MLX5_FLOW_LAYER_INNER_VLAN); 2058 2059 if ((last_item & l2_vlan) && ether_type && 2060 ether_type != RTE_ETHER_TYPE_IPV4) 2061 return rte_flow_error_set(error, EINVAL, 2062 RTE_FLOW_ERROR_TYPE_ITEM, item, 2063 "IPv4 cannot follow L2/VLAN layer " 2064 "which ether type is not IPv4"); 2065 if (item_flags & MLX5_FLOW_LAYER_IPIP) { 2066 if (mask && spec) 2067 next_proto = mask->hdr.next_proto_id & 2068 spec->hdr.next_proto_id; 2069 if (next_proto == IPPROTO_IPIP || next_proto == IPPROTO_IPV6) 2070 return rte_flow_error_set(error, EINVAL, 2071 RTE_FLOW_ERROR_TYPE_ITEM, 2072 item, 2073 "multiple tunnel " 2074 "not supported"); 2075 } 2076 if (item_flags & MLX5_FLOW_LAYER_IPV6_ENCAP) 2077 return rte_flow_error_set(error, EINVAL, 2078 RTE_FLOW_ERROR_TYPE_ITEM, item, 2079 "wrong tunnel type - IPv6 specified " 2080 "but IPv4 item provided"); 2081 if (item_flags & l3m) 2082 return rte_flow_error_set(error, ENOTSUP, 2083 RTE_FLOW_ERROR_TYPE_ITEM, item, 2084 "multiple L3 layers not supported"); 2085 else if (item_flags & l4m) 2086 return rte_flow_error_set(error, EINVAL, 2087 RTE_FLOW_ERROR_TYPE_ITEM, item, 2088 "L3 cannot follow an L4 layer."); 2089 else if ((item_flags & MLX5_FLOW_LAYER_NVGRE) && 2090 !(item_flags & MLX5_FLOW_LAYER_INNER_L2)) 2091 return rte_flow_error_set(error, EINVAL, 2092 RTE_FLOW_ERROR_TYPE_ITEM, item, 2093 "L3 cannot follow an NVGRE layer."); 2094 if (!mask) 2095 mask = &rte_flow_item_ipv4_mask; 2096 else if (mask->hdr.next_proto_id != 0 && 2097 mask->hdr.next_proto_id != 0xff) 2098 return rte_flow_error_set(error, EINVAL, 2099 RTE_FLOW_ERROR_TYPE_ITEM_MASK, mask, 2100 "partial mask is not supported" 2101 " for protocol"); 2102 ret = mlx5_flow_item_acceptable(item, (const uint8_t *)mask, 2103 acc_mask ? (const uint8_t *)acc_mask 2104 : (const uint8_t *)&nic_mask, 2105 sizeof(struct rte_flow_item_ipv4), 2106 range_accepted, error); 2107 if (ret < 0) 2108 return ret; 2109 return 0; 2110 } 2111 2112 /** 2113 * Validate IPV6 item. 2114 * 2115 * @param[in] item 2116 * Item specification. 2117 * @param[in] item_flags 2118 * Bit-fields that holds the items detected until now. 2119 * @param[in] last_item 2120 * Previous validated item in the pattern items. 2121 * @param[in] ether_type 2122 * Type in the ethernet layer header (including dot1q). 2123 * @param[in] acc_mask 2124 * Acceptable mask, if NULL default internal default mask 2125 * will be used to check whether item fields are supported. 2126 * @param[out] error 2127 * Pointer to error structure. 2128 * 2129 * @return 2130 * 0 on success, a negative errno value otherwise and rte_errno is set. 2131 */ 2132 int 2133 mlx5_flow_validate_item_ipv6(const struct rte_flow_item *item, 2134 uint64_t item_flags, 2135 uint64_t last_item, 2136 uint16_t ether_type, 2137 const struct rte_flow_item_ipv6 *acc_mask, 2138 struct rte_flow_error *error) 2139 { 2140 const struct rte_flow_item_ipv6 *mask = item->mask; 2141 const struct rte_flow_item_ipv6 *spec = item->spec; 2142 const struct rte_flow_item_ipv6 nic_mask = { 2143 .hdr = { 2144 .src_addr = 2145 "\xff\xff\xff\xff\xff\xff\xff\xff" 2146 "\xff\xff\xff\xff\xff\xff\xff\xff", 2147 .dst_addr = 2148 "\xff\xff\xff\xff\xff\xff\xff\xff" 2149 "\xff\xff\xff\xff\xff\xff\xff\xff", 2150 .vtc_flow = RTE_BE32(0xffffffff), 2151 .proto = 0xff, 2152 }, 2153 }; 2154 const int tunnel = !!(item_flags & MLX5_FLOW_LAYER_TUNNEL); 2155 const uint64_t l3m = tunnel ? MLX5_FLOW_LAYER_INNER_L3 : 2156 MLX5_FLOW_LAYER_OUTER_L3; 2157 const uint64_t l4m = tunnel ? MLX5_FLOW_LAYER_INNER_L4 : 2158 MLX5_FLOW_LAYER_OUTER_L4; 2159 int ret; 2160 uint8_t next_proto = 0xFF; 2161 const uint64_t l2_vlan = (MLX5_FLOW_LAYER_L2 | 2162 MLX5_FLOW_LAYER_OUTER_VLAN | 2163 MLX5_FLOW_LAYER_INNER_VLAN); 2164 2165 if ((last_item & l2_vlan) && ether_type && 2166 ether_type != RTE_ETHER_TYPE_IPV6) 2167 return rte_flow_error_set(error, EINVAL, 2168 RTE_FLOW_ERROR_TYPE_ITEM, item, 2169 "IPv6 cannot follow L2/VLAN layer " 2170 "which ether type is not IPv6"); 2171 if (mask && mask->hdr.proto == UINT8_MAX && spec) 2172 next_proto = spec->hdr.proto; 2173 if (item_flags & MLX5_FLOW_LAYER_IPV6_ENCAP) { 2174 if (next_proto == IPPROTO_IPIP || next_proto == IPPROTO_IPV6) 2175 return rte_flow_error_set(error, EINVAL, 2176 RTE_FLOW_ERROR_TYPE_ITEM, 2177 item, 2178 "multiple tunnel " 2179 "not supported"); 2180 } 2181 if (next_proto == IPPROTO_HOPOPTS || 2182 next_proto == IPPROTO_ROUTING || 2183 next_proto == IPPROTO_FRAGMENT || 2184 next_proto == IPPROTO_ESP || 2185 next_proto == IPPROTO_AH || 2186 next_proto == IPPROTO_DSTOPTS) 2187 return rte_flow_error_set(error, EINVAL, 2188 RTE_FLOW_ERROR_TYPE_ITEM, item, 2189 "IPv6 proto (next header) should " 2190 "not be set as extension header"); 2191 if (item_flags & MLX5_FLOW_LAYER_IPIP) 2192 return rte_flow_error_set(error, EINVAL, 2193 RTE_FLOW_ERROR_TYPE_ITEM, item, 2194 "wrong tunnel type - IPv4 specified " 2195 "but IPv6 item provided"); 2196 if (item_flags & l3m) 2197 return rte_flow_error_set(error, ENOTSUP, 2198 RTE_FLOW_ERROR_TYPE_ITEM, item, 2199 "multiple L3 layers not supported"); 2200 else if (item_flags & l4m) 2201 return rte_flow_error_set(error, EINVAL, 2202 RTE_FLOW_ERROR_TYPE_ITEM, item, 2203 "L3 cannot follow an L4 layer."); 2204 else if ((item_flags & MLX5_FLOW_LAYER_NVGRE) && 2205 !(item_flags & MLX5_FLOW_LAYER_INNER_L2)) 2206 return rte_flow_error_set(error, EINVAL, 2207 RTE_FLOW_ERROR_TYPE_ITEM, item, 2208 "L3 cannot follow an NVGRE layer."); 2209 if (!mask) 2210 mask = &rte_flow_item_ipv6_mask; 2211 ret = mlx5_flow_item_acceptable(item, (const uint8_t *)mask, 2212 acc_mask ? (const uint8_t *)acc_mask 2213 : (const uint8_t *)&nic_mask, 2214 sizeof(struct rte_flow_item_ipv6), 2215 MLX5_ITEM_RANGE_NOT_ACCEPTED, error); 2216 if (ret < 0) 2217 return ret; 2218 return 0; 2219 } 2220 2221 /** 2222 * Validate UDP item. 2223 * 2224 * @param[in] item 2225 * Item specification. 2226 * @param[in] item_flags 2227 * Bit-fields that holds the items detected until now. 2228 * @param[in] target_protocol 2229 * The next protocol in the previous item. 2230 * @param[in] flow_mask 2231 * mlx5 flow-specific (DV, verbs, etc.) supported header fields mask. 2232 * @param[out] error 2233 * Pointer to error structure. 2234 * 2235 * @return 2236 * 0 on success, a negative errno value otherwise and rte_errno is set. 2237 */ 2238 int 2239 mlx5_flow_validate_item_udp(const struct rte_flow_item *item, 2240 uint64_t item_flags, 2241 uint8_t target_protocol, 2242 struct rte_flow_error *error) 2243 { 2244 const struct rte_flow_item_udp *mask = item->mask; 2245 const int tunnel = !!(item_flags & MLX5_FLOW_LAYER_TUNNEL); 2246 const uint64_t l3m = tunnel ? MLX5_FLOW_LAYER_INNER_L3 : 2247 MLX5_FLOW_LAYER_OUTER_L3; 2248 const uint64_t l4m = tunnel ? MLX5_FLOW_LAYER_INNER_L4 : 2249 MLX5_FLOW_LAYER_OUTER_L4; 2250 int ret; 2251 2252 if (target_protocol != 0xff && target_protocol != IPPROTO_UDP) 2253 return rte_flow_error_set(error, EINVAL, 2254 RTE_FLOW_ERROR_TYPE_ITEM, item, 2255 "protocol filtering not compatible" 2256 " with UDP layer"); 2257 if (!(item_flags & l3m)) 2258 return rte_flow_error_set(error, EINVAL, 2259 RTE_FLOW_ERROR_TYPE_ITEM, item, 2260 "L3 is mandatory to filter on L4"); 2261 if (item_flags & l4m) 2262 return rte_flow_error_set(error, EINVAL, 2263 RTE_FLOW_ERROR_TYPE_ITEM, item, 2264 "multiple L4 layers not supported"); 2265 if (!mask) 2266 mask = &rte_flow_item_udp_mask; 2267 ret = mlx5_flow_item_acceptable 2268 (item, (const uint8_t *)mask, 2269 (const uint8_t *)&rte_flow_item_udp_mask, 2270 sizeof(struct rte_flow_item_udp), MLX5_ITEM_RANGE_NOT_ACCEPTED, 2271 error); 2272 if (ret < 0) 2273 return ret; 2274 return 0; 2275 } 2276 2277 /** 2278 * Validate TCP item. 2279 * 2280 * @param[in] item 2281 * Item specification. 2282 * @param[in] item_flags 2283 * Bit-fields that holds the items detected until now. 2284 * @param[in] target_protocol 2285 * The next protocol in the previous item. 2286 * @param[out] error 2287 * Pointer to error structure. 2288 * 2289 * @return 2290 * 0 on success, a negative errno value otherwise and rte_errno is set. 2291 */ 2292 int 2293 mlx5_flow_validate_item_tcp(const struct rte_flow_item *item, 2294 uint64_t item_flags, 2295 uint8_t target_protocol, 2296 const struct rte_flow_item_tcp *flow_mask, 2297 struct rte_flow_error *error) 2298 { 2299 const struct rte_flow_item_tcp *mask = item->mask; 2300 const int tunnel = !!(item_flags & MLX5_FLOW_LAYER_TUNNEL); 2301 const uint64_t l3m = tunnel ? MLX5_FLOW_LAYER_INNER_L3 : 2302 MLX5_FLOW_LAYER_OUTER_L3; 2303 const uint64_t l4m = tunnel ? MLX5_FLOW_LAYER_INNER_L4 : 2304 MLX5_FLOW_LAYER_OUTER_L4; 2305 int ret; 2306 2307 MLX5_ASSERT(flow_mask); 2308 if (target_protocol != 0xff && target_protocol != IPPROTO_TCP) 2309 return rte_flow_error_set(error, EINVAL, 2310 RTE_FLOW_ERROR_TYPE_ITEM, item, 2311 "protocol filtering not compatible" 2312 " with TCP layer"); 2313 if (!(item_flags & l3m)) 2314 return rte_flow_error_set(error, EINVAL, 2315 RTE_FLOW_ERROR_TYPE_ITEM, item, 2316 "L3 is mandatory to filter on L4"); 2317 if (item_flags & l4m) 2318 return rte_flow_error_set(error, EINVAL, 2319 RTE_FLOW_ERROR_TYPE_ITEM, item, 2320 "multiple L4 layers not supported"); 2321 if (!mask) 2322 mask = &rte_flow_item_tcp_mask; 2323 ret = mlx5_flow_item_acceptable 2324 (item, (const uint8_t *)mask, 2325 (const uint8_t *)flow_mask, 2326 sizeof(struct rte_flow_item_tcp), MLX5_ITEM_RANGE_NOT_ACCEPTED, 2327 error); 2328 if (ret < 0) 2329 return ret; 2330 return 0; 2331 } 2332 2333 /** 2334 * Validate VXLAN item. 2335 * 2336 * @param[in] item 2337 * Item specification. 2338 * @param[in] item_flags 2339 * Bit-fields that holds the items detected until now. 2340 * @param[in] target_protocol 2341 * The next protocol in the previous item. 2342 * @param[out] error 2343 * Pointer to error structure. 2344 * 2345 * @return 2346 * 0 on success, a negative errno value otherwise and rte_errno is set. 2347 */ 2348 int 2349 mlx5_flow_validate_item_vxlan(const struct rte_flow_item *item, 2350 uint64_t item_flags, 2351 struct rte_flow_error *error) 2352 { 2353 const struct rte_flow_item_vxlan *spec = item->spec; 2354 const struct rte_flow_item_vxlan *mask = item->mask; 2355 int ret; 2356 union vni { 2357 uint32_t vlan_id; 2358 uint8_t vni[4]; 2359 } id = { .vlan_id = 0, }; 2360 2361 2362 if (item_flags & MLX5_FLOW_LAYER_TUNNEL) 2363 return rte_flow_error_set(error, ENOTSUP, 2364 RTE_FLOW_ERROR_TYPE_ITEM, item, 2365 "multiple tunnel layers not" 2366 " supported"); 2367 /* 2368 * Verify only UDPv4 is present as defined in 2369 * https://tools.ietf.org/html/rfc7348 2370 */ 2371 if (!(item_flags & MLX5_FLOW_LAYER_OUTER_L4_UDP)) 2372 return rte_flow_error_set(error, EINVAL, 2373 RTE_FLOW_ERROR_TYPE_ITEM, item, 2374 "no outer UDP layer found"); 2375 if (!mask) 2376 mask = &rte_flow_item_vxlan_mask; 2377 ret = mlx5_flow_item_acceptable 2378 (item, (const uint8_t *)mask, 2379 (const uint8_t *)&rte_flow_item_vxlan_mask, 2380 sizeof(struct rte_flow_item_vxlan), 2381 MLX5_ITEM_RANGE_NOT_ACCEPTED, error); 2382 if (ret < 0) 2383 return ret; 2384 if (spec) { 2385 memcpy(&id.vni[1], spec->vni, 3); 2386 memcpy(&id.vni[1], mask->vni, 3); 2387 } 2388 if (!(item_flags & MLX5_FLOW_LAYER_OUTER)) 2389 return rte_flow_error_set(error, ENOTSUP, 2390 RTE_FLOW_ERROR_TYPE_ITEM, item, 2391 "VXLAN tunnel must be fully defined"); 2392 return 0; 2393 } 2394 2395 /** 2396 * Validate VXLAN_GPE item. 2397 * 2398 * @param[in] item 2399 * Item specification. 2400 * @param[in] item_flags 2401 * Bit-fields that holds the items detected until now. 2402 * @param[in] priv 2403 * Pointer to the private data structure. 2404 * @param[in] target_protocol 2405 * The next protocol in the previous item. 2406 * @param[out] error 2407 * Pointer to error structure. 2408 * 2409 * @return 2410 * 0 on success, a negative errno value otherwise and rte_errno is set. 2411 */ 2412 int 2413 mlx5_flow_validate_item_vxlan_gpe(const struct rte_flow_item *item, 2414 uint64_t item_flags, 2415 struct rte_eth_dev *dev, 2416 struct rte_flow_error *error) 2417 { 2418 struct mlx5_priv *priv = dev->data->dev_private; 2419 const struct rte_flow_item_vxlan_gpe *spec = item->spec; 2420 const struct rte_flow_item_vxlan_gpe *mask = item->mask; 2421 int ret; 2422 union vni { 2423 uint32_t vlan_id; 2424 uint8_t vni[4]; 2425 } id = { .vlan_id = 0, }; 2426 2427 if (!priv->config.l3_vxlan_en) 2428 return rte_flow_error_set(error, ENOTSUP, 2429 RTE_FLOW_ERROR_TYPE_ITEM, item, 2430 "L3 VXLAN is not enabled by device" 2431 " parameter and/or not configured in" 2432 " firmware"); 2433 if (item_flags & MLX5_FLOW_LAYER_TUNNEL) 2434 return rte_flow_error_set(error, ENOTSUP, 2435 RTE_FLOW_ERROR_TYPE_ITEM, item, 2436 "multiple tunnel layers not" 2437 " supported"); 2438 /* 2439 * Verify only UDPv4 is present as defined in 2440 * https://tools.ietf.org/html/rfc7348 2441 */ 2442 if (!(item_flags & MLX5_FLOW_LAYER_OUTER_L4_UDP)) 2443 return rte_flow_error_set(error, EINVAL, 2444 RTE_FLOW_ERROR_TYPE_ITEM, item, 2445 "no outer UDP layer found"); 2446 if (!mask) 2447 mask = &rte_flow_item_vxlan_gpe_mask; 2448 ret = mlx5_flow_item_acceptable 2449 (item, (const uint8_t *)mask, 2450 (const uint8_t *)&rte_flow_item_vxlan_gpe_mask, 2451 sizeof(struct rte_flow_item_vxlan_gpe), 2452 MLX5_ITEM_RANGE_NOT_ACCEPTED, error); 2453 if (ret < 0) 2454 return ret; 2455 if (spec) { 2456 if (spec->protocol) 2457 return rte_flow_error_set(error, ENOTSUP, 2458 RTE_FLOW_ERROR_TYPE_ITEM, 2459 item, 2460 "VxLAN-GPE protocol" 2461 " not supported"); 2462 memcpy(&id.vni[1], spec->vni, 3); 2463 memcpy(&id.vni[1], mask->vni, 3); 2464 } 2465 if (!(item_flags & MLX5_FLOW_LAYER_OUTER)) 2466 return rte_flow_error_set(error, ENOTSUP, 2467 RTE_FLOW_ERROR_TYPE_ITEM, item, 2468 "VXLAN-GPE tunnel must be fully" 2469 " defined"); 2470 return 0; 2471 } 2472 /** 2473 * Validate GRE Key item. 2474 * 2475 * @param[in] item 2476 * Item specification. 2477 * @param[in] item_flags 2478 * Bit flags to mark detected items. 2479 * @param[in] gre_item 2480 * Pointer to gre_item 2481 * @param[out] error 2482 * Pointer to error structure. 2483 * 2484 * @return 2485 * 0 on success, a negative errno value otherwise and rte_errno is set. 2486 */ 2487 int 2488 mlx5_flow_validate_item_gre_key(const struct rte_flow_item *item, 2489 uint64_t item_flags, 2490 const struct rte_flow_item *gre_item, 2491 struct rte_flow_error *error) 2492 { 2493 const rte_be32_t *mask = item->mask; 2494 int ret = 0; 2495 rte_be32_t gre_key_default_mask = RTE_BE32(UINT32_MAX); 2496 const struct rte_flow_item_gre *gre_spec; 2497 const struct rte_flow_item_gre *gre_mask; 2498 2499 if (item_flags & MLX5_FLOW_LAYER_GRE_KEY) 2500 return rte_flow_error_set(error, ENOTSUP, 2501 RTE_FLOW_ERROR_TYPE_ITEM, item, 2502 "Multiple GRE key not support"); 2503 if (!(item_flags & MLX5_FLOW_LAYER_GRE)) 2504 return rte_flow_error_set(error, ENOTSUP, 2505 RTE_FLOW_ERROR_TYPE_ITEM, item, 2506 "No preceding GRE header"); 2507 if (item_flags & MLX5_FLOW_LAYER_INNER) 2508 return rte_flow_error_set(error, ENOTSUP, 2509 RTE_FLOW_ERROR_TYPE_ITEM, item, 2510 "GRE key following a wrong item"); 2511 gre_mask = gre_item->mask; 2512 if (!gre_mask) 2513 gre_mask = &rte_flow_item_gre_mask; 2514 gre_spec = gre_item->spec; 2515 if (gre_spec && (gre_mask->c_rsvd0_ver & RTE_BE16(0x2000)) && 2516 !(gre_spec->c_rsvd0_ver & RTE_BE16(0x2000))) 2517 return rte_flow_error_set(error, EINVAL, 2518 RTE_FLOW_ERROR_TYPE_ITEM, item, 2519 "Key bit must be on"); 2520 2521 if (!mask) 2522 mask = &gre_key_default_mask; 2523 ret = mlx5_flow_item_acceptable 2524 (item, (const uint8_t *)mask, 2525 (const uint8_t *)&gre_key_default_mask, 2526 sizeof(rte_be32_t), MLX5_ITEM_RANGE_NOT_ACCEPTED, error); 2527 return ret; 2528 } 2529 2530 /** 2531 * Validate GRE item. 2532 * 2533 * @param[in] item 2534 * Item specification. 2535 * @param[in] item_flags 2536 * Bit flags to mark detected items. 2537 * @param[in] target_protocol 2538 * The next protocol in the previous item. 2539 * @param[out] error 2540 * Pointer to error structure. 2541 * 2542 * @return 2543 * 0 on success, a negative errno value otherwise and rte_errno is set. 2544 */ 2545 int 2546 mlx5_flow_validate_item_gre(const struct rte_flow_item *item, 2547 uint64_t item_flags, 2548 uint8_t target_protocol, 2549 struct rte_flow_error *error) 2550 { 2551 const struct rte_flow_item_gre *spec __rte_unused = item->spec; 2552 const struct rte_flow_item_gre *mask = item->mask; 2553 int ret; 2554 const struct rte_flow_item_gre nic_mask = { 2555 .c_rsvd0_ver = RTE_BE16(0xB000), 2556 .protocol = RTE_BE16(UINT16_MAX), 2557 }; 2558 2559 if (target_protocol != 0xff && target_protocol != IPPROTO_GRE) 2560 return rte_flow_error_set(error, EINVAL, 2561 RTE_FLOW_ERROR_TYPE_ITEM, item, 2562 "protocol filtering not compatible" 2563 " with this GRE layer"); 2564 if (item_flags & MLX5_FLOW_LAYER_TUNNEL) 2565 return rte_flow_error_set(error, ENOTSUP, 2566 RTE_FLOW_ERROR_TYPE_ITEM, item, 2567 "multiple tunnel layers not" 2568 " supported"); 2569 if (!(item_flags & MLX5_FLOW_LAYER_OUTER_L3)) 2570 return rte_flow_error_set(error, ENOTSUP, 2571 RTE_FLOW_ERROR_TYPE_ITEM, item, 2572 "L3 Layer is missing"); 2573 if (!mask) 2574 mask = &rte_flow_item_gre_mask; 2575 ret = mlx5_flow_item_acceptable 2576 (item, (const uint8_t *)mask, 2577 (const uint8_t *)&nic_mask, 2578 sizeof(struct rte_flow_item_gre), MLX5_ITEM_RANGE_NOT_ACCEPTED, 2579 error); 2580 if (ret < 0) 2581 return ret; 2582 #ifndef HAVE_MLX5DV_DR 2583 #ifndef HAVE_IBV_DEVICE_MPLS_SUPPORT 2584 if (spec && (spec->protocol & mask->protocol)) 2585 return rte_flow_error_set(error, ENOTSUP, 2586 RTE_FLOW_ERROR_TYPE_ITEM, item, 2587 "without MPLS support the" 2588 " specification cannot be used for" 2589 " filtering"); 2590 #endif 2591 #endif 2592 return 0; 2593 } 2594 2595 /** 2596 * Validate Geneve item. 2597 * 2598 * @param[in] item 2599 * Item specification. 2600 * @param[in] itemFlags 2601 * Bit-fields that holds the items detected until now. 2602 * @param[in] enPriv 2603 * Pointer to the private data structure. 2604 * @param[out] error 2605 * Pointer to error structure. 2606 * 2607 * @return 2608 * 0 on success, a negative errno value otherwise and rte_errno is set. 2609 */ 2610 2611 int 2612 mlx5_flow_validate_item_geneve(const struct rte_flow_item *item, 2613 uint64_t item_flags, 2614 struct rte_eth_dev *dev, 2615 struct rte_flow_error *error) 2616 { 2617 struct mlx5_priv *priv = dev->data->dev_private; 2618 const struct rte_flow_item_geneve *spec = item->spec; 2619 const struct rte_flow_item_geneve *mask = item->mask; 2620 int ret; 2621 uint16_t gbhdr; 2622 uint8_t opt_len = priv->config.hca_attr.geneve_max_opt_len ? 2623 MLX5_GENEVE_OPT_LEN_1 : MLX5_GENEVE_OPT_LEN_0; 2624 const struct rte_flow_item_geneve nic_mask = { 2625 .ver_opt_len_o_c_rsvd0 = RTE_BE16(0x3f80), 2626 .vni = "\xff\xff\xff", 2627 .protocol = RTE_BE16(UINT16_MAX), 2628 }; 2629 2630 if (!priv->config.hca_attr.tunnel_stateless_geneve_rx) 2631 return rte_flow_error_set(error, ENOTSUP, 2632 RTE_FLOW_ERROR_TYPE_ITEM, item, 2633 "L3 Geneve is not enabled by device" 2634 " parameter and/or not configured in" 2635 " firmware"); 2636 if (item_flags & MLX5_FLOW_LAYER_TUNNEL) 2637 return rte_flow_error_set(error, ENOTSUP, 2638 RTE_FLOW_ERROR_TYPE_ITEM, item, 2639 "multiple tunnel layers not" 2640 " supported"); 2641 /* 2642 * Verify only UDPv4 is present as defined in 2643 * https://tools.ietf.org/html/rfc7348 2644 */ 2645 if (!(item_flags & MLX5_FLOW_LAYER_OUTER_L4_UDP)) 2646 return rte_flow_error_set(error, EINVAL, 2647 RTE_FLOW_ERROR_TYPE_ITEM, item, 2648 "no outer UDP layer found"); 2649 if (!mask) 2650 mask = &rte_flow_item_geneve_mask; 2651 ret = mlx5_flow_item_acceptable 2652 (item, (const uint8_t *)mask, 2653 (const uint8_t *)&nic_mask, 2654 sizeof(struct rte_flow_item_geneve), 2655 MLX5_ITEM_RANGE_NOT_ACCEPTED, error); 2656 if (ret) 2657 return ret; 2658 if (spec) { 2659 gbhdr = rte_be_to_cpu_16(spec->ver_opt_len_o_c_rsvd0); 2660 if (MLX5_GENEVE_VER_VAL(gbhdr) || 2661 MLX5_GENEVE_CRITO_VAL(gbhdr) || 2662 MLX5_GENEVE_RSVD_VAL(gbhdr) || spec->rsvd1) 2663 return rte_flow_error_set(error, ENOTSUP, 2664 RTE_FLOW_ERROR_TYPE_ITEM, 2665 item, 2666 "Geneve protocol unsupported" 2667 " fields are being used"); 2668 if (MLX5_GENEVE_OPTLEN_VAL(gbhdr) > opt_len) 2669 return rte_flow_error_set 2670 (error, ENOTSUP, 2671 RTE_FLOW_ERROR_TYPE_ITEM, 2672 item, 2673 "Unsupported Geneve options length"); 2674 } 2675 if (!(item_flags & MLX5_FLOW_LAYER_OUTER)) 2676 return rte_flow_error_set 2677 (error, ENOTSUP, 2678 RTE_FLOW_ERROR_TYPE_ITEM, item, 2679 "Geneve tunnel must be fully defined"); 2680 return 0; 2681 } 2682 2683 /** 2684 * Validate Geneve TLV option item. 2685 * 2686 * @param[in] item 2687 * Item specification. 2688 * @param[in] last_item 2689 * Previous validated item in the pattern items. 2690 * @param[in] geneve_item 2691 * Previous GENEVE item specification. 2692 * @param[in] dev 2693 * Pointer to the rte_eth_dev structure. 2694 * @param[out] error 2695 * Pointer to error structure. 2696 * 2697 * @return 2698 * 0 on success, a negative errno value otherwise and rte_errno is set. 2699 */ 2700 int 2701 mlx5_flow_validate_item_geneve_opt(const struct rte_flow_item *item, 2702 uint64_t last_item, 2703 const struct rte_flow_item *geneve_item, 2704 struct rte_eth_dev *dev, 2705 struct rte_flow_error *error) 2706 { 2707 struct mlx5_priv *priv = dev->data->dev_private; 2708 struct mlx5_dev_ctx_shared *sh = priv->sh; 2709 struct mlx5_geneve_tlv_option_resource *geneve_opt_resource; 2710 struct mlx5_hca_attr *hca_attr = &priv->config.hca_attr; 2711 uint8_t data_max_supported = 2712 hca_attr->max_geneve_tlv_option_data_len * 4; 2713 struct mlx5_dev_config *config = &priv->config; 2714 const struct rte_flow_item_geneve *geneve_spec; 2715 const struct rte_flow_item_geneve *geneve_mask; 2716 const struct rte_flow_item_geneve_opt *spec = item->spec; 2717 const struct rte_flow_item_geneve_opt *mask = item->mask; 2718 unsigned int i; 2719 unsigned int data_len; 2720 uint8_t tlv_option_len; 2721 uint16_t optlen_m, optlen_v; 2722 const struct rte_flow_item_geneve_opt full_mask = { 2723 .option_class = RTE_BE16(0xffff), 2724 .option_type = 0xff, 2725 .option_len = 0x1f, 2726 }; 2727 2728 if (!mask) 2729 mask = &rte_flow_item_geneve_opt_mask; 2730 if (!spec) 2731 return rte_flow_error_set 2732 (error, ENOTSUP, RTE_FLOW_ERROR_TYPE_ITEM, item, 2733 "Geneve TLV opt class/type/length must be specified"); 2734 if ((uint32_t)spec->option_len > MLX5_GENEVE_OPTLEN_MASK) 2735 return rte_flow_error_set 2736 (error, ENOTSUP, RTE_FLOW_ERROR_TYPE_ITEM, item, 2737 "Geneve TLV opt length exceeeds the limit (31)"); 2738 /* Check if class type and length masks are full. */ 2739 if (full_mask.option_class != mask->option_class || 2740 full_mask.option_type != mask->option_type || 2741 full_mask.option_len != (mask->option_len & full_mask.option_len)) 2742 return rte_flow_error_set 2743 (error, ENOTSUP, RTE_FLOW_ERROR_TYPE_ITEM, item, 2744 "Geneve TLV opt class/type/length masks must be full"); 2745 /* Check if length is supported */ 2746 if ((uint32_t)spec->option_len > 2747 config->hca_attr.max_geneve_tlv_option_data_len) 2748 return rte_flow_error_set 2749 (error, ENOTSUP, RTE_FLOW_ERROR_TYPE_ITEM, item, 2750 "Geneve TLV opt length not supported"); 2751 if (config->hca_attr.max_geneve_tlv_options > 1) 2752 DRV_LOG(DEBUG, 2753 "max_geneve_tlv_options supports more than 1 option"); 2754 /* Check GENEVE item preceding. */ 2755 if (!geneve_item || !(last_item & MLX5_FLOW_LAYER_GENEVE)) 2756 return rte_flow_error_set 2757 (error, ENOTSUP, RTE_FLOW_ERROR_TYPE_ITEM, item, 2758 "Geneve opt item must be preceded with Geneve item"); 2759 geneve_spec = geneve_item->spec; 2760 geneve_mask = geneve_item->mask ? geneve_item->mask : 2761 &rte_flow_item_geneve_mask; 2762 /* Check if GENEVE TLV option size doesn't exceed option length */ 2763 if (geneve_spec && (geneve_mask->ver_opt_len_o_c_rsvd0 || 2764 geneve_spec->ver_opt_len_o_c_rsvd0)) { 2765 tlv_option_len = spec->option_len & mask->option_len; 2766 optlen_v = rte_be_to_cpu_16(geneve_spec->ver_opt_len_o_c_rsvd0); 2767 optlen_v = MLX5_GENEVE_OPTLEN_VAL(optlen_v); 2768 optlen_m = rte_be_to_cpu_16(geneve_mask->ver_opt_len_o_c_rsvd0); 2769 optlen_m = MLX5_GENEVE_OPTLEN_VAL(optlen_m); 2770 if ((optlen_v & optlen_m) <= tlv_option_len) 2771 return rte_flow_error_set 2772 (error, ENOTSUP, RTE_FLOW_ERROR_TYPE_ITEM, item, 2773 "GENEVE TLV option length exceeds optlen"); 2774 } 2775 /* Check if length is 0 or data is 0. */ 2776 if (spec->data == NULL || spec->option_len == 0) 2777 return rte_flow_error_set 2778 (error, ENOTSUP, RTE_FLOW_ERROR_TYPE_ITEM, item, 2779 "Geneve TLV opt with zero data/length not supported"); 2780 /* Check not all data & mask are 0. */ 2781 data_len = spec->option_len * 4; 2782 if (mask->data == NULL) { 2783 for (i = 0; i < data_len; i++) 2784 if (spec->data[i]) 2785 break; 2786 if (i == data_len) 2787 return rte_flow_error_set(error, ENOTSUP, 2788 RTE_FLOW_ERROR_TYPE_ITEM, item, 2789 "Can't match on Geneve option data 0"); 2790 } else { 2791 for (i = 0; i < data_len; i++) 2792 if (spec->data[i] & mask->data[i]) 2793 break; 2794 if (i == data_len) 2795 return rte_flow_error_set(error, ENOTSUP, 2796 RTE_FLOW_ERROR_TYPE_ITEM, item, 2797 "Can't match on Geneve option data and mask 0"); 2798 /* Check data mask supported. */ 2799 for (i = data_max_supported; i < data_len ; i++) 2800 if (mask->data[i]) 2801 return rte_flow_error_set(error, ENOTSUP, 2802 RTE_FLOW_ERROR_TYPE_ITEM, item, 2803 "Data mask is of unsupported size"); 2804 } 2805 /* Check GENEVE option is supported in NIC. */ 2806 if (!config->hca_attr.geneve_tlv_opt) 2807 return rte_flow_error_set 2808 (error, ENOTSUP, RTE_FLOW_ERROR_TYPE_ITEM, item, 2809 "Geneve TLV opt not supported"); 2810 /* Check if we already have geneve option with different type/class. */ 2811 rte_spinlock_lock(&sh->geneve_tlv_opt_sl); 2812 geneve_opt_resource = sh->geneve_tlv_option_resource; 2813 if (geneve_opt_resource != NULL) 2814 if (geneve_opt_resource->option_class != spec->option_class || 2815 geneve_opt_resource->option_type != spec->option_type || 2816 geneve_opt_resource->length != spec->option_len) { 2817 rte_spinlock_unlock(&sh->geneve_tlv_opt_sl); 2818 return rte_flow_error_set(error, ENOTSUP, 2819 RTE_FLOW_ERROR_TYPE_ITEM, item, 2820 "Only one Geneve TLV option supported"); 2821 } 2822 rte_spinlock_unlock(&sh->geneve_tlv_opt_sl); 2823 return 0; 2824 } 2825 2826 /** 2827 * Validate MPLS item. 2828 * 2829 * @param[in] dev 2830 * Pointer to the rte_eth_dev structure. 2831 * @param[in] item 2832 * Item specification. 2833 * @param[in] item_flags 2834 * Bit-fields that holds the items detected until now. 2835 * @param[in] prev_layer 2836 * The protocol layer indicated in previous item. 2837 * @param[out] error 2838 * Pointer to error structure. 2839 * 2840 * @return 2841 * 0 on success, a negative errno value otherwise and rte_errno is set. 2842 */ 2843 int 2844 mlx5_flow_validate_item_mpls(struct rte_eth_dev *dev __rte_unused, 2845 const struct rte_flow_item *item __rte_unused, 2846 uint64_t item_flags __rte_unused, 2847 uint64_t prev_layer __rte_unused, 2848 struct rte_flow_error *error) 2849 { 2850 #ifdef HAVE_IBV_DEVICE_MPLS_SUPPORT 2851 const struct rte_flow_item_mpls *mask = item->mask; 2852 struct mlx5_priv *priv = dev->data->dev_private; 2853 int ret; 2854 2855 if (!priv->config.mpls_en) 2856 return rte_flow_error_set(error, ENOTSUP, 2857 RTE_FLOW_ERROR_TYPE_ITEM, item, 2858 "MPLS not supported or" 2859 " disabled in firmware" 2860 " configuration."); 2861 /* MPLS over IP, UDP, GRE is allowed */ 2862 if (!(prev_layer & (MLX5_FLOW_LAYER_OUTER_L3 | 2863 MLX5_FLOW_LAYER_OUTER_L4_UDP | 2864 MLX5_FLOW_LAYER_GRE | 2865 MLX5_FLOW_LAYER_GRE_KEY))) 2866 return rte_flow_error_set(error, EINVAL, 2867 RTE_FLOW_ERROR_TYPE_ITEM, item, 2868 "protocol filtering not compatible" 2869 " with MPLS layer"); 2870 /* Multi-tunnel isn't allowed but MPLS over GRE is an exception. */ 2871 if ((item_flags & MLX5_FLOW_LAYER_TUNNEL) && 2872 !(item_flags & MLX5_FLOW_LAYER_GRE)) 2873 return rte_flow_error_set(error, ENOTSUP, 2874 RTE_FLOW_ERROR_TYPE_ITEM, item, 2875 "multiple tunnel layers not" 2876 " supported"); 2877 if (!mask) 2878 mask = &rte_flow_item_mpls_mask; 2879 ret = mlx5_flow_item_acceptable 2880 (item, (const uint8_t *)mask, 2881 (const uint8_t *)&rte_flow_item_mpls_mask, 2882 sizeof(struct rte_flow_item_mpls), 2883 MLX5_ITEM_RANGE_NOT_ACCEPTED, error); 2884 if (ret < 0) 2885 return ret; 2886 return 0; 2887 #else 2888 return rte_flow_error_set(error, ENOTSUP, 2889 RTE_FLOW_ERROR_TYPE_ITEM, item, 2890 "MPLS is not supported by Verbs, please" 2891 " update."); 2892 #endif 2893 } 2894 2895 /** 2896 * Validate NVGRE item. 2897 * 2898 * @param[in] item 2899 * Item specification. 2900 * @param[in] item_flags 2901 * Bit flags to mark detected items. 2902 * @param[in] target_protocol 2903 * The next protocol in the previous item. 2904 * @param[out] error 2905 * Pointer to error structure. 2906 * 2907 * @return 2908 * 0 on success, a negative errno value otherwise and rte_errno is set. 2909 */ 2910 int 2911 mlx5_flow_validate_item_nvgre(const struct rte_flow_item *item, 2912 uint64_t item_flags, 2913 uint8_t target_protocol, 2914 struct rte_flow_error *error) 2915 { 2916 const struct rte_flow_item_nvgre *mask = item->mask; 2917 int ret; 2918 2919 if (target_protocol != 0xff && target_protocol != IPPROTO_GRE) 2920 return rte_flow_error_set(error, EINVAL, 2921 RTE_FLOW_ERROR_TYPE_ITEM, item, 2922 "protocol filtering not compatible" 2923 " with this GRE layer"); 2924 if (item_flags & MLX5_FLOW_LAYER_TUNNEL) 2925 return rte_flow_error_set(error, ENOTSUP, 2926 RTE_FLOW_ERROR_TYPE_ITEM, item, 2927 "multiple tunnel layers not" 2928 " supported"); 2929 if (!(item_flags & MLX5_FLOW_LAYER_OUTER_L3)) 2930 return rte_flow_error_set(error, ENOTSUP, 2931 RTE_FLOW_ERROR_TYPE_ITEM, item, 2932 "L3 Layer is missing"); 2933 if (!mask) 2934 mask = &rte_flow_item_nvgre_mask; 2935 ret = mlx5_flow_item_acceptable 2936 (item, (const uint8_t *)mask, 2937 (const uint8_t *)&rte_flow_item_nvgre_mask, 2938 sizeof(struct rte_flow_item_nvgre), 2939 MLX5_ITEM_RANGE_NOT_ACCEPTED, error); 2940 if (ret < 0) 2941 return ret; 2942 return 0; 2943 } 2944 2945 /** 2946 * Validate eCPRI item. 2947 * 2948 * @param[in] item 2949 * Item specification. 2950 * @param[in] item_flags 2951 * Bit-fields that holds the items detected until now. 2952 * @param[in] last_item 2953 * Previous validated item in the pattern items. 2954 * @param[in] ether_type 2955 * Type in the ethernet layer header (including dot1q). 2956 * @param[in] acc_mask 2957 * Acceptable mask, if NULL default internal default mask 2958 * will be used to check whether item fields are supported. 2959 * @param[out] error 2960 * Pointer to error structure. 2961 * 2962 * @return 2963 * 0 on success, a negative errno value otherwise and rte_errno is set. 2964 */ 2965 int 2966 mlx5_flow_validate_item_ecpri(const struct rte_flow_item *item, 2967 uint64_t item_flags, 2968 uint64_t last_item, 2969 uint16_t ether_type, 2970 const struct rte_flow_item_ecpri *acc_mask, 2971 struct rte_flow_error *error) 2972 { 2973 const struct rte_flow_item_ecpri *mask = item->mask; 2974 const struct rte_flow_item_ecpri nic_mask = { 2975 .hdr = { 2976 .common = { 2977 .u32 = 2978 RTE_BE32(((const struct rte_ecpri_common_hdr) { 2979 .type = 0xFF, 2980 }).u32), 2981 }, 2982 .dummy[0] = 0xFFFFFFFF, 2983 }, 2984 }; 2985 const uint64_t outer_l2_vlan = (MLX5_FLOW_LAYER_OUTER_L2 | 2986 MLX5_FLOW_LAYER_OUTER_VLAN); 2987 struct rte_flow_item_ecpri mask_lo; 2988 2989 if (!(last_item & outer_l2_vlan) && 2990 last_item != MLX5_FLOW_LAYER_OUTER_L4_UDP) 2991 return rte_flow_error_set(error, EINVAL, 2992 RTE_FLOW_ERROR_TYPE_ITEM, item, 2993 "eCPRI can only follow L2/VLAN layer or UDP layer"); 2994 if ((last_item & outer_l2_vlan) && ether_type && 2995 ether_type != RTE_ETHER_TYPE_ECPRI) 2996 return rte_flow_error_set(error, EINVAL, 2997 RTE_FLOW_ERROR_TYPE_ITEM, item, 2998 "eCPRI cannot follow L2/VLAN layer which ether type is not 0xAEFE"); 2999 if (item_flags & MLX5_FLOW_LAYER_TUNNEL) 3000 return rte_flow_error_set(error, EINVAL, 3001 RTE_FLOW_ERROR_TYPE_ITEM, item, 3002 "eCPRI with tunnel is not supported right now"); 3003 if (item_flags & MLX5_FLOW_LAYER_OUTER_L3) 3004 return rte_flow_error_set(error, ENOTSUP, 3005 RTE_FLOW_ERROR_TYPE_ITEM, item, 3006 "multiple L3 layers not supported"); 3007 else if (item_flags & MLX5_FLOW_LAYER_OUTER_L4_TCP) 3008 return rte_flow_error_set(error, EINVAL, 3009 RTE_FLOW_ERROR_TYPE_ITEM, item, 3010 "eCPRI cannot coexist with a TCP layer"); 3011 /* In specification, eCPRI could be over UDP layer. */ 3012 else if (item_flags & MLX5_FLOW_LAYER_OUTER_L4_UDP) 3013 return rte_flow_error_set(error, EINVAL, 3014 RTE_FLOW_ERROR_TYPE_ITEM, item, 3015 "eCPRI over UDP layer is not yet supported right now"); 3016 /* Mask for type field in common header could be zero. */ 3017 if (!mask) 3018 mask = &rte_flow_item_ecpri_mask; 3019 mask_lo.hdr.common.u32 = rte_be_to_cpu_32(mask->hdr.common.u32); 3020 /* Input mask is in big-endian format. */ 3021 if (mask_lo.hdr.common.type != 0 && mask_lo.hdr.common.type != 0xff) 3022 return rte_flow_error_set(error, EINVAL, 3023 RTE_FLOW_ERROR_TYPE_ITEM_MASK, mask, 3024 "partial mask is not supported for protocol"); 3025 else if (mask_lo.hdr.common.type == 0 && mask->hdr.dummy[0] != 0) 3026 return rte_flow_error_set(error, EINVAL, 3027 RTE_FLOW_ERROR_TYPE_ITEM_MASK, mask, 3028 "message header mask must be after a type mask"); 3029 return mlx5_flow_item_acceptable(item, (const uint8_t *)mask, 3030 acc_mask ? (const uint8_t *)acc_mask 3031 : (const uint8_t *)&nic_mask, 3032 sizeof(struct rte_flow_item_ecpri), 3033 MLX5_ITEM_RANGE_NOT_ACCEPTED, error); 3034 } 3035 3036 /** 3037 * Release resource related QUEUE/RSS action split. 3038 * 3039 * @param dev 3040 * Pointer to Ethernet device. 3041 * @param flow 3042 * Flow to release id's from. 3043 */ 3044 static void 3045 flow_mreg_split_qrss_release(struct rte_eth_dev *dev, 3046 struct rte_flow *flow) 3047 { 3048 struct mlx5_priv *priv = dev->data->dev_private; 3049 uint32_t handle_idx; 3050 struct mlx5_flow_handle *dev_handle; 3051 3052 SILIST_FOREACH(priv->sh->ipool[MLX5_IPOOL_MLX5_FLOW], flow->dev_handles, 3053 handle_idx, dev_handle, next) 3054 if (dev_handle->split_flow_id) 3055 mlx5_ipool_free(priv->sh->ipool 3056 [MLX5_IPOOL_RSS_EXPANTION_FLOW_ID], 3057 dev_handle->split_flow_id); 3058 } 3059 3060 static int 3061 flow_null_validate(struct rte_eth_dev *dev __rte_unused, 3062 const struct rte_flow_attr *attr __rte_unused, 3063 const struct rte_flow_item items[] __rte_unused, 3064 const struct rte_flow_action actions[] __rte_unused, 3065 bool external __rte_unused, 3066 int hairpin __rte_unused, 3067 struct rte_flow_error *error) 3068 { 3069 return rte_flow_error_set(error, ENOTSUP, 3070 RTE_FLOW_ERROR_TYPE_UNSPECIFIED, NULL, NULL); 3071 } 3072 3073 static struct mlx5_flow * 3074 flow_null_prepare(struct rte_eth_dev *dev __rte_unused, 3075 const struct rte_flow_attr *attr __rte_unused, 3076 const struct rte_flow_item items[] __rte_unused, 3077 const struct rte_flow_action actions[] __rte_unused, 3078 struct rte_flow_error *error) 3079 { 3080 rte_flow_error_set(error, ENOTSUP, 3081 RTE_FLOW_ERROR_TYPE_UNSPECIFIED, NULL, NULL); 3082 return NULL; 3083 } 3084 3085 static int 3086 flow_null_translate(struct rte_eth_dev *dev __rte_unused, 3087 struct mlx5_flow *dev_flow __rte_unused, 3088 const struct rte_flow_attr *attr __rte_unused, 3089 const struct rte_flow_item items[] __rte_unused, 3090 const struct rte_flow_action actions[] __rte_unused, 3091 struct rte_flow_error *error) 3092 { 3093 return rte_flow_error_set(error, ENOTSUP, 3094 RTE_FLOW_ERROR_TYPE_UNSPECIFIED, NULL, NULL); 3095 } 3096 3097 static int 3098 flow_null_apply(struct rte_eth_dev *dev __rte_unused, 3099 struct rte_flow *flow __rte_unused, 3100 struct rte_flow_error *error) 3101 { 3102 return rte_flow_error_set(error, ENOTSUP, 3103 RTE_FLOW_ERROR_TYPE_UNSPECIFIED, NULL, NULL); 3104 } 3105 3106 static void 3107 flow_null_remove(struct rte_eth_dev *dev __rte_unused, 3108 struct rte_flow *flow __rte_unused) 3109 { 3110 } 3111 3112 static void 3113 flow_null_destroy(struct rte_eth_dev *dev __rte_unused, 3114 struct rte_flow *flow __rte_unused) 3115 { 3116 } 3117 3118 static int 3119 flow_null_query(struct rte_eth_dev *dev __rte_unused, 3120 struct rte_flow *flow __rte_unused, 3121 const struct rte_flow_action *actions __rte_unused, 3122 void *data __rte_unused, 3123 struct rte_flow_error *error) 3124 { 3125 return rte_flow_error_set(error, ENOTSUP, 3126 RTE_FLOW_ERROR_TYPE_UNSPECIFIED, NULL, NULL); 3127 } 3128 3129 static int 3130 flow_null_sync_domain(struct rte_eth_dev *dev __rte_unused, 3131 uint32_t domains __rte_unused, 3132 uint32_t flags __rte_unused) 3133 { 3134 return 0; 3135 } 3136 3137 /* Void driver to protect from null pointer reference. */ 3138 const struct mlx5_flow_driver_ops mlx5_flow_null_drv_ops = { 3139 .validate = flow_null_validate, 3140 .prepare = flow_null_prepare, 3141 .translate = flow_null_translate, 3142 .apply = flow_null_apply, 3143 .remove = flow_null_remove, 3144 .destroy = flow_null_destroy, 3145 .query = flow_null_query, 3146 .sync_domain = flow_null_sync_domain, 3147 }; 3148 3149 /** 3150 * Select flow driver type according to flow attributes and device 3151 * configuration. 3152 * 3153 * @param[in] dev 3154 * Pointer to the dev structure. 3155 * @param[in] attr 3156 * Pointer to the flow attributes. 3157 * 3158 * @return 3159 * flow driver type, MLX5_FLOW_TYPE_MAX otherwise. 3160 */ 3161 static enum mlx5_flow_drv_type 3162 flow_get_drv_type(struct rte_eth_dev *dev, const struct rte_flow_attr *attr) 3163 { 3164 struct mlx5_priv *priv = dev->data->dev_private; 3165 /* The OS can determine first a specific flow type (DV, VERBS) */ 3166 enum mlx5_flow_drv_type type = mlx5_flow_os_get_type(); 3167 3168 if (type != MLX5_FLOW_TYPE_MAX) 3169 return type; 3170 /* If no OS specific type - continue with DV/VERBS selection */ 3171 if (attr->transfer && priv->config.dv_esw_en) 3172 type = MLX5_FLOW_TYPE_DV; 3173 if (!attr->transfer) 3174 type = priv->config.dv_flow_en ? MLX5_FLOW_TYPE_DV : 3175 MLX5_FLOW_TYPE_VERBS; 3176 return type; 3177 } 3178 3179 #define flow_get_drv_ops(type) flow_drv_ops[type] 3180 3181 /** 3182 * Flow driver validation API. This abstracts calling driver specific functions. 3183 * The type of flow driver is determined according to flow attributes. 3184 * 3185 * @param[in] dev 3186 * Pointer to the dev structure. 3187 * @param[in] attr 3188 * Pointer to the flow attributes. 3189 * @param[in] items 3190 * Pointer to the list of items. 3191 * @param[in] actions 3192 * Pointer to the list of actions. 3193 * @param[in] external 3194 * This flow rule is created by request external to PMD. 3195 * @param[in] hairpin 3196 * Number of hairpin TX actions, 0 means classic flow. 3197 * @param[out] error 3198 * Pointer to the error structure. 3199 * 3200 * @return 3201 * 0 on success, a negative errno value otherwise and rte_errno is set. 3202 */ 3203 static inline int 3204 flow_drv_validate(struct rte_eth_dev *dev, 3205 const struct rte_flow_attr *attr, 3206 const struct rte_flow_item items[], 3207 const struct rte_flow_action actions[], 3208 bool external, int hairpin, struct rte_flow_error *error) 3209 { 3210 const struct mlx5_flow_driver_ops *fops; 3211 enum mlx5_flow_drv_type type = flow_get_drv_type(dev, attr); 3212 3213 fops = flow_get_drv_ops(type); 3214 return fops->validate(dev, attr, items, actions, external, 3215 hairpin, error); 3216 } 3217 3218 /** 3219 * Flow driver preparation API. This abstracts calling driver specific 3220 * functions. Parent flow (rte_flow) should have driver type (drv_type). It 3221 * calculates the size of memory required for device flow, allocates the memory, 3222 * initializes the device flow and returns the pointer. 3223 * 3224 * @note 3225 * This function initializes device flow structure such as dv or verbs in 3226 * struct mlx5_flow. However, it is caller's responsibility to initialize the 3227 * rest. For example, adding returning device flow to flow->dev_flow list and 3228 * setting backward reference to the flow should be done out of this function. 3229 * layers field is not filled either. 3230 * 3231 * @param[in] dev 3232 * Pointer to the dev structure. 3233 * @param[in] attr 3234 * Pointer to the flow attributes. 3235 * @param[in] items 3236 * Pointer to the list of items. 3237 * @param[in] actions 3238 * Pointer to the list of actions. 3239 * @param[in] flow_idx 3240 * This memory pool index to the flow. 3241 * @param[out] error 3242 * Pointer to the error structure. 3243 * 3244 * @return 3245 * Pointer to device flow on success, otherwise NULL and rte_errno is set. 3246 */ 3247 static inline struct mlx5_flow * 3248 flow_drv_prepare(struct rte_eth_dev *dev, 3249 const struct rte_flow *flow, 3250 const struct rte_flow_attr *attr, 3251 const struct rte_flow_item items[], 3252 const struct rte_flow_action actions[], 3253 uint32_t flow_idx, 3254 struct rte_flow_error *error) 3255 { 3256 const struct mlx5_flow_driver_ops *fops; 3257 enum mlx5_flow_drv_type type = flow->drv_type; 3258 struct mlx5_flow *mlx5_flow = NULL; 3259 3260 MLX5_ASSERT(type > MLX5_FLOW_TYPE_MIN && type < MLX5_FLOW_TYPE_MAX); 3261 fops = flow_get_drv_ops(type); 3262 mlx5_flow = fops->prepare(dev, attr, items, actions, error); 3263 if (mlx5_flow) 3264 mlx5_flow->flow_idx = flow_idx; 3265 return mlx5_flow; 3266 } 3267 3268 /** 3269 * Flow driver translation API. This abstracts calling driver specific 3270 * functions. Parent flow (rte_flow) should have driver type (drv_type). It 3271 * translates a generic flow into a driver flow. flow_drv_prepare() must 3272 * precede. 3273 * 3274 * @note 3275 * dev_flow->layers could be filled as a result of parsing during translation 3276 * if needed by flow_drv_apply(). dev_flow->flow->actions can also be filled 3277 * if necessary. As a flow can have multiple dev_flows by RSS flow expansion, 3278 * flow->actions could be overwritten even though all the expanded dev_flows 3279 * have the same actions. 3280 * 3281 * @param[in] dev 3282 * Pointer to the rte dev structure. 3283 * @param[in, out] dev_flow 3284 * Pointer to the mlx5 flow. 3285 * @param[in] attr 3286 * Pointer to the flow attributes. 3287 * @param[in] items 3288 * Pointer to the list of items. 3289 * @param[in] actions 3290 * Pointer to the list of actions. 3291 * @param[out] error 3292 * Pointer to the error structure. 3293 * 3294 * @return 3295 * 0 on success, a negative errno value otherwise and rte_errno is set. 3296 */ 3297 static inline int 3298 flow_drv_translate(struct rte_eth_dev *dev, struct mlx5_flow *dev_flow, 3299 const struct rte_flow_attr *attr, 3300 const struct rte_flow_item items[], 3301 const struct rte_flow_action actions[], 3302 struct rte_flow_error *error) 3303 { 3304 const struct mlx5_flow_driver_ops *fops; 3305 enum mlx5_flow_drv_type type = dev_flow->flow->drv_type; 3306 3307 MLX5_ASSERT(type > MLX5_FLOW_TYPE_MIN && type < MLX5_FLOW_TYPE_MAX); 3308 fops = flow_get_drv_ops(type); 3309 return fops->translate(dev, dev_flow, attr, items, actions, error); 3310 } 3311 3312 /** 3313 * Flow driver apply API. This abstracts calling driver specific functions. 3314 * Parent flow (rte_flow) should have driver type (drv_type). It applies 3315 * translated driver flows on to device. flow_drv_translate() must precede. 3316 * 3317 * @param[in] dev 3318 * Pointer to Ethernet device structure. 3319 * @param[in, out] flow 3320 * Pointer to flow structure. 3321 * @param[out] error 3322 * Pointer to error structure. 3323 * 3324 * @return 3325 * 0 on success, a negative errno value otherwise and rte_errno is set. 3326 */ 3327 static inline int 3328 flow_drv_apply(struct rte_eth_dev *dev, struct rte_flow *flow, 3329 struct rte_flow_error *error) 3330 { 3331 const struct mlx5_flow_driver_ops *fops; 3332 enum mlx5_flow_drv_type type = flow->drv_type; 3333 3334 MLX5_ASSERT(type > MLX5_FLOW_TYPE_MIN && type < MLX5_FLOW_TYPE_MAX); 3335 fops = flow_get_drv_ops(type); 3336 return fops->apply(dev, flow, error); 3337 } 3338 3339 /** 3340 * Flow driver destroy API. This abstracts calling driver specific functions. 3341 * Parent flow (rte_flow) should have driver type (drv_type). It removes a flow 3342 * on device and releases resources of the flow. 3343 * 3344 * @param[in] dev 3345 * Pointer to Ethernet device. 3346 * @param[in, out] flow 3347 * Pointer to flow structure. 3348 */ 3349 static inline void 3350 flow_drv_destroy(struct rte_eth_dev *dev, struct rte_flow *flow) 3351 { 3352 const struct mlx5_flow_driver_ops *fops; 3353 enum mlx5_flow_drv_type type = flow->drv_type; 3354 3355 flow_mreg_split_qrss_release(dev, flow); 3356 MLX5_ASSERT(type > MLX5_FLOW_TYPE_MIN && type < MLX5_FLOW_TYPE_MAX); 3357 fops = flow_get_drv_ops(type); 3358 fops->destroy(dev, flow); 3359 } 3360 3361 /** 3362 * Get RSS action from the action list. 3363 * 3364 * @param[in] actions 3365 * Pointer to the list of actions. 3366 * 3367 * @return 3368 * Pointer to the RSS action if exist, else return NULL. 3369 */ 3370 static const struct rte_flow_action_rss* 3371 flow_get_rss_action(const struct rte_flow_action actions[]) 3372 { 3373 const struct rte_flow_action_rss *rss = NULL; 3374 3375 for (; actions->type != RTE_FLOW_ACTION_TYPE_END; actions++) { 3376 switch (actions->type) { 3377 case RTE_FLOW_ACTION_TYPE_RSS: 3378 rss = actions->conf; 3379 break; 3380 case RTE_FLOW_ACTION_TYPE_SAMPLE: 3381 { 3382 const struct rte_flow_action_sample *sample = 3383 actions->conf; 3384 const struct rte_flow_action *act = sample->actions; 3385 for (; act->type != RTE_FLOW_ACTION_TYPE_END; act++) 3386 if (act->type == RTE_FLOW_ACTION_TYPE_RSS) 3387 rss = act->conf; 3388 break; 3389 } 3390 default: 3391 break; 3392 } 3393 } 3394 return rss; 3395 } 3396 3397 /** 3398 * Get ASO age action by index. 3399 * 3400 * @param[in] dev 3401 * Pointer to the Ethernet device structure. 3402 * @param[in] age_idx 3403 * Index to the ASO age action. 3404 * 3405 * @return 3406 * The specified ASO age action. 3407 */ 3408 struct mlx5_aso_age_action* 3409 flow_aso_age_get_by_idx(struct rte_eth_dev *dev, uint32_t age_idx) 3410 { 3411 uint16_t pool_idx = age_idx & UINT16_MAX; 3412 uint16_t offset = (age_idx >> 16) & UINT16_MAX; 3413 struct mlx5_priv *priv = dev->data->dev_private; 3414 struct mlx5_aso_age_mng *mng = priv->sh->aso_age_mng; 3415 struct mlx5_aso_age_pool *pool = mng->pools[pool_idx]; 3416 3417 return &pool->actions[offset - 1]; 3418 } 3419 3420 /* maps shared action to translated non shared in some actions array */ 3421 struct mlx5_translated_shared_action { 3422 struct rte_flow_shared_action *action; /**< Shared action */ 3423 int index; /**< Index in related array of rte_flow_action */ 3424 }; 3425 3426 /** 3427 * Translates actions of type RTE_FLOW_ACTION_TYPE_SHARED to related 3428 * non shared action if translation possible. 3429 * This functionality used to run same execution path for both shared & non 3430 * shared actions on flow create. All necessary preparations for shared 3431 * action handling should be preformed on *shared* actions list returned 3432 * from this call. 3433 * 3434 * @param[in] dev 3435 * Pointer to Ethernet device. 3436 * @param[in] actions 3437 * List of actions to translate. 3438 * @param[out] shared 3439 * List to store translated shared actions. 3440 * @param[in, out] shared_n 3441 * Size of *shared* array. On return should be updated with number of shared 3442 * actions retrieved from the *actions* list. 3443 * @param[out] translated_actions 3444 * List of actions where all shared actions were translated to non shared 3445 * if possible. NULL if no translation took place. 3446 * @param[out] error 3447 * Pointer to the error structure. 3448 * 3449 * @return 3450 * 0 on success, a negative errno value otherwise and rte_errno is set. 3451 */ 3452 static int 3453 flow_shared_actions_translate(struct rte_eth_dev *dev, 3454 const struct rte_flow_action actions[], 3455 struct mlx5_translated_shared_action *shared, 3456 int *shared_n, 3457 struct rte_flow_action **translated_actions, 3458 struct rte_flow_error *error) 3459 { 3460 struct mlx5_priv *priv = dev->data->dev_private; 3461 struct rte_flow_action *translated = NULL; 3462 size_t actions_size; 3463 int n; 3464 int copied_n = 0; 3465 struct mlx5_translated_shared_action *shared_end = NULL; 3466 3467 for (n = 0; actions[n].type != RTE_FLOW_ACTION_TYPE_END; n++) { 3468 if (actions[n].type != RTE_FLOW_ACTION_TYPE_SHARED) 3469 continue; 3470 if (copied_n == *shared_n) { 3471 return rte_flow_error_set 3472 (error, EINVAL, RTE_FLOW_ERROR_TYPE_ACTION_NUM, 3473 NULL, "too many shared actions"); 3474 } 3475 rte_memcpy(&shared[copied_n].action, &actions[n].conf, 3476 sizeof(actions[n].conf)); 3477 shared[copied_n].index = n; 3478 copied_n++; 3479 } 3480 n++; 3481 *shared_n = copied_n; 3482 if (!copied_n) 3483 return 0; 3484 actions_size = sizeof(struct rte_flow_action) * n; 3485 translated = mlx5_malloc(MLX5_MEM_ZERO, actions_size, 0, SOCKET_ID_ANY); 3486 if (!translated) { 3487 rte_errno = ENOMEM; 3488 return -ENOMEM; 3489 } 3490 memcpy(translated, actions, actions_size); 3491 for (shared_end = shared + copied_n; shared < shared_end; shared++) { 3492 struct mlx5_shared_action_rss *shared_rss; 3493 uint32_t act_idx = (uint32_t)(uintptr_t)shared->action; 3494 uint32_t type = act_idx >> MLX5_SHARED_ACTION_TYPE_OFFSET; 3495 uint32_t idx = act_idx & ((1u << MLX5_SHARED_ACTION_TYPE_OFFSET) 3496 - 1); 3497 3498 switch (type) { 3499 case MLX5_SHARED_ACTION_TYPE_RSS: 3500 shared_rss = mlx5_ipool_get 3501 (priv->sh->ipool[MLX5_IPOOL_RSS_SHARED_ACTIONS], idx); 3502 translated[shared->index].type = 3503 RTE_FLOW_ACTION_TYPE_RSS; 3504 translated[shared->index].conf = 3505 &shared_rss->origin; 3506 break; 3507 case MLX5_SHARED_ACTION_TYPE_AGE: 3508 if (priv->sh->flow_hit_aso_en) { 3509 translated[shared->index].type = 3510 (enum rte_flow_action_type) 3511 MLX5_RTE_FLOW_ACTION_TYPE_AGE; 3512 translated[shared->index].conf = 3513 (void *)(uintptr_t)idx; 3514 break; 3515 } 3516 /* Fall-through */ 3517 default: 3518 mlx5_free(translated); 3519 return rte_flow_error_set 3520 (error, EINVAL, RTE_FLOW_ERROR_TYPE_ACTION, 3521 NULL, "invalid shared action type"); 3522 } 3523 } 3524 *translated_actions = translated; 3525 return 0; 3526 } 3527 3528 /** 3529 * Get Shared RSS action from the action list. 3530 * 3531 * @param[in] dev 3532 * Pointer to Ethernet device. 3533 * @param[in] shared 3534 * Pointer to the list of actions. 3535 * @param[in] shared_n 3536 * Actions list length. 3537 * 3538 * @return 3539 * The MLX5 RSS action ID if exists, otherwise return 0. 3540 */ 3541 static uint32_t 3542 flow_get_shared_rss_action(struct rte_eth_dev *dev, 3543 struct mlx5_translated_shared_action *shared, 3544 int shared_n) 3545 { 3546 struct mlx5_translated_shared_action *shared_end; 3547 struct mlx5_priv *priv = dev->data->dev_private; 3548 struct mlx5_shared_action_rss *shared_rss; 3549 3550 3551 for (shared_end = shared + shared_n; shared < shared_end; shared++) { 3552 uint32_t act_idx = (uint32_t)(uintptr_t)shared->action; 3553 uint32_t type = act_idx >> MLX5_SHARED_ACTION_TYPE_OFFSET; 3554 uint32_t idx = act_idx & 3555 ((1u << MLX5_SHARED_ACTION_TYPE_OFFSET) - 1); 3556 switch (type) { 3557 case MLX5_SHARED_ACTION_TYPE_RSS: 3558 shared_rss = mlx5_ipool_get 3559 (priv->sh->ipool[MLX5_IPOOL_RSS_SHARED_ACTIONS], 3560 idx); 3561 __atomic_add_fetch(&shared_rss->refcnt, 1, 3562 __ATOMIC_RELAXED); 3563 return idx; 3564 default: 3565 break; 3566 } 3567 } 3568 return 0; 3569 } 3570 3571 static unsigned int 3572 find_graph_root(const struct rte_flow_item pattern[], uint32_t rss_level) 3573 { 3574 const struct rte_flow_item *item; 3575 unsigned int has_vlan = 0; 3576 3577 for (item = pattern; item->type != RTE_FLOW_ITEM_TYPE_END; item++) { 3578 if (item->type == RTE_FLOW_ITEM_TYPE_VLAN) { 3579 has_vlan = 1; 3580 break; 3581 } 3582 } 3583 if (has_vlan) 3584 return rss_level < 2 ? MLX5_EXPANSION_ROOT_ETH_VLAN : 3585 MLX5_EXPANSION_ROOT_OUTER_ETH_VLAN; 3586 return rss_level < 2 ? MLX5_EXPANSION_ROOT : 3587 MLX5_EXPANSION_ROOT_OUTER; 3588 } 3589 3590 /** 3591 * Get layer flags from the prefix flow. 3592 * 3593 * Some flows may be split to several subflows, the prefix subflow gets the 3594 * match items and the suffix sub flow gets the actions. 3595 * Some actions need the user defined match item flags to get the detail for 3596 * the action. 3597 * This function helps the suffix flow to get the item layer flags from prefix 3598 * subflow. 3599 * 3600 * @param[in] dev_flow 3601 * Pointer the created preifx subflow. 3602 * 3603 * @return 3604 * The layers get from prefix subflow. 3605 */ 3606 static inline uint64_t 3607 flow_get_prefix_layer_flags(struct mlx5_flow *dev_flow) 3608 { 3609 uint64_t layers = 0; 3610 3611 /* 3612 * Layers bits could be localization, but usually the compiler will 3613 * help to do the optimization work for source code. 3614 * If no decap actions, use the layers directly. 3615 */ 3616 if (!(dev_flow->act_flags & MLX5_FLOW_ACTION_DECAP)) 3617 return dev_flow->handle->layers; 3618 /* Convert L3 layers with decap action. */ 3619 if (dev_flow->handle->layers & MLX5_FLOW_LAYER_INNER_L3_IPV4) 3620 layers |= MLX5_FLOW_LAYER_OUTER_L3_IPV4; 3621 else if (dev_flow->handle->layers & MLX5_FLOW_LAYER_INNER_L3_IPV6) 3622 layers |= MLX5_FLOW_LAYER_OUTER_L3_IPV6; 3623 /* Convert L4 layers with decap action. */ 3624 if (dev_flow->handle->layers & MLX5_FLOW_LAYER_INNER_L4_TCP) 3625 layers |= MLX5_FLOW_LAYER_OUTER_L4_TCP; 3626 else if (dev_flow->handle->layers & MLX5_FLOW_LAYER_INNER_L4_UDP) 3627 layers |= MLX5_FLOW_LAYER_OUTER_L4_UDP; 3628 return layers; 3629 } 3630 3631 /** 3632 * Get metadata split action information. 3633 * 3634 * @param[in] actions 3635 * Pointer to the list of actions. 3636 * @param[out] qrss 3637 * Pointer to the return pointer. 3638 * @param[out] qrss_type 3639 * Pointer to the action type to return. RTE_FLOW_ACTION_TYPE_END is returned 3640 * if no QUEUE/RSS is found. 3641 * @param[out] encap_idx 3642 * Pointer to the index of the encap action if exists, otherwise the last 3643 * action index. 3644 * 3645 * @return 3646 * Total number of actions. 3647 */ 3648 static int 3649 flow_parse_metadata_split_actions_info(const struct rte_flow_action actions[], 3650 const struct rte_flow_action **qrss, 3651 int *encap_idx) 3652 { 3653 const struct rte_flow_action_raw_encap *raw_encap; 3654 int actions_n = 0; 3655 int raw_decap_idx = -1; 3656 3657 *encap_idx = -1; 3658 for (; actions->type != RTE_FLOW_ACTION_TYPE_END; actions++) { 3659 switch (actions->type) { 3660 case RTE_FLOW_ACTION_TYPE_VXLAN_ENCAP: 3661 case RTE_FLOW_ACTION_TYPE_NVGRE_ENCAP: 3662 *encap_idx = actions_n; 3663 break; 3664 case RTE_FLOW_ACTION_TYPE_RAW_DECAP: 3665 raw_decap_idx = actions_n; 3666 break; 3667 case RTE_FLOW_ACTION_TYPE_RAW_ENCAP: 3668 raw_encap = actions->conf; 3669 if (raw_encap->size > MLX5_ENCAPSULATION_DECISION_SIZE) 3670 *encap_idx = raw_decap_idx != -1 ? 3671 raw_decap_idx : actions_n; 3672 break; 3673 case RTE_FLOW_ACTION_TYPE_QUEUE: 3674 case RTE_FLOW_ACTION_TYPE_RSS: 3675 *qrss = actions; 3676 break; 3677 default: 3678 break; 3679 } 3680 actions_n++; 3681 } 3682 if (*encap_idx == -1) 3683 *encap_idx = actions_n; 3684 /* Count RTE_FLOW_ACTION_TYPE_END. */ 3685 return actions_n + 1; 3686 } 3687 3688 /** 3689 * Check meter action from the action list. 3690 * 3691 * @param[in] actions 3692 * Pointer to the list of actions. 3693 * @param[out] mtr 3694 * Pointer to the meter exist flag. 3695 * 3696 * @return 3697 * Total number of actions. 3698 */ 3699 static int 3700 flow_check_meter_action(const struct rte_flow_action actions[], uint32_t *mtr) 3701 { 3702 int actions_n = 0; 3703 3704 MLX5_ASSERT(mtr); 3705 *mtr = 0; 3706 for (; actions->type != RTE_FLOW_ACTION_TYPE_END; actions++) { 3707 switch (actions->type) { 3708 case RTE_FLOW_ACTION_TYPE_METER: 3709 *mtr = 1; 3710 break; 3711 default: 3712 break; 3713 } 3714 actions_n++; 3715 } 3716 /* Count RTE_FLOW_ACTION_TYPE_END. */ 3717 return actions_n + 1; 3718 } 3719 3720 /** 3721 * Check if the flow should be split due to hairpin. 3722 * The reason for the split is that in current HW we can't 3723 * support encap and push-vlan on Rx, so if a flow contains 3724 * these actions we move it to Tx. 3725 * 3726 * @param dev 3727 * Pointer to Ethernet device. 3728 * @param[in] attr 3729 * Flow rule attributes. 3730 * @param[in] actions 3731 * Associated actions (list terminated by the END action). 3732 * 3733 * @return 3734 * > 0 the number of actions and the flow should be split, 3735 * 0 when no split required. 3736 */ 3737 static int 3738 flow_check_hairpin_split(struct rte_eth_dev *dev, 3739 const struct rte_flow_attr *attr, 3740 const struct rte_flow_action actions[]) 3741 { 3742 int queue_action = 0; 3743 int action_n = 0; 3744 int split = 0; 3745 const struct rte_flow_action_queue *queue; 3746 const struct rte_flow_action_rss *rss; 3747 const struct rte_flow_action_raw_encap *raw_encap; 3748 const struct rte_eth_hairpin_conf *conf; 3749 3750 if (!attr->ingress) 3751 return 0; 3752 for (; actions->type != RTE_FLOW_ACTION_TYPE_END; actions++) { 3753 switch (actions->type) { 3754 case RTE_FLOW_ACTION_TYPE_QUEUE: 3755 queue = actions->conf; 3756 if (queue == NULL) 3757 return 0; 3758 conf = mlx5_rxq_get_hairpin_conf(dev, queue->index); 3759 if (conf == NULL || conf->tx_explicit != 0) 3760 return 0; 3761 queue_action = 1; 3762 action_n++; 3763 break; 3764 case RTE_FLOW_ACTION_TYPE_RSS: 3765 rss = actions->conf; 3766 if (rss == NULL || rss->queue_num == 0) 3767 return 0; 3768 conf = mlx5_rxq_get_hairpin_conf(dev, rss->queue[0]); 3769 if (conf == NULL || conf->tx_explicit != 0) 3770 return 0; 3771 queue_action = 1; 3772 action_n++; 3773 break; 3774 case RTE_FLOW_ACTION_TYPE_VXLAN_ENCAP: 3775 case RTE_FLOW_ACTION_TYPE_NVGRE_ENCAP: 3776 case RTE_FLOW_ACTION_TYPE_OF_PUSH_VLAN: 3777 case RTE_FLOW_ACTION_TYPE_OF_SET_VLAN_VID: 3778 case RTE_FLOW_ACTION_TYPE_OF_SET_VLAN_PCP: 3779 split++; 3780 action_n++; 3781 break; 3782 case RTE_FLOW_ACTION_TYPE_RAW_ENCAP: 3783 raw_encap = actions->conf; 3784 if (raw_encap->size > MLX5_ENCAPSULATION_DECISION_SIZE) 3785 split++; 3786 action_n++; 3787 break; 3788 default: 3789 action_n++; 3790 break; 3791 } 3792 } 3793 if (split && queue_action) 3794 return action_n; 3795 return 0; 3796 } 3797 3798 /* Declare flow create/destroy prototype in advance. */ 3799 static uint32_t 3800 flow_list_create(struct rte_eth_dev *dev, uint32_t *list, 3801 const struct rte_flow_attr *attr, 3802 const struct rte_flow_item items[], 3803 const struct rte_flow_action actions[], 3804 bool external, struct rte_flow_error *error); 3805 3806 static void 3807 flow_list_destroy(struct rte_eth_dev *dev, uint32_t *list, 3808 uint32_t flow_idx); 3809 3810 int 3811 flow_dv_mreg_match_cb(struct mlx5_hlist *list __rte_unused, 3812 struct mlx5_hlist_entry *entry, 3813 uint64_t key, void *cb_ctx __rte_unused) 3814 { 3815 struct mlx5_flow_mreg_copy_resource *mcp_res = 3816 container_of(entry, typeof(*mcp_res), hlist_ent); 3817 3818 return mcp_res->mark_id != key; 3819 } 3820 3821 struct mlx5_hlist_entry * 3822 flow_dv_mreg_create_cb(struct mlx5_hlist *list, uint64_t key, 3823 void *cb_ctx) 3824 { 3825 struct rte_eth_dev *dev = list->ctx; 3826 struct mlx5_priv *priv = dev->data->dev_private; 3827 struct mlx5_flow_cb_ctx *ctx = cb_ctx; 3828 struct mlx5_flow_mreg_copy_resource *mcp_res; 3829 struct rte_flow_error *error = ctx->error; 3830 uint32_t idx = 0; 3831 int ret; 3832 uint32_t mark_id = key; 3833 struct rte_flow_attr attr = { 3834 .group = MLX5_FLOW_MREG_CP_TABLE_GROUP, 3835 .ingress = 1, 3836 }; 3837 struct mlx5_rte_flow_item_tag tag_spec = { 3838 .data = mark_id, 3839 }; 3840 struct rte_flow_item items[] = { 3841 [1] = { .type = RTE_FLOW_ITEM_TYPE_END, }, 3842 }; 3843 struct rte_flow_action_mark ftag = { 3844 .id = mark_id, 3845 }; 3846 struct mlx5_flow_action_copy_mreg cp_mreg = { 3847 .dst = REG_B, 3848 .src = REG_NON, 3849 }; 3850 struct rte_flow_action_jump jump = { 3851 .group = MLX5_FLOW_MREG_ACT_TABLE_GROUP, 3852 }; 3853 struct rte_flow_action actions[] = { 3854 [3] = { .type = RTE_FLOW_ACTION_TYPE_END, }, 3855 }; 3856 3857 /* Fill the register fileds in the flow. */ 3858 ret = mlx5_flow_get_reg_id(dev, MLX5_FLOW_MARK, 0, error); 3859 if (ret < 0) 3860 return NULL; 3861 tag_spec.id = ret; 3862 ret = mlx5_flow_get_reg_id(dev, MLX5_METADATA_RX, 0, error); 3863 if (ret < 0) 3864 return NULL; 3865 cp_mreg.src = ret; 3866 /* Provide the full width of FLAG specific value. */ 3867 if (mark_id == (priv->sh->dv_regc0_mask & MLX5_FLOW_MARK_DEFAULT)) 3868 tag_spec.data = MLX5_FLOW_MARK_DEFAULT; 3869 /* Build a new flow. */ 3870 if (mark_id != MLX5_DEFAULT_COPY_ID) { 3871 items[0] = (struct rte_flow_item){ 3872 .type = (enum rte_flow_item_type) 3873 MLX5_RTE_FLOW_ITEM_TYPE_TAG, 3874 .spec = &tag_spec, 3875 }; 3876 items[1] = (struct rte_flow_item){ 3877 .type = RTE_FLOW_ITEM_TYPE_END, 3878 }; 3879 actions[0] = (struct rte_flow_action){ 3880 .type = (enum rte_flow_action_type) 3881 MLX5_RTE_FLOW_ACTION_TYPE_MARK, 3882 .conf = &ftag, 3883 }; 3884 actions[1] = (struct rte_flow_action){ 3885 .type = (enum rte_flow_action_type) 3886 MLX5_RTE_FLOW_ACTION_TYPE_COPY_MREG, 3887 .conf = &cp_mreg, 3888 }; 3889 actions[2] = (struct rte_flow_action){ 3890 .type = RTE_FLOW_ACTION_TYPE_JUMP, 3891 .conf = &jump, 3892 }; 3893 actions[3] = (struct rte_flow_action){ 3894 .type = RTE_FLOW_ACTION_TYPE_END, 3895 }; 3896 } else { 3897 /* Default rule, wildcard match. */ 3898 attr.priority = MLX5_FLOW_LOWEST_PRIO_INDICATOR; 3899 items[0] = (struct rte_flow_item){ 3900 .type = RTE_FLOW_ITEM_TYPE_END, 3901 }; 3902 actions[0] = (struct rte_flow_action){ 3903 .type = (enum rte_flow_action_type) 3904 MLX5_RTE_FLOW_ACTION_TYPE_COPY_MREG, 3905 .conf = &cp_mreg, 3906 }; 3907 actions[1] = (struct rte_flow_action){ 3908 .type = RTE_FLOW_ACTION_TYPE_JUMP, 3909 .conf = &jump, 3910 }; 3911 actions[2] = (struct rte_flow_action){ 3912 .type = RTE_FLOW_ACTION_TYPE_END, 3913 }; 3914 } 3915 /* Build a new entry. */ 3916 mcp_res = mlx5_ipool_zmalloc(priv->sh->ipool[MLX5_IPOOL_MCP], &idx); 3917 if (!mcp_res) { 3918 rte_errno = ENOMEM; 3919 return NULL; 3920 } 3921 mcp_res->idx = idx; 3922 mcp_res->mark_id = mark_id; 3923 /* 3924 * The copy Flows are not included in any list. There 3925 * ones are referenced from other Flows and can not 3926 * be applied, removed, deleted in ardbitrary order 3927 * by list traversing. 3928 */ 3929 mcp_res->rix_flow = flow_list_create(dev, NULL, &attr, items, 3930 actions, false, error); 3931 if (!mcp_res->rix_flow) { 3932 mlx5_ipool_free(priv->sh->ipool[MLX5_IPOOL_MCP], idx); 3933 return NULL; 3934 } 3935 return &mcp_res->hlist_ent; 3936 } 3937 3938 /** 3939 * Add a flow of copying flow metadata registers in RX_CP_TBL. 3940 * 3941 * As mark_id is unique, if there's already a registered flow for the mark_id, 3942 * return by increasing the reference counter of the resource. Otherwise, create 3943 * the resource (mcp_res) and flow. 3944 * 3945 * Flow looks like, 3946 * - If ingress port is ANY and reg_c[1] is mark_id, 3947 * flow_tag := mark_id, reg_b := reg_c[0] and jump to RX_ACT_TBL. 3948 * 3949 * For default flow (zero mark_id), flow is like, 3950 * - If ingress port is ANY, 3951 * reg_b := reg_c[0] and jump to RX_ACT_TBL. 3952 * 3953 * @param dev 3954 * Pointer to Ethernet device. 3955 * @param mark_id 3956 * ID of MARK action, zero means default flow for META. 3957 * @param[out] error 3958 * Perform verbose error reporting if not NULL. 3959 * 3960 * @return 3961 * Associated resource on success, NULL otherwise and rte_errno is set. 3962 */ 3963 static struct mlx5_flow_mreg_copy_resource * 3964 flow_mreg_add_copy_action(struct rte_eth_dev *dev, uint32_t mark_id, 3965 struct rte_flow_error *error) 3966 { 3967 struct mlx5_priv *priv = dev->data->dev_private; 3968 struct mlx5_hlist_entry *entry; 3969 struct mlx5_flow_cb_ctx ctx = { 3970 .dev = dev, 3971 .error = error, 3972 }; 3973 3974 /* Check if already registered. */ 3975 MLX5_ASSERT(priv->mreg_cp_tbl); 3976 entry = mlx5_hlist_register(priv->mreg_cp_tbl, mark_id, &ctx); 3977 if (!entry) 3978 return NULL; 3979 return container_of(entry, struct mlx5_flow_mreg_copy_resource, 3980 hlist_ent); 3981 } 3982 3983 void 3984 flow_dv_mreg_remove_cb(struct mlx5_hlist *list, struct mlx5_hlist_entry *entry) 3985 { 3986 struct mlx5_flow_mreg_copy_resource *mcp_res = 3987 container_of(entry, typeof(*mcp_res), hlist_ent); 3988 struct rte_eth_dev *dev = list->ctx; 3989 struct mlx5_priv *priv = dev->data->dev_private; 3990 3991 MLX5_ASSERT(mcp_res->rix_flow); 3992 flow_list_destroy(dev, NULL, mcp_res->rix_flow); 3993 mlx5_ipool_free(priv->sh->ipool[MLX5_IPOOL_MCP], mcp_res->idx); 3994 } 3995 3996 /** 3997 * Release flow in RX_CP_TBL. 3998 * 3999 * @param dev 4000 * Pointer to Ethernet device. 4001 * @flow 4002 * Parent flow for wich copying is provided. 4003 */ 4004 static void 4005 flow_mreg_del_copy_action(struct rte_eth_dev *dev, 4006 struct rte_flow *flow) 4007 { 4008 struct mlx5_flow_mreg_copy_resource *mcp_res; 4009 struct mlx5_priv *priv = dev->data->dev_private; 4010 4011 if (!flow->rix_mreg_copy) 4012 return; 4013 mcp_res = mlx5_ipool_get(priv->sh->ipool[MLX5_IPOOL_MCP], 4014 flow->rix_mreg_copy); 4015 if (!mcp_res || !priv->mreg_cp_tbl) 4016 return; 4017 MLX5_ASSERT(mcp_res->rix_flow); 4018 mlx5_hlist_unregister(priv->mreg_cp_tbl, &mcp_res->hlist_ent); 4019 flow->rix_mreg_copy = 0; 4020 } 4021 4022 /** 4023 * Remove the default copy action from RX_CP_TBL. 4024 * 4025 * This functions is called in the mlx5_dev_start(). No thread safe 4026 * is guaranteed. 4027 * 4028 * @param dev 4029 * Pointer to Ethernet device. 4030 */ 4031 static void 4032 flow_mreg_del_default_copy_action(struct rte_eth_dev *dev) 4033 { 4034 struct mlx5_hlist_entry *entry; 4035 struct mlx5_priv *priv = dev->data->dev_private; 4036 4037 /* Check if default flow is registered. */ 4038 if (!priv->mreg_cp_tbl) 4039 return; 4040 entry = mlx5_hlist_lookup(priv->mreg_cp_tbl, 4041 MLX5_DEFAULT_COPY_ID, NULL); 4042 if (!entry) 4043 return; 4044 mlx5_hlist_unregister(priv->mreg_cp_tbl, entry); 4045 } 4046 4047 /** 4048 * Add the default copy action in in RX_CP_TBL. 4049 * 4050 * This functions is called in the mlx5_dev_start(). No thread safe 4051 * is guaranteed. 4052 * 4053 * @param dev 4054 * Pointer to Ethernet device. 4055 * @param[out] error 4056 * Perform verbose error reporting if not NULL. 4057 * 4058 * @return 4059 * 0 for success, negative value otherwise and rte_errno is set. 4060 */ 4061 static int 4062 flow_mreg_add_default_copy_action(struct rte_eth_dev *dev, 4063 struct rte_flow_error *error) 4064 { 4065 struct mlx5_priv *priv = dev->data->dev_private; 4066 struct mlx5_flow_mreg_copy_resource *mcp_res; 4067 4068 /* Check whether extensive metadata feature is engaged. */ 4069 if (!priv->config.dv_flow_en || 4070 priv->config.dv_xmeta_en == MLX5_XMETA_MODE_LEGACY || 4071 !mlx5_flow_ext_mreg_supported(dev) || 4072 !priv->sh->dv_regc0_mask) 4073 return 0; 4074 /* 4075 * Add default mreg copy flow may be called multiple time, but 4076 * only be called once in stop. Avoid register it twice. 4077 */ 4078 if (mlx5_hlist_lookup(priv->mreg_cp_tbl, MLX5_DEFAULT_COPY_ID, NULL)) 4079 return 0; 4080 mcp_res = flow_mreg_add_copy_action(dev, MLX5_DEFAULT_COPY_ID, error); 4081 if (!mcp_res) 4082 return -rte_errno; 4083 return 0; 4084 } 4085 4086 /** 4087 * Add a flow of copying flow metadata registers in RX_CP_TBL. 4088 * 4089 * All the flow having Q/RSS action should be split by 4090 * flow_mreg_split_qrss_prep() to pass by RX_CP_TBL. A flow in the RX_CP_TBL 4091 * performs the following, 4092 * - CQE->flow_tag := reg_c[1] (MARK) 4093 * - CQE->flow_table_metadata (reg_b) := reg_c[0] (META) 4094 * As CQE's flow_tag is not a register, it can't be simply copied from reg_c[1] 4095 * but there should be a flow per each MARK ID set by MARK action. 4096 * 4097 * For the aforementioned reason, if there's a MARK action in flow's action 4098 * list, a corresponding flow should be added to the RX_CP_TBL in order to copy 4099 * the MARK ID to CQE's flow_tag like, 4100 * - If reg_c[1] is mark_id, 4101 * flow_tag := mark_id, reg_b := reg_c[0] and jump to RX_ACT_TBL. 4102 * 4103 * For SET_META action which stores value in reg_c[0], as the destination is 4104 * also a flow metadata register (reg_b), adding a default flow is enough. Zero 4105 * MARK ID means the default flow. The default flow looks like, 4106 * - For all flow, reg_b := reg_c[0] and jump to RX_ACT_TBL. 4107 * 4108 * @param dev 4109 * Pointer to Ethernet device. 4110 * @param flow 4111 * Pointer to flow structure. 4112 * @param[in] actions 4113 * Pointer to the list of actions. 4114 * @param[out] error 4115 * Perform verbose error reporting if not NULL. 4116 * 4117 * @return 4118 * 0 on success, negative value otherwise and rte_errno is set. 4119 */ 4120 static int 4121 flow_mreg_update_copy_table(struct rte_eth_dev *dev, 4122 struct rte_flow *flow, 4123 const struct rte_flow_action *actions, 4124 struct rte_flow_error *error) 4125 { 4126 struct mlx5_priv *priv = dev->data->dev_private; 4127 struct mlx5_dev_config *config = &priv->config; 4128 struct mlx5_flow_mreg_copy_resource *mcp_res; 4129 const struct rte_flow_action_mark *mark; 4130 4131 /* Check whether extensive metadata feature is engaged. */ 4132 if (!config->dv_flow_en || 4133 config->dv_xmeta_en == MLX5_XMETA_MODE_LEGACY || 4134 !mlx5_flow_ext_mreg_supported(dev) || 4135 !priv->sh->dv_regc0_mask) 4136 return 0; 4137 /* Find MARK action. */ 4138 for (; actions->type != RTE_FLOW_ACTION_TYPE_END; actions++) { 4139 switch (actions->type) { 4140 case RTE_FLOW_ACTION_TYPE_FLAG: 4141 mcp_res = flow_mreg_add_copy_action 4142 (dev, MLX5_FLOW_MARK_DEFAULT, error); 4143 if (!mcp_res) 4144 return -rte_errno; 4145 flow->rix_mreg_copy = mcp_res->idx; 4146 return 0; 4147 case RTE_FLOW_ACTION_TYPE_MARK: 4148 mark = (const struct rte_flow_action_mark *) 4149 actions->conf; 4150 mcp_res = 4151 flow_mreg_add_copy_action(dev, mark->id, error); 4152 if (!mcp_res) 4153 return -rte_errno; 4154 flow->rix_mreg_copy = mcp_res->idx; 4155 return 0; 4156 default: 4157 break; 4158 } 4159 } 4160 return 0; 4161 } 4162 4163 #define MLX5_MAX_SPLIT_ACTIONS 24 4164 #define MLX5_MAX_SPLIT_ITEMS 24 4165 4166 /** 4167 * Split the hairpin flow. 4168 * Since HW can't support encap and push-vlan on Rx, we move these 4169 * actions to Tx. 4170 * If the count action is after the encap then we also 4171 * move the count action. in this case the count will also measure 4172 * the outer bytes. 4173 * 4174 * @param dev 4175 * Pointer to Ethernet device. 4176 * @param[in] actions 4177 * Associated actions (list terminated by the END action). 4178 * @param[out] actions_rx 4179 * Rx flow actions. 4180 * @param[out] actions_tx 4181 * Tx flow actions.. 4182 * @param[out] pattern_tx 4183 * The pattern items for the Tx flow. 4184 * @param[out] flow_id 4185 * The flow ID connected to this flow. 4186 * 4187 * @return 4188 * 0 on success. 4189 */ 4190 static int 4191 flow_hairpin_split(struct rte_eth_dev *dev, 4192 const struct rte_flow_action actions[], 4193 struct rte_flow_action actions_rx[], 4194 struct rte_flow_action actions_tx[], 4195 struct rte_flow_item pattern_tx[], 4196 uint32_t flow_id) 4197 { 4198 const struct rte_flow_action_raw_encap *raw_encap; 4199 const struct rte_flow_action_raw_decap *raw_decap; 4200 struct mlx5_rte_flow_action_set_tag *set_tag; 4201 struct rte_flow_action *tag_action; 4202 struct mlx5_rte_flow_item_tag *tag_item; 4203 struct rte_flow_item *item; 4204 char *addr; 4205 int encap = 0; 4206 4207 for (; actions->type != RTE_FLOW_ACTION_TYPE_END; actions++) { 4208 switch (actions->type) { 4209 case RTE_FLOW_ACTION_TYPE_VXLAN_ENCAP: 4210 case RTE_FLOW_ACTION_TYPE_NVGRE_ENCAP: 4211 case RTE_FLOW_ACTION_TYPE_OF_PUSH_VLAN: 4212 case RTE_FLOW_ACTION_TYPE_OF_SET_VLAN_VID: 4213 case RTE_FLOW_ACTION_TYPE_OF_SET_VLAN_PCP: 4214 rte_memcpy(actions_tx, actions, 4215 sizeof(struct rte_flow_action)); 4216 actions_tx++; 4217 break; 4218 case RTE_FLOW_ACTION_TYPE_COUNT: 4219 if (encap) { 4220 rte_memcpy(actions_tx, actions, 4221 sizeof(struct rte_flow_action)); 4222 actions_tx++; 4223 } else { 4224 rte_memcpy(actions_rx, actions, 4225 sizeof(struct rte_flow_action)); 4226 actions_rx++; 4227 } 4228 break; 4229 case RTE_FLOW_ACTION_TYPE_RAW_ENCAP: 4230 raw_encap = actions->conf; 4231 if (raw_encap->size > MLX5_ENCAPSULATION_DECISION_SIZE) { 4232 memcpy(actions_tx, actions, 4233 sizeof(struct rte_flow_action)); 4234 actions_tx++; 4235 encap = 1; 4236 } else { 4237 rte_memcpy(actions_rx, actions, 4238 sizeof(struct rte_flow_action)); 4239 actions_rx++; 4240 } 4241 break; 4242 case RTE_FLOW_ACTION_TYPE_RAW_DECAP: 4243 raw_decap = actions->conf; 4244 if (raw_decap->size < MLX5_ENCAPSULATION_DECISION_SIZE) { 4245 memcpy(actions_tx, actions, 4246 sizeof(struct rte_flow_action)); 4247 actions_tx++; 4248 } else { 4249 rte_memcpy(actions_rx, actions, 4250 sizeof(struct rte_flow_action)); 4251 actions_rx++; 4252 } 4253 break; 4254 default: 4255 rte_memcpy(actions_rx, actions, 4256 sizeof(struct rte_flow_action)); 4257 actions_rx++; 4258 break; 4259 } 4260 } 4261 /* Add set meta action and end action for the Rx flow. */ 4262 tag_action = actions_rx; 4263 tag_action->type = (enum rte_flow_action_type) 4264 MLX5_RTE_FLOW_ACTION_TYPE_TAG; 4265 actions_rx++; 4266 rte_memcpy(actions_rx, actions, sizeof(struct rte_flow_action)); 4267 actions_rx++; 4268 set_tag = (void *)actions_rx; 4269 set_tag->id = mlx5_flow_get_reg_id(dev, MLX5_HAIRPIN_RX, 0, NULL); 4270 MLX5_ASSERT(set_tag->id > REG_NON); 4271 set_tag->data = flow_id; 4272 tag_action->conf = set_tag; 4273 /* Create Tx item list. */ 4274 rte_memcpy(actions_tx, actions, sizeof(struct rte_flow_action)); 4275 addr = (void *)&pattern_tx[2]; 4276 item = pattern_tx; 4277 item->type = (enum rte_flow_item_type) 4278 MLX5_RTE_FLOW_ITEM_TYPE_TAG; 4279 tag_item = (void *)addr; 4280 tag_item->data = flow_id; 4281 tag_item->id = mlx5_flow_get_reg_id(dev, MLX5_HAIRPIN_TX, 0, NULL); 4282 MLX5_ASSERT(set_tag->id > REG_NON); 4283 item->spec = tag_item; 4284 addr += sizeof(struct mlx5_rte_flow_item_tag); 4285 tag_item = (void *)addr; 4286 tag_item->data = UINT32_MAX; 4287 tag_item->id = UINT16_MAX; 4288 item->mask = tag_item; 4289 item->last = NULL; 4290 item++; 4291 item->type = RTE_FLOW_ITEM_TYPE_END; 4292 return 0; 4293 } 4294 4295 /** 4296 * The last stage of splitting chain, just creates the subflow 4297 * without any modification. 4298 * 4299 * @param[in] dev 4300 * Pointer to Ethernet device. 4301 * @param[in] flow 4302 * Parent flow structure pointer. 4303 * @param[in, out] sub_flow 4304 * Pointer to return the created subflow, may be NULL. 4305 * @param[in] attr 4306 * Flow rule attributes. 4307 * @param[in] items 4308 * Pattern specification (list terminated by the END pattern item). 4309 * @param[in] actions 4310 * Associated actions (list terminated by the END action). 4311 * @param[in] flow_split_info 4312 * Pointer to flow split info structure. 4313 * @param[out] error 4314 * Perform verbose error reporting if not NULL. 4315 * @return 4316 * 0 on success, negative value otherwise 4317 */ 4318 static int 4319 flow_create_split_inner(struct rte_eth_dev *dev, 4320 struct rte_flow *flow, 4321 struct mlx5_flow **sub_flow, 4322 const struct rte_flow_attr *attr, 4323 const struct rte_flow_item items[], 4324 const struct rte_flow_action actions[], 4325 struct mlx5_flow_split_info *flow_split_info, 4326 struct rte_flow_error *error) 4327 { 4328 struct mlx5_flow *dev_flow; 4329 4330 dev_flow = flow_drv_prepare(dev, flow, attr, items, actions, 4331 flow_split_info->flow_idx, error); 4332 if (!dev_flow) 4333 return -rte_errno; 4334 dev_flow->flow = flow; 4335 dev_flow->external = flow_split_info->external; 4336 dev_flow->skip_scale = flow_split_info->skip_scale; 4337 /* Subflow object was created, we must include one in the list. */ 4338 SILIST_INSERT(&flow->dev_handles, dev_flow->handle_idx, 4339 dev_flow->handle, next); 4340 /* 4341 * If dev_flow is as one of the suffix flow, some actions in suffix 4342 * flow may need some user defined item layer flags, and pass the 4343 * Metadate rxq mark flag to suffix flow as well. 4344 */ 4345 if (flow_split_info->prefix_layers) 4346 dev_flow->handle->layers = flow_split_info->prefix_layers; 4347 if (flow_split_info->prefix_mark) 4348 dev_flow->handle->mark = 1; 4349 if (sub_flow) 4350 *sub_flow = dev_flow; 4351 return flow_drv_translate(dev, dev_flow, attr, items, actions, error); 4352 } 4353 4354 /** 4355 * Split the meter flow. 4356 * 4357 * As meter flow will split to three sub flow, other than meter 4358 * action, the other actions make sense to only meter accepts 4359 * the packet. If it need to be dropped, no other additional 4360 * actions should be take. 4361 * 4362 * One kind of special action which decapsulates the L3 tunnel 4363 * header will be in the prefix sub flow, as not to take the 4364 * L3 tunnel header into account. 4365 * 4366 * @param dev 4367 * Pointer to Ethernet device. 4368 * @param[in] items 4369 * Pattern specification (list terminated by the END pattern item). 4370 * @param[out] sfx_items 4371 * Suffix flow match items (list terminated by the END pattern item). 4372 * @param[in] actions 4373 * Associated actions (list terminated by the END action). 4374 * @param[out] actions_sfx 4375 * Suffix flow actions. 4376 * @param[out] actions_pre 4377 * Prefix flow actions. 4378 * @param[out] pattern_sfx 4379 * The pattern items for the suffix flow. 4380 * @param[out] tag_sfx 4381 * Pointer to suffix flow tag. 4382 * 4383 * @return 4384 * 0 on success. 4385 */ 4386 static int 4387 flow_meter_split_prep(struct rte_eth_dev *dev, 4388 const struct rte_flow_item items[], 4389 struct rte_flow_item sfx_items[], 4390 const struct rte_flow_action actions[], 4391 struct rte_flow_action actions_sfx[], 4392 struct rte_flow_action actions_pre[]) 4393 { 4394 struct mlx5_priv *priv = dev->data->dev_private; 4395 struct rte_flow_action *tag_action = NULL; 4396 struct rte_flow_item *tag_item; 4397 struct mlx5_rte_flow_action_set_tag *set_tag; 4398 struct rte_flow_error error; 4399 const struct rte_flow_action_raw_encap *raw_encap; 4400 const struct rte_flow_action_raw_decap *raw_decap; 4401 struct mlx5_rte_flow_item_tag *tag_spec; 4402 struct mlx5_rte_flow_item_tag *tag_mask; 4403 uint32_t tag_id = 0; 4404 bool copy_vlan = false; 4405 4406 /* Prepare the actions for prefix and suffix flow. */ 4407 for (; actions->type != RTE_FLOW_ACTION_TYPE_END; actions++) { 4408 struct rte_flow_action **action_cur = NULL; 4409 4410 switch (actions->type) { 4411 case RTE_FLOW_ACTION_TYPE_METER: 4412 /* Add the extra tag action first. */ 4413 tag_action = actions_pre; 4414 tag_action->type = (enum rte_flow_action_type) 4415 MLX5_RTE_FLOW_ACTION_TYPE_TAG; 4416 actions_pre++; 4417 action_cur = &actions_pre; 4418 break; 4419 case RTE_FLOW_ACTION_TYPE_VXLAN_DECAP: 4420 case RTE_FLOW_ACTION_TYPE_NVGRE_DECAP: 4421 action_cur = &actions_pre; 4422 break; 4423 case RTE_FLOW_ACTION_TYPE_RAW_ENCAP: 4424 raw_encap = actions->conf; 4425 if (raw_encap->size < MLX5_ENCAPSULATION_DECISION_SIZE) 4426 action_cur = &actions_pre; 4427 break; 4428 case RTE_FLOW_ACTION_TYPE_RAW_DECAP: 4429 raw_decap = actions->conf; 4430 if (raw_decap->size > MLX5_ENCAPSULATION_DECISION_SIZE) 4431 action_cur = &actions_pre; 4432 break; 4433 case RTE_FLOW_ACTION_TYPE_OF_PUSH_VLAN: 4434 case RTE_FLOW_ACTION_TYPE_OF_SET_VLAN_VID: 4435 copy_vlan = true; 4436 break; 4437 default: 4438 break; 4439 } 4440 if (!action_cur) 4441 action_cur = &actions_sfx; 4442 memcpy(*action_cur, actions, sizeof(struct rte_flow_action)); 4443 (*action_cur)++; 4444 } 4445 /* Add end action to the actions. */ 4446 actions_sfx->type = RTE_FLOW_ACTION_TYPE_END; 4447 actions_pre->type = RTE_FLOW_ACTION_TYPE_END; 4448 actions_pre++; 4449 /* Set the tag. */ 4450 set_tag = (void *)actions_pre; 4451 set_tag->id = mlx5_flow_get_reg_id(dev, MLX5_MTR_SFX, 0, &error); 4452 mlx5_ipool_malloc(priv->sh->ipool[MLX5_IPOOL_RSS_EXPANTION_FLOW_ID], 4453 &tag_id); 4454 if (tag_id >= (1 << (sizeof(tag_id) * 8 - MLX5_MTR_COLOR_BITS))) { 4455 DRV_LOG(ERR, "Port %u meter flow id exceed max limit.", 4456 dev->data->port_id); 4457 mlx5_ipool_free(priv->sh->ipool 4458 [MLX5_IPOOL_RSS_EXPANTION_FLOW_ID], tag_id); 4459 return 0; 4460 } else if (!tag_id) { 4461 return 0; 4462 } 4463 set_tag->data = tag_id << MLX5_MTR_COLOR_BITS; 4464 assert(tag_action); 4465 tag_action->conf = set_tag; 4466 /* Prepare the suffix subflow items. */ 4467 tag_item = sfx_items++; 4468 for (; items->type != RTE_FLOW_ITEM_TYPE_END; items++) { 4469 int item_type = items->type; 4470 4471 switch (item_type) { 4472 case RTE_FLOW_ITEM_TYPE_PORT_ID: 4473 memcpy(sfx_items, items, sizeof(*sfx_items)); 4474 sfx_items++; 4475 break; 4476 case RTE_FLOW_ITEM_TYPE_VLAN: 4477 if (copy_vlan) { 4478 memcpy(sfx_items, items, sizeof(*sfx_items)); 4479 /* 4480 * Convert to internal match item, it is used 4481 * for vlan push and set vid. 4482 */ 4483 sfx_items->type = (enum rte_flow_item_type) 4484 MLX5_RTE_FLOW_ITEM_TYPE_VLAN; 4485 sfx_items++; 4486 } 4487 break; 4488 default: 4489 break; 4490 } 4491 } 4492 sfx_items->type = RTE_FLOW_ITEM_TYPE_END; 4493 sfx_items++; 4494 tag_spec = (struct mlx5_rte_flow_item_tag *)sfx_items; 4495 tag_spec->data = tag_id << MLX5_MTR_COLOR_BITS; 4496 tag_spec->id = mlx5_flow_get_reg_id(dev, MLX5_MTR_SFX, 0, &error); 4497 tag_mask = tag_spec + 1; 4498 tag_mask->data = 0xffffff00; 4499 tag_item->type = (enum rte_flow_item_type) 4500 MLX5_RTE_FLOW_ITEM_TYPE_TAG; 4501 tag_item->spec = tag_spec; 4502 tag_item->last = NULL; 4503 tag_item->mask = tag_mask; 4504 return tag_id; 4505 } 4506 4507 /** 4508 * Split action list having QUEUE/RSS for metadata register copy. 4509 * 4510 * Once Q/RSS action is detected in user's action list, the flow action 4511 * should be split in order to copy metadata registers, which will happen in 4512 * RX_CP_TBL like, 4513 * - CQE->flow_tag := reg_c[1] (MARK) 4514 * - CQE->flow_table_metadata (reg_b) := reg_c[0] (META) 4515 * The Q/RSS action will be performed on RX_ACT_TBL after passing by RX_CP_TBL. 4516 * This is because the last action of each flow must be a terminal action 4517 * (QUEUE, RSS or DROP). 4518 * 4519 * Flow ID must be allocated to identify actions in the RX_ACT_TBL and it is 4520 * stored and kept in the mlx5_flow structure per each sub_flow. 4521 * 4522 * The Q/RSS action is replaced with, 4523 * - SET_TAG, setting the allocated flow ID to reg_c[2]. 4524 * And the following JUMP action is added at the end, 4525 * - JUMP, to RX_CP_TBL. 4526 * 4527 * A flow to perform remained Q/RSS action will be created in RX_ACT_TBL by 4528 * flow_create_split_metadata() routine. The flow will look like, 4529 * - If flow ID matches (reg_c[2]), perform Q/RSS. 4530 * 4531 * @param dev 4532 * Pointer to Ethernet device. 4533 * @param[out] split_actions 4534 * Pointer to store split actions to jump to CP_TBL. 4535 * @param[in] actions 4536 * Pointer to the list of original flow actions. 4537 * @param[in] qrss 4538 * Pointer to the Q/RSS action. 4539 * @param[in] actions_n 4540 * Number of original actions. 4541 * @param[out] error 4542 * Perform verbose error reporting if not NULL. 4543 * 4544 * @return 4545 * non-zero unique flow_id on success, otherwise 0 and 4546 * error/rte_error are set. 4547 */ 4548 static uint32_t 4549 flow_mreg_split_qrss_prep(struct rte_eth_dev *dev, 4550 struct rte_flow_action *split_actions, 4551 const struct rte_flow_action *actions, 4552 const struct rte_flow_action *qrss, 4553 int actions_n, struct rte_flow_error *error) 4554 { 4555 struct mlx5_priv *priv = dev->data->dev_private; 4556 struct mlx5_rte_flow_action_set_tag *set_tag; 4557 struct rte_flow_action_jump *jump; 4558 const int qrss_idx = qrss - actions; 4559 uint32_t flow_id = 0; 4560 int ret = 0; 4561 4562 /* 4563 * Given actions will be split 4564 * - Replace QUEUE/RSS action with SET_TAG to set flow ID. 4565 * - Add jump to mreg CP_TBL. 4566 * As a result, there will be one more action. 4567 */ 4568 ++actions_n; 4569 memcpy(split_actions, actions, sizeof(*split_actions) * actions_n); 4570 set_tag = (void *)(split_actions + actions_n); 4571 /* 4572 * If tag action is not set to void(it means we are not the meter 4573 * suffix flow), add the tag action. Since meter suffix flow already 4574 * has the tag added. 4575 */ 4576 if (split_actions[qrss_idx].type != RTE_FLOW_ACTION_TYPE_VOID) { 4577 /* 4578 * Allocate the new subflow ID. This one is unique within 4579 * device and not shared with representors. Otherwise, 4580 * we would have to resolve multi-thread access synch 4581 * issue. Each flow on the shared device is appended 4582 * with source vport identifier, so the resulting 4583 * flows will be unique in the shared (by master and 4584 * representors) domain even if they have coinciding 4585 * IDs. 4586 */ 4587 mlx5_ipool_malloc(priv->sh->ipool 4588 [MLX5_IPOOL_RSS_EXPANTION_FLOW_ID], &flow_id); 4589 if (!flow_id) 4590 return rte_flow_error_set(error, ENOMEM, 4591 RTE_FLOW_ERROR_TYPE_ACTION, 4592 NULL, "can't allocate id " 4593 "for split Q/RSS subflow"); 4594 /* Internal SET_TAG action to set flow ID. */ 4595 *set_tag = (struct mlx5_rte_flow_action_set_tag){ 4596 .data = flow_id, 4597 }; 4598 ret = mlx5_flow_get_reg_id(dev, MLX5_COPY_MARK, 0, error); 4599 if (ret < 0) 4600 return ret; 4601 set_tag->id = ret; 4602 /* Construct new actions array. */ 4603 /* Replace QUEUE/RSS action. */ 4604 split_actions[qrss_idx] = (struct rte_flow_action){ 4605 .type = (enum rte_flow_action_type) 4606 MLX5_RTE_FLOW_ACTION_TYPE_TAG, 4607 .conf = set_tag, 4608 }; 4609 } 4610 /* JUMP action to jump to mreg copy table (CP_TBL). */ 4611 jump = (void *)(set_tag + 1); 4612 *jump = (struct rte_flow_action_jump){ 4613 .group = MLX5_FLOW_MREG_CP_TABLE_GROUP, 4614 }; 4615 split_actions[actions_n - 2] = (struct rte_flow_action){ 4616 .type = RTE_FLOW_ACTION_TYPE_JUMP, 4617 .conf = jump, 4618 }; 4619 split_actions[actions_n - 1] = (struct rte_flow_action){ 4620 .type = RTE_FLOW_ACTION_TYPE_END, 4621 }; 4622 return flow_id; 4623 } 4624 4625 /** 4626 * Extend the given action list for Tx metadata copy. 4627 * 4628 * Copy the given action list to the ext_actions and add flow metadata register 4629 * copy action in order to copy reg_a set by WQE to reg_c[0]. 4630 * 4631 * @param[out] ext_actions 4632 * Pointer to the extended action list. 4633 * @param[in] actions 4634 * Pointer to the list of actions. 4635 * @param[in] actions_n 4636 * Number of actions in the list. 4637 * @param[out] error 4638 * Perform verbose error reporting if not NULL. 4639 * @param[in] encap_idx 4640 * The encap action inndex. 4641 * 4642 * @return 4643 * 0 on success, negative value otherwise 4644 */ 4645 static int 4646 flow_mreg_tx_copy_prep(struct rte_eth_dev *dev, 4647 struct rte_flow_action *ext_actions, 4648 const struct rte_flow_action *actions, 4649 int actions_n, struct rte_flow_error *error, 4650 int encap_idx) 4651 { 4652 struct mlx5_flow_action_copy_mreg *cp_mreg = 4653 (struct mlx5_flow_action_copy_mreg *) 4654 (ext_actions + actions_n + 1); 4655 int ret; 4656 4657 ret = mlx5_flow_get_reg_id(dev, MLX5_METADATA_RX, 0, error); 4658 if (ret < 0) 4659 return ret; 4660 cp_mreg->dst = ret; 4661 ret = mlx5_flow_get_reg_id(dev, MLX5_METADATA_TX, 0, error); 4662 if (ret < 0) 4663 return ret; 4664 cp_mreg->src = ret; 4665 if (encap_idx != 0) 4666 memcpy(ext_actions, actions, sizeof(*ext_actions) * encap_idx); 4667 if (encap_idx == actions_n - 1) { 4668 ext_actions[actions_n - 1] = (struct rte_flow_action){ 4669 .type = (enum rte_flow_action_type) 4670 MLX5_RTE_FLOW_ACTION_TYPE_COPY_MREG, 4671 .conf = cp_mreg, 4672 }; 4673 ext_actions[actions_n] = (struct rte_flow_action){ 4674 .type = RTE_FLOW_ACTION_TYPE_END, 4675 }; 4676 } else { 4677 ext_actions[encap_idx] = (struct rte_flow_action){ 4678 .type = (enum rte_flow_action_type) 4679 MLX5_RTE_FLOW_ACTION_TYPE_COPY_MREG, 4680 .conf = cp_mreg, 4681 }; 4682 memcpy(ext_actions + encap_idx + 1, actions + encap_idx, 4683 sizeof(*ext_actions) * (actions_n - encap_idx)); 4684 } 4685 return 0; 4686 } 4687 4688 /** 4689 * Check the match action from the action list. 4690 * 4691 * @param[in] actions 4692 * Pointer to the list of actions. 4693 * @param[in] attr 4694 * Flow rule attributes. 4695 * @param[in] action 4696 * The action to be check if exist. 4697 * @param[out] match_action_pos 4698 * Pointer to the position of the matched action if exists, otherwise is -1. 4699 * @param[out] qrss_action_pos 4700 * Pointer to the position of the Queue/RSS action if exists, otherwise is -1. 4701 * @param[out] modify_after_mirror 4702 * Pointer to the flag of modify action after FDB mirroring. 4703 * 4704 * @return 4705 * > 0 the total number of actions. 4706 * 0 if not found match action in action list. 4707 */ 4708 static int 4709 flow_check_match_action(const struct rte_flow_action actions[], 4710 const struct rte_flow_attr *attr, 4711 enum rte_flow_action_type action, 4712 int *match_action_pos, int *qrss_action_pos, 4713 int *modify_after_mirror) 4714 { 4715 const struct rte_flow_action_sample *sample; 4716 int actions_n = 0; 4717 uint32_t ratio = 0; 4718 int sub_type = 0; 4719 int flag = 0; 4720 int fdb_mirror = 0; 4721 4722 *match_action_pos = -1; 4723 *qrss_action_pos = -1; 4724 for (; actions->type != RTE_FLOW_ACTION_TYPE_END; actions++) { 4725 if (actions->type == action) { 4726 flag = 1; 4727 *match_action_pos = actions_n; 4728 } 4729 switch (actions->type) { 4730 case RTE_FLOW_ACTION_TYPE_QUEUE: 4731 case RTE_FLOW_ACTION_TYPE_RSS: 4732 *qrss_action_pos = actions_n; 4733 break; 4734 case RTE_FLOW_ACTION_TYPE_SAMPLE: 4735 sample = actions->conf; 4736 ratio = sample->ratio; 4737 sub_type = ((const struct rte_flow_action *) 4738 (sample->actions))->type; 4739 if (ratio == 1 && attr->transfer) 4740 fdb_mirror = 1; 4741 break; 4742 case RTE_FLOW_ACTION_TYPE_SET_MAC_SRC: 4743 case RTE_FLOW_ACTION_TYPE_SET_MAC_DST: 4744 case RTE_FLOW_ACTION_TYPE_SET_IPV4_SRC: 4745 case RTE_FLOW_ACTION_TYPE_SET_IPV4_DST: 4746 case RTE_FLOW_ACTION_TYPE_SET_IPV6_SRC: 4747 case RTE_FLOW_ACTION_TYPE_SET_IPV6_DST: 4748 case RTE_FLOW_ACTION_TYPE_SET_TP_SRC: 4749 case RTE_FLOW_ACTION_TYPE_SET_TP_DST: 4750 case RTE_FLOW_ACTION_TYPE_DEC_TTL: 4751 case RTE_FLOW_ACTION_TYPE_SET_TTL: 4752 case RTE_FLOW_ACTION_TYPE_INC_TCP_SEQ: 4753 case RTE_FLOW_ACTION_TYPE_DEC_TCP_SEQ: 4754 case RTE_FLOW_ACTION_TYPE_INC_TCP_ACK: 4755 case RTE_FLOW_ACTION_TYPE_DEC_TCP_ACK: 4756 case RTE_FLOW_ACTION_TYPE_SET_IPV4_DSCP: 4757 case RTE_FLOW_ACTION_TYPE_SET_IPV6_DSCP: 4758 case RTE_FLOW_ACTION_TYPE_FLAG: 4759 case RTE_FLOW_ACTION_TYPE_MARK: 4760 case RTE_FLOW_ACTION_TYPE_SET_META: 4761 case RTE_FLOW_ACTION_TYPE_SET_TAG: 4762 if (fdb_mirror) 4763 *modify_after_mirror = 1; 4764 break; 4765 default: 4766 break; 4767 } 4768 actions_n++; 4769 } 4770 if (flag && fdb_mirror && !*modify_after_mirror) { 4771 /* FDB mirroring uses the destination array to implement 4772 * instead of FLOW_SAMPLER object. 4773 */ 4774 if (sub_type != RTE_FLOW_ACTION_TYPE_END) 4775 flag = 0; 4776 } 4777 /* Count RTE_FLOW_ACTION_TYPE_END. */ 4778 return flag ? actions_n + 1 : 0; 4779 } 4780 4781 #define SAMPLE_SUFFIX_ITEM 2 4782 4783 /** 4784 * Split the sample flow. 4785 * 4786 * As sample flow will split to two sub flow, sample flow with 4787 * sample action, the other actions will move to new suffix flow. 4788 * 4789 * Also add unique tag id with tag action in the sample flow, 4790 * the same tag id will be as match in the suffix flow. 4791 * 4792 * @param dev 4793 * Pointer to Ethernet device. 4794 * @param[in] add_tag 4795 * Add extra tag action flag. 4796 * @param[out] sfx_items 4797 * Suffix flow match items (list terminated by the END pattern item). 4798 * @param[in] actions 4799 * Associated actions (list terminated by the END action). 4800 * @param[out] actions_sfx 4801 * Suffix flow actions. 4802 * @param[out] actions_pre 4803 * Prefix flow actions. 4804 * @param[in] actions_n 4805 * The total number of actions. 4806 * @param[in] sample_action_pos 4807 * The sample action position. 4808 * @param[in] qrss_action_pos 4809 * The Queue/RSS action position. 4810 * @param[in] jump_table 4811 * Add extra jump action flag. 4812 * @param[out] error 4813 * Perform verbose error reporting if not NULL. 4814 * 4815 * @return 4816 * 0 on success, or unique flow_id, a negative errno value 4817 * otherwise and rte_errno is set. 4818 */ 4819 static int 4820 flow_sample_split_prep(struct rte_eth_dev *dev, 4821 int add_tag, 4822 struct rte_flow_item sfx_items[], 4823 const struct rte_flow_action actions[], 4824 struct rte_flow_action actions_sfx[], 4825 struct rte_flow_action actions_pre[], 4826 int actions_n, 4827 int sample_action_pos, 4828 int qrss_action_pos, 4829 int jump_table, 4830 struct rte_flow_error *error) 4831 { 4832 struct mlx5_priv *priv = dev->data->dev_private; 4833 struct mlx5_rte_flow_action_set_tag *set_tag; 4834 struct mlx5_rte_flow_item_tag *tag_spec; 4835 struct mlx5_rte_flow_item_tag *tag_mask; 4836 struct rte_flow_action_jump *jump_action; 4837 uint32_t tag_id = 0; 4838 int index; 4839 int append_index = 0; 4840 int ret; 4841 4842 if (sample_action_pos < 0) 4843 return rte_flow_error_set(error, EINVAL, 4844 RTE_FLOW_ERROR_TYPE_ACTION, 4845 NULL, "invalid position of sample " 4846 "action in list"); 4847 /* Prepare the actions for prefix and suffix flow. */ 4848 if (qrss_action_pos >= 0 && qrss_action_pos < sample_action_pos) { 4849 index = qrss_action_pos; 4850 /* Put the preceding the Queue/RSS action into prefix flow. */ 4851 if (index != 0) 4852 memcpy(actions_pre, actions, 4853 sizeof(struct rte_flow_action) * index); 4854 /* Put others preceding the sample action into prefix flow. */ 4855 if (sample_action_pos > index + 1) 4856 memcpy(actions_pre + index, actions + index + 1, 4857 sizeof(struct rte_flow_action) * 4858 (sample_action_pos - index - 1)); 4859 index = sample_action_pos - 1; 4860 /* Put Queue/RSS action into Suffix flow. */ 4861 memcpy(actions_sfx, actions + qrss_action_pos, 4862 sizeof(struct rte_flow_action)); 4863 actions_sfx++; 4864 } else { 4865 index = sample_action_pos; 4866 if (index != 0) 4867 memcpy(actions_pre, actions, 4868 sizeof(struct rte_flow_action) * index); 4869 } 4870 /* For CX5, add an extra tag action for NIC-RX and E-Switch ingress. 4871 * For CX6DX and above, metadata registers Cx preserve their value, 4872 * add an extra tag action for NIC-RX and E-Switch Domain. 4873 */ 4874 if (add_tag) { 4875 /* Prepare the prefix tag action. */ 4876 append_index++; 4877 set_tag = (void *)(actions_pre + actions_n + append_index); 4878 ret = mlx5_flow_get_reg_id(dev, MLX5_APP_TAG, 0, error); 4879 if (ret < 0) 4880 return ret; 4881 set_tag->id = ret; 4882 mlx5_ipool_malloc(priv->sh->ipool 4883 [MLX5_IPOOL_RSS_EXPANTION_FLOW_ID], &tag_id); 4884 set_tag->data = tag_id; 4885 /* Prepare the suffix subflow items. */ 4886 tag_spec = (void *)(sfx_items + SAMPLE_SUFFIX_ITEM); 4887 tag_spec->data = tag_id; 4888 tag_spec->id = set_tag->id; 4889 tag_mask = tag_spec + 1; 4890 tag_mask->data = UINT32_MAX; 4891 sfx_items[0] = (struct rte_flow_item){ 4892 .type = (enum rte_flow_item_type) 4893 MLX5_RTE_FLOW_ITEM_TYPE_TAG, 4894 .spec = tag_spec, 4895 .last = NULL, 4896 .mask = tag_mask, 4897 }; 4898 sfx_items[1] = (struct rte_flow_item){ 4899 .type = (enum rte_flow_item_type) 4900 RTE_FLOW_ITEM_TYPE_END, 4901 }; 4902 /* Prepare the tag action in prefix subflow. */ 4903 actions_pre[index++] = 4904 (struct rte_flow_action){ 4905 .type = (enum rte_flow_action_type) 4906 MLX5_RTE_FLOW_ACTION_TYPE_TAG, 4907 .conf = set_tag, 4908 }; 4909 } 4910 memcpy(actions_pre + index, actions + sample_action_pos, 4911 sizeof(struct rte_flow_action)); 4912 index += 1; 4913 /* For the modify action after the sample action in E-Switch mirroring, 4914 * Add the extra jump action in prefix subflow and jump into the next 4915 * table, then do the modify action in the new table. 4916 */ 4917 if (jump_table) { 4918 /* Prepare the prefix jump action. */ 4919 append_index++; 4920 jump_action = (void *)(actions_pre + actions_n + append_index); 4921 jump_action->group = jump_table; 4922 actions_pre[index++] = 4923 (struct rte_flow_action){ 4924 .type = (enum rte_flow_action_type) 4925 RTE_FLOW_ACTION_TYPE_JUMP, 4926 .conf = jump_action, 4927 }; 4928 } 4929 actions_pre[index] = (struct rte_flow_action){ 4930 .type = (enum rte_flow_action_type) 4931 RTE_FLOW_ACTION_TYPE_END, 4932 }; 4933 /* Put the actions after sample into Suffix flow. */ 4934 memcpy(actions_sfx, actions + sample_action_pos + 1, 4935 sizeof(struct rte_flow_action) * 4936 (actions_n - sample_action_pos - 1)); 4937 return tag_id; 4938 } 4939 4940 /** 4941 * The splitting for metadata feature. 4942 * 4943 * - Q/RSS action on NIC Rx should be split in order to pass by 4944 * the mreg copy table (RX_CP_TBL) and then it jumps to the 4945 * action table (RX_ACT_TBL) which has the split Q/RSS action. 4946 * 4947 * - All the actions on NIC Tx should have a mreg copy action to 4948 * copy reg_a from WQE to reg_c[0]. 4949 * 4950 * @param dev 4951 * Pointer to Ethernet device. 4952 * @param[in] flow 4953 * Parent flow structure pointer. 4954 * @param[in] attr 4955 * Flow rule attributes. 4956 * @param[in] items 4957 * Pattern specification (list terminated by the END pattern item). 4958 * @param[in] actions 4959 * Associated actions (list terminated by the END action). 4960 * @param[in] flow_split_info 4961 * Pointer to flow split info structure. 4962 * @param[out] error 4963 * Perform verbose error reporting if not NULL. 4964 * @return 4965 * 0 on success, negative value otherwise 4966 */ 4967 static int 4968 flow_create_split_metadata(struct rte_eth_dev *dev, 4969 struct rte_flow *flow, 4970 const struct rte_flow_attr *attr, 4971 const struct rte_flow_item items[], 4972 const struct rte_flow_action actions[], 4973 struct mlx5_flow_split_info *flow_split_info, 4974 struct rte_flow_error *error) 4975 { 4976 struct mlx5_priv *priv = dev->data->dev_private; 4977 struct mlx5_dev_config *config = &priv->config; 4978 const struct rte_flow_action *qrss = NULL; 4979 struct rte_flow_action *ext_actions = NULL; 4980 struct mlx5_flow *dev_flow = NULL; 4981 uint32_t qrss_id = 0; 4982 int mtr_sfx = 0; 4983 size_t act_size; 4984 int actions_n; 4985 int encap_idx; 4986 int ret; 4987 4988 /* Check whether extensive metadata feature is engaged. */ 4989 if (!config->dv_flow_en || 4990 config->dv_xmeta_en == MLX5_XMETA_MODE_LEGACY || 4991 !mlx5_flow_ext_mreg_supported(dev)) 4992 return flow_create_split_inner(dev, flow, NULL, attr, items, 4993 actions, flow_split_info, error); 4994 actions_n = flow_parse_metadata_split_actions_info(actions, &qrss, 4995 &encap_idx); 4996 if (qrss) { 4997 /* Exclude hairpin flows from splitting. */ 4998 if (qrss->type == RTE_FLOW_ACTION_TYPE_QUEUE) { 4999 const struct rte_flow_action_queue *queue; 5000 5001 queue = qrss->conf; 5002 if (mlx5_rxq_get_type(dev, queue->index) == 5003 MLX5_RXQ_TYPE_HAIRPIN) 5004 qrss = NULL; 5005 } else if (qrss->type == RTE_FLOW_ACTION_TYPE_RSS) { 5006 const struct rte_flow_action_rss *rss; 5007 5008 rss = qrss->conf; 5009 if (mlx5_rxq_get_type(dev, rss->queue[0]) == 5010 MLX5_RXQ_TYPE_HAIRPIN) 5011 qrss = NULL; 5012 } 5013 } 5014 if (qrss) { 5015 /* Check if it is in meter suffix table. */ 5016 mtr_sfx = attr->group == (attr->transfer ? 5017 (MLX5_FLOW_TABLE_LEVEL_SUFFIX - 1) : 5018 MLX5_FLOW_TABLE_LEVEL_SUFFIX); 5019 /* 5020 * Q/RSS action on NIC Rx should be split in order to pass by 5021 * the mreg copy table (RX_CP_TBL) and then it jumps to the 5022 * action table (RX_ACT_TBL) which has the split Q/RSS action. 5023 */ 5024 act_size = sizeof(struct rte_flow_action) * (actions_n + 1) + 5025 sizeof(struct rte_flow_action_set_tag) + 5026 sizeof(struct rte_flow_action_jump); 5027 ext_actions = mlx5_malloc(MLX5_MEM_ZERO, act_size, 0, 5028 SOCKET_ID_ANY); 5029 if (!ext_actions) 5030 return rte_flow_error_set(error, ENOMEM, 5031 RTE_FLOW_ERROR_TYPE_ACTION, 5032 NULL, "no memory to split " 5033 "metadata flow"); 5034 /* 5035 * If we are the suffix flow of meter, tag already exist. 5036 * Set the tag action to void. 5037 */ 5038 if (mtr_sfx) 5039 ext_actions[qrss - actions].type = 5040 RTE_FLOW_ACTION_TYPE_VOID; 5041 else 5042 ext_actions[qrss - actions].type = 5043 (enum rte_flow_action_type) 5044 MLX5_RTE_FLOW_ACTION_TYPE_TAG; 5045 /* 5046 * Create the new actions list with removed Q/RSS action 5047 * and appended set tag and jump to register copy table 5048 * (RX_CP_TBL). We should preallocate unique tag ID here 5049 * in advance, because it is needed for set tag action. 5050 */ 5051 qrss_id = flow_mreg_split_qrss_prep(dev, ext_actions, actions, 5052 qrss, actions_n, error); 5053 if (!mtr_sfx && !qrss_id) { 5054 ret = -rte_errno; 5055 goto exit; 5056 } 5057 } else if (attr->egress && !attr->transfer) { 5058 /* 5059 * All the actions on NIC Tx should have a metadata register 5060 * copy action to copy reg_a from WQE to reg_c[meta] 5061 */ 5062 act_size = sizeof(struct rte_flow_action) * (actions_n + 1) + 5063 sizeof(struct mlx5_flow_action_copy_mreg); 5064 ext_actions = mlx5_malloc(MLX5_MEM_ZERO, act_size, 0, 5065 SOCKET_ID_ANY); 5066 if (!ext_actions) 5067 return rte_flow_error_set(error, ENOMEM, 5068 RTE_FLOW_ERROR_TYPE_ACTION, 5069 NULL, "no memory to split " 5070 "metadata flow"); 5071 /* Create the action list appended with copy register. */ 5072 ret = flow_mreg_tx_copy_prep(dev, ext_actions, actions, 5073 actions_n, error, encap_idx); 5074 if (ret < 0) 5075 goto exit; 5076 } 5077 /* Add the unmodified original or prefix subflow. */ 5078 ret = flow_create_split_inner(dev, flow, &dev_flow, attr, 5079 items, ext_actions ? ext_actions : 5080 actions, flow_split_info, error); 5081 if (ret < 0) 5082 goto exit; 5083 MLX5_ASSERT(dev_flow); 5084 if (qrss) { 5085 const struct rte_flow_attr q_attr = { 5086 .group = MLX5_FLOW_MREG_ACT_TABLE_GROUP, 5087 .ingress = 1, 5088 }; 5089 /* Internal PMD action to set register. */ 5090 struct mlx5_rte_flow_item_tag q_tag_spec = { 5091 .data = qrss_id, 5092 .id = REG_NON, 5093 }; 5094 struct rte_flow_item q_items[] = { 5095 { 5096 .type = (enum rte_flow_item_type) 5097 MLX5_RTE_FLOW_ITEM_TYPE_TAG, 5098 .spec = &q_tag_spec, 5099 .last = NULL, 5100 .mask = NULL, 5101 }, 5102 { 5103 .type = RTE_FLOW_ITEM_TYPE_END, 5104 }, 5105 }; 5106 struct rte_flow_action q_actions[] = { 5107 { 5108 .type = qrss->type, 5109 .conf = qrss->conf, 5110 }, 5111 { 5112 .type = RTE_FLOW_ACTION_TYPE_END, 5113 }, 5114 }; 5115 uint64_t layers = flow_get_prefix_layer_flags(dev_flow); 5116 5117 /* 5118 * Configure the tag item only if there is no meter subflow. 5119 * Since tag is already marked in the meter suffix subflow 5120 * we can just use the meter suffix items as is. 5121 */ 5122 if (qrss_id) { 5123 /* Not meter subflow. */ 5124 MLX5_ASSERT(!mtr_sfx); 5125 /* 5126 * Put unique id in prefix flow due to it is destroyed 5127 * after suffix flow and id will be freed after there 5128 * is no actual flows with this id and identifier 5129 * reallocation becomes possible (for example, for 5130 * other flows in other threads). 5131 */ 5132 dev_flow->handle->split_flow_id = qrss_id; 5133 ret = mlx5_flow_get_reg_id(dev, MLX5_COPY_MARK, 0, 5134 error); 5135 if (ret < 0) 5136 goto exit; 5137 q_tag_spec.id = ret; 5138 } 5139 dev_flow = NULL; 5140 /* Add suffix subflow to execute Q/RSS. */ 5141 flow_split_info->prefix_layers = layers; 5142 flow_split_info->prefix_mark = 0; 5143 ret = flow_create_split_inner(dev, flow, &dev_flow, 5144 &q_attr, mtr_sfx ? items : 5145 q_items, q_actions, 5146 flow_split_info, error); 5147 if (ret < 0) 5148 goto exit; 5149 /* qrss ID should be freed if failed. */ 5150 qrss_id = 0; 5151 MLX5_ASSERT(dev_flow); 5152 } 5153 5154 exit: 5155 /* 5156 * We do not destroy the partially created sub_flows in case of error. 5157 * These ones are included into parent flow list and will be destroyed 5158 * by flow_drv_destroy. 5159 */ 5160 mlx5_ipool_free(priv->sh->ipool[MLX5_IPOOL_RSS_EXPANTION_FLOW_ID], 5161 qrss_id); 5162 mlx5_free(ext_actions); 5163 return ret; 5164 } 5165 5166 /** 5167 * The splitting for meter feature. 5168 * 5169 * - The meter flow will be split to two flows as prefix and 5170 * suffix flow. The packets make sense only it pass the prefix 5171 * meter action. 5172 * 5173 * - Reg_C_5 is used for the packet to match betweend prefix and 5174 * suffix flow. 5175 * 5176 * @param dev 5177 * Pointer to Ethernet device. 5178 * @param[in] flow 5179 * Parent flow structure pointer. 5180 * @param[in] attr 5181 * Flow rule attributes. 5182 * @param[in] items 5183 * Pattern specification (list terminated by the END pattern item). 5184 * @param[in] actions 5185 * Associated actions (list terminated by the END action). 5186 * @param[in] flow_split_info 5187 * Pointer to flow split info structure. 5188 * @param[out] error 5189 * Perform verbose error reporting if not NULL. 5190 * @return 5191 * 0 on success, negative value otherwise 5192 */ 5193 static int 5194 flow_create_split_meter(struct rte_eth_dev *dev, 5195 struct rte_flow *flow, 5196 const struct rte_flow_attr *attr, 5197 const struct rte_flow_item items[], 5198 const struct rte_flow_action actions[], 5199 struct mlx5_flow_split_info *flow_split_info, 5200 struct rte_flow_error *error) 5201 { 5202 struct mlx5_priv *priv = dev->data->dev_private; 5203 struct rte_flow_action *sfx_actions = NULL; 5204 struct rte_flow_action *pre_actions = NULL; 5205 struct rte_flow_item *sfx_items = NULL; 5206 struct mlx5_flow *dev_flow = NULL; 5207 struct rte_flow_attr sfx_attr = *attr; 5208 uint32_t mtr = 0; 5209 uint32_t mtr_tag_id = 0; 5210 size_t act_size; 5211 size_t item_size; 5212 int actions_n = 0; 5213 int ret; 5214 5215 if (priv->mtr_en) 5216 actions_n = flow_check_meter_action(actions, &mtr); 5217 if (mtr) { 5218 /* The five prefix actions: meter, decap, encap, tag, end. */ 5219 act_size = sizeof(struct rte_flow_action) * (actions_n + 5) + 5220 sizeof(struct mlx5_rte_flow_action_set_tag); 5221 /* tag, vlan, port id, end. */ 5222 #define METER_SUFFIX_ITEM 4 5223 item_size = sizeof(struct rte_flow_item) * METER_SUFFIX_ITEM + 5224 sizeof(struct mlx5_rte_flow_item_tag) * 2; 5225 sfx_actions = mlx5_malloc(MLX5_MEM_ZERO, (act_size + item_size), 5226 0, SOCKET_ID_ANY); 5227 if (!sfx_actions) 5228 return rte_flow_error_set(error, ENOMEM, 5229 RTE_FLOW_ERROR_TYPE_ACTION, 5230 NULL, "no memory to split " 5231 "meter flow"); 5232 sfx_items = (struct rte_flow_item *)((char *)sfx_actions + 5233 act_size); 5234 pre_actions = sfx_actions + actions_n; 5235 mtr_tag_id = flow_meter_split_prep(dev, items, sfx_items, 5236 actions, sfx_actions, 5237 pre_actions); 5238 if (!mtr_tag_id) { 5239 ret = -rte_errno; 5240 goto exit; 5241 } 5242 /* Add the prefix subflow. */ 5243 flow_split_info->prefix_mark = 0; 5244 ret = flow_create_split_inner(dev, flow, &dev_flow, 5245 attr, items, pre_actions, 5246 flow_split_info, error); 5247 if (ret) { 5248 ret = -rte_errno; 5249 goto exit; 5250 } 5251 dev_flow->handle->split_flow_id = mtr_tag_id; 5252 /* Setting the sfx group atrr. */ 5253 sfx_attr.group = sfx_attr.transfer ? 5254 (MLX5_FLOW_TABLE_LEVEL_SUFFIX - 1) : 5255 MLX5_FLOW_TABLE_LEVEL_SUFFIX; 5256 flow_split_info->prefix_layers = 5257 flow_get_prefix_layer_flags(dev_flow); 5258 flow_split_info->prefix_mark = dev_flow->handle->mark; 5259 } 5260 /* Add the prefix subflow. */ 5261 ret = flow_create_split_metadata(dev, flow, 5262 &sfx_attr, sfx_items ? 5263 sfx_items : items, 5264 sfx_actions ? sfx_actions : actions, 5265 flow_split_info, error); 5266 exit: 5267 if (sfx_actions) 5268 mlx5_free(sfx_actions); 5269 return ret; 5270 } 5271 5272 /** 5273 * The splitting for sample feature. 5274 * 5275 * Once Sample action is detected in the action list, the flow actions should 5276 * be split into prefix sub flow and suffix sub flow. 5277 * 5278 * The original items remain in the prefix sub flow, all actions preceding the 5279 * sample action and the sample action itself will be copied to the prefix 5280 * sub flow, the actions following the sample action will be copied to the 5281 * suffix sub flow, Queue action always be located in the suffix sub flow. 5282 * 5283 * In order to make the packet from prefix sub flow matches with suffix sub 5284 * flow, an extra tag action be added into prefix sub flow, and the suffix sub 5285 * flow uses tag item with the unique flow id. 5286 * 5287 * @param dev 5288 * Pointer to Ethernet device. 5289 * @param[in] flow 5290 * Parent flow structure pointer. 5291 * @param[in] attr 5292 * Flow rule attributes. 5293 * @param[in] items 5294 * Pattern specification (list terminated by the END pattern item). 5295 * @param[in] actions 5296 * Associated actions (list terminated by the END action). 5297 * @param[in] flow_split_info 5298 * Pointer to flow split info structure. 5299 * @param[out] error 5300 * Perform verbose error reporting if not NULL. 5301 * @return 5302 * 0 on success, negative value otherwise 5303 */ 5304 static int 5305 flow_create_split_sample(struct rte_eth_dev *dev, 5306 struct rte_flow *flow, 5307 const struct rte_flow_attr *attr, 5308 const struct rte_flow_item items[], 5309 const struct rte_flow_action actions[], 5310 struct mlx5_flow_split_info *flow_split_info, 5311 struct rte_flow_error *error) 5312 { 5313 struct mlx5_priv *priv = dev->data->dev_private; 5314 struct rte_flow_action *sfx_actions = NULL; 5315 struct rte_flow_action *pre_actions = NULL; 5316 struct rte_flow_item *sfx_items = NULL; 5317 struct mlx5_flow *dev_flow = NULL; 5318 struct rte_flow_attr sfx_attr = *attr; 5319 #ifdef HAVE_IBV_FLOW_DV_SUPPORT 5320 struct mlx5_flow_dv_sample_resource *sample_res; 5321 struct mlx5_flow_tbl_data_entry *sfx_tbl_data; 5322 struct mlx5_flow_tbl_resource *sfx_tbl; 5323 #endif 5324 size_t act_size; 5325 size_t item_size; 5326 uint32_t fdb_tx = 0; 5327 int32_t tag_id = 0; 5328 int actions_n = 0; 5329 int sample_action_pos; 5330 int qrss_action_pos; 5331 int add_tag = 0; 5332 int modify_after_mirror = 0; 5333 uint16_t jump_table = 0; 5334 const uint32_t next_ft_step = 1; 5335 int ret = 0; 5336 5337 if (priv->sampler_en) 5338 actions_n = flow_check_match_action(actions, attr, 5339 RTE_FLOW_ACTION_TYPE_SAMPLE, 5340 &sample_action_pos, &qrss_action_pos, 5341 &modify_after_mirror); 5342 if (actions_n) { 5343 /* The prefix actions must includes sample, tag, end. */ 5344 act_size = sizeof(struct rte_flow_action) * (actions_n * 2 + 1) 5345 + sizeof(struct mlx5_rte_flow_action_set_tag); 5346 item_size = sizeof(struct rte_flow_item) * SAMPLE_SUFFIX_ITEM + 5347 sizeof(struct mlx5_rte_flow_item_tag) * 2; 5348 sfx_actions = mlx5_malloc(MLX5_MEM_ZERO, (act_size + 5349 item_size), 0, SOCKET_ID_ANY); 5350 if (!sfx_actions) 5351 return rte_flow_error_set(error, ENOMEM, 5352 RTE_FLOW_ERROR_TYPE_ACTION, 5353 NULL, "no memory to split " 5354 "sample flow"); 5355 /* The representor_id is -1 for uplink. */ 5356 fdb_tx = (attr->transfer && priv->representor_id != -1); 5357 /* 5358 * When reg_c_preserve is set, metadata registers Cx preserve 5359 * their value even through packet duplication. 5360 */ 5361 add_tag = (!fdb_tx || priv->config.hca_attr.reg_c_preserve); 5362 if (add_tag) 5363 sfx_items = (struct rte_flow_item *)((char *)sfx_actions 5364 + act_size); 5365 if (modify_after_mirror) 5366 jump_table = attr->group * MLX5_FLOW_TABLE_FACTOR + 5367 next_ft_step; 5368 pre_actions = sfx_actions + actions_n; 5369 tag_id = flow_sample_split_prep(dev, add_tag, sfx_items, 5370 actions, sfx_actions, 5371 pre_actions, actions_n, 5372 sample_action_pos, 5373 qrss_action_pos, jump_table, 5374 error); 5375 if (tag_id < 0 || (add_tag && !tag_id)) { 5376 ret = -rte_errno; 5377 goto exit; 5378 } 5379 if (modify_after_mirror) 5380 flow_split_info->skip_scale = 5381 1 << MLX5_SCALE_JUMP_FLOW_GROUP_BIT; 5382 /* Add the prefix subflow. */ 5383 ret = flow_create_split_inner(dev, flow, &dev_flow, attr, 5384 items, pre_actions, 5385 flow_split_info, error); 5386 if (ret) { 5387 ret = -rte_errno; 5388 goto exit; 5389 } 5390 dev_flow->handle->split_flow_id = tag_id; 5391 #ifdef HAVE_IBV_FLOW_DV_SUPPORT 5392 if (!modify_after_mirror) { 5393 /* Set the sfx group attr. */ 5394 sample_res = (struct mlx5_flow_dv_sample_resource *) 5395 dev_flow->dv.sample_res; 5396 sfx_tbl = (struct mlx5_flow_tbl_resource *) 5397 sample_res->normal_path_tbl; 5398 sfx_tbl_data = container_of(sfx_tbl, 5399 struct mlx5_flow_tbl_data_entry, 5400 tbl); 5401 sfx_attr.group = sfx_attr.transfer ? 5402 (sfx_tbl_data->table_id - 1) : 5403 sfx_tbl_data->table_id; 5404 } else { 5405 MLX5_ASSERT(attr->transfer); 5406 sfx_attr.group = jump_table; 5407 } 5408 flow_split_info->prefix_layers = 5409 flow_get_prefix_layer_flags(dev_flow); 5410 flow_split_info->prefix_mark = dev_flow->handle->mark; 5411 /* Suffix group level already be scaled with factor, set 5412 * MLX5_SCALE_FLOW_GROUP_BIT of skip_scale to 1 to avoid scale 5413 * again in translation. 5414 */ 5415 flow_split_info->skip_scale = 1 << MLX5_SCALE_FLOW_GROUP_BIT; 5416 #endif 5417 } 5418 /* Add the suffix subflow. */ 5419 ret = flow_create_split_meter(dev, flow, &sfx_attr, 5420 sfx_items ? sfx_items : items, 5421 sfx_actions ? sfx_actions : actions, 5422 flow_split_info, error); 5423 exit: 5424 if (sfx_actions) 5425 mlx5_free(sfx_actions); 5426 return ret; 5427 } 5428 5429 /** 5430 * Split the flow to subflow set. The splitters might be linked 5431 * in the chain, like this: 5432 * flow_create_split_outer() calls: 5433 * flow_create_split_meter() calls: 5434 * flow_create_split_metadata(meter_subflow_0) calls: 5435 * flow_create_split_inner(metadata_subflow_0) 5436 * flow_create_split_inner(metadata_subflow_1) 5437 * flow_create_split_inner(metadata_subflow_2) 5438 * flow_create_split_metadata(meter_subflow_1) calls: 5439 * flow_create_split_inner(metadata_subflow_0) 5440 * flow_create_split_inner(metadata_subflow_1) 5441 * flow_create_split_inner(metadata_subflow_2) 5442 * 5443 * This provide flexible way to add new levels of flow splitting. 5444 * The all of successfully created subflows are included to the 5445 * parent flow dev_flow list. 5446 * 5447 * @param dev 5448 * Pointer to Ethernet device. 5449 * @param[in] flow 5450 * Parent flow structure pointer. 5451 * @param[in] attr 5452 * Flow rule attributes. 5453 * @param[in] items 5454 * Pattern specification (list terminated by the END pattern item). 5455 * @param[in] actions 5456 * Associated actions (list terminated by the END action). 5457 * @param[in] flow_split_info 5458 * Pointer to flow split info structure. 5459 * @param[out] error 5460 * Perform verbose error reporting if not NULL. 5461 * @return 5462 * 0 on success, negative value otherwise 5463 */ 5464 static int 5465 flow_create_split_outer(struct rte_eth_dev *dev, 5466 struct rte_flow *flow, 5467 const struct rte_flow_attr *attr, 5468 const struct rte_flow_item items[], 5469 const struct rte_flow_action actions[], 5470 struct mlx5_flow_split_info *flow_split_info, 5471 struct rte_flow_error *error) 5472 { 5473 int ret; 5474 5475 ret = flow_create_split_sample(dev, flow, attr, items, 5476 actions, flow_split_info, error); 5477 MLX5_ASSERT(ret <= 0); 5478 return ret; 5479 } 5480 5481 static struct mlx5_flow_tunnel * 5482 flow_tunnel_from_rule(struct rte_eth_dev *dev, 5483 const struct rte_flow_attr *attr, 5484 const struct rte_flow_item items[], 5485 const struct rte_flow_action actions[]) 5486 { 5487 struct mlx5_flow_tunnel *tunnel; 5488 5489 #pragma GCC diagnostic push 5490 #pragma GCC diagnostic ignored "-Wcast-qual" 5491 if (is_flow_tunnel_match_rule(dev, attr, items, actions)) 5492 tunnel = (struct mlx5_flow_tunnel *)items[0].spec; 5493 else if (is_flow_tunnel_steer_rule(dev, attr, items, actions)) 5494 tunnel = (struct mlx5_flow_tunnel *)actions[0].conf; 5495 else 5496 tunnel = NULL; 5497 #pragma GCC diagnostic pop 5498 5499 return tunnel; 5500 } 5501 5502 /** 5503 * Adjust flow RSS workspace if needed. 5504 * 5505 * @param wks 5506 * Pointer to thread flow work space. 5507 * @param rss_desc 5508 * Pointer to RSS descriptor. 5509 * @param[in] nrssq_num 5510 * New RSS queue number. 5511 * 5512 * @return 5513 * 0 on success, -1 otherwise and rte_errno is set. 5514 */ 5515 static int 5516 flow_rss_workspace_adjust(struct mlx5_flow_workspace *wks, 5517 struct mlx5_flow_rss_desc *rss_desc, 5518 uint32_t nrssq_num) 5519 { 5520 if (likely(nrssq_num <= wks->rssq_num)) 5521 return 0; 5522 rss_desc->queue = realloc(rss_desc->queue, 5523 sizeof(*rss_desc->queue) * RTE_ALIGN(nrssq_num, 2)); 5524 if (!rss_desc->queue) { 5525 rte_errno = ENOMEM; 5526 return -1; 5527 } 5528 wks->rssq_num = RTE_ALIGN(nrssq_num, 2); 5529 return 0; 5530 } 5531 5532 /** 5533 * Create a flow and add it to @p list. 5534 * 5535 * @param dev 5536 * Pointer to Ethernet device. 5537 * @param list 5538 * Pointer to a TAILQ flow list. If this parameter NULL, 5539 * no list insertion occurred, flow is just created, 5540 * this is caller's responsibility to track the 5541 * created flow. 5542 * @param[in] attr 5543 * Flow rule attributes. 5544 * @param[in] items 5545 * Pattern specification (list terminated by the END pattern item). 5546 * @param[in] actions 5547 * Associated actions (list terminated by the END action). 5548 * @param[in] external 5549 * This flow rule is created by request external to PMD. 5550 * @param[out] error 5551 * Perform verbose error reporting if not NULL. 5552 * 5553 * @return 5554 * A flow index on success, 0 otherwise and rte_errno is set. 5555 */ 5556 static uint32_t 5557 flow_list_create(struct rte_eth_dev *dev, uint32_t *list, 5558 const struct rte_flow_attr *attr, 5559 const struct rte_flow_item items[], 5560 const struct rte_flow_action original_actions[], 5561 bool external, struct rte_flow_error *error) 5562 { 5563 struct mlx5_priv *priv = dev->data->dev_private; 5564 struct rte_flow *flow = NULL; 5565 struct mlx5_flow *dev_flow; 5566 const struct rte_flow_action_rss *rss = NULL; 5567 struct mlx5_translated_shared_action 5568 shared_actions[MLX5_MAX_SHARED_ACTIONS]; 5569 int shared_actions_n = MLX5_MAX_SHARED_ACTIONS; 5570 union { 5571 struct mlx5_flow_expand_rss buf; 5572 uint8_t buffer[2048]; 5573 } expand_buffer; 5574 union { 5575 struct rte_flow_action actions[MLX5_MAX_SPLIT_ACTIONS]; 5576 uint8_t buffer[2048]; 5577 } actions_rx; 5578 union { 5579 struct rte_flow_action actions[MLX5_MAX_SPLIT_ACTIONS]; 5580 uint8_t buffer[2048]; 5581 } actions_hairpin_tx; 5582 union { 5583 struct rte_flow_item items[MLX5_MAX_SPLIT_ITEMS]; 5584 uint8_t buffer[2048]; 5585 } items_tx; 5586 struct mlx5_flow_expand_rss *buf = &expand_buffer.buf; 5587 struct mlx5_flow_rss_desc *rss_desc; 5588 const struct rte_flow_action *p_actions_rx; 5589 uint32_t i; 5590 uint32_t idx = 0; 5591 int hairpin_flow; 5592 struct rte_flow_attr attr_tx = { .priority = 0 }; 5593 const struct rte_flow_action *actions; 5594 struct rte_flow_action *translated_actions = NULL; 5595 struct mlx5_flow_tunnel *tunnel; 5596 struct tunnel_default_miss_ctx default_miss_ctx = { 0, }; 5597 struct mlx5_flow_workspace *wks = mlx5_flow_push_thread_workspace(); 5598 struct mlx5_flow_split_info flow_split_info = { 5599 .external = !!external, 5600 .skip_scale = 0, 5601 .flow_idx = 0, 5602 .prefix_mark = 0, 5603 .prefix_layers = 0 5604 }; 5605 int ret; 5606 5607 MLX5_ASSERT(wks); 5608 rss_desc = &wks->rss_desc; 5609 ret = flow_shared_actions_translate(dev, original_actions, 5610 shared_actions, 5611 &shared_actions_n, 5612 &translated_actions, error); 5613 if (ret < 0) { 5614 MLX5_ASSERT(translated_actions == NULL); 5615 return 0; 5616 } 5617 actions = translated_actions ? translated_actions : original_actions; 5618 p_actions_rx = actions; 5619 hairpin_flow = flow_check_hairpin_split(dev, attr, actions); 5620 ret = flow_drv_validate(dev, attr, items, p_actions_rx, 5621 external, hairpin_flow, error); 5622 if (ret < 0) 5623 goto error_before_hairpin_split; 5624 flow = mlx5_ipool_zmalloc(priv->sh->ipool[MLX5_IPOOL_RTE_FLOW], &idx); 5625 if (!flow) { 5626 rte_errno = ENOMEM; 5627 goto error_before_hairpin_split; 5628 } 5629 if (hairpin_flow > 0) { 5630 if (hairpin_flow > MLX5_MAX_SPLIT_ACTIONS) { 5631 rte_errno = EINVAL; 5632 goto error_before_hairpin_split; 5633 } 5634 flow_hairpin_split(dev, actions, actions_rx.actions, 5635 actions_hairpin_tx.actions, items_tx.items, 5636 idx); 5637 p_actions_rx = actions_rx.actions; 5638 } 5639 flow_split_info.flow_idx = idx; 5640 flow->drv_type = flow_get_drv_type(dev, attr); 5641 MLX5_ASSERT(flow->drv_type > MLX5_FLOW_TYPE_MIN && 5642 flow->drv_type < MLX5_FLOW_TYPE_MAX); 5643 memset(rss_desc, 0, offsetof(struct mlx5_flow_rss_desc, queue)); 5644 /* RSS Action only works on NIC RX domain */ 5645 if (attr->ingress && !attr->transfer) 5646 rss = flow_get_rss_action(p_actions_rx); 5647 if (rss) { 5648 if (flow_rss_workspace_adjust(wks, rss_desc, rss->queue_num)) 5649 return 0; 5650 /* 5651 * The following information is required by 5652 * mlx5_flow_hashfields_adjust() in advance. 5653 */ 5654 rss_desc->level = rss->level; 5655 /* RSS type 0 indicates default RSS type (ETH_RSS_IP). */ 5656 rss_desc->types = !rss->types ? ETH_RSS_IP : rss->types; 5657 } 5658 flow->dev_handles = 0; 5659 if (rss && rss->types) { 5660 unsigned int graph_root; 5661 5662 graph_root = find_graph_root(items, rss->level); 5663 ret = mlx5_flow_expand_rss(buf, sizeof(expand_buffer.buffer), 5664 items, rss->types, 5665 mlx5_support_expansion, graph_root); 5666 MLX5_ASSERT(ret > 0 && 5667 (unsigned int)ret < sizeof(expand_buffer.buffer)); 5668 } else { 5669 buf->entries = 1; 5670 buf->entry[0].pattern = (void *)(uintptr_t)items; 5671 } 5672 rss_desc->shared_rss = flow_get_shared_rss_action(dev, shared_actions, 5673 shared_actions_n); 5674 for (i = 0; i < buf->entries; ++i) { 5675 /* Initialize flow split data. */ 5676 flow_split_info.prefix_layers = 0; 5677 flow_split_info.prefix_mark = 0; 5678 flow_split_info.skip_scale = 0; 5679 /* 5680 * The splitter may create multiple dev_flows, 5681 * depending on configuration. In the simplest 5682 * case it just creates unmodified original flow. 5683 */ 5684 ret = flow_create_split_outer(dev, flow, attr, 5685 buf->entry[i].pattern, 5686 p_actions_rx, &flow_split_info, 5687 error); 5688 if (ret < 0) 5689 goto error; 5690 if (is_flow_tunnel_steer_rule(dev, attr, 5691 buf->entry[i].pattern, 5692 p_actions_rx)) { 5693 ret = flow_tunnel_add_default_miss(dev, flow, attr, 5694 p_actions_rx, 5695 idx, 5696 &default_miss_ctx, 5697 error); 5698 if (ret < 0) { 5699 mlx5_free(default_miss_ctx.queue); 5700 goto error; 5701 } 5702 } 5703 } 5704 /* Create the tx flow. */ 5705 if (hairpin_flow) { 5706 attr_tx.group = MLX5_HAIRPIN_TX_TABLE; 5707 attr_tx.ingress = 0; 5708 attr_tx.egress = 1; 5709 dev_flow = flow_drv_prepare(dev, flow, &attr_tx, items_tx.items, 5710 actions_hairpin_tx.actions, 5711 idx, error); 5712 if (!dev_flow) 5713 goto error; 5714 dev_flow->flow = flow; 5715 dev_flow->external = 0; 5716 SILIST_INSERT(&flow->dev_handles, dev_flow->handle_idx, 5717 dev_flow->handle, next); 5718 ret = flow_drv_translate(dev, dev_flow, &attr_tx, 5719 items_tx.items, 5720 actions_hairpin_tx.actions, error); 5721 if (ret < 0) 5722 goto error; 5723 } 5724 /* 5725 * Update the metadata register copy table. If extensive 5726 * metadata feature is enabled and registers are supported 5727 * we might create the extra rte_flow for each unique 5728 * MARK/FLAG action ID. 5729 * 5730 * The table is updated for ingress Flows only, because 5731 * the egress Flows belong to the different device and 5732 * copy table should be updated in peer NIC Rx domain. 5733 */ 5734 if (attr->ingress && 5735 (external || attr->group != MLX5_FLOW_MREG_CP_TABLE_GROUP)) { 5736 ret = flow_mreg_update_copy_table(dev, flow, actions, error); 5737 if (ret) 5738 goto error; 5739 } 5740 /* 5741 * If the flow is external (from application) OR device is started, 5742 * OR mreg discover, then apply immediately. 5743 */ 5744 if (external || dev->data->dev_started || 5745 (attr->group == MLX5_FLOW_MREG_CP_TABLE_GROUP && 5746 attr->priority == MLX5_FLOW_LOWEST_PRIO_INDICATOR)) { 5747 ret = flow_drv_apply(dev, flow, error); 5748 if (ret < 0) 5749 goto error; 5750 } 5751 if (list) { 5752 rte_spinlock_lock(&priv->flow_list_lock); 5753 ILIST_INSERT(priv->sh->ipool[MLX5_IPOOL_RTE_FLOW], list, idx, 5754 flow, next); 5755 rte_spinlock_unlock(&priv->flow_list_lock); 5756 } 5757 flow_rxq_flags_set(dev, flow); 5758 rte_free(translated_actions); 5759 tunnel = flow_tunnel_from_rule(dev, attr, items, actions); 5760 if (tunnel) { 5761 flow->tunnel = 1; 5762 flow->tunnel_id = tunnel->tunnel_id; 5763 __atomic_add_fetch(&tunnel->refctn, 1, __ATOMIC_RELAXED); 5764 mlx5_free(default_miss_ctx.queue); 5765 } 5766 mlx5_flow_pop_thread_workspace(); 5767 return idx; 5768 error: 5769 MLX5_ASSERT(flow); 5770 ret = rte_errno; /* Save rte_errno before cleanup. */ 5771 flow_mreg_del_copy_action(dev, flow); 5772 flow_drv_destroy(dev, flow); 5773 if (rss_desc->shared_rss) 5774 __atomic_sub_fetch(&((struct mlx5_shared_action_rss *) 5775 mlx5_ipool_get 5776 (priv->sh->ipool[MLX5_IPOOL_RSS_SHARED_ACTIONS], 5777 rss_desc->shared_rss))->refcnt, 1, __ATOMIC_RELAXED); 5778 mlx5_ipool_free(priv->sh->ipool[MLX5_IPOOL_RTE_FLOW], idx); 5779 rte_errno = ret; /* Restore rte_errno. */ 5780 ret = rte_errno; 5781 rte_errno = ret; 5782 mlx5_flow_pop_thread_workspace(); 5783 error_before_hairpin_split: 5784 rte_free(translated_actions); 5785 return 0; 5786 } 5787 5788 /** 5789 * Create a dedicated flow rule on e-switch table 0 (root table), to direct all 5790 * incoming packets to table 1. 5791 * 5792 * Other flow rules, requested for group n, will be created in 5793 * e-switch table n+1. 5794 * Jump action to e-switch group n will be created to group n+1. 5795 * 5796 * Used when working in switchdev mode, to utilise advantages of table 1 5797 * and above. 5798 * 5799 * @param dev 5800 * Pointer to Ethernet device. 5801 * 5802 * @return 5803 * Pointer to flow on success, NULL otherwise and rte_errno is set. 5804 */ 5805 struct rte_flow * 5806 mlx5_flow_create_esw_table_zero_flow(struct rte_eth_dev *dev) 5807 { 5808 const struct rte_flow_attr attr = { 5809 .group = 0, 5810 .priority = 0, 5811 .ingress = 1, 5812 .egress = 0, 5813 .transfer = 1, 5814 }; 5815 const struct rte_flow_item pattern = { 5816 .type = RTE_FLOW_ITEM_TYPE_END, 5817 }; 5818 struct rte_flow_action_jump jump = { 5819 .group = 1, 5820 }; 5821 const struct rte_flow_action actions[] = { 5822 { 5823 .type = RTE_FLOW_ACTION_TYPE_JUMP, 5824 .conf = &jump, 5825 }, 5826 { 5827 .type = RTE_FLOW_ACTION_TYPE_END, 5828 }, 5829 }; 5830 struct mlx5_priv *priv = dev->data->dev_private; 5831 struct rte_flow_error error; 5832 5833 return (void *)(uintptr_t)flow_list_create(dev, &priv->ctrl_flows, 5834 &attr, &pattern, 5835 actions, false, &error); 5836 } 5837 5838 /** 5839 * Validate a flow supported by the NIC. 5840 * 5841 * @see rte_flow_validate() 5842 * @see rte_flow_ops 5843 */ 5844 int 5845 mlx5_flow_validate(struct rte_eth_dev *dev, 5846 const struct rte_flow_attr *attr, 5847 const struct rte_flow_item items[], 5848 const struct rte_flow_action original_actions[], 5849 struct rte_flow_error *error) 5850 { 5851 int hairpin_flow; 5852 struct mlx5_translated_shared_action 5853 shared_actions[MLX5_MAX_SHARED_ACTIONS]; 5854 int shared_actions_n = MLX5_MAX_SHARED_ACTIONS; 5855 const struct rte_flow_action *actions; 5856 struct rte_flow_action *translated_actions = NULL; 5857 int ret = flow_shared_actions_translate(dev, original_actions, 5858 shared_actions, 5859 &shared_actions_n, 5860 &translated_actions, error); 5861 5862 if (ret) 5863 return ret; 5864 actions = translated_actions ? translated_actions : original_actions; 5865 hairpin_flow = flow_check_hairpin_split(dev, attr, actions); 5866 ret = flow_drv_validate(dev, attr, items, actions, 5867 true, hairpin_flow, error); 5868 rte_free(translated_actions); 5869 return ret; 5870 } 5871 5872 /** 5873 * Create a flow. 5874 * 5875 * @see rte_flow_create() 5876 * @see rte_flow_ops 5877 */ 5878 struct rte_flow * 5879 mlx5_flow_create(struct rte_eth_dev *dev, 5880 const struct rte_flow_attr *attr, 5881 const struct rte_flow_item items[], 5882 const struct rte_flow_action actions[], 5883 struct rte_flow_error *error) 5884 { 5885 struct mlx5_priv *priv = dev->data->dev_private; 5886 5887 /* 5888 * If the device is not started yet, it is not allowed to created a 5889 * flow from application. PMD default flows and traffic control flows 5890 * are not affected. 5891 */ 5892 if (unlikely(!dev->data->dev_started)) { 5893 DRV_LOG(DEBUG, "port %u is not started when " 5894 "inserting a flow", dev->data->port_id); 5895 rte_flow_error_set(error, ENODEV, 5896 RTE_FLOW_ERROR_TYPE_UNSPECIFIED, 5897 NULL, 5898 "port not started"); 5899 return NULL; 5900 } 5901 5902 return (void *)(uintptr_t)flow_list_create(dev, &priv->flows, 5903 attr, items, actions, true, error); 5904 } 5905 5906 /** 5907 * Destroy a flow in a list. 5908 * 5909 * @param dev 5910 * Pointer to Ethernet device. 5911 * @param list 5912 * Pointer to the Indexed flow list. If this parameter NULL, 5913 * there is no flow removal from the list. Be noted that as 5914 * flow is add to the indexed list, memory of the indexed 5915 * list points to maybe changed as flow destroyed. 5916 * @param[in] flow_idx 5917 * Index of flow to destroy. 5918 */ 5919 static void 5920 flow_list_destroy(struct rte_eth_dev *dev, uint32_t *list, 5921 uint32_t flow_idx) 5922 { 5923 struct mlx5_priv *priv = dev->data->dev_private; 5924 struct rte_flow *flow = mlx5_ipool_get(priv->sh->ipool 5925 [MLX5_IPOOL_RTE_FLOW], flow_idx); 5926 5927 if (!flow) 5928 return; 5929 /* 5930 * Update RX queue flags only if port is started, otherwise it is 5931 * already clean. 5932 */ 5933 if (dev->data->dev_started) 5934 flow_rxq_flags_trim(dev, flow); 5935 flow_drv_destroy(dev, flow); 5936 if (list) { 5937 rte_spinlock_lock(&priv->flow_list_lock); 5938 ILIST_REMOVE(priv->sh->ipool[MLX5_IPOOL_RTE_FLOW], list, 5939 flow_idx, flow, next); 5940 rte_spinlock_unlock(&priv->flow_list_lock); 5941 } 5942 if (flow->tunnel) { 5943 struct mlx5_flow_tunnel *tunnel; 5944 5945 tunnel = mlx5_find_tunnel_id(dev, flow->tunnel_id); 5946 RTE_VERIFY(tunnel); 5947 if (!__atomic_sub_fetch(&tunnel->refctn, 1, __ATOMIC_RELAXED)) 5948 mlx5_flow_tunnel_free(dev, tunnel); 5949 } 5950 flow_mreg_del_copy_action(dev, flow); 5951 mlx5_ipool_free(priv->sh->ipool[MLX5_IPOOL_RTE_FLOW], flow_idx); 5952 } 5953 5954 /** 5955 * Destroy all flows. 5956 * 5957 * @param dev 5958 * Pointer to Ethernet device. 5959 * @param list 5960 * Pointer to the Indexed flow list. 5961 * @param active 5962 * If flushing is called avtively. 5963 */ 5964 void 5965 mlx5_flow_list_flush(struct rte_eth_dev *dev, uint32_t *list, bool active) 5966 { 5967 uint32_t num_flushed = 0; 5968 5969 while (*list) { 5970 flow_list_destroy(dev, list, *list); 5971 num_flushed++; 5972 } 5973 if (active) { 5974 DRV_LOG(INFO, "port %u: %u flows flushed before stopping", 5975 dev->data->port_id, num_flushed); 5976 } 5977 } 5978 5979 /** 5980 * Stop all default actions for flows. 5981 * 5982 * @param dev 5983 * Pointer to Ethernet device. 5984 */ 5985 void 5986 mlx5_flow_stop_default(struct rte_eth_dev *dev) 5987 { 5988 flow_mreg_del_default_copy_action(dev); 5989 flow_rxq_flags_clear(dev); 5990 } 5991 5992 /** 5993 * Start all default actions for flows. 5994 * 5995 * @param dev 5996 * Pointer to Ethernet device. 5997 * @return 5998 * 0 on success, a negative errno value otherwise and rte_errno is set. 5999 */ 6000 int 6001 mlx5_flow_start_default(struct rte_eth_dev *dev) 6002 { 6003 struct rte_flow_error error; 6004 6005 /* Make sure default copy action (reg_c[0] -> reg_b) is created. */ 6006 return flow_mreg_add_default_copy_action(dev, &error); 6007 } 6008 6009 /** 6010 * Release key of thread specific flow workspace data. 6011 */ 6012 void 6013 flow_release_workspace(void *data) 6014 { 6015 struct mlx5_flow_workspace *wks = data; 6016 struct mlx5_flow_workspace *next; 6017 6018 while (wks) { 6019 next = wks->next; 6020 free(wks->rss_desc.queue); 6021 free(wks); 6022 wks = next; 6023 } 6024 } 6025 6026 /** 6027 * Get thread specific current flow workspace. 6028 * 6029 * @return pointer to thread specific flow workspace data, NULL on error. 6030 */ 6031 struct mlx5_flow_workspace* 6032 mlx5_flow_get_thread_workspace(void) 6033 { 6034 struct mlx5_flow_workspace *data; 6035 6036 data = mlx5_flow_os_get_specific_workspace(); 6037 MLX5_ASSERT(data && data->inuse); 6038 if (!data || !data->inuse) 6039 DRV_LOG(ERR, "flow workspace not initialized."); 6040 return data; 6041 } 6042 6043 /** 6044 * Allocate and init new flow workspace. 6045 * 6046 * @return pointer to flow workspace data, NULL on error. 6047 */ 6048 static struct mlx5_flow_workspace* 6049 flow_alloc_thread_workspace(void) 6050 { 6051 struct mlx5_flow_workspace *data = calloc(1, sizeof(*data)); 6052 6053 if (!data) { 6054 DRV_LOG(ERR, "Failed to allocate flow workspace " 6055 "memory."); 6056 return NULL; 6057 } 6058 data->rss_desc.queue = calloc(1, 6059 sizeof(uint16_t) * MLX5_RSSQ_DEFAULT_NUM); 6060 if (!data->rss_desc.queue) 6061 goto err; 6062 data->rssq_num = MLX5_RSSQ_DEFAULT_NUM; 6063 return data; 6064 err: 6065 if (data->rss_desc.queue) 6066 free(data->rss_desc.queue); 6067 free(data); 6068 return NULL; 6069 } 6070 6071 /** 6072 * Get new thread specific flow workspace. 6073 * 6074 * If current workspace inuse, create new one and set as current. 6075 * 6076 * @return pointer to thread specific flow workspace data, NULL on error. 6077 */ 6078 static struct mlx5_flow_workspace* 6079 mlx5_flow_push_thread_workspace(void) 6080 { 6081 struct mlx5_flow_workspace *curr; 6082 struct mlx5_flow_workspace *data; 6083 6084 curr = mlx5_flow_os_get_specific_workspace(); 6085 if (!curr) { 6086 data = flow_alloc_thread_workspace(); 6087 if (!data) 6088 return NULL; 6089 } else if (!curr->inuse) { 6090 data = curr; 6091 } else if (curr->next) { 6092 data = curr->next; 6093 } else { 6094 data = flow_alloc_thread_workspace(); 6095 if (!data) 6096 return NULL; 6097 curr->next = data; 6098 data->prev = curr; 6099 } 6100 data->inuse = 1; 6101 data->flow_idx = 0; 6102 /* Set as current workspace */ 6103 if (mlx5_flow_os_set_specific_workspace(data)) 6104 DRV_LOG(ERR, "Failed to set flow workspace to thread."); 6105 return data; 6106 } 6107 6108 /** 6109 * Close current thread specific flow workspace. 6110 * 6111 * If previous workspace available, set it as current. 6112 * 6113 * @return pointer to thread specific flow workspace data, NULL on error. 6114 */ 6115 static void 6116 mlx5_flow_pop_thread_workspace(void) 6117 { 6118 struct mlx5_flow_workspace *data = mlx5_flow_get_thread_workspace(); 6119 6120 if (!data) 6121 return; 6122 if (!data->inuse) { 6123 DRV_LOG(ERR, "Failed to close unused flow workspace."); 6124 return; 6125 } 6126 data->inuse = 0; 6127 if (!data->prev) 6128 return; 6129 if (mlx5_flow_os_set_specific_workspace(data->prev)) 6130 DRV_LOG(ERR, "Failed to set flow workspace to thread."); 6131 } 6132 6133 /** 6134 * Verify the flow list is empty 6135 * 6136 * @param dev 6137 * Pointer to Ethernet device. 6138 * 6139 * @return the number of flows not released. 6140 */ 6141 int 6142 mlx5_flow_verify(struct rte_eth_dev *dev) 6143 { 6144 struct mlx5_priv *priv = dev->data->dev_private; 6145 struct rte_flow *flow; 6146 uint32_t idx; 6147 int ret = 0; 6148 6149 ILIST_FOREACH(priv->sh->ipool[MLX5_IPOOL_RTE_FLOW], priv->flows, idx, 6150 flow, next) { 6151 DRV_LOG(DEBUG, "port %u flow %p still referenced", 6152 dev->data->port_id, (void *)flow); 6153 ++ret; 6154 } 6155 return ret; 6156 } 6157 6158 /** 6159 * Enable default hairpin egress flow. 6160 * 6161 * @param dev 6162 * Pointer to Ethernet device. 6163 * @param queue 6164 * The queue index. 6165 * 6166 * @return 6167 * 0 on success, a negative errno value otherwise and rte_errno is set. 6168 */ 6169 int 6170 mlx5_ctrl_flow_source_queue(struct rte_eth_dev *dev, 6171 uint32_t queue) 6172 { 6173 struct mlx5_priv *priv = dev->data->dev_private; 6174 const struct rte_flow_attr attr = { 6175 .egress = 1, 6176 .priority = 0, 6177 }; 6178 struct mlx5_rte_flow_item_tx_queue queue_spec = { 6179 .queue = queue, 6180 }; 6181 struct mlx5_rte_flow_item_tx_queue queue_mask = { 6182 .queue = UINT32_MAX, 6183 }; 6184 struct rte_flow_item items[] = { 6185 { 6186 .type = (enum rte_flow_item_type) 6187 MLX5_RTE_FLOW_ITEM_TYPE_TX_QUEUE, 6188 .spec = &queue_spec, 6189 .last = NULL, 6190 .mask = &queue_mask, 6191 }, 6192 { 6193 .type = RTE_FLOW_ITEM_TYPE_END, 6194 }, 6195 }; 6196 struct rte_flow_action_jump jump = { 6197 .group = MLX5_HAIRPIN_TX_TABLE, 6198 }; 6199 struct rte_flow_action actions[2]; 6200 uint32_t flow_idx; 6201 struct rte_flow_error error; 6202 6203 actions[0].type = RTE_FLOW_ACTION_TYPE_JUMP; 6204 actions[0].conf = &jump; 6205 actions[1].type = RTE_FLOW_ACTION_TYPE_END; 6206 flow_idx = flow_list_create(dev, &priv->ctrl_flows, 6207 &attr, items, actions, false, &error); 6208 if (!flow_idx) { 6209 DRV_LOG(DEBUG, 6210 "Failed to create ctrl flow: rte_errno(%d)," 6211 " type(%d), message(%s)", 6212 rte_errno, error.type, 6213 error.message ? error.message : " (no stated reason)"); 6214 return -rte_errno; 6215 } 6216 return 0; 6217 } 6218 6219 /** 6220 * Enable a control flow configured from the control plane. 6221 * 6222 * @param dev 6223 * Pointer to Ethernet device. 6224 * @param eth_spec 6225 * An Ethernet flow spec to apply. 6226 * @param eth_mask 6227 * An Ethernet flow mask to apply. 6228 * @param vlan_spec 6229 * A VLAN flow spec to apply. 6230 * @param vlan_mask 6231 * A VLAN flow mask to apply. 6232 * 6233 * @return 6234 * 0 on success, a negative errno value otherwise and rte_errno is set. 6235 */ 6236 int 6237 mlx5_ctrl_flow_vlan(struct rte_eth_dev *dev, 6238 struct rte_flow_item_eth *eth_spec, 6239 struct rte_flow_item_eth *eth_mask, 6240 struct rte_flow_item_vlan *vlan_spec, 6241 struct rte_flow_item_vlan *vlan_mask) 6242 { 6243 struct mlx5_priv *priv = dev->data->dev_private; 6244 const struct rte_flow_attr attr = { 6245 .ingress = 1, 6246 .priority = MLX5_FLOW_LOWEST_PRIO_INDICATOR, 6247 }; 6248 struct rte_flow_item items[] = { 6249 { 6250 .type = RTE_FLOW_ITEM_TYPE_ETH, 6251 .spec = eth_spec, 6252 .last = NULL, 6253 .mask = eth_mask, 6254 }, 6255 { 6256 .type = (vlan_spec) ? RTE_FLOW_ITEM_TYPE_VLAN : 6257 RTE_FLOW_ITEM_TYPE_END, 6258 .spec = vlan_spec, 6259 .last = NULL, 6260 .mask = vlan_mask, 6261 }, 6262 { 6263 .type = RTE_FLOW_ITEM_TYPE_END, 6264 }, 6265 }; 6266 uint16_t queue[priv->reta_idx_n]; 6267 struct rte_flow_action_rss action_rss = { 6268 .func = RTE_ETH_HASH_FUNCTION_DEFAULT, 6269 .level = 0, 6270 .types = priv->rss_conf.rss_hf, 6271 .key_len = priv->rss_conf.rss_key_len, 6272 .queue_num = priv->reta_idx_n, 6273 .key = priv->rss_conf.rss_key, 6274 .queue = queue, 6275 }; 6276 struct rte_flow_action actions[] = { 6277 { 6278 .type = RTE_FLOW_ACTION_TYPE_RSS, 6279 .conf = &action_rss, 6280 }, 6281 { 6282 .type = RTE_FLOW_ACTION_TYPE_END, 6283 }, 6284 }; 6285 uint32_t flow_idx; 6286 struct rte_flow_error error; 6287 unsigned int i; 6288 6289 if (!priv->reta_idx_n || !priv->rxqs_n) { 6290 return 0; 6291 } 6292 if (!(dev->data->dev_conf.rxmode.mq_mode & ETH_MQ_RX_RSS_FLAG)) 6293 action_rss.types = 0; 6294 for (i = 0; i != priv->reta_idx_n; ++i) 6295 queue[i] = (*priv->reta_idx)[i]; 6296 flow_idx = flow_list_create(dev, &priv->ctrl_flows, 6297 &attr, items, actions, false, &error); 6298 if (!flow_idx) 6299 return -rte_errno; 6300 return 0; 6301 } 6302 6303 /** 6304 * Enable a flow control configured from the control plane. 6305 * 6306 * @param dev 6307 * Pointer to Ethernet device. 6308 * @param eth_spec 6309 * An Ethernet flow spec to apply. 6310 * @param eth_mask 6311 * An Ethernet flow mask to apply. 6312 * 6313 * @return 6314 * 0 on success, a negative errno value otherwise and rte_errno is set. 6315 */ 6316 int 6317 mlx5_ctrl_flow(struct rte_eth_dev *dev, 6318 struct rte_flow_item_eth *eth_spec, 6319 struct rte_flow_item_eth *eth_mask) 6320 { 6321 return mlx5_ctrl_flow_vlan(dev, eth_spec, eth_mask, NULL, NULL); 6322 } 6323 6324 /** 6325 * Create default miss flow rule matching lacp traffic 6326 * 6327 * @param dev 6328 * Pointer to Ethernet device. 6329 * @param eth_spec 6330 * An Ethernet flow spec to apply. 6331 * 6332 * @return 6333 * 0 on success, a negative errno value otherwise and rte_errno is set. 6334 */ 6335 int 6336 mlx5_flow_lacp_miss(struct rte_eth_dev *dev) 6337 { 6338 struct mlx5_priv *priv = dev->data->dev_private; 6339 /* 6340 * The LACP matching is done by only using ether type since using 6341 * a multicast dst mac causes kernel to give low priority to this flow. 6342 */ 6343 static const struct rte_flow_item_eth lacp_spec = { 6344 .type = RTE_BE16(0x8809), 6345 }; 6346 static const struct rte_flow_item_eth lacp_mask = { 6347 .type = 0xffff, 6348 }; 6349 const struct rte_flow_attr attr = { 6350 .ingress = 1, 6351 }; 6352 struct rte_flow_item items[] = { 6353 { 6354 .type = RTE_FLOW_ITEM_TYPE_ETH, 6355 .spec = &lacp_spec, 6356 .mask = &lacp_mask, 6357 }, 6358 { 6359 .type = RTE_FLOW_ITEM_TYPE_END, 6360 }, 6361 }; 6362 struct rte_flow_action actions[] = { 6363 { 6364 .type = (enum rte_flow_action_type) 6365 MLX5_RTE_FLOW_ACTION_TYPE_DEFAULT_MISS, 6366 }, 6367 { 6368 .type = RTE_FLOW_ACTION_TYPE_END, 6369 }, 6370 }; 6371 struct rte_flow_error error; 6372 uint32_t flow_idx = flow_list_create(dev, &priv->ctrl_flows, 6373 &attr, items, actions, false, &error); 6374 6375 if (!flow_idx) 6376 return -rte_errno; 6377 return 0; 6378 } 6379 6380 /** 6381 * Destroy a flow. 6382 * 6383 * @see rte_flow_destroy() 6384 * @see rte_flow_ops 6385 */ 6386 int 6387 mlx5_flow_destroy(struct rte_eth_dev *dev, 6388 struct rte_flow *flow, 6389 struct rte_flow_error *error __rte_unused) 6390 { 6391 struct mlx5_priv *priv = dev->data->dev_private; 6392 6393 flow_list_destroy(dev, &priv->flows, (uintptr_t)(void *)flow); 6394 return 0; 6395 } 6396 6397 /** 6398 * Destroy all flows. 6399 * 6400 * @see rte_flow_flush() 6401 * @see rte_flow_ops 6402 */ 6403 int 6404 mlx5_flow_flush(struct rte_eth_dev *dev, 6405 struct rte_flow_error *error __rte_unused) 6406 { 6407 struct mlx5_priv *priv = dev->data->dev_private; 6408 6409 mlx5_flow_list_flush(dev, &priv->flows, false); 6410 return 0; 6411 } 6412 6413 /** 6414 * Isolated mode. 6415 * 6416 * @see rte_flow_isolate() 6417 * @see rte_flow_ops 6418 */ 6419 int 6420 mlx5_flow_isolate(struct rte_eth_dev *dev, 6421 int enable, 6422 struct rte_flow_error *error) 6423 { 6424 struct mlx5_priv *priv = dev->data->dev_private; 6425 6426 if (dev->data->dev_started) { 6427 rte_flow_error_set(error, EBUSY, 6428 RTE_FLOW_ERROR_TYPE_UNSPECIFIED, 6429 NULL, 6430 "port must be stopped first"); 6431 return -rte_errno; 6432 } 6433 priv->isolated = !!enable; 6434 if (enable) 6435 dev->dev_ops = &mlx5_dev_ops_isolate; 6436 else 6437 dev->dev_ops = &mlx5_dev_ops; 6438 6439 dev->rx_descriptor_status = mlx5_rx_descriptor_status; 6440 dev->tx_descriptor_status = mlx5_tx_descriptor_status; 6441 6442 return 0; 6443 } 6444 6445 /** 6446 * Query a flow. 6447 * 6448 * @see rte_flow_query() 6449 * @see rte_flow_ops 6450 */ 6451 static int 6452 flow_drv_query(struct rte_eth_dev *dev, 6453 uint32_t flow_idx, 6454 const struct rte_flow_action *actions, 6455 void *data, 6456 struct rte_flow_error *error) 6457 { 6458 struct mlx5_priv *priv = dev->data->dev_private; 6459 const struct mlx5_flow_driver_ops *fops; 6460 struct rte_flow *flow = mlx5_ipool_get(priv->sh->ipool 6461 [MLX5_IPOOL_RTE_FLOW], 6462 flow_idx); 6463 enum mlx5_flow_drv_type ftype; 6464 6465 if (!flow) { 6466 return rte_flow_error_set(error, ENOENT, 6467 RTE_FLOW_ERROR_TYPE_UNSPECIFIED, 6468 NULL, 6469 "invalid flow handle"); 6470 } 6471 ftype = flow->drv_type; 6472 MLX5_ASSERT(ftype > MLX5_FLOW_TYPE_MIN && ftype < MLX5_FLOW_TYPE_MAX); 6473 fops = flow_get_drv_ops(ftype); 6474 6475 return fops->query(dev, flow, actions, data, error); 6476 } 6477 6478 /** 6479 * Query a flow. 6480 * 6481 * @see rte_flow_query() 6482 * @see rte_flow_ops 6483 */ 6484 int 6485 mlx5_flow_query(struct rte_eth_dev *dev, 6486 struct rte_flow *flow, 6487 const struct rte_flow_action *actions, 6488 void *data, 6489 struct rte_flow_error *error) 6490 { 6491 int ret; 6492 6493 ret = flow_drv_query(dev, (uintptr_t)(void *)flow, actions, data, 6494 error); 6495 if (ret < 0) 6496 return ret; 6497 return 0; 6498 } 6499 6500 /** 6501 * Get rte_flow callbacks. 6502 * 6503 * @param dev 6504 * Pointer to Ethernet device structure. 6505 * @param ops 6506 * Pointer to operation-specific structure. 6507 * 6508 * @return 0 6509 */ 6510 int 6511 mlx5_flow_ops_get(struct rte_eth_dev *dev __rte_unused, 6512 const struct rte_flow_ops **ops) 6513 { 6514 *ops = &mlx5_flow_ops; 6515 return 0; 6516 } 6517 6518 /** 6519 * Create the needed meter and suffix tables. 6520 * 6521 * @param[in] dev 6522 * Pointer to Ethernet device. 6523 * @param[in] fm 6524 * Pointer to the flow meter. 6525 * 6526 * @return 6527 * Pointer to table set on success, NULL otherwise. 6528 */ 6529 struct mlx5_meter_domains_infos * 6530 mlx5_flow_create_mtr_tbls(struct rte_eth_dev *dev, 6531 const struct mlx5_flow_meter *fm) 6532 { 6533 const struct mlx5_flow_driver_ops *fops; 6534 6535 fops = flow_get_drv_ops(MLX5_FLOW_TYPE_DV); 6536 return fops->create_mtr_tbls(dev, fm); 6537 } 6538 6539 /** 6540 * Destroy the meter table set. 6541 * 6542 * @param[in] dev 6543 * Pointer to Ethernet device. 6544 * @param[in] tbl 6545 * Pointer to the meter table set. 6546 * 6547 * @return 6548 * 0 on success. 6549 */ 6550 int 6551 mlx5_flow_destroy_mtr_tbls(struct rte_eth_dev *dev, 6552 struct mlx5_meter_domains_infos *tbls) 6553 { 6554 const struct mlx5_flow_driver_ops *fops; 6555 6556 fops = flow_get_drv_ops(MLX5_FLOW_TYPE_DV); 6557 return fops->destroy_mtr_tbls(dev, tbls); 6558 } 6559 6560 /** 6561 * Create policer rules. 6562 * 6563 * @param[in] dev 6564 * Pointer to Ethernet device. 6565 * @param[in] fm 6566 * Pointer to flow meter structure. 6567 * @param[in] attr 6568 * Pointer to flow attributes. 6569 * 6570 * @return 6571 * 0 on success, -1 otherwise. 6572 */ 6573 int 6574 mlx5_flow_create_policer_rules(struct rte_eth_dev *dev, 6575 struct mlx5_flow_meter *fm, 6576 const struct rte_flow_attr *attr) 6577 { 6578 const struct mlx5_flow_driver_ops *fops; 6579 6580 fops = flow_get_drv_ops(MLX5_FLOW_TYPE_DV); 6581 return fops->create_policer_rules(dev, fm, attr); 6582 } 6583 6584 /** 6585 * Destroy policer rules. 6586 * 6587 * @param[in] fm 6588 * Pointer to flow meter structure. 6589 * @param[in] attr 6590 * Pointer to flow attributes. 6591 * 6592 * @return 6593 * 0 on success, -1 otherwise. 6594 */ 6595 int 6596 mlx5_flow_destroy_policer_rules(struct rte_eth_dev *dev, 6597 struct mlx5_flow_meter *fm, 6598 const struct rte_flow_attr *attr) 6599 { 6600 const struct mlx5_flow_driver_ops *fops; 6601 6602 fops = flow_get_drv_ops(MLX5_FLOW_TYPE_DV); 6603 return fops->destroy_policer_rules(dev, fm, attr); 6604 } 6605 6606 /** 6607 * Allocate a counter. 6608 * 6609 * @param[in] dev 6610 * Pointer to Ethernet device structure. 6611 * 6612 * @return 6613 * Index to allocated counter on success, 0 otherwise. 6614 */ 6615 uint32_t 6616 mlx5_counter_alloc(struct rte_eth_dev *dev) 6617 { 6618 const struct mlx5_flow_driver_ops *fops; 6619 struct rte_flow_attr attr = { .transfer = 0 }; 6620 6621 if (flow_get_drv_type(dev, &attr) == MLX5_FLOW_TYPE_DV) { 6622 fops = flow_get_drv_ops(MLX5_FLOW_TYPE_DV); 6623 return fops->counter_alloc(dev); 6624 } 6625 DRV_LOG(ERR, 6626 "port %u counter allocate is not supported.", 6627 dev->data->port_id); 6628 return 0; 6629 } 6630 6631 /** 6632 * Free a counter. 6633 * 6634 * @param[in] dev 6635 * Pointer to Ethernet device structure. 6636 * @param[in] cnt 6637 * Index to counter to be free. 6638 */ 6639 void 6640 mlx5_counter_free(struct rte_eth_dev *dev, uint32_t cnt) 6641 { 6642 const struct mlx5_flow_driver_ops *fops; 6643 struct rte_flow_attr attr = { .transfer = 0 }; 6644 6645 if (flow_get_drv_type(dev, &attr) == MLX5_FLOW_TYPE_DV) { 6646 fops = flow_get_drv_ops(MLX5_FLOW_TYPE_DV); 6647 fops->counter_free(dev, cnt); 6648 return; 6649 } 6650 DRV_LOG(ERR, 6651 "port %u counter free is not supported.", 6652 dev->data->port_id); 6653 } 6654 6655 /** 6656 * Query counter statistics. 6657 * 6658 * @param[in] dev 6659 * Pointer to Ethernet device structure. 6660 * @param[in] cnt 6661 * Index to counter to query. 6662 * @param[in] clear 6663 * Set to clear counter statistics. 6664 * @param[out] pkts 6665 * The counter hits packets number to save. 6666 * @param[out] bytes 6667 * The counter hits bytes number to save. 6668 * 6669 * @return 6670 * 0 on success, a negative errno value otherwise. 6671 */ 6672 int 6673 mlx5_counter_query(struct rte_eth_dev *dev, uint32_t cnt, 6674 bool clear, uint64_t *pkts, uint64_t *bytes) 6675 { 6676 const struct mlx5_flow_driver_ops *fops; 6677 struct rte_flow_attr attr = { .transfer = 0 }; 6678 6679 if (flow_get_drv_type(dev, &attr) == MLX5_FLOW_TYPE_DV) { 6680 fops = flow_get_drv_ops(MLX5_FLOW_TYPE_DV); 6681 return fops->counter_query(dev, cnt, clear, pkts, bytes); 6682 } 6683 DRV_LOG(ERR, 6684 "port %u counter query is not supported.", 6685 dev->data->port_id); 6686 return -ENOTSUP; 6687 } 6688 6689 /** 6690 * Allocate a new memory for the counter values wrapped by all the needed 6691 * management. 6692 * 6693 * @param[in] sh 6694 * Pointer to mlx5_dev_ctx_shared object. 6695 * 6696 * @return 6697 * 0 on success, a negative errno value otherwise. 6698 */ 6699 static int 6700 mlx5_flow_create_counter_stat_mem_mng(struct mlx5_dev_ctx_shared *sh) 6701 { 6702 struct mlx5_devx_mkey_attr mkey_attr; 6703 struct mlx5_counter_stats_mem_mng *mem_mng; 6704 volatile struct flow_counter_stats *raw_data; 6705 int raws_n = MLX5_CNT_CONTAINER_RESIZE + MLX5_MAX_PENDING_QUERIES; 6706 int size = (sizeof(struct flow_counter_stats) * 6707 MLX5_COUNTERS_PER_POOL + 6708 sizeof(struct mlx5_counter_stats_raw)) * raws_n + 6709 sizeof(struct mlx5_counter_stats_mem_mng); 6710 size_t pgsize = rte_mem_page_size(); 6711 uint8_t *mem; 6712 int i; 6713 6714 if (pgsize == (size_t)-1) { 6715 DRV_LOG(ERR, "Failed to get mem page size"); 6716 rte_errno = ENOMEM; 6717 return -ENOMEM; 6718 } 6719 mem = mlx5_malloc(MLX5_MEM_ZERO, size, pgsize, SOCKET_ID_ANY); 6720 if (!mem) { 6721 rte_errno = ENOMEM; 6722 return -ENOMEM; 6723 } 6724 mem_mng = (struct mlx5_counter_stats_mem_mng *)(mem + size) - 1; 6725 size = sizeof(*raw_data) * MLX5_COUNTERS_PER_POOL * raws_n; 6726 mem_mng->umem = mlx5_os_umem_reg(sh->ctx, mem, size, 6727 IBV_ACCESS_LOCAL_WRITE); 6728 if (!mem_mng->umem) { 6729 rte_errno = errno; 6730 mlx5_free(mem); 6731 return -rte_errno; 6732 } 6733 mkey_attr.addr = (uintptr_t)mem; 6734 mkey_attr.size = size; 6735 mkey_attr.umem_id = mlx5_os_get_umem_id(mem_mng->umem); 6736 mkey_attr.pd = sh->pdn; 6737 mkey_attr.log_entity_size = 0; 6738 mkey_attr.pg_access = 0; 6739 mkey_attr.klm_array = NULL; 6740 mkey_attr.klm_num = 0; 6741 mkey_attr.relaxed_ordering_write = sh->cmng.relaxed_ordering_write; 6742 mkey_attr.relaxed_ordering_read = sh->cmng.relaxed_ordering_read; 6743 mem_mng->dm = mlx5_devx_cmd_mkey_create(sh->ctx, &mkey_attr); 6744 if (!mem_mng->dm) { 6745 mlx5_os_umem_dereg(mem_mng->umem); 6746 rte_errno = errno; 6747 mlx5_free(mem); 6748 return -rte_errno; 6749 } 6750 mem_mng->raws = (struct mlx5_counter_stats_raw *)(mem + size); 6751 raw_data = (volatile struct flow_counter_stats *)mem; 6752 for (i = 0; i < raws_n; ++i) { 6753 mem_mng->raws[i].mem_mng = mem_mng; 6754 mem_mng->raws[i].data = raw_data + i * MLX5_COUNTERS_PER_POOL; 6755 } 6756 for (i = 0; i < MLX5_MAX_PENDING_QUERIES; ++i) 6757 LIST_INSERT_HEAD(&sh->cmng.free_stat_raws, 6758 mem_mng->raws + MLX5_CNT_CONTAINER_RESIZE + i, 6759 next); 6760 LIST_INSERT_HEAD(&sh->cmng.mem_mngs, mem_mng, next); 6761 sh->cmng.mem_mng = mem_mng; 6762 return 0; 6763 } 6764 6765 /** 6766 * Set the statistic memory to the new counter pool. 6767 * 6768 * @param[in] sh 6769 * Pointer to mlx5_dev_ctx_shared object. 6770 * @param[in] pool 6771 * Pointer to the pool to set the statistic memory. 6772 * 6773 * @return 6774 * 0 on success, a negative errno value otherwise. 6775 */ 6776 static int 6777 mlx5_flow_set_counter_stat_mem(struct mlx5_dev_ctx_shared *sh, 6778 struct mlx5_flow_counter_pool *pool) 6779 { 6780 struct mlx5_flow_counter_mng *cmng = &sh->cmng; 6781 /* Resize statistic memory once used out. */ 6782 if (!(pool->index % MLX5_CNT_CONTAINER_RESIZE) && 6783 mlx5_flow_create_counter_stat_mem_mng(sh)) { 6784 DRV_LOG(ERR, "Cannot resize counter stat mem."); 6785 return -1; 6786 } 6787 rte_spinlock_lock(&pool->sl); 6788 pool->raw = cmng->mem_mng->raws + pool->index % 6789 MLX5_CNT_CONTAINER_RESIZE; 6790 rte_spinlock_unlock(&pool->sl); 6791 pool->raw_hw = NULL; 6792 return 0; 6793 } 6794 6795 #define MLX5_POOL_QUERY_FREQ_US 1000000 6796 6797 /** 6798 * Set the periodic procedure for triggering asynchronous batch queries for all 6799 * the counter pools. 6800 * 6801 * @param[in] sh 6802 * Pointer to mlx5_dev_ctx_shared object. 6803 */ 6804 void 6805 mlx5_set_query_alarm(struct mlx5_dev_ctx_shared *sh) 6806 { 6807 uint32_t pools_n, us; 6808 6809 pools_n = __atomic_load_n(&sh->cmng.n_valid, __ATOMIC_RELAXED); 6810 us = MLX5_POOL_QUERY_FREQ_US / pools_n; 6811 DRV_LOG(DEBUG, "Set alarm for %u pools each %u us", pools_n, us); 6812 if (rte_eal_alarm_set(us, mlx5_flow_query_alarm, sh)) { 6813 sh->cmng.query_thread_on = 0; 6814 DRV_LOG(ERR, "Cannot reinitialize query alarm"); 6815 } else { 6816 sh->cmng.query_thread_on = 1; 6817 } 6818 } 6819 6820 /** 6821 * The periodic procedure for triggering asynchronous batch queries for all the 6822 * counter pools. This function is probably called by the host thread. 6823 * 6824 * @param[in] arg 6825 * The parameter for the alarm process. 6826 */ 6827 void 6828 mlx5_flow_query_alarm(void *arg) 6829 { 6830 struct mlx5_dev_ctx_shared *sh = arg; 6831 int ret; 6832 uint16_t pool_index = sh->cmng.pool_index; 6833 struct mlx5_flow_counter_mng *cmng = &sh->cmng; 6834 struct mlx5_flow_counter_pool *pool; 6835 uint16_t n_valid; 6836 6837 if (sh->cmng.pending_queries >= MLX5_MAX_PENDING_QUERIES) 6838 goto set_alarm; 6839 rte_spinlock_lock(&cmng->pool_update_sl); 6840 pool = cmng->pools[pool_index]; 6841 n_valid = cmng->n_valid; 6842 rte_spinlock_unlock(&cmng->pool_update_sl); 6843 /* Set the statistic memory to the new created pool. */ 6844 if ((!pool->raw && mlx5_flow_set_counter_stat_mem(sh, pool))) 6845 goto set_alarm; 6846 if (pool->raw_hw) 6847 /* There is a pool query in progress. */ 6848 goto set_alarm; 6849 pool->raw_hw = 6850 LIST_FIRST(&sh->cmng.free_stat_raws); 6851 if (!pool->raw_hw) 6852 /* No free counter statistics raw memory. */ 6853 goto set_alarm; 6854 /* 6855 * Identify the counters released between query trigger and query 6856 * handle more efficiently. The counter released in this gap period 6857 * should wait for a new round of query as the new arrived packets 6858 * will not be taken into account. 6859 */ 6860 pool->query_gen++; 6861 ret = mlx5_devx_cmd_flow_counter_query(pool->min_dcs, 0, 6862 MLX5_COUNTERS_PER_POOL, 6863 NULL, NULL, 6864 pool->raw_hw->mem_mng->dm->id, 6865 (void *)(uintptr_t) 6866 pool->raw_hw->data, 6867 sh->devx_comp, 6868 (uint64_t)(uintptr_t)pool); 6869 if (ret) { 6870 DRV_LOG(ERR, "Failed to trigger asynchronous query for dcs ID" 6871 " %d", pool->min_dcs->id); 6872 pool->raw_hw = NULL; 6873 goto set_alarm; 6874 } 6875 LIST_REMOVE(pool->raw_hw, next); 6876 sh->cmng.pending_queries++; 6877 pool_index++; 6878 if (pool_index >= n_valid) 6879 pool_index = 0; 6880 set_alarm: 6881 sh->cmng.pool_index = pool_index; 6882 mlx5_set_query_alarm(sh); 6883 } 6884 6885 /** 6886 * Check and callback event for new aged flow in the counter pool 6887 * 6888 * @param[in] sh 6889 * Pointer to mlx5_dev_ctx_shared object. 6890 * @param[in] pool 6891 * Pointer to Current counter pool. 6892 */ 6893 static void 6894 mlx5_flow_aging_check(struct mlx5_dev_ctx_shared *sh, 6895 struct mlx5_flow_counter_pool *pool) 6896 { 6897 struct mlx5_priv *priv; 6898 struct mlx5_flow_counter *cnt; 6899 struct mlx5_age_info *age_info; 6900 struct mlx5_age_param *age_param; 6901 struct mlx5_counter_stats_raw *cur = pool->raw_hw; 6902 struct mlx5_counter_stats_raw *prev = pool->raw; 6903 const uint64_t curr_time = MLX5_CURR_TIME_SEC; 6904 const uint32_t time_delta = curr_time - pool->time_of_last_age_check; 6905 uint16_t expected = AGE_CANDIDATE; 6906 uint32_t i; 6907 6908 pool->time_of_last_age_check = curr_time; 6909 for (i = 0; i < MLX5_COUNTERS_PER_POOL; ++i) { 6910 cnt = MLX5_POOL_GET_CNT(pool, i); 6911 age_param = MLX5_CNT_TO_AGE(cnt); 6912 if (__atomic_load_n(&age_param->state, 6913 __ATOMIC_RELAXED) != AGE_CANDIDATE) 6914 continue; 6915 if (cur->data[i].hits != prev->data[i].hits) { 6916 __atomic_store_n(&age_param->sec_since_last_hit, 0, 6917 __ATOMIC_RELAXED); 6918 continue; 6919 } 6920 if (__atomic_add_fetch(&age_param->sec_since_last_hit, 6921 time_delta, 6922 __ATOMIC_RELAXED) <= age_param->timeout) 6923 continue; 6924 /** 6925 * Hold the lock first, or if between the 6926 * state AGE_TMOUT and tailq operation the 6927 * release happened, the release procedure 6928 * may delete a non-existent tailq node. 6929 */ 6930 priv = rte_eth_devices[age_param->port_id].data->dev_private; 6931 age_info = GET_PORT_AGE_INFO(priv); 6932 rte_spinlock_lock(&age_info->aged_sl); 6933 if (__atomic_compare_exchange_n(&age_param->state, &expected, 6934 AGE_TMOUT, false, 6935 __ATOMIC_RELAXED, 6936 __ATOMIC_RELAXED)) { 6937 TAILQ_INSERT_TAIL(&age_info->aged_counters, cnt, next); 6938 MLX5_AGE_SET(age_info, MLX5_AGE_EVENT_NEW); 6939 } 6940 rte_spinlock_unlock(&age_info->aged_sl); 6941 } 6942 mlx5_age_event_prepare(sh); 6943 } 6944 6945 /** 6946 * Handler for the HW respond about ready values from an asynchronous batch 6947 * query. This function is probably called by the host thread. 6948 * 6949 * @param[in] sh 6950 * The pointer to the shared device context. 6951 * @param[in] async_id 6952 * The Devx async ID. 6953 * @param[in] status 6954 * The status of the completion. 6955 */ 6956 void 6957 mlx5_flow_async_pool_query_handle(struct mlx5_dev_ctx_shared *sh, 6958 uint64_t async_id, int status) 6959 { 6960 struct mlx5_flow_counter_pool *pool = 6961 (struct mlx5_flow_counter_pool *)(uintptr_t)async_id; 6962 struct mlx5_counter_stats_raw *raw_to_free; 6963 uint8_t query_gen = pool->query_gen ^ 1; 6964 struct mlx5_flow_counter_mng *cmng = &sh->cmng; 6965 enum mlx5_counter_type cnt_type = 6966 pool->is_aged ? MLX5_COUNTER_TYPE_AGE : 6967 MLX5_COUNTER_TYPE_ORIGIN; 6968 6969 if (unlikely(status)) { 6970 raw_to_free = pool->raw_hw; 6971 } else { 6972 raw_to_free = pool->raw; 6973 if (pool->is_aged) 6974 mlx5_flow_aging_check(sh, pool); 6975 rte_spinlock_lock(&pool->sl); 6976 pool->raw = pool->raw_hw; 6977 rte_spinlock_unlock(&pool->sl); 6978 /* Be sure the new raw counters data is updated in memory. */ 6979 rte_io_wmb(); 6980 if (!TAILQ_EMPTY(&pool->counters[query_gen])) { 6981 rte_spinlock_lock(&cmng->csl[cnt_type]); 6982 TAILQ_CONCAT(&cmng->counters[cnt_type], 6983 &pool->counters[query_gen], next); 6984 rte_spinlock_unlock(&cmng->csl[cnt_type]); 6985 } 6986 } 6987 LIST_INSERT_HEAD(&sh->cmng.free_stat_raws, raw_to_free, next); 6988 pool->raw_hw = NULL; 6989 sh->cmng.pending_queries--; 6990 } 6991 6992 static int 6993 flow_group_to_table(uint32_t port_id, uint32_t group, uint32_t *table, 6994 const struct flow_grp_info *grp_info, 6995 struct rte_flow_error *error) 6996 { 6997 if (grp_info->transfer && grp_info->external && 6998 grp_info->fdb_def_rule) { 6999 if (group == UINT32_MAX) 7000 return rte_flow_error_set 7001 (error, EINVAL, 7002 RTE_FLOW_ERROR_TYPE_ATTR_GROUP, 7003 NULL, 7004 "group index not supported"); 7005 *table = group + 1; 7006 } else { 7007 *table = group; 7008 } 7009 DRV_LOG(DEBUG, "port %u group=%#x table=%#x", port_id, group, *table); 7010 return 0; 7011 } 7012 7013 /** 7014 * Translate the rte_flow group index to HW table value. 7015 * 7016 * If tunnel offload is disabled, all group ids converted to flow table 7017 * id using the standard method. 7018 * If tunnel offload is enabled, group id can be converted using the 7019 * standard or tunnel conversion method. Group conversion method 7020 * selection depends on flags in `grp_info` parameter: 7021 * - Internal (grp_info.external == 0) groups conversion uses the 7022 * standard method. 7023 * - Group ids in JUMP action converted with the tunnel conversion. 7024 * - Group id in rule attribute conversion depends on a rule type and 7025 * group id value: 7026 * ** non zero group attributes converted with the tunnel method 7027 * ** zero group attribute in non-tunnel rule is converted using the 7028 * standard method - there's only one root table 7029 * ** zero group attribute in steer tunnel rule is converted with the 7030 * standard method - single root table 7031 * ** zero group attribute in match tunnel rule is a special OvS 7032 * case: that value is used for portability reasons. That group 7033 * id is converted with the tunnel conversion method. 7034 * 7035 * @param[in] dev 7036 * Port device 7037 * @param[in] tunnel 7038 * PMD tunnel offload object 7039 * @param[in] group 7040 * rte_flow group index value. 7041 * @param[out] table 7042 * HW table value. 7043 * @param[in] grp_info 7044 * flags used for conversion 7045 * @param[out] error 7046 * Pointer to error structure. 7047 * 7048 * @return 7049 * 0 on success, a negative errno value otherwise and rte_errno is set. 7050 */ 7051 int 7052 mlx5_flow_group_to_table(struct rte_eth_dev *dev, 7053 const struct mlx5_flow_tunnel *tunnel, 7054 uint32_t group, uint32_t *table, 7055 const struct flow_grp_info *grp_info, 7056 struct rte_flow_error *error) 7057 { 7058 int ret; 7059 bool standard_translation; 7060 7061 if (!grp_info->skip_scale && grp_info->external && 7062 group < MLX5_MAX_TABLES_EXTERNAL) 7063 group *= MLX5_FLOW_TABLE_FACTOR; 7064 if (is_tunnel_offload_active(dev)) { 7065 standard_translation = !grp_info->external || 7066 grp_info->std_tbl_fix; 7067 } else { 7068 standard_translation = true; 7069 } 7070 DRV_LOG(DEBUG, 7071 "port %u group=%u transfer=%d external=%d fdb_def_rule=%d translate=%s", 7072 dev->data->port_id, group, grp_info->transfer, 7073 grp_info->external, grp_info->fdb_def_rule, 7074 standard_translation ? "STANDARD" : "TUNNEL"); 7075 if (standard_translation) 7076 ret = flow_group_to_table(dev->data->port_id, group, table, 7077 grp_info, error); 7078 else 7079 ret = tunnel_flow_group_to_flow_table(dev, tunnel, group, 7080 table, error); 7081 7082 return ret; 7083 } 7084 7085 /** 7086 * Discover availability of metadata reg_c's. 7087 * 7088 * Iteratively use test flows to check availability. 7089 * 7090 * @param[in] dev 7091 * Pointer to the Ethernet device structure. 7092 * 7093 * @return 7094 * 0 on success, a negative errno value otherwise and rte_errno is set. 7095 */ 7096 int 7097 mlx5_flow_discover_mreg_c(struct rte_eth_dev *dev) 7098 { 7099 struct mlx5_priv *priv = dev->data->dev_private; 7100 struct mlx5_dev_config *config = &priv->config; 7101 enum modify_reg idx; 7102 int n = 0; 7103 7104 /* reg_c[0] and reg_c[1] are reserved. */ 7105 config->flow_mreg_c[n++] = REG_C_0; 7106 config->flow_mreg_c[n++] = REG_C_1; 7107 /* Discover availability of other reg_c's. */ 7108 for (idx = REG_C_2; idx <= REG_C_7; ++idx) { 7109 struct rte_flow_attr attr = { 7110 .group = MLX5_FLOW_MREG_CP_TABLE_GROUP, 7111 .priority = MLX5_FLOW_LOWEST_PRIO_INDICATOR, 7112 .ingress = 1, 7113 }; 7114 struct rte_flow_item items[] = { 7115 [0] = { 7116 .type = RTE_FLOW_ITEM_TYPE_END, 7117 }, 7118 }; 7119 struct rte_flow_action actions[] = { 7120 [0] = { 7121 .type = (enum rte_flow_action_type) 7122 MLX5_RTE_FLOW_ACTION_TYPE_COPY_MREG, 7123 .conf = &(struct mlx5_flow_action_copy_mreg){ 7124 .src = REG_C_1, 7125 .dst = idx, 7126 }, 7127 }, 7128 [1] = { 7129 .type = RTE_FLOW_ACTION_TYPE_JUMP, 7130 .conf = &(struct rte_flow_action_jump){ 7131 .group = MLX5_FLOW_MREG_ACT_TABLE_GROUP, 7132 }, 7133 }, 7134 [2] = { 7135 .type = RTE_FLOW_ACTION_TYPE_END, 7136 }, 7137 }; 7138 uint32_t flow_idx; 7139 struct rte_flow *flow; 7140 struct rte_flow_error error; 7141 7142 if (!config->dv_flow_en) 7143 break; 7144 /* Create internal flow, validation skips copy action. */ 7145 flow_idx = flow_list_create(dev, NULL, &attr, items, 7146 actions, false, &error); 7147 flow = mlx5_ipool_get(priv->sh->ipool[MLX5_IPOOL_RTE_FLOW], 7148 flow_idx); 7149 if (!flow) 7150 continue; 7151 config->flow_mreg_c[n++] = idx; 7152 flow_list_destroy(dev, NULL, flow_idx); 7153 } 7154 for (; n < MLX5_MREG_C_NUM; ++n) 7155 config->flow_mreg_c[n] = REG_NON; 7156 return 0; 7157 } 7158 7159 /** 7160 * Dump flow raw hw data to file 7161 * 7162 * @param[in] dev 7163 * The pointer to Ethernet device. 7164 * @param[in] file 7165 * A pointer to a file for output. 7166 * @param[out] error 7167 * Perform verbose error reporting if not NULL. PMDs initialize this 7168 * structure in case of error only. 7169 * @return 7170 * 0 on success, a nagative value otherwise. 7171 */ 7172 int 7173 mlx5_flow_dev_dump(struct rte_eth_dev *dev, 7174 FILE *file, 7175 struct rte_flow_error *error __rte_unused) 7176 { 7177 struct mlx5_priv *priv = dev->data->dev_private; 7178 struct mlx5_dev_ctx_shared *sh = priv->sh; 7179 7180 if (!priv->config.dv_flow_en) { 7181 if (fputs("device dv flow disabled\n", file) <= 0) 7182 return -errno; 7183 return -ENOTSUP; 7184 } 7185 return mlx5_devx_cmd_flow_dump(sh->fdb_domain, sh->rx_domain, 7186 sh->tx_domain, file); 7187 } 7188 7189 /** 7190 * Get aged-out flows. 7191 * 7192 * @param[in] dev 7193 * Pointer to the Ethernet device structure. 7194 * @param[in] context 7195 * The address of an array of pointers to the aged-out flows contexts. 7196 * @param[in] nb_countexts 7197 * The length of context array pointers. 7198 * @param[out] error 7199 * Perform verbose error reporting if not NULL. Initialized in case of 7200 * error only. 7201 * 7202 * @return 7203 * how many contexts get in success, otherwise negative errno value. 7204 * if nb_contexts is 0, return the amount of all aged contexts. 7205 * if nb_contexts is not 0 , return the amount of aged flows reported 7206 * in the context array. 7207 */ 7208 int 7209 mlx5_flow_get_aged_flows(struct rte_eth_dev *dev, void **contexts, 7210 uint32_t nb_contexts, struct rte_flow_error *error) 7211 { 7212 const struct mlx5_flow_driver_ops *fops; 7213 struct rte_flow_attr attr = { .transfer = 0 }; 7214 7215 if (flow_get_drv_type(dev, &attr) == MLX5_FLOW_TYPE_DV) { 7216 fops = flow_get_drv_ops(MLX5_FLOW_TYPE_DV); 7217 return fops->get_aged_flows(dev, contexts, nb_contexts, 7218 error); 7219 } 7220 DRV_LOG(ERR, 7221 "port %u get aged flows is not supported.", 7222 dev->data->port_id); 7223 return -ENOTSUP; 7224 } 7225 7226 /* Wrapper for driver action_validate op callback */ 7227 static int 7228 flow_drv_action_validate(struct rte_eth_dev *dev, 7229 const struct rte_flow_shared_action_conf *conf, 7230 const struct rte_flow_action *action, 7231 const struct mlx5_flow_driver_ops *fops, 7232 struct rte_flow_error *error) 7233 { 7234 static const char err_msg[] = "shared action validation unsupported"; 7235 7236 if (!fops->action_validate) { 7237 DRV_LOG(ERR, "port %u %s.", dev->data->port_id, err_msg); 7238 rte_flow_error_set(error, ENOTSUP, RTE_FLOW_ERROR_TYPE_ACTION, 7239 NULL, err_msg); 7240 return -rte_errno; 7241 } 7242 return fops->action_validate(dev, conf, action, error); 7243 } 7244 7245 /** 7246 * Destroys the shared action by handle. 7247 * 7248 * @param dev 7249 * Pointer to Ethernet device structure. 7250 * @param[in] action 7251 * Handle for the shared action to be destroyed. 7252 * @param[out] error 7253 * Perform verbose error reporting if not NULL. PMDs initialize this 7254 * structure in case of error only. 7255 * 7256 * @return 7257 * 0 on success, a negative errno value otherwise and rte_errno is set. 7258 * 7259 * @note: wrapper for driver action_create op callback. 7260 */ 7261 static int 7262 mlx5_shared_action_destroy(struct rte_eth_dev *dev, 7263 struct rte_flow_shared_action *action, 7264 struct rte_flow_error *error) 7265 { 7266 static const char err_msg[] = "shared action destruction unsupported"; 7267 struct rte_flow_attr attr = { .transfer = 0 }; 7268 const struct mlx5_flow_driver_ops *fops = 7269 flow_get_drv_ops(flow_get_drv_type(dev, &attr)); 7270 7271 if (!fops->action_destroy) { 7272 DRV_LOG(ERR, "port %u %s.", dev->data->port_id, err_msg); 7273 rte_flow_error_set(error, ENOTSUP, RTE_FLOW_ERROR_TYPE_ACTION, 7274 NULL, err_msg); 7275 return -rte_errno; 7276 } 7277 return fops->action_destroy(dev, action, error); 7278 } 7279 7280 /* Wrapper for driver action_destroy op callback */ 7281 static int 7282 flow_drv_action_update(struct rte_eth_dev *dev, 7283 struct rte_flow_shared_action *action, 7284 const void *action_conf, 7285 const struct mlx5_flow_driver_ops *fops, 7286 struct rte_flow_error *error) 7287 { 7288 static const char err_msg[] = "shared action update unsupported"; 7289 7290 if (!fops->action_update) { 7291 DRV_LOG(ERR, "port %u %s.", dev->data->port_id, err_msg); 7292 rte_flow_error_set(error, ENOTSUP, RTE_FLOW_ERROR_TYPE_ACTION, 7293 NULL, err_msg); 7294 return -rte_errno; 7295 } 7296 return fops->action_update(dev, action, action_conf, error); 7297 } 7298 7299 /* Wrapper for driver action_destroy op callback */ 7300 static int 7301 flow_drv_action_query(struct rte_eth_dev *dev, 7302 const struct rte_flow_shared_action *action, 7303 void *data, 7304 const struct mlx5_flow_driver_ops *fops, 7305 struct rte_flow_error *error) 7306 { 7307 static const char err_msg[] = "shared action query unsupported"; 7308 7309 if (!fops->action_query) { 7310 DRV_LOG(ERR, "port %u %s.", dev->data->port_id, err_msg); 7311 rte_flow_error_set(error, ENOTSUP, RTE_FLOW_ERROR_TYPE_ACTION, 7312 NULL, err_msg); 7313 return -rte_errno; 7314 } 7315 return fops->action_query(dev, action, data, error); 7316 } 7317 7318 /** 7319 * Create shared action for reuse in multiple flow rules. 7320 * 7321 * @param dev 7322 * Pointer to Ethernet device structure. 7323 * @param[in] action 7324 * Action configuration for shared action creation. 7325 * @param[out] error 7326 * Perform verbose error reporting if not NULL. PMDs initialize this 7327 * structure in case of error only. 7328 * @return 7329 * A valid handle in case of success, NULL otherwise and rte_errno is set. 7330 */ 7331 static struct rte_flow_shared_action * 7332 mlx5_shared_action_create(struct rte_eth_dev *dev, 7333 const struct rte_flow_shared_action_conf *conf, 7334 const struct rte_flow_action *action, 7335 struct rte_flow_error *error) 7336 { 7337 static const char err_msg[] = "shared action creation unsupported"; 7338 struct rte_flow_attr attr = { .transfer = 0 }; 7339 const struct mlx5_flow_driver_ops *fops = 7340 flow_get_drv_ops(flow_get_drv_type(dev, &attr)); 7341 7342 if (flow_drv_action_validate(dev, conf, action, fops, error)) 7343 return NULL; 7344 if (!fops->action_create) { 7345 DRV_LOG(ERR, "port %u %s.", dev->data->port_id, err_msg); 7346 rte_flow_error_set(error, ENOTSUP, RTE_FLOW_ERROR_TYPE_ACTION, 7347 NULL, err_msg); 7348 return NULL; 7349 } 7350 return fops->action_create(dev, conf, action, error); 7351 } 7352 7353 /** 7354 * Updates inplace the shared action configuration pointed by *action* handle 7355 * with the configuration provided as *action* argument. 7356 * The update of the shared action configuration effects all flow rules reusing 7357 * the action via handle. 7358 * 7359 * @param dev 7360 * Pointer to Ethernet device structure. 7361 * @param[in] shared_action 7362 * Handle for the shared action to be updated. 7363 * @param[in] action 7364 * Action specification used to modify the action pointed by handle. 7365 * *action* should be of same type with the action pointed by the *action* 7366 * handle argument, otherwise considered as invalid. 7367 * @param[out] error 7368 * Perform verbose error reporting if not NULL. PMDs initialize this 7369 * structure in case of error only. 7370 * 7371 * @return 7372 * 0 on success, a negative errno value otherwise and rte_errno is set. 7373 */ 7374 static int 7375 mlx5_shared_action_update(struct rte_eth_dev *dev, 7376 struct rte_flow_shared_action *shared_action, 7377 const struct rte_flow_action *action, 7378 struct rte_flow_error *error) 7379 { 7380 struct rte_flow_attr attr = { .transfer = 0 }; 7381 const struct mlx5_flow_driver_ops *fops = 7382 flow_get_drv_ops(flow_get_drv_type(dev, &attr)); 7383 int ret; 7384 7385 ret = flow_drv_action_validate(dev, NULL, action, fops, error); 7386 if (ret) 7387 return ret; 7388 return flow_drv_action_update(dev, shared_action, action->conf, fops, 7389 error); 7390 } 7391 7392 /** 7393 * Query the shared action by handle. 7394 * 7395 * This function allows retrieving action-specific data such as counters. 7396 * Data is gathered by special action which may be present/referenced in 7397 * more than one flow rule definition. 7398 * 7399 * \see RTE_FLOW_ACTION_TYPE_COUNT 7400 * 7401 * @param dev 7402 * Pointer to Ethernet device structure. 7403 * @param[in] action 7404 * Handle for the shared action to query. 7405 * @param[in, out] data 7406 * Pointer to storage for the associated query data type. 7407 * @param[out] error 7408 * Perform verbose error reporting if not NULL. PMDs initialize this 7409 * structure in case of error only. 7410 * 7411 * @return 7412 * 0 on success, a negative errno value otherwise and rte_errno is set. 7413 */ 7414 static int 7415 mlx5_shared_action_query(struct rte_eth_dev *dev, 7416 const struct rte_flow_shared_action *action, 7417 void *data, 7418 struct rte_flow_error *error) 7419 { 7420 struct rte_flow_attr attr = { .transfer = 0 }; 7421 const struct mlx5_flow_driver_ops *fops = 7422 flow_get_drv_ops(flow_get_drv_type(dev, &attr)); 7423 7424 return flow_drv_action_query(dev, action, data, fops, error); 7425 } 7426 7427 /** 7428 * Destroy all shared actions. 7429 * 7430 * @param dev 7431 * Pointer to Ethernet device. 7432 * 7433 * @return 7434 * 0 on success, a negative errno value otherwise and rte_errno is set. 7435 */ 7436 int 7437 mlx5_shared_action_flush(struct rte_eth_dev *dev) 7438 { 7439 struct rte_flow_error error; 7440 struct mlx5_priv *priv = dev->data->dev_private; 7441 struct mlx5_shared_action_rss *shared_rss; 7442 int ret = 0; 7443 uint32_t idx; 7444 7445 ILIST_FOREACH(priv->sh->ipool[MLX5_IPOOL_RSS_SHARED_ACTIONS], 7446 priv->rss_shared_actions, idx, shared_rss, next) { 7447 ret |= mlx5_shared_action_destroy(dev, 7448 (struct rte_flow_shared_action *)(uintptr_t)idx, &error); 7449 } 7450 return ret; 7451 } 7452 7453 #ifndef HAVE_MLX5DV_DR 7454 #define MLX5_DOMAIN_SYNC_FLOW ((1 << 0) | (1 << 1)) 7455 #else 7456 #define MLX5_DOMAIN_SYNC_FLOW \ 7457 (MLX5DV_DR_DOMAIN_SYNC_FLAGS_SW | MLX5DV_DR_DOMAIN_SYNC_FLAGS_HW) 7458 #endif 7459 7460 int rte_pmd_mlx5_sync_flow(uint16_t port_id, uint32_t domains) 7461 { 7462 struct rte_eth_dev *dev = &rte_eth_devices[port_id]; 7463 const struct mlx5_flow_driver_ops *fops; 7464 int ret; 7465 struct rte_flow_attr attr = { .transfer = 0 }; 7466 7467 fops = flow_get_drv_ops(flow_get_drv_type(dev, &attr)); 7468 ret = fops->sync_domain(dev, domains, MLX5_DOMAIN_SYNC_FLOW); 7469 if (ret > 0) 7470 ret = -ret; 7471 return ret; 7472 } 7473 7474 /** 7475 * tunnel offload functionalilty is defined for DV environment only 7476 */ 7477 #ifdef HAVE_IBV_FLOW_DV_SUPPORT 7478 __extension__ 7479 union tunnel_offload_mark { 7480 uint32_t val; 7481 struct { 7482 uint32_t app_reserve:8; 7483 uint32_t table_id:15; 7484 uint32_t transfer:1; 7485 uint32_t _unused_:8; 7486 }; 7487 }; 7488 7489 static bool 7490 mlx5_access_tunnel_offload_db 7491 (struct rte_eth_dev *dev, 7492 bool (*match)(struct rte_eth_dev *, 7493 struct mlx5_flow_tunnel *, const void *), 7494 void (*hit)(struct rte_eth_dev *, struct mlx5_flow_tunnel *, void *), 7495 void (*miss)(struct rte_eth_dev *, void *), 7496 void *ctx, bool lock_op); 7497 7498 static int 7499 flow_tunnel_add_default_miss(struct rte_eth_dev *dev, 7500 struct rte_flow *flow, 7501 const struct rte_flow_attr *attr, 7502 const struct rte_flow_action *app_actions, 7503 uint32_t flow_idx, 7504 struct tunnel_default_miss_ctx *ctx, 7505 struct rte_flow_error *error) 7506 { 7507 struct mlx5_priv *priv = dev->data->dev_private; 7508 struct mlx5_flow *dev_flow; 7509 struct rte_flow_attr miss_attr = *attr; 7510 const struct mlx5_flow_tunnel *tunnel = app_actions[0].conf; 7511 const struct rte_flow_item miss_items[2] = { 7512 { 7513 .type = RTE_FLOW_ITEM_TYPE_ETH, 7514 .spec = NULL, 7515 .last = NULL, 7516 .mask = NULL 7517 }, 7518 { 7519 .type = RTE_FLOW_ITEM_TYPE_END, 7520 .spec = NULL, 7521 .last = NULL, 7522 .mask = NULL 7523 } 7524 }; 7525 union tunnel_offload_mark mark_id; 7526 struct rte_flow_action_mark miss_mark; 7527 struct rte_flow_action miss_actions[3] = { 7528 [0] = { .type = RTE_FLOW_ACTION_TYPE_MARK, .conf = &miss_mark }, 7529 [2] = { .type = RTE_FLOW_ACTION_TYPE_END, .conf = NULL } 7530 }; 7531 const struct rte_flow_action_jump *jump_data; 7532 uint32_t i, flow_table = 0; /* prevent compilation warning */ 7533 struct flow_grp_info grp_info = { 7534 .external = 1, 7535 .transfer = attr->transfer, 7536 .fdb_def_rule = !!priv->fdb_def_rule, 7537 .std_tbl_fix = 0, 7538 }; 7539 int ret; 7540 7541 if (!attr->transfer) { 7542 uint32_t q_size; 7543 7544 miss_actions[1].type = RTE_FLOW_ACTION_TYPE_RSS; 7545 q_size = priv->reta_idx_n * sizeof(ctx->queue[0]); 7546 ctx->queue = mlx5_malloc(MLX5_MEM_SYS | MLX5_MEM_ZERO, q_size, 7547 0, SOCKET_ID_ANY); 7548 if (!ctx->queue) 7549 return rte_flow_error_set 7550 (error, ENOMEM, 7551 RTE_FLOW_ERROR_TYPE_ACTION_CONF, 7552 NULL, "invalid default miss RSS"); 7553 ctx->action_rss.func = RTE_ETH_HASH_FUNCTION_DEFAULT, 7554 ctx->action_rss.level = 0, 7555 ctx->action_rss.types = priv->rss_conf.rss_hf, 7556 ctx->action_rss.key_len = priv->rss_conf.rss_key_len, 7557 ctx->action_rss.queue_num = priv->reta_idx_n, 7558 ctx->action_rss.key = priv->rss_conf.rss_key, 7559 ctx->action_rss.queue = ctx->queue; 7560 if (!priv->reta_idx_n || !priv->rxqs_n) 7561 return rte_flow_error_set 7562 (error, EINVAL, 7563 RTE_FLOW_ERROR_TYPE_ACTION_CONF, 7564 NULL, "invalid port configuration"); 7565 if (!(dev->data->dev_conf.rxmode.mq_mode & ETH_MQ_RX_RSS_FLAG)) 7566 ctx->action_rss.types = 0; 7567 for (i = 0; i != priv->reta_idx_n; ++i) 7568 ctx->queue[i] = (*priv->reta_idx)[i]; 7569 } else { 7570 miss_actions[1].type = RTE_FLOW_ACTION_TYPE_JUMP; 7571 ctx->miss_jump.group = MLX5_TNL_MISS_FDB_JUMP_GRP; 7572 } 7573 miss_actions[1].conf = (typeof(miss_actions[1].conf))ctx->raw; 7574 for (; app_actions->type != RTE_FLOW_ACTION_TYPE_JUMP; app_actions++); 7575 jump_data = app_actions->conf; 7576 miss_attr.priority = MLX5_TNL_MISS_RULE_PRIORITY; 7577 miss_attr.group = jump_data->group; 7578 ret = mlx5_flow_group_to_table(dev, tunnel, jump_data->group, 7579 &flow_table, &grp_info, error); 7580 if (ret) 7581 return rte_flow_error_set(error, EINVAL, 7582 RTE_FLOW_ERROR_TYPE_ACTION_CONF, 7583 NULL, "invalid tunnel id"); 7584 mark_id.app_reserve = 0; 7585 mark_id.table_id = tunnel_flow_tbl_to_id(flow_table); 7586 mark_id.transfer = !!attr->transfer; 7587 mark_id._unused_ = 0; 7588 miss_mark.id = mark_id.val; 7589 dev_flow = flow_drv_prepare(dev, flow, &miss_attr, 7590 miss_items, miss_actions, flow_idx, error); 7591 if (!dev_flow) 7592 return -rte_errno; 7593 dev_flow->flow = flow; 7594 dev_flow->external = true; 7595 dev_flow->tunnel = tunnel; 7596 /* Subflow object was created, we must include one in the list. */ 7597 SILIST_INSERT(&flow->dev_handles, dev_flow->handle_idx, 7598 dev_flow->handle, next); 7599 DRV_LOG(DEBUG, 7600 "port %u tunnel type=%d id=%u miss rule priority=%u group=%u", 7601 dev->data->port_id, tunnel->app_tunnel.type, 7602 tunnel->tunnel_id, miss_attr.priority, miss_attr.group); 7603 ret = flow_drv_translate(dev, dev_flow, &miss_attr, miss_items, 7604 miss_actions, error); 7605 if (!ret) 7606 ret = flow_mreg_update_copy_table(dev, flow, miss_actions, 7607 error); 7608 7609 return ret; 7610 } 7611 7612 static const struct mlx5_flow_tbl_data_entry * 7613 tunnel_mark_decode(struct rte_eth_dev *dev, uint32_t mark) 7614 { 7615 struct mlx5_priv *priv = dev->data->dev_private; 7616 struct mlx5_dev_ctx_shared *sh = priv->sh; 7617 struct mlx5_hlist_entry *he; 7618 union tunnel_offload_mark mbits = { .val = mark }; 7619 union mlx5_flow_tbl_key table_key = { 7620 { 7621 .table_id = tunnel_id_to_flow_tbl(mbits.table_id), 7622 .dummy = 0, 7623 .domain = !!mbits.transfer, 7624 .direction = 0, 7625 } 7626 }; 7627 he = mlx5_hlist_lookup(sh->flow_tbls, table_key.v64, NULL); 7628 return he ? 7629 container_of(he, struct mlx5_flow_tbl_data_entry, entry) : NULL; 7630 } 7631 7632 static void 7633 mlx5_flow_tunnel_grp2tbl_remove_cb(struct mlx5_hlist *list, 7634 struct mlx5_hlist_entry *entry) 7635 { 7636 struct mlx5_dev_ctx_shared *sh = list->ctx; 7637 struct tunnel_tbl_entry *tte = container_of(entry, typeof(*tte), hash); 7638 7639 mlx5_ipool_free(sh->ipool[MLX5_IPOOL_TNL_TBL_ID], 7640 tunnel_flow_tbl_to_id(tte->flow_table)); 7641 mlx5_free(tte); 7642 } 7643 7644 static int 7645 mlx5_flow_tunnel_grp2tbl_match_cb(struct mlx5_hlist *list __rte_unused, 7646 struct mlx5_hlist_entry *entry, 7647 uint64_t key, void *cb_ctx __rte_unused) 7648 { 7649 union tunnel_tbl_key tbl = { 7650 .val = key, 7651 }; 7652 struct tunnel_tbl_entry *tte = container_of(entry, typeof(*tte), hash); 7653 7654 return tbl.tunnel_id != tte->tunnel_id || tbl.group != tte->group; 7655 } 7656 7657 static struct mlx5_hlist_entry * 7658 mlx5_flow_tunnel_grp2tbl_create_cb(struct mlx5_hlist *list, uint64_t key, 7659 void *ctx __rte_unused) 7660 { 7661 struct mlx5_dev_ctx_shared *sh = list->ctx; 7662 struct tunnel_tbl_entry *tte; 7663 union tunnel_tbl_key tbl = { 7664 .val = key, 7665 }; 7666 7667 tte = mlx5_malloc(MLX5_MEM_SYS | MLX5_MEM_ZERO, 7668 sizeof(*tte), 0, 7669 SOCKET_ID_ANY); 7670 if (!tte) 7671 goto err; 7672 mlx5_ipool_malloc(sh->ipool[MLX5_IPOOL_TNL_TBL_ID], 7673 &tte->flow_table); 7674 if (tte->flow_table >= MLX5_MAX_TABLES) { 7675 DRV_LOG(ERR, "Tunnel TBL ID %d exceed max limit.", 7676 tte->flow_table); 7677 mlx5_ipool_free(sh->ipool[MLX5_IPOOL_TNL_TBL_ID], 7678 tte->flow_table); 7679 goto err; 7680 } else if (!tte->flow_table) { 7681 goto err; 7682 } 7683 tte->flow_table = tunnel_id_to_flow_tbl(tte->flow_table); 7684 tte->tunnel_id = tbl.tunnel_id; 7685 tte->group = tbl.group; 7686 return &tte->hash; 7687 err: 7688 if (tte) 7689 mlx5_free(tte); 7690 return NULL; 7691 } 7692 7693 static uint32_t 7694 tunnel_flow_group_to_flow_table(struct rte_eth_dev *dev, 7695 const struct mlx5_flow_tunnel *tunnel, 7696 uint32_t group, uint32_t *table, 7697 struct rte_flow_error *error) 7698 { 7699 struct mlx5_hlist_entry *he; 7700 struct tunnel_tbl_entry *tte; 7701 union tunnel_tbl_key key = { 7702 .tunnel_id = tunnel ? tunnel->tunnel_id : 0, 7703 .group = group 7704 }; 7705 struct mlx5_flow_tunnel_hub *thub = mlx5_tunnel_hub(dev); 7706 struct mlx5_hlist *group_hash; 7707 7708 group_hash = tunnel ? tunnel->groups : thub->groups; 7709 he = mlx5_hlist_register(group_hash, key.val, NULL); 7710 if (!he) 7711 return rte_flow_error_set(error, EINVAL, 7712 RTE_FLOW_ERROR_TYPE_ATTR_GROUP, 7713 NULL, 7714 "tunnel group index not supported"); 7715 tte = container_of(he, typeof(*tte), hash); 7716 *table = tte->flow_table; 7717 DRV_LOG(DEBUG, "port %u tunnel %u group=%#x table=%#x", 7718 dev->data->port_id, key.tunnel_id, group, *table); 7719 return 0; 7720 } 7721 7722 static void 7723 mlx5_flow_tunnel_free(struct rte_eth_dev *dev, 7724 struct mlx5_flow_tunnel *tunnel) 7725 { 7726 struct mlx5_priv *priv = dev->data->dev_private; 7727 struct mlx5_indexed_pool *ipool; 7728 7729 DRV_LOG(DEBUG, "port %u release pmd tunnel id=0x%x", 7730 dev->data->port_id, tunnel->tunnel_id); 7731 LIST_REMOVE(tunnel, chain); 7732 mlx5_hlist_destroy(tunnel->groups); 7733 ipool = priv->sh->ipool[MLX5_IPOOL_TUNNEL_ID]; 7734 mlx5_ipool_free(ipool, tunnel->tunnel_id); 7735 } 7736 7737 static bool 7738 mlx5_access_tunnel_offload_db 7739 (struct rte_eth_dev *dev, 7740 bool (*match)(struct rte_eth_dev *, 7741 struct mlx5_flow_tunnel *, const void *), 7742 void (*hit)(struct rte_eth_dev *, struct mlx5_flow_tunnel *, void *), 7743 void (*miss)(struct rte_eth_dev *, void *), 7744 void *ctx, bool lock_op) 7745 { 7746 bool verdict = false; 7747 struct mlx5_flow_tunnel_hub *thub = mlx5_tunnel_hub(dev); 7748 struct mlx5_flow_tunnel *tunnel; 7749 7750 rte_spinlock_lock(&thub->sl); 7751 LIST_FOREACH(tunnel, &thub->tunnels, chain) { 7752 verdict = match(dev, tunnel, (const void *)ctx); 7753 if (verdict) 7754 break; 7755 } 7756 if (!lock_op) 7757 rte_spinlock_unlock(&thub->sl); 7758 if (verdict && hit) 7759 hit(dev, tunnel, ctx); 7760 if (!verdict && miss) 7761 miss(dev, ctx); 7762 if (lock_op) 7763 rte_spinlock_unlock(&thub->sl); 7764 7765 return verdict; 7766 } 7767 7768 struct tunnel_db_find_tunnel_id_ctx { 7769 uint32_t tunnel_id; 7770 struct mlx5_flow_tunnel *tunnel; 7771 }; 7772 7773 static bool 7774 find_tunnel_id_match(struct rte_eth_dev *dev, 7775 struct mlx5_flow_tunnel *tunnel, const void *x) 7776 { 7777 const struct tunnel_db_find_tunnel_id_ctx *ctx = x; 7778 7779 RTE_SET_USED(dev); 7780 return tunnel->tunnel_id == ctx->tunnel_id; 7781 } 7782 7783 static void 7784 find_tunnel_id_hit(struct rte_eth_dev *dev, 7785 struct mlx5_flow_tunnel *tunnel, void *x) 7786 { 7787 struct tunnel_db_find_tunnel_id_ctx *ctx = x; 7788 RTE_SET_USED(dev); 7789 ctx->tunnel = tunnel; 7790 } 7791 7792 static struct mlx5_flow_tunnel * 7793 mlx5_find_tunnel_id(struct rte_eth_dev *dev, uint32_t id) 7794 { 7795 struct tunnel_db_find_tunnel_id_ctx ctx = { 7796 .tunnel_id = id, 7797 }; 7798 7799 mlx5_access_tunnel_offload_db(dev, find_tunnel_id_match, 7800 find_tunnel_id_hit, NULL, &ctx, true); 7801 7802 return ctx.tunnel; 7803 } 7804 7805 static struct mlx5_flow_tunnel * 7806 mlx5_flow_tunnel_allocate(struct rte_eth_dev *dev, 7807 const struct rte_flow_tunnel *app_tunnel) 7808 { 7809 struct mlx5_priv *priv = dev->data->dev_private; 7810 struct mlx5_indexed_pool *ipool; 7811 struct mlx5_flow_tunnel *tunnel; 7812 uint32_t id; 7813 7814 ipool = priv->sh->ipool[MLX5_IPOOL_TUNNEL_ID]; 7815 tunnel = mlx5_ipool_zmalloc(ipool, &id); 7816 if (!tunnel) 7817 return NULL; 7818 if (id >= MLX5_MAX_TUNNELS) { 7819 mlx5_ipool_free(ipool, id); 7820 DRV_LOG(ERR, "Tunnel ID %d exceed max limit.", id); 7821 return NULL; 7822 } 7823 tunnel->groups = mlx5_hlist_create("tunnel groups", 1024, 0, 0, 7824 mlx5_flow_tunnel_grp2tbl_create_cb, 7825 mlx5_flow_tunnel_grp2tbl_match_cb, 7826 mlx5_flow_tunnel_grp2tbl_remove_cb); 7827 if (!tunnel->groups) { 7828 mlx5_ipool_free(ipool, id); 7829 return NULL; 7830 } 7831 tunnel->groups->ctx = priv->sh; 7832 /* initiate new PMD tunnel */ 7833 memcpy(&tunnel->app_tunnel, app_tunnel, sizeof(*app_tunnel)); 7834 tunnel->tunnel_id = id; 7835 tunnel->action.type = (typeof(tunnel->action.type)) 7836 MLX5_RTE_FLOW_ACTION_TYPE_TUNNEL_SET; 7837 tunnel->action.conf = tunnel; 7838 tunnel->item.type = (typeof(tunnel->item.type)) 7839 MLX5_RTE_FLOW_ITEM_TYPE_TUNNEL; 7840 tunnel->item.spec = tunnel; 7841 tunnel->item.last = NULL; 7842 tunnel->item.mask = NULL; 7843 7844 DRV_LOG(DEBUG, "port %u new pmd tunnel id=0x%x", 7845 dev->data->port_id, tunnel->tunnel_id); 7846 7847 return tunnel; 7848 } 7849 7850 struct tunnel_db_get_tunnel_ctx { 7851 const struct rte_flow_tunnel *app_tunnel; 7852 struct mlx5_flow_tunnel *tunnel; 7853 }; 7854 7855 static bool get_tunnel_match(struct rte_eth_dev *dev, 7856 struct mlx5_flow_tunnel *tunnel, const void *x) 7857 { 7858 const struct tunnel_db_get_tunnel_ctx *ctx = x; 7859 7860 RTE_SET_USED(dev); 7861 return !memcmp(ctx->app_tunnel, &tunnel->app_tunnel, 7862 sizeof(*ctx->app_tunnel)); 7863 } 7864 7865 static void get_tunnel_hit(struct rte_eth_dev *dev, 7866 struct mlx5_flow_tunnel *tunnel, void *x) 7867 { 7868 /* called under tunnel spinlock protection */ 7869 struct tunnel_db_get_tunnel_ctx *ctx = x; 7870 7871 RTE_SET_USED(dev); 7872 tunnel->refctn++; 7873 ctx->tunnel = tunnel; 7874 } 7875 7876 static void get_tunnel_miss(struct rte_eth_dev *dev, void *x) 7877 { 7878 /* called under tunnel spinlock protection */ 7879 struct mlx5_flow_tunnel_hub *thub = mlx5_tunnel_hub(dev); 7880 struct tunnel_db_get_tunnel_ctx *ctx = x; 7881 7882 rte_spinlock_unlock(&thub->sl); 7883 ctx->tunnel = mlx5_flow_tunnel_allocate(dev, ctx->app_tunnel); 7884 rte_spinlock_lock(&thub->sl); 7885 if (ctx->tunnel) { 7886 ctx->tunnel->refctn = 1; 7887 LIST_INSERT_HEAD(&thub->tunnels, ctx->tunnel, chain); 7888 } 7889 } 7890 7891 7892 static int 7893 mlx5_get_flow_tunnel(struct rte_eth_dev *dev, 7894 const struct rte_flow_tunnel *app_tunnel, 7895 struct mlx5_flow_tunnel **tunnel) 7896 { 7897 struct tunnel_db_get_tunnel_ctx ctx = { 7898 .app_tunnel = app_tunnel, 7899 }; 7900 7901 mlx5_access_tunnel_offload_db(dev, get_tunnel_match, get_tunnel_hit, 7902 get_tunnel_miss, &ctx, true); 7903 *tunnel = ctx.tunnel; 7904 return ctx.tunnel ? 0 : -ENOMEM; 7905 } 7906 7907 void mlx5_release_tunnel_hub(struct mlx5_dev_ctx_shared *sh, uint16_t port_id) 7908 { 7909 struct mlx5_flow_tunnel_hub *thub = sh->tunnel_hub; 7910 7911 if (!thub) 7912 return; 7913 if (!LIST_EMPTY(&thub->tunnels)) 7914 DRV_LOG(WARNING, "port %u tunnels present", port_id); 7915 mlx5_hlist_destroy(thub->groups); 7916 mlx5_free(thub); 7917 } 7918 7919 int mlx5_alloc_tunnel_hub(struct mlx5_dev_ctx_shared *sh) 7920 { 7921 int err; 7922 struct mlx5_flow_tunnel_hub *thub; 7923 7924 thub = mlx5_malloc(MLX5_MEM_SYS | MLX5_MEM_ZERO, sizeof(*thub), 7925 0, SOCKET_ID_ANY); 7926 if (!thub) 7927 return -ENOMEM; 7928 LIST_INIT(&thub->tunnels); 7929 rte_spinlock_init(&thub->sl); 7930 thub->groups = mlx5_hlist_create("flow groups", 7931 rte_align32pow2(MLX5_MAX_TABLES), 0, 7932 0, mlx5_flow_tunnel_grp2tbl_create_cb, 7933 mlx5_flow_tunnel_grp2tbl_match_cb, 7934 mlx5_flow_tunnel_grp2tbl_remove_cb); 7935 if (!thub->groups) { 7936 err = -rte_errno; 7937 goto err; 7938 } 7939 thub->groups->ctx = sh; 7940 sh->tunnel_hub = thub; 7941 7942 return 0; 7943 7944 err: 7945 if (thub->groups) 7946 mlx5_hlist_destroy(thub->groups); 7947 if (thub) 7948 mlx5_free(thub); 7949 return err; 7950 } 7951 7952 static inline bool 7953 mlx5_flow_tunnel_validate(struct rte_eth_dev *dev, 7954 struct rte_flow_tunnel *tunnel, 7955 const char *err_msg) 7956 { 7957 err_msg = NULL; 7958 if (!is_tunnel_offload_active(dev)) { 7959 err_msg = "tunnel offload was not activated"; 7960 goto out; 7961 } else if (!tunnel) { 7962 err_msg = "no application tunnel"; 7963 goto out; 7964 } 7965 7966 switch (tunnel->type) { 7967 default: 7968 err_msg = "unsupported tunnel type"; 7969 goto out; 7970 case RTE_FLOW_ITEM_TYPE_VXLAN: 7971 break; 7972 } 7973 7974 out: 7975 return !err_msg; 7976 } 7977 7978 static int 7979 mlx5_flow_tunnel_decap_set(struct rte_eth_dev *dev, 7980 struct rte_flow_tunnel *app_tunnel, 7981 struct rte_flow_action **actions, 7982 uint32_t *num_of_actions, 7983 struct rte_flow_error *error) 7984 { 7985 int ret; 7986 struct mlx5_flow_tunnel *tunnel; 7987 const char *err_msg = NULL; 7988 bool verdict = mlx5_flow_tunnel_validate(dev, app_tunnel, err_msg); 7989 7990 if (!verdict) 7991 return rte_flow_error_set(error, EINVAL, 7992 RTE_FLOW_ERROR_TYPE_ACTION_CONF, NULL, 7993 err_msg); 7994 ret = mlx5_get_flow_tunnel(dev, app_tunnel, &tunnel); 7995 if (ret < 0) { 7996 return rte_flow_error_set(error, ret, 7997 RTE_FLOW_ERROR_TYPE_ACTION_CONF, NULL, 7998 "failed to initialize pmd tunnel"); 7999 } 8000 *actions = &tunnel->action; 8001 *num_of_actions = 1; 8002 return 0; 8003 } 8004 8005 static int 8006 mlx5_flow_tunnel_match(struct rte_eth_dev *dev, 8007 struct rte_flow_tunnel *app_tunnel, 8008 struct rte_flow_item **items, 8009 uint32_t *num_of_items, 8010 struct rte_flow_error *error) 8011 { 8012 int ret; 8013 struct mlx5_flow_tunnel *tunnel; 8014 const char *err_msg = NULL; 8015 bool verdict = mlx5_flow_tunnel_validate(dev, app_tunnel, err_msg); 8016 8017 if (!verdict) 8018 return rte_flow_error_set(error, EINVAL, 8019 RTE_FLOW_ERROR_TYPE_HANDLE, NULL, 8020 err_msg); 8021 ret = mlx5_get_flow_tunnel(dev, app_tunnel, &tunnel); 8022 if (ret < 0) { 8023 return rte_flow_error_set(error, ret, 8024 RTE_FLOW_ERROR_TYPE_HANDLE, NULL, 8025 "failed to initialize pmd tunnel"); 8026 } 8027 *items = &tunnel->item; 8028 *num_of_items = 1; 8029 return 0; 8030 } 8031 8032 struct tunnel_db_element_release_ctx { 8033 struct rte_flow_item *items; 8034 struct rte_flow_action *actions; 8035 uint32_t num_elements; 8036 struct rte_flow_error *error; 8037 int ret; 8038 }; 8039 8040 static bool 8041 tunnel_element_release_match(struct rte_eth_dev *dev, 8042 struct mlx5_flow_tunnel *tunnel, const void *x) 8043 { 8044 const struct tunnel_db_element_release_ctx *ctx = x; 8045 8046 RTE_SET_USED(dev); 8047 if (ctx->num_elements != 1) 8048 return false; 8049 else if (ctx->items) 8050 return ctx->items == &tunnel->item; 8051 else if (ctx->actions) 8052 return ctx->actions == &tunnel->action; 8053 8054 return false; 8055 } 8056 8057 static void 8058 tunnel_element_release_hit(struct rte_eth_dev *dev, 8059 struct mlx5_flow_tunnel *tunnel, void *x) 8060 { 8061 struct tunnel_db_element_release_ctx *ctx = x; 8062 ctx->ret = 0; 8063 if (!__atomic_sub_fetch(&tunnel->refctn, 1, __ATOMIC_RELAXED)) 8064 mlx5_flow_tunnel_free(dev, tunnel); 8065 } 8066 8067 static void 8068 tunnel_element_release_miss(struct rte_eth_dev *dev, void *x) 8069 { 8070 struct tunnel_db_element_release_ctx *ctx = x; 8071 RTE_SET_USED(dev); 8072 ctx->ret = rte_flow_error_set(ctx->error, EINVAL, 8073 RTE_FLOW_ERROR_TYPE_HANDLE, NULL, 8074 "invalid argument"); 8075 } 8076 8077 static int 8078 mlx5_flow_tunnel_item_release(struct rte_eth_dev *dev, 8079 struct rte_flow_item *pmd_items, 8080 uint32_t num_items, struct rte_flow_error *err) 8081 { 8082 struct tunnel_db_element_release_ctx ctx = { 8083 .items = pmd_items, 8084 .actions = NULL, 8085 .num_elements = num_items, 8086 .error = err, 8087 }; 8088 8089 mlx5_access_tunnel_offload_db(dev, tunnel_element_release_match, 8090 tunnel_element_release_hit, 8091 tunnel_element_release_miss, &ctx, false); 8092 8093 return ctx.ret; 8094 } 8095 8096 static int 8097 mlx5_flow_tunnel_action_release(struct rte_eth_dev *dev, 8098 struct rte_flow_action *pmd_actions, 8099 uint32_t num_actions, struct rte_flow_error *err) 8100 { 8101 struct tunnel_db_element_release_ctx ctx = { 8102 .items = NULL, 8103 .actions = pmd_actions, 8104 .num_elements = num_actions, 8105 .error = err, 8106 }; 8107 8108 mlx5_access_tunnel_offload_db(dev, tunnel_element_release_match, 8109 tunnel_element_release_hit, 8110 tunnel_element_release_miss, &ctx, false); 8111 8112 return ctx.ret; 8113 } 8114 8115 static int 8116 mlx5_flow_tunnel_get_restore_info(struct rte_eth_dev *dev, 8117 struct rte_mbuf *m, 8118 struct rte_flow_restore_info *info, 8119 struct rte_flow_error *err) 8120 { 8121 uint64_t ol_flags = m->ol_flags; 8122 const struct mlx5_flow_tbl_data_entry *tble; 8123 const uint64_t mask = PKT_RX_FDIR | PKT_RX_FDIR_ID; 8124 8125 if (!is_tunnel_offload_active(dev)) { 8126 info->flags = 0; 8127 return 0; 8128 } 8129 8130 if ((ol_flags & mask) != mask) 8131 goto err; 8132 tble = tunnel_mark_decode(dev, m->hash.fdir.hi); 8133 if (!tble) { 8134 DRV_LOG(DEBUG, "port %u invalid miss tunnel mark %#x", 8135 dev->data->port_id, m->hash.fdir.hi); 8136 goto err; 8137 } 8138 MLX5_ASSERT(tble->tunnel); 8139 memcpy(&info->tunnel, &tble->tunnel->app_tunnel, sizeof(info->tunnel)); 8140 info->group_id = tble->group_id; 8141 info->flags = RTE_FLOW_RESTORE_INFO_TUNNEL | 8142 RTE_FLOW_RESTORE_INFO_GROUP_ID | 8143 RTE_FLOW_RESTORE_INFO_ENCAPSULATED; 8144 8145 return 0; 8146 8147 err: 8148 return rte_flow_error_set(err, EINVAL, 8149 RTE_FLOW_ERROR_TYPE_UNSPECIFIED, NULL, 8150 "failed to get restore info"); 8151 } 8152 8153 #else /* HAVE_IBV_FLOW_DV_SUPPORT */ 8154 static int 8155 mlx5_flow_tunnel_decap_set(__rte_unused struct rte_eth_dev *dev, 8156 __rte_unused struct rte_flow_tunnel *app_tunnel, 8157 __rte_unused struct rte_flow_action **actions, 8158 __rte_unused uint32_t *num_of_actions, 8159 __rte_unused struct rte_flow_error *error) 8160 { 8161 return -ENOTSUP; 8162 } 8163 8164 static int 8165 mlx5_flow_tunnel_match(__rte_unused struct rte_eth_dev *dev, 8166 __rte_unused struct rte_flow_tunnel *app_tunnel, 8167 __rte_unused struct rte_flow_item **items, 8168 __rte_unused uint32_t *num_of_items, 8169 __rte_unused struct rte_flow_error *error) 8170 { 8171 return -ENOTSUP; 8172 } 8173 8174 static int 8175 mlx5_flow_tunnel_item_release(__rte_unused struct rte_eth_dev *dev, 8176 __rte_unused struct rte_flow_item *pmd_items, 8177 __rte_unused uint32_t num_items, 8178 __rte_unused struct rte_flow_error *err) 8179 { 8180 return -ENOTSUP; 8181 } 8182 8183 static int 8184 mlx5_flow_tunnel_action_release(__rte_unused struct rte_eth_dev *dev, 8185 __rte_unused struct rte_flow_action *pmd_action, 8186 __rte_unused uint32_t num_actions, 8187 __rte_unused struct rte_flow_error *err) 8188 { 8189 return -ENOTSUP; 8190 } 8191 8192 static int 8193 mlx5_flow_tunnel_get_restore_info(__rte_unused struct rte_eth_dev *dev, 8194 __rte_unused struct rte_mbuf *m, 8195 __rte_unused struct rte_flow_restore_info *i, 8196 __rte_unused struct rte_flow_error *err) 8197 { 8198 return -ENOTSUP; 8199 } 8200 8201 static int 8202 flow_tunnel_add_default_miss(__rte_unused struct rte_eth_dev *dev, 8203 __rte_unused struct rte_flow *flow, 8204 __rte_unused const struct rte_flow_attr *attr, 8205 __rte_unused const struct rte_flow_action *actions, 8206 __rte_unused uint32_t flow_idx, 8207 __rte_unused struct tunnel_default_miss_ctx *ctx, 8208 __rte_unused struct rte_flow_error *error) 8209 { 8210 return -ENOTSUP; 8211 } 8212 8213 static struct mlx5_flow_tunnel * 8214 mlx5_find_tunnel_id(__rte_unused struct rte_eth_dev *dev, 8215 __rte_unused uint32_t id) 8216 { 8217 return NULL; 8218 } 8219 8220 static void 8221 mlx5_flow_tunnel_free(__rte_unused struct rte_eth_dev *dev, 8222 __rte_unused struct mlx5_flow_tunnel *tunnel) 8223 { 8224 } 8225 8226 static uint32_t 8227 tunnel_flow_group_to_flow_table(__rte_unused struct rte_eth_dev *dev, 8228 __rte_unused const struct mlx5_flow_tunnel *t, 8229 __rte_unused uint32_t group, 8230 __rte_unused uint32_t *table, 8231 struct rte_flow_error *error) 8232 { 8233 return rte_flow_error_set(error, ENOTSUP, 8234 RTE_FLOW_ERROR_TYPE_UNSPECIFIED, NULL, 8235 "tunnel offload requires DV support"); 8236 } 8237 8238 void 8239 mlx5_release_tunnel_hub(__rte_unused struct mlx5_dev_ctx_shared *sh, 8240 __rte_unused uint16_t port_id) 8241 { 8242 } 8243 #endif /* HAVE_IBV_FLOW_DV_SUPPORT */ 8244 8245