1 /* SPDX-License-Identifier: BSD-3-Clause 2 * Copyright 2016 6WIND S.A. 3 * Copyright 2016 Mellanox Technologies, Ltd 4 */ 5 6 #include <stdalign.h> 7 #include <stdint.h> 8 #include <string.h> 9 #include <stdbool.h> 10 #include <sys/queue.h> 11 12 #include <rte_common.h> 13 #include <rte_ether.h> 14 #include <ethdev_driver.h> 15 #include <rte_eal_paging.h> 16 #include <rte_flow.h> 17 #include <rte_cycles.h> 18 #include <rte_flow_driver.h> 19 #include <rte_malloc.h> 20 #include <rte_ip.h> 21 22 #include <mlx5_glue.h> 23 #include <mlx5_devx_cmds.h> 24 #include <mlx5_prm.h> 25 #include <mlx5_malloc.h> 26 27 #include "mlx5_defs.h" 28 #include "mlx5.h" 29 #include "mlx5_flow.h" 30 #include "mlx5_flow_os.h" 31 #include "mlx5_rx.h" 32 #include "mlx5_tx.h" 33 #include "mlx5_common_os.h" 34 #include "rte_pmd_mlx5.h" 35 36 struct tunnel_default_miss_ctx { 37 uint16_t *queue; 38 __extension__ 39 union { 40 struct rte_flow_action_rss action_rss; 41 struct rte_flow_action_queue miss_queue; 42 struct rte_flow_action_jump miss_jump; 43 uint8_t raw[0]; 44 }; 45 }; 46 47 static int 48 flow_tunnel_add_default_miss(struct rte_eth_dev *dev, 49 struct rte_flow *flow, 50 const struct rte_flow_attr *attr, 51 const struct rte_flow_action *app_actions, 52 uint32_t flow_idx, 53 struct tunnel_default_miss_ctx *ctx, 54 struct rte_flow_error *error); 55 static struct mlx5_flow_tunnel * 56 mlx5_find_tunnel_id(struct rte_eth_dev *dev, uint32_t id); 57 static void 58 mlx5_flow_tunnel_free(struct rte_eth_dev *dev, struct mlx5_flow_tunnel *tunnel); 59 static uint32_t 60 tunnel_flow_group_to_flow_table(struct rte_eth_dev *dev, 61 const struct mlx5_flow_tunnel *tunnel, 62 uint32_t group, uint32_t *table, 63 struct rte_flow_error *error); 64 65 static struct mlx5_flow_workspace *mlx5_flow_push_thread_workspace(void); 66 static void mlx5_flow_pop_thread_workspace(void); 67 68 69 /** Device flow drivers. */ 70 extern const struct mlx5_flow_driver_ops mlx5_flow_verbs_drv_ops; 71 72 const struct mlx5_flow_driver_ops mlx5_flow_null_drv_ops; 73 74 const struct mlx5_flow_driver_ops *flow_drv_ops[] = { 75 [MLX5_FLOW_TYPE_MIN] = &mlx5_flow_null_drv_ops, 76 #if defined(HAVE_IBV_FLOW_DV_SUPPORT) || !defined(HAVE_INFINIBAND_VERBS_H) 77 [MLX5_FLOW_TYPE_DV] = &mlx5_flow_dv_drv_ops, 78 #endif 79 [MLX5_FLOW_TYPE_VERBS] = &mlx5_flow_verbs_drv_ops, 80 [MLX5_FLOW_TYPE_MAX] = &mlx5_flow_null_drv_ops 81 }; 82 83 /** Helper macro to build input graph for mlx5_flow_expand_rss(). */ 84 #define MLX5_FLOW_EXPAND_RSS_NEXT(...) \ 85 (const int []){ \ 86 __VA_ARGS__, 0, \ 87 } 88 89 /** Node object of input graph for mlx5_flow_expand_rss(). */ 90 struct mlx5_flow_expand_node { 91 const int *const next; 92 /**< 93 * List of next node indexes. Index 0 is interpreted as a terminator. 94 */ 95 const enum rte_flow_item_type type; 96 /**< Pattern item type of current node. */ 97 uint64_t rss_types; 98 /**< 99 * RSS types bit-field associated with this node 100 * (see ETH_RSS_* definitions). 101 */ 102 }; 103 104 /** Object returned by mlx5_flow_expand_rss(). */ 105 struct mlx5_flow_expand_rss { 106 uint32_t entries; 107 /**< Number of entries @p patterns and @p priorities. */ 108 struct { 109 struct rte_flow_item *pattern; /**< Expanded pattern array. */ 110 uint32_t priority; /**< Priority offset for each expansion. */ 111 } entry[]; 112 }; 113 114 static enum rte_flow_item_type 115 mlx5_flow_expand_rss_item_complete(const struct rte_flow_item *item) 116 { 117 enum rte_flow_item_type ret = RTE_FLOW_ITEM_TYPE_VOID; 118 uint16_t ether_type = 0; 119 uint16_t ether_type_m; 120 uint8_t ip_next_proto = 0; 121 uint8_t ip_next_proto_m; 122 123 if (item == NULL || item->spec == NULL) 124 return ret; 125 switch (item->type) { 126 case RTE_FLOW_ITEM_TYPE_ETH: 127 if (item->mask) 128 ether_type_m = ((const struct rte_flow_item_eth *) 129 (item->mask))->type; 130 else 131 ether_type_m = rte_flow_item_eth_mask.type; 132 if (ether_type_m != RTE_BE16(0xFFFF)) 133 break; 134 ether_type = ((const struct rte_flow_item_eth *) 135 (item->spec))->type; 136 if (rte_be_to_cpu_16(ether_type) == RTE_ETHER_TYPE_IPV4) 137 ret = RTE_FLOW_ITEM_TYPE_IPV4; 138 else if (rte_be_to_cpu_16(ether_type) == RTE_ETHER_TYPE_IPV6) 139 ret = RTE_FLOW_ITEM_TYPE_IPV6; 140 else if (rte_be_to_cpu_16(ether_type) == RTE_ETHER_TYPE_VLAN) 141 ret = RTE_FLOW_ITEM_TYPE_VLAN; 142 else 143 ret = RTE_FLOW_ITEM_TYPE_END; 144 break; 145 case RTE_FLOW_ITEM_TYPE_VLAN: 146 if (item->mask) 147 ether_type_m = ((const struct rte_flow_item_vlan *) 148 (item->mask))->inner_type; 149 else 150 ether_type_m = rte_flow_item_vlan_mask.inner_type; 151 if (ether_type_m != RTE_BE16(0xFFFF)) 152 break; 153 ether_type = ((const struct rte_flow_item_vlan *) 154 (item->spec))->inner_type; 155 if (rte_be_to_cpu_16(ether_type) == RTE_ETHER_TYPE_IPV4) 156 ret = RTE_FLOW_ITEM_TYPE_IPV4; 157 else if (rte_be_to_cpu_16(ether_type) == RTE_ETHER_TYPE_IPV6) 158 ret = RTE_FLOW_ITEM_TYPE_IPV6; 159 else if (rte_be_to_cpu_16(ether_type) == RTE_ETHER_TYPE_VLAN) 160 ret = RTE_FLOW_ITEM_TYPE_VLAN; 161 else 162 ret = RTE_FLOW_ITEM_TYPE_END; 163 break; 164 case RTE_FLOW_ITEM_TYPE_IPV4: 165 if (item->mask) 166 ip_next_proto_m = ((const struct rte_flow_item_ipv4 *) 167 (item->mask))->hdr.next_proto_id; 168 else 169 ip_next_proto_m = 170 rte_flow_item_ipv4_mask.hdr.next_proto_id; 171 if (ip_next_proto_m != 0xFF) 172 break; 173 ip_next_proto = ((const struct rte_flow_item_ipv4 *) 174 (item->spec))->hdr.next_proto_id; 175 if (ip_next_proto == IPPROTO_UDP) 176 ret = RTE_FLOW_ITEM_TYPE_UDP; 177 else if (ip_next_proto == IPPROTO_TCP) 178 ret = RTE_FLOW_ITEM_TYPE_TCP; 179 else if (ip_next_proto == IPPROTO_IP) 180 ret = RTE_FLOW_ITEM_TYPE_IPV4; 181 else if (ip_next_proto == IPPROTO_IPV6) 182 ret = RTE_FLOW_ITEM_TYPE_IPV6; 183 else 184 ret = RTE_FLOW_ITEM_TYPE_END; 185 break; 186 case RTE_FLOW_ITEM_TYPE_IPV6: 187 if (item->mask) 188 ip_next_proto_m = ((const struct rte_flow_item_ipv6 *) 189 (item->mask))->hdr.proto; 190 else 191 ip_next_proto_m = 192 rte_flow_item_ipv6_mask.hdr.proto; 193 if (ip_next_proto_m != 0xFF) 194 break; 195 ip_next_proto = ((const struct rte_flow_item_ipv6 *) 196 (item->spec))->hdr.proto; 197 if (ip_next_proto == IPPROTO_UDP) 198 ret = RTE_FLOW_ITEM_TYPE_UDP; 199 else if (ip_next_proto == IPPROTO_TCP) 200 ret = RTE_FLOW_ITEM_TYPE_TCP; 201 else if (ip_next_proto == IPPROTO_IP) 202 ret = RTE_FLOW_ITEM_TYPE_IPV4; 203 else if (ip_next_proto == IPPROTO_IPV6) 204 ret = RTE_FLOW_ITEM_TYPE_IPV6; 205 else 206 ret = RTE_FLOW_ITEM_TYPE_END; 207 break; 208 default: 209 ret = RTE_FLOW_ITEM_TYPE_VOID; 210 break; 211 } 212 return ret; 213 } 214 215 #define MLX5_RSS_EXP_ELT_N 8 216 217 /** 218 * Expand RSS flows into several possible flows according to the RSS hash 219 * fields requested and the driver capabilities. 220 * 221 * @param[out] buf 222 * Buffer to store the result expansion. 223 * @param[in] size 224 * Buffer size in bytes. If 0, @p buf can be NULL. 225 * @param[in] pattern 226 * User flow pattern. 227 * @param[in] types 228 * RSS types to expand (see ETH_RSS_* definitions). 229 * @param[in] graph 230 * Input graph to expand @p pattern according to @p types. 231 * @param[in] graph_root_index 232 * Index of root node in @p graph, typically 0. 233 * 234 * @return 235 * A positive value representing the size of @p buf in bytes regardless of 236 * @p size on success, a negative errno value otherwise and rte_errno is 237 * set, the following errors are defined: 238 * 239 * -E2BIG: graph-depth @p graph is too deep. 240 */ 241 static int 242 mlx5_flow_expand_rss(struct mlx5_flow_expand_rss *buf, size_t size, 243 const struct rte_flow_item *pattern, uint64_t types, 244 const struct mlx5_flow_expand_node graph[], 245 int graph_root_index) 246 { 247 const struct rte_flow_item *item; 248 const struct mlx5_flow_expand_node *node = &graph[graph_root_index]; 249 const int *next_node; 250 const int *stack[MLX5_RSS_EXP_ELT_N]; 251 int stack_pos = 0; 252 struct rte_flow_item flow_items[MLX5_RSS_EXP_ELT_N]; 253 unsigned int i; 254 size_t lsize; 255 size_t user_pattern_size = 0; 256 void *addr = NULL; 257 const struct mlx5_flow_expand_node *next = NULL; 258 struct rte_flow_item missed_item; 259 int missed = 0; 260 int elt = 0; 261 const struct rte_flow_item *last_item = NULL; 262 263 memset(&missed_item, 0, sizeof(missed_item)); 264 lsize = offsetof(struct mlx5_flow_expand_rss, entry) + 265 MLX5_RSS_EXP_ELT_N * sizeof(buf->entry[0]); 266 if (lsize <= size) { 267 buf->entry[0].priority = 0; 268 buf->entry[0].pattern = (void *)&buf->entry[MLX5_RSS_EXP_ELT_N]; 269 buf->entries = 0; 270 addr = buf->entry[0].pattern; 271 } 272 for (item = pattern; item->type != RTE_FLOW_ITEM_TYPE_END; item++) { 273 if (item->type != RTE_FLOW_ITEM_TYPE_VOID) 274 last_item = item; 275 for (i = 0; node->next && node->next[i]; ++i) { 276 next = &graph[node->next[i]]; 277 if (next->type == item->type) 278 break; 279 } 280 if (next) 281 node = next; 282 user_pattern_size += sizeof(*item); 283 } 284 user_pattern_size += sizeof(*item); /* Handle END item. */ 285 lsize += user_pattern_size; 286 /* Copy the user pattern in the first entry of the buffer. */ 287 if (lsize <= size) { 288 rte_memcpy(addr, pattern, user_pattern_size); 289 addr = (void *)(((uintptr_t)addr) + user_pattern_size); 290 buf->entries = 1; 291 } 292 /* Start expanding. */ 293 memset(flow_items, 0, sizeof(flow_items)); 294 user_pattern_size -= sizeof(*item); 295 /* 296 * Check if the last valid item has spec set, need complete pattern, 297 * and the pattern can be used for expansion. 298 */ 299 missed_item.type = mlx5_flow_expand_rss_item_complete(last_item); 300 if (missed_item.type == RTE_FLOW_ITEM_TYPE_END) { 301 /* Item type END indicates expansion is not required. */ 302 return lsize; 303 } 304 if (missed_item.type != RTE_FLOW_ITEM_TYPE_VOID) { 305 next = NULL; 306 missed = 1; 307 for (i = 0; node->next && node->next[i]; ++i) { 308 next = &graph[node->next[i]]; 309 if (next->type == missed_item.type) { 310 flow_items[0].type = missed_item.type; 311 flow_items[1].type = RTE_FLOW_ITEM_TYPE_END; 312 break; 313 } 314 next = NULL; 315 } 316 } 317 if (next && missed) { 318 elt = 2; /* missed item + item end. */ 319 node = next; 320 lsize += elt * sizeof(*item) + user_pattern_size; 321 if ((node->rss_types & types) && lsize <= size) { 322 buf->entry[buf->entries].priority = 1; 323 buf->entry[buf->entries].pattern = addr; 324 buf->entries++; 325 rte_memcpy(addr, buf->entry[0].pattern, 326 user_pattern_size); 327 addr = (void *)(((uintptr_t)addr) + user_pattern_size); 328 rte_memcpy(addr, flow_items, elt * sizeof(*item)); 329 addr = (void *)(((uintptr_t)addr) + 330 elt * sizeof(*item)); 331 } 332 } 333 memset(flow_items, 0, sizeof(flow_items)); 334 next_node = node->next; 335 stack[stack_pos] = next_node; 336 node = next_node ? &graph[*next_node] : NULL; 337 while (node) { 338 flow_items[stack_pos].type = node->type; 339 if (node->rss_types & types) { 340 /* 341 * compute the number of items to copy from the 342 * expansion and copy it. 343 * When the stack_pos is 0, there are 1 element in it, 344 * plus the addition END item. 345 */ 346 elt = stack_pos + 2; 347 flow_items[stack_pos + 1].type = RTE_FLOW_ITEM_TYPE_END; 348 lsize += elt * sizeof(*item) + user_pattern_size; 349 if (lsize <= size) { 350 size_t n = elt * sizeof(*item); 351 352 buf->entry[buf->entries].priority = 353 stack_pos + 1 + missed; 354 buf->entry[buf->entries].pattern = addr; 355 buf->entries++; 356 rte_memcpy(addr, buf->entry[0].pattern, 357 user_pattern_size); 358 addr = (void *)(((uintptr_t)addr) + 359 user_pattern_size); 360 rte_memcpy(addr, &missed_item, 361 missed * sizeof(*item)); 362 addr = (void *)(((uintptr_t)addr) + 363 missed * sizeof(*item)); 364 rte_memcpy(addr, flow_items, n); 365 addr = (void *)(((uintptr_t)addr) + n); 366 } 367 } 368 /* Go deeper. */ 369 if (node->next) { 370 next_node = node->next; 371 if (stack_pos++ == MLX5_RSS_EXP_ELT_N) { 372 rte_errno = E2BIG; 373 return -rte_errno; 374 } 375 stack[stack_pos] = next_node; 376 } else if (*(next_node + 1)) { 377 /* Follow up with the next possibility. */ 378 ++next_node; 379 } else { 380 /* Move to the next path. */ 381 if (stack_pos) 382 next_node = stack[--stack_pos]; 383 next_node++; 384 stack[stack_pos] = next_node; 385 } 386 node = *next_node ? &graph[*next_node] : NULL; 387 }; 388 return lsize; 389 } 390 391 enum mlx5_expansion { 392 MLX5_EXPANSION_ROOT, 393 MLX5_EXPANSION_ROOT_OUTER, 394 MLX5_EXPANSION_ROOT_ETH_VLAN, 395 MLX5_EXPANSION_ROOT_OUTER_ETH_VLAN, 396 MLX5_EXPANSION_OUTER_ETH, 397 MLX5_EXPANSION_OUTER_ETH_VLAN, 398 MLX5_EXPANSION_OUTER_VLAN, 399 MLX5_EXPANSION_OUTER_IPV4, 400 MLX5_EXPANSION_OUTER_IPV4_UDP, 401 MLX5_EXPANSION_OUTER_IPV4_TCP, 402 MLX5_EXPANSION_OUTER_IPV6, 403 MLX5_EXPANSION_OUTER_IPV6_UDP, 404 MLX5_EXPANSION_OUTER_IPV6_TCP, 405 MLX5_EXPANSION_VXLAN, 406 MLX5_EXPANSION_VXLAN_GPE, 407 MLX5_EXPANSION_GRE, 408 MLX5_EXPANSION_MPLS, 409 MLX5_EXPANSION_ETH, 410 MLX5_EXPANSION_ETH_VLAN, 411 MLX5_EXPANSION_VLAN, 412 MLX5_EXPANSION_IPV4, 413 MLX5_EXPANSION_IPV4_UDP, 414 MLX5_EXPANSION_IPV4_TCP, 415 MLX5_EXPANSION_IPV6, 416 MLX5_EXPANSION_IPV6_UDP, 417 MLX5_EXPANSION_IPV6_TCP, 418 }; 419 420 /** Supported expansion of items. */ 421 static const struct mlx5_flow_expand_node mlx5_support_expansion[] = { 422 [MLX5_EXPANSION_ROOT] = { 423 .next = MLX5_FLOW_EXPAND_RSS_NEXT(MLX5_EXPANSION_ETH, 424 MLX5_EXPANSION_IPV4, 425 MLX5_EXPANSION_IPV6), 426 .type = RTE_FLOW_ITEM_TYPE_END, 427 }, 428 [MLX5_EXPANSION_ROOT_OUTER] = { 429 .next = MLX5_FLOW_EXPAND_RSS_NEXT(MLX5_EXPANSION_OUTER_ETH, 430 MLX5_EXPANSION_OUTER_IPV4, 431 MLX5_EXPANSION_OUTER_IPV6), 432 .type = RTE_FLOW_ITEM_TYPE_END, 433 }, 434 [MLX5_EXPANSION_ROOT_ETH_VLAN] = { 435 .next = MLX5_FLOW_EXPAND_RSS_NEXT(MLX5_EXPANSION_ETH_VLAN), 436 .type = RTE_FLOW_ITEM_TYPE_END, 437 }, 438 [MLX5_EXPANSION_ROOT_OUTER_ETH_VLAN] = { 439 .next = MLX5_FLOW_EXPAND_RSS_NEXT 440 (MLX5_EXPANSION_OUTER_ETH_VLAN), 441 .type = RTE_FLOW_ITEM_TYPE_END, 442 }, 443 [MLX5_EXPANSION_OUTER_ETH] = { 444 .next = MLX5_FLOW_EXPAND_RSS_NEXT(MLX5_EXPANSION_OUTER_IPV4, 445 MLX5_EXPANSION_OUTER_IPV6, 446 MLX5_EXPANSION_MPLS), 447 .type = RTE_FLOW_ITEM_TYPE_ETH, 448 .rss_types = 0, 449 }, 450 [MLX5_EXPANSION_OUTER_ETH_VLAN] = { 451 .next = MLX5_FLOW_EXPAND_RSS_NEXT(MLX5_EXPANSION_OUTER_VLAN), 452 .type = RTE_FLOW_ITEM_TYPE_ETH, 453 .rss_types = 0, 454 }, 455 [MLX5_EXPANSION_OUTER_VLAN] = { 456 .next = MLX5_FLOW_EXPAND_RSS_NEXT(MLX5_EXPANSION_OUTER_IPV4, 457 MLX5_EXPANSION_OUTER_IPV6), 458 .type = RTE_FLOW_ITEM_TYPE_VLAN, 459 }, 460 [MLX5_EXPANSION_OUTER_IPV4] = { 461 .next = MLX5_FLOW_EXPAND_RSS_NEXT 462 (MLX5_EXPANSION_OUTER_IPV4_UDP, 463 MLX5_EXPANSION_OUTER_IPV4_TCP, 464 MLX5_EXPANSION_GRE, 465 MLX5_EXPANSION_IPV4, 466 MLX5_EXPANSION_IPV6), 467 .type = RTE_FLOW_ITEM_TYPE_IPV4, 468 .rss_types = ETH_RSS_IPV4 | ETH_RSS_FRAG_IPV4 | 469 ETH_RSS_NONFRAG_IPV4_OTHER, 470 }, 471 [MLX5_EXPANSION_OUTER_IPV4_UDP] = { 472 .next = MLX5_FLOW_EXPAND_RSS_NEXT(MLX5_EXPANSION_VXLAN, 473 MLX5_EXPANSION_VXLAN_GPE), 474 .type = RTE_FLOW_ITEM_TYPE_UDP, 475 .rss_types = ETH_RSS_NONFRAG_IPV4_UDP, 476 }, 477 [MLX5_EXPANSION_OUTER_IPV4_TCP] = { 478 .type = RTE_FLOW_ITEM_TYPE_TCP, 479 .rss_types = ETH_RSS_NONFRAG_IPV4_TCP, 480 }, 481 [MLX5_EXPANSION_OUTER_IPV6] = { 482 .next = MLX5_FLOW_EXPAND_RSS_NEXT 483 (MLX5_EXPANSION_OUTER_IPV6_UDP, 484 MLX5_EXPANSION_OUTER_IPV6_TCP, 485 MLX5_EXPANSION_IPV4, 486 MLX5_EXPANSION_IPV6, 487 MLX5_EXPANSION_GRE), 488 .type = RTE_FLOW_ITEM_TYPE_IPV6, 489 .rss_types = ETH_RSS_IPV6 | ETH_RSS_FRAG_IPV6 | 490 ETH_RSS_NONFRAG_IPV6_OTHER, 491 }, 492 [MLX5_EXPANSION_OUTER_IPV6_UDP] = { 493 .next = MLX5_FLOW_EXPAND_RSS_NEXT(MLX5_EXPANSION_VXLAN, 494 MLX5_EXPANSION_VXLAN_GPE), 495 .type = RTE_FLOW_ITEM_TYPE_UDP, 496 .rss_types = ETH_RSS_NONFRAG_IPV6_UDP, 497 }, 498 [MLX5_EXPANSION_OUTER_IPV6_TCP] = { 499 .type = RTE_FLOW_ITEM_TYPE_TCP, 500 .rss_types = ETH_RSS_NONFRAG_IPV6_TCP, 501 }, 502 [MLX5_EXPANSION_VXLAN] = { 503 .next = MLX5_FLOW_EXPAND_RSS_NEXT(MLX5_EXPANSION_ETH, 504 MLX5_EXPANSION_IPV4, 505 MLX5_EXPANSION_IPV6), 506 .type = RTE_FLOW_ITEM_TYPE_VXLAN, 507 }, 508 [MLX5_EXPANSION_VXLAN_GPE] = { 509 .next = MLX5_FLOW_EXPAND_RSS_NEXT(MLX5_EXPANSION_ETH, 510 MLX5_EXPANSION_IPV4, 511 MLX5_EXPANSION_IPV6), 512 .type = RTE_FLOW_ITEM_TYPE_VXLAN_GPE, 513 }, 514 [MLX5_EXPANSION_GRE] = { 515 .next = MLX5_FLOW_EXPAND_RSS_NEXT(MLX5_EXPANSION_IPV4, 516 MLX5_EXPANSION_IPV6), 517 .type = RTE_FLOW_ITEM_TYPE_GRE, 518 }, 519 [MLX5_EXPANSION_MPLS] = { 520 .next = MLX5_FLOW_EXPAND_RSS_NEXT(MLX5_EXPANSION_IPV4, 521 MLX5_EXPANSION_IPV6), 522 .type = RTE_FLOW_ITEM_TYPE_MPLS, 523 }, 524 [MLX5_EXPANSION_ETH] = { 525 .next = MLX5_FLOW_EXPAND_RSS_NEXT(MLX5_EXPANSION_IPV4, 526 MLX5_EXPANSION_IPV6), 527 .type = RTE_FLOW_ITEM_TYPE_ETH, 528 }, 529 [MLX5_EXPANSION_ETH_VLAN] = { 530 .next = MLX5_FLOW_EXPAND_RSS_NEXT(MLX5_EXPANSION_VLAN), 531 .type = RTE_FLOW_ITEM_TYPE_ETH, 532 }, 533 [MLX5_EXPANSION_VLAN] = { 534 .next = MLX5_FLOW_EXPAND_RSS_NEXT(MLX5_EXPANSION_IPV4, 535 MLX5_EXPANSION_IPV6), 536 .type = RTE_FLOW_ITEM_TYPE_VLAN, 537 }, 538 [MLX5_EXPANSION_IPV4] = { 539 .next = MLX5_FLOW_EXPAND_RSS_NEXT(MLX5_EXPANSION_IPV4_UDP, 540 MLX5_EXPANSION_IPV4_TCP), 541 .type = RTE_FLOW_ITEM_TYPE_IPV4, 542 .rss_types = ETH_RSS_IPV4 | ETH_RSS_FRAG_IPV4 | 543 ETH_RSS_NONFRAG_IPV4_OTHER, 544 }, 545 [MLX5_EXPANSION_IPV4_UDP] = { 546 .type = RTE_FLOW_ITEM_TYPE_UDP, 547 .rss_types = ETH_RSS_NONFRAG_IPV4_UDP, 548 }, 549 [MLX5_EXPANSION_IPV4_TCP] = { 550 .type = RTE_FLOW_ITEM_TYPE_TCP, 551 .rss_types = ETH_RSS_NONFRAG_IPV4_TCP, 552 }, 553 [MLX5_EXPANSION_IPV6] = { 554 .next = MLX5_FLOW_EXPAND_RSS_NEXT(MLX5_EXPANSION_IPV6_UDP, 555 MLX5_EXPANSION_IPV6_TCP), 556 .type = RTE_FLOW_ITEM_TYPE_IPV6, 557 .rss_types = ETH_RSS_IPV6 | ETH_RSS_FRAG_IPV6 | 558 ETH_RSS_NONFRAG_IPV6_OTHER, 559 }, 560 [MLX5_EXPANSION_IPV6_UDP] = { 561 .type = RTE_FLOW_ITEM_TYPE_UDP, 562 .rss_types = ETH_RSS_NONFRAG_IPV6_UDP, 563 }, 564 [MLX5_EXPANSION_IPV6_TCP] = { 565 .type = RTE_FLOW_ITEM_TYPE_TCP, 566 .rss_types = ETH_RSS_NONFRAG_IPV6_TCP, 567 }, 568 }; 569 570 static struct rte_flow_action_handle * 571 mlx5_action_handle_create(struct rte_eth_dev *dev, 572 const struct rte_flow_indir_action_conf *conf, 573 const struct rte_flow_action *action, 574 struct rte_flow_error *error); 575 static int mlx5_action_handle_destroy 576 (struct rte_eth_dev *dev, 577 struct rte_flow_action_handle *handle, 578 struct rte_flow_error *error); 579 static int mlx5_action_handle_update 580 (struct rte_eth_dev *dev, 581 struct rte_flow_action_handle *handle, 582 const void *update, 583 struct rte_flow_error *error); 584 static int mlx5_action_handle_query 585 (struct rte_eth_dev *dev, 586 const struct rte_flow_action_handle *handle, 587 void *data, 588 struct rte_flow_error *error); 589 static int 590 mlx5_flow_tunnel_decap_set(struct rte_eth_dev *dev, 591 struct rte_flow_tunnel *app_tunnel, 592 struct rte_flow_action **actions, 593 uint32_t *num_of_actions, 594 struct rte_flow_error *error); 595 static int 596 mlx5_flow_tunnel_match(struct rte_eth_dev *dev, 597 struct rte_flow_tunnel *app_tunnel, 598 struct rte_flow_item **items, 599 uint32_t *num_of_items, 600 struct rte_flow_error *error); 601 static int 602 mlx5_flow_tunnel_item_release(struct rte_eth_dev *dev, 603 struct rte_flow_item *pmd_items, 604 uint32_t num_items, struct rte_flow_error *err); 605 static int 606 mlx5_flow_tunnel_action_release(struct rte_eth_dev *dev, 607 struct rte_flow_action *pmd_actions, 608 uint32_t num_actions, 609 struct rte_flow_error *err); 610 static int 611 mlx5_flow_tunnel_get_restore_info(struct rte_eth_dev *dev, 612 struct rte_mbuf *m, 613 struct rte_flow_restore_info *info, 614 struct rte_flow_error *err); 615 616 static const struct rte_flow_ops mlx5_flow_ops = { 617 .validate = mlx5_flow_validate, 618 .create = mlx5_flow_create, 619 .destroy = mlx5_flow_destroy, 620 .flush = mlx5_flow_flush, 621 .isolate = mlx5_flow_isolate, 622 .query = mlx5_flow_query, 623 .dev_dump = mlx5_flow_dev_dump, 624 .get_aged_flows = mlx5_flow_get_aged_flows, 625 .action_handle_create = mlx5_action_handle_create, 626 .action_handle_destroy = mlx5_action_handle_destroy, 627 .action_handle_update = mlx5_action_handle_update, 628 .action_handle_query = mlx5_action_handle_query, 629 .tunnel_decap_set = mlx5_flow_tunnel_decap_set, 630 .tunnel_match = mlx5_flow_tunnel_match, 631 .tunnel_action_decap_release = mlx5_flow_tunnel_action_release, 632 .tunnel_item_release = mlx5_flow_tunnel_item_release, 633 .get_restore_info = mlx5_flow_tunnel_get_restore_info, 634 }; 635 636 /* Tunnel information. */ 637 struct mlx5_flow_tunnel_info { 638 uint64_t tunnel; /**< Tunnel bit (see MLX5_FLOW_*). */ 639 uint32_t ptype; /**< Tunnel Ptype (see RTE_PTYPE_*). */ 640 }; 641 642 static struct mlx5_flow_tunnel_info tunnels_info[] = { 643 { 644 .tunnel = MLX5_FLOW_LAYER_VXLAN, 645 .ptype = RTE_PTYPE_TUNNEL_VXLAN | RTE_PTYPE_L4_UDP, 646 }, 647 { 648 .tunnel = MLX5_FLOW_LAYER_GENEVE, 649 .ptype = RTE_PTYPE_TUNNEL_GENEVE | RTE_PTYPE_L4_UDP, 650 }, 651 { 652 .tunnel = MLX5_FLOW_LAYER_VXLAN_GPE, 653 .ptype = RTE_PTYPE_TUNNEL_VXLAN_GPE | RTE_PTYPE_L4_UDP, 654 }, 655 { 656 .tunnel = MLX5_FLOW_LAYER_GRE, 657 .ptype = RTE_PTYPE_TUNNEL_GRE, 658 }, 659 { 660 .tunnel = MLX5_FLOW_LAYER_MPLS | MLX5_FLOW_LAYER_OUTER_L4_UDP, 661 .ptype = RTE_PTYPE_TUNNEL_MPLS_IN_UDP | RTE_PTYPE_L4_UDP, 662 }, 663 { 664 .tunnel = MLX5_FLOW_LAYER_MPLS, 665 .ptype = RTE_PTYPE_TUNNEL_MPLS_IN_GRE, 666 }, 667 { 668 .tunnel = MLX5_FLOW_LAYER_NVGRE, 669 .ptype = RTE_PTYPE_TUNNEL_NVGRE, 670 }, 671 { 672 .tunnel = MLX5_FLOW_LAYER_IPIP, 673 .ptype = RTE_PTYPE_TUNNEL_IP, 674 }, 675 { 676 .tunnel = MLX5_FLOW_LAYER_IPV6_ENCAP, 677 .ptype = RTE_PTYPE_TUNNEL_IP, 678 }, 679 { 680 .tunnel = MLX5_FLOW_LAYER_GTP, 681 .ptype = RTE_PTYPE_TUNNEL_GTPU, 682 }, 683 }; 684 685 686 687 /** 688 * Translate tag ID to register. 689 * 690 * @param[in] dev 691 * Pointer to the Ethernet device structure. 692 * @param[in] feature 693 * The feature that request the register. 694 * @param[in] id 695 * The request register ID. 696 * @param[out] error 697 * Error description in case of any. 698 * 699 * @return 700 * The request register on success, a negative errno 701 * value otherwise and rte_errno is set. 702 */ 703 int 704 mlx5_flow_get_reg_id(struct rte_eth_dev *dev, 705 enum mlx5_feature_name feature, 706 uint32_t id, 707 struct rte_flow_error *error) 708 { 709 struct mlx5_priv *priv = dev->data->dev_private; 710 struct mlx5_dev_config *config = &priv->config; 711 enum modify_reg start_reg; 712 bool skip_mtr_reg = false; 713 714 switch (feature) { 715 case MLX5_HAIRPIN_RX: 716 return REG_B; 717 case MLX5_HAIRPIN_TX: 718 return REG_A; 719 case MLX5_METADATA_RX: 720 switch (config->dv_xmeta_en) { 721 case MLX5_XMETA_MODE_LEGACY: 722 return REG_B; 723 case MLX5_XMETA_MODE_META16: 724 return REG_C_0; 725 case MLX5_XMETA_MODE_META32: 726 return REG_C_1; 727 } 728 break; 729 case MLX5_METADATA_TX: 730 return REG_A; 731 case MLX5_METADATA_FDB: 732 switch (config->dv_xmeta_en) { 733 case MLX5_XMETA_MODE_LEGACY: 734 return REG_NON; 735 case MLX5_XMETA_MODE_META16: 736 return REG_C_0; 737 case MLX5_XMETA_MODE_META32: 738 return REG_C_1; 739 } 740 break; 741 case MLX5_FLOW_MARK: 742 switch (config->dv_xmeta_en) { 743 case MLX5_XMETA_MODE_LEGACY: 744 return REG_NON; 745 case MLX5_XMETA_MODE_META16: 746 return REG_C_1; 747 case MLX5_XMETA_MODE_META32: 748 return REG_C_0; 749 } 750 break; 751 case MLX5_MTR_SFX: 752 /* 753 * If meter color and flow match share one register, flow match 754 * should use the meter color register for match. 755 */ 756 if (priv->mtr_reg_share) 757 return priv->mtr_color_reg; 758 else 759 return priv->mtr_color_reg != REG_C_2 ? REG_C_2 : 760 REG_C_3; 761 case MLX5_MTR_COLOR: 762 case MLX5_ASO_FLOW_HIT: /* Both features use the same REG_C. */ 763 MLX5_ASSERT(priv->mtr_color_reg != REG_NON); 764 return priv->mtr_color_reg; 765 case MLX5_COPY_MARK: 766 /* 767 * Metadata COPY_MARK register using is in meter suffix sub 768 * flow while with meter. It's safe to share the same register. 769 */ 770 return priv->mtr_color_reg != REG_C_2 ? REG_C_2 : REG_C_3; 771 case MLX5_APP_TAG: 772 /* 773 * If meter is enable, it will engage the register for color 774 * match and flow match. If meter color match is not using the 775 * REG_C_2, need to skip the REG_C_x be used by meter color 776 * match. 777 * If meter is disable, free to use all available registers. 778 */ 779 start_reg = priv->mtr_color_reg != REG_C_2 ? REG_C_2 : 780 (priv->mtr_reg_share ? REG_C_3 : REG_C_4); 781 skip_mtr_reg = !!(priv->mtr_en && start_reg == REG_C_2); 782 if (id > (uint32_t)(REG_C_7 - start_reg)) 783 return rte_flow_error_set(error, EINVAL, 784 RTE_FLOW_ERROR_TYPE_ITEM, 785 NULL, "invalid tag id"); 786 if (config->flow_mreg_c[id + start_reg - REG_C_0] == REG_NON) 787 return rte_flow_error_set(error, ENOTSUP, 788 RTE_FLOW_ERROR_TYPE_ITEM, 789 NULL, "unsupported tag id"); 790 /* 791 * This case means meter is using the REG_C_x great than 2. 792 * Take care not to conflict with meter color REG_C_x. 793 * If the available index REG_C_y >= REG_C_x, skip the 794 * color register. 795 */ 796 if (skip_mtr_reg && config->flow_mreg_c 797 [id + start_reg - REG_C_0] >= priv->mtr_color_reg) { 798 if (id >= (uint32_t)(REG_C_7 - start_reg)) 799 return rte_flow_error_set(error, EINVAL, 800 RTE_FLOW_ERROR_TYPE_ITEM, 801 NULL, "invalid tag id"); 802 if (config->flow_mreg_c 803 [id + 1 + start_reg - REG_C_0] != REG_NON) 804 return config->flow_mreg_c 805 [id + 1 + start_reg - REG_C_0]; 806 return rte_flow_error_set(error, ENOTSUP, 807 RTE_FLOW_ERROR_TYPE_ITEM, 808 NULL, "unsupported tag id"); 809 } 810 return config->flow_mreg_c[id + start_reg - REG_C_0]; 811 } 812 MLX5_ASSERT(false); 813 return rte_flow_error_set(error, EINVAL, 814 RTE_FLOW_ERROR_TYPE_UNSPECIFIED, 815 NULL, "invalid feature name"); 816 } 817 818 /** 819 * Check extensive flow metadata register support. 820 * 821 * @param dev 822 * Pointer to rte_eth_dev structure. 823 * 824 * @return 825 * True if device supports extensive flow metadata register, otherwise false. 826 */ 827 bool 828 mlx5_flow_ext_mreg_supported(struct rte_eth_dev *dev) 829 { 830 struct mlx5_priv *priv = dev->data->dev_private; 831 struct mlx5_dev_config *config = &priv->config; 832 833 /* 834 * Having available reg_c can be regarded inclusively as supporting 835 * extensive flow metadata register, which could mean, 836 * - metadata register copy action by modify header. 837 * - 16 modify header actions is supported. 838 * - reg_c's are preserved across different domain (FDB and NIC) on 839 * packet loopback by flow lookup miss. 840 */ 841 return config->flow_mreg_c[2] != REG_NON; 842 } 843 844 /** 845 * Get the lowest priority. 846 * 847 * @param[in] dev 848 * Pointer to the Ethernet device structure. 849 * @param[in] attributes 850 * Pointer to device flow rule attributes. 851 * 852 * @return 853 * The value of lowest priority of flow. 854 */ 855 uint32_t 856 mlx5_get_lowest_priority(struct rte_eth_dev *dev, 857 const struct rte_flow_attr *attr) 858 { 859 struct mlx5_priv *priv = dev->data->dev_private; 860 861 if (!attr->group && !attr->transfer) 862 return priv->config.flow_prio - 2; 863 return MLX5_NON_ROOT_FLOW_MAX_PRIO - 1; 864 } 865 866 /** 867 * Calculate matcher priority of the flow. 868 * 869 * @param[in] dev 870 * Pointer to the Ethernet device structure. 871 * @param[in] attr 872 * Pointer to device flow rule attributes. 873 * @param[in] subpriority 874 * The priority based on the items. 875 * @return 876 * The matcher priority of the flow. 877 */ 878 uint16_t 879 mlx5_get_matcher_priority(struct rte_eth_dev *dev, 880 const struct rte_flow_attr *attr, 881 uint32_t subpriority) 882 { 883 uint16_t priority = (uint16_t)attr->priority; 884 struct mlx5_priv *priv = dev->data->dev_private; 885 886 if (!attr->group && !attr->transfer) { 887 if (attr->priority == MLX5_FLOW_LOWEST_PRIO_INDICATOR) 888 priority = priv->config.flow_prio - 1; 889 return mlx5_os_flow_adjust_priority(dev, priority, subpriority); 890 } 891 if (attr->priority == MLX5_FLOW_LOWEST_PRIO_INDICATOR) 892 priority = MLX5_NON_ROOT_FLOW_MAX_PRIO; 893 return priority * 3 + subpriority; 894 } 895 896 /** 897 * Verify the @p item specifications (spec, last, mask) are compatible with the 898 * NIC capabilities. 899 * 900 * @param[in] item 901 * Item specification. 902 * @param[in] mask 903 * @p item->mask or flow default bit-masks. 904 * @param[in] nic_mask 905 * Bit-masks covering supported fields by the NIC to compare with user mask. 906 * @param[in] size 907 * Bit-masks size in bytes. 908 * @param[in] range_accepted 909 * True if range of values is accepted for specific fields, false otherwise. 910 * @param[out] error 911 * Pointer to error structure. 912 * 913 * @return 914 * 0 on success, a negative errno value otherwise and rte_errno is set. 915 */ 916 int 917 mlx5_flow_item_acceptable(const struct rte_flow_item *item, 918 const uint8_t *mask, 919 const uint8_t *nic_mask, 920 unsigned int size, 921 bool range_accepted, 922 struct rte_flow_error *error) 923 { 924 unsigned int i; 925 926 MLX5_ASSERT(nic_mask); 927 for (i = 0; i < size; ++i) 928 if ((nic_mask[i] | mask[i]) != nic_mask[i]) 929 return rte_flow_error_set(error, ENOTSUP, 930 RTE_FLOW_ERROR_TYPE_ITEM, 931 item, 932 "mask enables non supported" 933 " bits"); 934 if (!item->spec && (item->mask || item->last)) 935 return rte_flow_error_set(error, EINVAL, 936 RTE_FLOW_ERROR_TYPE_ITEM, item, 937 "mask/last without a spec is not" 938 " supported"); 939 if (item->spec && item->last && !range_accepted) { 940 uint8_t spec[size]; 941 uint8_t last[size]; 942 unsigned int i; 943 int ret; 944 945 for (i = 0; i < size; ++i) { 946 spec[i] = ((const uint8_t *)item->spec)[i] & mask[i]; 947 last[i] = ((const uint8_t *)item->last)[i] & mask[i]; 948 } 949 ret = memcmp(spec, last, size); 950 if (ret != 0) 951 return rte_flow_error_set(error, EINVAL, 952 RTE_FLOW_ERROR_TYPE_ITEM, 953 item, 954 "range is not valid"); 955 } 956 return 0; 957 } 958 959 /** 960 * Adjust the hash fields according to the @p flow information. 961 * 962 * @param[in] dev_flow. 963 * Pointer to the mlx5_flow. 964 * @param[in] tunnel 965 * 1 when the hash field is for a tunnel item. 966 * @param[in] layer_types 967 * ETH_RSS_* types. 968 * @param[in] hash_fields 969 * Item hash fields. 970 * 971 * @return 972 * The hash fields that should be used. 973 */ 974 uint64_t 975 mlx5_flow_hashfields_adjust(struct mlx5_flow_rss_desc *rss_desc, 976 int tunnel __rte_unused, uint64_t layer_types, 977 uint64_t hash_fields) 978 { 979 #ifdef HAVE_IBV_DEVICE_TUNNEL_SUPPORT 980 int rss_request_inner = rss_desc->level >= 2; 981 982 /* Check RSS hash level for tunnel. */ 983 if (tunnel && rss_request_inner) 984 hash_fields |= IBV_RX_HASH_INNER; 985 else if (tunnel || rss_request_inner) 986 return 0; 987 #endif 988 /* Check if requested layer matches RSS hash fields. */ 989 if (!(rss_desc->types & layer_types)) 990 return 0; 991 return hash_fields; 992 } 993 994 /** 995 * Lookup and set the ptype in the data Rx part. A single Ptype can be used, 996 * if several tunnel rules are used on this queue, the tunnel ptype will be 997 * cleared. 998 * 999 * @param rxq_ctrl 1000 * Rx queue to update. 1001 */ 1002 static void 1003 flow_rxq_tunnel_ptype_update(struct mlx5_rxq_ctrl *rxq_ctrl) 1004 { 1005 unsigned int i; 1006 uint32_t tunnel_ptype = 0; 1007 1008 /* Look up for the ptype to use. */ 1009 for (i = 0; i != MLX5_FLOW_TUNNEL; ++i) { 1010 if (!rxq_ctrl->flow_tunnels_n[i]) 1011 continue; 1012 if (!tunnel_ptype) { 1013 tunnel_ptype = tunnels_info[i].ptype; 1014 } else { 1015 tunnel_ptype = 0; 1016 break; 1017 } 1018 } 1019 rxq_ctrl->rxq.tunnel = tunnel_ptype; 1020 } 1021 1022 /** 1023 * Set the Rx queue flags (Mark/Flag and Tunnel Ptypes) according to the devive 1024 * flow. 1025 * 1026 * @param[in] dev 1027 * Pointer to the Ethernet device structure. 1028 * @param[in] dev_handle 1029 * Pointer to device flow handle structure. 1030 */ 1031 static void 1032 flow_drv_rxq_flags_set(struct rte_eth_dev *dev, 1033 struct mlx5_flow_handle *dev_handle) 1034 { 1035 struct mlx5_priv *priv = dev->data->dev_private; 1036 const int mark = dev_handle->mark; 1037 const int tunnel = !!(dev_handle->layers & MLX5_FLOW_LAYER_TUNNEL); 1038 struct mlx5_ind_table_obj *ind_tbl = NULL; 1039 unsigned int i; 1040 1041 if (dev_handle->fate_action == MLX5_FLOW_FATE_QUEUE) { 1042 struct mlx5_hrxq *hrxq; 1043 1044 hrxq = mlx5_ipool_get(priv->sh->ipool[MLX5_IPOOL_HRXQ], 1045 dev_handle->rix_hrxq); 1046 if (hrxq) 1047 ind_tbl = hrxq->ind_table; 1048 } else if (dev_handle->fate_action == MLX5_FLOW_FATE_SHARED_RSS) { 1049 struct mlx5_shared_action_rss *shared_rss; 1050 1051 shared_rss = mlx5_ipool_get 1052 (priv->sh->ipool[MLX5_IPOOL_RSS_SHARED_ACTIONS], 1053 dev_handle->rix_srss); 1054 if (shared_rss) 1055 ind_tbl = shared_rss->ind_tbl; 1056 } 1057 if (!ind_tbl) 1058 return; 1059 for (i = 0; i != ind_tbl->queues_n; ++i) { 1060 int idx = ind_tbl->queues[i]; 1061 struct mlx5_rxq_ctrl *rxq_ctrl = 1062 container_of((*priv->rxqs)[idx], 1063 struct mlx5_rxq_ctrl, rxq); 1064 1065 /* 1066 * To support metadata register copy on Tx loopback, 1067 * this must be always enabled (metadata may arive 1068 * from other port - not from local flows only. 1069 */ 1070 if (priv->config.dv_flow_en && 1071 priv->config.dv_xmeta_en != MLX5_XMETA_MODE_LEGACY && 1072 mlx5_flow_ext_mreg_supported(dev)) { 1073 rxq_ctrl->rxq.mark = 1; 1074 rxq_ctrl->flow_mark_n = 1; 1075 } else if (mark) { 1076 rxq_ctrl->rxq.mark = 1; 1077 rxq_ctrl->flow_mark_n++; 1078 } 1079 if (tunnel) { 1080 unsigned int j; 1081 1082 /* Increase the counter matching the flow. */ 1083 for (j = 0; j != MLX5_FLOW_TUNNEL; ++j) { 1084 if ((tunnels_info[j].tunnel & 1085 dev_handle->layers) == 1086 tunnels_info[j].tunnel) { 1087 rxq_ctrl->flow_tunnels_n[j]++; 1088 break; 1089 } 1090 } 1091 flow_rxq_tunnel_ptype_update(rxq_ctrl); 1092 } 1093 } 1094 } 1095 1096 /** 1097 * Set the Rx queue flags (Mark/Flag and Tunnel Ptypes) for a flow 1098 * 1099 * @param[in] dev 1100 * Pointer to the Ethernet device structure. 1101 * @param[in] flow 1102 * Pointer to flow structure. 1103 */ 1104 static void 1105 flow_rxq_flags_set(struct rte_eth_dev *dev, struct rte_flow *flow) 1106 { 1107 struct mlx5_priv *priv = dev->data->dev_private; 1108 uint32_t handle_idx; 1109 struct mlx5_flow_handle *dev_handle; 1110 1111 SILIST_FOREACH(priv->sh->ipool[MLX5_IPOOL_MLX5_FLOW], flow->dev_handles, 1112 handle_idx, dev_handle, next) 1113 flow_drv_rxq_flags_set(dev, dev_handle); 1114 } 1115 1116 /** 1117 * Clear the Rx queue flags (Mark/Flag and Tunnel Ptype) associated with the 1118 * device flow if no other flow uses it with the same kind of request. 1119 * 1120 * @param dev 1121 * Pointer to Ethernet device. 1122 * @param[in] dev_handle 1123 * Pointer to the device flow handle structure. 1124 */ 1125 static void 1126 flow_drv_rxq_flags_trim(struct rte_eth_dev *dev, 1127 struct mlx5_flow_handle *dev_handle) 1128 { 1129 struct mlx5_priv *priv = dev->data->dev_private; 1130 const int mark = dev_handle->mark; 1131 const int tunnel = !!(dev_handle->layers & MLX5_FLOW_LAYER_TUNNEL); 1132 struct mlx5_ind_table_obj *ind_tbl = NULL; 1133 unsigned int i; 1134 1135 if (dev_handle->fate_action == MLX5_FLOW_FATE_QUEUE) { 1136 struct mlx5_hrxq *hrxq; 1137 1138 hrxq = mlx5_ipool_get(priv->sh->ipool[MLX5_IPOOL_HRXQ], 1139 dev_handle->rix_hrxq); 1140 if (hrxq) 1141 ind_tbl = hrxq->ind_table; 1142 } else if (dev_handle->fate_action == MLX5_FLOW_FATE_SHARED_RSS) { 1143 struct mlx5_shared_action_rss *shared_rss; 1144 1145 shared_rss = mlx5_ipool_get 1146 (priv->sh->ipool[MLX5_IPOOL_RSS_SHARED_ACTIONS], 1147 dev_handle->rix_srss); 1148 if (shared_rss) 1149 ind_tbl = shared_rss->ind_tbl; 1150 } 1151 if (!ind_tbl) 1152 return; 1153 MLX5_ASSERT(dev->data->dev_started); 1154 for (i = 0; i != ind_tbl->queues_n; ++i) { 1155 int idx = ind_tbl->queues[i]; 1156 struct mlx5_rxq_ctrl *rxq_ctrl = 1157 container_of((*priv->rxqs)[idx], 1158 struct mlx5_rxq_ctrl, rxq); 1159 1160 if (priv->config.dv_flow_en && 1161 priv->config.dv_xmeta_en != MLX5_XMETA_MODE_LEGACY && 1162 mlx5_flow_ext_mreg_supported(dev)) { 1163 rxq_ctrl->rxq.mark = 1; 1164 rxq_ctrl->flow_mark_n = 1; 1165 } else if (mark) { 1166 rxq_ctrl->flow_mark_n--; 1167 rxq_ctrl->rxq.mark = !!rxq_ctrl->flow_mark_n; 1168 } 1169 if (tunnel) { 1170 unsigned int j; 1171 1172 /* Decrease the counter matching the flow. */ 1173 for (j = 0; j != MLX5_FLOW_TUNNEL; ++j) { 1174 if ((tunnels_info[j].tunnel & 1175 dev_handle->layers) == 1176 tunnels_info[j].tunnel) { 1177 rxq_ctrl->flow_tunnels_n[j]--; 1178 break; 1179 } 1180 } 1181 flow_rxq_tunnel_ptype_update(rxq_ctrl); 1182 } 1183 } 1184 } 1185 1186 /** 1187 * Clear the Rx queue flags (Mark/Flag and Tunnel Ptype) associated with the 1188 * @p flow if no other flow uses it with the same kind of request. 1189 * 1190 * @param dev 1191 * Pointer to Ethernet device. 1192 * @param[in] flow 1193 * Pointer to the flow. 1194 */ 1195 static void 1196 flow_rxq_flags_trim(struct rte_eth_dev *dev, struct rte_flow *flow) 1197 { 1198 struct mlx5_priv *priv = dev->data->dev_private; 1199 uint32_t handle_idx; 1200 struct mlx5_flow_handle *dev_handle; 1201 1202 SILIST_FOREACH(priv->sh->ipool[MLX5_IPOOL_MLX5_FLOW], flow->dev_handles, 1203 handle_idx, dev_handle, next) 1204 flow_drv_rxq_flags_trim(dev, dev_handle); 1205 } 1206 1207 /** 1208 * Clear the Mark/Flag and Tunnel ptype information in all Rx queues. 1209 * 1210 * @param dev 1211 * Pointer to Ethernet device. 1212 */ 1213 static void 1214 flow_rxq_flags_clear(struct rte_eth_dev *dev) 1215 { 1216 struct mlx5_priv *priv = dev->data->dev_private; 1217 unsigned int i; 1218 1219 for (i = 0; i != priv->rxqs_n; ++i) { 1220 struct mlx5_rxq_ctrl *rxq_ctrl; 1221 unsigned int j; 1222 1223 if (!(*priv->rxqs)[i]) 1224 continue; 1225 rxq_ctrl = container_of((*priv->rxqs)[i], 1226 struct mlx5_rxq_ctrl, rxq); 1227 rxq_ctrl->flow_mark_n = 0; 1228 rxq_ctrl->rxq.mark = 0; 1229 for (j = 0; j != MLX5_FLOW_TUNNEL; ++j) 1230 rxq_ctrl->flow_tunnels_n[j] = 0; 1231 rxq_ctrl->rxq.tunnel = 0; 1232 } 1233 } 1234 1235 /** 1236 * Set the Rx queue dynamic metadata (mask and offset) for a flow 1237 * 1238 * @param[in] dev 1239 * Pointer to the Ethernet device structure. 1240 */ 1241 void 1242 mlx5_flow_rxq_dynf_metadata_set(struct rte_eth_dev *dev) 1243 { 1244 struct mlx5_priv *priv = dev->data->dev_private; 1245 struct mlx5_rxq_data *data; 1246 unsigned int i; 1247 1248 for (i = 0; i != priv->rxqs_n; ++i) { 1249 if (!(*priv->rxqs)[i]) 1250 continue; 1251 data = (*priv->rxqs)[i]; 1252 if (!rte_flow_dynf_metadata_avail()) { 1253 data->dynf_meta = 0; 1254 data->flow_meta_mask = 0; 1255 data->flow_meta_offset = -1; 1256 data->flow_meta_port_mask = 0; 1257 } else { 1258 data->dynf_meta = 1; 1259 data->flow_meta_mask = rte_flow_dynf_metadata_mask; 1260 data->flow_meta_offset = rte_flow_dynf_metadata_offs; 1261 data->flow_meta_port_mask = (uint32_t)~0; 1262 if (priv->config.dv_xmeta_en == MLX5_XMETA_MODE_META16) 1263 data->flow_meta_port_mask >>= 16; 1264 } 1265 } 1266 } 1267 1268 /* 1269 * return a pointer to the desired action in the list of actions. 1270 * 1271 * @param[in] actions 1272 * The list of actions to search the action in. 1273 * @param[in] action 1274 * The action to find. 1275 * 1276 * @return 1277 * Pointer to the action in the list, if found. NULL otherwise. 1278 */ 1279 const struct rte_flow_action * 1280 mlx5_flow_find_action(const struct rte_flow_action *actions, 1281 enum rte_flow_action_type action) 1282 { 1283 if (actions == NULL) 1284 return NULL; 1285 for (; actions->type != RTE_FLOW_ACTION_TYPE_END; actions++) 1286 if (actions->type == action) 1287 return actions; 1288 return NULL; 1289 } 1290 1291 /* 1292 * Validate the flag action. 1293 * 1294 * @param[in] action_flags 1295 * Bit-fields that holds the actions detected until now. 1296 * @param[in] attr 1297 * Attributes of flow that includes this action. 1298 * @param[out] error 1299 * Pointer to error structure. 1300 * 1301 * @return 1302 * 0 on success, a negative errno value otherwise and rte_errno is set. 1303 */ 1304 int 1305 mlx5_flow_validate_action_flag(uint64_t action_flags, 1306 const struct rte_flow_attr *attr, 1307 struct rte_flow_error *error) 1308 { 1309 if (action_flags & MLX5_FLOW_ACTION_MARK) 1310 return rte_flow_error_set(error, EINVAL, 1311 RTE_FLOW_ERROR_TYPE_ACTION, NULL, 1312 "can't mark and flag in same flow"); 1313 if (action_flags & MLX5_FLOW_ACTION_FLAG) 1314 return rte_flow_error_set(error, EINVAL, 1315 RTE_FLOW_ERROR_TYPE_ACTION, NULL, 1316 "can't have 2 flag" 1317 " actions in same flow"); 1318 if (attr->egress) 1319 return rte_flow_error_set(error, ENOTSUP, 1320 RTE_FLOW_ERROR_TYPE_ATTR_EGRESS, NULL, 1321 "flag action not supported for " 1322 "egress"); 1323 return 0; 1324 } 1325 1326 /* 1327 * Validate the mark action. 1328 * 1329 * @param[in] action 1330 * Pointer to the queue action. 1331 * @param[in] action_flags 1332 * Bit-fields that holds the actions detected until now. 1333 * @param[in] attr 1334 * Attributes of flow that includes this action. 1335 * @param[out] error 1336 * Pointer to error structure. 1337 * 1338 * @return 1339 * 0 on success, a negative errno value otherwise and rte_errno is set. 1340 */ 1341 int 1342 mlx5_flow_validate_action_mark(const struct rte_flow_action *action, 1343 uint64_t action_flags, 1344 const struct rte_flow_attr *attr, 1345 struct rte_flow_error *error) 1346 { 1347 const struct rte_flow_action_mark *mark = action->conf; 1348 1349 if (!mark) 1350 return rte_flow_error_set(error, EINVAL, 1351 RTE_FLOW_ERROR_TYPE_ACTION, 1352 action, 1353 "configuration cannot be null"); 1354 if (mark->id >= MLX5_FLOW_MARK_MAX) 1355 return rte_flow_error_set(error, EINVAL, 1356 RTE_FLOW_ERROR_TYPE_ACTION_CONF, 1357 &mark->id, 1358 "mark id must in 0 <= id < " 1359 RTE_STR(MLX5_FLOW_MARK_MAX)); 1360 if (action_flags & MLX5_FLOW_ACTION_FLAG) 1361 return rte_flow_error_set(error, EINVAL, 1362 RTE_FLOW_ERROR_TYPE_ACTION, NULL, 1363 "can't flag and mark in same flow"); 1364 if (action_flags & MLX5_FLOW_ACTION_MARK) 1365 return rte_flow_error_set(error, EINVAL, 1366 RTE_FLOW_ERROR_TYPE_ACTION, NULL, 1367 "can't have 2 mark actions in same" 1368 " flow"); 1369 if (attr->egress) 1370 return rte_flow_error_set(error, ENOTSUP, 1371 RTE_FLOW_ERROR_TYPE_ATTR_EGRESS, NULL, 1372 "mark action not supported for " 1373 "egress"); 1374 return 0; 1375 } 1376 1377 /* 1378 * Validate the drop action. 1379 * 1380 * @param[in] action_flags 1381 * Bit-fields that holds the actions detected until now. 1382 * @param[in] attr 1383 * Attributes of flow that includes this action. 1384 * @param[out] error 1385 * Pointer to error structure. 1386 * 1387 * @return 1388 * 0 on success, a negative errno value otherwise and rte_errno is set. 1389 */ 1390 int 1391 mlx5_flow_validate_action_drop(uint64_t action_flags __rte_unused, 1392 const struct rte_flow_attr *attr, 1393 struct rte_flow_error *error) 1394 { 1395 if (attr->egress) 1396 return rte_flow_error_set(error, ENOTSUP, 1397 RTE_FLOW_ERROR_TYPE_ATTR_EGRESS, NULL, 1398 "drop action not supported for " 1399 "egress"); 1400 return 0; 1401 } 1402 1403 /* 1404 * Validate the queue action. 1405 * 1406 * @param[in] action 1407 * Pointer to the queue action. 1408 * @param[in] action_flags 1409 * Bit-fields that holds the actions detected until now. 1410 * @param[in] dev 1411 * Pointer to the Ethernet device structure. 1412 * @param[in] attr 1413 * Attributes of flow that includes this action. 1414 * @param[out] error 1415 * Pointer to error structure. 1416 * 1417 * @return 1418 * 0 on success, a negative errno value otherwise and rte_errno is set. 1419 */ 1420 int 1421 mlx5_flow_validate_action_queue(const struct rte_flow_action *action, 1422 uint64_t action_flags, 1423 struct rte_eth_dev *dev, 1424 const struct rte_flow_attr *attr, 1425 struct rte_flow_error *error) 1426 { 1427 struct mlx5_priv *priv = dev->data->dev_private; 1428 const struct rte_flow_action_queue *queue = action->conf; 1429 1430 if (action_flags & MLX5_FLOW_FATE_ACTIONS) 1431 return rte_flow_error_set(error, EINVAL, 1432 RTE_FLOW_ERROR_TYPE_ACTION, NULL, 1433 "can't have 2 fate actions in" 1434 " same flow"); 1435 if (!priv->rxqs_n) 1436 return rte_flow_error_set(error, EINVAL, 1437 RTE_FLOW_ERROR_TYPE_ACTION_CONF, 1438 NULL, "No Rx queues configured"); 1439 if (queue->index >= priv->rxqs_n) 1440 return rte_flow_error_set(error, EINVAL, 1441 RTE_FLOW_ERROR_TYPE_ACTION_CONF, 1442 &queue->index, 1443 "queue index out of range"); 1444 if (!(*priv->rxqs)[queue->index]) 1445 return rte_flow_error_set(error, EINVAL, 1446 RTE_FLOW_ERROR_TYPE_ACTION_CONF, 1447 &queue->index, 1448 "queue is not configured"); 1449 if (attr->egress) 1450 return rte_flow_error_set(error, ENOTSUP, 1451 RTE_FLOW_ERROR_TYPE_ATTR_EGRESS, NULL, 1452 "queue action not supported for " 1453 "egress"); 1454 return 0; 1455 } 1456 1457 /* 1458 * Validate the rss action. 1459 * 1460 * @param[in] dev 1461 * Pointer to the Ethernet device structure. 1462 * @param[in] action 1463 * Pointer to the queue action. 1464 * @param[out] error 1465 * Pointer to error structure. 1466 * 1467 * @return 1468 * 0 on success, a negative errno value otherwise and rte_errno is set. 1469 */ 1470 int 1471 mlx5_validate_action_rss(struct rte_eth_dev *dev, 1472 const struct rte_flow_action *action, 1473 struct rte_flow_error *error) 1474 { 1475 struct mlx5_priv *priv = dev->data->dev_private; 1476 const struct rte_flow_action_rss *rss = action->conf; 1477 enum mlx5_rxq_type rxq_type = MLX5_RXQ_TYPE_UNDEFINED; 1478 unsigned int i; 1479 1480 if (rss->func != RTE_ETH_HASH_FUNCTION_DEFAULT && 1481 rss->func != RTE_ETH_HASH_FUNCTION_TOEPLITZ) 1482 return rte_flow_error_set(error, ENOTSUP, 1483 RTE_FLOW_ERROR_TYPE_ACTION_CONF, 1484 &rss->func, 1485 "RSS hash function not supported"); 1486 #ifdef HAVE_IBV_DEVICE_TUNNEL_SUPPORT 1487 if (rss->level > 2) 1488 #else 1489 if (rss->level > 1) 1490 #endif 1491 return rte_flow_error_set(error, ENOTSUP, 1492 RTE_FLOW_ERROR_TYPE_ACTION_CONF, 1493 &rss->level, 1494 "tunnel RSS is not supported"); 1495 /* allow RSS key_len 0 in case of NULL (default) RSS key. */ 1496 if (rss->key_len == 0 && rss->key != NULL) 1497 return rte_flow_error_set(error, ENOTSUP, 1498 RTE_FLOW_ERROR_TYPE_ACTION_CONF, 1499 &rss->key_len, 1500 "RSS hash key length 0"); 1501 if (rss->key_len > 0 && rss->key_len < MLX5_RSS_HASH_KEY_LEN) 1502 return rte_flow_error_set(error, ENOTSUP, 1503 RTE_FLOW_ERROR_TYPE_ACTION_CONF, 1504 &rss->key_len, 1505 "RSS hash key too small"); 1506 if (rss->key_len > MLX5_RSS_HASH_KEY_LEN) 1507 return rte_flow_error_set(error, ENOTSUP, 1508 RTE_FLOW_ERROR_TYPE_ACTION_CONF, 1509 &rss->key_len, 1510 "RSS hash key too large"); 1511 if (rss->queue_num > priv->config.ind_table_max_size) 1512 return rte_flow_error_set(error, ENOTSUP, 1513 RTE_FLOW_ERROR_TYPE_ACTION_CONF, 1514 &rss->queue_num, 1515 "number of queues too large"); 1516 if (rss->types & MLX5_RSS_HF_MASK) 1517 return rte_flow_error_set(error, ENOTSUP, 1518 RTE_FLOW_ERROR_TYPE_ACTION_CONF, 1519 &rss->types, 1520 "some RSS protocols are not" 1521 " supported"); 1522 if ((rss->types & (ETH_RSS_L3_SRC_ONLY | ETH_RSS_L3_DST_ONLY)) && 1523 !(rss->types & ETH_RSS_IP)) 1524 return rte_flow_error_set(error, EINVAL, 1525 RTE_FLOW_ERROR_TYPE_ACTION_CONF, NULL, 1526 "L3 partial RSS requested but L3 RSS" 1527 " type not specified"); 1528 if ((rss->types & (ETH_RSS_L4_SRC_ONLY | ETH_RSS_L4_DST_ONLY)) && 1529 !(rss->types & (ETH_RSS_UDP | ETH_RSS_TCP))) 1530 return rte_flow_error_set(error, EINVAL, 1531 RTE_FLOW_ERROR_TYPE_ACTION_CONF, NULL, 1532 "L4 partial RSS requested but L4 RSS" 1533 " type not specified"); 1534 if (!priv->rxqs_n) 1535 return rte_flow_error_set(error, EINVAL, 1536 RTE_FLOW_ERROR_TYPE_ACTION_CONF, 1537 NULL, "No Rx queues configured"); 1538 if (!rss->queue_num) 1539 return rte_flow_error_set(error, EINVAL, 1540 RTE_FLOW_ERROR_TYPE_ACTION_CONF, 1541 NULL, "No queues configured"); 1542 for (i = 0; i != rss->queue_num; ++i) { 1543 struct mlx5_rxq_ctrl *rxq_ctrl; 1544 1545 if (rss->queue[i] >= priv->rxqs_n) 1546 return rte_flow_error_set 1547 (error, EINVAL, 1548 RTE_FLOW_ERROR_TYPE_ACTION_CONF, 1549 &rss->queue[i], "queue index out of range"); 1550 if (!(*priv->rxqs)[rss->queue[i]]) 1551 return rte_flow_error_set 1552 (error, EINVAL, RTE_FLOW_ERROR_TYPE_ACTION_CONF, 1553 &rss->queue[i], "queue is not configured"); 1554 rxq_ctrl = container_of((*priv->rxqs)[rss->queue[i]], 1555 struct mlx5_rxq_ctrl, rxq); 1556 if (i == 0) 1557 rxq_type = rxq_ctrl->type; 1558 if (rxq_type != rxq_ctrl->type) 1559 return rte_flow_error_set 1560 (error, ENOTSUP, RTE_FLOW_ERROR_TYPE_ACTION_CONF, 1561 &rss->queue[i], 1562 "combining hairpin and regular RSS queues is not supported"); 1563 } 1564 return 0; 1565 } 1566 1567 /* 1568 * Validate the rss action. 1569 * 1570 * @param[in] action 1571 * Pointer to the queue action. 1572 * @param[in] action_flags 1573 * Bit-fields that holds the actions detected until now. 1574 * @param[in] dev 1575 * Pointer to the Ethernet device structure. 1576 * @param[in] attr 1577 * Attributes of flow that includes this action. 1578 * @param[in] item_flags 1579 * Items that were detected. 1580 * @param[out] error 1581 * Pointer to error structure. 1582 * 1583 * @return 1584 * 0 on success, a negative errno value otherwise and rte_errno is set. 1585 */ 1586 int 1587 mlx5_flow_validate_action_rss(const struct rte_flow_action *action, 1588 uint64_t action_flags, 1589 struct rte_eth_dev *dev, 1590 const struct rte_flow_attr *attr, 1591 uint64_t item_flags, 1592 struct rte_flow_error *error) 1593 { 1594 const struct rte_flow_action_rss *rss = action->conf; 1595 int tunnel = !!(item_flags & MLX5_FLOW_LAYER_TUNNEL); 1596 int ret; 1597 1598 if (action_flags & MLX5_FLOW_FATE_ACTIONS) 1599 return rte_flow_error_set(error, EINVAL, 1600 RTE_FLOW_ERROR_TYPE_ACTION, NULL, 1601 "can't have 2 fate actions" 1602 " in same flow"); 1603 ret = mlx5_validate_action_rss(dev, action, error); 1604 if (ret) 1605 return ret; 1606 if (attr->egress) 1607 return rte_flow_error_set(error, ENOTSUP, 1608 RTE_FLOW_ERROR_TYPE_ATTR_EGRESS, NULL, 1609 "rss action not supported for " 1610 "egress"); 1611 if (rss->level > 1 && !tunnel) 1612 return rte_flow_error_set(error, EINVAL, 1613 RTE_FLOW_ERROR_TYPE_ACTION_CONF, NULL, 1614 "inner RSS is not supported for " 1615 "non-tunnel flows"); 1616 if ((item_flags & MLX5_FLOW_LAYER_ECPRI) && 1617 !(item_flags & MLX5_FLOW_LAYER_INNER_L4_UDP)) { 1618 return rte_flow_error_set(error, EINVAL, 1619 RTE_FLOW_ERROR_TYPE_ACTION_CONF, NULL, 1620 "RSS on eCPRI is not supported now"); 1621 } 1622 return 0; 1623 } 1624 1625 /* 1626 * Validate the default miss action. 1627 * 1628 * @param[in] action_flags 1629 * Bit-fields that holds the actions detected until now. 1630 * @param[out] error 1631 * Pointer to error structure. 1632 * 1633 * @return 1634 * 0 on success, a negative errno value otherwise and rte_errno is set. 1635 */ 1636 int 1637 mlx5_flow_validate_action_default_miss(uint64_t action_flags, 1638 const struct rte_flow_attr *attr, 1639 struct rte_flow_error *error) 1640 { 1641 if (action_flags & MLX5_FLOW_FATE_ACTIONS) 1642 return rte_flow_error_set(error, EINVAL, 1643 RTE_FLOW_ERROR_TYPE_ACTION, NULL, 1644 "can't have 2 fate actions in" 1645 " same flow"); 1646 if (attr->egress) 1647 return rte_flow_error_set(error, ENOTSUP, 1648 RTE_FLOW_ERROR_TYPE_ATTR_EGRESS, NULL, 1649 "default miss action not supported " 1650 "for egress"); 1651 if (attr->group) 1652 return rte_flow_error_set(error, ENOTSUP, 1653 RTE_FLOW_ERROR_TYPE_ATTR_GROUP, NULL, 1654 "only group 0 is supported"); 1655 if (attr->transfer) 1656 return rte_flow_error_set(error, ENOTSUP, 1657 RTE_FLOW_ERROR_TYPE_ATTR_TRANSFER, 1658 NULL, "transfer is not supported"); 1659 return 0; 1660 } 1661 1662 /* 1663 * Validate the count action. 1664 * 1665 * @param[in] dev 1666 * Pointer to the Ethernet device structure. 1667 * @param[in] attr 1668 * Attributes of flow that includes this action. 1669 * @param[out] error 1670 * Pointer to error structure. 1671 * 1672 * @return 1673 * 0 on success, a negative errno value otherwise and rte_errno is set. 1674 */ 1675 int 1676 mlx5_flow_validate_action_count(struct rte_eth_dev *dev __rte_unused, 1677 const struct rte_flow_attr *attr, 1678 struct rte_flow_error *error) 1679 { 1680 if (attr->egress) 1681 return rte_flow_error_set(error, ENOTSUP, 1682 RTE_FLOW_ERROR_TYPE_ATTR_EGRESS, NULL, 1683 "count action not supported for " 1684 "egress"); 1685 return 0; 1686 } 1687 1688 /** 1689 * Verify the @p attributes will be correctly understood by the NIC and store 1690 * them in the @p flow if everything is correct. 1691 * 1692 * @param[in] dev 1693 * Pointer to the Ethernet device structure. 1694 * @param[in] attributes 1695 * Pointer to flow attributes 1696 * @param[out] error 1697 * Pointer to error structure. 1698 * 1699 * @return 1700 * 0 on success, a negative errno value otherwise and rte_errno is set. 1701 */ 1702 int 1703 mlx5_flow_validate_attributes(struct rte_eth_dev *dev, 1704 const struct rte_flow_attr *attributes, 1705 struct rte_flow_error *error) 1706 { 1707 struct mlx5_priv *priv = dev->data->dev_private; 1708 uint32_t priority_max = priv->config.flow_prio - 1; 1709 1710 if (attributes->group) 1711 return rte_flow_error_set(error, ENOTSUP, 1712 RTE_FLOW_ERROR_TYPE_ATTR_GROUP, 1713 NULL, "groups is not supported"); 1714 if (attributes->priority != MLX5_FLOW_LOWEST_PRIO_INDICATOR && 1715 attributes->priority >= priority_max) 1716 return rte_flow_error_set(error, ENOTSUP, 1717 RTE_FLOW_ERROR_TYPE_ATTR_PRIORITY, 1718 NULL, "priority out of range"); 1719 if (attributes->egress) 1720 return rte_flow_error_set(error, ENOTSUP, 1721 RTE_FLOW_ERROR_TYPE_ATTR_EGRESS, NULL, 1722 "egress is not supported"); 1723 if (attributes->transfer && !priv->config.dv_esw_en) 1724 return rte_flow_error_set(error, ENOTSUP, 1725 RTE_FLOW_ERROR_TYPE_ATTR_TRANSFER, 1726 NULL, "transfer is not supported"); 1727 if (!attributes->ingress) 1728 return rte_flow_error_set(error, EINVAL, 1729 RTE_FLOW_ERROR_TYPE_ATTR_INGRESS, 1730 NULL, 1731 "ingress attribute is mandatory"); 1732 return 0; 1733 } 1734 1735 /** 1736 * Validate ICMP6 item. 1737 * 1738 * @param[in] item 1739 * Item specification. 1740 * @param[in] item_flags 1741 * Bit-fields that holds the items detected until now. 1742 * @param[in] ext_vlan_sup 1743 * Whether extended VLAN features are supported or not. 1744 * @param[out] error 1745 * Pointer to error structure. 1746 * 1747 * @return 1748 * 0 on success, a negative errno value otherwise and rte_errno is set. 1749 */ 1750 int 1751 mlx5_flow_validate_item_icmp6(const struct rte_flow_item *item, 1752 uint64_t item_flags, 1753 uint8_t target_protocol, 1754 struct rte_flow_error *error) 1755 { 1756 const struct rte_flow_item_icmp6 *mask = item->mask; 1757 const int tunnel = !!(item_flags & MLX5_FLOW_LAYER_TUNNEL); 1758 const uint64_t l3m = tunnel ? MLX5_FLOW_LAYER_INNER_L3_IPV6 : 1759 MLX5_FLOW_LAYER_OUTER_L3_IPV6; 1760 const uint64_t l4m = tunnel ? MLX5_FLOW_LAYER_INNER_L4 : 1761 MLX5_FLOW_LAYER_OUTER_L4; 1762 int ret; 1763 1764 if (target_protocol != 0xFF && target_protocol != IPPROTO_ICMPV6) 1765 return rte_flow_error_set(error, EINVAL, 1766 RTE_FLOW_ERROR_TYPE_ITEM, item, 1767 "protocol filtering not compatible" 1768 " with ICMP6 layer"); 1769 if (!(item_flags & l3m)) 1770 return rte_flow_error_set(error, EINVAL, 1771 RTE_FLOW_ERROR_TYPE_ITEM, item, 1772 "IPv6 is mandatory to filter on" 1773 " ICMP6"); 1774 if (item_flags & l4m) 1775 return rte_flow_error_set(error, EINVAL, 1776 RTE_FLOW_ERROR_TYPE_ITEM, item, 1777 "multiple L4 layers not supported"); 1778 if (!mask) 1779 mask = &rte_flow_item_icmp6_mask; 1780 ret = mlx5_flow_item_acceptable 1781 (item, (const uint8_t *)mask, 1782 (const uint8_t *)&rte_flow_item_icmp6_mask, 1783 sizeof(struct rte_flow_item_icmp6), 1784 MLX5_ITEM_RANGE_NOT_ACCEPTED, error); 1785 if (ret < 0) 1786 return ret; 1787 return 0; 1788 } 1789 1790 /** 1791 * Validate ICMP item. 1792 * 1793 * @param[in] item 1794 * Item specification. 1795 * @param[in] item_flags 1796 * Bit-fields that holds the items detected until now. 1797 * @param[out] error 1798 * Pointer to error structure. 1799 * 1800 * @return 1801 * 0 on success, a negative errno value otherwise and rte_errno is set. 1802 */ 1803 int 1804 mlx5_flow_validate_item_icmp(const struct rte_flow_item *item, 1805 uint64_t item_flags, 1806 uint8_t target_protocol, 1807 struct rte_flow_error *error) 1808 { 1809 const struct rte_flow_item_icmp *mask = item->mask; 1810 const struct rte_flow_item_icmp nic_mask = { 1811 .hdr.icmp_type = 0xff, 1812 .hdr.icmp_code = 0xff, 1813 .hdr.icmp_ident = RTE_BE16(0xffff), 1814 .hdr.icmp_seq_nb = RTE_BE16(0xffff), 1815 }; 1816 const int tunnel = !!(item_flags & MLX5_FLOW_LAYER_TUNNEL); 1817 const uint64_t l3m = tunnel ? MLX5_FLOW_LAYER_INNER_L3_IPV4 : 1818 MLX5_FLOW_LAYER_OUTER_L3_IPV4; 1819 const uint64_t l4m = tunnel ? MLX5_FLOW_LAYER_INNER_L4 : 1820 MLX5_FLOW_LAYER_OUTER_L4; 1821 int ret; 1822 1823 if (target_protocol != 0xFF && target_protocol != IPPROTO_ICMP) 1824 return rte_flow_error_set(error, EINVAL, 1825 RTE_FLOW_ERROR_TYPE_ITEM, item, 1826 "protocol filtering not compatible" 1827 " with ICMP layer"); 1828 if (!(item_flags & l3m)) 1829 return rte_flow_error_set(error, EINVAL, 1830 RTE_FLOW_ERROR_TYPE_ITEM, item, 1831 "IPv4 is mandatory to filter" 1832 " on ICMP"); 1833 if (item_flags & l4m) 1834 return rte_flow_error_set(error, EINVAL, 1835 RTE_FLOW_ERROR_TYPE_ITEM, item, 1836 "multiple L4 layers not supported"); 1837 if (!mask) 1838 mask = &nic_mask; 1839 ret = mlx5_flow_item_acceptable 1840 (item, (const uint8_t *)mask, 1841 (const uint8_t *)&nic_mask, 1842 sizeof(struct rte_flow_item_icmp), 1843 MLX5_ITEM_RANGE_NOT_ACCEPTED, error); 1844 if (ret < 0) 1845 return ret; 1846 return 0; 1847 } 1848 1849 /** 1850 * Validate Ethernet item. 1851 * 1852 * @param[in] item 1853 * Item specification. 1854 * @param[in] item_flags 1855 * Bit-fields that holds the items detected until now. 1856 * @param[out] error 1857 * Pointer to error structure. 1858 * 1859 * @return 1860 * 0 on success, a negative errno value otherwise and rte_errno is set. 1861 */ 1862 int 1863 mlx5_flow_validate_item_eth(const struct rte_flow_item *item, 1864 uint64_t item_flags, bool ext_vlan_sup, 1865 struct rte_flow_error *error) 1866 { 1867 const struct rte_flow_item_eth *mask = item->mask; 1868 const struct rte_flow_item_eth nic_mask = { 1869 .dst.addr_bytes = "\xff\xff\xff\xff\xff\xff", 1870 .src.addr_bytes = "\xff\xff\xff\xff\xff\xff", 1871 .type = RTE_BE16(0xffff), 1872 .has_vlan = ext_vlan_sup ? 1 : 0, 1873 }; 1874 int ret; 1875 int tunnel = !!(item_flags & MLX5_FLOW_LAYER_TUNNEL); 1876 const uint64_t ethm = tunnel ? MLX5_FLOW_LAYER_INNER_L2 : 1877 MLX5_FLOW_LAYER_OUTER_L2; 1878 1879 if (item_flags & ethm) 1880 return rte_flow_error_set(error, ENOTSUP, 1881 RTE_FLOW_ERROR_TYPE_ITEM, item, 1882 "multiple L2 layers not supported"); 1883 if ((!tunnel && (item_flags & MLX5_FLOW_LAYER_OUTER_L3)) || 1884 (tunnel && (item_flags & MLX5_FLOW_LAYER_INNER_L3))) 1885 return rte_flow_error_set(error, EINVAL, 1886 RTE_FLOW_ERROR_TYPE_ITEM, item, 1887 "L2 layer should not follow " 1888 "L3 layers"); 1889 if ((!tunnel && (item_flags & MLX5_FLOW_LAYER_OUTER_VLAN)) || 1890 (tunnel && (item_flags & MLX5_FLOW_LAYER_INNER_VLAN))) 1891 return rte_flow_error_set(error, EINVAL, 1892 RTE_FLOW_ERROR_TYPE_ITEM, item, 1893 "L2 layer should not follow VLAN"); 1894 if (!mask) 1895 mask = &rte_flow_item_eth_mask; 1896 ret = mlx5_flow_item_acceptable(item, (const uint8_t *)mask, 1897 (const uint8_t *)&nic_mask, 1898 sizeof(struct rte_flow_item_eth), 1899 MLX5_ITEM_RANGE_NOT_ACCEPTED, error); 1900 return ret; 1901 } 1902 1903 /** 1904 * Validate VLAN item. 1905 * 1906 * @param[in] item 1907 * Item specification. 1908 * @param[in] item_flags 1909 * Bit-fields that holds the items detected until now. 1910 * @param[in] dev 1911 * Ethernet device flow is being created on. 1912 * @param[out] error 1913 * Pointer to error structure. 1914 * 1915 * @return 1916 * 0 on success, a negative errno value otherwise and rte_errno is set. 1917 */ 1918 int 1919 mlx5_flow_validate_item_vlan(const struct rte_flow_item *item, 1920 uint64_t item_flags, 1921 struct rte_eth_dev *dev, 1922 struct rte_flow_error *error) 1923 { 1924 const struct rte_flow_item_vlan *spec = item->spec; 1925 const struct rte_flow_item_vlan *mask = item->mask; 1926 const struct rte_flow_item_vlan nic_mask = { 1927 .tci = RTE_BE16(UINT16_MAX), 1928 .inner_type = RTE_BE16(UINT16_MAX), 1929 }; 1930 uint16_t vlan_tag = 0; 1931 const int tunnel = !!(item_flags & MLX5_FLOW_LAYER_TUNNEL); 1932 int ret; 1933 const uint64_t l34m = tunnel ? (MLX5_FLOW_LAYER_INNER_L3 | 1934 MLX5_FLOW_LAYER_INNER_L4) : 1935 (MLX5_FLOW_LAYER_OUTER_L3 | 1936 MLX5_FLOW_LAYER_OUTER_L4); 1937 const uint64_t vlanm = tunnel ? MLX5_FLOW_LAYER_INNER_VLAN : 1938 MLX5_FLOW_LAYER_OUTER_VLAN; 1939 1940 if (item_flags & vlanm) 1941 return rte_flow_error_set(error, EINVAL, 1942 RTE_FLOW_ERROR_TYPE_ITEM, item, 1943 "multiple VLAN layers not supported"); 1944 else if ((item_flags & l34m) != 0) 1945 return rte_flow_error_set(error, EINVAL, 1946 RTE_FLOW_ERROR_TYPE_ITEM, item, 1947 "VLAN cannot follow L3/L4 layer"); 1948 if (!mask) 1949 mask = &rte_flow_item_vlan_mask; 1950 ret = mlx5_flow_item_acceptable(item, (const uint8_t *)mask, 1951 (const uint8_t *)&nic_mask, 1952 sizeof(struct rte_flow_item_vlan), 1953 MLX5_ITEM_RANGE_NOT_ACCEPTED, error); 1954 if (ret) 1955 return ret; 1956 if (!tunnel && mask->tci != RTE_BE16(0x0fff)) { 1957 struct mlx5_priv *priv = dev->data->dev_private; 1958 1959 if (priv->vmwa_context) { 1960 /* 1961 * Non-NULL context means we have a virtual machine 1962 * and SR-IOV enabled, we have to create VLAN interface 1963 * to make hypervisor to setup E-Switch vport 1964 * context correctly. We avoid creating the multiple 1965 * VLAN interfaces, so we cannot support VLAN tag mask. 1966 */ 1967 return rte_flow_error_set(error, EINVAL, 1968 RTE_FLOW_ERROR_TYPE_ITEM, 1969 item, 1970 "VLAN tag mask is not" 1971 " supported in virtual" 1972 " environment"); 1973 } 1974 } 1975 if (spec) { 1976 vlan_tag = spec->tci; 1977 vlan_tag &= mask->tci; 1978 } 1979 /* 1980 * From verbs perspective an empty VLAN is equivalent 1981 * to a packet without VLAN layer. 1982 */ 1983 if (!vlan_tag) 1984 return rte_flow_error_set(error, EINVAL, 1985 RTE_FLOW_ERROR_TYPE_ITEM_SPEC, 1986 item->spec, 1987 "VLAN cannot be empty"); 1988 return 0; 1989 } 1990 1991 /** 1992 * Validate IPV4 item. 1993 * 1994 * @param[in] item 1995 * Item specification. 1996 * @param[in] item_flags 1997 * Bit-fields that holds the items detected until now. 1998 * @param[in] last_item 1999 * Previous validated item in the pattern items. 2000 * @param[in] ether_type 2001 * Type in the ethernet layer header (including dot1q). 2002 * @param[in] acc_mask 2003 * Acceptable mask, if NULL default internal default mask 2004 * will be used to check whether item fields are supported. 2005 * @param[in] range_accepted 2006 * True if range of values is accepted for specific fields, false otherwise. 2007 * @param[out] error 2008 * Pointer to error structure. 2009 * 2010 * @return 2011 * 0 on success, a negative errno value otherwise and rte_errno is set. 2012 */ 2013 int 2014 mlx5_flow_validate_item_ipv4(const struct rte_flow_item *item, 2015 uint64_t item_flags, 2016 uint64_t last_item, 2017 uint16_t ether_type, 2018 const struct rte_flow_item_ipv4 *acc_mask, 2019 bool range_accepted, 2020 struct rte_flow_error *error) 2021 { 2022 const struct rte_flow_item_ipv4 *mask = item->mask; 2023 const struct rte_flow_item_ipv4 *spec = item->spec; 2024 const struct rte_flow_item_ipv4 nic_mask = { 2025 .hdr = { 2026 .src_addr = RTE_BE32(0xffffffff), 2027 .dst_addr = RTE_BE32(0xffffffff), 2028 .type_of_service = 0xff, 2029 .next_proto_id = 0xff, 2030 }, 2031 }; 2032 const int tunnel = !!(item_flags & MLX5_FLOW_LAYER_TUNNEL); 2033 const uint64_t l3m = tunnel ? MLX5_FLOW_LAYER_INNER_L3 : 2034 MLX5_FLOW_LAYER_OUTER_L3; 2035 const uint64_t l4m = tunnel ? MLX5_FLOW_LAYER_INNER_L4 : 2036 MLX5_FLOW_LAYER_OUTER_L4; 2037 int ret; 2038 uint8_t next_proto = 0xFF; 2039 const uint64_t l2_vlan = (MLX5_FLOW_LAYER_L2 | 2040 MLX5_FLOW_LAYER_OUTER_VLAN | 2041 MLX5_FLOW_LAYER_INNER_VLAN); 2042 2043 if ((last_item & l2_vlan) && ether_type && 2044 ether_type != RTE_ETHER_TYPE_IPV4) 2045 return rte_flow_error_set(error, EINVAL, 2046 RTE_FLOW_ERROR_TYPE_ITEM, item, 2047 "IPv4 cannot follow L2/VLAN layer " 2048 "which ether type is not IPv4"); 2049 if (item_flags & MLX5_FLOW_LAYER_IPIP) { 2050 if (mask && spec) 2051 next_proto = mask->hdr.next_proto_id & 2052 spec->hdr.next_proto_id; 2053 if (next_proto == IPPROTO_IPIP || next_proto == IPPROTO_IPV6) 2054 return rte_flow_error_set(error, EINVAL, 2055 RTE_FLOW_ERROR_TYPE_ITEM, 2056 item, 2057 "multiple tunnel " 2058 "not supported"); 2059 } 2060 if (item_flags & MLX5_FLOW_LAYER_IPV6_ENCAP) 2061 return rte_flow_error_set(error, EINVAL, 2062 RTE_FLOW_ERROR_TYPE_ITEM, item, 2063 "wrong tunnel type - IPv6 specified " 2064 "but IPv4 item provided"); 2065 if (item_flags & l3m) 2066 return rte_flow_error_set(error, ENOTSUP, 2067 RTE_FLOW_ERROR_TYPE_ITEM, item, 2068 "multiple L3 layers not supported"); 2069 else if (item_flags & l4m) 2070 return rte_flow_error_set(error, EINVAL, 2071 RTE_FLOW_ERROR_TYPE_ITEM, item, 2072 "L3 cannot follow an L4 layer."); 2073 else if ((item_flags & MLX5_FLOW_LAYER_NVGRE) && 2074 !(item_flags & MLX5_FLOW_LAYER_INNER_L2)) 2075 return rte_flow_error_set(error, EINVAL, 2076 RTE_FLOW_ERROR_TYPE_ITEM, item, 2077 "L3 cannot follow an NVGRE layer."); 2078 if (!mask) 2079 mask = &rte_flow_item_ipv4_mask; 2080 else if (mask->hdr.next_proto_id != 0 && 2081 mask->hdr.next_proto_id != 0xff) 2082 return rte_flow_error_set(error, EINVAL, 2083 RTE_FLOW_ERROR_TYPE_ITEM_MASK, mask, 2084 "partial mask is not supported" 2085 " for protocol"); 2086 ret = mlx5_flow_item_acceptable(item, (const uint8_t *)mask, 2087 acc_mask ? (const uint8_t *)acc_mask 2088 : (const uint8_t *)&nic_mask, 2089 sizeof(struct rte_flow_item_ipv4), 2090 range_accepted, error); 2091 if (ret < 0) 2092 return ret; 2093 return 0; 2094 } 2095 2096 /** 2097 * Validate IPV6 item. 2098 * 2099 * @param[in] item 2100 * Item specification. 2101 * @param[in] item_flags 2102 * Bit-fields that holds the items detected until now. 2103 * @param[in] last_item 2104 * Previous validated item in the pattern items. 2105 * @param[in] ether_type 2106 * Type in the ethernet layer header (including dot1q). 2107 * @param[in] acc_mask 2108 * Acceptable mask, if NULL default internal default mask 2109 * will be used to check whether item fields are supported. 2110 * @param[out] error 2111 * Pointer to error structure. 2112 * 2113 * @return 2114 * 0 on success, a negative errno value otherwise and rte_errno is set. 2115 */ 2116 int 2117 mlx5_flow_validate_item_ipv6(const struct rte_flow_item *item, 2118 uint64_t item_flags, 2119 uint64_t last_item, 2120 uint16_t ether_type, 2121 const struct rte_flow_item_ipv6 *acc_mask, 2122 struct rte_flow_error *error) 2123 { 2124 const struct rte_flow_item_ipv6 *mask = item->mask; 2125 const struct rte_flow_item_ipv6 *spec = item->spec; 2126 const struct rte_flow_item_ipv6 nic_mask = { 2127 .hdr = { 2128 .src_addr = 2129 "\xff\xff\xff\xff\xff\xff\xff\xff" 2130 "\xff\xff\xff\xff\xff\xff\xff\xff", 2131 .dst_addr = 2132 "\xff\xff\xff\xff\xff\xff\xff\xff" 2133 "\xff\xff\xff\xff\xff\xff\xff\xff", 2134 .vtc_flow = RTE_BE32(0xffffffff), 2135 .proto = 0xff, 2136 }, 2137 }; 2138 const int tunnel = !!(item_flags & MLX5_FLOW_LAYER_TUNNEL); 2139 const uint64_t l3m = tunnel ? MLX5_FLOW_LAYER_INNER_L3 : 2140 MLX5_FLOW_LAYER_OUTER_L3; 2141 const uint64_t l4m = tunnel ? MLX5_FLOW_LAYER_INNER_L4 : 2142 MLX5_FLOW_LAYER_OUTER_L4; 2143 int ret; 2144 uint8_t next_proto = 0xFF; 2145 const uint64_t l2_vlan = (MLX5_FLOW_LAYER_L2 | 2146 MLX5_FLOW_LAYER_OUTER_VLAN | 2147 MLX5_FLOW_LAYER_INNER_VLAN); 2148 2149 if ((last_item & l2_vlan) && ether_type && 2150 ether_type != RTE_ETHER_TYPE_IPV6) 2151 return rte_flow_error_set(error, EINVAL, 2152 RTE_FLOW_ERROR_TYPE_ITEM, item, 2153 "IPv6 cannot follow L2/VLAN layer " 2154 "which ether type is not IPv6"); 2155 if (mask && mask->hdr.proto == UINT8_MAX && spec) 2156 next_proto = spec->hdr.proto; 2157 if (item_flags & MLX5_FLOW_LAYER_IPV6_ENCAP) { 2158 if (next_proto == IPPROTO_IPIP || next_proto == IPPROTO_IPV6) 2159 return rte_flow_error_set(error, EINVAL, 2160 RTE_FLOW_ERROR_TYPE_ITEM, 2161 item, 2162 "multiple tunnel " 2163 "not supported"); 2164 } 2165 if (next_proto == IPPROTO_HOPOPTS || 2166 next_proto == IPPROTO_ROUTING || 2167 next_proto == IPPROTO_FRAGMENT || 2168 next_proto == IPPROTO_ESP || 2169 next_proto == IPPROTO_AH || 2170 next_proto == IPPROTO_DSTOPTS) 2171 return rte_flow_error_set(error, EINVAL, 2172 RTE_FLOW_ERROR_TYPE_ITEM, item, 2173 "IPv6 proto (next header) should " 2174 "not be set as extension header"); 2175 if (item_flags & MLX5_FLOW_LAYER_IPIP) 2176 return rte_flow_error_set(error, EINVAL, 2177 RTE_FLOW_ERROR_TYPE_ITEM, item, 2178 "wrong tunnel type - IPv4 specified " 2179 "but IPv6 item provided"); 2180 if (item_flags & l3m) 2181 return rte_flow_error_set(error, ENOTSUP, 2182 RTE_FLOW_ERROR_TYPE_ITEM, item, 2183 "multiple L3 layers not supported"); 2184 else if (item_flags & l4m) 2185 return rte_flow_error_set(error, EINVAL, 2186 RTE_FLOW_ERROR_TYPE_ITEM, item, 2187 "L3 cannot follow an L4 layer."); 2188 else if ((item_flags & MLX5_FLOW_LAYER_NVGRE) && 2189 !(item_flags & MLX5_FLOW_LAYER_INNER_L2)) 2190 return rte_flow_error_set(error, EINVAL, 2191 RTE_FLOW_ERROR_TYPE_ITEM, item, 2192 "L3 cannot follow an NVGRE layer."); 2193 if (!mask) 2194 mask = &rte_flow_item_ipv6_mask; 2195 ret = mlx5_flow_item_acceptable(item, (const uint8_t *)mask, 2196 acc_mask ? (const uint8_t *)acc_mask 2197 : (const uint8_t *)&nic_mask, 2198 sizeof(struct rte_flow_item_ipv6), 2199 MLX5_ITEM_RANGE_NOT_ACCEPTED, error); 2200 if (ret < 0) 2201 return ret; 2202 return 0; 2203 } 2204 2205 /** 2206 * Validate UDP item. 2207 * 2208 * @param[in] item 2209 * Item specification. 2210 * @param[in] item_flags 2211 * Bit-fields that holds the items detected until now. 2212 * @param[in] target_protocol 2213 * The next protocol in the previous item. 2214 * @param[in] flow_mask 2215 * mlx5 flow-specific (DV, verbs, etc.) supported header fields mask. 2216 * @param[out] error 2217 * Pointer to error structure. 2218 * 2219 * @return 2220 * 0 on success, a negative errno value otherwise and rte_errno is set. 2221 */ 2222 int 2223 mlx5_flow_validate_item_udp(const struct rte_flow_item *item, 2224 uint64_t item_flags, 2225 uint8_t target_protocol, 2226 struct rte_flow_error *error) 2227 { 2228 const struct rte_flow_item_udp *mask = item->mask; 2229 const int tunnel = !!(item_flags & MLX5_FLOW_LAYER_TUNNEL); 2230 const uint64_t l3m = tunnel ? MLX5_FLOW_LAYER_INNER_L3 : 2231 MLX5_FLOW_LAYER_OUTER_L3; 2232 const uint64_t l4m = tunnel ? MLX5_FLOW_LAYER_INNER_L4 : 2233 MLX5_FLOW_LAYER_OUTER_L4; 2234 int ret; 2235 2236 if (target_protocol != 0xff && target_protocol != IPPROTO_UDP) 2237 return rte_flow_error_set(error, EINVAL, 2238 RTE_FLOW_ERROR_TYPE_ITEM, item, 2239 "protocol filtering not compatible" 2240 " with UDP layer"); 2241 if (!(item_flags & l3m)) 2242 return rte_flow_error_set(error, EINVAL, 2243 RTE_FLOW_ERROR_TYPE_ITEM, item, 2244 "L3 is mandatory to filter on L4"); 2245 if (item_flags & l4m) 2246 return rte_flow_error_set(error, EINVAL, 2247 RTE_FLOW_ERROR_TYPE_ITEM, item, 2248 "multiple L4 layers not supported"); 2249 if (!mask) 2250 mask = &rte_flow_item_udp_mask; 2251 ret = mlx5_flow_item_acceptable 2252 (item, (const uint8_t *)mask, 2253 (const uint8_t *)&rte_flow_item_udp_mask, 2254 sizeof(struct rte_flow_item_udp), MLX5_ITEM_RANGE_NOT_ACCEPTED, 2255 error); 2256 if (ret < 0) 2257 return ret; 2258 return 0; 2259 } 2260 2261 /** 2262 * Validate TCP item. 2263 * 2264 * @param[in] item 2265 * Item specification. 2266 * @param[in] item_flags 2267 * Bit-fields that holds the items detected until now. 2268 * @param[in] target_protocol 2269 * The next protocol in the previous item. 2270 * @param[out] error 2271 * Pointer to error structure. 2272 * 2273 * @return 2274 * 0 on success, a negative errno value otherwise and rte_errno is set. 2275 */ 2276 int 2277 mlx5_flow_validate_item_tcp(const struct rte_flow_item *item, 2278 uint64_t item_flags, 2279 uint8_t target_protocol, 2280 const struct rte_flow_item_tcp *flow_mask, 2281 struct rte_flow_error *error) 2282 { 2283 const struct rte_flow_item_tcp *mask = item->mask; 2284 const int tunnel = !!(item_flags & MLX5_FLOW_LAYER_TUNNEL); 2285 const uint64_t l3m = tunnel ? MLX5_FLOW_LAYER_INNER_L3 : 2286 MLX5_FLOW_LAYER_OUTER_L3; 2287 const uint64_t l4m = tunnel ? MLX5_FLOW_LAYER_INNER_L4 : 2288 MLX5_FLOW_LAYER_OUTER_L4; 2289 int ret; 2290 2291 MLX5_ASSERT(flow_mask); 2292 if (target_protocol != 0xff && target_protocol != IPPROTO_TCP) 2293 return rte_flow_error_set(error, EINVAL, 2294 RTE_FLOW_ERROR_TYPE_ITEM, item, 2295 "protocol filtering not compatible" 2296 " with TCP layer"); 2297 if (!(item_flags & l3m)) 2298 return rte_flow_error_set(error, EINVAL, 2299 RTE_FLOW_ERROR_TYPE_ITEM, item, 2300 "L3 is mandatory to filter on L4"); 2301 if (item_flags & l4m) 2302 return rte_flow_error_set(error, EINVAL, 2303 RTE_FLOW_ERROR_TYPE_ITEM, item, 2304 "multiple L4 layers not supported"); 2305 if (!mask) 2306 mask = &rte_flow_item_tcp_mask; 2307 ret = mlx5_flow_item_acceptable 2308 (item, (const uint8_t *)mask, 2309 (const uint8_t *)flow_mask, 2310 sizeof(struct rte_flow_item_tcp), MLX5_ITEM_RANGE_NOT_ACCEPTED, 2311 error); 2312 if (ret < 0) 2313 return ret; 2314 return 0; 2315 } 2316 2317 /** 2318 * Validate VXLAN item. 2319 * 2320 * @param[in] item 2321 * Item specification. 2322 * @param[in] item_flags 2323 * Bit-fields that holds the items detected until now. 2324 * @param[in] target_protocol 2325 * The next protocol in the previous item. 2326 * @param[out] error 2327 * Pointer to error structure. 2328 * 2329 * @return 2330 * 0 on success, a negative errno value otherwise and rte_errno is set. 2331 */ 2332 int 2333 mlx5_flow_validate_item_vxlan(const struct rte_flow_item *item, 2334 uint64_t item_flags, 2335 struct rte_flow_error *error) 2336 { 2337 const struct rte_flow_item_vxlan *spec = item->spec; 2338 const struct rte_flow_item_vxlan *mask = item->mask; 2339 int ret; 2340 union vni { 2341 uint32_t vlan_id; 2342 uint8_t vni[4]; 2343 } id = { .vlan_id = 0, }; 2344 2345 2346 if (item_flags & MLX5_FLOW_LAYER_TUNNEL) 2347 return rte_flow_error_set(error, ENOTSUP, 2348 RTE_FLOW_ERROR_TYPE_ITEM, item, 2349 "multiple tunnel layers not" 2350 " supported"); 2351 /* 2352 * Verify only UDPv4 is present as defined in 2353 * https://tools.ietf.org/html/rfc7348 2354 */ 2355 if (!(item_flags & MLX5_FLOW_LAYER_OUTER_L4_UDP)) 2356 return rte_flow_error_set(error, EINVAL, 2357 RTE_FLOW_ERROR_TYPE_ITEM, item, 2358 "no outer UDP layer found"); 2359 if (!mask) 2360 mask = &rte_flow_item_vxlan_mask; 2361 ret = mlx5_flow_item_acceptable 2362 (item, (const uint8_t *)mask, 2363 (const uint8_t *)&rte_flow_item_vxlan_mask, 2364 sizeof(struct rte_flow_item_vxlan), 2365 MLX5_ITEM_RANGE_NOT_ACCEPTED, error); 2366 if (ret < 0) 2367 return ret; 2368 if (spec) { 2369 memcpy(&id.vni[1], spec->vni, 3); 2370 memcpy(&id.vni[1], mask->vni, 3); 2371 } 2372 if (!(item_flags & MLX5_FLOW_LAYER_OUTER)) 2373 return rte_flow_error_set(error, ENOTSUP, 2374 RTE_FLOW_ERROR_TYPE_ITEM, item, 2375 "VXLAN tunnel must be fully defined"); 2376 return 0; 2377 } 2378 2379 /** 2380 * Validate VXLAN_GPE item. 2381 * 2382 * @param[in] item 2383 * Item specification. 2384 * @param[in] item_flags 2385 * Bit-fields that holds the items detected until now. 2386 * @param[in] priv 2387 * Pointer to the private data structure. 2388 * @param[in] target_protocol 2389 * The next protocol in the previous item. 2390 * @param[out] error 2391 * Pointer to error structure. 2392 * 2393 * @return 2394 * 0 on success, a negative errno value otherwise and rte_errno is set. 2395 */ 2396 int 2397 mlx5_flow_validate_item_vxlan_gpe(const struct rte_flow_item *item, 2398 uint64_t item_flags, 2399 struct rte_eth_dev *dev, 2400 struct rte_flow_error *error) 2401 { 2402 struct mlx5_priv *priv = dev->data->dev_private; 2403 const struct rte_flow_item_vxlan_gpe *spec = item->spec; 2404 const struct rte_flow_item_vxlan_gpe *mask = item->mask; 2405 int ret; 2406 union vni { 2407 uint32_t vlan_id; 2408 uint8_t vni[4]; 2409 } id = { .vlan_id = 0, }; 2410 2411 if (!priv->config.l3_vxlan_en) 2412 return rte_flow_error_set(error, ENOTSUP, 2413 RTE_FLOW_ERROR_TYPE_ITEM, item, 2414 "L3 VXLAN is not enabled by device" 2415 " parameter and/or not configured in" 2416 " firmware"); 2417 if (item_flags & MLX5_FLOW_LAYER_TUNNEL) 2418 return rte_flow_error_set(error, ENOTSUP, 2419 RTE_FLOW_ERROR_TYPE_ITEM, item, 2420 "multiple tunnel layers not" 2421 " supported"); 2422 /* 2423 * Verify only UDPv4 is present as defined in 2424 * https://tools.ietf.org/html/rfc7348 2425 */ 2426 if (!(item_flags & MLX5_FLOW_LAYER_OUTER_L4_UDP)) 2427 return rte_flow_error_set(error, EINVAL, 2428 RTE_FLOW_ERROR_TYPE_ITEM, item, 2429 "no outer UDP layer found"); 2430 if (!mask) 2431 mask = &rte_flow_item_vxlan_gpe_mask; 2432 ret = mlx5_flow_item_acceptable 2433 (item, (const uint8_t *)mask, 2434 (const uint8_t *)&rte_flow_item_vxlan_gpe_mask, 2435 sizeof(struct rte_flow_item_vxlan_gpe), 2436 MLX5_ITEM_RANGE_NOT_ACCEPTED, error); 2437 if (ret < 0) 2438 return ret; 2439 if (spec) { 2440 if (spec->protocol) 2441 return rte_flow_error_set(error, ENOTSUP, 2442 RTE_FLOW_ERROR_TYPE_ITEM, 2443 item, 2444 "VxLAN-GPE protocol" 2445 " not supported"); 2446 memcpy(&id.vni[1], spec->vni, 3); 2447 memcpy(&id.vni[1], mask->vni, 3); 2448 } 2449 if (!(item_flags & MLX5_FLOW_LAYER_OUTER)) 2450 return rte_flow_error_set(error, ENOTSUP, 2451 RTE_FLOW_ERROR_TYPE_ITEM, item, 2452 "VXLAN-GPE tunnel must be fully" 2453 " defined"); 2454 return 0; 2455 } 2456 /** 2457 * Validate GRE Key item. 2458 * 2459 * @param[in] item 2460 * Item specification. 2461 * @param[in] item_flags 2462 * Bit flags to mark detected items. 2463 * @param[in] gre_item 2464 * Pointer to gre_item 2465 * @param[out] error 2466 * Pointer to error structure. 2467 * 2468 * @return 2469 * 0 on success, a negative errno value otherwise and rte_errno is set. 2470 */ 2471 int 2472 mlx5_flow_validate_item_gre_key(const struct rte_flow_item *item, 2473 uint64_t item_flags, 2474 const struct rte_flow_item *gre_item, 2475 struct rte_flow_error *error) 2476 { 2477 const rte_be32_t *mask = item->mask; 2478 int ret = 0; 2479 rte_be32_t gre_key_default_mask = RTE_BE32(UINT32_MAX); 2480 const struct rte_flow_item_gre *gre_spec; 2481 const struct rte_flow_item_gre *gre_mask; 2482 2483 if (item_flags & MLX5_FLOW_LAYER_GRE_KEY) 2484 return rte_flow_error_set(error, ENOTSUP, 2485 RTE_FLOW_ERROR_TYPE_ITEM, item, 2486 "Multiple GRE key not support"); 2487 if (!(item_flags & MLX5_FLOW_LAYER_GRE)) 2488 return rte_flow_error_set(error, ENOTSUP, 2489 RTE_FLOW_ERROR_TYPE_ITEM, item, 2490 "No preceding GRE header"); 2491 if (item_flags & MLX5_FLOW_LAYER_INNER) 2492 return rte_flow_error_set(error, ENOTSUP, 2493 RTE_FLOW_ERROR_TYPE_ITEM, item, 2494 "GRE key following a wrong item"); 2495 gre_mask = gre_item->mask; 2496 if (!gre_mask) 2497 gre_mask = &rte_flow_item_gre_mask; 2498 gre_spec = gre_item->spec; 2499 if (gre_spec && (gre_mask->c_rsvd0_ver & RTE_BE16(0x2000)) && 2500 !(gre_spec->c_rsvd0_ver & RTE_BE16(0x2000))) 2501 return rte_flow_error_set(error, EINVAL, 2502 RTE_FLOW_ERROR_TYPE_ITEM, item, 2503 "Key bit must be on"); 2504 2505 if (!mask) 2506 mask = &gre_key_default_mask; 2507 ret = mlx5_flow_item_acceptable 2508 (item, (const uint8_t *)mask, 2509 (const uint8_t *)&gre_key_default_mask, 2510 sizeof(rte_be32_t), MLX5_ITEM_RANGE_NOT_ACCEPTED, error); 2511 return ret; 2512 } 2513 2514 /** 2515 * Validate GRE item. 2516 * 2517 * @param[in] item 2518 * Item specification. 2519 * @param[in] item_flags 2520 * Bit flags to mark detected items. 2521 * @param[in] target_protocol 2522 * The next protocol in the previous item. 2523 * @param[out] error 2524 * Pointer to error structure. 2525 * 2526 * @return 2527 * 0 on success, a negative errno value otherwise and rte_errno is set. 2528 */ 2529 int 2530 mlx5_flow_validate_item_gre(const struct rte_flow_item *item, 2531 uint64_t item_flags, 2532 uint8_t target_protocol, 2533 struct rte_flow_error *error) 2534 { 2535 const struct rte_flow_item_gre *spec __rte_unused = item->spec; 2536 const struct rte_flow_item_gre *mask = item->mask; 2537 int ret; 2538 const struct rte_flow_item_gre nic_mask = { 2539 .c_rsvd0_ver = RTE_BE16(0xB000), 2540 .protocol = RTE_BE16(UINT16_MAX), 2541 }; 2542 2543 if (target_protocol != 0xff && target_protocol != IPPROTO_GRE) 2544 return rte_flow_error_set(error, EINVAL, 2545 RTE_FLOW_ERROR_TYPE_ITEM, item, 2546 "protocol filtering not compatible" 2547 " with this GRE layer"); 2548 if (item_flags & MLX5_FLOW_LAYER_TUNNEL) 2549 return rte_flow_error_set(error, ENOTSUP, 2550 RTE_FLOW_ERROR_TYPE_ITEM, item, 2551 "multiple tunnel layers not" 2552 " supported"); 2553 if (!(item_flags & MLX5_FLOW_LAYER_OUTER_L3)) 2554 return rte_flow_error_set(error, ENOTSUP, 2555 RTE_FLOW_ERROR_TYPE_ITEM, item, 2556 "L3 Layer is missing"); 2557 if (!mask) 2558 mask = &rte_flow_item_gre_mask; 2559 ret = mlx5_flow_item_acceptable 2560 (item, (const uint8_t *)mask, 2561 (const uint8_t *)&nic_mask, 2562 sizeof(struct rte_flow_item_gre), MLX5_ITEM_RANGE_NOT_ACCEPTED, 2563 error); 2564 if (ret < 0) 2565 return ret; 2566 #ifndef HAVE_MLX5DV_DR 2567 #ifndef HAVE_IBV_DEVICE_MPLS_SUPPORT 2568 if (spec && (spec->protocol & mask->protocol)) 2569 return rte_flow_error_set(error, ENOTSUP, 2570 RTE_FLOW_ERROR_TYPE_ITEM, item, 2571 "without MPLS support the" 2572 " specification cannot be used for" 2573 " filtering"); 2574 #endif 2575 #endif 2576 return 0; 2577 } 2578 2579 /** 2580 * Validate Geneve item. 2581 * 2582 * @param[in] item 2583 * Item specification. 2584 * @param[in] itemFlags 2585 * Bit-fields that holds the items detected until now. 2586 * @param[in] enPriv 2587 * Pointer to the private data structure. 2588 * @param[out] error 2589 * Pointer to error structure. 2590 * 2591 * @return 2592 * 0 on success, a negative errno value otherwise and rte_errno is set. 2593 */ 2594 2595 int 2596 mlx5_flow_validate_item_geneve(const struct rte_flow_item *item, 2597 uint64_t item_flags, 2598 struct rte_eth_dev *dev, 2599 struct rte_flow_error *error) 2600 { 2601 struct mlx5_priv *priv = dev->data->dev_private; 2602 const struct rte_flow_item_geneve *spec = item->spec; 2603 const struct rte_flow_item_geneve *mask = item->mask; 2604 int ret; 2605 uint16_t gbhdr; 2606 uint8_t opt_len = priv->config.hca_attr.geneve_max_opt_len ? 2607 MLX5_GENEVE_OPT_LEN_1 : MLX5_GENEVE_OPT_LEN_0; 2608 const struct rte_flow_item_geneve nic_mask = { 2609 .ver_opt_len_o_c_rsvd0 = RTE_BE16(0x3f80), 2610 .vni = "\xff\xff\xff", 2611 .protocol = RTE_BE16(UINT16_MAX), 2612 }; 2613 2614 if (!priv->config.hca_attr.tunnel_stateless_geneve_rx) 2615 return rte_flow_error_set(error, ENOTSUP, 2616 RTE_FLOW_ERROR_TYPE_ITEM, item, 2617 "L3 Geneve is not enabled by device" 2618 " parameter and/or not configured in" 2619 " firmware"); 2620 if (item_flags & MLX5_FLOW_LAYER_TUNNEL) 2621 return rte_flow_error_set(error, ENOTSUP, 2622 RTE_FLOW_ERROR_TYPE_ITEM, item, 2623 "multiple tunnel layers not" 2624 " supported"); 2625 /* 2626 * Verify only UDPv4 is present as defined in 2627 * https://tools.ietf.org/html/rfc7348 2628 */ 2629 if (!(item_flags & MLX5_FLOW_LAYER_OUTER_L4_UDP)) 2630 return rte_flow_error_set(error, EINVAL, 2631 RTE_FLOW_ERROR_TYPE_ITEM, item, 2632 "no outer UDP layer found"); 2633 if (!mask) 2634 mask = &rte_flow_item_geneve_mask; 2635 ret = mlx5_flow_item_acceptable 2636 (item, (const uint8_t *)mask, 2637 (const uint8_t *)&nic_mask, 2638 sizeof(struct rte_flow_item_geneve), 2639 MLX5_ITEM_RANGE_NOT_ACCEPTED, error); 2640 if (ret) 2641 return ret; 2642 if (spec) { 2643 gbhdr = rte_be_to_cpu_16(spec->ver_opt_len_o_c_rsvd0); 2644 if (MLX5_GENEVE_VER_VAL(gbhdr) || 2645 MLX5_GENEVE_CRITO_VAL(gbhdr) || 2646 MLX5_GENEVE_RSVD_VAL(gbhdr) || spec->rsvd1) 2647 return rte_flow_error_set(error, ENOTSUP, 2648 RTE_FLOW_ERROR_TYPE_ITEM, 2649 item, 2650 "Geneve protocol unsupported" 2651 " fields are being used"); 2652 if (MLX5_GENEVE_OPTLEN_VAL(gbhdr) > opt_len) 2653 return rte_flow_error_set 2654 (error, ENOTSUP, 2655 RTE_FLOW_ERROR_TYPE_ITEM, 2656 item, 2657 "Unsupported Geneve options length"); 2658 } 2659 if (!(item_flags & MLX5_FLOW_LAYER_OUTER)) 2660 return rte_flow_error_set 2661 (error, ENOTSUP, 2662 RTE_FLOW_ERROR_TYPE_ITEM, item, 2663 "Geneve tunnel must be fully defined"); 2664 return 0; 2665 } 2666 2667 /** 2668 * Validate Geneve TLV option item. 2669 * 2670 * @param[in] item 2671 * Item specification. 2672 * @param[in] last_item 2673 * Previous validated item in the pattern items. 2674 * @param[in] geneve_item 2675 * Previous GENEVE item specification. 2676 * @param[in] dev 2677 * Pointer to the rte_eth_dev structure. 2678 * @param[out] error 2679 * Pointer to error structure. 2680 * 2681 * @return 2682 * 0 on success, a negative errno value otherwise and rte_errno is set. 2683 */ 2684 int 2685 mlx5_flow_validate_item_geneve_opt(const struct rte_flow_item *item, 2686 uint64_t last_item, 2687 const struct rte_flow_item *geneve_item, 2688 struct rte_eth_dev *dev, 2689 struct rte_flow_error *error) 2690 { 2691 struct mlx5_priv *priv = dev->data->dev_private; 2692 struct mlx5_dev_ctx_shared *sh = priv->sh; 2693 struct mlx5_geneve_tlv_option_resource *geneve_opt_resource; 2694 struct mlx5_hca_attr *hca_attr = &priv->config.hca_attr; 2695 uint8_t data_max_supported = 2696 hca_attr->max_geneve_tlv_option_data_len * 4; 2697 struct mlx5_dev_config *config = &priv->config; 2698 const struct rte_flow_item_geneve *geneve_spec; 2699 const struct rte_flow_item_geneve *geneve_mask; 2700 const struct rte_flow_item_geneve_opt *spec = item->spec; 2701 const struct rte_flow_item_geneve_opt *mask = item->mask; 2702 unsigned int i; 2703 unsigned int data_len; 2704 uint8_t tlv_option_len; 2705 uint16_t optlen_m, optlen_v; 2706 const struct rte_flow_item_geneve_opt full_mask = { 2707 .option_class = RTE_BE16(0xffff), 2708 .option_type = 0xff, 2709 .option_len = 0x1f, 2710 }; 2711 2712 if (!mask) 2713 mask = &rte_flow_item_geneve_opt_mask; 2714 if (!spec) 2715 return rte_flow_error_set 2716 (error, ENOTSUP, RTE_FLOW_ERROR_TYPE_ITEM, item, 2717 "Geneve TLV opt class/type/length must be specified"); 2718 if ((uint32_t)spec->option_len > MLX5_GENEVE_OPTLEN_MASK) 2719 return rte_flow_error_set 2720 (error, ENOTSUP, RTE_FLOW_ERROR_TYPE_ITEM, item, 2721 "Geneve TLV opt length exceeeds the limit (31)"); 2722 /* Check if class type and length masks are full. */ 2723 if (full_mask.option_class != mask->option_class || 2724 full_mask.option_type != mask->option_type || 2725 full_mask.option_len != (mask->option_len & full_mask.option_len)) 2726 return rte_flow_error_set 2727 (error, ENOTSUP, RTE_FLOW_ERROR_TYPE_ITEM, item, 2728 "Geneve TLV opt class/type/length masks must be full"); 2729 /* Check if length is supported */ 2730 if ((uint32_t)spec->option_len > 2731 config->hca_attr.max_geneve_tlv_option_data_len) 2732 return rte_flow_error_set 2733 (error, ENOTSUP, RTE_FLOW_ERROR_TYPE_ITEM, item, 2734 "Geneve TLV opt length not supported"); 2735 if (config->hca_attr.max_geneve_tlv_options > 1) 2736 DRV_LOG(DEBUG, 2737 "max_geneve_tlv_options supports more than 1 option"); 2738 /* Check GENEVE item preceding. */ 2739 if (!geneve_item || !(last_item & MLX5_FLOW_LAYER_GENEVE)) 2740 return rte_flow_error_set 2741 (error, ENOTSUP, RTE_FLOW_ERROR_TYPE_ITEM, item, 2742 "Geneve opt item must be preceded with Geneve item"); 2743 geneve_spec = geneve_item->spec; 2744 geneve_mask = geneve_item->mask ? geneve_item->mask : 2745 &rte_flow_item_geneve_mask; 2746 /* Check if GENEVE TLV option size doesn't exceed option length */ 2747 if (geneve_spec && (geneve_mask->ver_opt_len_o_c_rsvd0 || 2748 geneve_spec->ver_opt_len_o_c_rsvd0)) { 2749 tlv_option_len = spec->option_len & mask->option_len; 2750 optlen_v = rte_be_to_cpu_16(geneve_spec->ver_opt_len_o_c_rsvd0); 2751 optlen_v = MLX5_GENEVE_OPTLEN_VAL(optlen_v); 2752 optlen_m = rte_be_to_cpu_16(geneve_mask->ver_opt_len_o_c_rsvd0); 2753 optlen_m = MLX5_GENEVE_OPTLEN_VAL(optlen_m); 2754 if ((optlen_v & optlen_m) <= tlv_option_len) 2755 return rte_flow_error_set 2756 (error, ENOTSUP, RTE_FLOW_ERROR_TYPE_ITEM, item, 2757 "GENEVE TLV option length exceeds optlen"); 2758 } 2759 /* Check if length is 0 or data is 0. */ 2760 if (spec->data == NULL || spec->option_len == 0) 2761 return rte_flow_error_set 2762 (error, ENOTSUP, RTE_FLOW_ERROR_TYPE_ITEM, item, 2763 "Geneve TLV opt with zero data/length not supported"); 2764 /* Check not all data & mask are 0. */ 2765 data_len = spec->option_len * 4; 2766 if (mask->data == NULL) { 2767 for (i = 0; i < data_len; i++) 2768 if (spec->data[i]) 2769 break; 2770 if (i == data_len) 2771 return rte_flow_error_set(error, ENOTSUP, 2772 RTE_FLOW_ERROR_TYPE_ITEM, item, 2773 "Can't match on Geneve option data 0"); 2774 } else { 2775 for (i = 0; i < data_len; i++) 2776 if (spec->data[i] & mask->data[i]) 2777 break; 2778 if (i == data_len) 2779 return rte_flow_error_set(error, ENOTSUP, 2780 RTE_FLOW_ERROR_TYPE_ITEM, item, 2781 "Can't match on Geneve option data and mask 0"); 2782 /* Check data mask supported. */ 2783 for (i = data_max_supported; i < data_len ; i++) 2784 if (mask->data[i]) 2785 return rte_flow_error_set(error, ENOTSUP, 2786 RTE_FLOW_ERROR_TYPE_ITEM, item, 2787 "Data mask is of unsupported size"); 2788 } 2789 /* Check GENEVE option is supported in NIC. */ 2790 if (!config->hca_attr.geneve_tlv_opt) 2791 return rte_flow_error_set 2792 (error, ENOTSUP, RTE_FLOW_ERROR_TYPE_ITEM, item, 2793 "Geneve TLV opt not supported"); 2794 /* Check if we already have geneve option with different type/class. */ 2795 rte_spinlock_lock(&sh->geneve_tlv_opt_sl); 2796 geneve_opt_resource = sh->geneve_tlv_option_resource; 2797 if (geneve_opt_resource != NULL) 2798 if (geneve_opt_resource->option_class != spec->option_class || 2799 geneve_opt_resource->option_type != spec->option_type || 2800 geneve_opt_resource->length != spec->option_len) { 2801 rte_spinlock_unlock(&sh->geneve_tlv_opt_sl); 2802 return rte_flow_error_set(error, ENOTSUP, 2803 RTE_FLOW_ERROR_TYPE_ITEM, item, 2804 "Only one Geneve TLV option supported"); 2805 } 2806 rte_spinlock_unlock(&sh->geneve_tlv_opt_sl); 2807 return 0; 2808 } 2809 2810 /** 2811 * Validate MPLS item. 2812 * 2813 * @param[in] dev 2814 * Pointer to the rte_eth_dev structure. 2815 * @param[in] item 2816 * Item specification. 2817 * @param[in] item_flags 2818 * Bit-fields that holds the items detected until now. 2819 * @param[in] prev_layer 2820 * The protocol layer indicated in previous item. 2821 * @param[out] error 2822 * Pointer to error structure. 2823 * 2824 * @return 2825 * 0 on success, a negative errno value otherwise and rte_errno is set. 2826 */ 2827 int 2828 mlx5_flow_validate_item_mpls(struct rte_eth_dev *dev __rte_unused, 2829 const struct rte_flow_item *item __rte_unused, 2830 uint64_t item_flags __rte_unused, 2831 uint64_t prev_layer __rte_unused, 2832 struct rte_flow_error *error) 2833 { 2834 #ifdef HAVE_IBV_DEVICE_MPLS_SUPPORT 2835 const struct rte_flow_item_mpls *mask = item->mask; 2836 struct mlx5_priv *priv = dev->data->dev_private; 2837 int ret; 2838 2839 if (!priv->config.mpls_en) 2840 return rte_flow_error_set(error, ENOTSUP, 2841 RTE_FLOW_ERROR_TYPE_ITEM, item, 2842 "MPLS not supported or" 2843 " disabled in firmware" 2844 " configuration."); 2845 /* MPLS over IP, UDP, GRE is allowed */ 2846 if (!(prev_layer & (MLX5_FLOW_LAYER_OUTER_L3 | 2847 MLX5_FLOW_LAYER_OUTER_L4_UDP | 2848 MLX5_FLOW_LAYER_GRE | 2849 MLX5_FLOW_LAYER_GRE_KEY))) 2850 return rte_flow_error_set(error, EINVAL, 2851 RTE_FLOW_ERROR_TYPE_ITEM, item, 2852 "protocol filtering not compatible" 2853 " with MPLS layer"); 2854 /* Multi-tunnel isn't allowed but MPLS over GRE is an exception. */ 2855 if ((item_flags & MLX5_FLOW_LAYER_TUNNEL) && 2856 !(item_flags & MLX5_FLOW_LAYER_GRE)) 2857 return rte_flow_error_set(error, ENOTSUP, 2858 RTE_FLOW_ERROR_TYPE_ITEM, item, 2859 "multiple tunnel layers not" 2860 " supported"); 2861 if (!mask) 2862 mask = &rte_flow_item_mpls_mask; 2863 ret = mlx5_flow_item_acceptable 2864 (item, (const uint8_t *)mask, 2865 (const uint8_t *)&rte_flow_item_mpls_mask, 2866 sizeof(struct rte_flow_item_mpls), 2867 MLX5_ITEM_RANGE_NOT_ACCEPTED, error); 2868 if (ret < 0) 2869 return ret; 2870 return 0; 2871 #else 2872 return rte_flow_error_set(error, ENOTSUP, 2873 RTE_FLOW_ERROR_TYPE_ITEM, item, 2874 "MPLS is not supported by Verbs, please" 2875 " update."); 2876 #endif 2877 } 2878 2879 /** 2880 * Validate NVGRE item. 2881 * 2882 * @param[in] item 2883 * Item specification. 2884 * @param[in] item_flags 2885 * Bit flags to mark detected items. 2886 * @param[in] target_protocol 2887 * The next protocol in the previous item. 2888 * @param[out] error 2889 * Pointer to error structure. 2890 * 2891 * @return 2892 * 0 on success, a negative errno value otherwise and rte_errno is set. 2893 */ 2894 int 2895 mlx5_flow_validate_item_nvgre(const struct rte_flow_item *item, 2896 uint64_t item_flags, 2897 uint8_t target_protocol, 2898 struct rte_flow_error *error) 2899 { 2900 const struct rte_flow_item_nvgre *mask = item->mask; 2901 int ret; 2902 2903 if (target_protocol != 0xff && target_protocol != IPPROTO_GRE) 2904 return rte_flow_error_set(error, EINVAL, 2905 RTE_FLOW_ERROR_TYPE_ITEM, item, 2906 "protocol filtering not compatible" 2907 " with this GRE layer"); 2908 if (item_flags & MLX5_FLOW_LAYER_TUNNEL) 2909 return rte_flow_error_set(error, ENOTSUP, 2910 RTE_FLOW_ERROR_TYPE_ITEM, item, 2911 "multiple tunnel layers not" 2912 " supported"); 2913 if (!(item_flags & MLX5_FLOW_LAYER_OUTER_L3)) 2914 return rte_flow_error_set(error, ENOTSUP, 2915 RTE_FLOW_ERROR_TYPE_ITEM, item, 2916 "L3 Layer is missing"); 2917 if (!mask) 2918 mask = &rte_flow_item_nvgre_mask; 2919 ret = mlx5_flow_item_acceptable 2920 (item, (const uint8_t *)mask, 2921 (const uint8_t *)&rte_flow_item_nvgre_mask, 2922 sizeof(struct rte_flow_item_nvgre), 2923 MLX5_ITEM_RANGE_NOT_ACCEPTED, error); 2924 if (ret < 0) 2925 return ret; 2926 return 0; 2927 } 2928 2929 /** 2930 * Validate eCPRI item. 2931 * 2932 * @param[in] item 2933 * Item specification. 2934 * @param[in] item_flags 2935 * Bit-fields that holds the items detected until now. 2936 * @param[in] last_item 2937 * Previous validated item in the pattern items. 2938 * @param[in] ether_type 2939 * Type in the ethernet layer header (including dot1q). 2940 * @param[in] acc_mask 2941 * Acceptable mask, if NULL default internal default mask 2942 * will be used to check whether item fields are supported. 2943 * @param[out] error 2944 * Pointer to error structure. 2945 * 2946 * @return 2947 * 0 on success, a negative errno value otherwise and rte_errno is set. 2948 */ 2949 int 2950 mlx5_flow_validate_item_ecpri(const struct rte_flow_item *item, 2951 uint64_t item_flags, 2952 uint64_t last_item, 2953 uint16_t ether_type, 2954 const struct rte_flow_item_ecpri *acc_mask, 2955 struct rte_flow_error *error) 2956 { 2957 const struct rte_flow_item_ecpri *mask = item->mask; 2958 const struct rte_flow_item_ecpri nic_mask = { 2959 .hdr = { 2960 .common = { 2961 .u32 = 2962 RTE_BE32(((const struct rte_ecpri_common_hdr) { 2963 .type = 0xFF, 2964 }).u32), 2965 }, 2966 .dummy[0] = 0xFFFFFFFF, 2967 }, 2968 }; 2969 const uint64_t outer_l2_vlan = (MLX5_FLOW_LAYER_OUTER_L2 | 2970 MLX5_FLOW_LAYER_OUTER_VLAN); 2971 struct rte_flow_item_ecpri mask_lo; 2972 2973 if (!(last_item & outer_l2_vlan) && 2974 last_item != MLX5_FLOW_LAYER_OUTER_L4_UDP) 2975 return rte_flow_error_set(error, EINVAL, 2976 RTE_FLOW_ERROR_TYPE_ITEM, item, 2977 "eCPRI can only follow L2/VLAN layer or UDP layer"); 2978 if ((last_item & outer_l2_vlan) && ether_type && 2979 ether_type != RTE_ETHER_TYPE_ECPRI) 2980 return rte_flow_error_set(error, EINVAL, 2981 RTE_FLOW_ERROR_TYPE_ITEM, item, 2982 "eCPRI cannot follow L2/VLAN layer which ether type is not 0xAEFE"); 2983 if (item_flags & MLX5_FLOW_LAYER_TUNNEL) 2984 return rte_flow_error_set(error, EINVAL, 2985 RTE_FLOW_ERROR_TYPE_ITEM, item, 2986 "eCPRI with tunnel is not supported right now"); 2987 if (item_flags & MLX5_FLOW_LAYER_OUTER_L3) 2988 return rte_flow_error_set(error, ENOTSUP, 2989 RTE_FLOW_ERROR_TYPE_ITEM, item, 2990 "multiple L3 layers not supported"); 2991 else if (item_flags & MLX5_FLOW_LAYER_OUTER_L4_TCP) 2992 return rte_flow_error_set(error, EINVAL, 2993 RTE_FLOW_ERROR_TYPE_ITEM, item, 2994 "eCPRI cannot coexist with a TCP layer"); 2995 /* In specification, eCPRI could be over UDP layer. */ 2996 else if (item_flags & MLX5_FLOW_LAYER_OUTER_L4_UDP) 2997 return rte_flow_error_set(error, EINVAL, 2998 RTE_FLOW_ERROR_TYPE_ITEM, item, 2999 "eCPRI over UDP layer is not yet supported right now"); 3000 /* Mask for type field in common header could be zero. */ 3001 if (!mask) 3002 mask = &rte_flow_item_ecpri_mask; 3003 mask_lo.hdr.common.u32 = rte_be_to_cpu_32(mask->hdr.common.u32); 3004 /* Input mask is in big-endian format. */ 3005 if (mask_lo.hdr.common.type != 0 && mask_lo.hdr.common.type != 0xff) 3006 return rte_flow_error_set(error, EINVAL, 3007 RTE_FLOW_ERROR_TYPE_ITEM_MASK, mask, 3008 "partial mask is not supported for protocol"); 3009 else if (mask_lo.hdr.common.type == 0 && mask->hdr.dummy[0] != 0) 3010 return rte_flow_error_set(error, EINVAL, 3011 RTE_FLOW_ERROR_TYPE_ITEM_MASK, mask, 3012 "message header mask must be after a type mask"); 3013 return mlx5_flow_item_acceptable(item, (const uint8_t *)mask, 3014 acc_mask ? (const uint8_t *)acc_mask 3015 : (const uint8_t *)&nic_mask, 3016 sizeof(struct rte_flow_item_ecpri), 3017 MLX5_ITEM_RANGE_NOT_ACCEPTED, error); 3018 } 3019 3020 /** 3021 * Release resource related QUEUE/RSS action split. 3022 * 3023 * @param dev 3024 * Pointer to Ethernet device. 3025 * @param flow 3026 * Flow to release id's from. 3027 */ 3028 static void 3029 flow_mreg_split_qrss_release(struct rte_eth_dev *dev, 3030 struct rte_flow *flow) 3031 { 3032 struct mlx5_priv *priv = dev->data->dev_private; 3033 uint32_t handle_idx; 3034 struct mlx5_flow_handle *dev_handle; 3035 3036 SILIST_FOREACH(priv->sh->ipool[MLX5_IPOOL_MLX5_FLOW], flow->dev_handles, 3037 handle_idx, dev_handle, next) 3038 if (dev_handle->split_flow_id) 3039 mlx5_ipool_free(priv->sh->ipool 3040 [MLX5_IPOOL_RSS_EXPANTION_FLOW_ID], 3041 dev_handle->split_flow_id); 3042 } 3043 3044 static int 3045 flow_null_validate(struct rte_eth_dev *dev __rte_unused, 3046 const struct rte_flow_attr *attr __rte_unused, 3047 const struct rte_flow_item items[] __rte_unused, 3048 const struct rte_flow_action actions[] __rte_unused, 3049 bool external __rte_unused, 3050 int hairpin __rte_unused, 3051 struct rte_flow_error *error) 3052 { 3053 return rte_flow_error_set(error, ENOTSUP, 3054 RTE_FLOW_ERROR_TYPE_UNSPECIFIED, NULL, NULL); 3055 } 3056 3057 static struct mlx5_flow * 3058 flow_null_prepare(struct rte_eth_dev *dev __rte_unused, 3059 const struct rte_flow_attr *attr __rte_unused, 3060 const struct rte_flow_item items[] __rte_unused, 3061 const struct rte_flow_action actions[] __rte_unused, 3062 struct rte_flow_error *error) 3063 { 3064 rte_flow_error_set(error, ENOTSUP, 3065 RTE_FLOW_ERROR_TYPE_UNSPECIFIED, NULL, NULL); 3066 return NULL; 3067 } 3068 3069 static int 3070 flow_null_translate(struct rte_eth_dev *dev __rte_unused, 3071 struct mlx5_flow *dev_flow __rte_unused, 3072 const struct rte_flow_attr *attr __rte_unused, 3073 const struct rte_flow_item items[] __rte_unused, 3074 const struct rte_flow_action actions[] __rte_unused, 3075 struct rte_flow_error *error) 3076 { 3077 return rte_flow_error_set(error, ENOTSUP, 3078 RTE_FLOW_ERROR_TYPE_UNSPECIFIED, NULL, NULL); 3079 } 3080 3081 static int 3082 flow_null_apply(struct rte_eth_dev *dev __rte_unused, 3083 struct rte_flow *flow __rte_unused, 3084 struct rte_flow_error *error) 3085 { 3086 return rte_flow_error_set(error, ENOTSUP, 3087 RTE_FLOW_ERROR_TYPE_UNSPECIFIED, NULL, NULL); 3088 } 3089 3090 static void 3091 flow_null_remove(struct rte_eth_dev *dev __rte_unused, 3092 struct rte_flow *flow __rte_unused) 3093 { 3094 } 3095 3096 static void 3097 flow_null_destroy(struct rte_eth_dev *dev __rte_unused, 3098 struct rte_flow *flow __rte_unused) 3099 { 3100 } 3101 3102 static int 3103 flow_null_query(struct rte_eth_dev *dev __rte_unused, 3104 struct rte_flow *flow __rte_unused, 3105 const struct rte_flow_action *actions __rte_unused, 3106 void *data __rte_unused, 3107 struct rte_flow_error *error) 3108 { 3109 return rte_flow_error_set(error, ENOTSUP, 3110 RTE_FLOW_ERROR_TYPE_UNSPECIFIED, NULL, NULL); 3111 } 3112 3113 static int 3114 flow_null_sync_domain(struct rte_eth_dev *dev __rte_unused, 3115 uint32_t domains __rte_unused, 3116 uint32_t flags __rte_unused) 3117 { 3118 return 0; 3119 } 3120 3121 /* Void driver to protect from null pointer reference. */ 3122 const struct mlx5_flow_driver_ops mlx5_flow_null_drv_ops = { 3123 .validate = flow_null_validate, 3124 .prepare = flow_null_prepare, 3125 .translate = flow_null_translate, 3126 .apply = flow_null_apply, 3127 .remove = flow_null_remove, 3128 .destroy = flow_null_destroy, 3129 .query = flow_null_query, 3130 .sync_domain = flow_null_sync_domain, 3131 }; 3132 3133 /** 3134 * Select flow driver type according to flow attributes and device 3135 * configuration. 3136 * 3137 * @param[in] dev 3138 * Pointer to the dev structure. 3139 * @param[in] attr 3140 * Pointer to the flow attributes. 3141 * 3142 * @return 3143 * flow driver type, MLX5_FLOW_TYPE_MAX otherwise. 3144 */ 3145 static enum mlx5_flow_drv_type 3146 flow_get_drv_type(struct rte_eth_dev *dev, const struct rte_flow_attr *attr) 3147 { 3148 struct mlx5_priv *priv = dev->data->dev_private; 3149 /* The OS can determine first a specific flow type (DV, VERBS) */ 3150 enum mlx5_flow_drv_type type = mlx5_flow_os_get_type(); 3151 3152 if (type != MLX5_FLOW_TYPE_MAX) 3153 return type; 3154 /* If no OS specific type - continue with DV/VERBS selection */ 3155 if (attr->transfer && priv->config.dv_esw_en) 3156 type = MLX5_FLOW_TYPE_DV; 3157 if (!attr->transfer) 3158 type = priv->config.dv_flow_en ? MLX5_FLOW_TYPE_DV : 3159 MLX5_FLOW_TYPE_VERBS; 3160 return type; 3161 } 3162 3163 #define flow_get_drv_ops(type) flow_drv_ops[type] 3164 3165 /** 3166 * Flow driver validation API. This abstracts calling driver specific functions. 3167 * The type of flow driver is determined according to flow attributes. 3168 * 3169 * @param[in] dev 3170 * Pointer to the dev structure. 3171 * @param[in] attr 3172 * Pointer to the flow attributes. 3173 * @param[in] items 3174 * Pointer to the list of items. 3175 * @param[in] actions 3176 * Pointer to the list of actions. 3177 * @param[in] external 3178 * This flow rule is created by request external to PMD. 3179 * @param[in] hairpin 3180 * Number of hairpin TX actions, 0 means classic flow. 3181 * @param[out] error 3182 * Pointer to the error structure. 3183 * 3184 * @return 3185 * 0 on success, a negative errno value otherwise and rte_errno is set. 3186 */ 3187 static inline int 3188 flow_drv_validate(struct rte_eth_dev *dev, 3189 const struct rte_flow_attr *attr, 3190 const struct rte_flow_item items[], 3191 const struct rte_flow_action actions[], 3192 bool external, int hairpin, struct rte_flow_error *error) 3193 { 3194 const struct mlx5_flow_driver_ops *fops; 3195 enum mlx5_flow_drv_type type = flow_get_drv_type(dev, attr); 3196 3197 fops = flow_get_drv_ops(type); 3198 return fops->validate(dev, attr, items, actions, external, 3199 hairpin, error); 3200 } 3201 3202 /** 3203 * Flow driver preparation API. This abstracts calling driver specific 3204 * functions. Parent flow (rte_flow) should have driver type (drv_type). It 3205 * calculates the size of memory required for device flow, allocates the memory, 3206 * initializes the device flow and returns the pointer. 3207 * 3208 * @note 3209 * This function initializes device flow structure such as dv or verbs in 3210 * struct mlx5_flow. However, it is caller's responsibility to initialize the 3211 * rest. For example, adding returning device flow to flow->dev_flow list and 3212 * setting backward reference to the flow should be done out of this function. 3213 * layers field is not filled either. 3214 * 3215 * @param[in] dev 3216 * Pointer to the dev structure. 3217 * @param[in] attr 3218 * Pointer to the flow attributes. 3219 * @param[in] items 3220 * Pointer to the list of items. 3221 * @param[in] actions 3222 * Pointer to the list of actions. 3223 * @param[in] flow_idx 3224 * This memory pool index to the flow. 3225 * @param[out] error 3226 * Pointer to the error structure. 3227 * 3228 * @return 3229 * Pointer to device flow on success, otherwise NULL and rte_errno is set. 3230 */ 3231 static inline struct mlx5_flow * 3232 flow_drv_prepare(struct rte_eth_dev *dev, 3233 const struct rte_flow *flow, 3234 const struct rte_flow_attr *attr, 3235 const struct rte_flow_item items[], 3236 const struct rte_flow_action actions[], 3237 uint32_t flow_idx, 3238 struct rte_flow_error *error) 3239 { 3240 const struct mlx5_flow_driver_ops *fops; 3241 enum mlx5_flow_drv_type type = flow->drv_type; 3242 struct mlx5_flow *mlx5_flow = NULL; 3243 3244 MLX5_ASSERT(type > MLX5_FLOW_TYPE_MIN && type < MLX5_FLOW_TYPE_MAX); 3245 fops = flow_get_drv_ops(type); 3246 mlx5_flow = fops->prepare(dev, attr, items, actions, error); 3247 if (mlx5_flow) 3248 mlx5_flow->flow_idx = flow_idx; 3249 return mlx5_flow; 3250 } 3251 3252 /** 3253 * Flow driver translation API. This abstracts calling driver specific 3254 * functions. Parent flow (rte_flow) should have driver type (drv_type). It 3255 * translates a generic flow into a driver flow. flow_drv_prepare() must 3256 * precede. 3257 * 3258 * @note 3259 * dev_flow->layers could be filled as a result of parsing during translation 3260 * if needed by flow_drv_apply(). dev_flow->flow->actions can also be filled 3261 * if necessary. As a flow can have multiple dev_flows by RSS flow expansion, 3262 * flow->actions could be overwritten even though all the expanded dev_flows 3263 * have the same actions. 3264 * 3265 * @param[in] dev 3266 * Pointer to the rte dev structure. 3267 * @param[in, out] dev_flow 3268 * Pointer to the mlx5 flow. 3269 * @param[in] attr 3270 * Pointer to the flow attributes. 3271 * @param[in] items 3272 * Pointer to the list of items. 3273 * @param[in] actions 3274 * Pointer to the list of actions. 3275 * @param[out] error 3276 * Pointer to the error structure. 3277 * 3278 * @return 3279 * 0 on success, a negative errno value otherwise and rte_errno is set. 3280 */ 3281 static inline int 3282 flow_drv_translate(struct rte_eth_dev *dev, struct mlx5_flow *dev_flow, 3283 const struct rte_flow_attr *attr, 3284 const struct rte_flow_item items[], 3285 const struct rte_flow_action actions[], 3286 struct rte_flow_error *error) 3287 { 3288 const struct mlx5_flow_driver_ops *fops; 3289 enum mlx5_flow_drv_type type = dev_flow->flow->drv_type; 3290 3291 MLX5_ASSERT(type > MLX5_FLOW_TYPE_MIN && type < MLX5_FLOW_TYPE_MAX); 3292 fops = flow_get_drv_ops(type); 3293 return fops->translate(dev, dev_flow, attr, items, actions, error); 3294 } 3295 3296 /** 3297 * Flow driver apply API. This abstracts calling driver specific functions. 3298 * Parent flow (rte_flow) should have driver type (drv_type). It applies 3299 * translated driver flows on to device. flow_drv_translate() must precede. 3300 * 3301 * @param[in] dev 3302 * Pointer to Ethernet device structure. 3303 * @param[in, out] flow 3304 * Pointer to flow structure. 3305 * @param[out] error 3306 * Pointer to error structure. 3307 * 3308 * @return 3309 * 0 on success, a negative errno value otherwise and rte_errno is set. 3310 */ 3311 static inline int 3312 flow_drv_apply(struct rte_eth_dev *dev, struct rte_flow *flow, 3313 struct rte_flow_error *error) 3314 { 3315 const struct mlx5_flow_driver_ops *fops; 3316 enum mlx5_flow_drv_type type = flow->drv_type; 3317 3318 MLX5_ASSERT(type > MLX5_FLOW_TYPE_MIN && type < MLX5_FLOW_TYPE_MAX); 3319 fops = flow_get_drv_ops(type); 3320 return fops->apply(dev, flow, error); 3321 } 3322 3323 /** 3324 * Flow driver destroy API. This abstracts calling driver specific functions. 3325 * Parent flow (rte_flow) should have driver type (drv_type). It removes a flow 3326 * on device and releases resources of the flow. 3327 * 3328 * @param[in] dev 3329 * Pointer to Ethernet device. 3330 * @param[in, out] flow 3331 * Pointer to flow structure. 3332 */ 3333 static inline void 3334 flow_drv_destroy(struct rte_eth_dev *dev, struct rte_flow *flow) 3335 { 3336 const struct mlx5_flow_driver_ops *fops; 3337 enum mlx5_flow_drv_type type = flow->drv_type; 3338 3339 flow_mreg_split_qrss_release(dev, flow); 3340 MLX5_ASSERT(type > MLX5_FLOW_TYPE_MIN && type < MLX5_FLOW_TYPE_MAX); 3341 fops = flow_get_drv_ops(type); 3342 fops->destroy(dev, flow); 3343 } 3344 3345 /** 3346 * Get RSS action from the action list. 3347 * 3348 * @param[in] actions 3349 * Pointer to the list of actions. 3350 * 3351 * @return 3352 * Pointer to the RSS action if exist, else return NULL. 3353 */ 3354 static const struct rte_flow_action_rss* 3355 flow_get_rss_action(const struct rte_flow_action actions[]) 3356 { 3357 const struct rte_flow_action_rss *rss = NULL; 3358 3359 for (; actions->type != RTE_FLOW_ACTION_TYPE_END; actions++) { 3360 switch (actions->type) { 3361 case RTE_FLOW_ACTION_TYPE_RSS: 3362 rss = actions->conf; 3363 break; 3364 case RTE_FLOW_ACTION_TYPE_SAMPLE: 3365 { 3366 const struct rte_flow_action_sample *sample = 3367 actions->conf; 3368 const struct rte_flow_action *act = sample->actions; 3369 for (; act->type != RTE_FLOW_ACTION_TYPE_END; act++) 3370 if (act->type == RTE_FLOW_ACTION_TYPE_RSS) 3371 rss = act->conf; 3372 break; 3373 } 3374 default: 3375 break; 3376 } 3377 } 3378 return rss; 3379 } 3380 3381 /** 3382 * Get ASO age action by index. 3383 * 3384 * @param[in] dev 3385 * Pointer to the Ethernet device structure. 3386 * @param[in] age_idx 3387 * Index to the ASO age action. 3388 * 3389 * @return 3390 * The specified ASO age action. 3391 */ 3392 struct mlx5_aso_age_action* 3393 flow_aso_age_get_by_idx(struct rte_eth_dev *dev, uint32_t age_idx) 3394 { 3395 uint16_t pool_idx = age_idx & UINT16_MAX; 3396 uint16_t offset = (age_idx >> 16) & UINT16_MAX; 3397 struct mlx5_priv *priv = dev->data->dev_private; 3398 struct mlx5_aso_age_mng *mng = priv->sh->aso_age_mng; 3399 struct mlx5_aso_age_pool *pool = mng->pools[pool_idx]; 3400 3401 return &pool->actions[offset - 1]; 3402 } 3403 3404 /* maps indirect action to translated direct in some actions array */ 3405 struct mlx5_translated_action_handle { 3406 struct rte_flow_action_handle *action; /**< Indirect action handle. */ 3407 int index; /**< Index in related array of rte_flow_action. */ 3408 }; 3409 3410 /** 3411 * Translates actions of type RTE_FLOW_ACTION_TYPE_INDIRECT to related 3412 * direct action if translation possible. 3413 * This functionality used to run same execution path for both direct and 3414 * indirect actions on flow create. All necessary preparations for indirect 3415 * action handling should be performed on *handle* actions list returned 3416 * from this call. 3417 * 3418 * @param[in] dev 3419 * Pointer to Ethernet device. 3420 * @param[in] actions 3421 * List of actions to translate. 3422 * @param[out] handle 3423 * List to store translated indirect action object handles. 3424 * @param[in, out] indir_n 3425 * Size of *handle* array. On return should be updated with number of 3426 * indirect actions retrieved from the *actions* list. 3427 * @param[out] translated_actions 3428 * List of actions where all indirect actions were translated to direct 3429 * if possible. NULL if no translation took place. 3430 * @param[out] error 3431 * Pointer to the error structure. 3432 * 3433 * @return 3434 * 0 on success, a negative errno value otherwise and rte_errno is set. 3435 */ 3436 static int 3437 flow_action_handles_translate(struct rte_eth_dev *dev, 3438 const struct rte_flow_action actions[], 3439 struct mlx5_translated_action_handle *handle, 3440 int *indir_n, 3441 struct rte_flow_action **translated_actions, 3442 struct rte_flow_error *error) 3443 { 3444 struct mlx5_priv *priv = dev->data->dev_private; 3445 struct rte_flow_action *translated = NULL; 3446 size_t actions_size; 3447 int n; 3448 int copied_n = 0; 3449 struct mlx5_translated_action_handle *handle_end = NULL; 3450 3451 for (n = 0; actions[n].type != RTE_FLOW_ACTION_TYPE_END; n++) { 3452 if (actions[n].type != RTE_FLOW_ACTION_TYPE_INDIRECT) 3453 continue; 3454 if (copied_n == *indir_n) { 3455 return rte_flow_error_set 3456 (error, EINVAL, RTE_FLOW_ERROR_TYPE_ACTION_NUM, 3457 NULL, "too many shared actions"); 3458 } 3459 rte_memcpy(&handle[copied_n].action, &actions[n].conf, 3460 sizeof(actions[n].conf)); 3461 handle[copied_n].index = n; 3462 copied_n++; 3463 } 3464 n++; 3465 *indir_n = copied_n; 3466 if (!copied_n) 3467 return 0; 3468 actions_size = sizeof(struct rte_flow_action) * n; 3469 translated = mlx5_malloc(MLX5_MEM_ZERO, actions_size, 0, SOCKET_ID_ANY); 3470 if (!translated) { 3471 rte_errno = ENOMEM; 3472 return -ENOMEM; 3473 } 3474 memcpy(translated, actions, actions_size); 3475 for (handle_end = handle + copied_n; handle < handle_end; handle++) { 3476 struct mlx5_shared_action_rss *shared_rss; 3477 uint32_t act_idx = (uint32_t)(uintptr_t)handle->action; 3478 uint32_t type = act_idx >> MLX5_INDIRECT_ACTION_TYPE_OFFSET; 3479 uint32_t idx = act_idx & 3480 ((1u << MLX5_INDIRECT_ACTION_TYPE_OFFSET) - 1); 3481 3482 switch (type) { 3483 case MLX5_INDIRECT_ACTION_TYPE_RSS: 3484 shared_rss = mlx5_ipool_get 3485 (priv->sh->ipool[MLX5_IPOOL_RSS_SHARED_ACTIONS], idx); 3486 translated[handle->index].type = 3487 RTE_FLOW_ACTION_TYPE_RSS; 3488 translated[handle->index].conf = 3489 &shared_rss->origin; 3490 break; 3491 case MLX5_INDIRECT_ACTION_TYPE_AGE: 3492 if (priv->sh->flow_hit_aso_en) { 3493 translated[handle->index].type = 3494 (enum rte_flow_action_type) 3495 MLX5_RTE_FLOW_ACTION_TYPE_AGE; 3496 translated[handle->index].conf = 3497 (void *)(uintptr_t)idx; 3498 break; 3499 } 3500 /* Fall-through */ 3501 default: 3502 mlx5_free(translated); 3503 return rte_flow_error_set 3504 (error, EINVAL, RTE_FLOW_ERROR_TYPE_ACTION, 3505 NULL, "invalid indirect action type"); 3506 } 3507 } 3508 *translated_actions = translated; 3509 return 0; 3510 } 3511 3512 /** 3513 * Get Shared RSS action from the action list. 3514 * 3515 * @param[in] dev 3516 * Pointer to Ethernet device. 3517 * @param[in] shared 3518 * Pointer to the list of actions. 3519 * @param[in] shared_n 3520 * Actions list length. 3521 * 3522 * @return 3523 * The MLX5 RSS action ID if exists, otherwise return 0. 3524 */ 3525 static uint32_t 3526 flow_get_shared_rss_action(struct rte_eth_dev *dev, 3527 struct mlx5_translated_action_handle *handle, 3528 int shared_n) 3529 { 3530 struct mlx5_translated_action_handle *handle_end; 3531 struct mlx5_priv *priv = dev->data->dev_private; 3532 struct mlx5_shared_action_rss *shared_rss; 3533 3534 3535 for (handle_end = handle + shared_n; handle < handle_end; handle++) { 3536 uint32_t act_idx = (uint32_t)(uintptr_t)handle->action; 3537 uint32_t type = act_idx >> MLX5_INDIRECT_ACTION_TYPE_OFFSET; 3538 uint32_t idx = act_idx & 3539 ((1u << MLX5_INDIRECT_ACTION_TYPE_OFFSET) - 1); 3540 switch (type) { 3541 case MLX5_INDIRECT_ACTION_TYPE_RSS: 3542 shared_rss = mlx5_ipool_get 3543 (priv->sh->ipool[MLX5_IPOOL_RSS_SHARED_ACTIONS], 3544 idx); 3545 __atomic_add_fetch(&shared_rss->refcnt, 1, 3546 __ATOMIC_RELAXED); 3547 return idx; 3548 default: 3549 break; 3550 } 3551 } 3552 return 0; 3553 } 3554 3555 static unsigned int 3556 find_graph_root(const struct rte_flow_item pattern[], uint32_t rss_level) 3557 { 3558 const struct rte_flow_item *item; 3559 unsigned int has_vlan = 0; 3560 3561 for (item = pattern; item->type != RTE_FLOW_ITEM_TYPE_END; item++) { 3562 if (item->type == RTE_FLOW_ITEM_TYPE_VLAN) { 3563 has_vlan = 1; 3564 break; 3565 } 3566 } 3567 if (has_vlan) 3568 return rss_level < 2 ? MLX5_EXPANSION_ROOT_ETH_VLAN : 3569 MLX5_EXPANSION_ROOT_OUTER_ETH_VLAN; 3570 return rss_level < 2 ? MLX5_EXPANSION_ROOT : 3571 MLX5_EXPANSION_ROOT_OUTER; 3572 } 3573 3574 /** 3575 * Get layer flags from the prefix flow. 3576 * 3577 * Some flows may be split to several subflows, the prefix subflow gets the 3578 * match items and the suffix sub flow gets the actions. 3579 * Some actions need the user defined match item flags to get the detail for 3580 * the action. 3581 * This function helps the suffix flow to get the item layer flags from prefix 3582 * subflow. 3583 * 3584 * @param[in] dev_flow 3585 * Pointer the created preifx subflow. 3586 * 3587 * @return 3588 * The layers get from prefix subflow. 3589 */ 3590 static inline uint64_t 3591 flow_get_prefix_layer_flags(struct mlx5_flow *dev_flow) 3592 { 3593 uint64_t layers = 0; 3594 3595 /* 3596 * Layers bits could be localization, but usually the compiler will 3597 * help to do the optimization work for source code. 3598 * If no decap actions, use the layers directly. 3599 */ 3600 if (!(dev_flow->act_flags & MLX5_FLOW_ACTION_DECAP)) 3601 return dev_flow->handle->layers; 3602 /* Convert L3 layers with decap action. */ 3603 if (dev_flow->handle->layers & MLX5_FLOW_LAYER_INNER_L3_IPV4) 3604 layers |= MLX5_FLOW_LAYER_OUTER_L3_IPV4; 3605 else if (dev_flow->handle->layers & MLX5_FLOW_LAYER_INNER_L3_IPV6) 3606 layers |= MLX5_FLOW_LAYER_OUTER_L3_IPV6; 3607 /* Convert L4 layers with decap action. */ 3608 if (dev_flow->handle->layers & MLX5_FLOW_LAYER_INNER_L4_TCP) 3609 layers |= MLX5_FLOW_LAYER_OUTER_L4_TCP; 3610 else if (dev_flow->handle->layers & MLX5_FLOW_LAYER_INNER_L4_UDP) 3611 layers |= MLX5_FLOW_LAYER_OUTER_L4_UDP; 3612 return layers; 3613 } 3614 3615 /** 3616 * Get metadata split action information. 3617 * 3618 * @param[in] actions 3619 * Pointer to the list of actions. 3620 * @param[out] qrss 3621 * Pointer to the return pointer. 3622 * @param[out] qrss_type 3623 * Pointer to the action type to return. RTE_FLOW_ACTION_TYPE_END is returned 3624 * if no QUEUE/RSS is found. 3625 * @param[out] encap_idx 3626 * Pointer to the index of the encap action if exists, otherwise the last 3627 * action index. 3628 * 3629 * @return 3630 * Total number of actions. 3631 */ 3632 static int 3633 flow_parse_metadata_split_actions_info(const struct rte_flow_action actions[], 3634 const struct rte_flow_action **qrss, 3635 int *encap_idx) 3636 { 3637 const struct rte_flow_action_raw_encap *raw_encap; 3638 int actions_n = 0; 3639 int raw_decap_idx = -1; 3640 3641 *encap_idx = -1; 3642 for (; actions->type != RTE_FLOW_ACTION_TYPE_END; actions++) { 3643 switch (actions->type) { 3644 case RTE_FLOW_ACTION_TYPE_VXLAN_ENCAP: 3645 case RTE_FLOW_ACTION_TYPE_NVGRE_ENCAP: 3646 *encap_idx = actions_n; 3647 break; 3648 case RTE_FLOW_ACTION_TYPE_RAW_DECAP: 3649 raw_decap_idx = actions_n; 3650 break; 3651 case RTE_FLOW_ACTION_TYPE_RAW_ENCAP: 3652 raw_encap = actions->conf; 3653 if (raw_encap->size > MLX5_ENCAPSULATION_DECISION_SIZE) 3654 *encap_idx = raw_decap_idx != -1 ? 3655 raw_decap_idx : actions_n; 3656 break; 3657 case RTE_FLOW_ACTION_TYPE_QUEUE: 3658 case RTE_FLOW_ACTION_TYPE_RSS: 3659 *qrss = actions; 3660 break; 3661 default: 3662 break; 3663 } 3664 actions_n++; 3665 } 3666 if (*encap_idx == -1) 3667 *encap_idx = actions_n; 3668 /* Count RTE_FLOW_ACTION_TYPE_END. */ 3669 return actions_n + 1; 3670 } 3671 3672 /** 3673 * Check meter action from the action list. 3674 * 3675 * @param[in] actions 3676 * Pointer to the list of actions. 3677 * @param[out] mtr 3678 * Pointer to the meter exist flag. 3679 * 3680 * @return 3681 * Total number of actions. 3682 */ 3683 static int 3684 flow_check_meter_action(const struct rte_flow_action actions[], uint32_t *mtr) 3685 { 3686 int actions_n = 0; 3687 3688 MLX5_ASSERT(mtr); 3689 *mtr = 0; 3690 for (; actions->type != RTE_FLOW_ACTION_TYPE_END; actions++) { 3691 switch (actions->type) { 3692 case RTE_FLOW_ACTION_TYPE_METER: 3693 *mtr = 1; 3694 break; 3695 default: 3696 break; 3697 } 3698 actions_n++; 3699 } 3700 /* Count RTE_FLOW_ACTION_TYPE_END. */ 3701 return actions_n + 1; 3702 } 3703 3704 /** 3705 * Check if the flow should be split due to hairpin. 3706 * The reason for the split is that in current HW we can't 3707 * support encap and push-vlan on Rx, so if a flow contains 3708 * these actions we move it to Tx. 3709 * 3710 * @param dev 3711 * Pointer to Ethernet device. 3712 * @param[in] attr 3713 * Flow rule attributes. 3714 * @param[in] actions 3715 * Associated actions (list terminated by the END action). 3716 * 3717 * @return 3718 * > 0 the number of actions and the flow should be split, 3719 * 0 when no split required. 3720 */ 3721 static int 3722 flow_check_hairpin_split(struct rte_eth_dev *dev, 3723 const struct rte_flow_attr *attr, 3724 const struct rte_flow_action actions[]) 3725 { 3726 int queue_action = 0; 3727 int action_n = 0; 3728 int split = 0; 3729 const struct rte_flow_action_queue *queue; 3730 const struct rte_flow_action_rss *rss; 3731 const struct rte_flow_action_raw_encap *raw_encap; 3732 const struct rte_eth_hairpin_conf *conf; 3733 3734 if (!attr->ingress) 3735 return 0; 3736 for (; actions->type != RTE_FLOW_ACTION_TYPE_END; actions++) { 3737 switch (actions->type) { 3738 case RTE_FLOW_ACTION_TYPE_QUEUE: 3739 queue = actions->conf; 3740 if (queue == NULL) 3741 return 0; 3742 conf = mlx5_rxq_get_hairpin_conf(dev, queue->index); 3743 if (conf == NULL || conf->tx_explicit != 0) 3744 return 0; 3745 queue_action = 1; 3746 action_n++; 3747 break; 3748 case RTE_FLOW_ACTION_TYPE_RSS: 3749 rss = actions->conf; 3750 if (rss == NULL || rss->queue_num == 0) 3751 return 0; 3752 conf = mlx5_rxq_get_hairpin_conf(dev, rss->queue[0]); 3753 if (conf == NULL || conf->tx_explicit != 0) 3754 return 0; 3755 queue_action = 1; 3756 action_n++; 3757 break; 3758 case RTE_FLOW_ACTION_TYPE_VXLAN_ENCAP: 3759 case RTE_FLOW_ACTION_TYPE_NVGRE_ENCAP: 3760 case RTE_FLOW_ACTION_TYPE_OF_PUSH_VLAN: 3761 case RTE_FLOW_ACTION_TYPE_OF_SET_VLAN_VID: 3762 case RTE_FLOW_ACTION_TYPE_OF_SET_VLAN_PCP: 3763 split++; 3764 action_n++; 3765 break; 3766 case RTE_FLOW_ACTION_TYPE_RAW_ENCAP: 3767 raw_encap = actions->conf; 3768 if (raw_encap->size > MLX5_ENCAPSULATION_DECISION_SIZE) 3769 split++; 3770 action_n++; 3771 break; 3772 default: 3773 action_n++; 3774 break; 3775 } 3776 } 3777 if (split && queue_action) 3778 return action_n; 3779 return 0; 3780 } 3781 3782 /* Declare flow create/destroy prototype in advance. */ 3783 static uint32_t 3784 flow_list_create(struct rte_eth_dev *dev, uint32_t *list, 3785 const struct rte_flow_attr *attr, 3786 const struct rte_flow_item items[], 3787 const struct rte_flow_action actions[], 3788 bool external, struct rte_flow_error *error); 3789 3790 static void 3791 flow_list_destroy(struct rte_eth_dev *dev, uint32_t *list, 3792 uint32_t flow_idx); 3793 3794 int 3795 flow_dv_mreg_match_cb(struct mlx5_hlist *list __rte_unused, 3796 struct mlx5_hlist_entry *entry, 3797 uint64_t key, void *cb_ctx __rte_unused) 3798 { 3799 struct mlx5_flow_mreg_copy_resource *mcp_res = 3800 container_of(entry, typeof(*mcp_res), hlist_ent); 3801 3802 return mcp_res->mark_id != key; 3803 } 3804 3805 struct mlx5_hlist_entry * 3806 flow_dv_mreg_create_cb(struct mlx5_hlist *list, uint64_t key, 3807 void *cb_ctx) 3808 { 3809 struct rte_eth_dev *dev = list->ctx; 3810 struct mlx5_priv *priv = dev->data->dev_private; 3811 struct mlx5_flow_cb_ctx *ctx = cb_ctx; 3812 struct mlx5_flow_mreg_copy_resource *mcp_res; 3813 struct rte_flow_error *error = ctx->error; 3814 uint32_t idx = 0; 3815 int ret; 3816 uint32_t mark_id = key; 3817 struct rte_flow_attr attr = { 3818 .group = MLX5_FLOW_MREG_CP_TABLE_GROUP, 3819 .ingress = 1, 3820 }; 3821 struct mlx5_rte_flow_item_tag tag_spec = { 3822 .data = mark_id, 3823 }; 3824 struct rte_flow_item items[] = { 3825 [1] = { .type = RTE_FLOW_ITEM_TYPE_END, }, 3826 }; 3827 struct rte_flow_action_mark ftag = { 3828 .id = mark_id, 3829 }; 3830 struct mlx5_flow_action_copy_mreg cp_mreg = { 3831 .dst = REG_B, 3832 .src = REG_NON, 3833 }; 3834 struct rte_flow_action_jump jump = { 3835 .group = MLX5_FLOW_MREG_ACT_TABLE_GROUP, 3836 }; 3837 struct rte_flow_action actions[] = { 3838 [3] = { .type = RTE_FLOW_ACTION_TYPE_END, }, 3839 }; 3840 3841 /* Fill the register fileds in the flow. */ 3842 ret = mlx5_flow_get_reg_id(dev, MLX5_FLOW_MARK, 0, error); 3843 if (ret < 0) 3844 return NULL; 3845 tag_spec.id = ret; 3846 ret = mlx5_flow_get_reg_id(dev, MLX5_METADATA_RX, 0, error); 3847 if (ret < 0) 3848 return NULL; 3849 cp_mreg.src = ret; 3850 /* Provide the full width of FLAG specific value. */ 3851 if (mark_id == (priv->sh->dv_regc0_mask & MLX5_FLOW_MARK_DEFAULT)) 3852 tag_spec.data = MLX5_FLOW_MARK_DEFAULT; 3853 /* Build a new flow. */ 3854 if (mark_id != MLX5_DEFAULT_COPY_ID) { 3855 items[0] = (struct rte_flow_item){ 3856 .type = (enum rte_flow_item_type) 3857 MLX5_RTE_FLOW_ITEM_TYPE_TAG, 3858 .spec = &tag_spec, 3859 }; 3860 items[1] = (struct rte_flow_item){ 3861 .type = RTE_FLOW_ITEM_TYPE_END, 3862 }; 3863 actions[0] = (struct rte_flow_action){ 3864 .type = (enum rte_flow_action_type) 3865 MLX5_RTE_FLOW_ACTION_TYPE_MARK, 3866 .conf = &ftag, 3867 }; 3868 actions[1] = (struct rte_flow_action){ 3869 .type = (enum rte_flow_action_type) 3870 MLX5_RTE_FLOW_ACTION_TYPE_COPY_MREG, 3871 .conf = &cp_mreg, 3872 }; 3873 actions[2] = (struct rte_flow_action){ 3874 .type = RTE_FLOW_ACTION_TYPE_JUMP, 3875 .conf = &jump, 3876 }; 3877 actions[3] = (struct rte_flow_action){ 3878 .type = RTE_FLOW_ACTION_TYPE_END, 3879 }; 3880 } else { 3881 /* Default rule, wildcard match. */ 3882 attr.priority = MLX5_FLOW_LOWEST_PRIO_INDICATOR; 3883 items[0] = (struct rte_flow_item){ 3884 .type = RTE_FLOW_ITEM_TYPE_END, 3885 }; 3886 actions[0] = (struct rte_flow_action){ 3887 .type = (enum rte_flow_action_type) 3888 MLX5_RTE_FLOW_ACTION_TYPE_COPY_MREG, 3889 .conf = &cp_mreg, 3890 }; 3891 actions[1] = (struct rte_flow_action){ 3892 .type = RTE_FLOW_ACTION_TYPE_JUMP, 3893 .conf = &jump, 3894 }; 3895 actions[2] = (struct rte_flow_action){ 3896 .type = RTE_FLOW_ACTION_TYPE_END, 3897 }; 3898 } 3899 /* Build a new entry. */ 3900 mcp_res = mlx5_ipool_zmalloc(priv->sh->ipool[MLX5_IPOOL_MCP], &idx); 3901 if (!mcp_res) { 3902 rte_errno = ENOMEM; 3903 return NULL; 3904 } 3905 mcp_res->idx = idx; 3906 mcp_res->mark_id = mark_id; 3907 /* 3908 * The copy Flows are not included in any list. There 3909 * ones are referenced from other Flows and can not 3910 * be applied, removed, deleted in ardbitrary order 3911 * by list traversing. 3912 */ 3913 mcp_res->rix_flow = flow_list_create(dev, NULL, &attr, items, 3914 actions, false, error); 3915 if (!mcp_res->rix_flow) { 3916 mlx5_ipool_free(priv->sh->ipool[MLX5_IPOOL_MCP], idx); 3917 return NULL; 3918 } 3919 return &mcp_res->hlist_ent; 3920 } 3921 3922 /** 3923 * Add a flow of copying flow metadata registers in RX_CP_TBL. 3924 * 3925 * As mark_id is unique, if there's already a registered flow for the mark_id, 3926 * return by increasing the reference counter of the resource. Otherwise, create 3927 * the resource (mcp_res) and flow. 3928 * 3929 * Flow looks like, 3930 * - If ingress port is ANY and reg_c[1] is mark_id, 3931 * flow_tag := mark_id, reg_b := reg_c[0] and jump to RX_ACT_TBL. 3932 * 3933 * For default flow (zero mark_id), flow is like, 3934 * - If ingress port is ANY, 3935 * reg_b := reg_c[0] and jump to RX_ACT_TBL. 3936 * 3937 * @param dev 3938 * Pointer to Ethernet device. 3939 * @param mark_id 3940 * ID of MARK action, zero means default flow for META. 3941 * @param[out] error 3942 * Perform verbose error reporting if not NULL. 3943 * 3944 * @return 3945 * Associated resource on success, NULL otherwise and rte_errno is set. 3946 */ 3947 static struct mlx5_flow_mreg_copy_resource * 3948 flow_mreg_add_copy_action(struct rte_eth_dev *dev, uint32_t mark_id, 3949 struct rte_flow_error *error) 3950 { 3951 struct mlx5_priv *priv = dev->data->dev_private; 3952 struct mlx5_hlist_entry *entry; 3953 struct mlx5_flow_cb_ctx ctx = { 3954 .dev = dev, 3955 .error = error, 3956 }; 3957 3958 /* Check if already registered. */ 3959 MLX5_ASSERT(priv->mreg_cp_tbl); 3960 entry = mlx5_hlist_register(priv->mreg_cp_tbl, mark_id, &ctx); 3961 if (!entry) 3962 return NULL; 3963 return container_of(entry, struct mlx5_flow_mreg_copy_resource, 3964 hlist_ent); 3965 } 3966 3967 void 3968 flow_dv_mreg_remove_cb(struct mlx5_hlist *list, struct mlx5_hlist_entry *entry) 3969 { 3970 struct mlx5_flow_mreg_copy_resource *mcp_res = 3971 container_of(entry, typeof(*mcp_res), hlist_ent); 3972 struct rte_eth_dev *dev = list->ctx; 3973 struct mlx5_priv *priv = dev->data->dev_private; 3974 3975 MLX5_ASSERT(mcp_res->rix_flow); 3976 flow_list_destroy(dev, NULL, mcp_res->rix_flow); 3977 mlx5_ipool_free(priv->sh->ipool[MLX5_IPOOL_MCP], mcp_res->idx); 3978 } 3979 3980 /** 3981 * Release flow in RX_CP_TBL. 3982 * 3983 * @param dev 3984 * Pointer to Ethernet device. 3985 * @flow 3986 * Parent flow for wich copying is provided. 3987 */ 3988 static void 3989 flow_mreg_del_copy_action(struct rte_eth_dev *dev, 3990 struct rte_flow *flow) 3991 { 3992 struct mlx5_flow_mreg_copy_resource *mcp_res; 3993 struct mlx5_priv *priv = dev->data->dev_private; 3994 3995 if (!flow->rix_mreg_copy) 3996 return; 3997 mcp_res = mlx5_ipool_get(priv->sh->ipool[MLX5_IPOOL_MCP], 3998 flow->rix_mreg_copy); 3999 if (!mcp_res || !priv->mreg_cp_tbl) 4000 return; 4001 MLX5_ASSERT(mcp_res->rix_flow); 4002 mlx5_hlist_unregister(priv->mreg_cp_tbl, &mcp_res->hlist_ent); 4003 flow->rix_mreg_copy = 0; 4004 } 4005 4006 /** 4007 * Remove the default copy action from RX_CP_TBL. 4008 * 4009 * This functions is called in the mlx5_dev_start(). No thread safe 4010 * is guaranteed. 4011 * 4012 * @param dev 4013 * Pointer to Ethernet device. 4014 */ 4015 static void 4016 flow_mreg_del_default_copy_action(struct rte_eth_dev *dev) 4017 { 4018 struct mlx5_hlist_entry *entry; 4019 struct mlx5_priv *priv = dev->data->dev_private; 4020 4021 /* Check if default flow is registered. */ 4022 if (!priv->mreg_cp_tbl) 4023 return; 4024 entry = mlx5_hlist_lookup(priv->mreg_cp_tbl, 4025 MLX5_DEFAULT_COPY_ID, NULL); 4026 if (!entry) 4027 return; 4028 mlx5_hlist_unregister(priv->mreg_cp_tbl, entry); 4029 } 4030 4031 /** 4032 * Add the default copy action in in RX_CP_TBL. 4033 * 4034 * This functions is called in the mlx5_dev_start(). No thread safe 4035 * is guaranteed. 4036 * 4037 * @param dev 4038 * Pointer to Ethernet device. 4039 * @param[out] error 4040 * Perform verbose error reporting if not NULL. 4041 * 4042 * @return 4043 * 0 for success, negative value otherwise and rte_errno is set. 4044 */ 4045 static int 4046 flow_mreg_add_default_copy_action(struct rte_eth_dev *dev, 4047 struct rte_flow_error *error) 4048 { 4049 struct mlx5_priv *priv = dev->data->dev_private; 4050 struct mlx5_flow_mreg_copy_resource *mcp_res; 4051 4052 /* Check whether extensive metadata feature is engaged. */ 4053 if (!priv->config.dv_flow_en || 4054 priv->config.dv_xmeta_en == MLX5_XMETA_MODE_LEGACY || 4055 !mlx5_flow_ext_mreg_supported(dev) || 4056 !priv->sh->dv_regc0_mask) 4057 return 0; 4058 /* 4059 * Add default mreg copy flow may be called multiple time, but 4060 * only be called once in stop. Avoid register it twice. 4061 */ 4062 if (mlx5_hlist_lookup(priv->mreg_cp_tbl, MLX5_DEFAULT_COPY_ID, NULL)) 4063 return 0; 4064 mcp_res = flow_mreg_add_copy_action(dev, MLX5_DEFAULT_COPY_ID, error); 4065 if (!mcp_res) 4066 return -rte_errno; 4067 return 0; 4068 } 4069 4070 /** 4071 * Add a flow of copying flow metadata registers in RX_CP_TBL. 4072 * 4073 * All the flow having Q/RSS action should be split by 4074 * flow_mreg_split_qrss_prep() to pass by RX_CP_TBL. A flow in the RX_CP_TBL 4075 * performs the following, 4076 * - CQE->flow_tag := reg_c[1] (MARK) 4077 * - CQE->flow_table_metadata (reg_b) := reg_c[0] (META) 4078 * As CQE's flow_tag is not a register, it can't be simply copied from reg_c[1] 4079 * but there should be a flow per each MARK ID set by MARK action. 4080 * 4081 * For the aforementioned reason, if there's a MARK action in flow's action 4082 * list, a corresponding flow should be added to the RX_CP_TBL in order to copy 4083 * the MARK ID to CQE's flow_tag like, 4084 * - If reg_c[1] is mark_id, 4085 * flow_tag := mark_id, reg_b := reg_c[0] and jump to RX_ACT_TBL. 4086 * 4087 * For SET_META action which stores value in reg_c[0], as the destination is 4088 * also a flow metadata register (reg_b), adding a default flow is enough. Zero 4089 * MARK ID means the default flow. The default flow looks like, 4090 * - For all flow, reg_b := reg_c[0] and jump to RX_ACT_TBL. 4091 * 4092 * @param dev 4093 * Pointer to Ethernet device. 4094 * @param flow 4095 * Pointer to flow structure. 4096 * @param[in] actions 4097 * Pointer to the list of actions. 4098 * @param[out] error 4099 * Perform verbose error reporting if not NULL. 4100 * 4101 * @return 4102 * 0 on success, negative value otherwise and rte_errno is set. 4103 */ 4104 static int 4105 flow_mreg_update_copy_table(struct rte_eth_dev *dev, 4106 struct rte_flow *flow, 4107 const struct rte_flow_action *actions, 4108 struct rte_flow_error *error) 4109 { 4110 struct mlx5_priv *priv = dev->data->dev_private; 4111 struct mlx5_dev_config *config = &priv->config; 4112 struct mlx5_flow_mreg_copy_resource *mcp_res; 4113 const struct rte_flow_action_mark *mark; 4114 4115 /* Check whether extensive metadata feature is engaged. */ 4116 if (!config->dv_flow_en || 4117 config->dv_xmeta_en == MLX5_XMETA_MODE_LEGACY || 4118 !mlx5_flow_ext_mreg_supported(dev) || 4119 !priv->sh->dv_regc0_mask) 4120 return 0; 4121 /* Find MARK action. */ 4122 for (; actions->type != RTE_FLOW_ACTION_TYPE_END; actions++) { 4123 switch (actions->type) { 4124 case RTE_FLOW_ACTION_TYPE_FLAG: 4125 mcp_res = flow_mreg_add_copy_action 4126 (dev, MLX5_FLOW_MARK_DEFAULT, error); 4127 if (!mcp_res) 4128 return -rte_errno; 4129 flow->rix_mreg_copy = mcp_res->idx; 4130 return 0; 4131 case RTE_FLOW_ACTION_TYPE_MARK: 4132 mark = (const struct rte_flow_action_mark *) 4133 actions->conf; 4134 mcp_res = 4135 flow_mreg_add_copy_action(dev, mark->id, error); 4136 if (!mcp_res) 4137 return -rte_errno; 4138 flow->rix_mreg_copy = mcp_res->idx; 4139 return 0; 4140 default: 4141 break; 4142 } 4143 } 4144 return 0; 4145 } 4146 4147 #define MLX5_MAX_SPLIT_ACTIONS 24 4148 #define MLX5_MAX_SPLIT_ITEMS 24 4149 4150 /** 4151 * Split the hairpin flow. 4152 * Since HW can't support encap and push-vlan on Rx, we move these 4153 * actions to Tx. 4154 * If the count action is after the encap then we also 4155 * move the count action. in this case the count will also measure 4156 * the outer bytes. 4157 * 4158 * @param dev 4159 * Pointer to Ethernet device. 4160 * @param[in] actions 4161 * Associated actions (list terminated by the END action). 4162 * @param[out] actions_rx 4163 * Rx flow actions. 4164 * @param[out] actions_tx 4165 * Tx flow actions.. 4166 * @param[out] pattern_tx 4167 * The pattern items for the Tx flow. 4168 * @param[out] flow_id 4169 * The flow ID connected to this flow. 4170 * 4171 * @return 4172 * 0 on success. 4173 */ 4174 static int 4175 flow_hairpin_split(struct rte_eth_dev *dev, 4176 const struct rte_flow_action actions[], 4177 struct rte_flow_action actions_rx[], 4178 struct rte_flow_action actions_tx[], 4179 struct rte_flow_item pattern_tx[], 4180 uint32_t flow_id) 4181 { 4182 const struct rte_flow_action_raw_encap *raw_encap; 4183 const struct rte_flow_action_raw_decap *raw_decap; 4184 struct mlx5_rte_flow_action_set_tag *set_tag; 4185 struct rte_flow_action *tag_action; 4186 struct mlx5_rte_flow_item_tag *tag_item; 4187 struct rte_flow_item *item; 4188 char *addr; 4189 int encap = 0; 4190 4191 for (; actions->type != RTE_FLOW_ACTION_TYPE_END; actions++) { 4192 switch (actions->type) { 4193 case RTE_FLOW_ACTION_TYPE_VXLAN_ENCAP: 4194 case RTE_FLOW_ACTION_TYPE_NVGRE_ENCAP: 4195 case RTE_FLOW_ACTION_TYPE_OF_PUSH_VLAN: 4196 case RTE_FLOW_ACTION_TYPE_OF_SET_VLAN_VID: 4197 case RTE_FLOW_ACTION_TYPE_OF_SET_VLAN_PCP: 4198 rte_memcpy(actions_tx, actions, 4199 sizeof(struct rte_flow_action)); 4200 actions_tx++; 4201 break; 4202 case RTE_FLOW_ACTION_TYPE_COUNT: 4203 if (encap) { 4204 rte_memcpy(actions_tx, actions, 4205 sizeof(struct rte_flow_action)); 4206 actions_tx++; 4207 } else { 4208 rte_memcpy(actions_rx, actions, 4209 sizeof(struct rte_flow_action)); 4210 actions_rx++; 4211 } 4212 break; 4213 case RTE_FLOW_ACTION_TYPE_RAW_ENCAP: 4214 raw_encap = actions->conf; 4215 if (raw_encap->size > MLX5_ENCAPSULATION_DECISION_SIZE) { 4216 memcpy(actions_tx, actions, 4217 sizeof(struct rte_flow_action)); 4218 actions_tx++; 4219 encap = 1; 4220 } else { 4221 rte_memcpy(actions_rx, actions, 4222 sizeof(struct rte_flow_action)); 4223 actions_rx++; 4224 } 4225 break; 4226 case RTE_FLOW_ACTION_TYPE_RAW_DECAP: 4227 raw_decap = actions->conf; 4228 if (raw_decap->size < MLX5_ENCAPSULATION_DECISION_SIZE) { 4229 memcpy(actions_tx, actions, 4230 sizeof(struct rte_flow_action)); 4231 actions_tx++; 4232 } else { 4233 rte_memcpy(actions_rx, actions, 4234 sizeof(struct rte_flow_action)); 4235 actions_rx++; 4236 } 4237 break; 4238 default: 4239 rte_memcpy(actions_rx, actions, 4240 sizeof(struct rte_flow_action)); 4241 actions_rx++; 4242 break; 4243 } 4244 } 4245 /* Add set meta action and end action for the Rx flow. */ 4246 tag_action = actions_rx; 4247 tag_action->type = (enum rte_flow_action_type) 4248 MLX5_RTE_FLOW_ACTION_TYPE_TAG; 4249 actions_rx++; 4250 rte_memcpy(actions_rx, actions, sizeof(struct rte_flow_action)); 4251 actions_rx++; 4252 set_tag = (void *)actions_rx; 4253 set_tag->id = mlx5_flow_get_reg_id(dev, MLX5_HAIRPIN_RX, 0, NULL); 4254 MLX5_ASSERT(set_tag->id > REG_NON); 4255 set_tag->data = flow_id; 4256 tag_action->conf = set_tag; 4257 /* Create Tx item list. */ 4258 rte_memcpy(actions_tx, actions, sizeof(struct rte_flow_action)); 4259 addr = (void *)&pattern_tx[2]; 4260 item = pattern_tx; 4261 item->type = (enum rte_flow_item_type) 4262 MLX5_RTE_FLOW_ITEM_TYPE_TAG; 4263 tag_item = (void *)addr; 4264 tag_item->data = flow_id; 4265 tag_item->id = mlx5_flow_get_reg_id(dev, MLX5_HAIRPIN_TX, 0, NULL); 4266 MLX5_ASSERT(set_tag->id > REG_NON); 4267 item->spec = tag_item; 4268 addr += sizeof(struct mlx5_rte_flow_item_tag); 4269 tag_item = (void *)addr; 4270 tag_item->data = UINT32_MAX; 4271 tag_item->id = UINT16_MAX; 4272 item->mask = tag_item; 4273 item->last = NULL; 4274 item++; 4275 item->type = RTE_FLOW_ITEM_TYPE_END; 4276 return 0; 4277 } 4278 4279 /** 4280 * The last stage of splitting chain, just creates the subflow 4281 * without any modification. 4282 * 4283 * @param[in] dev 4284 * Pointer to Ethernet device. 4285 * @param[in] flow 4286 * Parent flow structure pointer. 4287 * @param[in, out] sub_flow 4288 * Pointer to return the created subflow, may be NULL. 4289 * @param[in] attr 4290 * Flow rule attributes. 4291 * @param[in] items 4292 * Pattern specification (list terminated by the END pattern item). 4293 * @param[in] actions 4294 * Associated actions (list terminated by the END action). 4295 * @param[in] flow_split_info 4296 * Pointer to flow split info structure. 4297 * @param[out] error 4298 * Perform verbose error reporting if not NULL. 4299 * @return 4300 * 0 on success, negative value otherwise 4301 */ 4302 static int 4303 flow_create_split_inner(struct rte_eth_dev *dev, 4304 struct rte_flow *flow, 4305 struct mlx5_flow **sub_flow, 4306 const struct rte_flow_attr *attr, 4307 const struct rte_flow_item items[], 4308 const struct rte_flow_action actions[], 4309 struct mlx5_flow_split_info *flow_split_info, 4310 struct rte_flow_error *error) 4311 { 4312 struct mlx5_flow *dev_flow; 4313 4314 dev_flow = flow_drv_prepare(dev, flow, attr, items, actions, 4315 flow_split_info->flow_idx, error); 4316 if (!dev_flow) 4317 return -rte_errno; 4318 dev_flow->flow = flow; 4319 dev_flow->external = flow_split_info->external; 4320 dev_flow->skip_scale = flow_split_info->skip_scale; 4321 /* Subflow object was created, we must include one in the list. */ 4322 SILIST_INSERT(&flow->dev_handles, dev_flow->handle_idx, 4323 dev_flow->handle, next); 4324 /* 4325 * If dev_flow is as one of the suffix flow, some actions in suffix 4326 * flow may need some user defined item layer flags, and pass the 4327 * Metadate rxq mark flag to suffix flow as well. 4328 */ 4329 if (flow_split_info->prefix_layers) 4330 dev_flow->handle->layers = flow_split_info->prefix_layers; 4331 if (flow_split_info->prefix_mark) 4332 dev_flow->handle->mark = 1; 4333 if (sub_flow) 4334 *sub_flow = dev_flow; 4335 return flow_drv_translate(dev, dev_flow, attr, items, actions, error); 4336 } 4337 4338 /** 4339 * Split the meter flow. 4340 * 4341 * As meter flow will split to three sub flow, other than meter 4342 * action, the other actions make sense to only meter accepts 4343 * the packet. If it need to be dropped, no other additional 4344 * actions should be take. 4345 * 4346 * One kind of special action which decapsulates the L3 tunnel 4347 * header will be in the prefix sub flow, as not to take the 4348 * L3 tunnel header into account. 4349 * 4350 * @param dev 4351 * Pointer to Ethernet device. 4352 * @param[in] items 4353 * Pattern specification (list terminated by the END pattern item). 4354 * @param[out] sfx_items 4355 * Suffix flow match items (list terminated by the END pattern item). 4356 * @param[in] actions 4357 * Associated actions (list terminated by the END action). 4358 * @param[out] actions_sfx 4359 * Suffix flow actions. 4360 * @param[out] actions_pre 4361 * Prefix flow actions. 4362 * @param[out] pattern_sfx 4363 * The pattern items for the suffix flow. 4364 * @param[out] tag_sfx 4365 * Pointer to suffix flow tag. 4366 * 4367 * @return 4368 * 0 on success. 4369 */ 4370 static int 4371 flow_meter_split_prep(struct rte_eth_dev *dev, 4372 const struct rte_flow_item items[], 4373 struct rte_flow_item sfx_items[], 4374 const struct rte_flow_action actions[], 4375 struct rte_flow_action actions_sfx[], 4376 struct rte_flow_action actions_pre[]) 4377 { 4378 struct mlx5_priv *priv = dev->data->dev_private; 4379 struct rte_flow_action *tag_action = NULL; 4380 struct rte_flow_item *tag_item; 4381 struct mlx5_rte_flow_action_set_tag *set_tag; 4382 struct rte_flow_error error; 4383 const struct rte_flow_action_raw_encap *raw_encap; 4384 const struct rte_flow_action_raw_decap *raw_decap; 4385 struct mlx5_rte_flow_item_tag *tag_spec; 4386 struct mlx5_rte_flow_item_tag *tag_mask; 4387 uint32_t tag_id = 0; 4388 bool copy_vlan = false; 4389 4390 /* Prepare the actions for prefix and suffix flow. */ 4391 for (; actions->type != RTE_FLOW_ACTION_TYPE_END; actions++) { 4392 struct rte_flow_action **action_cur = NULL; 4393 4394 switch (actions->type) { 4395 case RTE_FLOW_ACTION_TYPE_METER: 4396 /* Add the extra tag action first. */ 4397 tag_action = actions_pre; 4398 tag_action->type = (enum rte_flow_action_type) 4399 MLX5_RTE_FLOW_ACTION_TYPE_TAG; 4400 actions_pre++; 4401 action_cur = &actions_pre; 4402 break; 4403 case RTE_FLOW_ACTION_TYPE_VXLAN_DECAP: 4404 case RTE_FLOW_ACTION_TYPE_NVGRE_DECAP: 4405 action_cur = &actions_pre; 4406 break; 4407 case RTE_FLOW_ACTION_TYPE_RAW_ENCAP: 4408 raw_encap = actions->conf; 4409 if (raw_encap->size < MLX5_ENCAPSULATION_DECISION_SIZE) 4410 action_cur = &actions_pre; 4411 break; 4412 case RTE_FLOW_ACTION_TYPE_RAW_DECAP: 4413 raw_decap = actions->conf; 4414 if (raw_decap->size > MLX5_ENCAPSULATION_DECISION_SIZE) 4415 action_cur = &actions_pre; 4416 break; 4417 case RTE_FLOW_ACTION_TYPE_OF_PUSH_VLAN: 4418 case RTE_FLOW_ACTION_TYPE_OF_SET_VLAN_VID: 4419 copy_vlan = true; 4420 break; 4421 default: 4422 break; 4423 } 4424 if (!action_cur) 4425 action_cur = &actions_sfx; 4426 memcpy(*action_cur, actions, sizeof(struct rte_flow_action)); 4427 (*action_cur)++; 4428 } 4429 /* Add end action to the actions. */ 4430 actions_sfx->type = RTE_FLOW_ACTION_TYPE_END; 4431 actions_pre->type = RTE_FLOW_ACTION_TYPE_END; 4432 actions_pre++; 4433 /* Set the tag. */ 4434 set_tag = (void *)actions_pre; 4435 set_tag->id = mlx5_flow_get_reg_id(dev, MLX5_MTR_SFX, 0, &error); 4436 mlx5_ipool_malloc(priv->sh->ipool[MLX5_IPOOL_RSS_EXPANTION_FLOW_ID], 4437 &tag_id); 4438 if (tag_id >= (1 << (sizeof(tag_id) * 8 - MLX5_MTR_COLOR_BITS))) { 4439 DRV_LOG(ERR, "Port %u meter flow id exceed max limit.", 4440 dev->data->port_id); 4441 mlx5_ipool_free(priv->sh->ipool 4442 [MLX5_IPOOL_RSS_EXPANTION_FLOW_ID], tag_id); 4443 return 0; 4444 } else if (!tag_id) { 4445 return 0; 4446 } 4447 set_tag->data = tag_id << MLX5_MTR_COLOR_BITS; 4448 assert(tag_action); 4449 tag_action->conf = set_tag; 4450 /* Prepare the suffix subflow items. */ 4451 tag_item = sfx_items++; 4452 for (; items->type != RTE_FLOW_ITEM_TYPE_END; items++) { 4453 int item_type = items->type; 4454 4455 switch (item_type) { 4456 case RTE_FLOW_ITEM_TYPE_PORT_ID: 4457 memcpy(sfx_items, items, sizeof(*sfx_items)); 4458 sfx_items++; 4459 break; 4460 case RTE_FLOW_ITEM_TYPE_VLAN: 4461 if (copy_vlan) { 4462 memcpy(sfx_items, items, sizeof(*sfx_items)); 4463 /* 4464 * Convert to internal match item, it is used 4465 * for vlan push and set vid. 4466 */ 4467 sfx_items->type = (enum rte_flow_item_type) 4468 MLX5_RTE_FLOW_ITEM_TYPE_VLAN; 4469 sfx_items++; 4470 } 4471 break; 4472 default: 4473 break; 4474 } 4475 } 4476 sfx_items->type = RTE_FLOW_ITEM_TYPE_END; 4477 sfx_items++; 4478 tag_spec = (struct mlx5_rte_flow_item_tag *)sfx_items; 4479 tag_spec->data = tag_id << MLX5_MTR_COLOR_BITS; 4480 tag_spec->id = mlx5_flow_get_reg_id(dev, MLX5_MTR_SFX, 0, &error); 4481 tag_mask = tag_spec + 1; 4482 tag_mask->data = 0xffffff00; 4483 tag_item->type = (enum rte_flow_item_type) 4484 MLX5_RTE_FLOW_ITEM_TYPE_TAG; 4485 tag_item->spec = tag_spec; 4486 tag_item->last = NULL; 4487 tag_item->mask = tag_mask; 4488 return tag_id; 4489 } 4490 4491 /** 4492 * Split action list having QUEUE/RSS for metadata register copy. 4493 * 4494 * Once Q/RSS action is detected in user's action list, the flow action 4495 * should be split in order to copy metadata registers, which will happen in 4496 * RX_CP_TBL like, 4497 * - CQE->flow_tag := reg_c[1] (MARK) 4498 * - CQE->flow_table_metadata (reg_b) := reg_c[0] (META) 4499 * The Q/RSS action will be performed on RX_ACT_TBL after passing by RX_CP_TBL. 4500 * This is because the last action of each flow must be a terminal action 4501 * (QUEUE, RSS or DROP). 4502 * 4503 * Flow ID must be allocated to identify actions in the RX_ACT_TBL and it is 4504 * stored and kept in the mlx5_flow structure per each sub_flow. 4505 * 4506 * The Q/RSS action is replaced with, 4507 * - SET_TAG, setting the allocated flow ID to reg_c[2]. 4508 * And the following JUMP action is added at the end, 4509 * - JUMP, to RX_CP_TBL. 4510 * 4511 * A flow to perform remained Q/RSS action will be created in RX_ACT_TBL by 4512 * flow_create_split_metadata() routine. The flow will look like, 4513 * - If flow ID matches (reg_c[2]), perform Q/RSS. 4514 * 4515 * @param dev 4516 * Pointer to Ethernet device. 4517 * @param[out] split_actions 4518 * Pointer to store split actions to jump to CP_TBL. 4519 * @param[in] actions 4520 * Pointer to the list of original flow actions. 4521 * @param[in] qrss 4522 * Pointer to the Q/RSS action. 4523 * @param[in] actions_n 4524 * Number of original actions. 4525 * @param[out] error 4526 * Perform verbose error reporting if not NULL. 4527 * 4528 * @return 4529 * non-zero unique flow_id on success, otherwise 0 and 4530 * error/rte_error are set. 4531 */ 4532 static uint32_t 4533 flow_mreg_split_qrss_prep(struct rte_eth_dev *dev, 4534 struct rte_flow_action *split_actions, 4535 const struct rte_flow_action *actions, 4536 const struct rte_flow_action *qrss, 4537 int actions_n, struct rte_flow_error *error) 4538 { 4539 struct mlx5_priv *priv = dev->data->dev_private; 4540 struct mlx5_rte_flow_action_set_tag *set_tag; 4541 struct rte_flow_action_jump *jump; 4542 const int qrss_idx = qrss - actions; 4543 uint32_t flow_id = 0; 4544 int ret = 0; 4545 4546 /* 4547 * Given actions will be split 4548 * - Replace QUEUE/RSS action with SET_TAG to set flow ID. 4549 * - Add jump to mreg CP_TBL. 4550 * As a result, there will be one more action. 4551 */ 4552 ++actions_n; 4553 memcpy(split_actions, actions, sizeof(*split_actions) * actions_n); 4554 set_tag = (void *)(split_actions + actions_n); 4555 /* 4556 * If tag action is not set to void(it means we are not the meter 4557 * suffix flow), add the tag action. Since meter suffix flow already 4558 * has the tag added. 4559 */ 4560 if (split_actions[qrss_idx].type != RTE_FLOW_ACTION_TYPE_VOID) { 4561 /* 4562 * Allocate the new subflow ID. This one is unique within 4563 * device and not shared with representors. Otherwise, 4564 * we would have to resolve multi-thread access synch 4565 * issue. Each flow on the shared device is appended 4566 * with source vport identifier, so the resulting 4567 * flows will be unique in the shared (by master and 4568 * representors) domain even if they have coinciding 4569 * IDs. 4570 */ 4571 mlx5_ipool_malloc(priv->sh->ipool 4572 [MLX5_IPOOL_RSS_EXPANTION_FLOW_ID], &flow_id); 4573 if (!flow_id) 4574 return rte_flow_error_set(error, ENOMEM, 4575 RTE_FLOW_ERROR_TYPE_ACTION, 4576 NULL, "can't allocate id " 4577 "for split Q/RSS subflow"); 4578 /* Internal SET_TAG action to set flow ID. */ 4579 *set_tag = (struct mlx5_rte_flow_action_set_tag){ 4580 .data = flow_id, 4581 }; 4582 ret = mlx5_flow_get_reg_id(dev, MLX5_COPY_MARK, 0, error); 4583 if (ret < 0) 4584 return ret; 4585 set_tag->id = ret; 4586 /* Construct new actions array. */ 4587 /* Replace QUEUE/RSS action. */ 4588 split_actions[qrss_idx] = (struct rte_flow_action){ 4589 .type = (enum rte_flow_action_type) 4590 MLX5_RTE_FLOW_ACTION_TYPE_TAG, 4591 .conf = set_tag, 4592 }; 4593 } 4594 /* JUMP action to jump to mreg copy table (CP_TBL). */ 4595 jump = (void *)(set_tag + 1); 4596 *jump = (struct rte_flow_action_jump){ 4597 .group = MLX5_FLOW_MREG_CP_TABLE_GROUP, 4598 }; 4599 split_actions[actions_n - 2] = (struct rte_flow_action){ 4600 .type = RTE_FLOW_ACTION_TYPE_JUMP, 4601 .conf = jump, 4602 }; 4603 split_actions[actions_n - 1] = (struct rte_flow_action){ 4604 .type = RTE_FLOW_ACTION_TYPE_END, 4605 }; 4606 return flow_id; 4607 } 4608 4609 /** 4610 * Extend the given action list for Tx metadata copy. 4611 * 4612 * Copy the given action list to the ext_actions and add flow metadata register 4613 * copy action in order to copy reg_a set by WQE to reg_c[0]. 4614 * 4615 * @param[out] ext_actions 4616 * Pointer to the extended action list. 4617 * @param[in] actions 4618 * Pointer to the list of actions. 4619 * @param[in] actions_n 4620 * Number of actions in the list. 4621 * @param[out] error 4622 * Perform verbose error reporting if not NULL. 4623 * @param[in] encap_idx 4624 * The encap action inndex. 4625 * 4626 * @return 4627 * 0 on success, negative value otherwise 4628 */ 4629 static int 4630 flow_mreg_tx_copy_prep(struct rte_eth_dev *dev, 4631 struct rte_flow_action *ext_actions, 4632 const struct rte_flow_action *actions, 4633 int actions_n, struct rte_flow_error *error, 4634 int encap_idx) 4635 { 4636 struct mlx5_flow_action_copy_mreg *cp_mreg = 4637 (struct mlx5_flow_action_copy_mreg *) 4638 (ext_actions + actions_n + 1); 4639 int ret; 4640 4641 ret = mlx5_flow_get_reg_id(dev, MLX5_METADATA_RX, 0, error); 4642 if (ret < 0) 4643 return ret; 4644 cp_mreg->dst = ret; 4645 ret = mlx5_flow_get_reg_id(dev, MLX5_METADATA_TX, 0, error); 4646 if (ret < 0) 4647 return ret; 4648 cp_mreg->src = ret; 4649 if (encap_idx != 0) 4650 memcpy(ext_actions, actions, sizeof(*ext_actions) * encap_idx); 4651 if (encap_idx == actions_n - 1) { 4652 ext_actions[actions_n - 1] = (struct rte_flow_action){ 4653 .type = (enum rte_flow_action_type) 4654 MLX5_RTE_FLOW_ACTION_TYPE_COPY_MREG, 4655 .conf = cp_mreg, 4656 }; 4657 ext_actions[actions_n] = (struct rte_flow_action){ 4658 .type = RTE_FLOW_ACTION_TYPE_END, 4659 }; 4660 } else { 4661 ext_actions[encap_idx] = (struct rte_flow_action){ 4662 .type = (enum rte_flow_action_type) 4663 MLX5_RTE_FLOW_ACTION_TYPE_COPY_MREG, 4664 .conf = cp_mreg, 4665 }; 4666 memcpy(ext_actions + encap_idx + 1, actions + encap_idx, 4667 sizeof(*ext_actions) * (actions_n - encap_idx)); 4668 } 4669 return 0; 4670 } 4671 4672 /** 4673 * Check the match action from the action list. 4674 * 4675 * @param[in] actions 4676 * Pointer to the list of actions. 4677 * @param[in] attr 4678 * Flow rule attributes. 4679 * @param[in] action 4680 * The action to be check if exist. 4681 * @param[out] match_action_pos 4682 * Pointer to the position of the matched action if exists, otherwise is -1. 4683 * @param[out] qrss_action_pos 4684 * Pointer to the position of the Queue/RSS action if exists, otherwise is -1. 4685 * @param[out] modify_after_mirror 4686 * Pointer to the flag of modify action after FDB mirroring. 4687 * 4688 * @return 4689 * > 0 the total number of actions. 4690 * 0 if not found match action in action list. 4691 */ 4692 static int 4693 flow_check_match_action(const struct rte_flow_action actions[], 4694 const struct rte_flow_attr *attr, 4695 enum rte_flow_action_type action, 4696 int *match_action_pos, int *qrss_action_pos, 4697 int *modify_after_mirror) 4698 { 4699 const struct rte_flow_action_sample *sample; 4700 int actions_n = 0; 4701 uint32_t ratio = 0; 4702 int sub_type = 0; 4703 int flag = 0; 4704 int fdb_mirror = 0; 4705 4706 *match_action_pos = -1; 4707 *qrss_action_pos = -1; 4708 for (; actions->type != RTE_FLOW_ACTION_TYPE_END; actions++) { 4709 if (actions->type == action) { 4710 flag = 1; 4711 *match_action_pos = actions_n; 4712 } 4713 switch (actions->type) { 4714 case RTE_FLOW_ACTION_TYPE_QUEUE: 4715 case RTE_FLOW_ACTION_TYPE_RSS: 4716 *qrss_action_pos = actions_n; 4717 break; 4718 case RTE_FLOW_ACTION_TYPE_SAMPLE: 4719 sample = actions->conf; 4720 ratio = sample->ratio; 4721 sub_type = ((const struct rte_flow_action *) 4722 (sample->actions))->type; 4723 if (ratio == 1 && attr->transfer) 4724 fdb_mirror = 1; 4725 break; 4726 case RTE_FLOW_ACTION_TYPE_SET_MAC_SRC: 4727 case RTE_FLOW_ACTION_TYPE_SET_MAC_DST: 4728 case RTE_FLOW_ACTION_TYPE_SET_IPV4_SRC: 4729 case RTE_FLOW_ACTION_TYPE_SET_IPV4_DST: 4730 case RTE_FLOW_ACTION_TYPE_SET_IPV6_SRC: 4731 case RTE_FLOW_ACTION_TYPE_SET_IPV6_DST: 4732 case RTE_FLOW_ACTION_TYPE_SET_TP_SRC: 4733 case RTE_FLOW_ACTION_TYPE_SET_TP_DST: 4734 case RTE_FLOW_ACTION_TYPE_DEC_TTL: 4735 case RTE_FLOW_ACTION_TYPE_SET_TTL: 4736 case RTE_FLOW_ACTION_TYPE_INC_TCP_SEQ: 4737 case RTE_FLOW_ACTION_TYPE_DEC_TCP_SEQ: 4738 case RTE_FLOW_ACTION_TYPE_INC_TCP_ACK: 4739 case RTE_FLOW_ACTION_TYPE_DEC_TCP_ACK: 4740 case RTE_FLOW_ACTION_TYPE_SET_IPV4_DSCP: 4741 case RTE_FLOW_ACTION_TYPE_SET_IPV6_DSCP: 4742 case RTE_FLOW_ACTION_TYPE_FLAG: 4743 case RTE_FLOW_ACTION_TYPE_MARK: 4744 case RTE_FLOW_ACTION_TYPE_SET_META: 4745 case RTE_FLOW_ACTION_TYPE_SET_TAG: 4746 if (fdb_mirror) 4747 *modify_after_mirror = 1; 4748 break; 4749 default: 4750 break; 4751 } 4752 actions_n++; 4753 } 4754 if (flag && fdb_mirror && !*modify_after_mirror) { 4755 /* FDB mirroring uses the destination array to implement 4756 * instead of FLOW_SAMPLER object. 4757 */ 4758 if (sub_type != RTE_FLOW_ACTION_TYPE_END) 4759 flag = 0; 4760 } 4761 /* Count RTE_FLOW_ACTION_TYPE_END. */ 4762 return flag ? actions_n + 1 : 0; 4763 } 4764 4765 #define SAMPLE_SUFFIX_ITEM 2 4766 4767 /** 4768 * Split the sample flow. 4769 * 4770 * As sample flow will split to two sub flow, sample flow with 4771 * sample action, the other actions will move to new suffix flow. 4772 * 4773 * Also add unique tag id with tag action in the sample flow, 4774 * the same tag id will be as match in the suffix flow. 4775 * 4776 * @param dev 4777 * Pointer to Ethernet device. 4778 * @param[in] add_tag 4779 * Add extra tag action flag. 4780 * @param[out] sfx_items 4781 * Suffix flow match items (list terminated by the END pattern item). 4782 * @param[in] actions 4783 * Associated actions (list terminated by the END action). 4784 * @param[out] actions_sfx 4785 * Suffix flow actions. 4786 * @param[out] actions_pre 4787 * Prefix flow actions. 4788 * @param[in] actions_n 4789 * The total number of actions. 4790 * @param[in] sample_action_pos 4791 * The sample action position. 4792 * @param[in] qrss_action_pos 4793 * The Queue/RSS action position. 4794 * @param[in] jump_table 4795 * Add extra jump action flag. 4796 * @param[out] error 4797 * Perform verbose error reporting if not NULL. 4798 * 4799 * @return 4800 * 0 on success, or unique flow_id, a negative errno value 4801 * otherwise and rte_errno is set. 4802 */ 4803 static int 4804 flow_sample_split_prep(struct rte_eth_dev *dev, 4805 int add_tag, 4806 struct rte_flow_item sfx_items[], 4807 const struct rte_flow_action actions[], 4808 struct rte_flow_action actions_sfx[], 4809 struct rte_flow_action actions_pre[], 4810 int actions_n, 4811 int sample_action_pos, 4812 int qrss_action_pos, 4813 int jump_table, 4814 struct rte_flow_error *error) 4815 { 4816 struct mlx5_priv *priv = dev->data->dev_private; 4817 struct mlx5_rte_flow_action_set_tag *set_tag; 4818 struct mlx5_rte_flow_item_tag *tag_spec; 4819 struct mlx5_rte_flow_item_tag *tag_mask; 4820 struct rte_flow_action_jump *jump_action; 4821 uint32_t tag_id = 0; 4822 int index; 4823 int append_index = 0; 4824 int ret; 4825 4826 if (sample_action_pos < 0) 4827 return rte_flow_error_set(error, EINVAL, 4828 RTE_FLOW_ERROR_TYPE_ACTION, 4829 NULL, "invalid position of sample " 4830 "action in list"); 4831 /* Prepare the actions for prefix and suffix flow. */ 4832 if (qrss_action_pos >= 0 && qrss_action_pos < sample_action_pos) { 4833 index = qrss_action_pos; 4834 /* Put the preceding the Queue/RSS action into prefix flow. */ 4835 if (index != 0) 4836 memcpy(actions_pre, actions, 4837 sizeof(struct rte_flow_action) * index); 4838 /* Put others preceding the sample action into prefix flow. */ 4839 if (sample_action_pos > index + 1) 4840 memcpy(actions_pre + index, actions + index + 1, 4841 sizeof(struct rte_flow_action) * 4842 (sample_action_pos - index - 1)); 4843 index = sample_action_pos - 1; 4844 /* Put Queue/RSS action into Suffix flow. */ 4845 memcpy(actions_sfx, actions + qrss_action_pos, 4846 sizeof(struct rte_flow_action)); 4847 actions_sfx++; 4848 } else { 4849 index = sample_action_pos; 4850 if (index != 0) 4851 memcpy(actions_pre, actions, 4852 sizeof(struct rte_flow_action) * index); 4853 } 4854 /* For CX5, add an extra tag action for NIC-RX and E-Switch ingress. 4855 * For CX6DX and above, metadata registers Cx preserve their value, 4856 * add an extra tag action for NIC-RX and E-Switch Domain. 4857 */ 4858 if (add_tag) { 4859 /* Prepare the prefix tag action. */ 4860 append_index++; 4861 set_tag = (void *)(actions_pre + actions_n + append_index); 4862 ret = mlx5_flow_get_reg_id(dev, MLX5_APP_TAG, 0, error); 4863 if (ret < 0) 4864 return ret; 4865 set_tag->id = ret; 4866 mlx5_ipool_malloc(priv->sh->ipool 4867 [MLX5_IPOOL_RSS_EXPANTION_FLOW_ID], &tag_id); 4868 set_tag->data = tag_id; 4869 /* Prepare the suffix subflow items. */ 4870 tag_spec = (void *)(sfx_items + SAMPLE_SUFFIX_ITEM); 4871 tag_spec->data = tag_id; 4872 tag_spec->id = set_tag->id; 4873 tag_mask = tag_spec + 1; 4874 tag_mask->data = UINT32_MAX; 4875 sfx_items[0] = (struct rte_flow_item){ 4876 .type = (enum rte_flow_item_type) 4877 MLX5_RTE_FLOW_ITEM_TYPE_TAG, 4878 .spec = tag_spec, 4879 .last = NULL, 4880 .mask = tag_mask, 4881 }; 4882 sfx_items[1] = (struct rte_flow_item){ 4883 .type = (enum rte_flow_item_type) 4884 RTE_FLOW_ITEM_TYPE_END, 4885 }; 4886 /* Prepare the tag action in prefix subflow. */ 4887 actions_pre[index++] = 4888 (struct rte_flow_action){ 4889 .type = (enum rte_flow_action_type) 4890 MLX5_RTE_FLOW_ACTION_TYPE_TAG, 4891 .conf = set_tag, 4892 }; 4893 } 4894 memcpy(actions_pre + index, actions + sample_action_pos, 4895 sizeof(struct rte_flow_action)); 4896 index += 1; 4897 /* For the modify action after the sample action in E-Switch mirroring, 4898 * Add the extra jump action in prefix subflow and jump into the next 4899 * table, then do the modify action in the new table. 4900 */ 4901 if (jump_table) { 4902 /* Prepare the prefix jump action. */ 4903 append_index++; 4904 jump_action = (void *)(actions_pre + actions_n + append_index); 4905 jump_action->group = jump_table; 4906 actions_pre[index++] = 4907 (struct rte_flow_action){ 4908 .type = (enum rte_flow_action_type) 4909 RTE_FLOW_ACTION_TYPE_JUMP, 4910 .conf = jump_action, 4911 }; 4912 } 4913 actions_pre[index] = (struct rte_flow_action){ 4914 .type = (enum rte_flow_action_type) 4915 RTE_FLOW_ACTION_TYPE_END, 4916 }; 4917 /* Put the actions after sample into Suffix flow. */ 4918 memcpy(actions_sfx, actions + sample_action_pos + 1, 4919 sizeof(struct rte_flow_action) * 4920 (actions_n - sample_action_pos - 1)); 4921 return tag_id; 4922 } 4923 4924 /** 4925 * The splitting for metadata feature. 4926 * 4927 * - Q/RSS action on NIC Rx should be split in order to pass by 4928 * the mreg copy table (RX_CP_TBL) and then it jumps to the 4929 * action table (RX_ACT_TBL) which has the split Q/RSS action. 4930 * 4931 * - All the actions on NIC Tx should have a mreg copy action to 4932 * copy reg_a from WQE to reg_c[0]. 4933 * 4934 * @param dev 4935 * Pointer to Ethernet device. 4936 * @param[in] flow 4937 * Parent flow structure pointer. 4938 * @param[in] attr 4939 * Flow rule attributes. 4940 * @param[in] items 4941 * Pattern specification (list terminated by the END pattern item). 4942 * @param[in] actions 4943 * Associated actions (list terminated by the END action). 4944 * @param[in] flow_split_info 4945 * Pointer to flow split info structure. 4946 * @param[out] error 4947 * Perform verbose error reporting if not NULL. 4948 * @return 4949 * 0 on success, negative value otherwise 4950 */ 4951 static int 4952 flow_create_split_metadata(struct rte_eth_dev *dev, 4953 struct rte_flow *flow, 4954 const struct rte_flow_attr *attr, 4955 const struct rte_flow_item items[], 4956 const struct rte_flow_action actions[], 4957 struct mlx5_flow_split_info *flow_split_info, 4958 struct rte_flow_error *error) 4959 { 4960 struct mlx5_priv *priv = dev->data->dev_private; 4961 struct mlx5_dev_config *config = &priv->config; 4962 const struct rte_flow_action *qrss = NULL; 4963 struct rte_flow_action *ext_actions = NULL; 4964 struct mlx5_flow *dev_flow = NULL; 4965 uint32_t qrss_id = 0; 4966 int mtr_sfx = 0; 4967 size_t act_size; 4968 int actions_n; 4969 int encap_idx; 4970 int ret; 4971 4972 /* Check whether extensive metadata feature is engaged. */ 4973 if (!config->dv_flow_en || 4974 config->dv_xmeta_en == MLX5_XMETA_MODE_LEGACY || 4975 !mlx5_flow_ext_mreg_supported(dev)) 4976 return flow_create_split_inner(dev, flow, NULL, attr, items, 4977 actions, flow_split_info, error); 4978 actions_n = flow_parse_metadata_split_actions_info(actions, &qrss, 4979 &encap_idx); 4980 if (qrss) { 4981 /* Exclude hairpin flows from splitting. */ 4982 if (qrss->type == RTE_FLOW_ACTION_TYPE_QUEUE) { 4983 const struct rte_flow_action_queue *queue; 4984 4985 queue = qrss->conf; 4986 if (mlx5_rxq_get_type(dev, queue->index) == 4987 MLX5_RXQ_TYPE_HAIRPIN) 4988 qrss = NULL; 4989 } else if (qrss->type == RTE_FLOW_ACTION_TYPE_RSS) { 4990 const struct rte_flow_action_rss *rss; 4991 4992 rss = qrss->conf; 4993 if (mlx5_rxq_get_type(dev, rss->queue[0]) == 4994 MLX5_RXQ_TYPE_HAIRPIN) 4995 qrss = NULL; 4996 } 4997 } 4998 if (qrss) { 4999 /* Check if it is in meter suffix table. */ 5000 mtr_sfx = attr->group == (attr->transfer ? 5001 (MLX5_FLOW_TABLE_LEVEL_SUFFIX - 1) : 5002 MLX5_FLOW_TABLE_LEVEL_SUFFIX); 5003 /* 5004 * Q/RSS action on NIC Rx should be split in order to pass by 5005 * the mreg copy table (RX_CP_TBL) and then it jumps to the 5006 * action table (RX_ACT_TBL) which has the split Q/RSS action. 5007 */ 5008 act_size = sizeof(struct rte_flow_action) * (actions_n + 1) + 5009 sizeof(struct rte_flow_action_set_tag) + 5010 sizeof(struct rte_flow_action_jump); 5011 ext_actions = mlx5_malloc(MLX5_MEM_ZERO, act_size, 0, 5012 SOCKET_ID_ANY); 5013 if (!ext_actions) 5014 return rte_flow_error_set(error, ENOMEM, 5015 RTE_FLOW_ERROR_TYPE_ACTION, 5016 NULL, "no memory to split " 5017 "metadata flow"); 5018 /* 5019 * If we are the suffix flow of meter, tag already exist. 5020 * Set the tag action to void. 5021 */ 5022 if (mtr_sfx) 5023 ext_actions[qrss - actions].type = 5024 RTE_FLOW_ACTION_TYPE_VOID; 5025 else 5026 ext_actions[qrss - actions].type = 5027 (enum rte_flow_action_type) 5028 MLX5_RTE_FLOW_ACTION_TYPE_TAG; 5029 /* 5030 * Create the new actions list with removed Q/RSS action 5031 * and appended set tag and jump to register copy table 5032 * (RX_CP_TBL). We should preallocate unique tag ID here 5033 * in advance, because it is needed for set tag action. 5034 */ 5035 qrss_id = flow_mreg_split_qrss_prep(dev, ext_actions, actions, 5036 qrss, actions_n, error); 5037 if (!mtr_sfx && !qrss_id) { 5038 ret = -rte_errno; 5039 goto exit; 5040 } 5041 } else if (attr->egress && !attr->transfer) { 5042 /* 5043 * All the actions on NIC Tx should have a metadata register 5044 * copy action to copy reg_a from WQE to reg_c[meta] 5045 */ 5046 act_size = sizeof(struct rte_flow_action) * (actions_n + 1) + 5047 sizeof(struct mlx5_flow_action_copy_mreg); 5048 ext_actions = mlx5_malloc(MLX5_MEM_ZERO, act_size, 0, 5049 SOCKET_ID_ANY); 5050 if (!ext_actions) 5051 return rte_flow_error_set(error, ENOMEM, 5052 RTE_FLOW_ERROR_TYPE_ACTION, 5053 NULL, "no memory to split " 5054 "metadata flow"); 5055 /* Create the action list appended with copy register. */ 5056 ret = flow_mreg_tx_copy_prep(dev, ext_actions, actions, 5057 actions_n, error, encap_idx); 5058 if (ret < 0) 5059 goto exit; 5060 } 5061 /* Add the unmodified original or prefix subflow. */ 5062 ret = flow_create_split_inner(dev, flow, &dev_flow, attr, 5063 items, ext_actions ? ext_actions : 5064 actions, flow_split_info, error); 5065 if (ret < 0) 5066 goto exit; 5067 MLX5_ASSERT(dev_flow); 5068 if (qrss) { 5069 const struct rte_flow_attr q_attr = { 5070 .group = MLX5_FLOW_MREG_ACT_TABLE_GROUP, 5071 .ingress = 1, 5072 }; 5073 /* Internal PMD action to set register. */ 5074 struct mlx5_rte_flow_item_tag q_tag_spec = { 5075 .data = qrss_id, 5076 .id = REG_NON, 5077 }; 5078 struct rte_flow_item q_items[] = { 5079 { 5080 .type = (enum rte_flow_item_type) 5081 MLX5_RTE_FLOW_ITEM_TYPE_TAG, 5082 .spec = &q_tag_spec, 5083 .last = NULL, 5084 .mask = NULL, 5085 }, 5086 { 5087 .type = RTE_FLOW_ITEM_TYPE_END, 5088 }, 5089 }; 5090 struct rte_flow_action q_actions[] = { 5091 { 5092 .type = qrss->type, 5093 .conf = qrss->conf, 5094 }, 5095 { 5096 .type = RTE_FLOW_ACTION_TYPE_END, 5097 }, 5098 }; 5099 uint64_t layers = flow_get_prefix_layer_flags(dev_flow); 5100 5101 /* 5102 * Configure the tag item only if there is no meter subflow. 5103 * Since tag is already marked in the meter suffix subflow 5104 * we can just use the meter suffix items as is. 5105 */ 5106 if (qrss_id) { 5107 /* Not meter subflow. */ 5108 MLX5_ASSERT(!mtr_sfx); 5109 /* 5110 * Put unique id in prefix flow due to it is destroyed 5111 * after suffix flow and id will be freed after there 5112 * is no actual flows with this id and identifier 5113 * reallocation becomes possible (for example, for 5114 * other flows in other threads). 5115 */ 5116 dev_flow->handle->split_flow_id = qrss_id; 5117 ret = mlx5_flow_get_reg_id(dev, MLX5_COPY_MARK, 0, 5118 error); 5119 if (ret < 0) 5120 goto exit; 5121 q_tag_spec.id = ret; 5122 } 5123 dev_flow = NULL; 5124 /* Add suffix subflow to execute Q/RSS. */ 5125 flow_split_info->prefix_layers = layers; 5126 flow_split_info->prefix_mark = 0; 5127 ret = flow_create_split_inner(dev, flow, &dev_flow, 5128 &q_attr, mtr_sfx ? items : 5129 q_items, q_actions, 5130 flow_split_info, error); 5131 if (ret < 0) 5132 goto exit; 5133 /* qrss ID should be freed if failed. */ 5134 qrss_id = 0; 5135 MLX5_ASSERT(dev_flow); 5136 } 5137 5138 exit: 5139 /* 5140 * We do not destroy the partially created sub_flows in case of error. 5141 * These ones are included into parent flow list and will be destroyed 5142 * by flow_drv_destroy. 5143 */ 5144 mlx5_ipool_free(priv->sh->ipool[MLX5_IPOOL_RSS_EXPANTION_FLOW_ID], 5145 qrss_id); 5146 mlx5_free(ext_actions); 5147 return ret; 5148 } 5149 5150 /** 5151 * The splitting for meter feature. 5152 * 5153 * - The meter flow will be split to two flows as prefix and 5154 * suffix flow. The packets make sense only it pass the prefix 5155 * meter action. 5156 * 5157 * - Reg_C_5 is used for the packet to match betweend prefix and 5158 * suffix flow. 5159 * 5160 * @param dev 5161 * Pointer to Ethernet device. 5162 * @param[in] flow 5163 * Parent flow structure pointer. 5164 * @param[in] attr 5165 * Flow rule attributes. 5166 * @param[in] items 5167 * Pattern specification (list terminated by the END pattern item). 5168 * @param[in] actions 5169 * Associated actions (list terminated by the END action). 5170 * @param[in] flow_split_info 5171 * Pointer to flow split info structure. 5172 * @param[out] error 5173 * Perform verbose error reporting if not NULL. 5174 * @return 5175 * 0 on success, negative value otherwise 5176 */ 5177 static int 5178 flow_create_split_meter(struct rte_eth_dev *dev, 5179 struct rte_flow *flow, 5180 const struct rte_flow_attr *attr, 5181 const struct rte_flow_item items[], 5182 const struct rte_flow_action actions[], 5183 struct mlx5_flow_split_info *flow_split_info, 5184 struct rte_flow_error *error) 5185 { 5186 struct mlx5_priv *priv = dev->data->dev_private; 5187 struct rte_flow_action *sfx_actions = NULL; 5188 struct rte_flow_action *pre_actions = NULL; 5189 struct rte_flow_item *sfx_items = NULL; 5190 struct mlx5_flow *dev_flow = NULL; 5191 struct rte_flow_attr sfx_attr = *attr; 5192 uint32_t mtr = 0; 5193 uint32_t mtr_tag_id = 0; 5194 size_t act_size; 5195 size_t item_size; 5196 int actions_n = 0; 5197 int ret; 5198 5199 if (priv->mtr_en) 5200 actions_n = flow_check_meter_action(actions, &mtr); 5201 if (mtr) { 5202 /* The five prefix actions: meter, decap, encap, tag, end. */ 5203 act_size = sizeof(struct rte_flow_action) * (actions_n + 5) + 5204 sizeof(struct mlx5_rte_flow_action_set_tag); 5205 /* tag, vlan, port id, end. */ 5206 #define METER_SUFFIX_ITEM 4 5207 item_size = sizeof(struct rte_flow_item) * METER_SUFFIX_ITEM + 5208 sizeof(struct mlx5_rte_flow_item_tag) * 2; 5209 sfx_actions = mlx5_malloc(MLX5_MEM_ZERO, (act_size + item_size), 5210 0, SOCKET_ID_ANY); 5211 if (!sfx_actions) 5212 return rte_flow_error_set(error, ENOMEM, 5213 RTE_FLOW_ERROR_TYPE_ACTION, 5214 NULL, "no memory to split " 5215 "meter flow"); 5216 sfx_items = (struct rte_flow_item *)((char *)sfx_actions + 5217 act_size); 5218 pre_actions = sfx_actions + actions_n; 5219 mtr_tag_id = flow_meter_split_prep(dev, items, sfx_items, 5220 actions, sfx_actions, 5221 pre_actions); 5222 if (!mtr_tag_id) { 5223 ret = -rte_errno; 5224 goto exit; 5225 } 5226 /* Add the prefix subflow. */ 5227 flow_split_info->prefix_mark = 0; 5228 ret = flow_create_split_inner(dev, flow, &dev_flow, 5229 attr, items, pre_actions, 5230 flow_split_info, error); 5231 if (ret) { 5232 ret = -rte_errno; 5233 goto exit; 5234 } 5235 dev_flow->handle->split_flow_id = mtr_tag_id; 5236 /* Setting the sfx group atrr. */ 5237 sfx_attr.group = sfx_attr.transfer ? 5238 (MLX5_FLOW_TABLE_LEVEL_SUFFIX - 1) : 5239 MLX5_FLOW_TABLE_LEVEL_SUFFIX; 5240 flow_split_info->prefix_layers = 5241 flow_get_prefix_layer_flags(dev_flow); 5242 flow_split_info->prefix_mark = dev_flow->handle->mark; 5243 } 5244 /* Add the prefix subflow. */ 5245 ret = flow_create_split_metadata(dev, flow, 5246 &sfx_attr, sfx_items ? 5247 sfx_items : items, 5248 sfx_actions ? sfx_actions : actions, 5249 flow_split_info, error); 5250 exit: 5251 if (sfx_actions) 5252 mlx5_free(sfx_actions); 5253 return ret; 5254 } 5255 5256 /** 5257 * The splitting for sample feature. 5258 * 5259 * Once Sample action is detected in the action list, the flow actions should 5260 * be split into prefix sub flow and suffix sub flow. 5261 * 5262 * The original items remain in the prefix sub flow, all actions preceding the 5263 * sample action and the sample action itself will be copied to the prefix 5264 * sub flow, the actions following the sample action will be copied to the 5265 * suffix sub flow, Queue action always be located in the suffix sub flow. 5266 * 5267 * In order to make the packet from prefix sub flow matches with suffix sub 5268 * flow, an extra tag action be added into prefix sub flow, and the suffix sub 5269 * flow uses tag item with the unique flow id. 5270 * 5271 * @param dev 5272 * Pointer to Ethernet device. 5273 * @param[in] flow 5274 * Parent flow structure pointer. 5275 * @param[in] attr 5276 * Flow rule attributes. 5277 * @param[in] items 5278 * Pattern specification (list terminated by the END pattern item). 5279 * @param[in] actions 5280 * Associated actions (list terminated by the END action). 5281 * @param[in] flow_split_info 5282 * Pointer to flow split info structure. 5283 * @param[out] error 5284 * Perform verbose error reporting if not NULL. 5285 * @return 5286 * 0 on success, negative value otherwise 5287 */ 5288 static int 5289 flow_create_split_sample(struct rte_eth_dev *dev, 5290 struct rte_flow *flow, 5291 const struct rte_flow_attr *attr, 5292 const struct rte_flow_item items[], 5293 const struct rte_flow_action actions[], 5294 struct mlx5_flow_split_info *flow_split_info, 5295 struct rte_flow_error *error) 5296 { 5297 struct mlx5_priv *priv = dev->data->dev_private; 5298 struct rte_flow_action *sfx_actions = NULL; 5299 struct rte_flow_action *pre_actions = NULL; 5300 struct rte_flow_item *sfx_items = NULL; 5301 struct mlx5_flow *dev_flow = NULL; 5302 struct rte_flow_attr sfx_attr = *attr; 5303 #ifdef HAVE_IBV_FLOW_DV_SUPPORT 5304 struct mlx5_flow_dv_sample_resource *sample_res; 5305 struct mlx5_flow_tbl_data_entry *sfx_tbl_data; 5306 struct mlx5_flow_tbl_resource *sfx_tbl; 5307 #endif 5308 size_t act_size; 5309 size_t item_size; 5310 uint32_t fdb_tx = 0; 5311 int32_t tag_id = 0; 5312 int actions_n = 0; 5313 int sample_action_pos; 5314 int qrss_action_pos; 5315 int add_tag = 0; 5316 int modify_after_mirror = 0; 5317 uint16_t jump_table = 0; 5318 const uint32_t next_ft_step = 1; 5319 int ret = 0; 5320 5321 if (priv->sampler_en) 5322 actions_n = flow_check_match_action(actions, attr, 5323 RTE_FLOW_ACTION_TYPE_SAMPLE, 5324 &sample_action_pos, &qrss_action_pos, 5325 &modify_after_mirror); 5326 if (actions_n) { 5327 /* The prefix actions must includes sample, tag, end. */ 5328 act_size = sizeof(struct rte_flow_action) * (actions_n * 2 + 1) 5329 + sizeof(struct mlx5_rte_flow_action_set_tag); 5330 item_size = sizeof(struct rte_flow_item) * SAMPLE_SUFFIX_ITEM + 5331 sizeof(struct mlx5_rte_flow_item_tag) * 2; 5332 sfx_actions = mlx5_malloc(MLX5_MEM_ZERO, (act_size + 5333 item_size), 0, SOCKET_ID_ANY); 5334 if (!sfx_actions) 5335 return rte_flow_error_set(error, ENOMEM, 5336 RTE_FLOW_ERROR_TYPE_ACTION, 5337 NULL, "no memory to split " 5338 "sample flow"); 5339 /* The representor_id is -1 for uplink. */ 5340 fdb_tx = (attr->transfer && priv->representor_id != -1); 5341 /* 5342 * When reg_c_preserve is set, metadata registers Cx preserve 5343 * their value even through packet duplication. 5344 */ 5345 add_tag = (!fdb_tx || priv->config.hca_attr.reg_c_preserve); 5346 if (add_tag) 5347 sfx_items = (struct rte_flow_item *)((char *)sfx_actions 5348 + act_size); 5349 if (modify_after_mirror) 5350 jump_table = attr->group * MLX5_FLOW_TABLE_FACTOR + 5351 next_ft_step; 5352 pre_actions = sfx_actions + actions_n; 5353 tag_id = flow_sample_split_prep(dev, add_tag, sfx_items, 5354 actions, sfx_actions, 5355 pre_actions, actions_n, 5356 sample_action_pos, 5357 qrss_action_pos, jump_table, 5358 error); 5359 if (tag_id < 0 || (add_tag && !tag_id)) { 5360 ret = -rte_errno; 5361 goto exit; 5362 } 5363 if (modify_after_mirror) 5364 flow_split_info->skip_scale = 5365 1 << MLX5_SCALE_JUMP_FLOW_GROUP_BIT; 5366 /* Add the prefix subflow. */ 5367 ret = flow_create_split_inner(dev, flow, &dev_flow, attr, 5368 items, pre_actions, 5369 flow_split_info, error); 5370 if (ret) { 5371 ret = -rte_errno; 5372 goto exit; 5373 } 5374 dev_flow->handle->split_flow_id = tag_id; 5375 #ifdef HAVE_IBV_FLOW_DV_SUPPORT 5376 if (!modify_after_mirror) { 5377 /* Set the sfx group attr. */ 5378 sample_res = (struct mlx5_flow_dv_sample_resource *) 5379 dev_flow->dv.sample_res; 5380 sfx_tbl = (struct mlx5_flow_tbl_resource *) 5381 sample_res->normal_path_tbl; 5382 sfx_tbl_data = container_of(sfx_tbl, 5383 struct mlx5_flow_tbl_data_entry, 5384 tbl); 5385 sfx_attr.group = sfx_attr.transfer ? 5386 (sfx_tbl_data->table_id - 1) : 5387 sfx_tbl_data->table_id; 5388 } else { 5389 MLX5_ASSERT(attr->transfer); 5390 sfx_attr.group = jump_table; 5391 } 5392 flow_split_info->prefix_layers = 5393 flow_get_prefix_layer_flags(dev_flow); 5394 flow_split_info->prefix_mark = dev_flow->handle->mark; 5395 /* Suffix group level already be scaled with factor, set 5396 * MLX5_SCALE_FLOW_GROUP_BIT of skip_scale to 1 to avoid scale 5397 * again in translation. 5398 */ 5399 flow_split_info->skip_scale = 1 << MLX5_SCALE_FLOW_GROUP_BIT; 5400 #endif 5401 } 5402 /* Add the suffix subflow. */ 5403 ret = flow_create_split_meter(dev, flow, &sfx_attr, 5404 sfx_items ? sfx_items : items, 5405 sfx_actions ? sfx_actions : actions, 5406 flow_split_info, error); 5407 exit: 5408 if (sfx_actions) 5409 mlx5_free(sfx_actions); 5410 return ret; 5411 } 5412 5413 /** 5414 * Split the flow to subflow set. The splitters might be linked 5415 * in the chain, like this: 5416 * flow_create_split_outer() calls: 5417 * flow_create_split_meter() calls: 5418 * flow_create_split_metadata(meter_subflow_0) calls: 5419 * flow_create_split_inner(metadata_subflow_0) 5420 * flow_create_split_inner(metadata_subflow_1) 5421 * flow_create_split_inner(metadata_subflow_2) 5422 * flow_create_split_metadata(meter_subflow_1) calls: 5423 * flow_create_split_inner(metadata_subflow_0) 5424 * flow_create_split_inner(metadata_subflow_1) 5425 * flow_create_split_inner(metadata_subflow_2) 5426 * 5427 * This provide flexible way to add new levels of flow splitting. 5428 * The all of successfully created subflows are included to the 5429 * parent flow dev_flow list. 5430 * 5431 * @param dev 5432 * Pointer to Ethernet device. 5433 * @param[in] flow 5434 * Parent flow structure pointer. 5435 * @param[in] attr 5436 * Flow rule attributes. 5437 * @param[in] items 5438 * Pattern specification (list terminated by the END pattern item). 5439 * @param[in] actions 5440 * Associated actions (list terminated by the END action). 5441 * @param[in] flow_split_info 5442 * Pointer to flow split info structure. 5443 * @param[out] error 5444 * Perform verbose error reporting if not NULL. 5445 * @return 5446 * 0 on success, negative value otherwise 5447 */ 5448 static int 5449 flow_create_split_outer(struct rte_eth_dev *dev, 5450 struct rte_flow *flow, 5451 const struct rte_flow_attr *attr, 5452 const struct rte_flow_item items[], 5453 const struct rte_flow_action actions[], 5454 struct mlx5_flow_split_info *flow_split_info, 5455 struct rte_flow_error *error) 5456 { 5457 int ret; 5458 5459 ret = flow_create_split_sample(dev, flow, attr, items, 5460 actions, flow_split_info, error); 5461 MLX5_ASSERT(ret <= 0); 5462 return ret; 5463 } 5464 5465 static struct mlx5_flow_tunnel * 5466 flow_tunnel_from_rule(struct rte_eth_dev *dev, 5467 const struct rte_flow_attr *attr, 5468 const struct rte_flow_item items[], 5469 const struct rte_flow_action actions[]) 5470 { 5471 struct mlx5_flow_tunnel *tunnel; 5472 5473 #pragma GCC diagnostic push 5474 #pragma GCC diagnostic ignored "-Wcast-qual" 5475 if (is_flow_tunnel_match_rule(dev, attr, items, actions)) 5476 tunnel = (struct mlx5_flow_tunnel *)items[0].spec; 5477 else if (is_flow_tunnel_steer_rule(dev, attr, items, actions)) 5478 tunnel = (struct mlx5_flow_tunnel *)actions[0].conf; 5479 else 5480 tunnel = NULL; 5481 #pragma GCC diagnostic pop 5482 5483 return tunnel; 5484 } 5485 5486 /** 5487 * Adjust flow RSS workspace if needed. 5488 * 5489 * @param wks 5490 * Pointer to thread flow work space. 5491 * @param rss_desc 5492 * Pointer to RSS descriptor. 5493 * @param[in] nrssq_num 5494 * New RSS queue number. 5495 * 5496 * @return 5497 * 0 on success, -1 otherwise and rte_errno is set. 5498 */ 5499 static int 5500 flow_rss_workspace_adjust(struct mlx5_flow_workspace *wks, 5501 struct mlx5_flow_rss_desc *rss_desc, 5502 uint32_t nrssq_num) 5503 { 5504 if (likely(nrssq_num <= wks->rssq_num)) 5505 return 0; 5506 rss_desc->queue = realloc(rss_desc->queue, 5507 sizeof(*rss_desc->queue) * RTE_ALIGN(nrssq_num, 2)); 5508 if (!rss_desc->queue) { 5509 rte_errno = ENOMEM; 5510 return -1; 5511 } 5512 wks->rssq_num = RTE_ALIGN(nrssq_num, 2); 5513 return 0; 5514 } 5515 5516 /** 5517 * Create a flow and add it to @p list. 5518 * 5519 * @param dev 5520 * Pointer to Ethernet device. 5521 * @param list 5522 * Pointer to a TAILQ flow list. If this parameter NULL, 5523 * no list insertion occurred, flow is just created, 5524 * this is caller's responsibility to track the 5525 * created flow. 5526 * @param[in] attr 5527 * Flow rule attributes. 5528 * @param[in] items 5529 * Pattern specification (list terminated by the END pattern item). 5530 * @param[in] actions 5531 * Associated actions (list terminated by the END action). 5532 * @param[in] external 5533 * This flow rule is created by request external to PMD. 5534 * @param[out] error 5535 * Perform verbose error reporting if not NULL. 5536 * 5537 * @return 5538 * A flow index on success, 0 otherwise and rte_errno is set. 5539 */ 5540 static uint32_t 5541 flow_list_create(struct rte_eth_dev *dev, uint32_t *list, 5542 const struct rte_flow_attr *attr, 5543 const struct rte_flow_item items[], 5544 const struct rte_flow_action original_actions[], 5545 bool external, struct rte_flow_error *error) 5546 { 5547 struct mlx5_priv *priv = dev->data->dev_private; 5548 struct rte_flow *flow = NULL; 5549 struct mlx5_flow *dev_flow; 5550 const struct rte_flow_action_rss *rss = NULL; 5551 struct mlx5_translated_action_handle 5552 indir_actions[MLX5_MAX_INDIRECT_ACTIONS]; 5553 int indir_actions_n = MLX5_MAX_INDIRECT_ACTIONS; 5554 union { 5555 struct mlx5_flow_expand_rss buf; 5556 uint8_t buffer[2048]; 5557 } expand_buffer; 5558 union { 5559 struct rte_flow_action actions[MLX5_MAX_SPLIT_ACTIONS]; 5560 uint8_t buffer[2048]; 5561 } actions_rx; 5562 union { 5563 struct rte_flow_action actions[MLX5_MAX_SPLIT_ACTIONS]; 5564 uint8_t buffer[2048]; 5565 } actions_hairpin_tx; 5566 union { 5567 struct rte_flow_item items[MLX5_MAX_SPLIT_ITEMS]; 5568 uint8_t buffer[2048]; 5569 } items_tx; 5570 struct mlx5_flow_expand_rss *buf = &expand_buffer.buf; 5571 struct mlx5_flow_rss_desc *rss_desc; 5572 const struct rte_flow_action *p_actions_rx; 5573 uint32_t i; 5574 uint32_t idx = 0; 5575 int hairpin_flow; 5576 struct rte_flow_attr attr_tx = { .priority = 0 }; 5577 const struct rte_flow_action *actions; 5578 struct rte_flow_action *translated_actions = NULL; 5579 struct mlx5_flow_tunnel *tunnel; 5580 struct tunnel_default_miss_ctx default_miss_ctx = { 0, }; 5581 struct mlx5_flow_workspace *wks = mlx5_flow_push_thread_workspace(); 5582 struct mlx5_flow_split_info flow_split_info = { 5583 .external = !!external, 5584 .skip_scale = 0, 5585 .flow_idx = 0, 5586 .prefix_mark = 0, 5587 .prefix_layers = 0 5588 }; 5589 int ret; 5590 5591 MLX5_ASSERT(wks); 5592 rss_desc = &wks->rss_desc; 5593 ret = flow_action_handles_translate(dev, original_actions, 5594 indir_actions, 5595 &indir_actions_n, 5596 &translated_actions, error); 5597 if (ret < 0) { 5598 MLX5_ASSERT(translated_actions == NULL); 5599 return 0; 5600 } 5601 actions = translated_actions ? translated_actions : original_actions; 5602 p_actions_rx = actions; 5603 hairpin_flow = flow_check_hairpin_split(dev, attr, actions); 5604 ret = flow_drv_validate(dev, attr, items, p_actions_rx, 5605 external, hairpin_flow, error); 5606 if (ret < 0) 5607 goto error_before_hairpin_split; 5608 flow = mlx5_ipool_zmalloc(priv->sh->ipool[MLX5_IPOOL_RTE_FLOW], &idx); 5609 if (!flow) { 5610 rte_errno = ENOMEM; 5611 goto error_before_hairpin_split; 5612 } 5613 if (hairpin_flow > 0) { 5614 if (hairpin_flow > MLX5_MAX_SPLIT_ACTIONS) { 5615 rte_errno = EINVAL; 5616 goto error_before_hairpin_split; 5617 } 5618 flow_hairpin_split(dev, actions, actions_rx.actions, 5619 actions_hairpin_tx.actions, items_tx.items, 5620 idx); 5621 p_actions_rx = actions_rx.actions; 5622 } 5623 flow_split_info.flow_idx = idx; 5624 flow->drv_type = flow_get_drv_type(dev, attr); 5625 MLX5_ASSERT(flow->drv_type > MLX5_FLOW_TYPE_MIN && 5626 flow->drv_type < MLX5_FLOW_TYPE_MAX); 5627 memset(rss_desc, 0, offsetof(struct mlx5_flow_rss_desc, queue)); 5628 /* RSS Action only works on NIC RX domain */ 5629 if (attr->ingress && !attr->transfer) 5630 rss = flow_get_rss_action(p_actions_rx); 5631 if (rss) { 5632 if (flow_rss_workspace_adjust(wks, rss_desc, rss->queue_num)) 5633 return 0; 5634 /* 5635 * The following information is required by 5636 * mlx5_flow_hashfields_adjust() in advance. 5637 */ 5638 rss_desc->level = rss->level; 5639 /* RSS type 0 indicates default RSS type (ETH_RSS_IP). */ 5640 rss_desc->types = !rss->types ? ETH_RSS_IP : rss->types; 5641 } 5642 flow->dev_handles = 0; 5643 if (rss && rss->types) { 5644 unsigned int graph_root; 5645 5646 graph_root = find_graph_root(items, rss->level); 5647 ret = mlx5_flow_expand_rss(buf, sizeof(expand_buffer.buffer), 5648 items, rss->types, 5649 mlx5_support_expansion, graph_root); 5650 MLX5_ASSERT(ret > 0 && 5651 (unsigned int)ret < sizeof(expand_buffer.buffer)); 5652 } else { 5653 buf->entries = 1; 5654 buf->entry[0].pattern = (void *)(uintptr_t)items; 5655 } 5656 rss_desc->shared_rss = flow_get_shared_rss_action(dev, indir_actions, 5657 indir_actions_n); 5658 for (i = 0; i < buf->entries; ++i) { 5659 /* Initialize flow split data. */ 5660 flow_split_info.prefix_layers = 0; 5661 flow_split_info.prefix_mark = 0; 5662 flow_split_info.skip_scale = 0; 5663 /* 5664 * The splitter may create multiple dev_flows, 5665 * depending on configuration. In the simplest 5666 * case it just creates unmodified original flow. 5667 */ 5668 ret = flow_create_split_outer(dev, flow, attr, 5669 buf->entry[i].pattern, 5670 p_actions_rx, &flow_split_info, 5671 error); 5672 if (ret < 0) 5673 goto error; 5674 if (is_flow_tunnel_steer_rule(dev, attr, 5675 buf->entry[i].pattern, 5676 p_actions_rx)) { 5677 ret = flow_tunnel_add_default_miss(dev, flow, attr, 5678 p_actions_rx, 5679 idx, 5680 &default_miss_ctx, 5681 error); 5682 if (ret < 0) { 5683 mlx5_free(default_miss_ctx.queue); 5684 goto error; 5685 } 5686 } 5687 } 5688 /* Create the tx flow. */ 5689 if (hairpin_flow) { 5690 attr_tx.group = MLX5_HAIRPIN_TX_TABLE; 5691 attr_tx.ingress = 0; 5692 attr_tx.egress = 1; 5693 dev_flow = flow_drv_prepare(dev, flow, &attr_tx, items_tx.items, 5694 actions_hairpin_tx.actions, 5695 idx, error); 5696 if (!dev_flow) 5697 goto error; 5698 dev_flow->flow = flow; 5699 dev_flow->external = 0; 5700 SILIST_INSERT(&flow->dev_handles, dev_flow->handle_idx, 5701 dev_flow->handle, next); 5702 ret = flow_drv_translate(dev, dev_flow, &attr_tx, 5703 items_tx.items, 5704 actions_hairpin_tx.actions, error); 5705 if (ret < 0) 5706 goto error; 5707 } 5708 /* 5709 * Update the metadata register copy table. If extensive 5710 * metadata feature is enabled and registers are supported 5711 * we might create the extra rte_flow for each unique 5712 * MARK/FLAG action ID. 5713 * 5714 * The table is updated for ingress Flows only, because 5715 * the egress Flows belong to the different device and 5716 * copy table should be updated in peer NIC Rx domain. 5717 */ 5718 if (attr->ingress && 5719 (external || attr->group != MLX5_FLOW_MREG_CP_TABLE_GROUP)) { 5720 ret = flow_mreg_update_copy_table(dev, flow, actions, error); 5721 if (ret) 5722 goto error; 5723 } 5724 /* 5725 * If the flow is external (from application) OR device is started, 5726 * OR mreg discover, then apply immediately. 5727 */ 5728 if (external || dev->data->dev_started || 5729 (attr->group == MLX5_FLOW_MREG_CP_TABLE_GROUP && 5730 attr->priority == MLX5_FLOW_LOWEST_PRIO_INDICATOR)) { 5731 ret = flow_drv_apply(dev, flow, error); 5732 if (ret < 0) 5733 goto error; 5734 } 5735 if (list) { 5736 rte_spinlock_lock(&priv->flow_list_lock); 5737 ILIST_INSERT(priv->sh->ipool[MLX5_IPOOL_RTE_FLOW], list, idx, 5738 flow, next); 5739 rte_spinlock_unlock(&priv->flow_list_lock); 5740 } 5741 flow_rxq_flags_set(dev, flow); 5742 rte_free(translated_actions); 5743 tunnel = flow_tunnel_from_rule(dev, attr, items, actions); 5744 if (tunnel) { 5745 flow->tunnel = 1; 5746 flow->tunnel_id = tunnel->tunnel_id; 5747 __atomic_add_fetch(&tunnel->refctn, 1, __ATOMIC_RELAXED); 5748 mlx5_free(default_miss_ctx.queue); 5749 } 5750 mlx5_flow_pop_thread_workspace(); 5751 return idx; 5752 error: 5753 MLX5_ASSERT(flow); 5754 ret = rte_errno; /* Save rte_errno before cleanup. */ 5755 flow_mreg_del_copy_action(dev, flow); 5756 flow_drv_destroy(dev, flow); 5757 if (rss_desc->shared_rss) 5758 __atomic_sub_fetch(&((struct mlx5_shared_action_rss *) 5759 mlx5_ipool_get 5760 (priv->sh->ipool[MLX5_IPOOL_RSS_SHARED_ACTIONS], 5761 rss_desc->shared_rss))->refcnt, 1, __ATOMIC_RELAXED); 5762 mlx5_ipool_free(priv->sh->ipool[MLX5_IPOOL_RTE_FLOW], idx); 5763 rte_errno = ret; /* Restore rte_errno. */ 5764 ret = rte_errno; 5765 rte_errno = ret; 5766 mlx5_flow_pop_thread_workspace(); 5767 error_before_hairpin_split: 5768 rte_free(translated_actions); 5769 return 0; 5770 } 5771 5772 /** 5773 * Create a dedicated flow rule on e-switch table 0 (root table), to direct all 5774 * incoming packets to table 1. 5775 * 5776 * Other flow rules, requested for group n, will be created in 5777 * e-switch table n+1. 5778 * Jump action to e-switch group n will be created to group n+1. 5779 * 5780 * Used when working in switchdev mode, to utilise advantages of table 1 5781 * and above. 5782 * 5783 * @param dev 5784 * Pointer to Ethernet device. 5785 * 5786 * @return 5787 * Pointer to flow on success, NULL otherwise and rte_errno is set. 5788 */ 5789 struct rte_flow * 5790 mlx5_flow_create_esw_table_zero_flow(struct rte_eth_dev *dev) 5791 { 5792 const struct rte_flow_attr attr = { 5793 .group = 0, 5794 .priority = 0, 5795 .ingress = 1, 5796 .egress = 0, 5797 .transfer = 1, 5798 }; 5799 const struct rte_flow_item pattern = { 5800 .type = RTE_FLOW_ITEM_TYPE_END, 5801 }; 5802 struct rte_flow_action_jump jump = { 5803 .group = 1, 5804 }; 5805 const struct rte_flow_action actions[] = { 5806 { 5807 .type = RTE_FLOW_ACTION_TYPE_JUMP, 5808 .conf = &jump, 5809 }, 5810 { 5811 .type = RTE_FLOW_ACTION_TYPE_END, 5812 }, 5813 }; 5814 struct mlx5_priv *priv = dev->data->dev_private; 5815 struct rte_flow_error error; 5816 5817 return (void *)(uintptr_t)flow_list_create(dev, &priv->ctrl_flows, 5818 &attr, &pattern, 5819 actions, false, &error); 5820 } 5821 5822 /** 5823 * Validate a flow supported by the NIC. 5824 * 5825 * @see rte_flow_validate() 5826 * @see rte_flow_ops 5827 */ 5828 int 5829 mlx5_flow_validate(struct rte_eth_dev *dev, 5830 const struct rte_flow_attr *attr, 5831 const struct rte_flow_item items[], 5832 const struct rte_flow_action original_actions[], 5833 struct rte_flow_error *error) 5834 { 5835 int hairpin_flow; 5836 struct mlx5_translated_action_handle 5837 indir_actions[MLX5_MAX_INDIRECT_ACTIONS]; 5838 int indir_actions_n = MLX5_MAX_INDIRECT_ACTIONS; 5839 const struct rte_flow_action *actions; 5840 struct rte_flow_action *translated_actions = NULL; 5841 int ret = flow_action_handles_translate(dev, original_actions, 5842 indir_actions, 5843 &indir_actions_n, 5844 &translated_actions, error); 5845 5846 if (ret) 5847 return ret; 5848 actions = translated_actions ? translated_actions : original_actions; 5849 hairpin_flow = flow_check_hairpin_split(dev, attr, actions); 5850 ret = flow_drv_validate(dev, attr, items, actions, 5851 true, hairpin_flow, error); 5852 rte_free(translated_actions); 5853 return ret; 5854 } 5855 5856 /** 5857 * Create a flow. 5858 * 5859 * @see rte_flow_create() 5860 * @see rte_flow_ops 5861 */ 5862 struct rte_flow * 5863 mlx5_flow_create(struct rte_eth_dev *dev, 5864 const struct rte_flow_attr *attr, 5865 const struct rte_flow_item items[], 5866 const struct rte_flow_action actions[], 5867 struct rte_flow_error *error) 5868 { 5869 struct mlx5_priv *priv = dev->data->dev_private; 5870 5871 /* 5872 * If the device is not started yet, it is not allowed to created a 5873 * flow from application. PMD default flows and traffic control flows 5874 * are not affected. 5875 */ 5876 if (unlikely(!dev->data->dev_started)) { 5877 DRV_LOG(DEBUG, "port %u is not started when " 5878 "inserting a flow", dev->data->port_id); 5879 rte_flow_error_set(error, ENODEV, 5880 RTE_FLOW_ERROR_TYPE_UNSPECIFIED, 5881 NULL, 5882 "port not started"); 5883 return NULL; 5884 } 5885 5886 return (void *)(uintptr_t)flow_list_create(dev, &priv->flows, 5887 attr, items, actions, true, error); 5888 } 5889 5890 /** 5891 * Destroy a flow in a list. 5892 * 5893 * @param dev 5894 * Pointer to Ethernet device. 5895 * @param list 5896 * Pointer to the Indexed flow list. If this parameter NULL, 5897 * there is no flow removal from the list. Be noted that as 5898 * flow is add to the indexed list, memory of the indexed 5899 * list points to maybe changed as flow destroyed. 5900 * @param[in] flow_idx 5901 * Index of flow to destroy. 5902 */ 5903 static void 5904 flow_list_destroy(struct rte_eth_dev *dev, uint32_t *list, 5905 uint32_t flow_idx) 5906 { 5907 struct mlx5_priv *priv = dev->data->dev_private; 5908 struct rte_flow *flow = mlx5_ipool_get(priv->sh->ipool 5909 [MLX5_IPOOL_RTE_FLOW], flow_idx); 5910 5911 if (!flow) 5912 return; 5913 /* 5914 * Update RX queue flags only if port is started, otherwise it is 5915 * already clean. 5916 */ 5917 if (dev->data->dev_started) 5918 flow_rxq_flags_trim(dev, flow); 5919 flow_drv_destroy(dev, flow); 5920 if (list) { 5921 rte_spinlock_lock(&priv->flow_list_lock); 5922 ILIST_REMOVE(priv->sh->ipool[MLX5_IPOOL_RTE_FLOW], list, 5923 flow_idx, flow, next); 5924 rte_spinlock_unlock(&priv->flow_list_lock); 5925 } 5926 if (flow->tunnel) { 5927 struct mlx5_flow_tunnel *tunnel; 5928 5929 tunnel = mlx5_find_tunnel_id(dev, flow->tunnel_id); 5930 RTE_VERIFY(tunnel); 5931 if (!__atomic_sub_fetch(&tunnel->refctn, 1, __ATOMIC_RELAXED)) 5932 mlx5_flow_tunnel_free(dev, tunnel); 5933 } 5934 flow_mreg_del_copy_action(dev, flow); 5935 mlx5_ipool_free(priv->sh->ipool[MLX5_IPOOL_RTE_FLOW], flow_idx); 5936 } 5937 5938 /** 5939 * Destroy all flows. 5940 * 5941 * @param dev 5942 * Pointer to Ethernet device. 5943 * @param list 5944 * Pointer to the Indexed flow list. 5945 * @param active 5946 * If flushing is called avtively. 5947 */ 5948 void 5949 mlx5_flow_list_flush(struct rte_eth_dev *dev, uint32_t *list, bool active) 5950 { 5951 uint32_t num_flushed = 0; 5952 5953 while (*list) { 5954 flow_list_destroy(dev, list, *list); 5955 num_flushed++; 5956 } 5957 if (active) { 5958 DRV_LOG(INFO, "port %u: %u flows flushed before stopping", 5959 dev->data->port_id, num_flushed); 5960 } 5961 } 5962 5963 /** 5964 * Stop all default actions for flows. 5965 * 5966 * @param dev 5967 * Pointer to Ethernet device. 5968 */ 5969 void 5970 mlx5_flow_stop_default(struct rte_eth_dev *dev) 5971 { 5972 flow_mreg_del_default_copy_action(dev); 5973 flow_rxq_flags_clear(dev); 5974 } 5975 5976 /** 5977 * Start all default actions for flows. 5978 * 5979 * @param dev 5980 * Pointer to Ethernet device. 5981 * @return 5982 * 0 on success, a negative errno value otherwise and rte_errno is set. 5983 */ 5984 int 5985 mlx5_flow_start_default(struct rte_eth_dev *dev) 5986 { 5987 struct rte_flow_error error; 5988 5989 /* Make sure default copy action (reg_c[0] -> reg_b) is created. */ 5990 return flow_mreg_add_default_copy_action(dev, &error); 5991 } 5992 5993 /** 5994 * Release key of thread specific flow workspace data. 5995 */ 5996 void 5997 flow_release_workspace(void *data) 5998 { 5999 struct mlx5_flow_workspace *wks = data; 6000 struct mlx5_flow_workspace *next; 6001 6002 while (wks) { 6003 next = wks->next; 6004 free(wks->rss_desc.queue); 6005 free(wks); 6006 wks = next; 6007 } 6008 } 6009 6010 /** 6011 * Get thread specific current flow workspace. 6012 * 6013 * @return pointer to thread specific flow workspace data, NULL on error. 6014 */ 6015 struct mlx5_flow_workspace* 6016 mlx5_flow_get_thread_workspace(void) 6017 { 6018 struct mlx5_flow_workspace *data; 6019 6020 data = mlx5_flow_os_get_specific_workspace(); 6021 MLX5_ASSERT(data && data->inuse); 6022 if (!data || !data->inuse) 6023 DRV_LOG(ERR, "flow workspace not initialized."); 6024 return data; 6025 } 6026 6027 /** 6028 * Allocate and init new flow workspace. 6029 * 6030 * @return pointer to flow workspace data, NULL on error. 6031 */ 6032 static struct mlx5_flow_workspace* 6033 flow_alloc_thread_workspace(void) 6034 { 6035 struct mlx5_flow_workspace *data = calloc(1, sizeof(*data)); 6036 6037 if (!data) { 6038 DRV_LOG(ERR, "Failed to allocate flow workspace " 6039 "memory."); 6040 return NULL; 6041 } 6042 data->rss_desc.queue = calloc(1, 6043 sizeof(uint16_t) * MLX5_RSSQ_DEFAULT_NUM); 6044 if (!data->rss_desc.queue) 6045 goto err; 6046 data->rssq_num = MLX5_RSSQ_DEFAULT_NUM; 6047 return data; 6048 err: 6049 if (data->rss_desc.queue) 6050 free(data->rss_desc.queue); 6051 free(data); 6052 return NULL; 6053 } 6054 6055 /** 6056 * Get new thread specific flow workspace. 6057 * 6058 * If current workspace inuse, create new one and set as current. 6059 * 6060 * @return pointer to thread specific flow workspace data, NULL on error. 6061 */ 6062 static struct mlx5_flow_workspace* 6063 mlx5_flow_push_thread_workspace(void) 6064 { 6065 struct mlx5_flow_workspace *curr; 6066 struct mlx5_flow_workspace *data; 6067 6068 curr = mlx5_flow_os_get_specific_workspace(); 6069 if (!curr) { 6070 data = flow_alloc_thread_workspace(); 6071 if (!data) 6072 return NULL; 6073 } else if (!curr->inuse) { 6074 data = curr; 6075 } else if (curr->next) { 6076 data = curr->next; 6077 } else { 6078 data = flow_alloc_thread_workspace(); 6079 if (!data) 6080 return NULL; 6081 curr->next = data; 6082 data->prev = curr; 6083 } 6084 data->inuse = 1; 6085 data->flow_idx = 0; 6086 /* Set as current workspace */ 6087 if (mlx5_flow_os_set_specific_workspace(data)) 6088 DRV_LOG(ERR, "Failed to set flow workspace to thread."); 6089 return data; 6090 } 6091 6092 /** 6093 * Close current thread specific flow workspace. 6094 * 6095 * If previous workspace available, set it as current. 6096 * 6097 * @return pointer to thread specific flow workspace data, NULL on error. 6098 */ 6099 static void 6100 mlx5_flow_pop_thread_workspace(void) 6101 { 6102 struct mlx5_flow_workspace *data = mlx5_flow_get_thread_workspace(); 6103 6104 if (!data) 6105 return; 6106 if (!data->inuse) { 6107 DRV_LOG(ERR, "Failed to close unused flow workspace."); 6108 return; 6109 } 6110 data->inuse = 0; 6111 if (!data->prev) 6112 return; 6113 if (mlx5_flow_os_set_specific_workspace(data->prev)) 6114 DRV_LOG(ERR, "Failed to set flow workspace to thread."); 6115 } 6116 6117 /** 6118 * Verify the flow list is empty 6119 * 6120 * @param dev 6121 * Pointer to Ethernet device. 6122 * 6123 * @return the number of flows not released. 6124 */ 6125 int 6126 mlx5_flow_verify(struct rte_eth_dev *dev) 6127 { 6128 struct mlx5_priv *priv = dev->data->dev_private; 6129 struct rte_flow *flow; 6130 uint32_t idx; 6131 int ret = 0; 6132 6133 ILIST_FOREACH(priv->sh->ipool[MLX5_IPOOL_RTE_FLOW], priv->flows, idx, 6134 flow, next) { 6135 DRV_LOG(DEBUG, "port %u flow %p still referenced", 6136 dev->data->port_id, (void *)flow); 6137 ++ret; 6138 } 6139 return ret; 6140 } 6141 6142 /** 6143 * Enable default hairpin egress flow. 6144 * 6145 * @param dev 6146 * Pointer to Ethernet device. 6147 * @param queue 6148 * The queue index. 6149 * 6150 * @return 6151 * 0 on success, a negative errno value otherwise and rte_errno is set. 6152 */ 6153 int 6154 mlx5_ctrl_flow_source_queue(struct rte_eth_dev *dev, 6155 uint32_t queue) 6156 { 6157 struct mlx5_priv *priv = dev->data->dev_private; 6158 const struct rte_flow_attr attr = { 6159 .egress = 1, 6160 .priority = 0, 6161 }; 6162 struct mlx5_rte_flow_item_tx_queue queue_spec = { 6163 .queue = queue, 6164 }; 6165 struct mlx5_rte_flow_item_tx_queue queue_mask = { 6166 .queue = UINT32_MAX, 6167 }; 6168 struct rte_flow_item items[] = { 6169 { 6170 .type = (enum rte_flow_item_type) 6171 MLX5_RTE_FLOW_ITEM_TYPE_TX_QUEUE, 6172 .spec = &queue_spec, 6173 .last = NULL, 6174 .mask = &queue_mask, 6175 }, 6176 { 6177 .type = RTE_FLOW_ITEM_TYPE_END, 6178 }, 6179 }; 6180 struct rte_flow_action_jump jump = { 6181 .group = MLX5_HAIRPIN_TX_TABLE, 6182 }; 6183 struct rte_flow_action actions[2]; 6184 uint32_t flow_idx; 6185 struct rte_flow_error error; 6186 6187 actions[0].type = RTE_FLOW_ACTION_TYPE_JUMP; 6188 actions[0].conf = &jump; 6189 actions[1].type = RTE_FLOW_ACTION_TYPE_END; 6190 flow_idx = flow_list_create(dev, &priv->ctrl_flows, 6191 &attr, items, actions, false, &error); 6192 if (!flow_idx) { 6193 DRV_LOG(DEBUG, 6194 "Failed to create ctrl flow: rte_errno(%d)," 6195 " type(%d), message(%s)", 6196 rte_errno, error.type, 6197 error.message ? error.message : " (no stated reason)"); 6198 return -rte_errno; 6199 } 6200 return 0; 6201 } 6202 6203 /** 6204 * Enable a control flow configured from the control plane. 6205 * 6206 * @param dev 6207 * Pointer to Ethernet device. 6208 * @param eth_spec 6209 * An Ethernet flow spec to apply. 6210 * @param eth_mask 6211 * An Ethernet flow mask to apply. 6212 * @param vlan_spec 6213 * A VLAN flow spec to apply. 6214 * @param vlan_mask 6215 * A VLAN flow mask to apply. 6216 * 6217 * @return 6218 * 0 on success, a negative errno value otherwise and rte_errno is set. 6219 */ 6220 int 6221 mlx5_ctrl_flow_vlan(struct rte_eth_dev *dev, 6222 struct rte_flow_item_eth *eth_spec, 6223 struct rte_flow_item_eth *eth_mask, 6224 struct rte_flow_item_vlan *vlan_spec, 6225 struct rte_flow_item_vlan *vlan_mask) 6226 { 6227 struct mlx5_priv *priv = dev->data->dev_private; 6228 const struct rte_flow_attr attr = { 6229 .ingress = 1, 6230 .priority = MLX5_FLOW_LOWEST_PRIO_INDICATOR, 6231 }; 6232 struct rte_flow_item items[] = { 6233 { 6234 .type = RTE_FLOW_ITEM_TYPE_ETH, 6235 .spec = eth_spec, 6236 .last = NULL, 6237 .mask = eth_mask, 6238 }, 6239 { 6240 .type = (vlan_spec) ? RTE_FLOW_ITEM_TYPE_VLAN : 6241 RTE_FLOW_ITEM_TYPE_END, 6242 .spec = vlan_spec, 6243 .last = NULL, 6244 .mask = vlan_mask, 6245 }, 6246 { 6247 .type = RTE_FLOW_ITEM_TYPE_END, 6248 }, 6249 }; 6250 uint16_t queue[priv->reta_idx_n]; 6251 struct rte_flow_action_rss action_rss = { 6252 .func = RTE_ETH_HASH_FUNCTION_DEFAULT, 6253 .level = 0, 6254 .types = priv->rss_conf.rss_hf, 6255 .key_len = priv->rss_conf.rss_key_len, 6256 .queue_num = priv->reta_idx_n, 6257 .key = priv->rss_conf.rss_key, 6258 .queue = queue, 6259 }; 6260 struct rte_flow_action actions[] = { 6261 { 6262 .type = RTE_FLOW_ACTION_TYPE_RSS, 6263 .conf = &action_rss, 6264 }, 6265 { 6266 .type = RTE_FLOW_ACTION_TYPE_END, 6267 }, 6268 }; 6269 uint32_t flow_idx; 6270 struct rte_flow_error error; 6271 unsigned int i; 6272 6273 if (!priv->reta_idx_n || !priv->rxqs_n) { 6274 return 0; 6275 } 6276 if (!(dev->data->dev_conf.rxmode.mq_mode & ETH_MQ_RX_RSS_FLAG)) 6277 action_rss.types = 0; 6278 for (i = 0; i != priv->reta_idx_n; ++i) 6279 queue[i] = (*priv->reta_idx)[i]; 6280 flow_idx = flow_list_create(dev, &priv->ctrl_flows, 6281 &attr, items, actions, false, &error); 6282 if (!flow_idx) 6283 return -rte_errno; 6284 return 0; 6285 } 6286 6287 /** 6288 * Enable a flow control configured from the control plane. 6289 * 6290 * @param dev 6291 * Pointer to Ethernet device. 6292 * @param eth_spec 6293 * An Ethernet flow spec to apply. 6294 * @param eth_mask 6295 * An Ethernet flow mask to apply. 6296 * 6297 * @return 6298 * 0 on success, a negative errno value otherwise and rte_errno is set. 6299 */ 6300 int 6301 mlx5_ctrl_flow(struct rte_eth_dev *dev, 6302 struct rte_flow_item_eth *eth_spec, 6303 struct rte_flow_item_eth *eth_mask) 6304 { 6305 return mlx5_ctrl_flow_vlan(dev, eth_spec, eth_mask, NULL, NULL); 6306 } 6307 6308 /** 6309 * Create default miss flow rule matching lacp traffic 6310 * 6311 * @param dev 6312 * Pointer to Ethernet device. 6313 * @param eth_spec 6314 * An Ethernet flow spec to apply. 6315 * 6316 * @return 6317 * 0 on success, a negative errno value otherwise and rte_errno is set. 6318 */ 6319 int 6320 mlx5_flow_lacp_miss(struct rte_eth_dev *dev) 6321 { 6322 struct mlx5_priv *priv = dev->data->dev_private; 6323 /* 6324 * The LACP matching is done by only using ether type since using 6325 * a multicast dst mac causes kernel to give low priority to this flow. 6326 */ 6327 static const struct rte_flow_item_eth lacp_spec = { 6328 .type = RTE_BE16(0x8809), 6329 }; 6330 static const struct rte_flow_item_eth lacp_mask = { 6331 .type = 0xffff, 6332 }; 6333 const struct rte_flow_attr attr = { 6334 .ingress = 1, 6335 }; 6336 struct rte_flow_item items[] = { 6337 { 6338 .type = RTE_FLOW_ITEM_TYPE_ETH, 6339 .spec = &lacp_spec, 6340 .mask = &lacp_mask, 6341 }, 6342 { 6343 .type = RTE_FLOW_ITEM_TYPE_END, 6344 }, 6345 }; 6346 struct rte_flow_action actions[] = { 6347 { 6348 .type = (enum rte_flow_action_type) 6349 MLX5_RTE_FLOW_ACTION_TYPE_DEFAULT_MISS, 6350 }, 6351 { 6352 .type = RTE_FLOW_ACTION_TYPE_END, 6353 }, 6354 }; 6355 struct rte_flow_error error; 6356 uint32_t flow_idx = flow_list_create(dev, &priv->ctrl_flows, 6357 &attr, items, actions, false, &error); 6358 6359 if (!flow_idx) 6360 return -rte_errno; 6361 return 0; 6362 } 6363 6364 /** 6365 * Destroy a flow. 6366 * 6367 * @see rte_flow_destroy() 6368 * @see rte_flow_ops 6369 */ 6370 int 6371 mlx5_flow_destroy(struct rte_eth_dev *dev, 6372 struct rte_flow *flow, 6373 struct rte_flow_error *error __rte_unused) 6374 { 6375 struct mlx5_priv *priv = dev->data->dev_private; 6376 6377 flow_list_destroy(dev, &priv->flows, (uintptr_t)(void *)flow); 6378 return 0; 6379 } 6380 6381 /** 6382 * Destroy all flows. 6383 * 6384 * @see rte_flow_flush() 6385 * @see rte_flow_ops 6386 */ 6387 int 6388 mlx5_flow_flush(struct rte_eth_dev *dev, 6389 struct rte_flow_error *error __rte_unused) 6390 { 6391 struct mlx5_priv *priv = dev->data->dev_private; 6392 6393 mlx5_flow_list_flush(dev, &priv->flows, false); 6394 return 0; 6395 } 6396 6397 /** 6398 * Isolated mode. 6399 * 6400 * @see rte_flow_isolate() 6401 * @see rte_flow_ops 6402 */ 6403 int 6404 mlx5_flow_isolate(struct rte_eth_dev *dev, 6405 int enable, 6406 struct rte_flow_error *error) 6407 { 6408 struct mlx5_priv *priv = dev->data->dev_private; 6409 6410 if (dev->data->dev_started) { 6411 rte_flow_error_set(error, EBUSY, 6412 RTE_FLOW_ERROR_TYPE_UNSPECIFIED, 6413 NULL, 6414 "port must be stopped first"); 6415 return -rte_errno; 6416 } 6417 priv->isolated = !!enable; 6418 if (enable) 6419 dev->dev_ops = &mlx5_dev_ops_isolate; 6420 else 6421 dev->dev_ops = &mlx5_dev_ops; 6422 6423 dev->rx_descriptor_status = mlx5_rx_descriptor_status; 6424 dev->tx_descriptor_status = mlx5_tx_descriptor_status; 6425 6426 return 0; 6427 } 6428 6429 /** 6430 * Query a flow. 6431 * 6432 * @see rte_flow_query() 6433 * @see rte_flow_ops 6434 */ 6435 static int 6436 flow_drv_query(struct rte_eth_dev *dev, 6437 uint32_t flow_idx, 6438 const struct rte_flow_action *actions, 6439 void *data, 6440 struct rte_flow_error *error) 6441 { 6442 struct mlx5_priv *priv = dev->data->dev_private; 6443 const struct mlx5_flow_driver_ops *fops; 6444 struct rte_flow *flow = mlx5_ipool_get(priv->sh->ipool 6445 [MLX5_IPOOL_RTE_FLOW], 6446 flow_idx); 6447 enum mlx5_flow_drv_type ftype; 6448 6449 if (!flow) { 6450 return rte_flow_error_set(error, ENOENT, 6451 RTE_FLOW_ERROR_TYPE_UNSPECIFIED, 6452 NULL, 6453 "invalid flow handle"); 6454 } 6455 ftype = flow->drv_type; 6456 MLX5_ASSERT(ftype > MLX5_FLOW_TYPE_MIN && ftype < MLX5_FLOW_TYPE_MAX); 6457 fops = flow_get_drv_ops(ftype); 6458 6459 return fops->query(dev, flow, actions, data, error); 6460 } 6461 6462 /** 6463 * Query a flow. 6464 * 6465 * @see rte_flow_query() 6466 * @see rte_flow_ops 6467 */ 6468 int 6469 mlx5_flow_query(struct rte_eth_dev *dev, 6470 struct rte_flow *flow, 6471 const struct rte_flow_action *actions, 6472 void *data, 6473 struct rte_flow_error *error) 6474 { 6475 int ret; 6476 6477 ret = flow_drv_query(dev, (uintptr_t)(void *)flow, actions, data, 6478 error); 6479 if (ret < 0) 6480 return ret; 6481 return 0; 6482 } 6483 6484 /** 6485 * Get rte_flow callbacks. 6486 * 6487 * @param dev 6488 * Pointer to Ethernet device structure. 6489 * @param ops 6490 * Pointer to operation-specific structure. 6491 * 6492 * @return 0 6493 */ 6494 int 6495 mlx5_flow_ops_get(struct rte_eth_dev *dev __rte_unused, 6496 const struct rte_flow_ops **ops) 6497 { 6498 *ops = &mlx5_flow_ops; 6499 return 0; 6500 } 6501 6502 /** 6503 * Create the needed meter and suffix tables. 6504 * 6505 * @param[in] dev 6506 * Pointer to Ethernet device. 6507 * @param[in] fm 6508 * Pointer to the flow meter. 6509 * 6510 * @return 6511 * Pointer to table set on success, NULL otherwise. 6512 */ 6513 struct mlx5_meter_domains_infos * 6514 mlx5_flow_create_mtr_tbls(struct rte_eth_dev *dev, 6515 const struct mlx5_flow_meter *fm) 6516 { 6517 const struct mlx5_flow_driver_ops *fops; 6518 6519 fops = flow_get_drv_ops(MLX5_FLOW_TYPE_DV); 6520 return fops->create_mtr_tbls(dev, fm); 6521 } 6522 6523 /** 6524 * Destroy the meter table set. 6525 * 6526 * @param[in] dev 6527 * Pointer to Ethernet device. 6528 * @param[in] tbl 6529 * Pointer to the meter table set. 6530 * 6531 * @return 6532 * 0 on success. 6533 */ 6534 int 6535 mlx5_flow_destroy_mtr_tbls(struct rte_eth_dev *dev, 6536 struct mlx5_meter_domains_infos *tbls) 6537 { 6538 const struct mlx5_flow_driver_ops *fops; 6539 6540 fops = flow_get_drv_ops(MLX5_FLOW_TYPE_DV); 6541 return fops->destroy_mtr_tbls(dev, tbls); 6542 } 6543 6544 /** 6545 * Create policer rules. 6546 * 6547 * @param[in] dev 6548 * Pointer to Ethernet device. 6549 * @param[in] fm 6550 * Pointer to flow meter structure. 6551 * @param[in] attr 6552 * Pointer to flow attributes. 6553 * 6554 * @return 6555 * 0 on success, -1 otherwise. 6556 */ 6557 int 6558 mlx5_flow_create_policer_rules(struct rte_eth_dev *dev, 6559 struct mlx5_flow_meter *fm, 6560 const struct rte_flow_attr *attr) 6561 { 6562 const struct mlx5_flow_driver_ops *fops; 6563 6564 fops = flow_get_drv_ops(MLX5_FLOW_TYPE_DV); 6565 return fops->create_policer_rules(dev, fm, attr); 6566 } 6567 6568 /** 6569 * Destroy policer rules. 6570 * 6571 * @param[in] fm 6572 * Pointer to flow meter structure. 6573 * @param[in] attr 6574 * Pointer to flow attributes. 6575 * 6576 * @return 6577 * 0 on success, -1 otherwise. 6578 */ 6579 int 6580 mlx5_flow_destroy_policer_rules(struct rte_eth_dev *dev, 6581 struct mlx5_flow_meter *fm, 6582 const struct rte_flow_attr *attr) 6583 { 6584 const struct mlx5_flow_driver_ops *fops; 6585 6586 fops = flow_get_drv_ops(MLX5_FLOW_TYPE_DV); 6587 return fops->destroy_policer_rules(dev, fm, attr); 6588 } 6589 6590 /** 6591 * Allocate a counter. 6592 * 6593 * @param[in] dev 6594 * Pointer to Ethernet device structure. 6595 * 6596 * @return 6597 * Index to allocated counter on success, 0 otherwise. 6598 */ 6599 uint32_t 6600 mlx5_counter_alloc(struct rte_eth_dev *dev) 6601 { 6602 const struct mlx5_flow_driver_ops *fops; 6603 struct rte_flow_attr attr = { .transfer = 0 }; 6604 6605 if (flow_get_drv_type(dev, &attr) == MLX5_FLOW_TYPE_DV) { 6606 fops = flow_get_drv_ops(MLX5_FLOW_TYPE_DV); 6607 return fops->counter_alloc(dev); 6608 } 6609 DRV_LOG(ERR, 6610 "port %u counter allocate is not supported.", 6611 dev->data->port_id); 6612 return 0; 6613 } 6614 6615 /** 6616 * Free a counter. 6617 * 6618 * @param[in] dev 6619 * Pointer to Ethernet device structure. 6620 * @param[in] cnt 6621 * Index to counter to be free. 6622 */ 6623 void 6624 mlx5_counter_free(struct rte_eth_dev *dev, uint32_t cnt) 6625 { 6626 const struct mlx5_flow_driver_ops *fops; 6627 struct rte_flow_attr attr = { .transfer = 0 }; 6628 6629 if (flow_get_drv_type(dev, &attr) == MLX5_FLOW_TYPE_DV) { 6630 fops = flow_get_drv_ops(MLX5_FLOW_TYPE_DV); 6631 fops->counter_free(dev, cnt); 6632 return; 6633 } 6634 DRV_LOG(ERR, 6635 "port %u counter free is not supported.", 6636 dev->data->port_id); 6637 } 6638 6639 /** 6640 * Query counter statistics. 6641 * 6642 * @param[in] dev 6643 * Pointer to Ethernet device structure. 6644 * @param[in] cnt 6645 * Index to counter to query. 6646 * @param[in] clear 6647 * Set to clear counter statistics. 6648 * @param[out] pkts 6649 * The counter hits packets number to save. 6650 * @param[out] bytes 6651 * The counter hits bytes number to save. 6652 * 6653 * @return 6654 * 0 on success, a negative errno value otherwise. 6655 */ 6656 int 6657 mlx5_counter_query(struct rte_eth_dev *dev, uint32_t cnt, 6658 bool clear, uint64_t *pkts, uint64_t *bytes) 6659 { 6660 const struct mlx5_flow_driver_ops *fops; 6661 struct rte_flow_attr attr = { .transfer = 0 }; 6662 6663 if (flow_get_drv_type(dev, &attr) == MLX5_FLOW_TYPE_DV) { 6664 fops = flow_get_drv_ops(MLX5_FLOW_TYPE_DV); 6665 return fops->counter_query(dev, cnt, clear, pkts, bytes); 6666 } 6667 DRV_LOG(ERR, 6668 "port %u counter query is not supported.", 6669 dev->data->port_id); 6670 return -ENOTSUP; 6671 } 6672 6673 /** 6674 * Allocate a new memory for the counter values wrapped by all the needed 6675 * management. 6676 * 6677 * @param[in] sh 6678 * Pointer to mlx5_dev_ctx_shared object. 6679 * 6680 * @return 6681 * 0 on success, a negative errno value otherwise. 6682 */ 6683 static int 6684 mlx5_flow_create_counter_stat_mem_mng(struct mlx5_dev_ctx_shared *sh) 6685 { 6686 struct mlx5_devx_mkey_attr mkey_attr; 6687 struct mlx5_counter_stats_mem_mng *mem_mng; 6688 volatile struct flow_counter_stats *raw_data; 6689 int raws_n = MLX5_CNT_CONTAINER_RESIZE + MLX5_MAX_PENDING_QUERIES; 6690 int size = (sizeof(struct flow_counter_stats) * 6691 MLX5_COUNTERS_PER_POOL + 6692 sizeof(struct mlx5_counter_stats_raw)) * raws_n + 6693 sizeof(struct mlx5_counter_stats_mem_mng); 6694 size_t pgsize = rte_mem_page_size(); 6695 uint8_t *mem; 6696 int i; 6697 6698 if (pgsize == (size_t)-1) { 6699 DRV_LOG(ERR, "Failed to get mem page size"); 6700 rte_errno = ENOMEM; 6701 return -ENOMEM; 6702 } 6703 mem = mlx5_malloc(MLX5_MEM_ZERO, size, pgsize, SOCKET_ID_ANY); 6704 if (!mem) { 6705 rte_errno = ENOMEM; 6706 return -ENOMEM; 6707 } 6708 mem_mng = (struct mlx5_counter_stats_mem_mng *)(mem + size) - 1; 6709 size = sizeof(*raw_data) * MLX5_COUNTERS_PER_POOL * raws_n; 6710 mem_mng->umem = mlx5_os_umem_reg(sh->ctx, mem, size, 6711 IBV_ACCESS_LOCAL_WRITE); 6712 if (!mem_mng->umem) { 6713 rte_errno = errno; 6714 mlx5_free(mem); 6715 return -rte_errno; 6716 } 6717 mkey_attr.addr = (uintptr_t)mem; 6718 mkey_attr.size = size; 6719 mkey_attr.umem_id = mlx5_os_get_umem_id(mem_mng->umem); 6720 mkey_attr.pd = sh->pdn; 6721 mkey_attr.log_entity_size = 0; 6722 mkey_attr.pg_access = 0; 6723 mkey_attr.klm_array = NULL; 6724 mkey_attr.klm_num = 0; 6725 mkey_attr.relaxed_ordering_write = sh->cmng.relaxed_ordering_write; 6726 mkey_attr.relaxed_ordering_read = sh->cmng.relaxed_ordering_read; 6727 mem_mng->dm = mlx5_devx_cmd_mkey_create(sh->ctx, &mkey_attr); 6728 if (!mem_mng->dm) { 6729 mlx5_os_umem_dereg(mem_mng->umem); 6730 rte_errno = errno; 6731 mlx5_free(mem); 6732 return -rte_errno; 6733 } 6734 mem_mng->raws = (struct mlx5_counter_stats_raw *)(mem + size); 6735 raw_data = (volatile struct flow_counter_stats *)mem; 6736 for (i = 0; i < raws_n; ++i) { 6737 mem_mng->raws[i].mem_mng = mem_mng; 6738 mem_mng->raws[i].data = raw_data + i * MLX5_COUNTERS_PER_POOL; 6739 } 6740 for (i = 0; i < MLX5_MAX_PENDING_QUERIES; ++i) 6741 LIST_INSERT_HEAD(&sh->cmng.free_stat_raws, 6742 mem_mng->raws + MLX5_CNT_CONTAINER_RESIZE + i, 6743 next); 6744 LIST_INSERT_HEAD(&sh->cmng.mem_mngs, mem_mng, next); 6745 sh->cmng.mem_mng = mem_mng; 6746 return 0; 6747 } 6748 6749 /** 6750 * Set the statistic memory to the new counter pool. 6751 * 6752 * @param[in] sh 6753 * Pointer to mlx5_dev_ctx_shared object. 6754 * @param[in] pool 6755 * Pointer to the pool to set the statistic memory. 6756 * 6757 * @return 6758 * 0 on success, a negative errno value otherwise. 6759 */ 6760 static int 6761 mlx5_flow_set_counter_stat_mem(struct mlx5_dev_ctx_shared *sh, 6762 struct mlx5_flow_counter_pool *pool) 6763 { 6764 struct mlx5_flow_counter_mng *cmng = &sh->cmng; 6765 /* Resize statistic memory once used out. */ 6766 if (!(pool->index % MLX5_CNT_CONTAINER_RESIZE) && 6767 mlx5_flow_create_counter_stat_mem_mng(sh)) { 6768 DRV_LOG(ERR, "Cannot resize counter stat mem."); 6769 return -1; 6770 } 6771 rte_spinlock_lock(&pool->sl); 6772 pool->raw = cmng->mem_mng->raws + pool->index % 6773 MLX5_CNT_CONTAINER_RESIZE; 6774 rte_spinlock_unlock(&pool->sl); 6775 pool->raw_hw = NULL; 6776 return 0; 6777 } 6778 6779 #define MLX5_POOL_QUERY_FREQ_US 1000000 6780 6781 /** 6782 * Set the periodic procedure for triggering asynchronous batch queries for all 6783 * the counter pools. 6784 * 6785 * @param[in] sh 6786 * Pointer to mlx5_dev_ctx_shared object. 6787 */ 6788 void 6789 mlx5_set_query_alarm(struct mlx5_dev_ctx_shared *sh) 6790 { 6791 uint32_t pools_n, us; 6792 6793 pools_n = __atomic_load_n(&sh->cmng.n_valid, __ATOMIC_RELAXED); 6794 us = MLX5_POOL_QUERY_FREQ_US / pools_n; 6795 DRV_LOG(DEBUG, "Set alarm for %u pools each %u us", pools_n, us); 6796 if (rte_eal_alarm_set(us, mlx5_flow_query_alarm, sh)) { 6797 sh->cmng.query_thread_on = 0; 6798 DRV_LOG(ERR, "Cannot reinitialize query alarm"); 6799 } else { 6800 sh->cmng.query_thread_on = 1; 6801 } 6802 } 6803 6804 /** 6805 * The periodic procedure for triggering asynchronous batch queries for all the 6806 * counter pools. This function is probably called by the host thread. 6807 * 6808 * @param[in] arg 6809 * The parameter for the alarm process. 6810 */ 6811 void 6812 mlx5_flow_query_alarm(void *arg) 6813 { 6814 struct mlx5_dev_ctx_shared *sh = arg; 6815 int ret; 6816 uint16_t pool_index = sh->cmng.pool_index; 6817 struct mlx5_flow_counter_mng *cmng = &sh->cmng; 6818 struct mlx5_flow_counter_pool *pool; 6819 uint16_t n_valid; 6820 6821 if (sh->cmng.pending_queries >= MLX5_MAX_PENDING_QUERIES) 6822 goto set_alarm; 6823 rte_spinlock_lock(&cmng->pool_update_sl); 6824 pool = cmng->pools[pool_index]; 6825 n_valid = cmng->n_valid; 6826 rte_spinlock_unlock(&cmng->pool_update_sl); 6827 /* Set the statistic memory to the new created pool. */ 6828 if ((!pool->raw && mlx5_flow_set_counter_stat_mem(sh, pool))) 6829 goto set_alarm; 6830 if (pool->raw_hw) 6831 /* There is a pool query in progress. */ 6832 goto set_alarm; 6833 pool->raw_hw = 6834 LIST_FIRST(&sh->cmng.free_stat_raws); 6835 if (!pool->raw_hw) 6836 /* No free counter statistics raw memory. */ 6837 goto set_alarm; 6838 /* 6839 * Identify the counters released between query trigger and query 6840 * handle more efficiently. The counter released in this gap period 6841 * should wait for a new round of query as the new arrived packets 6842 * will not be taken into account. 6843 */ 6844 pool->query_gen++; 6845 ret = mlx5_devx_cmd_flow_counter_query(pool->min_dcs, 0, 6846 MLX5_COUNTERS_PER_POOL, 6847 NULL, NULL, 6848 pool->raw_hw->mem_mng->dm->id, 6849 (void *)(uintptr_t) 6850 pool->raw_hw->data, 6851 sh->devx_comp, 6852 (uint64_t)(uintptr_t)pool); 6853 if (ret) { 6854 DRV_LOG(ERR, "Failed to trigger asynchronous query for dcs ID" 6855 " %d", pool->min_dcs->id); 6856 pool->raw_hw = NULL; 6857 goto set_alarm; 6858 } 6859 LIST_REMOVE(pool->raw_hw, next); 6860 sh->cmng.pending_queries++; 6861 pool_index++; 6862 if (pool_index >= n_valid) 6863 pool_index = 0; 6864 set_alarm: 6865 sh->cmng.pool_index = pool_index; 6866 mlx5_set_query_alarm(sh); 6867 } 6868 6869 /** 6870 * Check and callback event for new aged flow in the counter pool 6871 * 6872 * @param[in] sh 6873 * Pointer to mlx5_dev_ctx_shared object. 6874 * @param[in] pool 6875 * Pointer to Current counter pool. 6876 */ 6877 static void 6878 mlx5_flow_aging_check(struct mlx5_dev_ctx_shared *sh, 6879 struct mlx5_flow_counter_pool *pool) 6880 { 6881 struct mlx5_priv *priv; 6882 struct mlx5_flow_counter *cnt; 6883 struct mlx5_age_info *age_info; 6884 struct mlx5_age_param *age_param; 6885 struct mlx5_counter_stats_raw *cur = pool->raw_hw; 6886 struct mlx5_counter_stats_raw *prev = pool->raw; 6887 const uint64_t curr_time = MLX5_CURR_TIME_SEC; 6888 const uint32_t time_delta = curr_time - pool->time_of_last_age_check; 6889 uint16_t expected = AGE_CANDIDATE; 6890 uint32_t i; 6891 6892 pool->time_of_last_age_check = curr_time; 6893 for (i = 0; i < MLX5_COUNTERS_PER_POOL; ++i) { 6894 cnt = MLX5_POOL_GET_CNT(pool, i); 6895 age_param = MLX5_CNT_TO_AGE(cnt); 6896 if (__atomic_load_n(&age_param->state, 6897 __ATOMIC_RELAXED) != AGE_CANDIDATE) 6898 continue; 6899 if (cur->data[i].hits != prev->data[i].hits) { 6900 __atomic_store_n(&age_param->sec_since_last_hit, 0, 6901 __ATOMIC_RELAXED); 6902 continue; 6903 } 6904 if (__atomic_add_fetch(&age_param->sec_since_last_hit, 6905 time_delta, 6906 __ATOMIC_RELAXED) <= age_param->timeout) 6907 continue; 6908 /** 6909 * Hold the lock first, or if between the 6910 * state AGE_TMOUT and tailq operation the 6911 * release happened, the release procedure 6912 * may delete a non-existent tailq node. 6913 */ 6914 priv = rte_eth_devices[age_param->port_id].data->dev_private; 6915 age_info = GET_PORT_AGE_INFO(priv); 6916 rte_spinlock_lock(&age_info->aged_sl); 6917 if (__atomic_compare_exchange_n(&age_param->state, &expected, 6918 AGE_TMOUT, false, 6919 __ATOMIC_RELAXED, 6920 __ATOMIC_RELAXED)) { 6921 TAILQ_INSERT_TAIL(&age_info->aged_counters, cnt, next); 6922 MLX5_AGE_SET(age_info, MLX5_AGE_EVENT_NEW); 6923 } 6924 rte_spinlock_unlock(&age_info->aged_sl); 6925 } 6926 mlx5_age_event_prepare(sh); 6927 } 6928 6929 /** 6930 * Handler for the HW respond about ready values from an asynchronous batch 6931 * query. This function is probably called by the host thread. 6932 * 6933 * @param[in] sh 6934 * The pointer to the shared device context. 6935 * @param[in] async_id 6936 * The Devx async ID. 6937 * @param[in] status 6938 * The status of the completion. 6939 */ 6940 void 6941 mlx5_flow_async_pool_query_handle(struct mlx5_dev_ctx_shared *sh, 6942 uint64_t async_id, int status) 6943 { 6944 struct mlx5_flow_counter_pool *pool = 6945 (struct mlx5_flow_counter_pool *)(uintptr_t)async_id; 6946 struct mlx5_counter_stats_raw *raw_to_free; 6947 uint8_t query_gen = pool->query_gen ^ 1; 6948 struct mlx5_flow_counter_mng *cmng = &sh->cmng; 6949 enum mlx5_counter_type cnt_type = 6950 pool->is_aged ? MLX5_COUNTER_TYPE_AGE : 6951 MLX5_COUNTER_TYPE_ORIGIN; 6952 6953 if (unlikely(status)) { 6954 raw_to_free = pool->raw_hw; 6955 } else { 6956 raw_to_free = pool->raw; 6957 if (pool->is_aged) 6958 mlx5_flow_aging_check(sh, pool); 6959 rte_spinlock_lock(&pool->sl); 6960 pool->raw = pool->raw_hw; 6961 rte_spinlock_unlock(&pool->sl); 6962 /* Be sure the new raw counters data is updated in memory. */ 6963 rte_io_wmb(); 6964 if (!TAILQ_EMPTY(&pool->counters[query_gen])) { 6965 rte_spinlock_lock(&cmng->csl[cnt_type]); 6966 TAILQ_CONCAT(&cmng->counters[cnt_type], 6967 &pool->counters[query_gen], next); 6968 rte_spinlock_unlock(&cmng->csl[cnt_type]); 6969 } 6970 } 6971 LIST_INSERT_HEAD(&sh->cmng.free_stat_raws, raw_to_free, next); 6972 pool->raw_hw = NULL; 6973 sh->cmng.pending_queries--; 6974 } 6975 6976 static int 6977 flow_group_to_table(uint32_t port_id, uint32_t group, uint32_t *table, 6978 const struct flow_grp_info *grp_info, 6979 struct rte_flow_error *error) 6980 { 6981 if (grp_info->transfer && grp_info->external && 6982 grp_info->fdb_def_rule) { 6983 if (group == UINT32_MAX) 6984 return rte_flow_error_set 6985 (error, EINVAL, 6986 RTE_FLOW_ERROR_TYPE_ATTR_GROUP, 6987 NULL, 6988 "group index not supported"); 6989 *table = group + 1; 6990 } else { 6991 *table = group; 6992 } 6993 DRV_LOG(DEBUG, "port %u group=%#x table=%#x", port_id, group, *table); 6994 return 0; 6995 } 6996 6997 /** 6998 * Translate the rte_flow group index to HW table value. 6999 * 7000 * If tunnel offload is disabled, all group ids converted to flow table 7001 * id using the standard method. 7002 * If tunnel offload is enabled, group id can be converted using the 7003 * standard or tunnel conversion method. Group conversion method 7004 * selection depends on flags in `grp_info` parameter: 7005 * - Internal (grp_info.external == 0) groups conversion uses the 7006 * standard method. 7007 * - Group ids in JUMP action converted with the tunnel conversion. 7008 * - Group id in rule attribute conversion depends on a rule type and 7009 * group id value: 7010 * ** non zero group attributes converted with the tunnel method 7011 * ** zero group attribute in non-tunnel rule is converted using the 7012 * standard method - there's only one root table 7013 * ** zero group attribute in steer tunnel rule is converted with the 7014 * standard method - single root table 7015 * ** zero group attribute in match tunnel rule is a special OvS 7016 * case: that value is used for portability reasons. That group 7017 * id is converted with the tunnel conversion method. 7018 * 7019 * @param[in] dev 7020 * Port device 7021 * @param[in] tunnel 7022 * PMD tunnel offload object 7023 * @param[in] group 7024 * rte_flow group index value. 7025 * @param[out] table 7026 * HW table value. 7027 * @param[in] grp_info 7028 * flags used for conversion 7029 * @param[out] error 7030 * Pointer to error structure. 7031 * 7032 * @return 7033 * 0 on success, a negative errno value otherwise and rte_errno is set. 7034 */ 7035 int 7036 mlx5_flow_group_to_table(struct rte_eth_dev *dev, 7037 const struct mlx5_flow_tunnel *tunnel, 7038 uint32_t group, uint32_t *table, 7039 const struct flow_grp_info *grp_info, 7040 struct rte_flow_error *error) 7041 { 7042 int ret; 7043 bool standard_translation; 7044 7045 if (!grp_info->skip_scale && grp_info->external && 7046 group < MLX5_MAX_TABLES_EXTERNAL) 7047 group *= MLX5_FLOW_TABLE_FACTOR; 7048 if (is_tunnel_offload_active(dev)) { 7049 standard_translation = !grp_info->external || 7050 grp_info->std_tbl_fix; 7051 } else { 7052 standard_translation = true; 7053 } 7054 DRV_LOG(DEBUG, 7055 "port %u group=%u transfer=%d external=%d fdb_def_rule=%d translate=%s", 7056 dev->data->port_id, group, grp_info->transfer, 7057 grp_info->external, grp_info->fdb_def_rule, 7058 standard_translation ? "STANDARD" : "TUNNEL"); 7059 if (standard_translation) 7060 ret = flow_group_to_table(dev->data->port_id, group, table, 7061 grp_info, error); 7062 else 7063 ret = tunnel_flow_group_to_flow_table(dev, tunnel, group, 7064 table, error); 7065 7066 return ret; 7067 } 7068 7069 /** 7070 * Discover availability of metadata reg_c's. 7071 * 7072 * Iteratively use test flows to check availability. 7073 * 7074 * @param[in] dev 7075 * Pointer to the Ethernet device structure. 7076 * 7077 * @return 7078 * 0 on success, a negative errno value otherwise and rte_errno is set. 7079 */ 7080 int 7081 mlx5_flow_discover_mreg_c(struct rte_eth_dev *dev) 7082 { 7083 struct mlx5_priv *priv = dev->data->dev_private; 7084 struct mlx5_dev_config *config = &priv->config; 7085 enum modify_reg idx; 7086 int n = 0; 7087 7088 /* reg_c[0] and reg_c[1] are reserved. */ 7089 config->flow_mreg_c[n++] = REG_C_0; 7090 config->flow_mreg_c[n++] = REG_C_1; 7091 /* Discover availability of other reg_c's. */ 7092 for (idx = REG_C_2; idx <= REG_C_7; ++idx) { 7093 struct rte_flow_attr attr = { 7094 .group = MLX5_FLOW_MREG_CP_TABLE_GROUP, 7095 .priority = MLX5_FLOW_LOWEST_PRIO_INDICATOR, 7096 .ingress = 1, 7097 }; 7098 struct rte_flow_item items[] = { 7099 [0] = { 7100 .type = RTE_FLOW_ITEM_TYPE_END, 7101 }, 7102 }; 7103 struct rte_flow_action actions[] = { 7104 [0] = { 7105 .type = (enum rte_flow_action_type) 7106 MLX5_RTE_FLOW_ACTION_TYPE_COPY_MREG, 7107 .conf = &(struct mlx5_flow_action_copy_mreg){ 7108 .src = REG_C_1, 7109 .dst = idx, 7110 }, 7111 }, 7112 [1] = { 7113 .type = RTE_FLOW_ACTION_TYPE_JUMP, 7114 .conf = &(struct rte_flow_action_jump){ 7115 .group = MLX5_FLOW_MREG_ACT_TABLE_GROUP, 7116 }, 7117 }, 7118 [2] = { 7119 .type = RTE_FLOW_ACTION_TYPE_END, 7120 }, 7121 }; 7122 uint32_t flow_idx; 7123 struct rte_flow *flow; 7124 struct rte_flow_error error; 7125 7126 if (!config->dv_flow_en) 7127 break; 7128 /* Create internal flow, validation skips copy action. */ 7129 flow_idx = flow_list_create(dev, NULL, &attr, items, 7130 actions, false, &error); 7131 flow = mlx5_ipool_get(priv->sh->ipool[MLX5_IPOOL_RTE_FLOW], 7132 flow_idx); 7133 if (!flow) 7134 continue; 7135 config->flow_mreg_c[n++] = idx; 7136 flow_list_destroy(dev, NULL, flow_idx); 7137 } 7138 for (; n < MLX5_MREG_C_NUM; ++n) 7139 config->flow_mreg_c[n] = REG_NON; 7140 return 0; 7141 } 7142 7143 /** 7144 * Dump flow raw hw data to file 7145 * 7146 * @param[in] dev 7147 * The pointer to Ethernet device. 7148 * @param[in] file 7149 * A pointer to a file for output. 7150 * @param[out] error 7151 * Perform verbose error reporting if not NULL. PMDs initialize this 7152 * structure in case of error only. 7153 * @return 7154 * 0 on success, a nagative value otherwise. 7155 */ 7156 int 7157 mlx5_flow_dev_dump(struct rte_eth_dev *dev, struct rte_flow *flow_idx, 7158 FILE *file, 7159 struct rte_flow_error *error __rte_unused) 7160 { 7161 struct mlx5_priv *priv = dev->data->dev_private; 7162 struct mlx5_dev_ctx_shared *sh = priv->sh; 7163 7164 if (!priv->config.dv_flow_en) { 7165 if (fputs("device dv flow disabled\n", file) <= 0) 7166 return -errno; 7167 return -ENOTSUP; 7168 } 7169 7170 if (!flow_idx) 7171 return mlx5_devx_cmd_flow_dump(sh->fdb_domain, 7172 sh->rx_domain, sh->tx_domain, file); 7173 return -ENOTSUP; 7174 } 7175 7176 /** 7177 * Get aged-out flows. 7178 * 7179 * @param[in] dev 7180 * Pointer to the Ethernet device structure. 7181 * @param[in] context 7182 * The address of an array of pointers to the aged-out flows contexts. 7183 * @param[in] nb_countexts 7184 * The length of context array pointers. 7185 * @param[out] error 7186 * Perform verbose error reporting if not NULL. Initialized in case of 7187 * error only. 7188 * 7189 * @return 7190 * how many contexts get in success, otherwise negative errno value. 7191 * if nb_contexts is 0, return the amount of all aged contexts. 7192 * if nb_contexts is not 0 , return the amount of aged flows reported 7193 * in the context array. 7194 */ 7195 int 7196 mlx5_flow_get_aged_flows(struct rte_eth_dev *dev, void **contexts, 7197 uint32_t nb_contexts, struct rte_flow_error *error) 7198 { 7199 const struct mlx5_flow_driver_ops *fops; 7200 struct rte_flow_attr attr = { .transfer = 0 }; 7201 7202 if (flow_get_drv_type(dev, &attr) == MLX5_FLOW_TYPE_DV) { 7203 fops = flow_get_drv_ops(MLX5_FLOW_TYPE_DV); 7204 return fops->get_aged_flows(dev, contexts, nb_contexts, 7205 error); 7206 } 7207 DRV_LOG(ERR, 7208 "port %u get aged flows is not supported.", 7209 dev->data->port_id); 7210 return -ENOTSUP; 7211 } 7212 7213 /* Wrapper for driver action_validate op callback */ 7214 static int 7215 flow_drv_action_validate(struct rte_eth_dev *dev, 7216 const struct rte_flow_indir_action_conf *conf, 7217 const struct rte_flow_action *action, 7218 const struct mlx5_flow_driver_ops *fops, 7219 struct rte_flow_error *error) 7220 { 7221 static const char err_msg[] = "indirect action validation unsupported"; 7222 7223 if (!fops->action_validate) { 7224 DRV_LOG(ERR, "port %u %s.", dev->data->port_id, err_msg); 7225 rte_flow_error_set(error, ENOTSUP, RTE_FLOW_ERROR_TYPE_ACTION, 7226 NULL, err_msg); 7227 return -rte_errno; 7228 } 7229 return fops->action_validate(dev, conf, action, error); 7230 } 7231 7232 /** 7233 * Destroys the shared action by handle. 7234 * 7235 * @param dev 7236 * Pointer to Ethernet device structure. 7237 * @param[in] handle 7238 * Handle for the indirect action object to be destroyed. 7239 * @param[out] error 7240 * Perform verbose error reporting if not NULL. PMDs initialize this 7241 * structure in case of error only. 7242 * 7243 * @return 7244 * 0 on success, a negative errno value otherwise and rte_errno is set. 7245 * 7246 * @note: wrapper for driver action_create op callback. 7247 */ 7248 static int 7249 mlx5_action_handle_destroy(struct rte_eth_dev *dev, 7250 struct rte_flow_action_handle *handle, 7251 struct rte_flow_error *error) 7252 { 7253 static const char err_msg[] = "indirect action destruction unsupported"; 7254 struct rte_flow_attr attr = { .transfer = 0 }; 7255 const struct mlx5_flow_driver_ops *fops = 7256 flow_get_drv_ops(flow_get_drv_type(dev, &attr)); 7257 7258 if (!fops->action_destroy) { 7259 DRV_LOG(ERR, "port %u %s.", dev->data->port_id, err_msg); 7260 rte_flow_error_set(error, ENOTSUP, RTE_FLOW_ERROR_TYPE_ACTION, 7261 NULL, err_msg); 7262 return -rte_errno; 7263 } 7264 return fops->action_destroy(dev, handle, error); 7265 } 7266 7267 /* Wrapper for driver action_destroy op callback */ 7268 static int 7269 flow_drv_action_update(struct rte_eth_dev *dev, 7270 struct rte_flow_action_handle *handle, 7271 const void *update, 7272 const struct mlx5_flow_driver_ops *fops, 7273 struct rte_flow_error *error) 7274 { 7275 static const char err_msg[] = "indirect action update unsupported"; 7276 7277 if (!fops->action_update) { 7278 DRV_LOG(ERR, "port %u %s.", dev->data->port_id, err_msg); 7279 rte_flow_error_set(error, ENOTSUP, RTE_FLOW_ERROR_TYPE_ACTION, 7280 NULL, err_msg); 7281 return -rte_errno; 7282 } 7283 return fops->action_update(dev, handle, update, error); 7284 } 7285 7286 /* Wrapper for driver action_destroy op callback */ 7287 static int 7288 flow_drv_action_query(struct rte_eth_dev *dev, 7289 const struct rte_flow_action_handle *handle, 7290 void *data, 7291 const struct mlx5_flow_driver_ops *fops, 7292 struct rte_flow_error *error) 7293 { 7294 static const char err_msg[] = "indirect action query unsupported"; 7295 7296 if (!fops->action_query) { 7297 DRV_LOG(ERR, "port %u %s.", dev->data->port_id, err_msg); 7298 rte_flow_error_set(error, ENOTSUP, RTE_FLOW_ERROR_TYPE_ACTION, 7299 NULL, err_msg); 7300 return -rte_errno; 7301 } 7302 return fops->action_query(dev, handle, data, error); 7303 } 7304 7305 /** 7306 * Create indirect action for reuse in multiple flow rules. 7307 * 7308 * @param dev 7309 * Pointer to Ethernet device structure. 7310 * @param conf 7311 * Pointer to indirect action object configuration. 7312 * @param[in] action 7313 * Action configuration for indirect action object creation. 7314 * @param[out] error 7315 * Perform verbose error reporting if not NULL. PMDs initialize this 7316 * structure in case of error only. 7317 * @return 7318 * A valid handle in case of success, NULL otherwise and rte_errno is set. 7319 */ 7320 static struct rte_flow_action_handle * 7321 mlx5_action_handle_create(struct rte_eth_dev *dev, 7322 const struct rte_flow_indir_action_conf *conf, 7323 const struct rte_flow_action *action, 7324 struct rte_flow_error *error) 7325 { 7326 static const char err_msg[] = "indirect action creation unsupported"; 7327 struct rte_flow_attr attr = { .transfer = 0 }; 7328 const struct mlx5_flow_driver_ops *fops = 7329 flow_get_drv_ops(flow_get_drv_type(dev, &attr)); 7330 7331 if (flow_drv_action_validate(dev, conf, action, fops, error)) 7332 return NULL; 7333 if (!fops->action_create) { 7334 DRV_LOG(ERR, "port %u %s.", dev->data->port_id, err_msg); 7335 rte_flow_error_set(error, ENOTSUP, RTE_FLOW_ERROR_TYPE_ACTION, 7336 NULL, err_msg); 7337 return NULL; 7338 } 7339 return fops->action_create(dev, conf, action, error); 7340 } 7341 7342 /** 7343 * Updates inplace the indirect action configuration pointed by *handle* 7344 * with the configuration provided as *update* argument. 7345 * The update of the indirect action configuration effects all flow rules 7346 * reusing the action via handle. 7347 * 7348 * @param dev 7349 * Pointer to Ethernet device structure. 7350 * @param[in] handle 7351 * Handle for the indirect action to be updated. 7352 * @param[in] update 7353 * Action specification used to modify the action pointed by handle. 7354 * *update* could be of same type with the action pointed by the *handle* 7355 * handle argument, or some other structures like a wrapper, depending on 7356 * the indirect action type. 7357 * @param[out] error 7358 * Perform verbose error reporting if not NULL. PMDs initialize this 7359 * structure in case of error only. 7360 * 7361 * @return 7362 * 0 on success, a negative errno value otherwise and rte_errno is set. 7363 */ 7364 static int 7365 mlx5_action_handle_update(struct rte_eth_dev *dev, 7366 struct rte_flow_action_handle *handle, 7367 const void *update, 7368 struct rte_flow_error *error) 7369 { 7370 struct rte_flow_attr attr = { .transfer = 0 }; 7371 const struct mlx5_flow_driver_ops *fops = 7372 flow_get_drv_ops(flow_get_drv_type(dev, &attr)); 7373 int ret; 7374 7375 ret = flow_drv_action_validate(dev, NULL, 7376 (const struct rte_flow_action *)update, fops, error); 7377 if (ret) 7378 return ret; 7379 return flow_drv_action_update(dev, handle, update, fops, 7380 error); 7381 } 7382 7383 /** 7384 * Query the indirect action by handle. 7385 * 7386 * This function allows retrieving action-specific data such as counters. 7387 * Data is gathered by special action which may be present/referenced in 7388 * more than one flow rule definition. 7389 * 7390 * see @RTE_FLOW_ACTION_TYPE_COUNT 7391 * 7392 * @param dev 7393 * Pointer to Ethernet device structure. 7394 * @param[in] handle 7395 * Handle for the indirect action to query. 7396 * @param[in, out] data 7397 * Pointer to storage for the associated query data type. 7398 * @param[out] error 7399 * Perform verbose error reporting if not NULL. PMDs initialize this 7400 * structure in case of error only. 7401 * 7402 * @return 7403 * 0 on success, a negative errno value otherwise and rte_errno is set. 7404 */ 7405 static int 7406 mlx5_action_handle_query(struct rte_eth_dev *dev, 7407 const struct rte_flow_action_handle *handle, 7408 void *data, 7409 struct rte_flow_error *error) 7410 { 7411 struct rte_flow_attr attr = { .transfer = 0 }; 7412 const struct mlx5_flow_driver_ops *fops = 7413 flow_get_drv_ops(flow_get_drv_type(dev, &attr)); 7414 7415 return flow_drv_action_query(dev, handle, data, fops, error); 7416 } 7417 7418 /** 7419 * Destroy all indirect actions (shared RSS). 7420 * 7421 * @param dev 7422 * Pointer to Ethernet device. 7423 * 7424 * @return 7425 * 0 on success, a negative errno value otherwise and rte_errno is set. 7426 */ 7427 int 7428 mlx5_action_handle_flush(struct rte_eth_dev *dev) 7429 { 7430 struct rte_flow_error error; 7431 struct mlx5_priv *priv = dev->data->dev_private; 7432 struct mlx5_shared_action_rss *shared_rss; 7433 int ret = 0; 7434 uint32_t idx; 7435 7436 ILIST_FOREACH(priv->sh->ipool[MLX5_IPOOL_RSS_SHARED_ACTIONS], 7437 priv->rss_shared_actions, idx, shared_rss, next) { 7438 ret |= mlx5_action_handle_destroy(dev, 7439 (struct rte_flow_action_handle *)(uintptr_t)idx, &error); 7440 } 7441 return ret; 7442 } 7443 7444 #ifndef HAVE_MLX5DV_DR 7445 #define MLX5_DOMAIN_SYNC_FLOW ((1 << 0) | (1 << 1)) 7446 #else 7447 #define MLX5_DOMAIN_SYNC_FLOW \ 7448 (MLX5DV_DR_DOMAIN_SYNC_FLAGS_SW | MLX5DV_DR_DOMAIN_SYNC_FLAGS_HW) 7449 #endif 7450 7451 int rte_pmd_mlx5_sync_flow(uint16_t port_id, uint32_t domains) 7452 { 7453 struct rte_eth_dev *dev = &rte_eth_devices[port_id]; 7454 const struct mlx5_flow_driver_ops *fops; 7455 int ret; 7456 struct rte_flow_attr attr = { .transfer = 0 }; 7457 7458 fops = flow_get_drv_ops(flow_get_drv_type(dev, &attr)); 7459 ret = fops->sync_domain(dev, domains, MLX5_DOMAIN_SYNC_FLOW); 7460 if (ret > 0) 7461 ret = -ret; 7462 return ret; 7463 } 7464 7465 /** 7466 * tunnel offload functionalilty is defined for DV environment only 7467 */ 7468 #ifdef HAVE_IBV_FLOW_DV_SUPPORT 7469 __extension__ 7470 union tunnel_offload_mark { 7471 uint32_t val; 7472 struct { 7473 uint32_t app_reserve:8; 7474 uint32_t table_id:15; 7475 uint32_t transfer:1; 7476 uint32_t _unused_:8; 7477 }; 7478 }; 7479 7480 static bool 7481 mlx5_access_tunnel_offload_db 7482 (struct rte_eth_dev *dev, 7483 bool (*match)(struct rte_eth_dev *, 7484 struct mlx5_flow_tunnel *, const void *), 7485 void (*hit)(struct rte_eth_dev *, struct mlx5_flow_tunnel *, void *), 7486 void (*miss)(struct rte_eth_dev *, void *), 7487 void *ctx, bool lock_op); 7488 7489 static int 7490 flow_tunnel_add_default_miss(struct rte_eth_dev *dev, 7491 struct rte_flow *flow, 7492 const struct rte_flow_attr *attr, 7493 const struct rte_flow_action *app_actions, 7494 uint32_t flow_idx, 7495 struct tunnel_default_miss_ctx *ctx, 7496 struct rte_flow_error *error) 7497 { 7498 struct mlx5_priv *priv = dev->data->dev_private; 7499 struct mlx5_flow *dev_flow; 7500 struct rte_flow_attr miss_attr = *attr; 7501 const struct mlx5_flow_tunnel *tunnel = app_actions[0].conf; 7502 const struct rte_flow_item miss_items[2] = { 7503 { 7504 .type = RTE_FLOW_ITEM_TYPE_ETH, 7505 .spec = NULL, 7506 .last = NULL, 7507 .mask = NULL 7508 }, 7509 { 7510 .type = RTE_FLOW_ITEM_TYPE_END, 7511 .spec = NULL, 7512 .last = NULL, 7513 .mask = NULL 7514 } 7515 }; 7516 union tunnel_offload_mark mark_id; 7517 struct rte_flow_action_mark miss_mark; 7518 struct rte_flow_action miss_actions[3] = { 7519 [0] = { .type = RTE_FLOW_ACTION_TYPE_MARK, .conf = &miss_mark }, 7520 [2] = { .type = RTE_FLOW_ACTION_TYPE_END, .conf = NULL } 7521 }; 7522 const struct rte_flow_action_jump *jump_data; 7523 uint32_t i, flow_table = 0; /* prevent compilation warning */ 7524 struct flow_grp_info grp_info = { 7525 .external = 1, 7526 .transfer = attr->transfer, 7527 .fdb_def_rule = !!priv->fdb_def_rule, 7528 .std_tbl_fix = 0, 7529 }; 7530 int ret; 7531 7532 if (!attr->transfer) { 7533 uint32_t q_size; 7534 7535 miss_actions[1].type = RTE_FLOW_ACTION_TYPE_RSS; 7536 q_size = priv->reta_idx_n * sizeof(ctx->queue[0]); 7537 ctx->queue = mlx5_malloc(MLX5_MEM_SYS | MLX5_MEM_ZERO, q_size, 7538 0, SOCKET_ID_ANY); 7539 if (!ctx->queue) 7540 return rte_flow_error_set 7541 (error, ENOMEM, 7542 RTE_FLOW_ERROR_TYPE_ACTION_CONF, 7543 NULL, "invalid default miss RSS"); 7544 ctx->action_rss.func = RTE_ETH_HASH_FUNCTION_DEFAULT, 7545 ctx->action_rss.level = 0, 7546 ctx->action_rss.types = priv->rss_conf.rss_hf, 7547 ctx->action_rss.key_len = priv->rss_conf.rss_key_len, 7548 ctx->action_rss.queue_num = priv->reta_idx_n, 7549 ctx->action_rss.key = priv->rss_conf.rss_key, 7550 ctx->action_rss.queue = ctx->queue; 7551 if (!priv->reta_idx_n || !priv->rxqs_n) 7552 return rte_flow_error_set 7553 (error, EINVAL, 7554 RTE_FLOW_ERROR_TYPE_ACTION_CONF, 7555 NULL, "invalid port configuration"); 7556 if (!(dev->data->dev_conf.rxmode.mq_mode & ETH_MQ_RX_RSS_FLAG)) 7557 ctx->action_rss.types = 0; 7558 for (i = 0; i != priv->reta_idx_n; ++i) 7559 ctx->queue[i] = (*priv->reta_idx)[i]; 7560 } else { 7561 miss_actions[1].type = RTE_FLOW_ACTION_TYPE_JUMP; 7562 ctx->miss_jump.group = MLX5_TNL_MISS_FDB_JUMP_GRP; 7563 } 7564 miss_actions[1].conf = (typeof(miss_actions[1].conf))ctx->raw; 7565 for (; app_actions->type != RTE_FLOW_ACTION_TYPE_JUMP; app_actions++); 7566 jump_data = app_actions->conf; 7567 miss_attr.priority = MLX5_TNL_MISS_RULE_PRIORITY; 7568 miss_attr.group = jump_data->group; 7569 ret = mlx5_flow_group_to_table(dev, tunnel, jump_data->group, 7570 &flow_table, &grp_info, error); 7571 if (ret) 7572 return rte_flow_error_set(error, EINVAL, 7573 RTE_FLOW_ERROR_TYPE_ACTION_CONF, 7574 NULL, "invalid tunnel id"); 7575 mark_id.app_reserve = 0; 7576 mark_id.table_id = tunnel_flow_tbl_to_id(flow_table); 7577 mark_id.transfer = !!attr->transfer; 7578 mark_id._unused_ = 0; 7579 miss_mark.id = mark_id.val; 7580 dev_flow = flow_drv_prepare(dev, flow, &miss_attr, 7581 miss_items, miss_actions, flow_idx, error); 7582 if (!dev_flow) 7583 return -rte_errno; 7584 dev_flow->flow = flow; 7585 dev_flow->external = true; 7586 dev_flow->tunnel = tunnel; 7587 /* Subflow object was created, we must include one in the list. */ 7588 SILIST_INSERT(&flow->dev_handles, dev_flow->handle_idx, 7589 dev_flow->handle, next); 7590 DRV_LOG(DEBUG, 7591 "port %u tunnel type=%d id=%u miss rule priority=%u group=%u", 7592 dev->data->port_id, tunnel->app_tunnel.type, 7593 tunnel->tunnel_id, miss_attr.priority, miss_attr.group); 7594 ret = flow_drv_translate(dev, dev_flow, &miss_attr, miss_items, 7595 miss_actions, error); 7596 if (!ret) 7597 ret = flow_mreg_update_copy_table(dev, flow, miss_actions, 7598 error); 7599 7600 return ret; 7601 } 7602 7603 static const struct mlx5_flow_tbl_data_entry * 7604 tunnel_mark_decode(struct rte_eth_dev *dev, uint32_t mark) 7605 { 7606 struct mlx5_priv *priv = dev->data->dev_private; 7607 struct mlx5_dev_ctx_shared *sh = priv->sh; 7608 struct mlx5_hlist_entry *he; 7609 union tunnel_offload_mark mbits = { .val = mark }; 7610 union mlx5_flow_tbl_key table_key = { 7611 { 7612 .table_id = tunnel_id_to_flow_tbl(mbits.table_id), 7613 .dummy = 0, 7614 .domain = !!mbits.transfer, 7615 .direction = 0, 7616 } 7617 }; 7618 he = mlx5_hlist_lookup(sh->flow_tbls, table_key.v64, NULL); 7619 return he ? 7620 container_of(he, struct mlx5_flow_tbl_data_entry, entry) : NULL; 7621 } 7622 7623 static void 7624 mlx5_flow_tunnel_grp2tbl_remove_cb(struct mlx5_hlist *list, 7625 struct mlx5_hlist_entry *entry) 7626 { 7627 struct mlx5_dev_ctx_shared *sh = list->ctx; 7628 struct tunnel_tbl_entry *tte = container_of(entry, typeof(*tte), hash); 7629 7630 mlx5_ipool_free(sh->ipool[MLX5_IPOOL_TNL_TBL_ID], 7631 tunnel_flow_tbl_to_id(tte->flow_table)); 7632 mlx5_free(tte); 7633 } 7634 7635 static int 7636 mlx5_flow_tunnel_grp2tbl_match_cb(struct mlx5_hlist *list __rte_unused, 7637 struct mlx5_hlist_entry *entry, 7638 uint64_t key, void *cb_ctx __rte_unused) 7639 { 7640 union tunnel_tbl_key tbl = { 7641 .val = key, 7642 }; 7643 struct tunnel_tbl_entry *tte = container_of(entry, typeof(*tte), hash); 7644 7645 return tbl.tunnel_id != tte->tunnel_id || tbl.group != tte->group; 7646 } 7647 7648 static struct mlx5_hlist_entry * 7649 mlx5_flow_tunnel_grp2tbl_create_cb(struct mlx5_hlist *list, uint64_t key, 7650 void *ctx __rte_unused) 7651 { 7652 struct mlx5_dev_ctx_shared *sh = list->ctx; 7653 struct tunnel_tbl_entry *tte; 7654 union tunnel_tbl_key tbl = { 7655 .val = key, 7656 }; 7657 7658 tte = mlx5_malloc(MLX5_MEM_SYS | MLX5_MEM_ZERO, 7659 sizeof(*tte), 0, 7660 SOCKET_ID_ANY); 7661 if (!tte) 7662 goto err; 7663 mlx5_ipool_malloc(sh->ipool[MLX5_IPOOL_TNL_TBL_ID], 7664 &tte->flow_table); 7665 if (tte->flow_table >= MLX5_MAX_TABLES) { 7666 DRV_LOG(ERR, "Tunnel TBL ID %d exceed max limit.", 7667 tte->flow_table); 7668 mlx5_ipool_free(sh->ipool[MLX5_IPOOL_TNL_TBL_ID], 7669 tte->flow_table); 7670 goto err; 7671 } else if (!tte->flow_table) { 7672 goto err; 7673 } 7674 tte->flow_table = tunnel_id_to_flow_tbl(tte->flow_table); 7675 tte->tunnel_id = tbl.tunnel_id; 7676 tte->group = tbl.group; 7677 return &tte->hash; 7678 err: 7679 if (tte) 7680 mlx5_free(tte); 7681 return NULL; 7682 } 7683 7684 static uint32_t 7685 tunnel_flow_group_to_flow_table(struct rte_eth_dev *dev, 7686 const struct mlx5_flow_tunnel *tunnel, 7687 uint32_t group, uint32_t *table, 7688 struct rte_flow_error *error) 7689 { 7690 struct mlx5_hlist_entry *he; 7691 struct tunnel_tbl_entry *tte; 7692 union tunnel_tbl_key key = { 7693 .tunnel_id = tunnel ? tunnel->tunnel_id : 0, 7694 .group = group 7695 }; 7696 struct mlx5_flow_tunnel_hub *thub = mlx5_tunnel_hub(dev); 7697 struct mlx5_hlist *group_hash; 7698 7699 group_hash = tunnel ? tunnel->groups : thub->groups; 7700 he = mlx5_hlist_register(group_hash, key.val, NULL); 7701 if (!he) 7702 return rte_flow_error_set(error, EINVAL, 7703 RTE_FLOW_ERROR_TYPE_ATTR_GROUP, 7704 NULL, 7705 "tunnel group index not supported"); 7706 tte = container_of(he, typeof(*tte), hash); 7707 *table = tte->flow_table; 7708 DRV_LOG(DEBUG, "port %u tunnel %u group=%#x table=%#x", 7709 dev->data->port_id, key.tunnel_id, group, *table); 7710 return 0; 7711 } 7712 7713 static void 7714 mlx5_flow_tunnel_free(struct rte_eth_dev *dev, 7715 struct mlx5_flow_tunnel *tunnel) 7716 { 7717 struct mlx5_priv *priv = dev->data->dev_private; 7718 struct mlx5_indexed_pool *ipool; 7719 7720 DRV_LOG(DEBUG, "port %u release pmd tunnel id=0x%x", 7721 dev->data->port_id, tunnel->tunnel_id); 7722 LIST_REMOVE(tunnel, chain); 7723 mlx5_hlist_destroy(tunnel->groups); 7724 ipool = priv->sh->ipool[MLX5_IPOOL_TUNNEL_ID]; 7725 mlx5_ipool_free(ipool, tunnel->tunnel_id); 7726 } 7727 7728 static bool 7729 mlx5_access_tunnel_offload_db 7730 (struct rte_eth_dev *dev, 7731 bool (*match)(struct rte_eth_dev *, 7732 struct mlx5_flow_tunnel *, const void *), 7733 void (*hit)(struct rte_eth_dev *, struct mlx5_flow_tunnel *, void *), 7734 void (*miss)(struct rte_eth_dev *, void *), 7735 void *ctx, bool lock_op) 7736 { 7737 bool verdict = false; 7738 struct mlx5_flow_tunnel_hub *thub = mlx5_tunnel_hub(dev); 7739 struct mlx5_flow_tunnel *tunnel; 7740 7741 rte_spinlock_lock(&thub->sl); 7742 LIST_FOREACH(tunnel, &thub->tunnels, chain) { 7743 verdict = match(dev, tunnel, (const void *)ctx); 7744 if (verdict) 7745 break; 7746 } 7747 if (!lock_op) 7748 rte_spinlock_unlock(&thub->sl); 7749 if (verdict && hit) 7750 hit(dev, tunnel, ctx); 7751 if (!verdict && miss) 7752 miss(dev, ctx); 7753 if (lock_op) 7754 rte_spinlock_unlock(&thub->sl); 7755 7756 return verdict; 7757 } 7758 7759 struct tunnel_db_find_tunnel_id_ctx { 7760 uint32_t tunnel_id; 7761 struct mlx5_flow_tunnel *tunnel; 7762 }; 7763 7764 static bool 7765 find_tunnel_id_match(struct rte_eth_dev *dev, 7766 struct mlx5_flow_tunnel *tunnel, const void *x) 7767 { 7768 const struct tunnel_db_find_tunnel_id_ctx *ctx = x; 7769 7770 RTE_SET_USED(dev); 7771 return tunnel->tunnel_id == ctx->tunnel_id; 7772 } 7773 7774 static void 7775 find_tunnel_id_hit(struct rte_eth_dev *dev, 7776 struct mlx5_flow_tunnel *tunnel, void *x) 7777 { 7778 struct tunnel_db_find_tunnel_id_ctx *ctx = x; 7779 RTE_SET_USED(dev); 7780 ctx->tunnel = tunnel; 7781 } 7782 7783 static struct mlx5_flow_tunnel * 7784 mlx5_find_tunnel_id(struct rte_eth_dev *dev, uint32_t id) 7785 { 7786 struct tunnel_db_find_tunnel_id_ctx ctx = { 7787 .tunnel_id = id, 7788 }; 7789 7790 mlx5_access_tunnel_offload_db(dev, find_tunnel_id_match, 7791 find_tunnel_id_hit, NULL, &ctx, true); 7792 7793 return ctx.tunnel; 7794 } 7795 7796 static struct mlx5_flow_tunnel * 7797 mlx5_flow_tunnel_allocate(struct rte_eth_dev *dev, 7798 const struct rte_flow_tunnel *app_tunnel) 7799 { 7800 struct mlx5_priv *priv = dev->data->dev_private; 7801 struct mlx5_indexed_pool *ipool; 7802 struct mlx5_flow_tunnel *tunnel; 7803 uint32_t id; 7804 7805 ipool = priv->sh->ipool[MLX5_IPOOL_TUNNEL_ID]; 7806 tunnel = mlx5_ipool_zmalloc(ipool, &id); 7807 if (!tunnel) 7808 return NULL; 7809 if (id >= MLX5_MAX_TUNNELS) { 7810 mlx5_ipool_free(ipool, id); 7811 DRV_LOG(ERR, "Tunnel ID %d exceed max limit.", id); 7812 return NULL; 7813 } 7814 tunnel->groups = mlx5_hlist_create("tunnel groups", 1024, 0, 0, 7815 mlx5_flow_tunnel_grp2tbl_create_cb, 7816 mlx5_flow_tunnel_grp2tbl_match_cb, 7817 mlx5_flow_tunnel_grp2tbl_remove_cb); 7818 if (!tunnel->groups) { 7819 mlx5_ipool_free(ipool, id); 7820 return NULL; 7821 } 7822 tunnel->groups->ctx = priv->sh; 7823 /* initiate new PMD tunnel */ 7824 memcpy(&tunnel->app_tunnel, app_tunnel, sizeof(*app_tunnel)); 7825 tunnel->tunnel_id = id; 7826 tunnel->action.type = (typeof(tunnel->action.type)) 7827 MLX5_RTE_FLOW_ACTION_TYPE_TUNNEL_SET; 7828 tunnel->action.conf = tunnel; 7829 tunnel->item.type = (typeof(tunnel->item.type)) 7830 MLX5_RTE_FLOW_ITEM_TYPE_TUNNEL; 7831 tunnel->item.spec = tunnel; 7832 tunnel->item.last = NULL; 7833 tunnel->item.mask = NULL; 7834 7835 DRV_LOG(DEBUG, "port %u new pmd tunnel id=0x%x", 7836 dev->data->port_id, tunnel->tunnel_id); 7837 7838 return tunnel; 7839 } 7840 7841 struct tunnel_db_get_tunnel_ctx { 7842 const struct rte_flow_tunnel *app_tunnel; 7843 struct mlx5_flow_tunnel *tunnel; 7844 }; 7845 7846 static bool get_tunnel_match(struct rte_eth_dev *dev, 7847 struct mlx5_flow_tunnel *tunnel, const void *x) 7848 { 7849 const struct tunnel_db_get_tunnel_ctx *ctx = x; 7850 7851 RTE_SET_USED(dev); 7852 return !memcmp(ctx->app_tunnel, &tunnel->app_tunnel, 7853 sizeof(*ctx->app_tunnel)); 7854 } 7855 7856 static void get_tunnel_hit(struct rte_eth_dev *dev, 7857 struct mlx5_flow_tunnel *tunnel, void *x) 7858 { 7859 /* called under tunnel spinlock protection */ 7860 struct tunnel_db_get_tunnel_ctx *ctx = x; 7861 7862 RTE_SET_USED(dev); 7863 tunnel->refctn++; 7864 ctx->tunnel = tunnel; 7865 } 7866 7867 static void get_tunnel_miss(struct rte_eth_dev *dev, void *x) 7868 { 7869 /* called under tunnel spinlock protection */ 7870 struct mlx5_flow_tunnel_hub *thub = mlx5_tunnel_hub(dev); 7871 struct tunnel_db_get_tunnel_ctx *ctx = x; 7872 7873 rte_spinlock_unlock(&thub->sl); 7874 ctx->tunnel = mlx5_flow_tunnel_allocate(dev, ctx->app_tunnel); 7875 rte_spinlock_lock(&thub->sl); 7876 if (ctx->tunnel) { 7877 ctx->tunnel->refctn = 1; 7878 LIST_INSERT_HEAD(&thub->tunnels, ctx->tunnel, chain); 7879 } 7880 } 7881 7882 7883 static int 7884 mlx5_get_flow_tunnel(struct rte_eth_dev *dev, 7885 const struct rte_flow_tunnel *app_tunnel, 7886 struct mlx5_flow_tunnel **tunnel) 7887 { 7888 struct tunnel_db_get_tunnel_ctx ctx = { 7889 .app_tunnel = app_tunnel, 7890 }; 7891 7892 mlx5_access_tunnel_offload_db(dev, get_tunnel_match, get_tunnel_hit, 7893 get_tunnel_miss, &ctx, true); 7894 *tunnel = ctx.tunnel; 7895 return ctx.tunnel ? 0 : -ENOMEM; 7896 } 7897 7898 void mlx5_release_tunnel_hub(struct mlx5_dev_ctx_shared *sh, uint16_t port_id) 7899 { 7900 struct mlx5_flow_tunnel_hub *thub = sh->tunnel_hub; 7901 7902 if (!thub) 7903 return; 7904 if (!LIST_EMPTY(&thub->tunnels)) 7905 DRV_LOG(WARNING, "port %u tunnels present", port_id); 7906 mlx5_hlist_destroy(thub->groups); 7907 mlx5_free(thub); 7908 } 7909 7910 int mlx5_alloc_tunnel_hub(struct mlx5_dev_ctx_shared *sh) 7911 { 7912 int err; 7913 struct mlx5_flow_tunnel_hub *thub; 7914 7915 thub = mlx5_malloc(MLX5_MEM_SYS | MLX5_MEM_ZERO, sizeof(*thub), 7916 0, SOCKET_ID_ANY); 7917 if (!thub) 7918 return -ENOMEM; 7919 LIST_INIT(&thub->tunnels); 7920 rte_spinlock_init(&thub->sl); 7921 thub->groups = mlx5_hlist_create("flow groups", 7922 rte_align32pow2(MLX5_MAX_TABLES), 0, 7923 0, mlx5_flow_tunnel_grp2tbl_create_cb, 7924 mlx5_flow_tunnel_grp2tbl_match_cb, 7925 mlx5_flow_tunnel_grp2tbl_remove_cb); 7926 if (!thub->groups) { 7927 err = -rte_errno; 7928 goto err; 7929 } 7930 thub->groups->ctx = sh; 7931 sh->tunnel_hub = thub; 7932 7933 return 0; 7934 7935 err: 7936 if (thub->groups) 7937 mlx5_hlist_destroy(thub->groups); 7938 if (thub) 7939 mlx5_free(thub); 7940 return err; 7941 } 7942 7943 static inline bool 7944 mlx5_flow_tunnel_validate(struct rte_eth_dev *dev, 7945 struct rte_flow_tunnel *tunnel, 7946 const char *err_msg) 7947 { 7948 err_msg = NULL; 7949 if (!is_tunnel_offload_active(dev)) { 7950 err_msg = "tunnel offload was not activated"; 7951 goto out; 7952 } else if (!tunnel) { 7953 err_msg = "no application tunnel"; 7954 goto out; 7955 } 7956 7957 switch (tunnel->type) { 7958 default: 7959 err_msg = "unsupported tunnel type"; 7960 goto out; 7961 case RTE_FLOW_ITEM_TYPE_VXLAN: 7962 break; 7963 } 7964 7965 out: 7966 return !err_msg; 7967 } 7968 7969 static int 7970 mlx5_flow_tunnel_decap_set(struct rte_eth_dev *dev, 7971 struct rte_flow_tunnel *app_tunnel, 7972 struct rte_flow_action **actions, 7973 uint32_t *num_of_actions, 7974 struct rte_flow_error *error) 7975 { 7976 int ret; 7977 struct mlx5_flow_tunnel *tunnel; 7978 const char *err_msg = NULL; 7979 bool verdict = mlx5_flow_tunnel_validate(dev, app_tunnel, err_msg); 7980 7981 if (!verdict) 7982 return rte_flow_error_set(error, EINVAL, 7983 RTE_FLOW_ERROR_TYPE_ACTION_CONF, NULL, 7984 err_msg); 7985 ret = mlx5_get_flow_tunnel(dev, app_tunnel, &tunnel); 7986 if (ret < 0) { 7987 return rte_flow_error_set(error, ret, 7988 RTE_FLOW_ERROR_TYPE_ACTION_CONF, NULL, 7989 "failed to initialize pmd tunnel"); 7990 } 7991 *actions = &tunnel->action; 7992 *num_of_actions = 1; 7993 return 0; 7994 } 7995 7996 static int 7997 mlx5_flow_tunnel_match(struct rte_eth_dev *dev, 7998 struct rte_flow_tunnel *app_tunnel, 7999 struct rte_flow_item **items, 8000 uint32_t *num_of_items, 8001 struct rte_flow_error *error) 8002 { 8003 int ret; 8004 struct mlx5_flow_tunnel *tunnel; 8005 const char *err_msg = NULL; 8006 bool verdict = mlx5_flow_tunnel_validate(dev, app_tunnel, err_msg); 8007 8008 if (!verdict) 8009 return rte_flow_error_set(error, EINVAL, 8010 RTE_FLOW_ERROR_TYPE_HANDLE, NULL, 8011 err_msg); 8012 ret = mlx5_get_flow_tunnel(dev, app_tunnel, &tunnel); 8013 if (ret < 0) { 8014 return rte_flow_error_set(error, ret, 8015 RTE_FLOW_ERROR_TYPE_HANDLE, NULL, 8016 "failed to initialize pmd tunnel"); 8017 } 8018 *items = &tunnel->item; 8019 *num_of_items = 1; 8020 return 0; 8021 } 8022 8023 struct tunnel_db_element_release_ctx { 8024 struct rte_flow_item *items; 8025 struct rte_flow_action *actions; 8026 uint32_t num_elements; 8027 struct rte_flow_error *error; 8028 int ret; 8029 }; 8030 8031 static bool 8032 tunnel_element_release_match(struct rte_eth_dev *dev, 8033 struct mlx5_flow_tunnel *tunnel, const void *x) 8034 { 8035 const struct tunnel_db_element_release_ctx *ctx = x; 8036 8037 RTE_SET_USED(dev); 8038 if (ctx->num_elements != 1) 8039 return false; 8040 else if (ctx->items) 8041 return ctx->items == &tunnel->item; 8042 else if (ctx->actions) 8043 return ctx->actions == &tunnel->action; 8044 8045 return false; 8046 } 8047 8048 static void 8049 tunnel_element_release_hit(struct rte_eth_dev *dev, 8050 struct mlx5_flow_tunnel *tunnel, void *x) 8051 { 8052 struct tunnel_db_element_release_ctx *ctx = x; 8053 ctx->ret = 0; 8054 if (!__atomic_sub_fetch(&tunnel->refctn, 1, __ATOMIC_RELAXED)) 8055 mlx5_flow_tunnel_free(dev, tunnel); 8056 } 8057 8058 static void 8059 tunnel_element_release_miss(struct rte_eth_dev *dev, void *x) 8060 { 8061 struct tunnel_db_element_release_ctx *ctx = x; 8062 RTE_SET_USED(dev); 8063 ctx->ret = rte_flow_error_set(ctx->error, EINVAL, 8064 RTE_FLOW_ERROR_TYPE_HANDLE, NULL, 8065 "invalid argument"); 8066 } 8067 8068 static int 8069 mlx5_flow_tunnel_item_release(struct rte_eth_dev *dev, 8070 struct rte_flow_item *pmd_items, 8071 uint32_t num_items, struct rte_flow_error *err) 8072 { 8073 struct tunnel_db_element_release_ctx ctx = { 8074 .items = pmd_items, 8075 .actions = NULL, 8076 .num_elements = num_items, 8077 .error = err, 8078 }; 8079 8080 mlx5_access_tunnel_offload_db(dev, tunnel_element_release_match, 8081 tunnel_element_release_hit, 8082 tunnel_element_release_miss, &ctx, false); 8083 8084 return ctx.ret; 8085 } 8086 8087 static int 8088 mlx5_flow_tunnel_action_release(struct rte_eth_dev *dev, 8089 struct rte_flow_action *pmd_actions, 8090 uint32_t num_actions, struct rte_flow_error *err) 8091 { 8092 struct tunnel_db_element_release_ctx ctx = { 8093 .items = NULL, 8094 .actions = pmd_actions, 8095 .num_elements = num_actions, 8096 .error = err, 8097 }; 8098 8099 mlx5_access_tunnel_offload_db(dev, tunnel_element_release_match, 8100 tunnel_element_release_hit, 8101 tunnel_element_release_miss, &ctx, false); 8102 8103 return ctx.ret; 8104 } 8105 8106 static int 8107 mlx5_flow_tunnel_get_restore_info(struct rte_eth_dev *dev, 8108 struct rte_mbuf *m, 8109 struct rte_flow_restore_info *info, 8110 struct rte_flow_error *err) 8111 { 8112 uint64_t ol_flags = m->ol_flags; 8113 const struct mlx5_flow_tbl_data_entry *tble; 8114 const uint64_t mask = PKT_RX_FDIR | PKT_RX_FDIR_ID; 8115 8116 if (!is_tunnel_offload_active(dev)) { 8117 info->flags = 0; 8118 return 0; 8119 } 8120 8121 if ((ol_flags & mask) != mask) 8122 goto err; 8123 tble = tunnel_mark_decode(dev, m->hash.fdir.hi); 8124 if (!tble) { 8125 DRV_LOG(DEBUG, "port %u invalid miss tunnel mark %#x", 8126 dev->data->port_id, m->hash.fdir.hi); 8127 goto err; 8128 } 8129 MLX5_ASSERT(tble->tunnel); 8130 memcpy(&info->tunnel, &tble->tunnel->app_tunnel, sizeof(info->tunnel)); 8131 info->group_id = tble->group_id; 8132 info->flags = RTE_FLOW_RESTORE_INFO_TUNNEL | 8133 RTE_FLOW_RESTORE_INFO_GROUP_ID | 8134 RTE_FLOW_RESTORE_INFO_ENCAPSULATED; 8135 8136 return 0; 8137 8138 err: 8139 return rte_flow_error_set(err, EINVAL, 8140 RTE_FLOW_ERROR_TYPE_UNSPECIFIED, NULL, 8141 "failed to get restore info"); 8142 } 8143 8144 #else /* HAVE_IBV_FLOW_DV_SUPPORT */ 8145 static int 8146 mlx5_flow_tunnel_decap_set(__rte_unused struct rte_eth_dev *dev, 8147 __rte_unused struct rte_flow_tunnel *app_tunnel, 8148 __rte_unused struct rte_flow_action **actions, 8149 __rte_unused uint32_t *num_of_actions, 8150 __rte_unused struct rte_flow_error *error) 8151 { 8152 return -ENOTSUP; 8153 } 8154 8155 static int 8156 mlx5_flow_tunnel_match(__rte_unused struct rte_eth_dev *dev, 8157 __rte_unused struct rte_flow_tunnel *app_tunnel, 8158 __rte_unused struct rte_flow_item **items, 8159 __rte_unused uint32_t *num_of_items, 8160 __rte_unused struct rte_flow_error *error) 8161 { 8162 return -ENOTSUP; 8163 } 8164 8165 static int 8166 mlx5_flow_tunnel_item_release(__rte_unused struct rte_eth_dev *dev, 8167 __rte_unused struct rte_flow_item *pmd_items, 8168 __rte_unused uint32_t num_items, 8169 __rte_unused struct rte_flow_error *err) 8170 { 8171 return -ENOTSUP; 8172 } 8173 8174 static int 8175 mlx5_flow_tunnel_action_release(__rte_unused struct rte_eth_dev *dev, 8176 __rte_unused struct rte_flow_action *pmd_action, 8177 __rte_unused uint32_t num_actions, 8178 __rte_unused struct rte_flow_error *err) 8179 { 8180 return -ENOTSUP; 8181 } 8182 8183 static int 8184 mlx5_flow_tunnel_get_restore_info(__rte_unused struct rte_eth_dev *dev, 8185 __rte_unused struct rte_mbuf *m, 8186 __rte_unused struct rte_flow_restore_info *i, 8187 __rte_unused struct rte_flow_error *err) 8188 { 8189 return -ENOTSUP; 8190 } 8191 8192 static int 8193 flow_tunnel_add_default_miss(__rte_unused struct rte_eth_dev *dev, 8194 __rte_unused struct rte_flow *flow, 8195 __rte_unused const struct rte_flow_attr *attr, 8196 __rte_unused const struct rte_flow_action *actions, 8197 __rte_unused uint32_t flow_idx, 8198 __rte_unused struct tunnel_default_miss_ctx *ctx, 8199 __rte_unused struct rte_flow_error *error) 8200 { 8201 return -ENOTSUP; 8202 } 8203 8204 static struct mlx5_flow_tunnel * 8205 mlx5_find_tunnel_id(__rte_unused struct rte_eth_dev *dev, 8206 __rte_unused uint32_t id) 8207 { 8208 return NULL; 8209 } 8210 8211 static void 8212 mlx5_flow_tunnel_free(__rte_unused struct rte_eth_dev *dev, 8213 __rte_unused struct mlx5_flow_tunnel *tunnel) 8214 { 8215 } 8216 8217 static uint32_t 8218 tunnel_flow_group_to_flow_table(__rte_unused struct rte_eth_dev *dev, 8219 __rte_unused const struct mlx5_flow_tunnel *t, 8220 __rte_unused uint32_t group, 8221 __rte_unused uint32_t *table, 8222 struct rte_flow_error *error) 8223 { 8224 return rte_flow_error_set(error, ENOTSUP, 8225 RTE_FLOW_ERROR_TYPE_UNSPECIFIED, NULL, 8226 "tunnel offload requires DV support"); 8227 } 8228 8229 void 8230 mlx5_release_tunnel_hub(__rte_unused struct mlx5_dev_ctx_shared *sh, 8231 __rte_unused uint16_t port_id) 8232 { 8233 } 8234 #endif /* HAVE_IBV_FLOW_DV_SUPPORT */ 8235