1 /* SPDX-License-Identifier: BSD-3-Clause 2 * Copyright 2016 6WIND S.A. 3 * Copyright 2016 Mellanox Technologies, Ltd 4 */ 5 6 #include <netinet/in.h> 7 #include <sys/queue.h> 8 #include <stdalign.h> 9 #include <stdint.h> 10 #include <string.h> 11 12 /* Verbs header. */ 13 /* ISO C doesn't support unnamed structs/unions, disabling -pedantic. */ 14 #ifdef PEDANTIC 15 #pragma GCC diagnostic ignored "-Wpedantic" 16 #endif 17 #include <infiniband/verbs.h> 18 #ifdef PEDANTIC 19 #pragma GCC diagnostic error "-Wpedantic" 20 #endif 21 22 #include <rte_common.h> 23 #include <rte_ether.h> 24 #include <rte_ethdev_driver.h> 25 #include <rte_flow.h> 26 #include <rte_flow_driver.h> 27 #include <rte_malloc.h> 28 #include <rte_ip.h> 29 30 #include "mlx5.h" 31 #include "mlx5_defs.h" 32 #include "mlx5_flow.h" 33 #include "mlx5_glue.h" 34 #include "mlx5_prm.h" 35 #include "mlx5_rxtx.h" 36 37 /* Dev ops structure defined in mlx5.c */ 38 extern const struct eth_dev_ops mlx5_dev_ops; 39 extern const struct eth_dev_ops mlx5_dev_ops_isolate; 40 41 /** Device flow drivers. */ 42 #ifdef HAVE_IBV_FLOW_DV_SUPPORT 43 extern const struct mlx5_flow_driver_ops mlx5_flow_dv_drv_ops; 44 #endif 45 extern const struct mlx5_flow_driver_ops mlx5_flow_verbs_drv_ops; 46 47 const struct mlx5_flow_driver_ops mlx5_flow_null_drv_ops; 48 49 const struct mlx5_flow_driver_ops *flow_drv_ops[] = { 50 [MLX5_FLOW_TYPE_MIN] = &mlx5_flow_null_drv_ops, 51 #ifdef HAVE_IBV_FLOW_DV_SUPPORT 52 [MLX5_FLOW_TYPE_DV] = &mlx5_flow_dv_drv_ops, 53 #endif 54 [MLX5_FLOW_TYPE_VERBS] = &mlx5_flow_verbs_drv_ops, 55 [MLX5_FLOW_TYPE_MAX] = &mlx5_flow_null_drv_ops 56 }; 57 58 enum mlx5_expansion { 59 MLX5_EXPANSION_ROOT, 60 MLX5_EXPANSION_ROOT_OUTER, 61 MLX5_EXPANSION_ROOT_ETH_VLAN, 62 MLX5_EXPANSION_ROOT_OUTER_ETH_VLAN, 63 MLX5_EXPANSION_OUTER_ETH, 64 MLX5_EXPANSION_OUTER_ETH_VLAN, 65 MLX5_EXPANSION_OUTER_VLAN, 66 MLX5_EXPANSION_OUTER_IPV4, 67 MLX5_EXPANSION_OUTER_IPV4_UDP, 68 MLX5_EXPANSION_OUTER_IPV4_TCP, 69 MLX5_EXPANSION_OUTER_IPV6, 70 MLX5_EXPANSION_OUTER_IPV6_UDP, 71 MLX5_EXPANSION_OUTER_IPV6_TCP, 72 MLX5_EXPANSION_VXLAN, 73 MLX5_EXPANSION_VXLAN_GPE, 74 MLX5_EXPANSION_GRE, 75 MLX5_EXPANSION_MPLS, 76 MLX5_EXPANSION_ETH, 77 MLX5_EXPANSION_ETH_VLAN, 78 MLX5_EXPANSION_VLAN, 79 MLX5_EXPANSION_IPV4, 80 MLX5_EXPANSION_IPV4_UDP, 81 MLX5_EXPANSION_IPV4_TCP, 82 MLX5_EXPANSION_IPV6, 83 MLX5_EXPANSION_IPV6_UDP, 84 MLX5_EXPANSION_IPV6_TCP, 85 }; 86 87 /** Supported expansion of items. */ 88 static const struct rte_flow_expand_node mlx5_support_expansion[] = { 89 [MLX5_EXPANSION_ROOT] = { 90 .next = RTE_FLOW_EXPAND_RSS_NEXT(MLX5_EXPANSION_ETH, 91 MLX5_EXPANSION_IPV4, 92 MLX5_EXPANSION_IPV6), 93 .type = RTE_FLOW_ITEM_TYPE_END, 94 }, 95 [MLX5_EXPANSION_ROOT_OUTER] = { 96 .next = RTE_FLOW_EXPAND_RSS_NEXT(MLX5_EXPANSION_OUTER_ETH, 97 MLX5_EXPANSION_OUTER_IPV4, 98 MLX5_EXPANSION_OUTER_IPV6), 99 .type = RTE_FLOW_ITEM_TYPE_END, 100 }, 101 [MLX5_EXPANSION_ROOT_ETH_VLAN] = { 102 .next = RTE_FLOW_EXPAND_RSS_NEXT(MLX5_EXPANSION_ETH_VLAN), 103 .type = RTE_FLOW_ITEM_TYPE_END, 104 }, 105 [MLX5_EXPANSION_ROOT_OUTER_ETH_VLAN] = { 106 .next = RTE_FLOW_EXPAND_RSS_NEXT(MLX5_EXPANSION_OUTER_ETH_VLAN), 107 .type = RTE_FLOW_ITEM_TYPE_END, 108 }, 109 [MLX5_EXPANSION_OUTER_ETH] = { 110 .next = RTE_FLOW_EXPAND_RSS_NEXT(MLX5_EXPANSION_OUTER_IPV4, 111 MLX5_EXPANSION_OUTER_IPV6, 112 MLX5_EXPANSION_MPLS), 113 .type = RTE_FLOW_ITEM_TYPE_ETH, 114 .rss_types = 0, 115 }, 116 [MLX5_EXPANSION_OUTER_ETH_VLAN] = { 117 .next = RTE_FLOW_EXPAND_RSS_NEXT(MLX5_EXPANSION_OUTER_VLAN), 118 .type = RTE_FLOW_ITEM_TYPE_ETH, 119 .rss_types = 0, 120 }, 121 [MLX5_EXPANSION_OUTER_VLAN] = { 122 .next = RTE_FLOW_EXPAND_RSS_NEXT(MLX5_EXPANSION_OUTER_IPV4, 123 MLX5_EXPANSION_OUTER_IPV6), 124 .type = RTE_FLOW_ITEM_TYPE_VLAN, 125 }, 126 [MLX5_EXPANSION_OUTER_IPV4] = { 127 .next = RTE_FLOW_EXPAND_RSS_NEXT 128 (MLX5_EXPANSION_OUTER_IPV4_UDP, 129 MLX5_EXPANSION_OUTER_IPV4_TCP, 130 MLX5_EXPANSION_GRE, 131 MLX5_EXPANSION_IPV4, 132 MLX5_EXPANSION_IPV6), 133 .type = RTE_FLOW_ITEM_TYPE_IPV4, 134 .rss_types = ETH_RSS_IPV4 | ETH_RSS_FRAG_IPV4 | 135 ETH_RSS_NONFRAG_IPV4_OTHER, 136 }, 137 [MLX5_EXPANSION_OUTER_IPV4_UDP] = { 138 .next = RTE_FLOW_EXPAND_RSS_NEXT(MLX5_EXPANSION_VXLAN, 139 MLX5_EXPANSION_VXLAN_GPE), 140 .type = RTE_FLOW_ITEM_TYPE_UDP, 141 .rss_types = ETH_RSS_NONFRAG_IPV4_UDP, 142 }, 143 [MLX5_EXPANSION_OUTER_IPV4_TCP] = { 144 .type = RTE_FLOW_ITEM_TYPE_TCP, 145 .rss_types = ETH_RSS_NONFRAG_IPV4_TCP, 146 }, 147 [MLX5_EXPANSION_OUTER_IPV6] = { 148 .next = RTE_FLOW_EXPAND_RSS_NEXT 149 (MLX5_EXPANSION_OUTER_IPV6_UDP, 150 MLX5_EXPANSION_OUTER_IPV6_TCP, 151 MLX5_EXPANSION_IPV4, 152 MLX5_EXPANSION_IPV6), 153 .type = RTE_FLOW_ITEM_TYPE_IPV6, 154 .rss_types = ETH_RSS_IPV6 | ETH_RSS_FRAG_IPV6 | 155 ETH_RSS_NONFRAG_IPV6_OTHER, 156 }, 157 [MLX5_EXPANSION_OUTER_IPV6_UDP] = { 158 .next = RTE_FLOW_EXPAND_RSS_NEXT(MLX5_EXPANSION_VXLAN, 159 MLX5_EXPANSION_VXLAN_GPE), 160 .type = RTE_FLOW_ITEM_TYPE_UDP, 161 .rss_types = ETH_RSS_NONFRAG_IPV6_UDP, 162 }, 163 [MLX5_EXPANSION_OUTER_IPV6_TCP] = { 164 .type = RTE_FLOW_ITEM_TYPE_TCP, 165 .rss_types = ETH_RSS_NONFRAG_IPV6_TCP, 166 }, 167 [MLX5_EXPANSION_VXLAN] = { 168 .next = RTE_FLOW_EXPAND_RSS_NEXT(MLX5_EXPANSION_ETH), 169 .type = RTE_FLOW_ITEM_TYPE_VXLAN, 170 }, 171 [MLX5_EXPANSION_VXLAN_GPE] = { 172 .next = RTE_FLOW_EXPAND_RSS_NEXT(MLX5_EXPANSION_ETH, 173 MLX5_EXPANSION_IPV4, 174 MLX5_EXPANSION_IPV6), 175 .type = RTE_FLOW_ITEM_TYPE_VXLAN_GPE, 176 }, 177 [MLX5_EXPANSION_GRE] = { 178 .next = RTE_FLOW_EXPAND_RSS_NEXT(MLX5_EXPANSION_IPV4), 179 .type = RTE_FLOW_ITEM_TYPE_GRE, 180 }, 181 [MLX5_EXPANSION_MPLS] = { 182 .next = RTE_FLOW_EXPAND_RSS_NEXT(MLX5_EXPANSION_IPV4, 183 MLX5_EXPANSION_IPV6), 184 .type = RTE_FLOW_ITEM_TYPE_MPLS, 185 }, 186 [MLX5_EXPANSION_ETH] = { 187 .next = RTE_FLOW_EXPAND_RSS_NEXT(MLX5_EXPANSION_IPV4, 188 MLX5_EXPANSION_IPV6), 189 .type = RTE_FLOW_ITEM_TYPE_ETH, 190 }, 191 [MLX5_EXPANSION_ETH_VLAN] = { 192 .next = RTE_FLOW_EXPAND_RSS_NEXT(MLX5_EXPANSION_VLAN), 193 .type = RTE_FLOW_ITEM_TYPE_ETH, 194 }, 195 [MLX5_EXPANSION_VLAN] = { 196 .next = RTE_FLOW_EXPAND_RSS_NEXT(MLX5_EXPANSION_IPV4, 197 MLX5_EXPANSION_IPV6), 198 .type = RTE_FLOW_ITEM_TYPE_VLAN, 199 }, 200 [MLX5_EXPANSION_IPV4] = { 201 .next = RTE_FLOW_EXPAND_RSS_NEXT(MLX5_EXPANSION_IPV4_UDP, 202 MLX5_EXPANSION_IPV4_TCP), 203 .type = RTE_FLOW_ITEM_TYPE_IPV4, 204 .rss_types = ETH_RSS_IPV4 | ETH_RSS_FRAG_IPV4 | 205 ETH_RSS_NONFRAG_IPV4_OTHER, 206 }, 207 [MLX5_EXPANSION_IPV4_UDP] = { 208 .type = RTE_FLOW_ITEM_TYPE_UDP, 209 .rss_types = ETH_RSS_NONFRAG_IPV4_UDP, 210 }, 211 [MLX5_EXPANSION_IPV4_TCP] = { 212 .type = RTE_FLOW_ITEM_TYPE_TCP, 213 .rss_types = ETH_RSS_NONFRAG_IPV4_TCP, 214 }, 215 [MLX5_EXPANSION_IPV6] = { 216 .next = RTE_FLOW_EXPAND_RSS_NEXT(MLX5_EXPANSION_IPV6_UDP, 217 MLX5_EXPANSION_IPV6_TCP), 218 .type = RTE_FLOW_ITEM_TYPE_IPV6, 219 .rss_types = ETH_RSS_IPV6 | ETH_RSS_FRAG_IPV6 | 220 ETH_RSS_NONFRAG_IPV6_OTHER, 221 }, 222 [MLX5_EXPANSION_IPV6_UDP] = { 223 .type = RTE_FLOW_ITEM_TYPE_UDP, 224 .rss_types = ETH_RSS_NONFRAG_IPV6_UDP, 225 }, 226 [MLX5_EXPANSION_IPV6_TCP] = { 227 .type = RTE_FLOW_ITEM_TYPE_TCP, 228 .rss_types = ETH_RSS_NONFRAG_IPV6_TCP, 229 }, 230 }; 231 232 static const struct rte_flow_ops mlx5_flow_ops = { 233 .validate = mlx5_flow_validate, 234 .create = mlx5_flow_create, 235 .destroy = mlx5_flow_destroy, 236 .flush = mlx5_flow_flush, 237 .isolate = mlx5_flow_isolate, 238 .query = mlx5_flow_query, 239 }; 240 241 /* Convert FDIR request to Generic flow. */ 242 struct mlx5_fdir { 243 struct rte_flow_attr attr; 244 struct rte_flow_item items[4]; 245 struct rte_flow_item_eth l2; 246 struct rte_flow_item_eth l2_mask; 247 union { 248 struct rte_flow_item_ipv4 ipv4; 249 struct rte_flow_item_ipv6 ipv6; 250 } l3; 251 union { 252 struct rte_flow_item_ipv4 ipv4; 253 struct rte_flow_item_ipv6 ipv6; 254 } l3_mask; 255 union { 256 struct rte_flow_item_udp udp; 257 struct rte_flow_item_tcp tcp; 258 } l4; 259 union { 260 struct rte_flow_item_udp udp; 261 struct rte_flow_item_tcp tcp; 262 } l4_mask; 263 struct rte_flow_action actions[2]; 264 struct rte_flow_action_queue queue; 265 }; 266 267 /* Map of Verbs to Flow priority with 8 Verbs priorities. */ 268 static const uint32_t priority_map_3[][MLX5_PRIORITY_MAP_MAX] = { 269 { 0, 1, 2 }, { 2, 3, 4 }, { 5, 6, 7 }, 270 }; 271 272 /* Map of Verbs to Flow priority with 16 Verbs priorities. */ 273 static const uint32_t priority_map_5[][MLX5_PRIORITY_MAP_MAX] = { 274 { 0, 1, 2 }, { 3, 4, 5 }, { 6, 7, 8 }, 275 { 9, 10, 11 }, { 12, 13, 14 }, 276 }; 277 278 /* Tunnel information. */ 279 struct mlx5_flow_tunnel_info { 280 uint64_t tunnel; /**< Tunnel bit (see MLX5_FLOW_*). */ 281 uint32_t ptype; /**< Tunnel Ptype (see RTE_PTYPE_*). */ 282 }; 283 284 static struct mlx5_flow_tunnel_info tunnels_info[] = { 285 { 286 .tunnel = MLX5_FLOW_LAYER_VXLAN, 287 .ptype = RTE_PTYPE_TUNNEL_VXLAN | RTE_PTYPE_L4_UDP, 288 }, 289 { 290 .tunnel = MLX5_FLOW_LAYER_GENEVE, 291 .ptype = RTE_PTYPE_TUNNEL_GENEVE | RTE_PTYPE_L4_UDP, 292 }, 293 { 294 .tunnel = MLX5_FLOW_LAYER_VXLAN_GPE, 295 .ptype = RTE_PTYPE_TUNNEL_VXLAN_GPE | RTE_PTYPE_L4_UDP, 296 }, 297 { 298 .tunnel = MLX5_FLOW_LAYER_GRE, 299 .ptype = RTE_PTYPE_TUNNEL_GRE, 300 }, 301 { 302 .tunnel = MLX5_FLOW_LAYER_MPLS | MLX5_FLOW_LAYER_OUTER_L4_UDP, 303 .ptype = RTE_PTYPE_TUNNEL_MPLS_IN_UDP | RTE_PTYPE_L4_UDP, 304 }, 305 { 306 .tunnel = MLX5_FLOW_LAYER_MPLS, 307 .ptype = RTE_PTYPE_TUNNEL_MPLS_IN_GRE, 308 }, 309 { 310 .tunnel = MLX5_FLOW_LAYER_NVGRE, 311 .ptype = RTE_PTYPE_TUNNEL_NVGRE, 312 }, 313 { 314 .tunnel = MLX5_FLOW_LAYER_IPIP, 315 .ptype = RTE_PTYPE_TUNNEL_IP, 316 }, 317 { 318 .tunnel = MLX5_FLOW_LAYER_IPV6_ENCAP, 319 .ptype = RTE_PTYPE_TUNNEL_IP, 320 }, 321 }; 322 323 enum mlx5_feature_name { 324 MLX5_HAIRPIN_RX, 325 MLX5_HAIRPIN_TX, 326 MLX5_APPLICATION, 327 }; 328 329 /** 330 * Translate tag ID to register. 331 * 332 * @param[in] dev 333 * Pointer to the Ethernet device structure. 334 * @param[in] feature 335 * The feature that request the register. 336 * @param[in] id 337 * The request register ID. 338 * @param[out] error 339 * Error description in case of any. 340 * 341 * @return 342 * The request register on success, a negative errno 343 * value otherwise and rte_errno is set. 344 */ 345 __rte_unused 346 static enum modify_reg flow_get_reg_id(struct rte_eth_dev *dev, 347 enum mlx5_feature_name feature, 348 uint32_t id, 349 struct rte_flow_error *error) 350 { 351 static enum modify_reg id2reg[] = { 352 [0] = REG_A, 353 [1] = REG_C_2, 354 [2] = REG_C_3, 355 [3] = REG_C_4, 356 [4] = REG_B,}; 357 358 dev = (void *)dev; 359 switch (feature) { 360 case MLX5_HAIRPIN_RX: 361 return REG_B; 362 case MLX5_HAIRPIN_TX: 363 return REG_A; 364 case MLX5_APPLICATION: 365 if (id > 4) 366 return rte_flow_error_set(error, EINVAL, 367 RTE_FLOW_ERROR_TYPE_ITEM, 368 NULL, "invalid tag id"); 369 return id2reg[id]; 370 } 371 return rte_flow_error_set(error, EINVAL, RTE_FLOW_ERROR_TYPE_ITEM, 372 NULL, "invalid feature name"); 373 } 374 375 /** 376 * Discover the maximum number of priority available. 377 * 378 * @param[in] dev 379 * Pointer to the Ethernet device structure. 380 * 381 * @return 382 * number of supported flow priority on success, a negative errno 383 * value otherwise and rte_errno is set. 384 */ 385 int 386 mlx5_flow_discover_priorities(struct rte_eth_dev *dev) 387 { 388 struct mlx5_priv *priv = dev->data->dev_private; 389 struct { 390 struct ibv_flow_attr attr; 391 struct ibv_flow_spec_eth eth; 392 struct ibv_flow_spec_action_drop drop; 393 } flow_attr = { 394 .attr = { 395 .num_of_specs = 2, 396 .port = (uint8_t)priv->ibv_port, 397 }, 398 .eth = { 399 .type = IBV_FLOW_SPEC_ETH, 400 .size = sizeof(struct ibv_flow_spec_eth), 401 }, 402 .drop = { 403 .size = sizeof(struct ibv_flow_spec_action_drop), 404 .type = IBV_FLOW_SPEC_ACTION_DROP, 405 }, 406 }; 407 struct ibv_flow *flow; 408 struct mlx5_hrxq *drop = mlx5_hrxq_drop_new(dev); 409 uint16_t vprio[] = { 8, 16 }; 410 int i; 411 int priority = 0; 412 413 if (!drop) { 414 rte_errno = ENOTSUP; 415 return -rte_errno; 416 } 417 for (i = 0; i != RTE_DIM(vprio); i++) { 418 flow_attr.attr.priority = vprio[i] - 1; 419 flow = mlx5_glue->create_flow(drop->qp, &flow_attr.attr); 420 if (!flow) 421 break; 422 claim_zero(mlx5_glue->destroy_flow(flow)); 423 priority = vprio[i]; 424 } 425 mlx5_hrxq_drop_release(dev); 426 switch (priority) { 427 case 8: 428 priority = RTE_DIM(priority_map_3); 429 break; 430 case 16: 431 priority = RTE_DIM(priority_map_5); 432 break; 433 default: 434 rte_errno = ENOTSUP; 435 DRV_LOG(ERR, 436 "port %u verbs maximum priority: %d expected 8/16", 437 dev->data->port_id, priority); 438 return -rte_errno; 439 } 440 DRV_LOG(INFO, "port %u flow maximum priority: %d", 441 dev->data->port_id, priority); 442 return priority; 443 } 444 445 /** 446 * Adjust flow priority based on the highest layer and the request priority. 447 * 448 * @param[in] dev 449 * Pointer to the Ethernet device structure. 450 * @param[in] priority 451 * The rule base priority. 452 * @param[in] subpriority 453 * The priority based on the items. 454 * 455 * @return 456 * The new priority. 457 */ 458 uint32_t mlx5_flow_adjust_priority(struct rte_eth_dev *dev, int32_t priority, 459 uint32_t subpriority) 460 { 461 uint32_t res = 0; 462 struct mlx5_priv *priv = dev->data->dev_private; 463 464 switch (priv->config.flow_prio) { 465 case RTE_DIM(priority_map_3): 466 res = priority_map_3[priority][subpriority]; 467 break; 468 case RTE_DIM(priority_map_5): 469 res = priority_map_5[priority][subpriority]; 470 break; 471 } 472 return res; 473 } 474 475 /** 476 * Verify the @p item specifications (spec, last, mask) are compatible with the 477 * NIC capabilities. 478 * 479 * @param[in] item 480 * Item specification. 481 * @param[in] mask 482 * @p item->mask or flow default bit-masks. 483 * @param[in] nic_mask 484 * Bit-masks covering supported fields by the NIC to compare with user mask. 485 * @param[in] size 486 * Bit-masks size in bytes. 487 * @param[out] error 488 * Pointer to error structure. 489 * 490 * @return 491 * 0 on success, a negative errno value otherwise and rte_errno is set. 492 */ 493 int 494 mlx5_flow_item_acceptable(const struct rte_flow_item *item, 495 const uint8_t *mask, 496 const uint8_t *nic_mask, 497 unsigned int size, 498 struct rte_flow_error *error) 499 { 500 unsigned int i; 501 502 assert(nic_mask); 503 for (i = 0; i < size; ++i) 504 if ((nic_mask[i] | mask[i]) != nic_mask[i]) 505 return rte_flow_error_set(error, ENOTSUP, 506 RTE_FLOW_ERROR_TYPE_ITEM, 507 item, 508 "mask enables non supported" 509 " bits"); 510 if (!item->spec && (item->mask || item->last)) 511 return rte_flow_error_set(error, EINVAL, 512 RTE_FLOW_ERROR_TYPE_ITEM, item, 513 "mask/last without a spec is not" 514 " supported"); 515 if (item->spec && item->last) { 516 uint8_t spec[size]; 517 uint8_t last[size]; 518 unsigned int i; 519 int ret; 520 521 for (i = 0; i < size; ++i) { 522 spec[i] = ((const uint8_t *)item->spec)[i] & mask[i]; 523 last[i] = ((const uint8_t *)item->last)[i] & mask[i]; 524 } 525 ret = memcmp(spec, last, size); 526 if (ret != 0) 527 return rte_flow_error_set(error, EINVAL, 528 RTE_FLOW_ERROR_TYPE_ITEM, 529 item, 530 "range is not valid"); 531 } 532 return 0; 533 } 534 535 /** 536 * Adjust the hash fields according to the @p flow information. 537 * 538 * @param[in] dev_flow. 539 * Pointer to the mlx5_flow. 540 * @param[in] tunnel 541 * 1 when the hash field is for a tunnel item. 542 * @param[in] layer_types 543 * ETH_RSS_* types. 544 * @param[in] hash_fields 545 * Item hash fields. 546 * 547 * @return 548 * The hash fields that should be used. 549 */ 550 uint64_t 551 mlx5_flow_hashfields_adjust(struct mlx5_flow *dev_flow, 552 int tunnel __rte_unused, uint64_t layer_types, 553 uint64_t hash_fields) 554 { 555 struct rte_flow *flow = dev_flow->flow; 556 #ifdef HAVE_IBV_DEVICE_TUNNEL_SUPPORT 557 int rss_request_inner = flow->rss.level >= 2; 558 559 /* Check RSS hash level for tunnel. */ 560 if (tunnel && rss_request_inner) 561 hash_fields |= IBV_RX_HASH_INNER; 562 else if (tunnel || rss_request_inner) 563 return 0; 564 #endif 565 /* Check if requested layer matches RSS hash fields. */ 566 if (!(flow->rss.types & layer_types)) 567 return 0; 568 return hash_fields; 569 } 570 571 /** 572 * Lookup and set the ptype in the data Rx part. A single Ptype can be used, 573 * if several tunnel rules are used on this queue, the tunnel ptype will be 574 * cleared. 575 * 576 * @param rxq_ctrl 577 * Rx queue to update. 578 */ 579 static void 580 flow_rxq_tunnel_ptype_update(struct mlx5_rxq_ctrl *rxq_ctrl) 581 { 582 unsigned int i; 583 uint32_t tunnel_ptype = 0; 584 585 /* Look up for the ptype to use. */ 586 for (i = 0; i != MLX5_FLOW_TUNNEL; ++i) { 587 if (!rxq_ctrl->flow_tunnels_n[i]) 588 continue; 589 if (!tunnel_ptype) { 590 tunnel_ptype = tunnels_info[i].ptype; 591 } else { 592 tunnel_ptype = 0; 593 break; 594 } 595 } 596 rxq_ctrl->rxq.tunnel = tunnel_ptype; 597 } 598 599 /** 600 * Set the Rx queue flags (Mark/Flag and Tunnel Ptypes) according to the devive 601 * flow. 602 * 603 * @param[in] dev 604 * Pointer to the Ethernet device structure. 605 * @param[in] dev_flow 606 * Pointer to device flow structure. 607 */ 608 static void 609 flow_drv_rxq_flags_set(struct rte_eth_dev *dev, struct mlx5_flow *dev_flow) 610 { 611 struct mlx5_priv *priv = dev->data->dev_private; 612 struct rte_flow *flow = dev_flow->flow; 613 const int mark = !!(dev_flow->actions & 614 (MLX5_FLOW_ACTION_FLAG | MLX5_FLOW_ACTION_MARK)); 615 const int tunnel = !!(dev_flow->layers & MLX5_FLOW_LAYER_TUNNEL); 616 unsigned int i; 617 618 for (i = 0; i != flow->rss.queue_num; ++i) { 619 int idx = (*flow->queue)[i]; 620 struct mlx5_rxq_ctrl *rxq_ctrl = 621 container_of((*priv->rxqs)[idx], 622 struct mlx5_rxq_ctrl, rxq); 623 624 if (mark) { 625 rxq_ctrl->rxq.mark = 1; 626 rxq_ctrl->flow_mark_n++; 627 } 628 if (tunnel) { 629 unsigned int j; 630 631 /* Increase the counter matching the flow. */ 632 for (j = 0; j != MLX5_FLOW_TUNNEL; ++j) { 633 if ((tunnels_info[j].tunnel & 634 dev_flow->layers) == 635 tunnels_info[j].tunnel) { 636 rxq_ctrl->flow_tunnels_n[j]++; 637 break; 638 } 639 } 640 flow_rxq_tunnel_ptype_update(rxq_ctrl); 641 } 642 } 643 } 644 645 /** 646 * Set the Rx queue flags (Mark/Flag and Tunnel Ptypes) for a flow 647 * 648 * @param[in] dev 649 * Pointer to the Ethernet device structure. 650 * @param[in] flow 651 * Pointer to flow structure. 652 */ 653 static void 654 flow_rxq_flags_set(struct rte_eth_dev *dev, struct rte_flow *flow) 655 { 656 struct mlx5_flow *dev_flow; 657 658 LIST_FOREACH(dev_flow, &flow->dev_flows, next) 659 flow_drv_rxq_flags_set(dev, dev_flow); 660 } 661 662 /** 663 * Clear the Rx queue flags (Mark/Flag and Tunnel Ptype) associated with the 664 * device flow if no other flow uses it with the same kind of request. 665 * 666 * @param dev 667 * Pointer to Ethernet device. 668 * @param[in] dev_flow 669 * Pointer to the device flow. 670 */ 671 static void 672 flow_drv_rxq_flags_trim(struct rte_eth_dev *dev, struct mlx5_flow *dev_flow) 673 { 674 struct mlx5_priv *priv = dev->data->dev_private; 675 struct rte_flow *flow = dev_flow->flow; 676 const int mark = !!(dev_flow->actions & 677 (MLX5_FLOW_ACTION_FLAG | MLX5_FLOW_ACTION_MARK)); 678 const int tunnel = !!(dev_flow->layers & MLX5_FLOW_LAYER_TUNNEL); 679 unsigned int i; 680 681 assert(dev->data->dev_started); 682 for (i = 0; i != flow->rss.queue_num; ++i) { 683 int idx = (*flow->queue)[i]; 684 struct mlx5_rxq_ctrl *rxq_ctrl = 685 container_of((*priv->rxqs)[idx], 686 struct mlx5_rxq_ctrl, rxq); 687 688 if (mark) { 689 rxq_ctrl->flow_mark_n--; 690 rxq_ctrl->rxq.mark = !!rxq_ctrl->flow_mark_n; 691 } 692 if (tunnel) { 693 unsigned int j; 694 695 /* Decrease the counter matching the flow. */ 696 for (j = 0; j != MLX5_FLOW_TUNNEL; ++j) { 697 if ((tunnels_info[j].tunnel & 698 dev_flow->layers) == 699 tunnels_info[j].tunnel) { 700 rxq_ctrl->flow_tunnels_n[j]--; 701 break; 702 } 703 } 704 flow_rxq_tunnel_ptype_update(rxq_ctrl); 705 } 706 } 707 } 708 709 /** 710 * Clear the Rx queue flags (Mark/Flag and Tunnel Ptype) associated with the 711 * @p flow if no other flow uses it with the same kind of request. 712 * 713 * @param dev 714 * Pointer to Ethernet device. 715 * @param[in] flow 716 * Pointer to the flow. 717 */ 718 static void 719 flow_rxq_flags_trim(struct rte_eth_dev *dev, struct rte_flow *flow) 720 { 721 struct mlx5_flow *dev_flow; 722 723 LIST_FOREACH(dev_flow, &flow->dev_flows, next) 724 flow_drv_rxq_flags_trim(dev, dev_flow); 725 } 726 727 /** 728 * Clear the Mark/Flag and Tunnel ptype information in all Rx queues. 729 * 730 * @param dev 731 * Pointer to Ethernet device. 732 */ 733 static void 734 flow_rxq_flags_clear(struct rte_eth_dev *dev) 735 { 736 struct mlx5_priv *priv = dev->data->dev_private; 737 unsigned int i; 738 739 for (i = 0; i != priv->rxqs_n; ++i) { 740 struct mlx5_rxq_ctrl *rxq_ctrl; 741 unsigned int j; 742 743 if (!(*priv->rxqs)[i]) 744 continue; 745 rxq_ctrl = container_of((*priv->rxqs)[i], 746 struct mlx5_rxq_ctrl, rxq); 747 rxq_ctrl->flow_mark_n = 0; 748 rxq_ctrl->rxq.mark = 0; 749 for (j = 0; j != MLX5_FLOW_TUNNEL; ++j) 750 rxq_ctrl->flow_tunnels_n[j] = 0; 751 rxq_ctrl->rxq.tunnel = 0; 752 } 753 } 754 755 /* 756 * return a pointer to the desired action in the list of actions. 757 * 758 * @param[in] actions 759 * The list of actions to search the action in. 760 * @param[in] action 761 * The action to find. 762 * 763 * @return 764 * Pointer to the action in the list, if found. NULL otherwise. 765 */ 766 const struct rte_flow_action * 767 mlx5_flow_find_action(const struct rte_flow_action *actions, 768 enum rte_flow_action_type action) 769 { 770 if (actions == NULL) 771 return NULL; 772 for (; actions->type != RTE_FLOW_ACTION_TYPE_END; actions++) 773 if (actions->type == action) 774 return actions; 775 return NULL; 776 } 777 778 /* 779 * Validate the flag action. 780 * 781 * @param[in] action_flags 782 * Bit-fields that holds the actions detected until now. 783 * @param[in] attr 784 * Attributes of flow that includes this action. 785 * @param[out] error 786 * Pointer to error structure. 787 * 788 * @return 789 * 0 on success, a negative errno value otherwise and rte_errno is set. 790 */ 791 int 792 mlx5_flow_validate_action_flag(uint64_t action_flags, 793 const struct rte_flow_attr *attr, 794 struct rte_flow_error *error) 795 { 796 797 if (action_flags & MLX5_FLOW_ACTION_DROP) 798 return rte_flow_error_set(error, EINVAL, 799 RTE_FLOW_ERROR_TYPE_ACTION, NULL, 800 "can't drop and flag in same flow"); 801 if (action_flags & MLX5_FLOW_ACTION_MARK) 802 return rte_flow_error_set(error, EINVAL, 803 RTE_FLOW_ERROR_TYPE_ACTION, NULL, 804 "can't mark and flag in same flow"); 805 if (action_flags & MLX5_FLOW_ACTION_FLAG) 806 return rte_flow_error_set(error, EINVAL, 807 RTE_FLOW_ERROR_TYPE_ACTION, NULL, 808 "can't have 2 flag" 809 " actions in same flow"); 810 if (attr->egress) 811 return rte_flow_error_set(error, ENOTSUP, 812 RTE_FLOW_ERROR_TYPE_ATTR_EGRESS, NULL, 813 "flag action not supported for " 814 "egress"); 815 return 0; 816 } 817 818 /* 819 * Validate the mark action. 820 * 821 * @param[in] action 822 * Pointer to the queue action. 823 * @param[in] action_flags 824 * Bit-fields that holds the actions detected until now. 825 * @param[in] attr 826 * Attributes of flow that includes this action. 827 * @param[out] error 828 * Pointer to error structure. 829 * 830 * @return 831 * 0 on success, a negative errno value otherwise and rte_errno is set. 832 */ 833 int 834 mlx5_flow_validate_action_mark(const struct rte_flow_action *action, 835 uint64_t action_flags, 836 const struct rte_flow_attr *attr, 837 struct rte_flow_error *error) 838 { 839 const struct rte_flow_action_mark *mark = action->conf; 840 841 if (!mark) 842 return rte_flow_error_set(error, EINVAL, 843 RTE_FLOW_ERROR_TYPE_ACTION, 844 action, 845 "configuration cannot be null"); 846 if (mark->id >= MLX5_FLOW_MARK_MAX) 847 return rte_flow_error_set(error, EINVAL, 848 RTE_FLOW_ERROR_TYPE_ACTION_CONF, 849 &mark->id, 850 "mark id must in 0 <= id < " 851 RTE_STR(MLX5_FLOW_MARK_MAX)); 852 if (action_flags & MLX5_FLOW_ACTION_DROP) 853 return rte_flow_error_set(error, EINVAL, 854 RTE_FLOW_ERROR_TYPE_ACTION, NULL, 855 "can't drop and mark in same flow"); 856 if (action_flags & MLX5_FLOW_ACTION_FLAG) 857 return rte_flow_error_set(error, EINVAL, 858 RTE_FLOW_ERROR_TYPE_ACTION, NULL, 859 "can't flag and mark in same flow"); 860 if (action_flags & MLX5_FLOW_ACTION_MARK) 861 return rte_flow_error_set(error, EINVAL, 862 RTE_FLOW_ERROR_TYPE_ACTION, NULL, 863 "can't have 2 mark actions in same" 864 " flow"); 865 if (attr->egress) 866 return rte_flow_error_set(error, ENOTSUP, 867 RTE_FLOW_ERROR_TYPE_ATTR_EGRESS, NULL, 868 "mark action not supported for " 869 "egress"); 870 return 0; 871 } 872 873 /* 874 * Validate the drop action. 875 * 876 * @param[in] action_flags 877 * Bit-fields that holds the actions detected until now. 878 * @param[in] attr 879 * Attributes of flow that includes this action. 880 * @param[out] error 881 * Pointer to error structure. 882 * 883 * @return 884 * 0 on success, a negative errno value otherwise and rte_errno is set. 885 */ 886 int 887 mlx5_flow_validate_action_drop(uint64_t action_flags, 888 const struct rte_flow_attr *attr, 889 struct rte_flow_error *error) 890 { 891 if (action_flags & MLX5_FLOW_ACTION_FLAG) 892 return rte_flow_error_set(error, EINVAL, 893 RTE_FLOW_ERROR_TYPE_ACTION, NULL, 894 "can't drop and flag in same flow"); 895 if (action_flags & MLX5_FLOW_ACTION_MARK) 896 return rte_flow_error_set(error, EINVAL, 897 RTE_FLOW_ERROR_TYPE_ACTION, NULL, 898 "can't drop and mark in same flow"); 899 if (action_flags & (MLX5_FLOW_FATE_ACTIONS | 900 MLX5_FLOW_FATE_ESWITCH_ACTIONS)) 901 return rte_flow_error_set(error, EINVAL, 902 RTE_FLOW_ERROR_TYPE_ACTION, NULL, 903 "can't have 2 fate actions in" 904 " same flow"); 905 if (attr->egress) 906 return rte_flow_error_set(error, ENOTSUP, 907 RTE_FLOW_ERROR_TYPE_ATTR_EGRESS, NULL, 908 "drop action not supported for " 909 "egress"); 910 return 0; 911 } 912 913 /* 914 * Validate the queue action. 915 * 916 * @param[in] action 917 * Pointer to the queue action. 918 * @param[in] action_flags 919 * Bit-fields that holds the actions detected until now. 920 * @param[in] dev 921 * Pointer to the Ethernet device structure. 922 * @param[in] attr 923 * Attributes of flow that includes this action. 924 * @param[out] error 925 * Pointer to error structure. 926 * 927 * @return 928 * 0 on success, a negative errno value otherwise and rte_errno is set. 929 */ 930 int 931 mlx5_flow_validate_action_queue(const struct rte_flow_action *action, 932 uint64_t action_flags, 933 struct rte_eth_dev *dev, 934 const struct rte_flow_attr *attr, 935 struct rte_flow_error *error) 936 { 937 struct mlx5_priv *priv = dev->data->dev_private; 938 const struct rte_flow_action_queue *queue = action->conf; 939 940 if (action_flags & MLX5_FLOW_FATE_ACTIONS) 941 return rte_flow_error_set(error, EINVAL, 942 RTE_FLOW_ERROR_TYPE_ACTION, NULL, 943 "can't have 2 fate actions in" 944 " same flow"); 945 if (!priv->rxqs_n) 946 return rte_flow_error_set(error, EINVAL, 947 RTE_FLOW_ERROR_TYPE_ACTION_CONF, 948 NULL, "No Rx queues configured"); 949 if (queue->index >= priv->rxqs_n) 950 return rte_flow_error_set(error, EINVAL, 951 RTE_FLOW_ERROR_TYPE_ACTION_CONF, 952 &queue->index, 953 "queue index out of range"); 954 if (!(*priv->rxqs)[queue->index]) 955 return rte_flow_error_set(error, EINVAL, 956 RTE_FLOW_ERROR_TYPE_ACTION_CONF, 957 &queue->index, 958 "queue is not configured"); 959 if (attr->egress) 960 return rte_flow_error_set(error, ENOTSUP, 961 RTE_FLOW_ERROR_TYPE_ATTR_EGRESS, NULL, 962 "queue action not supported for " 963 "egress"); 964 return 0; 965 } 966 967 /* 968 * Validate the rss action. 969 * 970 * @param[in] action 971 * Pointer to the queue action. 972 * @param[in] action_flags 973 * Bit-fields that holds the actions detected until now. 974 * @param[in] dev 975 * Pointer to the Ethernet device structure. 976 * @param[in] attr 977 * Attributes of flow that includes this action. 978 * @param[in] item_flags 979 * Items that were detected. 980 * @param[out] error 981 * Pointer to error structure. 982 * 983 * @return 984 * 0 on success, a negative errno value otherwise and rte_errno is set. 985 */ 986 int 987 mlx5_flow_validate_action_rss(const struct rte_flow_action *action, 988 uint64_t action_flags, 989 struct rte_eth_dev *dev, 990 const struct rte_flow_attr *attr, 991 uint64_t item_flags, 992 struct rte_flow_error *error) 993 { 994 struct mlx5_priv *priv = dev->data->dev_private; 995 const struct rte_flow_action_rss *rss = action->conf; 996 int tunnel = !!(item_flags & MLX5_FLOW_LAYER_TUNNEL); 997 unsigned int i; 998 999 if (action_flags & MLX5_FLOW_FATE_ACTIONS) 1000 return rte_flow_error_set(error, EINVAL, 1001 RTE_FLOW_ERROR_TYPE_ACTION, NULL, 1002 "can't have 2 fate actions" 1003 " in same flow"); 1004 if (rss->func != RTE_ETH_HASH_FUNCTION_DEFAULT && 1005 rss->func != RTE_ETH_HASH_FUNCTION_TOEPLITZ) 1006 return rte_flow_error_set(error, ENOTSUP, 1007 RTE_FLOW_ERROR_TYPE_ACTION_CONF, 1008 &rss->func, 1009 "RSS hash function not supported"); 1010 #ifdef HAVE_IBV_DEVICE_TUNNEL_SUPPORT 1011 if (rss->level > 2) 1012 #else 1013 if (rss->level > 1) 1014 #endif 1015 return rte_flow_error_set(error, ENOTSUP, 1016 RTE_FLOW_ERROR_TYPE_ACTION_CONF, 1017 &rss->level, 1018 "tunnel RSS is not supported"); 1019 /* allow RSS key_len 0 in case of NULL (default) RSS key. */ 1020 if (rss->key_len == 0 && rss->key != NULL) 1021 return rte_flow_error_set(error, ENOTSUP, 1022 RTE_FLOW_ERROR_TYPE_ACTION_CONF, 1023 &rss->key_len, 1024 "RSS hash key length 0"); 1025 if (rss->key_len > 0 && rss->key_len < MLX5_RSS_HASH_KEY_LEN) 1026 return rte_flow_error_set(error, ENOTSUP, 1027 RTE_FLOW_ERROR_TYPE_ACTION_CONF, 1028 &rss->key_len, 1029 "RSS hash key too small"); 1030 if (rss->key_len > MLX5_RSS_HASH_KEY_LEN) 1031 return rte_flow_error_set(error, ENOTSUP, 1032 RTE_FLOW_ERROR_TYPE_ACTION_CONF, 1033 &rss->key_len, 1034 "RSS hash key too large"); 1035 if (rss->queue_num > priv->config.ind_table_max_size) 1036 return rte_flow_error_set(error, ENOTSUP, 1037 RTE_FLOW_ERROR_TYPE_ACTION_CONF, 1038 &rss->queue_num, 1039 "number of queues too large"); 1040 if (rss->types & MLX5_RSS_HF_MASK) 1041 return rte_flow_error_set(error, ENOTSUP, 1042 RTE_FLOW_ERROR_TYPE_ACTION_CONF, 1043 &rss->types, 1044 "some RSS protocols are not" 1045 " supported"); 1046 if (!priv->rxqs_n) 1047 return rte_flow_error_set(error, EINVAL, 1048 RTE_FLOW_ERROR_TYPE_ACTION_CONF, 1049 NULL, "No Rx queues configured"); 1050 if (!rss->queue_num) 1051 return rte_flow_error_set(error, EINVAL, 1052 RTE_FLOW_ERROR_TYPE_ACTION_CONF, 1053 NULL, "No queues configured"); 1054 for (i = 0; i != rss->queue_num; ++i) { 1055 if (!(*priv->rxqs)[rss->queue[i]]) 1056 return rte_flow_error_set 1057 (error, EINVAL, RTE_FLOW_ERROR_TYPE_ACTION_CONF, 1058 &rss->queue[i], "queue is not configured"); 1059 } 1060 if (attr->egress) 1061 return rte_flow_error_set(error, ENOTSUP, 1062 RTE_FLOW_ERROR_TYPE_ATTR_EGRESS, NULL, 1063 "rss action not supported for " 1064 "egress"); 1065 if (rss->level > 1 && !tunnel) 1066 return rte_flow_error_set(error, EINVAL, 1067 RTE_FLOW_ERROR_TYPE_ACTION_CONF, NULL, 1068 "inner RSS is not supported for " 1069 "non-tunnel flows"); 1070 return 0; 1071 } 1072 1073 /* 1074 * Validate the count action. 1075 * 1076 * @param[in] dev 1077 * Pointer to the Ethernet device structure. 1078 * @param[in] attr 1079 * Attributes of flow that includes this action. 1080 * @param[out] error 1081 * Pointer to error structure. 1082 * 1083 * @return 1084 * 0 on success, a negative errno value otherwise and rte_errno is set. 1085 */ 1086 int 1087 mlx5_flow_validate_action_count(struct rte_eth_dev *dev __rte_unused, 1088 const struct rte_flow_attr *attr, 1089 struct rte_flow_error *error) 1090 { 1091 if (attr->egress) 1092 return rte_flow_error_set(error, ENOTSUP, 1093 RTE_FLOW_ERROR_TYPE_ATTR_EGRESS, NULL, 1094 "count action not supported for " 1095 "egress"); 1096 return 0; 1097 } 1098 1099 /** 1100 * Verify the @p attributes will be correctly understood by the NIC and store 1101 * them in the @p flow if everything is correct. 1102 * 1103 * @param[in] dev 1104 * Pointer to the Ethernet device structure. 1105 * @param[in] attributes 1106 * Pointer to flow attributes 1107 * @param[out] error 1108 * Pointer to error structure. 1109 * 1110 * @return 1111 * 0 on success, a negative errno value otherwise and rte_errno is set. 1112 */ 1113 int 1114 mlx5_flow_validate_attributes(struct rte_eth_dev *dev, 1115 const struct rte_flow_attr *attributes, 1116 struct rte_flow_error *error) 1117 { 1118 struct mlx5_priv *priv = dev->data->dev_private; 1119 uint32_t priority_max = priv->config.flow_prio - 1; 1120 1121 if (attributes->group) 1122 return rte_flow_error_set(error, ENOTSUP, 1123 RTE_FLOW_ERROR_TYPE_ATTR_GROUP, 1124 NULL, "groups is not supported"); 1125 if (attributes->priority != MLX5_FLOW_PRIO_RSVD && 1126 attributes->priority >= priority_max) 1127 return rte_flow_error_set(error, ENOTSUP, 1128 RTE_FLOW_ERROR_TYPE_ATTR_PRIORITY, 1129 NULL, "priority out of range"); 1130 if (attributes->egress) 1131 return rte_flow_error_set(error, ENOTSUP, 1132 RTE_FLOW_ERROR_TYPE_ATTR_EGRESS, NULL, 1133 "egress is not supported"); 1134 if (attributes->transfer && !priv->config.dv_esw_en) 1135 return rte_flow_error_set(error, ENOTSUP, 1136 RTE_FLOW_ERROR_TYPE_ATTR_TRANSFER, 1137 NULL, "transfer is not supported"); 1138 if (!attributes->ingress) 1139 return rte_flow_error_set(error, EINVAL, 1140 RTE_FLOW_ERROR_TYPE_ATTR_INGRESS, 1141 NULL, 1142 "ingress attribute is mandatory"); 1143 return 0; 1144 } 1145 1146 /** 1147 * Validate ICMP6 item. 1148 * 1149 * @param[in] item 1150 * Item specification. 1151 * @param[in] item_flags 1152 * Bit-fields that holds the items detected until now. 1153 * @param[out] error 1154 * Pointer to error structure. 1155 * 1156 * @return 1157 * 0 on success, a negative errno value otherwise and rte_errno is set. 1158 */ 1159 int 1160 mlx5_flow_validate_item_icmp6(const struct rte_flow_item *item, 1161 uint64_t item_flags, 1162 uint8_t target_protocol, 1163 struct rte_flow_error *error) 1164 { 1165 const struct rte_flow_item_icmp6 *mask = item->mask; 1166 const int tunnel = !!(item_flags & MLX5_FLOW_LAYER_TUNNEL); 1167 const uint64_t l3m = tunnel ? MLX5_FLOW_LAYER_INNER_L3_IPV6 : 1168 MLX5_FLOW_LAYER_OUTER_L3_IPV6; 1169 const uint64_t l4m = tunnel ? MLX5_FLOW_LAYER_INNER_L4 : 1170 MLX5_FLOW_LAYER_OUTER_L4; 1171 int ret; 1172 1173 if (target_protocol != 0xFF && target_protocol != IPPROTO_ICMPV6) 1174 return rte_flow_error_set(error, EINVAL, 1175 RTE_FLOW_ERROR_TYPE_ITEM, item, 1176 "protocol filtering not compatible" 1177 " with ICMP6 layer"); 1178 if (!(item_flags & l3m)) 1179 return rte_flow_error_set(error, EINVAL, 1180 RTE_FLOW_ERROR_TYPE_ITEM, item, 1181 "IPv6 is mandatory to filter on" 1182 " ICMP6"); 1183 if (item_flags & l4m) 1184 return rte_flow_error_set(error, EINVAL, 1185 RTE_FLOW_ERROR_TYPE_ITEM, item, 1186 "multiple L4 layers not supported"); 1187 if (!mask) 1188 mask = &rte_flow_item_icmp6_mask; 1189 ret = mlx5_flow_item_acceptable 1190 (item, (const uint8_t *)mask, 1191 (const uint8_t *)&rte_flow_item_icmp6_mask, 1192 sizeof(struct rte_flow_item_icmp6), error); 1193 if (ret < 0) 1194 return ret; 1195 return 0; 1196 } 1197 1198 /** 1199 * Validate ICMP item. 1200 * 1201 * @param[in] item 1202 * Item specification. 1203 * @param[in] item_flags 1204 * Bit-fields that holds the items detected until now. 1205 * @param[out] error 1206 * Pointer to error structure. 1207 * 1208 * @return 1209 * 0 on success, a negative errno value otherwise and rte_errno is set. 1210 */ 1211 int 1212 mlx5_flow_validate_item_icmp(const struct rte_flow_item *item, 1213 uint64_t item_flags, 1214 uint8_t target_protocol, 1215 struct rte_flow_error *error) 1216 { 1217 const struct rte_flow_item_icmp *mask = item->mask; 1218 const int tunnel = !!(item_flags & MLX5_FLOW_LAYER_TUNNEL); 1219 const uint64_t l3m = tunnel ? MLX5_FLOW_LAYER_INNER_L3_IPV4 : 1220 MLX5_FLOW_LAYER_OUTER_L3_IPV4; 1221 const uint64_t l4m = tunnel ? MLX5_FLOW_LAYER_INNER_L4 : 1222 MLX5_FLOW_LAYER_OUTER_L4; 1223 int ret; 1224 1225 if (target_protocol != 0xFF && target_protocol != IPPROTO_ICMP) 1226 return rte_flow_error_set(error, EINVAL, 1227 RTE_FLOW_ERROR_TYPE_ITEM, item, 1228 "protocol filtering not compatible" 1229 " with ICMP layer"); 1230 if (!(item_flags & l3m)) 1231 return rte_flow_error_set(error, EINVAL, 1232 RTE_FLOW_ERROR_TYPE_ITEM, item, 1233 "IPv4 is mandatory to filter" 1234 " on ICMP"); 1235 if (item_flags & l4m) 1236 return rte_flow_error_set(error, EINVAL, 1237 RTE_FLOW_ERROR_TYPE_ITEM, item, 1238 "multiple L4 layers not supported"); 1239 if (!mask) 1240 mask = &rte_flow_item_icmp_mask; 1241 ret = mlx5_flow_item_acceptable 1242 (item, (const uint8_t *)mask, 1243 (const uint8_t *)&rte_flow_item_icmp_mask, 1244 sizeof(struct rte_flow_item_icmp), error); 1245 if (ret < 0) 1246 return ret; 1247 return 0; 1248 } 1249 1250 /** 1251 * Validate Ethernet item. 1252 * 1253 * @param[in] item 1254 * Item specification. 1255 * @param[in] item_flags 1256 * Bit-fields that holds the items detected until now. 1257 * @param[out] error 1258 * Pointer to error structure. 1259 * 1260 * @return 1261 * 0 on success, a negative errno value otherwise and rte_errno is set. 1262 */ 1263 int 1264 mlx5_flow_validate_item_eth(const struct rte_flow_item *item, 1265 uint64_t item_flags, 1266 struct rte_flow_error *error) 1267 { 1268 const struct rte_flow_item_eth *mask = item->mask; 1269 const struct rte_flow_item_eth nic_mask = { 1270 .dst.addr_bytes = "\xff\xff\xff\xff\xff\xff", 1271 .src.addr_bytes = "\xff\xff\xff\xff\xff\xff", 1272 .type = RTE_BE16(0xffff), 1273 }; 1274 int ret; 1275 int tunnel = !!(item_flags & MLX5_FLOW_LAYER_TUNNEL); 1276 const uint64_t ethm = tunnel ? MLX5_FLOW_LAYER_INNER_L2 : 1277 MLX5_FLOW_LAYER_OUTER_L2; 1278 1279 if (item_flags & ethm) 1280 return rte_flow_error_set(error, ENOTSUP, 1281 RTE_FLOW_ERROR_TYPE_ITEM, item, 1282 "multiple L2 layers not supported"); 1283 if ((!tunnel && (item_flags & MLX5_FLOW_LAYER_OUTER_L3)) || 1284 (tunnel && (item_flags & MLX5_FLOW_LAYER_INNER_L3))) 1285 return rte_flow_error_set(error, EINVAL, 1286 RTE_FLOW_ERROR_TYPE_ITEM, item, 1287 "L2 layer should not follow " 1288 "L3 layers"); 1289 if ((!tunnel && (item_flags & MLX5_FLOW_LAYER_OUTER_VLAN)) || 1290 (tunnel && (item_flags & MLX5_FLOW_LAYER_INNER_VLAN))) 1291 return rte_flow_error_set(error, EINVAL, 1292 RTE_FLOW_ERROR_TYPE_ITEM, item, 1293 "L2 layer should not follow VLAN"); 1294 if (!mask) 1295 mask = &rte_flow_item_eth_mask; 1296 ret = mlx5_flow_item_acceptable(item, (const uint8_t *)mask, 1297 (const uint8_t *)&nic_mask, 1298 sizeof(struct rte_flow_item_eth), 1299 error); 1300 return ret; 1301 } 1302 1303 /** 1304 * Validate VLAN item. 1305 * 1306 * @param[in] item 1307 * Item specification. 1308 * @param[in] item_flags 1309 * Bit-fields that holds the items detected until now. 1310 * @param[in] dev 1311 * Ethernet device flow is being created on. 1312 * @param[out] error 1313 * Pointer to error structure. 1314 * 1315 * @return 1316 * 0 on success, a negative errno value otherwise and rte_errno is set. 1317 */ 1318 int 1319 mlx5_flow_validate_item_vlan(const struct rte_flow_item *item, 1320 uint64_t item_flags, 1321 struct rte_eth_dev *dev, 1322 struct rte_flow_error *error) 1323 { 1324 const struct rte_flow_item_vlan *spec = item->spec; 1325 const struct rte_flow_item_vlan *mask = item->mask; 1326 const struct rte_flow_item_vlan nic_mask = { 1327 .tci = RTE_BE16(UINT16_MAX), 1328 .inner_type = RTE_BE16(UINT16_MAX), 1329 }; 1330 uint16_t vlan_tag = 0; 1331 const int tunnel = !!(item_flags & MLX5_FLOW_LAYER_TUNNEL); 1332 int ret; 1333 const uint64_t l34m = tunnel ? (MLX5_FLOW_LAYER_INNER_L3 | 1334 MLX5_FLOW_LAYER_INNER_L4) : 1335 (MLX5_FLOW_LAYER_OUTER_L3 | 1336 MLX5_FLOW_LAYER_OUTER_L4); 1337 const uint64_t vlanm = tunnel ? MLX5_FLOW_LAYER_INNER_VLAN : 1338 MLX5_FLOW_LAYER_OUTER_VLAN; 1339 1340 if (item_flags & vlanm) 1341 return rte_flow_error_set(error, EINVAL, 1342 RTE_FLOW_ERROR_TYPE_ITEM, item, 1343 "multiple VLAN layers not supported"); 1344 else if ((item_flags & l34m) != 0) 1345 return rte_flow_error_set(error, EINVAL, 1346 RTE_FLOW_ERROR_TYPE_ITEM, item, 1347 "VLAN cannot follow L3/L4 layer"); 1348 if (!mask) 1349 mask = &rte_flow_item_vlan_mask; 1350 ret = mlx5_flow_item_acceptable(item, (const uint8_t *)mask, 1351 (const uint8_t *)&nic_mask, 1352 sizeof(struct rte_flow_item_vlan), 1353 error); 1354 if (ret) 1355 return ret; 1356 if (!tunnel && mask->tci != RTE_BE16(0x0fff)) { 1357 struct mlx5_priv *priv = dev->data->dev_private; 1358 1359 if (priv->vmwa_context) { 1360 /* 1361 * Non-NULL context means we have a virtual machine 1362 * and SR-IOV enabled, we have to create VLAN interface 1363 * to make hypervisor to setup E-Switch vport 1364 * context correctly. We avoid creating the multiple 1365 * VLAN interfaces, so we cannot support VLAN tag mask. 1366 */ 1367 return rte_flow_error_set(error, EINVAL, 1368 RTE_FLOW_ERROR_TYPE_ITEM, 1369 item, 1370 "VLAN tag mask is not" 1371 " supported in virtual" 1372 " environment"); 1373 } 1374 } 1375 if (spec) { 1376 vlan_tag = spec->tci; 1377 vlan_tag &= mask->tci; 1378 } 1379 /* 1380 * From verbs perspective an empty VLAN is equivalent 1381 * to a packet without VLAN layer. 1382 */ 1383 if (!vlan_tag) 1384 return rte_flow_error_set(error, EINVAL, 1385 RTE_FLOW_ERROR_TYPE_ITEM_SPEC, 1386 item->spec, 1387 "VLAN cannot be empty"); 1388 return 0; 1389 } 1390 1391 /** 1392 * Validate IPV4 item. 1393 * 1394 * @param[in] item 1395 * Item specification. 1396 * @param[in] item_flags 1397 * Bit-fields that holds the items detected until now. 1398 * @param[in] acc_mask 1399 * Acceptable mask, if NULL default internal default mask 1400 * will be used to check whether item fields are supported. 1401 * @param[out] error 1402 * Pointer to error structure. 1403 * 1404 * @return 1405 * 0 on success, a negative errno value otherwise and rte_errno is set. 1406 */ 1407 int 1408 mlx5_flow_validate_item_ipv4(const struct rte_flow_item *item, 1409 uint64_t item_flags, 1410 uint64_t last_item, 1411 uint16_t ether_type, 1412 const struct rte_flow_item_ipv4 *acc_mask, 1413 struct rte_flow_error *error) 1414 { 1415 const struct rte_flow_item_ipv4 *mask = item->mask; 1416 const struct rte_flow_item_ipv4 *spec = item->spec; 1417 const struct rte_flow_item_ipv4 nic_mask = { 1418 .hdr = { 1419 .src_addr = RTE_BE32(0xffffffff), 1420 .dst_addr = RTE_BE32(0xffffffff), 1421 .type_of_service = 0xff, 1422 .next_proto_id = 0xff, 1423 }, 1424 }; 1425 const int tunnel = !!(item_flags & MLX5_FLOW_LAYER_TUNNEL); 1426 const uint64_t l3m = tunnel ? MLX5_FLOW_LAYER_INNER_L3 : 1427 MLX5_FLOW_LAYER_OUTER_L3; 1428 const uint64_t l4m = tunnel ? MLX5_FLOW_LAYER_INNER_L4 : 1429 MLX5_FLOW_LAYER_OUTER_L4; 1430 int ret; 1431 uint8_t next_proto = 0xFF; 1432 const uint64_t l2_vlan = (MLX5_FLOW_LAYER_L2 | 1433 MLX5_FLOW_LAYER_OUTER_VLAN | 1434 MLX5_FLOW_LAYER_INNER_VLAN); 1435 1436 if ((last_item & l2_vlan) && ether_type && 1437 ether_type != RTE_ETHER_TYPE_IPV4) 1438 return rte_flow_error_set(error, EINVAL, 1439 RTE_FLOW_ERROR_TYPE_ITEM, item, 1440 "IPv4 cannot follow L2/VLAN layer " 1441 "which ether type is not IPv4"); 1442 if (item_flags & MLX5_FLOW_LAYER_IPIP) { 1443 if (mask && spec) 1444 next_proto = mask->hdr.next_proto_id & 1445 spec->hdr.next_proto_id; 1446 if (next_proto == IPPROTO_IPIP || next_proto == IPPROTO_IPV6) 1447 return rte_flow_error_set(error, EINVAL, 1448 RTE_FLOW_ERROR_TYPE_ITEM, 1449 item, 1450 "multiple tunnel " 1451 "not supported"); 1452 } 1453 if (item_flags & MLX5_FLOW_LAYER_IPV6_ENCAP) 1454 return rte_flow_error_set(error, EINVAL, 1455 RTE_FLOW_ERROR_TYPE_ITEM, item, 1456 "wrong tunnel type - IPv6 specified " 1457 "but IPv4 item provided"); 1458 if (item_flags & l3m) 1459 return rte_flow_error_set(error, ENOTSUP, 1460 RTE_FLOW_ERROR_TYPE_ITEM, item, 1461 "multiple L3 layers not supported"); 1462 else if (item_flags & l4m) 1463 return rte_flow_error_set(error, EINVAL, 1464 RTE_FLOW_ERROR_TYPE_ITEM, item, 1465 "L3 cannot follow an L4 layer."); 1466 else if ((item_flags & MLX5_FLOW_LAYER_NVGRE) && 1467 !(item_flags & MLX5_FLOW_LAYER_INNER_L2)) 1468 return rte_flow_error_set(error, EINVAL, 1469 RTE_FLOW_ERROR_TYPE_ITEM, item, 1470 "L3 cannot follow an NVGRE layer."); 1471 if (!mask) 1472 mask = &rte_flow_item_ipv4_mask; 1473 else if (mask->hdr.next_proto_id != 0 && 1474 mask->hdr.next_proto_id != 0xff) 1475 return rte_flow_error_set(error, EINVAL, 1476 RTE_FLOW_ERROR_TYPE_ITEM_MASK, mask, 1477 "partial mask is not supported" 1478 " for protocol"); 1479 ret = mlx5_flow_item_acceptable(item, (const uint8_t *)mask, 1480 acc_mask ? (const uint8_t *)acc_mask 1481 : (const uint8_t *)&nic_mask, 1482 sizeof(struct rte_flow_item_ipv4), 1483 error); 1484 if (ret < 0) 1485 return ret; 1486 return 0; 1487 } 1488 1489 /** 1490 * Validate IPV6 item. 1491 * 1492 * @param[in] item 1493 * Item specification. 1494 * @param[in] item_flags 1495 * Bit-fields that holds the items detected until now. 1496 * @param[in] acc_mask 1497 * Acceptable mask, if NULL default internal default mask 1498 * will be used to check whether item fields are supported. 1499 * @param[out] error 1500 * Pointer to error structure. 1501 * 1502 * @return 1503 * 0 on success, a negative errno value otherwise and rte_errno is set. 1504 */ 1505 int 1506 mlx5_flow_validate_item_ipv6(const struct rte_flow_item *item, 1507 uint64_t item_flags, 1508 uint64_t last_item, 1509 uint16_t ether_type, 1510 const struct rte_flow_item_ipv6 *acc_mask, 1511 struct rte_flow_error *error) 1512 { 1513 const struct rte_flow_item_ipv6 *mask = item->mask; 1514 const struct rte_flow_item_ipv6 *spec = item->spec; 1515 const struct rte_flow_item_ipv6 nic_mask = { 1516 .hdr = { 1517 .src_addr = 1518 "\xff\xff\xff\xff\xff\xff\xff\xff" 1519 "\xff\xff\xff\xff\xff\xff\xff\xff", 1520 .dst_addr = 1521 "\xff\xff\xff\xff\xff\xff\xff\xff" 1522 "\xff\xff\xff\xff\xff\xff\xff\xff", 1523 .vtc_flow = RTE_BE32(0xffffffff), 1524 .proto = 0xff, 1525 .hop_limits = 0xff, 1526 }, 1527 }; 1528 const int tunnel = !!(item_flags & MLX5_FLOW_LAYER_TUNNEL); 1529 const uint64_t l3m = tunnel ? MLX5_FLOW_LAYER_INNER_L3 : 1530 MLX5_FLOW_LAYER_OUTER_L3; 1531 const uint64_t l4m = tunnel ? MLX5_FLOW_LAYER_INNER_L4 : 1532 MLX5_FLOW_LAYER_OUTER_L4; 1533 int ret; 1534 uint8_t next_proto = 0xFF; 1535 const uint64_t l2_vlan = (MLX5_FLOW_LAYER_L2 | 1536 MLX5_FLOW_LAYER_OUTER_VLAN | 1537 MLX5_FLOW_LAYER_INNER_VLAN); 1538 1539 if ((last_item & l2_vlan) && ether_type && 1540 ether_type != RTE_ETHER_TYPE_IPV6) 1541 return rte_flow_error_set(error, EINVAL, 1542 RTE_FLOW_ERROR_TYPE_ITEM, item, 1543 "IPv6 cannot follow L2/VLAN layer " 1544 "which ether type is not IPv6"); 1545 if (item_flags & MLX5_FLOW_LAYER_IPV6_ENCAP) { 1546 if (mask && spec) 1547 next_proto = mask->hdr.proto & spec->hdr.proto; 1548 if (next_proto == IPPROTO_IPIP || next_proto == IPPROTO_IPV6) 1549 return rte_flow_error_set(error, EINVAL, 1550 RTE_FLOW_ERROR_TYPE_ITEM, 1551 item, 1552 "multiple tunnel " 1553 "not supported"); 1554 } 1555 if (item_flags & MLX5_FLOW_LAYER_IPIP) 1556 return rte_flow_error_set(error, EINVAL, 1557 RTE_FLOW_ERROR_TYPE_ITEM, item, 1558 "wrong tunnel type - IPv4 specified " 1559 "but IPv6 item provided"); 1560 if (item_flags & l3m) 1561 return rte_flow_error_set(error, ENOTSUP, 1562 RTE_FLOW_ERROR_TYPE_ITEM, item, 1563 "multiple L3 layers not supported"); 1564 else if (item_flags & l4m) 1565 return rte_flow_error_set(error, EINVAL, 1566 RTE_FLOW_ERROR_TYPE_ITEM, item, 1567 "L3 cannot follow an L4 layer."); 1568 else if ((item_flags & MLX5_FLOW_LAYER_NVGRE) && 1569 !(item_flags & MLX5_FLOW_LAYER_INNER_L2)) 1570 return rte_flow_error_set(error, EINVAL, 1571 RTE_FLOW_ERROR_TYPE_ITEM, item, 1572 "L3 cannot follow an NVGRE layer."); 1573 if (!mask) 1574 mask = &rte_flow_item_ipv6_mask; 1575 ret = mlx5_flow_item_acceptable(item, (const uint8_t *)mask, 1576 acc_mask ? (const uint8_t *)acc_mask 1577 : (const uint8_t *)&nic_mask, 1578 sizeof(struct rte_flow_item_ipv6), 1579 error); 1580 if (ret < 0) 1581 return ret; 1582 return 0; 1583 } 1584 1585 /** 1586 * Validate UDP item. 1587 * 1588 * @param[in] item 1589 * Item specification. 1590 * @param[in] item_flags 1591 * Bit-fields that holds the items detected until now. 1592 * @param[in] target_protocol 1593 * The next protocol in the previous item. 1594 * @param[in] flow_mask 1595 * mlx5 flow-specific (DV, verbs, etc.) supported header fields mask. 1596 * @param[out] error 1597 * Pointer to error structure. 1598 * 1599 * @return 1600 * 0 on success, a negative errno value otherwise and rte_errno is set. 1601 */ 1602 int 1603 mlx5_flow_validate_item_udp(const struct rte_flow_item *item, 1604 uint64_t item_flags, 1605 uint8_t target_protocol, 1606 struct rte_flow_error *error) 1607 { 1608 const struct rte_flow_item_udp *mask = item->mask; 1609 const int tunnel = !!(item_flags & MLX5_FLOW_LAYER_TUNNEL); 1610 const uint64_t l3m = tunnel ? MLX5_FLOW_LAYER_INNER_L3 : 1611 MLX5_FLOW_LAYER_OUTER_L3; 1612 const uint64_t l4m = tunnel ? MLX5_FLOW_LAYER_INNER_L4 : 1613 MLX5_FLOW_LAYER_OUTER_L4; 1614 int ret; 1615 1616 if (target_protocol != 0xff && target_protocol != IPPROTO_UDP) 1617 return rte_flow_error_set(error, EINVAL, 1618 RTE_FLOW_ERROR_TYPE_ITEM, item, 1619 "protocol filtering not compatible" 1620 " with UDP layer"); 1621 if (!(item_flags & l3m)) 1622 return rte_flow_error_set(error, EINVAL, 1623 RTE_FLOW_ERROR_TYPE_ITEM, item, 1624 "L3 is mandatory to filter on L4"); 1625 if (item_flags & l4m) 1626 return rte_flow_error_set(error, EINVAL, 1627 RTE_FLOW_ERROR_TYPE_ITEM, item, 1628 "multiple L4 layers not supported"); 1629 if (!mask) 1630 mask = &rte_flow_item_udp_mask; 1631 ret = mlx5_flow_item_acceptable 1632 (item, (const uint8_t *)mask, 1633 (const uint8_t *)&rte_flow_item_udp_mask, 1634 sizeof(struct rte_flow_item_udp), error); 1635 if (ret < 0) 1636 return ret; 1637 return 0; 1638 } 1639 1640 /** 1641 * Validate TCP item. 1642 * 1643 * @param[in] item 1644 * Item specification. 1645 * @param[in] item_flags 1646 * Bit-fields that holds the items detected until now. 1647 * @param[in] target_protocol 1648 * The next protocol in the previous item. 1649 * @param[out] error 1650 * Pointer to error structure. 1651 * 1652 * @return 1653 * 0 on success, a negative errno value otherwise and rte_errno is set. 1654 */ 1655 int 1656 mlx5_flow_validate_item_tcp(const struct rte_flow_item *item, 1657 uint64_t item_flags, 1658 uint8_t target_protocol, 1659 const struct rte_flow_item_tcp *flow_mask, 1660 struct rte_flow_error *error) 1661 { 1662 const struct rte_flow_item_tcp *mask = item->mask; 1663 const int tunnel = !!(item_flags & MLX5_FLOW_LAYER_TUNNEL); 1664 const uint64_t l3m = tunnel ? MLX5_FLOW_LAYER_INNER_L3 : 1665 MLX5_FLOW_LAYER_OUTER_L3; 1666 const uint64_t l4m = tunnel ? MLX5_FLOW_LAYER_INNER_L4 : 1667 MLX5_FLOW_LAYER_OUTER_L4; 1668 int ret; 1669 1670 assert(flow_mask); 1671 if (target_protocol != 0xff && target_protocol != IPPROTO_TCP) 1672 return rte_flow_error_set(error, EINVAL, 1673 RTE_FLOW_ERROR_TYPE_ITEM, item, 1674 "protocol filtering not compatible" 1675 " with TCP layer"); 1676 if (!(item_flags & l3m)) 1677 return rte_flow_error_set(error, EINVAL, 1678 RTE_FLOW_ERROR_TYPE_ITEM, item, 1679 "L3 is mandatory to filter on L4"); 1680 if (item_flags & l4m) 1681 return rte_flow_error_set(error, EINVAL, 1682 RTE_FLOW_ERROR_TYPE_ITEM, item, 1683 "multiple L4 layers not supported"); 1684 if (!mask) 1685 mask = &rte_flow_item_tcp_mask; 1686 ret = mlx5_flow_item_acceptable 1687 (item, (const uint8_t *)mask, 1688 (const uint8_t *)flow_mask, 1689 sizeof(struct rte_flow_item_tcp), error); 1690 if (ret < 0) 1691 return ret; 1692 return 0; 1693 } 1694 1695 /** 1696 * Validate VXLAN item. 1697 * 1698 * @param[in] item 1699 * Item specification. 1700 * @param[in] item_flags 1701 * Bit-fields that holds the items detected until now. 1702 * @param[in] target_protocol 1703 * The next protocol in the previous item. 1704 * @param[out] error 1705 * Pointer to error structure. 1706 * 1707 * @return 1708 * 0 on success, a negative errno value otherwise and rte_errno is set. 1709 */ 1710 int 1711 mlx5_flow_validate_item_vxlan(const struct rte_flow_item *item, 1712 uint64_t item_flags, 1713 struct rte_flow_error *error) 1714 { 1715 const struct rte_flow_item_vxlan *spec = item->spec; 1716 const struct rte_flow_item_vxlan *mask = item->mask; 1717 int ret; 1718 union vni { 1719 uint32_t vlan_id; 1720 uint8_t vni[4]; 1721 } id = { .vlan_id = 0, }; 1722 uint32_t vlan_id = 0; 1723 1724 1725 if (item_flags & MLX5_FLOW_LAYER_TUNNEL) 1726 return rte_flow_error_set(error, ENOTSUP, 1727 RTE_FLOW_ERROR_TYPE_ITEM, item, 1728 "multiple tunnel layers not" 1729 " supported"); 1730 /* 1731 * Verify only UDPv4 is present as defined in 1732 * https://tools.ietf.org/html/rfc7348 1733 */ 1734 if (!(item_flags & MLX5_FLOW_LAYER_OUTER_L4_UDP)) 1735 return rte_flow_error_set(error, EINVAL, 1736 RTE_FLOW_ERROR_TYPE_ITEM, item, 1737 "no outer UDP layer found"); 1738 if (!mask) 1739 mask = &rte_flow_item_vxlan_mask; 1740 ret = mlx5_flow_item_acceptable 1741 (item, (const uint8_t *)mask, 1742 (const uint8_t *)&rte_flow_item_vxlan_mask, 1743 sizeof(struct rte_flow_item_vxlan), 1744 error); 1745 if (ret < 0) 1746 return ret; 1747 if (spec) { 1748 memcpy(&id.vni[1], spec->vni, 3); 1749 vlan_id = id.vlan_id; 1750 memcpy(&id.vni[1], mask->vni, 3); 1751 vlan_id &= id.vlan_id; 1752 } 1753 /* 1754 * Tunnel id 0 is equivalent as not adding a VXLAN layer, if 1755 * only this layer is defined in the Verbs specification it is 1756 * interpreted as wildcard and all packets will match this 1757 * rule, if it follows a full stack layer (ex: eth / ipv4 / 1758 * udp), all packets matching the layers before will also 1759 * match this rule. To avoid such situation, VNI 0 is 1760 * currently refused. 1761 */ 1762 if (!vlan_id) 1763 return rte_flow_error_set(error, ENOTSUP, 1764 RTE_FLOW_ERROR_TYPE_ITEM, item, 1765 "VXLAN vni cannot be 0"); 1766 if (!(item_flags & MLX5_FLOW_LAYER_OUTER)) 1767 return rte_flow_error_set(error, ENOTSUP, 1768 RTE_FLOW_ERROR_TYPE_ITEM, item, 1769 "VXLAN tunnel must be fully defined"); 1770 return 0; 1771 } 1772 1773 /** 1774 * Validate VXLAN_GPE item. 1775 * 1776 * @param[in] item 1777 * Item specification. 1778 * @param[in] item_flags 1779 * Bit-fields that holds the items detected until now. 1780 * @param[in] priv 1781 * Pointer to the private data structure. 1782 * @param[in] target_protocol 1783 * The next protocol in the previous item. 1784 * @param[out] error 1785 * Pointer to error structure. 1786 * 1787 * @return 1788 * 0 on success, a negative errno value otherwise and rte_errno is set. 1789 */ 1790 int 1791 mlx5_flow_validate_item_vxlan_gpe(const struct rte_flow_item *item, 1792 uint64_t item_flags, 1793 struct rte_eth_dev *dev, 1794 struct rte_flow_error *error) 1795 { 1796 struct mlx5_priv *priv = dev->data->dev_private; 1797 const struct rte_flow_item_vxlan_gpe *spec = item->spec; 1798 const struct rte_flow_item_vxlan_gpe *mask = item->mask; 1799 int ret; 1800 union vni { 1801 uint32_t vlan_id; 1802 uint8_t vni[4]; 1803 } id = { .vlan_id = 0, }; 1804 uint32_t vlan_id = 0; 1805 1806 if (!priv->config.l3_vxlan_en) 1807 return rte_flow_error_set(error, ENOTSUP, 1808 RTE_FLOW_ERROR_TYPE_ITEM, item, 1809 "L3 VXLAN is not enabled by device" 1810 " parameter and/or not configured in" 1811 " firmware"); 1812 if (item_flags & MLX5_FLOW_LAYER_TUNNEL) 1813 return rte_flow_error_set(error, ENOTSUP, 1814 RTE_FLOW_ERROR_TYPE_ITEM, item, 1815 "multiple tunnel layers not" 1816 " supported"); 1817 /* 1818 * Verify only UDPv4 is present as defined in 1819 * https://tools.ietf.org/html/rfc7348 1820 */ 1821 if (!(item_flags & MLX5_FLOW_LAYER_OUTER_L4_UDP)) 1822 return rte_flow_error_set(error, EINVAL, 1823 RTE_FLOW_ERROR_TYPE_ITEM, item, 1824 "no outer UDP layer found"); 1825 if (!mask) 1826 mask = &rte_flow_item_vxlan_gpe_mask; 1827 ret = mlx5_flow_item_acceptable 1828 (item, (const uint8_t *)mask, 1829 (const uint8_t *)&rte_flow_item_vxlan_gpe_mask, 1830 sizeof(struct rte_flow_item_vxlan_gpe), 1831 error); 1832 if (ret < 0) 1833 return ret; 1834 if (spec) { 1835 if (spec->protocol) 1836 return rte_flow_error_set(error, ENOTSUP, 1837 RTE_FLOW_ERROR_TYPE_ITEM, 1838 item, 1839 "VxLAN-GPE protocol" 1840 " not supported"); 1841 memcpy(&id.vni[1], spec->vni, 3); 1842 vlan_id = id.vlan_id; 1843 memcpy(&id.vni[1], mask->vni, 3); 1844 vlan_id &= id.vlan_id; 1845 } 1846 /* 1847 * Tunnel id 0 is equivalent as not adding a VXLAN layer, if only this 1848 * layer is defined in the Verbs specification it is interpreted as 1849 * wildcard and all packets will match this rule, if it follows a full 1850 * stack layer (ex: eth / ipv4 / udp), all packets matching the layers 1851 * before will also match this rule. To avoid such situation, VNI 0 1852 * is currently refused. 1853 */ 1854 if (!vlan_id) 1855 return rte_flow_error_set(error, ENOTSUP, 1856 RTE_FLOW_ERROR_TYPE_ITEM, item, 1857 "VXLAN-GPE vni cannot be 0"); 1858 if (!(item_flags & MLX5_FLOW_LAYER_OUTER)) 1859 return rte_flow_error_set(error, ENOTSUP, 1860 RTE_FLOW_ERROR_TYPE_ITEM, item, 1861 "VXLAN-GPE tunnel must be fully" 1862 " defined"); 1863 return 0; 1864 } 1865 /** 1866 * Validate GRE Key item. 1867 * 1868 * @param[in] item 1869 * Item specification. 1870 * @param[in] item_flags 1871 * Bit flags to mark detected items. 1872 * @param[in] gre_item 1873 * Pointer to gre_item 1874 * @param[out] error 1875 * Pointer to error structure. 1876 * 1877 * @return 1878 * 0 on success, a negative errno value otherwise and rte_errno is set. 1879 */ 1880 int 1881 mlx5_flow_validate_item_gre_key(const struct rte_flow_item *item, 1882 uint64_t item_flags, 1883 const struct rte_flow_item *gre_item, 1884 struct rte_flow_error *error) 1885 { 1886 const rte_be32_t *mask = item->mask; 1887 int ret = 0; 1888 rte_be32_t gre_key_default_mask = RTE_BE32(UINT32_MAX); 1889 const struct rte_flow_item_gre *gre_spec = gre_item->spec; 1890 const struct rte_flow_item_gre *gre_mask = gre_item->mask; 1891 1892 if (item_flags & MLX5_FLOW_LAYER_GRE_KEY) 1893 return rte_flow_error_set(error, ENOTSUP, 1894 RTE_FLOW_ERROR_TYPE_ITEM, item, 1895 "Multiple GRE key not support"); 1896 if (!(item_flags & MLX5_FLOW_LAYER_GRE)) 1897 return rte_flow_error_set(error, ENOTSUP, 1898 RTE_FLOW_ERROR_TYPE_ITEM, item, 1899 "No preceding GRE header"); 1900 if (item_flags & MLX5_FLOW_LAYER_INNER) 1901 return rte_flow_error_set(error, ENOTSUP, 1902 RTE_FLOW_ERROR_TYPE_ITEM, item, 1903 "GRE key following a wrong item"); 1904 if (!gre_mask) 1905 gre_mask = &rte_flow_item_gre_mask; 1906 if (gre_spec && (gre_mask->c_rsvd0_ver & RTE_BE16(0x2000)) && 1907 !(gre_spec->c_rsvd0_ver & RTE_BE16(0x2000))) 1908 return rte_flow_error_set(error, EINVAL, 1909 RTE_FLOW_ERROR_TYPE_ITEM, item, 1910 "Key bit must be on"); 1911 1912 if (!mask) 1913 mask = &gre_key_default_mask; 1914 ret = mlx5_flow_item_acceptable 1915 (item, (const uint8_t *)mask, 1916 (const uint8_t *)&gre_key_default_mask, 1917 sizeof(rte_be32_t), error); 1918 return ret; 1919 } 1920 1921 /** 1922 * Validate GRE item. 1923 * 1924 * @param[in] item 1925 * Item specification. 1926 * @param[in] item_flags 1927 * Bit flags to mark detected items. 1928 * @param[in] target_protocol 1929 * The next protocol in the previous item. 1930 * @param[out] error 1931 * Pointer to error structure. 1932 * 1933 * @return 1934 * 0 on success, a negative errno value otherwise and rte_errno is set. 1935 */ 1936 int 1937 mlx5_flow_validate_item_gre(const struct rte_flow_item *item, 1938 uint64_t item_flags, 1939 uint8_t target_protocol, 1940 struct rte_flow_error *error) 1941 { 1942 const struct rte_flow_item_gre *spec __rte_unused = item->spec; 1943 const struct rte_flow_item_gre *mask = item->mask; 1944 int ret; 1945 const struct rte_flow_item_gre nic_mask = { 1946 .c_rsvd0_ver = RTE_BE16(0xB000), 1947 .protocol = RTE_BE16(UINT16_MAX), 1948 }; 1949 1950 if (target_protocol != 0xff && target_protocol != IPPROTO_GRE) 1951 return rte_flow_error_set(error, EINVAL, 1952 RTE_FLOW_ERROR_TYPE_ITEM, item, 1953 "protocol filtering not compatible" 1954 " with this GRE layer"); 1955 if (item_flags & MLX5_FLOW_LAYER_TUNNEL) 1956 return rte_flow_error_set(error, ENOTSUP, 1957 RTE_FLOW_ERROR_TYPE_ITEM, item, 1958 "multiple tunnel layers not" 1959 " supported"); 1960 if (!(item_flags & MLX5_FLOW_LAYER_OUTER_L3)) 1961 return rte_flow_error_set(error, ENOTSUP, 1962 RTE_FLOW_ERROR_TYPE_ITEM, item, 1963 "L3 Layer is missing"); 1964 if (!mask) 1965 mask = &rte_flow_item_gre_mask; 1966 ret = mlx5_flow_item_acceptable 1967 (item, (const uint8_t *)mask, 1968 (const uint8_t *)&nic_mask, 1969 sizeof(struct rte_flow_item_gre), error); 1970 if (ret < 0) 1971 return ret; 1972 #ifndef HAVE_MLX5DV_DR 1973 #ifndef HAVE_IBV_DEVICE_MPLS_SUPPORT 1974 if (spec && (spec->protocol & mask->protocol)) 1975 return rte_flow_error_set(error, ENOTSUP, 1976 RTE_FLOW_ERROR_TYPE_ITEM, item, 1977 "without MPLS support the" 1978 " specification cannot be used for" 1979 " filtering"); 1980 #endif 1981 #endif 1982 return 0; 1983 } 1984 1985 /** 1986 * Validate Geneve item. 1987 * 1988 * @param[in] item 1989 * Item specification. 1990 * @param[in] itemFlags 1991 * Bit-fields that holds the items detected until now. 1992 * @param[in] enPriv 1993 * Pointer to the private data structure. 1994 * @param[out] error 1995 * Pointer to error structure. 1996 * 1997 * @return 1998 * 0 on success, a negative errno value otherwise and rte_errno is set. 1999 */ 2000 2001 int 2002 mlx5_flow_validate_item_geneve(const struct rte_flow_item *item, 2003 uint64_t item_flags, 2004 struct rte_eth_dev *dev, 2005 struct rte_flow_error *error) 2006 { 2007 struct mlx5_priv *priv = dev->data->dev_private; 2008 const struct rte_flow_item_geneve *spec = item->spec; 2009 const struct rte_flow_item_geneve *mask = item->mask; 2010 int ret; 2011 uint16_t gbhdr; 2012 uint8_t opt_len = priv->config.hca_attr.geneve_max_opt_len ? 2013 MLX5_GENEVE_OPT_LEN_1 : MLX5_GENEVE_OPT_LEN_0; 2014 const struct rte_flow_item_geneve nic_mask = { 2015 .ver_opt_len_o_c_rsvd0 = RTE_BE16(0x3f80), 2016 .vni = "\xff\xff\xff", 2017 .protocol = RTE_BE16(UINT16_MAX), 2018 }; 2019 2020 if (!(priv->config.hca_attr.flex_parser_protocols & 2021 MLX5_HCA_FLEX_GENEVE_ENABLED) || 2022 !priv->config.hca_attr.tunnel_stateless_geneve_rx) 2023 return rte_flow_error_set(error, ENOTSUP, 2024 RTE_FLOW_ERROR_TYPE_ITEM, item, 2025 "L3 Geneve is not enabled by device" 2026 " parameter and/or not configured in" 2027 " firmware"); 2028 if (item_flags & MLX5_FLOW_LAYER_TUNNEL) 2029 return rte_flow_error_set(error, ENOTSUP, 2030 RTE_FLOW_ERROR_TYPE_ITEM, item, 2031 "multiple tunnel layers not" 2032 " supported"); 2033 /* 2034 * Verify only UDPv4 is present as defined in 2035 * https://tools.ietf.org/html/rfc7348 2036 */ 2037 if (!(item_flags & MLX5_FLOW_LAYER_OUTER_L4_UDP)) 2038 return rte_flow_error_set(error, EINVAL, 2039 RTE_FLOW_ERROR_TYPE_ITEM, item, 2040 "no outer UDP layer found"); 2041 if (!mask) 2042 mask = &rte_flow_item_geneve_mask; 2043 ret = mlx5_flow_item_acceptable 2044 (item, (const uint8_t *)mask, 2045 (const uint8_t *)&nic_mask, 2046 sizeof(struct rte_flow_item_geneve), error); 2047 if (ret) 2048 return ret; 2049 if (spec) { 2050 gbhdr = rte_be_to_cpu_16(spec->ver_opt_len_o_c_rsvd0); 2051 if (MLX5_GENEVE_VER_VAL(gbhdr) || 2052 MLX5_GENEVE_CRITO_VAL(gbhdr) || 2053 MLX5_GENEVE_RSVD_VAL(gbhdr) || spec->rsvd1) 2054 return rte_flow_error_set(error, ENOTSUP, 2055 RTE_FLOW_ERROR_TYPE_ITEM, 2056 item, 2057 "Geneve protocol unsupported" 2058 " fields are being used"); 2059 if (MLX5_GENEVE_OPTLEN_VAL(gbhdr) > opt_len) 2060 return rte_flow_error_set 2061 (error, ENOTSUP, 2062 RTE_FLOW_ERROR_TYPE_ITEM, 2063 item, 2064 "Unsupported Geneve options length"); 2065 } 2066 if (!(item_flags & MLX5_FLOW_LAYER_OUTER)) 2067 return rte_flow_error_set 2068 (error, ENOTSUP, 2069 RTE_FLOW_ERROR_TYPE_ITEM, item, 2070 "Geneve tunnel must be fully defined"); 2071 return 0; 2072 } 2073 2074 /** 2075 * Validate MPLS item. 2076 * 2077 * @param[in] dev 2078 * Pointer to the rte_eth_dev structure. 2079 * @param[in] item 2080 * Item specification. 2081 * @param[in] item_flags 2082 * Bit-fields that holds the items detected until now. 2083 * @param[in] prev_layer 2084 * The protocol layer indicated in previous item. 2085 * @param[out] error 2086 * Pointer to error structure. 2087 * 2088 * @return 2089 * 0 on success, a negative errno value otherwise and rte_errno is set. 2090 */ 2091 int 2092 mlx5_flow_validate_item_mpls(struct rte_eth_dev *dev __rte_unused, 2093 const struct rte_flow_item *item __rte_unused, 2094 uint64_t item_flags __rte_unused, 2095 uint64_t prev_layer __rte_unused, 2096 struct rte_flow_error *error) 2097 { 2098 #ifdef HAVE_IBV_DEVICE_MPLS_SUPPORT 2099 const struct rte_flow_item_mpls *mask = item->mask; 2100 struct mlx5_priv *priv = dev->data->dev_private; 2101 int ret; 2102 2103 if (!priv->config.mpls_en) 2104 return rte_flow_error_set(error, ENOTSUP, 2105 RTE_FLOW_ERROR_TYPE_ITEM, item, 2106 "MPLS not supported or" 2107 " disabled in firmware" 2108 " configuration."); 2109 /* MPLS over IP, UDP, GRE is allowed */ 2110 if (!(prev_layer & (MLX5_FLOW_LAYER_OUTER_L3 | 2111 MLX5_FLOW_LAYER_OUTER_L4_UDP | 2112 MLX5_FLOW_LAYER_GRE))) 2113 return rte_flow_error_set(error, EINVAL, 2114 RTE_FLOW_ERROR_TYPE_ITEM, item, 2115 "protocol filtering not compatible" 2116 " with MPLS layer"); 2117 /* Multi-tunnel isn't allowed but MPLS over GRE is an exception. */ 2118 if ((item_flags & MLX5_FLOW_LAYER_TUNNEL) && 2119 !(item_flags & MLX5_FLOW_LAYER_GRE)) 2120 return rte_flow_error_set(error, ENOTSUP, 2121 RTE_FLOW_ERROR_TYPE_ITEM, item, 2122 "multiple tunnel layers not" 2123 " supported"); 2124 if (!mask) 2125 mask = &rte_flow_item_mpls_mask; 2126 ret = mlx5_flow_item_acceptable 2127 (item, (const uint8_t *)mask, 2128 (const uint8_t *)&rte_flow_item_mpls_mask, 2129 sizeof(struct rte_flow_item_mpls), error); 2130 if (ret < 0) 2131 return ret; 2132 return 0; 2133 #endif 2134 return rte_flow_error_set(error, ENOTSUP, 2135 RTE_FLOW_ERROR_TYPE_ITEM, item, 2136 "MPLS is not supported by Verbs, please" 2137 " update."); 2138 } 2139 2140 /** 2141 * Validate NVGRE item. 2142 * 2143 * @param[in] item 2144 * Item specification. 2145 * @param[in] item_flags 2146 * Bit flags to mark detected items. 2147 * @param[in] target_protocol 2148 * The next protocol in the previous item. 2149 * @param[out] error 2150 * Pointer to error structure. 2151 * 2152 * @return 2153 * 0 on success, a negative errno value otherwise and rte_errno is set. 2154 */ 2155 int 2156 mlx5_flow_validate_item_nvgre(const struct rte_flow_item *item, 2157 uint64_t item_flags, 2158 uint8_t target_protocol, 2159 struct rte_flow_error *error) 2160 { 2161 const struct rte_flow_item_nvgre *mask = item->mask; 2162 int ret; 2163 2164 if (target_protocol != 0xff && target_protocol != IPPROTO_GRE) 2165 return rte_flow_error_set(error, EINVAL, 2166 RTE_FLOW_ERROR_TYPE_ITEM, item, 2167 "protocol filtering not compatible" 2168 " with this GRE layer"); 2169 if (item_flags & MLX5_FLOW_LAYER_TUNNEL) 2170 return rte_flow_error_set(error, ENOTSUP, 2171 RTE_FLOW_ERROR_TYPE_ITEM, item, 2172 "multiple tunnel layers not" 2173 " supported"); 2174 if (!(item_flags & MLX5_FLOW_LAYER_OUTER_L3)) 2175 return rte_flow_error_set(error, ENOTSUP, 2176 RTE_FLOW_ERROR_TYPE_ITEM, item, 2177 "L3 Layer is missing"); 2178 if (!mask) 2179 mask = &rte_flow_item_nvgre_mask; 2180 ret = mlx5_flow_item_acceptable 2181 (item, (const uint8_t *)mask, 2182 (const uint8_t *)&rte_flow_item_nvgre_mask, 2183 sizeof(struct rte_flow_item_nvgre), error); 2184 if (ret < 0) 2185 return ret; 2186 return 0; 2187 } 2188 2189 static int 2190 flow_null_validate(struct rte_eth_dev *dev __rte_unused, 2191 const struct rte_flow_attr *attr __rte_unused, 2192 const struct rte_flow_item items[] __rte_unused, 2193 const struct rte_flow_action actions[] __rte_unused, 2194 bool external __rte_unused, 2195 struct rte_flow_error *error) 2196 { 2197 return rte_flow_error_set(error, ENOTSUP, 2198 RTE_FLOW_ERROR_TYPE_UNSPECIFIED, NULL, NULL); 2199 } 2200 2201 static struct mlx5_flow * 2202 flow_null_prepare(const struct rte_flow_attr *attr __rte_unused, 2203 const struct rte_flow_item items[] __rte_unused, 2204 const struct rte_flow_action actions[] __rte_unused, 2205 struct rte_flow_error *error) 2206 { 2207 rte_flow_error_set(error, ENOTSUP, 2208 RTE_FLOW_ERROR_TYPE_UNSPECIFIED, NULL, NULL); 2209 return NULL; 2210 } 2211 2212 static int 2213 flow_null_translate(struct rte_eth_dev *dev __rte_unused, 2214 struct mlx5_flow *dev_flow __rte_unused, 2215 const struct rte_flow_attr *attr __rte_unused, 2216 const struct rte_flow_item items[] __rte_unused, 2217 const struct rte_flow_action actions[] __rte_unused, 2218 struct rte_flow_error *error) 2219 { 2220 return rte_flow_error_set(error, ENOTSUP, 2221 RTE_FLOW_ERROR_TYPE_UNSPECIFIED, NULL, NULL); 2222 } 2223 2224 static int 2225 flow_null_apply(struct rte_eth_dev *dev __rte_unused, 2226 struct rte_flow *flow __rte_unused, 2227 struct rte_flow_error *error) 2228 { 2229 return rte_flow_error_set(error, ENOTSUP, 2230 RTE_FLOW_ERROR_TYPE_UNSPECIFIED, NULL, NULL); 2231 } 2232 2233 static void 2234 flow_null_remove(struct rte_eth_dev *dev __rte_unused, 2235 struct rte_flow *flow __rte_unused) 2236 { 2237 } 2238 2239 static void 2240 flow_null_destroy(struct rte_eth_dev *dev __rte_unused, 2241 struct rte_flow *flow __rte_unused) 2242 { 2243 } 2244 2245 static int 2246 flow_null_query(struct rte_eth_dev *dev __rte_unused, 2247 struct rte_flow *flow __rte_unused, 2248 const struct rte_flow_action *actions __rte_unused, 2249 void *data __rte_unused, 2250 struct rte_flow_error *error) 2251 { 2252 return rte_flow_error_set(error, ENOTSUP, 2253 RTE_FLOW_ERROR_TYPE_UNSPECIFIED, NULL, NULL); 2254 } 2255 2256 /* Void driver to protect from null pointer reference. */ 2257 const struct mlx5_flow_driver_ops mlx5_flow_null_drv_ops = { 2258 .validate = flow_null_validate, 2259 .prepare = flow_null_prepare, 2260 .translate = flow_null_translate, 2261 .apply = flow_null_apply, 2262 .remove = flow_null_remove, 2263 .destroy = flow_null_destroy, 2264 .query = flow_null_query, 2265 }; 2266 2267 /** 2268 * Select flow driver type according to flow attributes and device 2269 * configuration. 2270 * 2271 * @param[in] dev 2272 * Pointer to the dev structure. 2273 * @param[in] attr 2274 * Pointer to the flow attributes. 2275 * 2276 * @return 2277 * flow driver type, MLX5_FLOW_TYPE_MAX otherwise. 2278 */ 2279 static enum mlx5_flow_drv_type 2280 flow_get_drv_type(struct rte_eth_dev *dev, const struct rte_flow_attr *attr) 2281 { 2282 struct mlx5_priv *priv = dev->data->dev_private; 2283 enum mlx5_flow_drv_type type = MLX5_FLOW_TYPE_MAX; 2284 2285 if (attr->transfer && priv->config.dv_esw_en) 2286 type = MLX5_FLOW_TYPE_DV; 2287 if (!attr->transfer) 2288 type = priv->config.dv_flow_en ? MLX5_FLOW_TYPE_DV : 2289 MLX5_FLOW_TYPE_VERBS; 2290 return type; 2291 } 2292 2293 #define flow_get_drv_ops(type) flow_drv_ops[type] 2294 2295 /** 2296 * Flow driver validation API. This abstracts calling driver specific functions. 2297 * The type of flow driver is determined according to flow attributes. 2298 * 2299 * @param[in] dev 2300 * Pointer to the dev structure. 2301 * @param[in] attr 2302 * Pointer to the flow attributes. 2303 * @param[in] items 2304 * Pointer to the list of items. 2305 * @param[in] actions 2306 * Pointer to the list of actions. 2307 * @param[in] external 2308 * This flow rule is created by request external to PMD. 2309 * @param[out] error 2310 * Pointer to the error structure. 2311 * 2312 * @return 2313 * 0 on success, a negative errno value otherwise and rte_errno is set. 2314 */ 2315 static inline int 2316 flow_drv_validate(struct rte_eth_dev *dev, 2317 const struct rte_flow_attr *attr, 2318 const struct rte_flow_item items[], 2319 const struct rte_flow_action actions[], 2320 bool external, struct rte_flow_error *error) 2321 { 2322 const struct mlx5_flow_driver_ops *fops; 2323 enum mlx5_flow_drv_type type = flow_get_drv_type(dev, attr); 2324 2325 fops = flow_get_drv_ops(type); 2326 return fops->validate(dev, attr, items, actions, external, error); 2327 } 2328 2329 /** 2330 * Flow driver preparation API. This abstracts calling driver specific 2331 * functions. Parent flow (rte_flow) should have driver type (drv_type). It 2332 * calculates the size of memory required for device flow, allocates the memory, 2333 * initializes the device flow and returns the pointer. 2334 * 2335 * @note 2336 * This function initializes device flow structure such as dv or verbs in 2337 * struct mlx5_flow. However, it is caller's responsibility to initialize the 2338 * rest. For example, adding returning device flow to flow->dev_flow list and 2339 * setting backward reference to the flow should be done out of this function. 2340 * layers field is not filled either. 2341 * 2342 * @param[in] attr 2343 * Pointer to the flow attributes. 2344 * @param[in] items 2345 * Pointer to the list of items. 2346 * @param[in] actions 2347 * Pointer to the list of actions. 2348 * @param[out] error 2349 * Pointer to the error structure. 2350 * 2351 * @return 2352 * Pointer to device flow on success, otherwise NULL and rte_errno is set. 2353 */ 2354 static inline struct mlx5_flow * 2355 flow_drv_prepare(const struct rte_flow *flow, 2356 const struct rte_flow_attr *attr, 2357 const struct rte_flow_item items[], 2358 const struct rte_flow_action actions[], 2359 struct rte_flow_error *error) 2360 { 2361 const struct mlx5_flow_driver_ops *fops; 2362 enum mlx5_flow_drv_type type = flow->drv_type; 2363 2364 assert(type > MLX5_FLOW_TYPE_MIN && type < MLX5_FLOW_TYPE_MAX); 2365 fops = flow_get_drv_ops(type); 2366 return fops->prepare(attr, items, actions, error); 2367 } 2368 2369 /** 2370 * Flow driver translation API. This abstracts calling driver specific 2371 * functions. Parent flow (rte_flow) should have driver type (drv_type). It 2372 * translates a generic flow into a driver flow. flow_drv_prepare() must 2373 * precede. 2374 * 2375 * @note 2376 * dev_flow->layers could be filled as a result of parsing during translation 2377 * if needed by flow_drv_apply(). dev_flow->flow->actions can also be filled 2378 * if necessary. As a flow can have multiple dev_flows by RSS flow expansion, 2379 * flow->actions could be overwritten even though all the expanded dev_flows 2380 * have the same actions. 2381 * 2382 * @param[in] dev 2383 * Pointer to the rte dev structure. 2384 * @param[in, out] dev_flow 2385 * Pointer to the mlx5 flow. 2386 * @param[in] attr 2387 * Pointer to the flow attributes. 2388 * @param[in] items 2389 * Pointer to the list of items. 2390 * @param[in] actions 2391 * Pointer to the list of actions. 2392 * @param[out] error 2393 * Pointer to the error structure. 2394 * 2395 * @return 2396 * 0 on success, a negative errno value otherwise and rte_errno is set. 2397 */ 2398 static inline int 2399 flow_drv_translate(struct rte_eth_dev *dev, struct mlx5_flow *dev_flow, 2400 const struct rte_flow_attr *attr, 2401 const struct rte_flow_item items[], 2402 const struct rte_flow_action actions[], 2403 struct rte_flow_error *error) 2404 { 2405 const struct mlx5_flow_driver_ops *fops; 2406 enum mlx5_flow_drv_type type = dev_flow->flow->drv_type; 2407 2408 assert(type > MLX5_FLOW_TYPE_MIN && type < MLX5_FLOW_TYPE_MAX); 2409 fops = flow_get_drv_ops(type); 2410 return fops->translate(dev, dev_flow, attr, items, actions, error); 2411 } 2412 2413 /** 2414 * Flow driver apply API. This abstracts calling driver specific functions. 2415 * Parent flow (rte_flow) should have driver type (drv_type). It applies 2416 * translated driver flows on to device. flow_drv_translate() must precede. 2417 * 2418 * @param[in] dev 2419 * Pointer to Ethernet device structure. 2420 * @param[in, out] flow 2421 * Pointer to flow structure. 2422 * @param[out] error 2423 * Pointer to error structure. 2424 * 2425 * @return 2426 * 0 on success, a negative errno value otherwise and rte_errno is set. 2427 */ 2428 static inline int 2429 flow_drv_apply(struct rte_eth_dev *dev, struct rte_flow *flow, 2430 struct rte_flow_error *error) 2431 { 2432 const struct mlx5_flow_driver_ops *fops; 2433 enum mlx5_flow_drv_type type = flow->drv_type; 2434 2435 assert(type > MLX5_FLOW_TYPE_MIN && type < MLX5_FLOW_TYPE_MAX); 2436 fops = flow_get_drv_ops(type); 2437 return fops->apply(dev, flow, error); 2438 } 2439 2440 /** 2441 * Flow driver remove API. This abstracts calling driver specific functions. 2442 * Parent flow (rte_flow) should have driver type (drv_type). It removes a flow 2443 * on device. All the resources of the flow should be freed by calling 2444 * flow_drv_destroy(). 2445 * 2446 * @param[in] dev 2447 * Pointer to Ethernet device. 2448 * @param[in, out] flow 2449 * Pointer to flow structure. 2450 */ 2451 static inline void 2452 flow_drv_remove(struct rte_eth_dev *dev, struct rte_flow *flow) 2453 { 2454 const struct mlx5_flow_driver_ops *fops; 2455 enum mlx5_flow_drv_type type = flow->drv_type; 2456 2457 assert(type > MLX5_FLOW_TYPE_MIN && type < MLX5_FLOW_TYPE_MAX); 2458 fops = flow_get_drv_ops(type); 2459 fops->remove(dev, flow); 2460 } 2461 2462 /** 2463 * Flow driver destroy API. This abstracts calling driver specific functions. 2464 * Parent flow (rte_flow) should have driver type (drv_type). It removes a flow 2465 * on device and releases resources of the flow. 2466 * 2467 * @param[in] dev 2468 * Pointer to Ethernet device. 2469 * @param[in, out] flow 2470 * Pointer to flow structure. 2471 */ 2472 static inline void 2473 flow_drv_destroy(struct rte_eth_dev *dev, struct rte_flow *flow) 2474 { 2475 const struct mlx5_flow_driver_ops *fops; 2476 enum mlx5_flow_drv_type type = flow->drv_type; 2477 2478 assert(type > MLX5_FLOW_TYPE_MIN && type < MLX5_FLOW_TYPE_MAX); 2479 fops = flow_get_drv_ops(type); 2480 fops->destroy(dev, flow); 2481 } 2482 2483 /** 2484 * Validate a flow supported by the NIC. 2485 * 2486 * @see rte_flow_validate() 2487 * @see rte_flow_ops 2488 */ 2489 int 2490 mlx5_flow_validate(struct rte_eth_dev *dev, 2491 const struct rte_flow_attr *attr, 2492 const struct rte_flow_item items[], 2493 const struct rte_flow_action actions[], 2494 struct rte_flow_error *error) 2495 { 2496 int ret; 2497 2498 ret = flow_drv_validate(dev, attr, items, actions, true, error); 2499 if (ret < 0) 2500 return ret; 2501 return 0; 2502 } 2503 2504 /** 2505 * Get RSS action from the action list. 2506 * 2507 * @param[in] actions 2508 * Pointer to the list of actions. 2509 * 2510 * @return 2511 * Pointer to the RSS action if exist, else return NULL. 2512 */ 2513 static const struct rte_flow_action_rss* 2514 flow_get_rss_action(const struct rte_flow_action actions[]) 2515 { 2516 for (; actions->type != RTE_FLOW_ACTION_TYPE_END; actions++) { 2517 switch (actions->type) { 2518 case RTE_FLOW_ACTION_TYPE_RSS: 2519 return (const struct rte_flow_action_rss *) 2520 actions->conf; 2521 default: 2522 break; 2523 } 2524 } 2525 return NULL; 2526 } 2527 2528 static unsigned int 2529 find_graph_root(const struct rte_flow_item pattern[], uint32_t rss_level) 2530 { 2531 const struct rte_flow_item *item; 2532 unsigned int has_vlan = 0; 2533 2534 for (item = pattern; item->type != RTE_FLOW_ITEM_TYPE_END; item++) { 2535 if (item->type == RTE_FLOW_ITEM_TYPE_VLAN) { 2536 has_vlan = 1; 2537 break; 2538 } 2539 } 2540 if (has_vlan) 2541 return rss_level < 2 ? MLX5_EXPANSION_ROOT_ETH_VLAN : 2542 MLX5_EXPANSION_ROOT_OUTER_ETH_VLAN; 2543 return rss_level < 2 ? MLX5_EXPANSION_ROOT : 2544 MLX5_EXPANSION_ROOT_OUTER; 2545 } 2546 2547 /** 2548 * Check if the flow should be splited due to hairpin. 2549 * The reason for the split is that in current HW we can't 2550 * support encap on Rx, so if a flow have encap we move it 2551 * to Tx. 2552 * 2553 * @param dev 2554 * Pointer to Ethernet device. 2555 * @param[in] attr 2556 * Flow rule attributes. 2557 * @param[in] actions 2558 * Associated actions (list terminated by the END action). 2559 * 2560 * @return 2561 * > 0 the number of actions and the flow should be split, 2562 * 0 when no split required. 2563 */ 2564 static int 2565 flow_check_hairpin_split(struct rte_eth_dev *dev, 2566 const struct rte_flow_attr *attr, 2567 const struct rte_flow_action actions[]) 2568 { 2569 int queue_action = 0; 2570 int action_n = 0; 2571 int encap = 0; 2572 const struct rte_flow_action_queue *queue; 2573 const struct rte_flow_action_rss *rss; 2574 const struct rte_flow_action_raw_encap *raw_encap; 2575 2576 if (!attr->ingress) 2577 return 0; 2578 for (; actions->type != RTE_FLOW_ACTION_TYPE_END; actions++) { 2579 switch (actions->type) { 2580 case RTE_FLOW_ACTION_TYPE_QUEUE: 2581 queue = actions->conf; 2582 if (mlx5_rxq_get_type(dev, queue->index) != 2583 MLX5_RXQ_TYPE_HAIRPIN) 2584 return 0; 2585 queue_action = 1; 2586 action_n++; 2587 break; 2588 case RTE_FLOW_ACTION_TYPE_RSS: 2589 rss = actions->conf; 2590 if (mlx5_rxq_get_type(dev, rss->queue[0]) != 2591 MLX5_RXQ_TYPE_HAIRPIN) 2592 return 0; 2593 queue_action = 1; 2594 action_n++; 2595 break; 2596 case RTE_FLOW_ACTION_TYPE_VXLAN_ENCAP: 2597 case RTE_FLOW_ACTION_TYPE_NVGRE_ENCAP: 2598 encap = 1; 2599 action_n++; 2600 break; 2601 case RTE_FLOW_ACTION_TYPE_RAW_ENCAP: 2602 raw_encap = actions->conf; 2603 if (raw_encap->size > 2604 (sizeof(struct rte_flow_item_eth) + 2605 sizeof(struct rte_flow_item_ipv4))) 2606 encap = 1; 2607 action_n++; 2608 break; 2609 default: 2610 action_n++; 2611 break; 2612 } 2613 } 2614 if (encap == 1 && queue_action) 2615 return action_n; 2616 return 0; 2617 } 2618 2619 #define MLX5_MAX_SPLIT_ACTIONS 24 2620 #define MLX5_MAX_SPLIT_ITEMS 24 2621 2622 /** 2623 * Split the hairpin flow. 2624 * Since HW can't support encap on Rx we move the encap to Tx. 2625 * If the count action is after the encap then we also 2626 * move the count action. in this case the count will also measure 2627 * the outer bytes. 2628 * 2629 * @param dev 2630 * Pointer to Ethernet device. 2631 * @param[in] actions 2632 * Associated actions (list terminated by the END action). 2633 * @param[out] actions_rx 2634 * Rx flow actions. 2635 * @param[out] actions_tx 2636 * Tx flow actions.. 2637 * @param[out] pattern_tx 2638 * The pattern items for the Tx flow. 2639 * @param[out] flow_id 2640 * The flow ID connected to this flow. 2641 * 2642 * @return 2643 * 0 on success. 2644 */ 2645 static int 2646 flow_hairpin_split(struct rte_eth_dev *dev, 2647 const struct rte_flow_action actions[], 2648 struct rte_flow_action actions_rx[], 2649 struct rte_flow_action actions_tx[], 2650 struct rte_flow_item pattern_tx[], 2651 uint32_t *flow_id) 2652 { 2653 struct mlx5_priv *priv = dev->data->dev_private; 2654 const struct rte_flow_action_raw_encap *raw_encap; 2655 const struct rte_flow_action_raw_decap *raw_decap; 2656 struct mlx5_rte_flow_action_set_tag *set_tag; 2657 struct rte_flow_action *tag_action; 2658 struct mlx5_rte_flow_item_tag *tag_item; 2659 struct rte_flow_item *item; 2660 char *addr; 2661 struct rte_flow_error error; 2662 int encap = 0; 2663 2664 mlx5_flow_id_get(priv->sh->flow_id_pool, flow_id); 2665 for (; actions->type != RTE_FLOW_ACTION_TYPE_END; actions++) { 2666 switch (actions->type) { 2667 case RTE_FLOW_ACTION_TYPE_VXLAN_ENCAP: 2668 case RTE_FLOW_ACTION_TYPE_NVGRE_ENCAP: 2669 rte_memcpy(actions_tx, actions, 2670 sizeof(struct rte_flow_action)); 2671 actions_tx++; 2672 break; 2673 case RTE_FLOW_ACTION_TYPE_COUNT: 2674 if (encap) { 2675 rte_memcpy(actions_tx, actions, 2676 sizeof(struct rte_flow_action)); 2677 actions_tx++; 2678 } else { 2679 rte_memcpy(actions_rx, actions, 2680 sizeof(struct rte_flow_action)); 2681 actions_rx++; 2682 } 2683 break; 2684 case RTE_FLOW_ACTION_TYPE_RAW_ENCAP: 2685 raw_encap = actions->conf; 2686 if (raw_encap->size > 2687 (sizeof(struct rte_flow_item_eth) + 2688 sizeof(struct rte_flow_item_ipv4))) { 2689 memcpy(actions_tx, actions, 2690 sizeof(struct rte_flow_action)); 2691 actions_tx++; 2692 encap = 1; 2693 } else { 2694 rte_memcpy(actions_rx, actions, 2695 sizeof(struct rte_flow_action)); 2696 actions_rx++; 2697 } 2698 break; 2699 case RTE_FLOW_ACTION_TYPE_RAW_DECAP: 2700 raw_decap = actions->conf; 2701 if (raw_decap->size < 2702 (sizeof(struct rte_flow_item_eth) + 2703 sizeof(struct rte_flow_item_ipv4))) { 2704 memcpy(actions_tx, actions, 2705 sizeof(struct rte_flow_action)); 2706 actions_tx++; 2707 } else { 2708 rte_memcpy(actions_rx, actions, 2709 sizeof(struct rte_flow_action)); 2710 actions_rx++; 2711 } 2712 break; 2713 default: 2714 rte_memcpy(actions_rx, actions, 2715 sizeof(struct rte_flow_action)); 2716 actions_rx++; 2717 break; 2718 } 2719 } 2720 /* Add set meta action and end action for the Rx flow. */ 2721 tag_action = actions_rx; 2722 tag_action->type = MLX5_RTE_FLOW_ACTION_TYPE_TAG; 2723 actions_rx++; 2724 rte_memcpy(actions_rx, actions, sizeof(struct rte_flow_action)); 2725 actions_rx++; 2726 set_tag = (void *)actions_rx; 2727 set_tag->id = flow_get_reg_id(dev, MLX5_HAIRPIN_RX, 0, &error); 2728 set_tag->data = rte_cpu_to_be_32(*flow_id); 2729 tag_action->conf = set_tag; 2730 /* Create Tx item list. */ 2731 rte_memcpy(actions_tx, actions, sizeof(struct rte_flow_action)); 2732 addr = (void *)&pattern_tx[2]; 2733 item = pattern_tx; 2734 item->type = MLX5_RTE_FLOW_ITEM_TYPE_TAG; 2735 tag_item = (void *)addr; 2736 tag_item->data = rte_cpu_to_be_32(*flow_id); 2737 tag_item->id = flow_get_reg_id(dev, MLX5_HAIRPIN_TX, 0, &error); 2738 item->spec = tag_item; 2739 addr += sizeof(struct mlx5_rte_flow_item_tag); 2740 tag_item = (void *)addr; 2741 tag_item->data = UINT32_MAX; 2742 tag_item->id = UINT16_MAX; 2743 item->mask = tag_item; 2744 addr += sizeof(struct mlx5_rte_flow_item_tag); 2745 item->last = NULL; 2746 item++; 2747 item->type = RTE_FLOW_ITEM_TYPE_END; 2748 return 0; 2749 } 2750 2751 /** 2752 * Create a flow and add it to @p list. 2753 * 2754 * @param dev 2755 * Pointer to Ethernet device. 2756 * @param list 2757 * Pointer to a TAILQ flow list. 2758 * @param[in] attr 2759 * Flow rule attributes. 2760 * @param[in] items 2761 * Pattern specification (list terminated by the END pattern item). 2762 * @param[in] actions 2763 * Associated actions (list terminated by the END action). 2764 * @param[in] external 2765 * This flow rule is created by request external to PMD. 2766 * @param[out] error 2767 * Perform verbose error reporting if not NULL. 2768 * 2769 * @return 2770 * A flow on success, NULL otherwise and rte_errno is set. 2771 */ 2772 static struct rte_flow * 2773 flow_list_create(struct rte_eth_dev *dev, struct mlx5_flows *list, 2774 const struct rte_flow_attr *attr, 2775 const struct rte_flow_item items[], 2776 const struct rte_flow_action actions[], 2777 bool external, struct rte_flow_error *error) 2778 { 2779 struct mlx5_priv *priv = dev->data->dev_private; 2780 struct rte_flow *flow = NULL; 2781 struct mlx5_flow *dev_flow; 2782 const struct rte_flow_action_rss *rss; 2783 union { 2784 struct rte_flow_expand_rss buf; 2785 uint8_t buffer[2048]; 2786 } expand_buffer; 2787 union { 2788 struct rte_flow_action actions[MLX5_MAX_SPLIT_ACTIONS]; 2789 uint8_t buffer[2048]; 2790 } actions_rx; 2791 union { 2792 struct rte_flow_action actions[MLX5_MAX_SPLIT_ACTIONS]; 2793 uint8_t buffer[2048]; 2794 } actions_hairpin_tx; 2795 union { 2796 struct rte_flow_item items[MLX5_MAX_SPLIT_ITEMS]; 2797 uint8_t buffer[2048]; 2798 } items_tx; 2799 struct rte_flow_expand_rss *buf = &expand_buffer.buf; 2800 const struct rte_flow_action *p_actions_rx = actions; 2801 int ret; 2802 uint32_t i; 2803 uint32_t flow_size; 2804 int hairpin_flow = 0; 2805 uint32_t hairpin_id = 0; 2806 struct rte_flow_attr attr_tx = { .priority = 0 }; 2807 2808 hairpin_flow = flow_check_hairpin_split(dev, attr, actions); 2809 if (hairpin_flow > 0) { 2810 if (hairpin_flow > MLX5_MAX_SPLIT_ACTIONS) { 2811 rte_errno = EINVAL; 2812 return NULL; 2813 } 2814 flow_hairpin_split(dev, actions, actions_rx.actions, 2815 actions_hairpin_tx.actions, items_tx.items, 2816 &hairpin_id); 2817 p_actions_rx = actions_rx.actions; 2818 } 2819 ret = flow_drv_validate(dev, attr, items, p_actions_rx, external, 2820 error); 2821 if (ret < 0) 2822 goto error_before_flow; 2823 flow_size = sizeof(struct rte_flow); 2824 rss = flow_get_rss_action(p_actions_rx); 2825 if (rss) 2826 flow_size += RTE_ALIGN_CEIL(rss->queue_num * sizeof(uint16_t), 2827 sizeof(void *)); 2828 else 2829 flow_size += RTE_ALIGN_CEIL(sizeof(uint16_t), sizeof(void *)); 2830 flow = rte_calloc(__func__, 1, flow_size, 0); 2831 if (!flow) { 2832 rte_errno = ENOMEM; 2833 goto error_before_flow; 2834 } 2835 flow->drv_type = flow_get_drv_type(dev, attr); 2836 flow->ingress = attr->ingress; 2837 flow->transfer = attr->transfer; 2838 if (hairpin_id != 0) 2839 flow->hairpin_flow_id = hairpin_id; 2840 assert(flow->drv_type > MLX5_FLOW_TYPE_MIN && 2841 flow->drv_type < MLX5_FLOW_TYPE_MAX); 2842 flow->queue = (void *)(flow + 1); 2843 LIST_INIT(&flow->dev_flows); 2844 if (rss && rss->types) { 2845 unsigned int graph_root; 2846 2847 graph_root = find_graph_root(items, rss->level); 2848 ret = rte_flow_expand_rss(buf, sizeof(expand_buffer.buffer), 2849 items, rss->types, 2850 mlx5_support_expansion, 2851 graph_root); 2852 assert(ret > 0 && 2853 (unsigned int)ret < sizeof(expand_buffer.buffer)); 2854 } else { 2855 buf->entries = 1; 2856 buf->entry[0].pattern = (void *)(uintptr_t)items; 2857 } 2858 for (i = 0; i < buf->entries; ++i) { 2859 dev_flow = flow_drv_prepare(flow, attr, buf->entry[i].pattern, 2860 p_actions_rx, error); 2861 if (!dev_flow) 2862 goto error; 2863 dev_flow->flow = flow; 2864 dev_flow->external = external; 2865 LIST_INSERT_HEAD(&flow->dev_flows, dev_flow, next); 2866 ret = flow_drv_translate(dev, dev_flow, attr, 2867 buf->entry[i].pattern, 2868 p_actions_rx, error); 2869 if (ret < 0) 2870 goto error; 2871 } 2872 /* Create the tx flow. */ 2873 if (hairpin_flow) { 2874 attr_tx.group = MLX5_HAIRPIN_TX_TABLE; 2875 attr_tx.ingress = 0; 2876 attr_tx.egress = 1; 2877 dev_flow = flow_drv_prepare(flow, &attr_tx, items_tx.items, 2878 actions_hairpin_tx.actions, error); 2879 if (!dev_flow) 2880 goto error; 2881 dev_flow->flow = flow; 2882 LIST_INSERT_HEAD(&flow->dev_flows, dev_flow, next); 2883 ret = flow_drv_translate(dev, dev_flow, &attr_tx, 2884 items_tx.items, 2885 actions_hairpin_tx.actions, error); 2886 if (ret < 0) 2887 goto error; 2888 } 2889 if (dev->data->dev_started) { 2890 ret = flow_drv_apply(dev, flow, error); 2891 if (ret < 0) 2892 goto error; 2893 } 2894 TAILQ_INSERT_TAIL(list, flow, next); 2895 flow_rxq_flags_set(dev, flow); 2896 return flow; 2897 error_before_flow: 2898 if (hairpin_id) 2899 mlx5_flow_id_release(priv->sh->flow_id_pool, 2900 hairpin_id); 2901 return NULL; 2902 error: 2903 ret = rte_errno; /* Save rte_errno before cleanup. */ 2904 if (flow->hairpin_flow_id) 2905 mlx5_flow_id_release(priv->sh->flow_id_pool, 2906 flow->hairpin_flow_id); 2907 assert(flow); 2908 flow_drv_destroy(dev, flow); 2909 rte_free(flow); 2910 rte_errno = ret; /* Restore rte_errno. */ 2911 return NULL; 2912 } 2913 2914 /** 2915 * Create a dedicated flow rule on e-switch table 0 (root table), to direct all 2916 * incoming packets to table 1. 2917 * 2918 * Other flow rules, requested for group n, will be created in 2919 * e-switch table n+1. 2920 * Jump action to e-switch group n will be created to group n+1. 2921 * 2922 * Used when working in switchdev mode, to utilise advantages of table 1 2923 * and above. 2924 * 2925 * @param dev 2926 * Pointer to Ethernet device. 2927 * 2928 * @return 2929 * Pointer to flow on success, NULL otherwise and rte_errno is set. 2930 */ 2931 struct rte_flow * 2932 mlx5_flow_create_esw_table_zero_flow(struct rte_eth_dev *dev) 2933 { 2934 const struct rte_flow_attr attr = { 2935 .group = 0, 2936 .priority = 0, 2937 .ingress = 1, 2938 .egress = 0, 2939 .transfer = 1, 2940 }; 2941 const struct rte_flow_item pattern = { 2942 .type = RTE_FLOW_ITEM_TYPE_END, 2943 }; 2944 struct rte_flow_action_jump jump = { 2945 .group = 1, 2946 }; 2947 const struct rte_flow_action actions[] = { 2948 { 2949 .type = RTE_FLOW_ACTION_TYPE_JUMP, 2950 .conf = &jump, 2951 }, 2952 { 2953 .type = RTE_FLOW_ACTION_TYPE_END, 2954 }, 2955 }; 2956 struct mlx5_priv *priv = dev->data->dev_private; 2957 struct rte_flow_error error; 2958 2959 return flow_list_create(dev, &priv->ctrl_flows, &attr, &pattern, 2960 actions, false, &error); 2961 } 2962 2963 /** 2964 * Create a flow. 2965 * 2966 * @see rte_flow_create() 2967 * @see rte_flow_ops 2968 */ 2969 struct rte_flow * 2970 mlx5_flow_create(struct rte_eth_dev *dev, 2971 const struct rte_flow_attr *attr, 2972 const struct rte_flow_item items[], 2973 const struct rte_flow_action actions[], 2974 struct rte_flow_error *error) 2975 { 2976 struct mlx5_priv *priv = dev->data->dev_private; 2977 2978 return flow_list_create(dev, &priv->flows, 2979 attr, items, actions, true, error); 2980 } 2981 2982 /** 2983 * Destroy a flow in a list. 2984 * 2985 * @param dev 2986 * Pointer to Ethernet device. 2987 * @param list 2988 * Pointer to a TAILQ flow list. 2989 * @param[in] flow 2990 * Flow to destroy. 2991 */ 2992 static void 2993 flow_list_destroy(struct rte_eth_dev *dev, struct mlx5_flows *list, 2994 struct rte_flow *flow) 2995 { 2996 struct mlx5_priv *priv = dev->data->dev_private; 2997 2998 /* 2999 * Update RX queue flags only if port is started, otherwise it is 3000 * already clean. 3001 */ 3002 if (dev->data->dev_started) 3003 flow_rxq_flags_trim(dev, flow); 3004 if (flow->hairpin_flow_id) 3005 mlx5_flow_id_release(priv->sh->flow_id_pool, 3006 flow->hairpin_flow_id); 3007 flow_drv_destroy(dev, flow); 3008 TAILQ_REMOVE(list, flow, next); 3009 rte_free(flow->fdir); 3010 rte_free(flow); 3011 } 3012 3013 /** 3014 * Destroy all flows. 3015 * 3016 * @param dev 3017 * Pointer to Ethernet device. 3018 * @param list 3019 * Pointer to a TAILQ flow list. 3020 */ 3021 void 3022 mlx5_flow_list_flush(struct rte_eth_dev *dev, struct mlx5_flows *list) 3023 { 3024 while (!TAILQ_EMPTY(list)) { 3025 struct rte_flow *flow; 3026 3027 flow = TAILQ_FIRST(list); 3028 flow_list_destroy(dev, list, flow); 3029 } 3030 } 3031 3032 /** 3033 * Remove all flows. 3034 * 3035 * @param dev 3036 * Pointer to Ethernet device. 3037 * @param list 3038 * Pointer to a TAILQ flow list. 3039 */ 3040 void 3041 mlx5_flow_stop(struct rte_eth_dev *dev, struct mlx5_flows *list) 3042 { 3043 struct rte_flow *flow; 3044 3045 TAILQ_FOREACH_REVERSE(flow, list, mlx5_flows, next) 3046 flow_drv_remove(dev, flow); 3047 flow_rxq_flags_clear(dev); 3048 } 3049 3050 /** 3051 * Add all flows. 3052 * 3053 * @param dev 3054 * Pointer to Ethernet device. 3055 * @param list 3056 * Pointer to a TAILQ flow list. 3057 * 3058 * @return 3059 * 0 on success, a negative errno value otherwise and rte_errno is set. 3060 */ 3061 int 3062 mlx5_flow_start(struct rte_eth_dev *dev, struct mlx5_flows *list) 3063 { 3064 struct rte_flow *flow; 3065 struct rte_flow_error error; 3066 int ret = 0; 3067 3068 TAILQ_FOREACH(flow, list, next) { 3069 ret = flow_drv_apply(dev, flow, &error); 3070 if (ret < 0) 3071 goto error; 3072 flow_rxq_flags_set(dev, flow); 3073 } 3074 return 0; 3075 error: 3076 ret = rte_errno; /* Save rte_errno before cleanup. */ 3077 mlx5_flow_stop(dev, list); 3078 rte_errno = ret; /* Restore rte_errno. */ 3079 return -rte_errno; 3080 } 3081 3082 /** 3083 * Verify the flow list is empty 3084 * 3085 * @param dev 3086 * Pointer to Ethernet device. 3087 * 3088 * @return the number of flows not released. 3089 */ 3090 int 3091 mlx5_flow_verify(struct rte_eth_dev *dev) 3092 { 3093 struct mlx5_priv *priv = dev->data->dev_private; 3094 struct rte_flow *flow; 3095 int ret = 0; 3096 3097 TAILQ_FOREACH(flow, &priv->flows, next) { 3098 DRV_LOG(DEBUG, "port %u flow %p still referenced", 3099 dev->data->port_id, (void *)flow); 3100 ++ret; 3101 } 3102 return ret; 3103 } 3104 3105 /** 3106 * Enable default hairpin egress flow. 3107 * 3108 * @param dev 3109 * Pointer to Ethernet device. 3110 * @param queue 3111 * The queue index. 3112 * 3113 * @return 3114 * 0 on success, a negative errno value otherwise and rte_errno is set. 3115 */ 3116 int 3117 mlx5_ctrl_flow_source_queue(struct rte_eth_dev *dev, 3118 uint32_t queue) 3119 { 3120 struct mlx5_priv *priv = dev->data->dev_private; 3121 const struct rte_flow_attr attr = { 3122 .egress = 1, 3123 .priority = 0, 3124 }; 3125 struct mlx5_rte_flow_item_tx_queue queue_spec = { 3126 .queue = queue, 3127 }; 3128 struct mlx5_rte_flow_item_tx_queue queue_mask = { 3129 .queue = UINT32_MAX, 3130 }; 3131 struct rte_flow_item items[] = { 3132 { 3133 .type = MLX5_RTE_FLOW_ITEM_TYPE_TX_QUEUE, 3134 .spec = &queue_spec, 3135 .last = NULL, 3136 .mask = &queue_mask, 3137 }, 3138 { 3139 .type = RTE_FLOW_ITEM_TYPE_END, 3140 }, 3141 }; 3142 struct rte_flow_action_jump jump = { 3143 .group = MLX5_HAIRPIN_TX_TABLE, 3144 }; 3145 struct rte_flow_action actions[2]; 3146 struct rte_flow *flow; 3147 struct rte_flow_error error; 3148 3149 actions[0].type = RTE_FLOW_ACTION_TYPE_JUMP; 3150 actions[0].conf = &jump; 3151 actions[1].type = RTE_FLOW_ACTION_TYPE_END; 3152 flow = flow_list_create(dev, &priv->ctrl_flows, 3153 &attr, items, actions, false, &error); 3154 if (!flow) { 3155 DRV_LOG(DEBUG, 3156 "Failed to create ctrl flow: rte_errno(%d)," 3157 " type(%d), message(%s)", 3158 rte_errno, error.type, 3159 error.message ? error.message : " (no stated reason)"); 3160 return -rte_errno; 3161 } 3162 return 0; 3163 } 3164 3165 /** 3166 * Enable a control flow configured from the control plane. 3167 * 3168 * @param dev 3169 * Pointer to Ethernet device. 3170 * @param eth_spec 3171 * An Ethernet flow spec to apply. 3172 * @param eth_mask 3173 * An Ethernet flow mask to apply. 3174 * @param vlan_spec 3175 * A VLAN flow spec to apply. 3176 * @param vlan_mask 3177 * A VLAN flow mask to apply. 3178 * 3179 * @return 3180 * 0 on success, a negative errno value otherwise and rte_errno is set. 3181 */ 3182 int 3183 mlx5_ctrl_flow_vlan(struct rte_eth_dev *dev, 3184 struct rte_flow_item_eth *eth_spec, 3185 struct rte_flow_item_eth *eth_mask, 3186 struct rte_flow_item_vlan *vlan_spec, 3187 struct rte_flow_item_vlan *vlan_mask) 3188 { 3189 struct mlx5_priv *priv = dev->data->dev_private; 3190 const struct rte_flow_attr attr = { 3191 .ingress = 1, 3192 .priority = MLX5_FLOW_PRIO_RSVD, 3193 }; 3194 struct rte_flow_item items[] = { 3195 { 3196 .type = RTE_FLOW_ITEM_TYPE_ETH, 3197 .spec = eth_spec, 3198 .last = NULL, 3199 .mask = eth_mask, 3200 }, 3201 { 3202 .type = (vlan_spec) ? RTE_FLOW_ITEM_TYPE_VLAN : 3203 RTE_FLOW_ITEM_TYPE_END, 3204 .spec = vlan_spec, 3205 .last = NULL, 3206 .mask = vlan_mask, 3207 }, 3208 { 3209 .type = RTE_FLOW_ITEM_TYPE_END, 3210 }, 3211 }; 3212 uint16_t queue[priv->reta_idx_n]; 3213 struct rte_flow_action_rss action_rss = { 3214 .func = RTE_ETH_HASH_FUNCTION_DEFAULT, 3215 .level = 0, 3216 .types = priv->rss_conf.rss_hf, 3217 .key_len = priv->rss_conf.rss_key_len, 3218 .queue_num = priv->reta_idx_n, 3219 .key = priv->rss_conf.rss_key, 3220 .queue = queue, 3221 }; 3222 struct rte_flow_action actions[] = { 3223 { 3224 .type = RTE_FLOW_ACTION_TYPE_RSS, 3225 .conf = &action_rss, 3226 }, 3227 { 3228 .type = RTE_FLOW_ACTION_TYPE_END, 3229 }, 3230 }; 3231 struct rte_flow *flow; 3232 struct rte_flow_error error; 3233 unsigned int i; 3234 3235 if (!priv->reta_idx_n || !priv->rxqs_n) { 3236 return 0; 3237 } 3238 for (i = 0; i != priv->reta_idx_n; ++i) 3239 queue[i] = (*priv->reta_idx)[i]; 3240 flow = flow_list_create(dev, &priv->ctrl_flows, 3241 &attr, items, actions, false, &error); 3242 if (!flow) 3243 return -rte_errno; 3244 return 0; 3245 } 3246 3247 /** 3248 * Enable a flow control configured from the control plane. 3249 * 3250 * @param dev 3251 * Pointer to Ethernet device. 3252 * @param eth_spec 3253 * An Ethernet flow spec to apply. 3254 * @param eth_mask 3255 * An Ethernet flow mask to apply. 3256 * 3257 * @return 3258 * 0 on success, a negative errno value otherwise and rte_errno is set. 3259 */ 3260 int 3261 mlx5_ctrl_flow(struct rte_eth_dev *dev, 3262 struct rte_flow_item_eth *eth_spec, 3263 struct rte_flow_item_eth *eth_mask) 3264 { 3265 return mlx5_ctrl_flow_vlan(dev, eth_spec, eth_mask, NULL, NULL); 3266 } 3267 3268 /** 3269 * Destroy a flow. 3270 * 3271 * @see rte_flow_destroy() 3272 * @see rte_flow_ops 3273 */ 3274 int 3275 mlx5_flow_destroy(struct rte_eth_dev *dev, 3276 struct rte_flow *flow, 3277 struct rte_flow_error *error __rte_unused) 3278 { 3279 struct mlx5_priv *priv = dev->data->dev_private; 3280 3281 flow_list_destroy(dev, &priv->flows, flow); 3282 return 0; 3283 } 3284 3285 /** 3286 * Destroy all flows. 3287 * 3288 * @see rte_flow_flush() 3289 * @see rte_flow_ops 3290 */ 3291 int 3292 mlx5_flow_flush(struct rte_eth_dev *dev, 3293 struct rte_flow_error *error __rte_unused) 3294 { 3295 struct mlx5_priv *priv = dev->data->dev_private; 3296 3297 mlx5_flow_list_flush(dev, &priv->flows); 3298 return 0; 3299 } 3300 3301 /** 3302 * Isolated mode. 3303 * 3304 * @see rte_flow_isolate() 3305 * @see rte_flow_ops 3306 */ 3307 int 3308 mlx5_flow_isolate(struct rte_eth_dev *dev, 3309 int enable, 3310 struct rte_flow_error *error) 3311 { 3312 struct mlx5_priv *priv = dev->data->dev_private; 3313 3314 if (dev->data->dev_started) { 3315 rte_flow_error_set(error, EBUSY, 3316 RTE_FLOW_ERROR_TYPE_UNSPECIFIED, 3317 NULL, 3318 "port must be stopped first"); 3319 return -rte_errno; 3320 } 3321 priv->isolated = !!enable; 3322 if (enable) 3323 dev->dev_ops = &mlx5_dev_ops_isolate; 3324 else 3325 dev->dev_ops = &mlx5_dev_ops; 3326 return 0; 3327 } 3328 3329 /** 3330 * Query a flow. 3331 * 3332 * @see rte_flow_query() 3333 * @see rte_flow_ops 3334 */ 3335 static int 3336 flow_drv_query(struct rte_eth_dev *dev, 3337 struct rte_flow *flow, 3338 const struct rte_flow_action *actions, 3339 void *data, 3340 struct rte_flow_error *error) 3341 { 3342 const struct mlx5_flow_driver_ops *fops; 3343 enum mlx5_flow_drv_type ftype = flow->drv_type; 3344 3345 assert(ftype > MLX5_FLOW_TYPE_MIN && ftype < MLX5_FLOW_TYPE_MAX); 3346 fops = flow_get_drv_ops(ftype); 3347 3348 return fops->query(dev, flow, actions, data, error); 3349 } 3350 3351 /** 3352 * Query a flow. 3353 * 3354 * @see rte_flow_query() 3355 * @see rte_flow_ops 3356 */ 3357 int 3358 mlx5_flow_query(struct rte_eth_dev *dev, 3359 struct rte_flow *flow, 3360 const struct rte_flow_action *actions, 3361 void *data, 3362 struct rte_flow_error *error) 3363 { 3364 int ret; 3365 3366 ret = flow_drv_query(dev, flow, actions, data, error); 3367 if (ret < 0) 3368 return ret; 3369 return 0; 3370 } 3371 3372 /** 3373 * Convert a flow director filter to a generic flow. 3374 * 3375 * @param dev 3376 * Pointer to Ethernet device. 3377 * @param fdir_filter 3378 * Flow director filter to add. 3379 * @param attributes 3380 * Generic flow parameters structure. 3381 * 3382 * @return 3383 * 0 on success, a negative errno value otherwise and rte_errno is set. 3384 */ 3385 static int 3386 flow_fdir_filter_convert(struct rte_eth_dev *dev, 3387 const struct rte_eth_fdir_filter *fdir_filter, 3388 struct mlx5_fdir *attributes) 3389 { 3390 struct mlx5_priv *priv = dev->data->dev_private; 3391 const struct rte_eth_fdir_input *input = &fdir_filter->input; 3392 const struct rte_eth_fdir_masks *mask = 3393 &dev->data->dev_conf.fdir_conf.mask; 3394 3395 /* Validate queue number. */ 3396 if (fdir_filter->action.rx_queue >= priv->rxqs_n) { 3397 DRV_LOG(ERR, "port %u invalid queue number %d", 3398 dev->data->port_id, fdir_filter->action.rx_queue); 3399 rte_errno = EINVAL; 3400 return -rte_errno; 3401 } 3402 attributes->attr.ingress = 1; 3403 attributes->items[0] = (struct rte_flow_item) { 3404 .type = RTE_FLOW_ITEM_TYPE_ETH, 3405 .spec = &attributes->l2, 3406 .mask = &attributes->l2_mask, 3407 }; 3408 switch (fdir_filter->action.behavior) { 3409 case RTE_ETH_FDIR_ACCEPT: 3410 attributes->actions[0] = (struct rte_flow_action){ 3411 .type = RTE_FLOW_ACTION_TYPE_QUEUE, 3412 .conf = &attributes->queue, 3413 }; 3414 break; 3415 case RTE_ETH_FDIR_REJECT: 3416 attributes->actions[0] = (struct rte_flow_action){ 3417 .type = RTE_FLOW_ACTION_TYPE_DROP, 3418 }; 3419 break; 3420 default: 3421 DRV_LOG(ERR, "port %u invalid behavior %d", 3422 dev->data->port_id, 3423 fdir_filter->action.behavior); 3424 rte_errno = ENOTSUP; 3425 return -rte_errno; 3426 } 3427 attributes->queue.index = fdir_filter->action.rx_queue; 3428 /* Handle L3. */ 3429 switch (fdir_filter->input.flow_type) { 3430 case RTE_ETH_FLOW_NONFRAG_IPV4_UDP: 3431 case RTE_ETH_FLOW_NONFRAG_IPV4_TCP: 3432 case RTE_ETH_FLOW_NONFRAG_IPV4_OTHER: 3433 attributes->l3.ipv4.hdr = (struct rte_ipv4_hdr){ 3434 .src_addr = input->flow.ip4_flow.src_ip, 3435 .dst_addr = input->flow.ip4_flow.dst_ip, 3436 .time_to_live = input->flow.ip4_flow.ttl, 3437 .type_of_service = input->flow.ip4_flow.tos, 3438 }; 3439 attributes->l3_mask.ipv4.hdr = (struct rte_ipv4_hdr){ 3440 .src_addr = mask->ipv4_mask.src_ip, 3441 .dst_addr = mask->ipv4_mask.dst_ip, 3442 .time_to_live = mask->ipv4_mask.ttl, 3443 .type_of_service = mask->ipv4_mask.tos, 3444 .next_proto_id = mask->ipv4_mask.proto, 3445 }; 3446 attributes->items[1] = (struct rte_flow_item){ 3447 .type = RTE_FLOW_ITEM_TYPE_IPV4, 3448 .spec = &attributes->l3, 3449 .mask = &attributes->l3_mask, 3450 }; 3451 break; 3452 case RTE_ETH_FLOW_NONFRAG_IPV6_UDP: 3453 case RTE_ETH_FLOW_NONFRAG_IPV6_TCP: 3454 case RTE_ETH_FLOW_NONFRAG_IPV6_OTHER: 3455 attributes->l3.ipv6.hdr = (struct rte_ipv6_hdr){ 3456 .hop_limits = input->flow.ipv6_flow.hop_limits, 3457 .proto = input->flow.ipv6_flow.proto, 3458 }; 3459 3460 memcpy(attributes->l3.ipv6.hdr.src_addr, 3461 input->flow.ipv6_flow.src_ip, 3462 RTE_DIM(attributes->l3.ipv6.hdr.src_addr)); 3463 memcpy(attributes->l3.ipv6.hdr.dst_addr, 3464 input->flow.ipv6_flow.dst_ip, 3465 RTE_DIM(attributes->l3.ipv6.hdr.src_addr)); 3466 memcpy(attributes->l3_mask.ipv6.hdr.src_addr, 3467 mask->ipv6_mask.src_ip, 3468 RTE_DIM(attributes->l3_mask.ipv6.hdr.src_addr)); 3469 memcpy(attributes->l3_mask.ipv6.hdr.dst_addr, 3470 mask->ipv6_mask.dst_ip, 3471 RTE_DIM(attributes->l3_mask.ipv6.hdr.src_addr)); 3472 attributes->items[1] = (struct rte_flow_item){ 3473 .type = RTE_FLOW_ITEM_TYPE_IPV6, 3474 .spec = &attributes->l3, 3475 .mask = &attributes->l3_mask, 3476 }; 3477 break; 3478 default: 3479 DRV_LOG(ERR, "port %u invalid flow type%d", 3480 dev->data->port_id, fdir_filter->input.flow_type); 3481 rte_errno = ENOTSUP; 3482 return -rte_errno; 3483 } 3484 /* Handle L4. */ 3485 switch (fdir_filter->input.flow_type) { 3486 case RTE_ETH_FLOW_NONFRAG_IPV4_UDP: 3487 attributes->l4.udp.hdr = (struct rte_udp_hdr){ 3488 .src_port = input->flow.udp4_flow.src_port, 3489 .dst_port = input->flow.udp4_flow.dst_port, 3490 }; 3491 attributes->l4_mask.udp.hdr = (struct rte_udp_hdr){ 3492 .src_port = mask->src_port_mask, 3493 .dst_port = mask->dst_port_mask, 3494 }; 3495 attributes->items[2] = (struct rte_flow_item){ 3496 .type = RTE_FLOW_ITEM_TYPE_UDP, 3497 .spec = &attributes->l4, 3498 .mask = &attributes->l4_mask, 3499 }; 3500 break; 3501 case RTE_ETH_FLOW_NONFRAG_IPV4_TCP: 3502 attributes->l4.tcp.hdr = (struct rte_tcp_hdr){ 3503 .src_port = input->flow.tcp4_flow.src_port, 3504 .dst_port = input->flow.tcp4_flow.dst_port, 3505 }; 3506 attributes->l4_mask.tcp.hdr = (struct rte_tcp_hdr){ 3507 .src_port = mask->src_port_mask, 3508 .dst_port = mask->dst_port_mask, 3509 }; 3510 attributes->items[2] = (struct rte_flow_item){ 3511 .type = RTE_FLOW_ITEM_TYPE_TCP, 3512 .spec = &attributes->l4, 3513 .mask = &attributes->l4_mask, 3514 }; 3515 break; 3516 case RTE_ETH_FLOW_NONFRAG_IPV6_UDP: 3517 attributes->l4.udp.hdr = (struct rte_udp_hdr){ 3518 .src_port = input->flow.udp6_flow.src_port, 3519 .dst_port = input->flow.udp6_flow.dst_port, 3520 }; 3521 attributes->l4_mask.udp.hdr = (struct rte_udp_hdr){ 3522 .src_port = mask->src_port_mask, 3523 .dst_port = mask->dst_port_mask, 3524 }; 3525 attributes->items[2] = (struct rte_flow_item){ 3526 .type = RTE_FLOW_ITEM_TYPE_UDP, 3527 .spec = &attributes->l4, 3528 .mask = &attributes->l4_mask, 3529 }; 3530 break; 3531 case RTE_ETH_FLOW_NONFRAG_IPV6_TCP: 3532 attributes->l4.tcp.hdr = (struct rte_tcp_hdr){ 3533 .src_port = input->flow.tcp6_flow.src_port, 3534 .dst_port = input->flow.tcp6_flow.dst_port, 3535 }; 3536 attributes->l4_mask.tcp.hdr = (struct rte_tcp_hdr){ 3537 .src_port = mask->src_port_mask, 3538 .dst_port = mask->dst_port_mask, 3539 }; 3540 attributes->items[2] = (struct rte_flow_item){ 3541 .type = RTE_FLOW_ITEM_TYPE_TCP, 3542 .spec = &attributes->l4, 3543 .mask = &attributes->l4_mask, 3544 }; 3545 break; 3546 case RTE_ETH_FLOW_NONFRAG_IPV4_OTHER: 3547 case RTE_ETH_FLOW_NONFRAG_IPV6_OTHER: 3548 break; 3549 default: 3550 DRV_LOG(ERR, "port %u invalid flow type%d", 3551 dev->data->port_id, fdir_filter->input.flow_type); 3552 rte_errno = ENOTSUP; 3553 return -rte_errno; 3554 } 3555 return 0; 3556 } 3557 3558 #define FLOW_FDIR_CMP(f1, f2, fld) \ 3559 memcmp(&(f1)->fld, &(f2)->fld, sizeof(f1->fld)) 3560 3561 /** 3562 * Compare two FDIR flows. If items and actions are identical, the two flows are 3563 * regarded as same. 3564 * 3565 * @param dev 3566 * Pointer to Ethernet device. 3567 * @param f1 3568 * FDIR flow to compare. 3569 * @param f2 3570 * FDIR flow to compare. 3571 * 3572 * @return 3573 * Zero on match, 1 otherwise. 3574 */ 3575 static int 3576 flow_fdir_cmp(const struct mlx5_fdir *f1, const struct mlx5_fdir *f2) 3577 { 3578 if (FLOW_FDIR_CMP(f1, f2, attr) || 3579 FLOW_FDIR_CMP(f1, f2, l2) || 3580 FLOW_FDIR_CMP(f1, f2, l2_mask) || 3581 FLOW_FDIR_CMP(f1, f2, l3) || 3582 FLOW_FDIR_CMP(f1, f2, l3_mask) || 3583 FLOW_FDIR_CMP(f1, f2, l4) || 3584 FLOW_FDIR_CMP(f1, f2, l4_mask) || 3585 FLOW_FDIR_CMP(f1, f2, actions[0].type)) 3586 return 1; 3587 if (f1->actions[0].type == RTE_FLOW_ACTION_TYPE_QUEUE && 3588 FLOW_FDIR_CMP(f1, f2, queue)) 3589 return 1; 3590 return 0; 3591 } 3592 3593 /** 3594 * Search device flow list to find out a matched FDIR flow. 3595 * 3596 * @param dev 3597 * Pointer to Ethernet device. 3598 * @param fdir_flow 3599 * FDIR flow to lookup. 3600 * 3601 * @return 3602 * Pointer of flow if found, NULL otherwise. 3603 */ 3604 static struct rte_flow * 3605 flow_fdir_filter_lookup(struct rte_eth_dev *dev, struct mlx5_fdir *fdir_flow) 3606 { 3607 struct mlx5_priv *priv = dev->data->dev_private; 3608 struct rte_flow *flow = NULL; 3609 3610 assert(fdir_flow); 3611 TAILQ_FOREACH(flow, &priv->flows, next) { 3612 if (flow->fdir && !flow_fdir_cmp(flow->fdir, fdir_flow)) { 3613 DRV_LOG(DEBUG, "port %u found FDIR flow %p", 3614 dev->data->port_id, (void *)flow); 3615 break; 3616 } 3617 } 3618 return flow; 3619 } 3620 3621 /** 3622 * Add new flow director filter and store it in list. 3623 * 3624 * @param dev 3625 * Pointer to Ethernet device. 3626 * @param fdir_filter 3627 * Flow director filter to add. 3628 * 3629 * @return 3630 * 0 on success, a negative errno value otherwise and rte_errno is set. 3631 */ 3632 static int 3633 flow_fdir_filter_add(struct rte_eth_dev *dev, 3634 const struct rte_eth_fdir_filter *fdir_filter) 3635 { 3636 struct mlx5_priv *priv = dev->data->dev_private; 3637 struct mlx5_fdir *fdir_flow; 3638 struct rte_flow *flow; 3639 int ret; 3640 3641 fdir_flow = rte_zmalloc(__func__, sizeof(*fdir_flow), 0); 3642 if (!fdir_flow) { 3643 rte_errno = ENOMEM; 3644 return -rte_errno; 3645 } 3646 ret = flow_fdir_filter_convert(dev, fdir_filter, fdir_flow); 3647 if (ret) 3648 goto error; 3649 flow = flow_fdir_filter_lookup(dev, fdir_flow); 3650 if (flow) { 3651 rte_errno = EEXIST; 3652 goto error; 3653 } 3654 flow = flow_list_create(dev, &priv->flows, &fdir_flow->attr, 3655 fdir_flow->items, fdir_flow->actions, true, 3656 NULL); 3657 if (!flow) 3658 goto error; 3659 assert(!flow->fdir); 3660 flow->fdir = fdir_flow; 3661 DRV_LOG(DEBUG, "port %u created FDIR flow %p", 3662 dev->data->port_id, (void *)flow); 3663 return 0; 3664 error: 3665 rte_free(fdir_flow); 3666 return -rte_errno; 3667 } 3668 3669 /** 3670 * Delete specific filter. 3671 * 3672 * @param dev 3673 * Pointer to Ethernet device. 3674 * @param fdir_filter 3675 * Filter to be deleted. 3676 * 3677 * @return 3678 * 0 on success, a negative errno value otherwise and rte_errno is set. 3679 */ 3680 static int 3681 flow_fdir_filter_delete(struct rte_eth_dev *dev, 3682 const struct rte_eth_fdir_filter *fdir_filter) 3683 { 3684 struct mlx5_priv *priv = dev->data->dev_private; 3685 struct rte_flow *flow; 3686 struct mlx5_fdir fdir_flow = { 3687 .attr.group = 0, 3688 }; 3689 int ret; 3690 3691 ret = flow_fdir_filter_convert(dev, fdir_filter, &fdir_flow); 3692 if (ret) 3693 return -rte_errno; 3694 flow = flow_fdir_filter_lookup(dev, &fdir_flow); 3695 if (!flow) { 3696 rte_errno = ENOENT; 3697 return -rte_errno; 3698 } 3699 flow_list_destroy(dev, &priv->flows, flow); 3700 DRV_LOG(DEBUG, "port %u deleted FDIR flow %p", 3701 dev->data->port_id, (void *)flow); 3702 return 0; 3703 } 3704 3705 /** 3706 * Update queue for specific filter. 3707 * 3708 * @param dev 3709 * Pointer to Ethernet device. 3710 * @param fdir_filter 3711 * Filter to be updated. 3712 * 3713 * @return 3714 * 0 on success, a negative errno value otherwise and rte_errno is set. 3715 */ 3716 static int 3717 flow_fdir_filter_update(struct rte_eth_dev *dev, 3718 const struct rte_eth_fdir_filter *fdir_filter) 3719 { 3720 int ret; 3721 3722 ret = flow_fdir_filter_delete(dev, fdir_filter); 3723 if (ret) 3724 return ret; 3725 return flow_fdir_filter_add(dev, fdir_filter); 3726 } 3727 3728 /** 3729 * Flush all filters. 3730 * 3731 * @param dev 3732 * Pointer to Ethernet device. 3733 */ 3734 static void 3735 flow_fdir_filter_flush(struct rte_eth_dev *dev) 3736 { 3737 struct mlx5_priv *priv = dev->data->dev_private; 3738 3739 mlx5_flow_list_flush(dev, &priv->flows); 3740 } 3741 3742 /** 3743 * Get flow director information. 3744 * 3745 * @param dev 3746 * Pointer to Ethernet device. 3747 * @param[out] fdir_info 3748 * Resulting flow director information. 3749 */ 3750 static void 3751 flow_fdir_info_get(struct rte_eth_dev *dev, struct rte_eth_fdir_info *fdir_info) 3752 { 3753 struct rte_eth_fdir_masks *mask = 3754 &dev->data->dev_conf.fdir_conf.mask; 3755 3756 fdir_info->mode = dev->data->dev_conf.fdir_conf.mode; 3757 fdir_info->guarant_spc = 0; 3758 rte_memcpy(&fdir_info->mask, mask, sizeof(fdir_info->mask)); 3759 fdir_info->max_flexpayload = 0; 3760 fdir_info->flow_types_mask[0] = 0; 3761 fdir_info->flex_payload_unit = 0; 3762 fdir_info->max_flex_payload_segment_num = 0; 3763 fdir_info->flex_payload_limit = 0; 3764 memset(&fdir_info->flex_conf, 0, sizeof(fdir_info->flex_conf)); 3765 } 3766 3767 /** 3768 * Deal with flow director operations. 3769 * 3770 * @param dev 3771 * Pointer to Ethernet device. 3772 * @param filter_op 3773 * Operation to perform. 3774 * @param arg 3775 * Pointer to operation-specific structure. 3776 * 3777 * @return 3778 * 0 on success, a negative errno value otherwise and rte_errno is set. 3779 */ 3780 static int 3781 flow_fdir_ctrl_func(struct rte_eth_dev *dev, enum rte_filter_op filter_op, 3782 void *arg) 3783 { 3784 enum rte_fdir_mode fdir_mode = 3785 dev->data->dev_conf.fdir_conf.mode; 3786 3787 if (filter_op == RTE_ETH_FILTER_NOP) 3788 return 0; 3789 if (fdir_mode != RTE_FDIR_MODE_PERFECT && 3790 fdir_mode != RTE_FDIR_MODE_PERFECT_MAC_VLAN) { 3791 DRV_LOG(ERR, "port %u flow director mode %d not supported", 3792 dev->data->port_id, fdir_mode); 3793 rte_errno = EINVAL; 3794 return -rte_errno; 3795 } 3796 switch (filter_op) { 3797 case RTE_ETH_FILTER_ADD: 3798 return flow_fdir_filter_add(dev, arg); 3799 case RTE_ETH_FILTER_UPDATE: 3800 return flow_fdir_filter_update(dev, arg); 3801 case RTE_ETH_FILTER_DELETE: 3802 return flow_fdir_filter_delete(dev, arg); 3803 case RTE_ETH_FILTER_FLUSH: 3804 flow_fdir_filter_flush(dev); 3805 break; 3806 case RTE_ETH_FILTER_INFO: 3807 flow_fdir_info_get(dev, arg); 3808 break; 3809 default: 3810 DRV_LOG(DEBUG, "port %u unknown operation %u", 3811 dev->data->port_id, filter_op); 3812 rte_errno = EINVAL; 3813 return -rte_errno; 3814 } 3815 return 0; 3816 } 3817 3818 /** 3819 * Manage filter operations. 3820 * 3821 * @param dev 3822 * Pointer to Ethernet device structure. 3823 * @param filter_type 3824 * Filter type. 3825 * @param filter_op 3826 * Operation to perform. 3827 * @param arg 3828 * Pointer to operation-specific structure. 3829 * 3830 * @return 3831 * 0 on success, a negative errno value otherwise and rte_errno is set. 3832 */ 3833 int 3834 mlx5_dev_filter_ctrl(struct rte_eth_dev *dev, 3835 enum rte_filter_type filter_type, 3836 enum rte_filter_op filter_op, 3837 void *arg) 3838 { 3839 switch (filter_type) { 3840 case RTE_ETH_FILTER_GENERIC: 3841 if (filter_op != RTE_ETH_FILTER_GET) { 3842 rte_errno = EINVAL; 3843 return -rte_errno; 3844 } 3845 *(const void **)arg = &mlx5_flow_ops; 3846 return 0; 3847 case RTE_ETH_FILTER_FDIR: 3848 return flow_fdir_ctrl_func(dev, filter_op, arg); 3849 default: 3850 DRV_LOG(ERR, "port %u filter type (%d) not supported", 3851 dev->data->port_id, filter_type); 3852 rte_errno = ENOTSUP; 3853 return -rte_errno; 3854 } 3855 return 0; 3856 } 3857 3858 #define MLX5_POOL_QUERY_FREQ_US 1000000 3859 3860 /** 3861 * Set the periodic procedure for triggering asynchronous batch queries for all 3862 * the counter pools. 3863 * 3864 * @param[in] sh 3865 * Pointer to mlx5_ibv_shared object. 3866 */ 3867 void 3868 mlx5_set_query_alarm(struct mlx5_ibv_shared *sh) 3869 { 3870 struct mlx5_pools_container *cont = MLX5_CNT_CONTAINER(sh, 0, 0); 3871 uint32_t pools_n = rte_atomic16_read(&cont->n_valid); 3872 uint32_t us; 3873 3874 cont = MLX5_CNT_CONTAINER(sh, 1, 0); 3875 pools_n += rte_atomic16_read(&cont->n_valid); 3876 us = MLX5_POOL_QUERY_FREQ_US / pools_n; 3877 DRV_LOG(DEBUG, "Set alarm for %u pools each %u us", pools_n, us); 3878 if (rte_eal_alarm_set(us, mlx5_flow_query_alarm, sh)) { 3879 sh->cmng.query_thread_on = 0; 3880 DRV_LOG(ERR, "Cannot reinitialize query alarm"); 3881 } else { 3882 sh->cmng.query_thread_on = 1; 3883 } 3884 } 3885 3886 /** 3887 * The periodic procedure for triggering asynchronous batch queries for all the 3888 * counter pools. This function is probably called by the host thread. 3889 * 3890 * @param[in] arg 3891 * The parameter for the alarm process. 3892 */ 3893 void 3894 mlx5_flow_query_alarm(void *arg) 3895 { 3896 struct mlx5_ibv_shared *sh = arg; 3897 struct mlx5_devx_obj *dcs; 3898 uint16_t offset; 3899 int ret; 3900 uint8_t batch = sh->cmng.batch; 3901 uint16_t pool_index = sh->cmng.pool_index; 3902 struct mlx5_pools_container *cont; 3903 struct mlx5_pools_container *mcont; 3904 struct mlx5_flow_counter_pool *pool; 3905 3906 if (sh->cmng.pending_queries >= MLX5_MAX_PENDING_QUERIES) 3907 goto set_alarm; 3908 next_container: 3909 cont = MLX5_CNT_CONTAINER(sh, batch, 1); 3910 mcont = MLX5_CNT_CONTAINER(sh, batch, 0); 3911 /* Check if resize was done and need to flip a container. */ 3912 if (cont != mcont) { 3913 if (cont->pools) { 3914 /* Clean the old container. */ 3915 rte_free(cont->pools); 3916 memset(cont, 0, sizeof(*cont)); 3917 } 3918 rte_cio_wmb(); 3919 /* Flip the host container. */ 3920 sh->cmng.mhi[batch] ^= (uint8_t)2; 3921 cont = mcont; 3922 } 3923 if (!cont->pools) { 3924 /* 2 empty containers case is unexpected. */ 3925 if (unlikely(batch != sh->cmng.batch)) 3926 goto set_alarm; 3927 batch ^= 0x1; 3928 pool_index = 0; 3929 goto next_container; 3930 } 3931 pool = cont->pools[pool_index]; 3932 if (pool->raw_hw) 3933 /* There is a pool query in progress. */ 3934 goto set_alarm; 3935 pool->raw_hw = 3936 LIST_FIRST(&sh->cmng.free_stat_raws); 3937 if (!pool->raw_hw) 3938 /* No free counter statistics raw memory. */ 3939 goto set_alarm; 3940 dcs = (struct mlx5_devx_obj *)(uintptr_t)rte_atomic64_read 3941 (&pool->a64_dcs); 3942 offset = batch ? 0 : dcs->id % MLX5_COUNTERS_PER_POOL; 3943 ret = mlx5_devx_cmd_flow_counter_query(dcs, 0, MLX5_COUNTERS_PER_POOL - 3944 offset, NULL, NULL, 3945 pool->raw_hw->mem_mng->dm->id, 3946 (void *)(uintptr_t) 3947 (pool->raw_hw->data + offset), 3948 sh->devx_comp, 3949 (uint64_t)(uintptr_t)pool); 3950 if (ret) { 3951 DRV_LOG(ERR, "Failed to trigger asynchronous query for dcs ID" 3952 " %d", pool->min_dcs->id); 3953 pool->raw_hw = NULL; 3954 goto set_alarm; 3955 } 3956 pool->raw_hw->min_dcs_id = dcs->id; 3957 LIST_REMOVE(pool->raw_hw, next); 3958 sh->cmng.pending_queries++; 3959 pool_index++; 3960 if (pool_index >= rte_atomic16_read(&cont->n_valid)) { 3961 batch ^= 0x1; 3962 pool_index = 0; 3963 } 3964 set_alarm: 3965 sh->cmng.batch = batch; 3966 sh->cmng.pool_index = pool_index; 3967 mlx5_set_query_alarm(sh); 3968 } 3969 3970 /** 3971 * Handler for the HW respond about ready values from an asynchronous batch 3972 * query. This function is probably called by the host thread. 3973 * 3974 * @param[in] sh 3975 * The pointer to the shared IB device context. 3976 * @param[in] async_id 3977 * The Devx async ID. 3978 * @param[in] status 3979 * The status of the completion. 3980 */ 3981 void 3982 mlx5_flow_async_pool_query_handle(struct mlx5_ibv_shared *sh, 3983 uint64_t async_id, int status) 3984 { 3985 struct mlx5_flow_counter_pool *pool = 3986 (struct mlx5_flow_counter_pool *)(uintptr_t)async_id; 3987 struct mlx5_counter_stats_raw *raw_to_free; 3988 3989 if (unlikely(status)) { 3990 raw_to_free = pool->raw_hw; 3991 } else { 3992 raw_to_free = pool->raw; 3993 rte_spinlock_lock(&pool->sl); 3994 pool->raw = pool->raw_hw; 3995 rte_spinlock_unlock(&pool->sl); 3996 rte_atomic64_add(&pool->query_gen, 1); 3997 /* Be sure the new raw counters data is updated in memory. */ 3998 rte_cio_wmb(); 3999 } 4000 LIST_INSERT_HEAD(&sh->cmng.free_stat_raws, raw_to_free, next); 4001 pool->raw_hw = NULL; 4002 sh->cmng.pending_queries--; 4003 } 4004 4005 /** 4006 * Translate the rte_flow group index to HW table value. 4007 * 4008 * @param[in] attributes 4009 * Pointer to flow attributes 4010 * @param[in] external 4011 * Value is part of flow rule created by request external to PMD. 4012 * @param[in] group 4013 * rte_flow group index value. 4014 * @param[out] table 4015 * HW table value. 4016 * @param[out] error 4017 * Pointer to error structure. 4018 * 4019 * @return 4020 * 0 on success, a negative errno value otherwise and rte_errno is set. 4021 */ 4022 int 4023 mlx5_flow_group_to_table(const struct rte_flow_attr *attributes, bool external, 4024 uint32_t group, uint32_t *table, 4025 struct rte_flow_error *error) 4026 { 4027 if (attributes->transfer && external) { 4028 if (group == UINT32_MAX) 4029 return rte_flow_error_set 4030 (error, EINVAL, 4031 RTE_FLOW_ERROR_TYPE_ATTR_GROUP, 4032 NULL, 4033 "group index not supported"); 4034 *table = group + 1; 4035 } else { 4036 *table = group; 4037 } 4038 return 0; 4039 } 4040