1 /* SPDX-License-Identifier: BSD-3-Clause 2 * Copyright 2015 6WIND S.A. 3 * Copyright 2015 Mellanox Technologies, Ltd 4 */ 5 6 #ifndef RTE_PMD_MLX5_DEFS_H_ 7 #define RTE_PMD_MLX5_DEFS_H_ 8 9 #include <rte_ethdev_driver.h> 10 #include <rte_vxlan.h> 11 12 #include "mlx5_autoconf.h" 13 14 /* Reported driver name. */ 15 #define MLX5_DRIVER_NAME "net_mlx5" 16 17 /* Maximum number of simultaneous VLAN filters. */ 18 #define MLX5_MAX_VLAN_IDS 128 19 20 /* 21 * Request TX completion every time descriptors reach this threshold since 22 * the previous request. Must be a power of two for performance reasons. 23 */ 24 #define MLX5_TX_COMP_THRESH 32u 25 26 /* 27 * Request TX completion every time the total number of WQEBBs used for inlining 28 * packets exceeds the size of WQ divided by this divisor. Better to be power of 29 * two for performance. 30 */ 31 #define MLX5_TX_COMP_THRESH_INLINE_DIV (1 << 3) 32 33 /* 34 * Maximal amount of normal completion CQEs 35 * processed in one call of tx_burst() routine. 36 */ 37 #define MLX5_TX_COMP_MAX_CQE 2u 38 39 40 /* Size of per-queue MR cache array for linear search. */ 41 #define MLX5_MR_CACHE_N 8 42 43 /* Size of MR cache table for binary search. */ 44 #define MLX5_MR_BTREE_CACHE_N 256 45 46 /* 47 * If defined, only use software counters. The PMD will never ask the hardware 48 * for these, and many of them won't be available. 49 */ 50 #ifndef MLX5_PMD_SOFT_COUNTERS 51 #define MLX5_PMD_SOFT_COUNTERS 1 52 #endif 53 54 /* Switch port ID parameters for bonding configurations. */ 55 #define MLX5_PORT_ID_BONDING_PF_MASK 0xf 56 #define MLX5_PORT_ID_BONDING_PF_SHIFT 0xf 57 58 /* Alarm timeout. */ 59 #define MLX5_ALARM_TIMEOUT_US 100000 60 61 /* Maximum number of extended statistics counters. */ 62 #define MLX5_MAX_XSTATS 32 63 64 /* Maximum Packet headers size (L2+L3+L4) for TSO. */ 65 #define MLX5_MAX_TSO_HEADER (128u + 34u) 66 67 /* Inline data size required by NICs. */ 68 #define MLX5_INLINE_HSIZE_NONE 0 69 #define MLX5_INLINE_HSIZE_L2 (sizeof(struct rte_ether_hdr) + \ 70 sizeof(struct rte_vlan_hdr)) 71 #define MLX5_INLINE_HSIZE_L3 (MLX5_INLINE_HSIZE_L2 + \ 72 sizeof(struct rte_ipv6_hdr)) 73 #define MLX5_INLINE_HSIZE_L4 (MLX5_INLINE_HSIZE_L3 + \ 74 sizeof(struct rte_tcp_hdr)) 75 #define MLX5_INLINE_HSIZE_INNER_L2 (MLX5_INLINE_HSIZE_L3 + \ 76 sizeof(struct rte_udp_hdr) + \ 77 sizeof(struct rte_vxlan_hdr) + \ 78 sizeof(struct rte_ether_hdr) + \ 79 sizeof(struct rte_vlan_hdr)) 80 #define MLX5_INLINE_HSIZE_INNER_L3 (MLX5_INLINE_HSIZE_INNER_L2 + \ 81 sizeof(struct rte_ipv6_hdr)) 82 #define MLX5_INLINE_HSIZE_INNER_L4 (MLX5_INLINE_HSIZE_INNER_L3 + \ 83 sizeof(struct rte_tcp_hdr)) 84 85 /* Threshold of buffer replenishment for vectorized Rx. */ 86 #define MLX5_VPMD_RXQ_RPLNSH_THRESH(n) \ 87 (RTE_MIN(MLX5_VPMD_RX_MAX_BURST, (unsigned int)(n) >> 2)) 88 89 /* Maximum size of burst for vectorized Rx. */ 90 #define MLX5_VPMD_RX_MAX_BURST 64U 91 92 /* Recommended optimal burst size. */ 93 #define MLX5_RX_DEFAULT_BURST 64U 94 #define MLX5_TX_DEFAULT_BURST 64U 95 96 /* Number of packets vectorized Rx can simultaneously process in a loop. */ 97 #define MLX5_VPMD_DESCS_PER_LOOP 4 98 99 /* Mask of RSS on source only or destination only. */ 100 #define MLX5_RSS_SRC_DST_ONLY (ETH_RSS_L3_SRC_ONLY | ETH_RSS_L3_DST_ONLY | \ 101 ETH_RSS_L4_SRC_ONLY | ETH_RSS_L4_DST_ONLY) 102 103 /* Supported RSS */ 104 #define MLX5_RSS_HF_MASK (~(ETH_RSS_IP | ETH_RSS_UDP | ETH_RSS_TCP | \ 105 MLX5_RSS_SRC_DST_ONLY)) 106 107 /* Timeout in seconds to get a valid link status. */ 108 #define MLX5_LINK_STATUS_TIMEOUT 10 109 110 /* Number of times to retry retrieving the physical link information. */ 111 #define MLX5_GET_LINK_STATUS_RETRY_COUNT 3 112 113 /* Maximum number of UAR pages used by a port, 114 * These are the size and mask for an array of mutexes used to synchronize 115 * the access to port's UARs on platforms that do not support 64 bit writes. 116 * In such systems it is possible to issue the 64 bits DoorBells through two 117 * consecutive writes, each write 32 bits. The access to a UAR page (which can 118 * be accessible by all threads in the process) must be synchronized 119 * (for example, using a semaphore). Such a synchronization is not required 120 * when ringing DoorBells on different UAR pages. 121 * A port with 512 Tx queues uses 8, 4kBytes, UAR pages which are shared 122 * among the ports. 123 */ 124 #define MLX5_UAR_PAGE_NUM_MAX 64 125 #define MLX5_UAR_PAGE_NUM_MASK ((MLX5_UAR_PAGE_NUM_MAX) - 1) 126 127 /* Fields of memory mapping type in offset parameter of mmap() */ 128 #define MLX5_UAR_MMAP_CMD_SHIFT 8 129 #define MLX5_UAR_MMAP_CMD_MASK 0xff 130 131 /* Environment variable to control the doorbell register mapping. */ 132 #define MLX5_SHUT_UP_BF "MLX5_SHUT_UP_BF" 133 #if defined(RTE_ARCH_ARM64) 134 #define MLX5_SHUT_UP_BF_DEFAULT "0" 135 #else 136 #define MLX5_SHUT_UP_BF_DEFAULT "1" 137 #endif 138 139 #ifndef HAVE_MLX5DV_MMAP_GET_NC_PAGES_CMD 140 #define MLX5_MMAP_GET_NC_PAGES_CMD 3 141 #endif 142 143 /* Log 2 of the default number of strides per WQE for Multi-Packet RQ. */ 144 #define MLX5_MPRQ_STRIDE_NUM_N 6U 145 146 /* Log 2 of the default size of a stride per WQE for Multi-Packet RQ. */ 147 #define MLX5_MPRQ_STRIDE_SIZE_N 11U 148 149 /* Two-byte shift is disabled for Multi-Packet RQ. */ 150 #define MLX5_MPRQ_TWO_BYTE_SHIFT 0 151 152 /* 153 * Minimum size of packet to be memcpy'd instead of being attached as an 154 * external buffer. 155 */ 156 #define MLX5_MPRQ_MEMCPY_DEFAULT_LEN 128 157 158 /* Minimum number Rx queues to enable Multi-Packet RQ. */ 159 #define MLX5_MPRQ_MIN_RXQS 12 160 161 /* Cache size of mempool for Multi-Packet RQ. */ 162 #define MLX5_MPRQ_MP_CACHE_SZ 32U 163 164 /* MLX5_DV_XMETA_EN supported values. */ 165 #define MLX5_XMETA_MODE_LEGACY 0 166 #define MLX5_XMETA_MODE_META16 1 167 #define MLX5_XMETA_MODE_META32 2 168 169 /* MLX5_TX_DB_NC supported values. */ 170 #define MLX5_TXDB_CACHED 0 171 #define MLX5_TXDB_NCACHED 1 172 #define MLX5_TXDB_HEURISTIC 2 173 174 /* Tx accurate scheduling on timestamps parameters. */ 175 #define MLX5_TXPP_WAIT_INIT_TS 1000ul /* How long to wait timestamp. */ 176 #define MLX5_TXPP_CLKQ_SIZE 1 177 #define MLX5_TXPP_REARM ((1UL << MLX5_WQ_INDEX_WIDTH) / 4) 178 #define MLX5_TXPP_REARM_SQ_SIZE (((1UL << MLX5_CQ_INDEX_WIDTH) / \ 179 MLX5_TXPP_REARM) * 2) 180 #define MLX5_TXPP_REARM_CQ_SIZE (MLX5_TXPP_REARM_SQ_SIZE / 2) 181 /* The minimal size test packet to put into one WQE, padded by HW. */ 182 #define MLX5_TXPP_TEST_PKT_SIZE (sizeof(struct rte_ether_hdr) + \ 183 sizeof(struct rte_ipv4_hdr)) 184 185 /* Size of the simple hash table for metadata register table. */ 186 #define MLX5_FLOW_MREG_HTABLE_SZ 4096 187 #define MLX5_FLOW_MREG_HNAME "MARK_COPY_TABLE" 188 #define MLX5_DEFAULT_COPY_ID UINT32_MAX 189 190 /* Size of the simple hash table for header modify table. */ 191 #define MLX5_FLOW_HDR_MODIFY_HTABLE_SZ (1 << 16) 192 193 /* Size of the simple hash table for encap decap table. */ 194 #define MLX5_FLOW_ENCAP_DECAP_HTABLE_SZ (1 << 16) 195 196 /* Hairpin TX/RX queue configuration parameters. */ 197 #define MLX5_HAIRPIN_QUEUE_STRIDE 6 198 #define MLX5_HAIRPIN_JUMBO_LOG_SIZE (14 + 2) 199 200 /* Definition of static_assert found in /usr/include/assert.h */ 201 #ifndef HAVE_STATIC_ASSERT 202 #define static_assert _Static_assert 203 #endif 204 205 /* 206 * Defines the amount of retries to allocate the first UAR in the page. 207 * OFED 5.0.x and Upstream rdma_core before v29 returned the NULL as 208 * UAR base address if UAR was not the first object in the UAR page. 209 * It caused the PMD failure and we should try to get another UAR 210 * till we get the first one with non-NULL base address returned. 211 */ 212 #define MLX5_ALLOC_UAR_RETRY 32 213 214 #endif /* RTE_PMD_MLX5_DEFS_H_ */ 215