1 /* SPDX-License-Identifier: BSD-3-Clause 2 * Copyright 2015 6WIND S.A. 3 * Copyright 2015 Mellanox Technologies, Ltd 4 */ 5 6 #ifndef RTE_PMD_MLX5_DEFS_H_ 7 #define RTE_PMD_MLX5_DEFS_H_ 8 9 #include <ethdev_driver.h> 10 #include <rte_vxlan.h> 11 12 #include <mlx5_common_defs.h> 13 14 #include "mlx5_autoconf.h" 15 16 /* Maximum number of simultaneous VLAN filters. */ 17 #define MLX5_MAX_VLAN_IDS 128 18 19 /* 20 * Request TX completion every time descriptors reach this threshold since 21 * the previous request. Must be a power of two for performance reasons. 22 */ 23 #define MLX5_TX_COMP_THRESH 32u 24 25 /* 26 * Request TX completion every time the total number of WQEBBs used for inlining 27 * packets exceeds the size of WQ divided by this divisor. Better to be power of 28 * two for performance. 29 */ 30 #define MLX5_TX_COMP_THRESH_INLINE_DIV (1 << 3) 31 32 /* 33 * Maximal amount of normal completion CQEs 34 * processed in one call of tx_burst() routine. 35 */ 36 #define MLX5_TX_COMP_MAX_CQE 2u 37 38 /* 39 * If defined, only use software counters. The PMD will never ask the hardware 40 * for these, and many of them won't be available. 41 */ 42 #ifndef MLX5_PMD_SOFT_COUNTERS 43 #define MLX5_PMD_SOFT_COUNTERS 1 44 #endif 45 46 /* Maximum number of DCS created per port. */ 47 #define MLX5_HWS_CNT_DCS_NUM 4 48 49 /* Alarm timeout. */ 50 #define MLX5_ALARM_TIMEOUT_US 100000 51 52 /* Maximum number of extended statistics counters. */ 53 #define MLX5_MAX_XSTATS 64 54 55 /* Maximum Packet headers size (L2+L3+L4) for TSO. */ 56 #define MLX5_MAX_TSO_HEADER 192U 57 58 /* Inline data size required by NICs. */ 59 #define MLX5_INLINE_HSIZE_NONE 0 60 #define MLX5_INLINE_HSIZE_L2 (sizeof(struct rte_ether_hdr) + \ 61 sizeof(struct rte_vlan_hdr)) 62 #define MLX5_INLINE_HSIZE_L3 (MLX5_INLINE_HSIZE_L2 + \ 63 sizeof(struct rte_ipv6_hdr)) 64 #define MLX5_INLINE_HSIZE_L4 (MLX5_INLINE_HSIZE_L3 + \ 65 sizeof(struct rte_tcp_hdr)) 66 #define MLX5_INLINE_HSIZE_INNER_L2 (MLX5_INLINE_HSIZE_L3 + \ 67 sizeof(struct rte_udp_hdr) + \ 68 sizeof(struct rte_vxlan_hdr) + \ 69 sizeof(struct rte_ether_hdr) + \ 70 sizeof(struct rte_vlan_hdr)) 71 #define MLX5_INLINE_HSIZE_INNER_L3 (MLX5_INLINE_HSIZE_INNER_L2 + \ 72 sizeof(struct rte_ipv6_hdr)) 73 #define MLX5_INLINE_HSIZE_INNER_L4 (MLX5_INLINE_HSIZE_INNER_L3 + \ 74 sizeof(struct rte_tcp_hdr)) 75 76 /* Threshold of buffer replenishment for vectorized Rx. */ 77 #define MLX5_VPMD_RXQ_RPLNSH_THRESH(n) \ 78 (RTE_MIN(MLX5_VPMD_RX_MAX_BURST, (unsigned int)(n) >> 2)) 79 80 /* Maximum size of burst for vectorized Rx. */ 81 #define MLX5_VPMD_RX_MAX_BURST 64U 82 83 /* Recommended optimal burst size. */ 84 #define MLX5_RX_DEFAULT_BURST 64U 85 #define MLX5_TX_DEFAULT_BURST 64U 86 87 /* Number of packets vectorized Rx can simultaneously process in a loop. */ 88 #define MLX5_VPMD_DESCS_PER_LOOP 4 89 90 /* Mask of RSS on source only or destination only. */ 91 #define MLX5_RSS_SRC_DST_ONLY (RTE_ETH_RSS_L3_SRC_ONLY | RTE_ETH_RSS_L3_DST_ONLY | \ 92 RTE_ETH_RSS_L4_SRC_ONLY | RTE_ETH_RSS_L4_DST_ONLY) 93 94 /* Supported RSS */ 95 #define MLX5_RSS_HF_MASK (~(RTE_ETH_RSS_IP | RTE_ETH_RSS_UDP | RTE_ETH_RSS_TCP | \ 96 MLX5_RSS_SRC_DST_ONLY | RTE_ETH_RSS_ESP)) 97 98 /* Timeout in seconds to get a valid link status. */ 99 #define MLX5_LINK_STATUS_TIMEOUT 10 100 101 /* Number of times to retry retrieving the physical link information. */ 102 #define MLX5_GET_LINK_STATUS_RETRY_COUNT 3 103 104 /* Maximum number of UAR pages used by a port, 105 * These are the size and mask for an array of mutexes used to synchronize 106 * the access to port's UARs on platforms that do not support 64 bit writes. 107 * In such systems it is possible to issue the 64 bits DoorBells through two 108 * consecutive writes, each write 32 bits. The access to a UAR page (which can 109 * be accessible by all threads in the process) must be synchronized 110 * (for example, using a semaphore). Such a synchronization is not required 111 * when ringing DoorBells on different UAR pages. 112 * A port with 512 Tx queues uses 8, 4kBytes, UAR pages which are shared 113 * among the ports. 114 */ 115 #define MLX5_UAR_PAGE_NUM_MAX 64 116 #define MLX5_UAR_PAGE_NUM_MASK ((MLX5_UAR_PAGE_NUM_MAX) - 1) 117 118 /* Log 2 of the default number of strides per WQE for Multi-Packet RQ. */ 119 #define MLX5_MPRQ_DEFAULT_LOG_STRIDE_NUM 6U 120 121 /* Log 2 of the default size of a stride per WQE for Multi-Packet RQ. */ 122 #define MLX5_MPRQ_DEFAULT_LOG_STRIDE_SIZE 11U 123 124 /* Two-byte shift is disabled for Multi-Packet RQ. */ 125 #define MLX5_MPRQ_TWO_BYTE_SHIFT 0 126 127 /* 128 * Minimum size of packet to be memcpy'd instead of being attached as an 129 * external buffer. 130 */ 131 #define MLX5_MPRQ_MEMCPY_DEFAULT_LEN 128 132 133 /* Minimum number Rx queues to enable Multi-Packet RQ. */ 134 #define MLX5_MPRQ_MIN_RXQS 12 135 136 /* Cache size of mempool for Multi-Packet RQ. */ 137 #define MLX5_MPRQ_MP_CACHE_SZ 32U 138 139 /* MLX5_DV_XMETA_EN supported values. */ 140 #define MLX5_XMETA_MODE_LEGACY 0 141 #define MLX5_XMETA_MODE_META16 1 142 #define MLX5_XMETA_MODE_META32 2 143 /* Provide info on patrial hw miss. Implies MLX5_XMETA_MODE_META16 */ 144 #define MLX5_XMETA_MODE_MISS_INFO 3 145 /* Only valid in HWS, 32bits extended META without MARK support in FDB. */ 146 #define MLX5_XMETA_MODE_META32_HWS 4 147 148 /* Tx accurate scheduling on timestamps parameters. */ 149 #define MLX5_TXPP_WAIT_INIT_TS 1000ul /* How long to wait timestamp. */ 150 #define MLX5_TXPP_CLKQ_SIZE 1 151 #define MLX5_TXPP_REARM ((1UL << MLX5_WQ_INDEX_WIDTH) / 4) 152 #define MLX5_TXPP_REARM_SQ_SIZE (((1UL << MLX5_CQ_INDEX_WIDTH) / \ 153 MLX5_TXPP_REARM) * 2) 154 #define MLX5_TXPP_REARM_CQ_SIZE (MLX5_TXPP_REARM_SQ_SIZE / 2) 155 /* The minimal size test packet to put into one WQE, padded by HW. */ 156 #define MLX5_TXPP_TEST_PKT_SIZE (sizeof(struct rte_ether_hdr) + \ 157 sizeof(struct rte_ipv4_hdr)) 158 159 /* Size of the simple hash table for metadata register table. */ 160 #define MLX5_FLOW_MREG_HTABLE_SZ 64 161 #define MLX5_FLOW_MREG_HNAME "MARK_COPY_TABLE" 162 #define MLX5_DEFAULT_COPY_ID UINT32_MAX 163 164 /* Size of the simple hash table for header modify table. */ 165 #define MLX5_FLOW_HDR_MODIFY_HTABLE_SZ (1 << 15) 166 167 /* Size of the simple hash table for encap decap table. */ 168 #define MLX5_FLOW_ENCAP_DECAP_HTABLE_SZ (1 << 12) 169 170 /* Size of the hash table for tag table. */ 171 #define MLX5_TAGS_HLIST_ARRAY_SIZE (1 << 15) 172 173 /* Size fo the hash table for SFT table. */ 174 #define MLX5_FLOW_SFT_HLIST_ARRAY_SIZE 4096 175 176 /* Hairpin TX/RX queue configuration parameters. */ 177 #define MLX5_HAIRPIN_QUEUE_STRIDE 6 178 #define MLX5_HAIRPIN_JUMBO_LOG_SIZE (14 + 2) 179 180 /* Maximum number of indirect actions supported by rte_flow */ 181 #define MLX5_MAX_INDIRECT_ACTIONS 3 182 183 /* Maximum number of external Rx queues supported by rte_flow */ 184 #define MLX5_MAX_EXT_RX_QUEUES (UINT16_MAX - RTE_PMD_MLX5_EXTERNAL_RX_QUEUE_ID_MIN + 1) 185 186 /* Maximum number of external Tx queues supported by rte_flow */ 187 #define MLX5_MAX_EXT_TX_QUEUES (UINT16_MAX - MLX5_EXTERNAL_TX_QUEUE_ID_MIN + 1) 188 189 /* 190 * Linux definition of static_assert is found in /usr/include/assert.h. 191 * Windows does not require a redefinition. 192 */ 193 #if !defined(HAVE_STATIC_ASSERT) && !defined(RTE_EXEC_ENV_WINDOWS) 194 #define static_assert _Static_assert 195 #endif 196 197 #define MLX5_CNT_SVC_CYCLE_TIME_DEFAULT 500 198 199 #endif /* RTE_PMD_MLX5_DEFS_H_ */ 200