1 /*- 2 * BSD LICENSE 3 * 4 * Copyright 2015 6WIND S.A. 5 * Copyright 2015 Mellanox. 6 * 7 * Redistribution and use in source and binary forms, with or without 8 * modification, are permitted provided that the following conditions 9 * are met: 10 * 11 * * Redistributions of source code must retain the above copyright 12 * notice, this list of conditions and the following disclaimer. 13 * * Redistributions in binary form must reproduce the above copyright 14 * notice, this list of conditions and the following disclaimer in 15 * the documentation and/or other materials provided with the 16 * distribution. 17 * * Neither the name of 6WIND S.A. nor the names of its 18 * contributors may be used to endorse or promote products derived 19 * from this software without specific prior written permission. 20 * 21 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 22 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 23 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 24 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 25 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 26 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 27 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 28 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 29 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 30 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 31 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 32 */ 33 34 #ifndef RTE_PMD_MLX5_DEFS_H_ 35 #define RTE_PMD_MLX5_DEFS_H_ 36 37 #include <rte_ethdev_driver.h> 38 39 #include "mlx5_autoconf.h" 40 41 /* Reported driver name. */ 42 #define MLX5_DRIVER_NAME "net_mlx5" 43 44 /* Maximum number of simultaneous MAC addresses. */ 45 #define MLX5_MAX_MAC_ADDRESSES 128 46 47 /* Maximum number of simultaneous VLAN filters. */ 48 #define MLX5_MAX_VLAN_IDS 128 49 50 /* 51 * Request TX completion every time descriptors reach this threshold since 52 * the previous request. Must be a power of two for performance reasons. 53 */ 54 #define MLX5_TX_COMP_THRESH 32 55 56 /* 57 * Request TX completion every time the total number of WQEBBs used for inlining 58 * packets exceeds the size of WQ divided by this divisor. Better to be power of 59 * two for performance. 60 */ 61 #define MLX5_TX_COMP_THRESH_INLINE_DIV (1 << 3) 62 63 /* 64 * Maximum number of cached Memory Pools (MPs) per TX queue. Each RTE MP 65 * from which buffers are to be transmitted will have to be mapped by this 66 * driver to their own Memory Region (MR). This is a slow operation. 67 * 68 * This value is always 1 for RX queues. 69 */ 70 #ifndef MLX5_PMD_TX_MP_CACHE 71 #define MLX5_PMD_TX_MP_CACHE 8 72 #endif 73 74 /* 75 * If defined, only use software counters. The PMD will never ask the hardware 76 * for these, and many of them won't be available. 77 */ 78 #ifndef MLX5_PMD_SOFT_COUNTERS 79 #define MLX5_PMD_SOFT_COUNTERS 1 80 #endif 81 82 /* Alarm timeout. */ 83 #define MLX5_ALARM_TIMEOUT_US 100000 84 85 /* Maximum number of extended statistics counters. */ 86 #define MLX5_MAX_XSTATS 32 87 88 /* Maximum Packet headers size (L2+L3+L4) for TSO. */ 89 #define MLX5_MAX_TSO_HEADER 128 90 91 /* Default minimum number of Tx queues for vectorized Tx. */ 92 #define MLX5_VPMD_MIN_TXQS 4 93 94 /* Threshold of buffer replenishment for vectorized Rx. */ 95 #define MLX5_VPMD_RXQ_RPLNSH_THRESH 64U 96 97 /* Maximum size of burst for vectorized Rx. */ 98 #define MLX5_VPMD_RX_MAX_BURST MLX5_VPMD_RXQ_RPLNSH_THRESH 99 100 /* 101 * Maximum size of burst for vectorized Tx. This is related to the maximum size 102 * of Enhanced MPW (eMPW) WQE as vectorized Tx is supported with eMPW. 103 * Careful when changing, large value can cause WQE DS to overlap. 104 */ 105 #define MLX5_VPMD_TX_MAX_BURST 32U 106 107 /* Number of packets vectorized Rx can simultaneously process in a loop. */ 108 #define MLX5_VPMD_DESCS_PER_LOOP 4 109 110 /* Supported RSS */ 111 #define MLX5_RSS_HF_MASK (~(ETH_RSS_IP | ETH_RSS_UDP | ETH_RSS_TCP)) 112 113 /* Maximum number of attempts to query link status before giving up. */ 114 #define MLX5_MAX_LINK_QUERY_ATTEMPTS 5 115 116 /* Reserved address space for UAR mapping. */ 117 #define MLX5_UAR_SIZE (1ULL << 32) 118 119 /* Offset of reserved UAR address space to hugepage memory. Offset is used here 120 * to minimize possibility of address next to hugepage being used by other code 121 * in either primary or secondary process, failing to map TX UAR would make TX 122 * packets invisible to HW. 123 */ 124 #define MLX5_UAR_OFFSET (1ULL << 32) 125 126 #endif /* RTE_PMD_MLX5_DEFS_H_ */ 127