1 /* SPDX-License-Identifier: BSD-3-Clause 2 * Copyright 2015 6WIND S.A. 3 * Copyright 2015 Mellanox Technologies, Ltd 4 */ 5 6 #ifndef RTE_PMD_MLX5_DEFS_H_ 7 #define RTE_PMD_MLX5_DEFS_H_ 8 9 #include <rte_ethdev_driver.h> 10 11 #include "mlx5_autoconf.h" 12 13 /* Reported driver name. */ 14 #define MLX5_DRIVER_NAME "net_mlx5" 15 16 /* Maximum number of simultaneous unicast MAC addresses. */ 17 #define MLX5_MAX_UC_MAC_ADDRESSES 128 18 /* Maximum number of simultaneous Multicast MAC addresses. */ 19 #define MLX5_MAX_MC_MAC_ADDRESSES 128 20 /* Maximum number of simultaneous MAC addresses. */ 21 #define MLX5_MAX_MAC_ADDRESSES \ 22 (MLX5_MAX_UC_MAC_ADDRESSES + MLX5_MAX_MC_MAC_ADDRESSES) 23 24 /* Maximum number of simultaneous VLAN filters. */ 25 #define MLX5_MAX_VLAN_IDS 128 26 27 /* 28 * Request TX completion every time descriptors reach this threshold since 29 * the previous request. Must be a power of two for performance reasons. 30 */ 31 #define MLX5_TX_COMP_THRESH 32 32 33 /* 34 * Request TX completion every time the total number of WQEBBs used for inlining 35 * packets exceeds the size of WQ divided by this divisor. Better to be power of 36 * two for performance. 37 */ 38 #define MLX5_TX_COMP_THRESH_INLINE_DIV (1 << 3) 39 40 /* Size of per-queue MR cache array for linear search. */ 41 #define MLX5_MR_CACHE_N 8 42 43 /* Size of MR cache table for binary search. */ 44 #define MLX5_MR_BTREE_CACHE_N 256 45 46 /* 47 * If defined, only use software counters. The PMD will never ask the hardware 48 * for these, and many of them won't be available. 49 */ 50 #ifndef MLX5_PMD_SOFT_COUNTERS 51 #define MLX5_PMD_SOFT_COUNTERS 1 52 #endif 53 54 /* Alarm timeout. */ 55 #define MLX5_ALARM_TIMEOUT_US 100000 56 57 /* Maximum number of extended statistics counters. */ 58 #define MLX5_MAX_XSTATS 32 59 60 /* Maximum Packet headers size (L2+L3+L4) for TSO. */ 61 #define MLX5_MAX_TSO_HEADER 192 62 63 /* Default maximum number of Tx queues for vectorized Tx. */ 64 #if defined(RTE_ARCH_ARM64) 65 #define MLX5_VPMD_MAX_TXQS 8 66 #else 67 #define MLX5_VPMD_MAX_TXQS 4 68 #endif 69 #define MLX5_VPMD_MAX_TXQS_BLUEFIELD 16 70 71 /* Threshold of buffer replenishment for vectorized Rx. */ 72 #define MLX5_VPMD_RXQ_RPLNSH_THRESH(n) \ 73 (RTE_MIN(MLX5_VPMD_RX_MAX_BURST, (unsigned int)(n) >> 2)) 74 75 /* Maximum size of burst for vectorized Rx. */ 76 #define MLX5_VPMD_RX_MAX_BURST 64U 77 78 /* 79 * Maximum size of burst for vectorized Tx. This is related to the maximum size 80 * of Enhanced MPW (eMPW) WQE as vectorized Tx is supported with eMPW. 81 * Careful when changing, large value can cause WQE DS to overlap. 82 */ 83 #define MLX5_VPMD_TX_MAX_BURST 32U 84 85 /* Number of packets vectorized Rx can simultaneously process in a loop. */ 86 #define MLX5_VPMD_DESCS_PER_LOOP 4 87 88 /* Supported RSS */ 89 #define MLX5_RSS_HF_MASK (~(ETH_RSS_IP | ETH_RSS_UDP | ETH_RSS_TCP)) 90 91 /* Timeout in seconds to get a valid link status. */ 92 #define MLX5_LINK_STATUS_TIMEOUT 10 93 94 /* Maximum number of UAR pages used by a port, 95 * These are the size and mask for an array of mutexes used to synchronize 96 * the access to port's UARs on platforms that do not support 64 bit writes. 97 * In such systems it is possible to issue the 64 bits DoorBells through two 98 * consecutive writes, each write 32 bits. The access to a UAR page (which can 99 * be accessible by all threads in the process) must be synchronized 100 * (for example, using a semaphore). Such a synchronization is not required 101 * when ringing DoorBells on different UAR pages. 102 * A port with 512 Tx queues uses 8, 4kBytes, UAR pages which are shared 103 * among the ports. 104 */ 105 #define MLX5_UAR_PAGE_NUM_MAX 64 106 #define MLX5_UAR_PAGE_NUM_MASK ((MLX5_UAR_PAGE_NUM_MAX) - 1) 107 108 /* Log 2 of the default number of strides per WQE for Multi-Packet RQ. */ 109 #define MLX5_MPRQ_STRIDE_NUM_N 6U 110 111 /* Two-byte shift is disabled for Multi-Packet RQ. */ 112 #define MLX5_MPRQ_TWO_BYTE_SHIFT 0 113 114 /* 115 * Minimum size of packet to be memcpy'd instead of being attached as an 116 * external buffer. 117 */ 118 #define MLX5_MPRQ_MEMCPY_DEFAULT_LEN 128 119 120 /* Minimum number Rx queues to enable Multi-Packet RQ. */ 121 #define MLX5_MPRQ_MIN_RXQS 12 122 123 /* Cache size of mempool for Multi-Packet RQ. */ 124 #define MLX5_MPRQ_MP_CACHE_SZ 32U 125 126 /* Definition of static_assert found in /usr/include/assert.h */ 127 #ifndef HAVE_STATIC_ASSERT 128 #define static_assert _Static_assert 129 #endif 130 131 #endif /* RTE_PMD_MLX5_DEFS_H_ */ 132