1 /* SPDX-License-Identifier: BSD-3-Clause 2 * Copyright 2015 6WIND S.A. 3 * Copyright 2015 Mellanox Technologies, Ltd 4 */ 5 6 #ifndef RTE_PMD_MLX5_H_ 7 #define RTE_PMD_MLX5_H_ 8 9 #include <stddef.h> 10 #include <stdbool.h> 11 #include <stdint.h> 12 #include <limits.h> 13 #include <net/if.h> 14 #include <netinet/in.h> 15 #include <sys/queue.h> 16 17 /* Verbs header. */ 18 /* ISO C doesn't support unnamed structs/unions, disabling -pedantic. */ 19 #ifdef PEDANTIC 20 #pragma GCC diagnostic ignored "-Wpedantic" 21 #endif 22 #include <infiniband/verbs.h> 23 #ifdef PEDANTIC 24 #pragma GCC diagnostic error "-Wpedantic" 25 #endif 26 27 #include <rte_pci.h> 28 #include <rte_ether.h> 29 #include <rte_ethdev_driver.h> 30 #include <rte_rwlock.h> 31 #include <rte_interrupts.h> 32 #include <rte_errno.h> 33 #include <rte_flow.h> 34 35 #include <mlx5_glue.h> 36 #include <mlx5_devx_cmds.h> 37 #include <mlx5_prm.h> 38 #include <mlx5_nl.h> 39 #include <mlx5_common_mp.h> 40 #include <mlx5_common_mr.h> 41 42 #include "mlx5_defs.h" 43 #include "mlx5_utils.h" 44 #include "mlx5_autoconf.h" 45 46 47 enum mlx5_ipool_index { 48 #ifdef HAVE_IBV_FLOW_DV_SUPPORT 49 MLX5_IPOOL_DECAP_ENCAP = 0, /* Pool for encap/decap resource. */ 50 MLX5_IPOOL_PUSH_VLAN, /* Pool for push vlan resource. */ 51 MLX5_IPOOL_TAG, /* Pool for tag resource. */ 52 MLX5_IPOOL_PORT_ID, /* Pool for port id resource. */ 53 MLX5_IPOOL_JUMP, /* Pool for jump resource. */ 54 #endif 55 MLX5_IPOOL_MTR, /* Pool for meter resource. */ 56 MLX5_IPOOL_MCP, /* Pool for metadata resource. */ 57 MLX5_IPOOL_HRXQ, /* Pool for hrxq resource. */ 58 MLX5_IPOOL_MLX5_FLOW, /* Pool for mlx5 flow handle. */ 59 MLX5_IPOOL_RTE_FLOW, /* Pool for rte_flow. */ 60 MLX5_IPOOL_MAX, 61 }; 62 63 /** Key string for IPC. */ 64 #define MLX5_MP_NAME "net_mlx5_mp" 65 66 67 LIST_HEAD(mlx5_dev_list, mlx5_ibv_shared); 68 69 /* Shared data between primary and secondary processes. */ 70 struct mlx5_shared_data { 71 rte_spinlock_t lock; 72 /* Global spinlock for primary and secondary processes. */ 73 int init_done; /* Whether primary has done initialization. */ 74 unsigned int secondary_cnt; /* Number of secondary processes init'd. */ 75 struct mlx5_dev_list mem_event_cb_list; 76 rte_rwlock_t mem_event_rwlock; 77 }; 78 79 /* Per-process data structure, not visible to other processes. */ 80 struct mlx5_local_data { 81 int init_done; /* Whether a secondary has done initialization. */ 82 }; 83 84 extern struct mlx5_shared_data *mlx5_shared_data; 85 86 struct mlx5_counter_ctrl { 87 /* Name of the counter. */ 88 char dpdk_name[RTE_ETH_XSTATS_NAME_SIZE]; 89 /* Name of the counter on the device table. */ 90 char ctr_name[RTE_ETH_XSTATS_NAME_SIZE]; 91 uint32_t ib:1; /**< Nonzero for IB counters. */ 92 }; 93 94 struct mlx5_xstats_ctrl { 95 /* Number of device stats. */ 96 uint16_t stats_n; 97 /* Number of device stats identified by PMD. */ 98 uint16_t mlx5_stats_n; 99 /* Index in the device counters table. */ 100 uint16_t dev_table_idx[MLX5_MAX_XSTATS]; 101 uint64_t base[MLX5_MAX_XSTATS]; 102 uint64_t xstats[MLX5_MAX_XSTATS]; 103 uint64_t hw_stats[MLX5_MAX_XSTATS]; 104 struct mlx5_counter_ctrl info[MLX5_MAX_XSTATS]; 105 }; 106 107 struct mlx5_stats_ctrl { 108 /* Base for imissed counter. */ 109 uint64_t imissed_base; 110 uint64_t imissed; 111 }; 112 113 /* Default PMD specific parameter value. */ 114 #define MLX5_ARG_UNSET (-1) 115 116 #define MLX5_LRO_SUPPORTED(dev) \ 117 (((struct mlx5_priv *)((dev)->data->dev_private))->config.lro.supported) 118 119 /* Maximal size of coalesced segment for LRO is set in chunks of 256 Bytes. */ 120 #define MLX5_LRO_SEG_CHUNK_SIZE 256u 121 122 /* Maximal size of aggregated LRO packet. */ 123 #define MLX5_MAX_LRO_SIZE (UINT8_MAX * MLX5_LRO_SEG_CHUNK_SIZE) 124 125 /* LRO configurations structure. */ 126 struct mlx5_lro_config { 127 uint32_t supported:1; /* Whether LRO is supported. */ 128 uint32_t timeout; /* User configuration. */ 129 }; 130 131 /* 132 * Device configuration structure. 133 * 134 * Merged configuration from: 135 * 136 * - Device capabilities, 137 * - User device parameters disabled features. 138 */ 139 struct mlx5_dev_config { 140 unsigned int hw_csum:1; /* Checksum offload is supported. */ 141 unsigned int hw_vlan_strip:1; /* VLAN stripping is supported. */ 142 unsigned int hw_vlan_insert:1; /* VLAN insertion in WQE is supported. */ 143 unsigned int hw_fcs_strip:1; /* FCS stripping is supported. */ 144 unsigned int hw_padding:1; /* End alignment padding is supported. */ 145 unsigned int vf:1; /* This is a VF. */ 146 unsigned int tunnel_en:1; 147 /* Whether tunnel stateless offloads are supported. */ 148 unsigned int mpls_en:1; /* MPLS over GRE/UDP is enabled. */ 149 unsigned int cqe_comp:1; /* CQE compression is enabled. */ 150 unsigned int cqe_pad:1; /* CQE padding is enabled. */ 151 unsigned int tso:1; /* Whether TSO is supported. */ 152 unsigned int rx_vec_en:1; /* Rx vector is enabled. */ 153 unsigned int mr_ext_memseg_en:1; 154 /* Whether memseg should be extended for MR creation. */ 155 unsigned int l3_vxlan_en:1; /* Enable L3 VXLAN flow creation. */ 156 unsigned int vf_nl_en:1; /* Enable Netlink requests in VF mode. */ 157 unsigned int dv_esw_en:1; /* Enable E-Switch DV flow. */ 158 unsigned int dv_flow_en:1; /* Enable DV flow. */ 159 unsigned int dv_xmeta_en:2; /* Enable extensive flow metadata. */ 160 unsigned int swp:1; /* Tx generic tunnel checksum and TSO offload. */ 161 unsigned int devx:1; /* Whether devx interface is available or not. */ 162 unsigned int dest_tir:1; /* Whether advanced DR API is available. */ 163 struct { 164 unsigned int enabled:1; /* Whether MPRQ is enabled. */ 165 unsigned int stride_num_n; /* Number of strides. */ 166 unsigned int stride_size_n; /* Size of a stride. */ 167 unsigned int min_stride_size_n; /* Min size of a stride. */ 168 unsigned int max_stride_size_n; /* Max size of a stride. */ 169 unsigned int max_memcpy_len; 170 /* Maximum packet size to memcpy Rx packets. */ 171 unsigned int min_rxqs_num; 172 /* Rx queue count threshold to enable MPRQ. */ 173 } mprq; /* Configurations for Multi-Packet RQ. */ 174 int mps; /* Multi-packet send supported mode. */ 175 int dbnc; /* Skip doorbell register write barrier. */ 176 unsigned int flow_prio; /* Number of flow priorities. */ 177 enum modify_reg flow_mreg_c[MLX5_MREG_C_NUM]; 178 /* Availibility of mreg_c's. */ 179 unsigned int tso_max_payload_sz; /* Maximum TCP payload for TSO. */ 180 unsigned int ind_table_max_size; /* Maximum indirection table size. */ 181 unsigned int max_dump_files_num; /* Maximum dump files per queue. */ 182 unsigned int log_hp_size; /* Single hairpin queue data size in total. */ 183 int txqs_inline; /* Queue number threshold for inlining. */ 184 int txq_inline_min; /* Minimal amount of data bytes to inline. */ 185 int txq_inline_max; /* Max packet size for inlining with SEND. */ 186 int txq_inline_mpw; /* Max packet size for inlining with eMPW. */ 187 struct mlx5_hca_attr hca_attr; /* HCA attributes. */ 188 struct mlx5_lro_config lro; /* LRO configuration. */ 189 }; 190 191 192 /** 193 * Type of object being allocated. 194 */ 195 enum mlx5_verbs_alloc_type { 196 MLX5_VERBS_ALLOC_TYPE_NONE, 197 MLX5_VERBS_ALLOC_TYPE_TX_QUEUE, 198 MLX5_VERBS_ALLOC_TYPE_RX_QUEUE, 199 }; 200 201 /* Structure for VF VLAN workaround. */ 202 struct mlx5_vf_vlan { 203 uint32_t tag:12; 204 uint32_t created:1; 205 }; 206 207 /** 208 * Verbs allocator needs a context to know in the callback which kind of 209 * resources it is allocating. 210 */ 211 struct mlx5_verbs_alloc_ctx { 212 enum mlx5_verbs_alloc_type type; /* Kind of object being allocated. */ 213 const void *obj; /* Pointer to the DPDK object. */ 214 }; 215 216 /* Flow drop context necessary due to Verbs API. */ 217 struct mlx5_drop { 218 struct mlx5_hrxq *hrxq; /* Hash Rx queue queue. */ 219 struct mlx5_rxq_obj *rxq; /* Rx queue object. */ 220 }; 221 222 #define MLX5_COUNTERS_PER_POOL 512 223 #define MLX5_MAX_PENDING_QUERIES 4 224 #define MLX5_CNT_CONTAINER_RESIZE 64 225 #define MLX5_CNT_AGE_OFFSET 0x80000000 226 #define CNT_SIZE (sizeof(struct mlx5_flow_counter)) 227 #define CNTEXT_SIZE (sizeof(struct mlx5_flow_counter_ext)) 228 #define AGE_SIZE (sizeof(struct mlx5_age_param)) 229 #define MLX5_AGING_TIME_DELAY 7 230 231 #define CNT_POOL_TYPE_EXT (1 << 0) 232 #define CNT_POOL_TYPE_AGE (1 << 1) 233 #define IS_EXT_POOL(pool) (((pool)->type) & CNT_POOL_TYPE_EXT) 234 #define IS_AGE_POOL(pool) (((pool)->type) & CNT_POOL_TYPE_AGE) 235 #define MLX_CNT_IS_AGE(counter) ((counter) & MLX5_CNT_AGE_OFFSET ? 1 : 0) 236 237 #define MLX5_CNT_LEN(pool) \ 238 (CNT_SIZE + \ 239 (IS_AGE_POOL(pool) ? AGE_SIZE : 0) + \ 240 (IS_EXT_POOL(pool) ? CNTEXT_SIZE : 0)) 241 #define MLX5_POOL_GET_CNT(pool, index) \ 242 ((struct mlx5_flow_counter *) \ 243 ((uint8_t *)((pool) + 1) + (index) * (MLX5_CNT_LEN(pool)))) 244 #define MLX5_CNT_ARRAY_IDX(pool, cnt) \ 245 ((int)(((uint8_t *)(cnt) - (uint8_t *)((pool) + 1)) / \ 246 MLX5_CNT_LEN(pool))) 247 /* 248 * The pool index and offset of counter in the pool array makes up the 249 * counter index. In case the counter is from pool 0 and offset 0, it 250 * should plus 1 to avoid index 0, since 0 means invalid counter index 251 * currently. 252 */ 253 #define MLX5_MAKE_CNT_IDX(pi, offset) \ 254 ((pi) * MLX5_COUNTERS_PER_POOL + (offset) + 1) 255 #define MLX5_CNT_TO_CNT_EXT(pool, cnt) \ 256 ((struct mlx5_flow_counter_ext *)\ 257 ((uint8_t *)((cnt) + 1) + \ 258 (IS_AGE_POOL(pool) ? AGE_SIZE : 0))) 259 #define MLX5_GET_POOL_CNT_EXT(pool, offset) \ 260 MLX5_CNT_TO_CNT_EXT(pool, MLX5_POOL_GET_CNT((pool), (offset))) 261 #define MLX5_CNT_TO_AGE(cnt) \ 262 ((struct mlx5_age_param *)((cnt) + 1)) 263 264 struct mlx5_flow_counter_pool; 265 266 /*age status*/ 267 enum { 268 AGE_FREE, /* Initialized state. */ 269 AGE_CANDIDATE, /* Counter assigned to flows. */ 270 AGE_TMOUT, /* Timeout, wait for rte_flow_get_aged_flows and destroy. */ 271 }; 272 273 /* Counter age parameter. */ 274 struct mlx5_age_param { 275 rte_atomic16_t state; /**< Age state. */ 276 uint16_t port_id; /**< Port id of the counter. */ 277 uint32_t timeout:15; /**< Age timeout in unit of 0.1sec. */ 278 uint32_t expire:16; /**< Expire time(0.1sec) in the future. */ 279 void *context; /**< Flow counter age context. */ 280 }; 281 282 struct flow_counter_stats { 283 uint64_t hits; 284 uint64_t bytes; 285 }; 286 287 /* Generic counters information. */ 288 struct mlx5_flow_counter { 289 TAILQ_ENTRY(mlx5_flow_counter) next; 290 /**< Pointer to the next flow counter structure. */ 291 union { 292 uint64_t hits; /**< Reset value of hits packets. */ 293 int64_t query_gen; /**< Generation of the last release. */ 294 }; 295 uint64_t bytes; /**< Reset value of bytes. */ 296 void *action; /**< Pointer to the dv action. */ 297 }; 298 299 /* Extend counters information for none batch counters. */ 300 struct mlx5_flow_counter_ext { 301 uint32_t shared:1; /**< Share counter ID with other flow rules. */ 302 uint32_t batch: 1; 303 /**< Whether the counter was allocated by batch command. */ 304 uint32_t ref_cnt:30; /**< Reference counter. */ 305 uint32_t id; /**< User counter ID. */ 306 union { /**< Holds the counters for the rule. */ 307 #if defined(HAVE_IBV_DEVICE_COUNTERS_SET_V42) 308 struct ibv_counter_set *cs; 309 #elif defined(HAVE_IBV_DEVICE_COUNTERS_SET_V45) 310 struct ibv_counters *cs; 311 #endif 312 struct mlx5_devx_obj *dcs; /**< Counter Devx object. */ 313 }; 314 }; 315 316 317 TAILQ_HEAD(mlx5_counters, mlx5_flow_counter); 318 319 /* Generic counter pool structure - query is in pool resolution. */ 320 struct mlx5_flow_counter_pool { 321 TAILQ_ENTRY(mlx5_flow_counter_pool) next; 322 struct mlx5_counters counters; /* Free counter list. */ 323 union { 324 struct mlx5_devx_obj *min_dcs; 325 rte_atomic64_t a64_dcs; 326 }; 327 /* The devx object of the minimum counter ID. */ 328 rte_atomic64_t start_query_gen; /* Query start round. */ 329 rte_atomic64_t end_query_gen; /* Query end round. */ 330 uint32_t index; /* Pool index in container. */ 331 uint8_t type; /* Memory type behind the counter array. */ 332 rte_spinlock_t sl; /* The pool lock. */ 333 struct mlx5_counter_stats_raw *raw; 334 struct mlx5_counter_stats_raw *raw_hw; /* The raw on HW working. */ 335 }; 336 337 struct mlx5_counter_stats_raw; 338 339 /* Memory management structure for group of counter statistics raws. */ 340 struct mlx5_counter_stats_mem_mng { 341 LIST_ENTRY(mlx5_counter_stats_mem_mng) next; 342 struct mlx5_counter_stats_raw *raws; 343 struct mlx5_devx_obj *dm; 344 struct mlx5dv_devx_umem *umem; 345 }; 346 347 /* Raw memory structure for the counter statistics values of a pool. */ 348 struct mlx5_counter_stats_raw { 349 LIST_ENTRY(mlx5_counter_stats_raw) next; 350 int min_dcs_id; 351 struct mlx5_counter_stats_mem_mng *mem_mng; 352 volatile struct flow_counter_stats *data; 353 }; 354 355 TAILQ_HEAD(mlx5_counter_pools, mlx5_flow_counter_pool); 356 357 /* Container structure for counter pools. */ 358 struct mlx5_pools_container { 359 rte_atomic16_t n_valid; /* Number of valid pools. */ 360 uint16_t n; /* Number of pools. */ 361 struct mlx5_counter_pools pool_list; /* Counter pool list. */ 362 struct mlx5_flow_counter_pool **pools; /* Counter pool array. */ 363 struct mlx5_counter_stats_mem_mng *init_mem_mng; 364 /* Hold the memory management for the next allocated pools raws. */ 365 }; 366 367 /* Counter global management structure. */ 368 struct mlx5_flow_counter_mng { 369 uint8_t mhi[2][2]; /* master \ host and age \ no age container index. */ 370 struct mlx5_pools_container ccont[2 * 2][2]; 371 /* master \ host and age \ no age pools container. */ 372 struct mlx5_counters flow_counters; /* Legacy flow counter list. */ 373 uint8_t pending_queries; 374 uint8_t batch; 375 uint16_t pool_index; 376 uint8_t age; 377 uint8_t query_thread_on; 378 LIST_HEAD(mem_mngs, mlx5_counter_stats_mem_mng) mem_mngs; 379 LIST_HEAD(stat_raws, mlx5_counter_stats_raw) free_stat_raws; 380 }; 381 #define MLX5_AGE_EVENT_NEW 1 382 #define MLX5_AGE_TRIGGER 2 383 #define MLX5_AGE_SET(age_info, BIT) \ 384 ((age_info)->flags |= (1 << (BIT))) 385 #define MLX5_AGE_GET(age_info, BIT) \ 386 ((age_info)->flags & (1 << (BIT))) 387 #define GET_PORT_AGE_INFO(priv) \ 388 (&((priv)->sh->port[(priv)->ibv_port - 1].age_info)) 389 390 /* Aging information for per port. */ 391 struct mlx5_age_info { 392 uint8_t flags; /*Indicate if is new event or need be trigered*/ 393 struct mlx5_counters aged_counters; /* Aged flow counter list. */ 394 rte_spinlock_t aged_sl; /* Aged flow counter list lock. */ 395 }; 396 /* Per port data of shared IB device. */ 397 struct mlx5_ibv_shared_port { 398 uint32_t ih_port_id; 399 uint32_t devx_ih_port_id; 400 /* 401 * Interrupt handler port_id. Used by shared interrupt 402 * handler to find the corresponding rte_eth device 403 * by IB port index. If value is equal or greater 404 * RTE_MAX_ETHPORTS it means there is no subhandler 405 * installed for specified IB port index. 406 */ 407 struct mlx5_age_info age_info; 408 /* Aging information for per port. */ 409 }; 410 411 /* Table key of the hash organization. */ 412 union mlx5_flow_tbl_key { 413 struct { 414 /* Table ID should be at the lowest address. */ 415 uint32_t table_id; /**< ID of the table. */ 416 uint16_t reserved; /**< must be zero for comparison. */ 417 uint8_t domain; /**< 1 - FDB, 0 - NIC TX/RX. */ 418 uint8_t direction; /**< 1 - egress, 0 - ingress. */ 419 }; 420 uint64_t v64; /**< full 64bits value of key */ 421 }; 422 423 /* Table structure. */ 424 struct mlx5_flow_tbl_resource { 425 void *obj; /**< Pointer to DR table object. */ 426 rte_atomic32_t refcnt; /**< Reference counter. */ 427 }; 428 429 #define MLX5_MAX_TABLES UINT16_MAX 430 #define MLX5_FLOW_TABLE_LEVEL_METER (UINT16_MAX - 3) 431 #define MLX5_FLOW_TABLE_LEVEL_SUFFIX (UINT16_MAX - 2) 432 #define MLX5_HAIRPIN_TX_TABLE (UINT16_MAX - 1) 433 /* Reserve the last two tables for metadata register copy. */ 434 #define MLX5_FLOW_MREG_ACT_TABLE_GROUP (MLX5_MAX_TABLES - 1) 435 #define MLX5_FLOW_MREG_CP_TABLE_GROUP (MLX5_MAX_TABLES - 2) 436 /* Tables for metering splits should be added here. */ 437 #define MLX5_MAX_TABLES_EXTERNAL (MLX5_MAX_TABLES - 3) 438 #define MLX5_MAX_TABLES_FDB UINT16_MAX 439 440 #define MLX5_DBR_PAGE_SIZE 4096 /* Must be >= 512. */ 441 #define MLX5_DBR_SIZE 8 442 #define MLX5_DBR_PER_PAGE (MLX5_DBR_PAGE_SIZE / MLX5_DBR_SIZE) 443 #define MLX5_DBR_BITMAP_SIZE (MLX5_DBR_PER_PAGE / 64) 444 445 struct mlx5_devx_dbr_page { 446 /* Door-bell records, must be first member in structure. */ 447 uint8_t dbrs[MLX5_DBR_PAGE_SIZE]; 448 LIST_ENTRY(mlx5_devx_dbr_page) next; /* Pointer to the next element. */ 449 struct mlx5dv_devx_umem *umem; 450 uint32_t dbr_count; /* Number of door-bell records in use. */ 451 /* 1 bit marks matching door-bell is in use. */ 452 uint64_t dbr_bitmap[MLX5_DBR_BITMAP_SIZE]; 453 }; 454 455 /* ID generation structure. */ 456 struct mlx5_flow_id_pool { 457 uint32_t *free_arr; /**< Pointer to the a array of free values. */ 458 uint32_t base_index; 459 /**< The next index that can be used without any free elements. */ 460 uint32_t *curr; /**< Pointer to the index to pop. */ 461 uint32_t *last; /**< Pointer to the last element in the empty arrray. */ 462 uint32_t max_id; /**< Maximum id can be allocated from the pool. */ 463 }; 464 465 /* 466 * Shared Infiniband device context for Master/Representors 467 * which belong to same IB device with multiple IB ports. 468 **/ 469 struct mlx5_ibv_shared { 470 LIST_ENTRY(mlx5_ibv_shared) next; 471 uint32_t refcnt; 472 uint32_t devx:1; /* Opened with DV. */ 473 uint32_t max_port; /* Maximal IB device port index. */ 474 struct ibv_context *ctx; /* Verbs/DV context. */ 475 struct ibv_pd *pd; /* Protection Domain. */ 476 uint32_t pdn; /* Protection Domain number. */ 477 uint32_t tdn; /* Transport Domain number. */ 478 char ibdev_name[IBV_SYSFS_NAME_MAX]; /* IB device name. */ 479 char ibdev_path[IBV_SYSFS_PATH_MAX]; /* IB device path for secondary */ 480 struct ibv_device_attr_ex device_attr; /* Device properties. */ 481 LIST_ENTRY(mlx5_ibv_shared) mem_event_cb; 482 /**< Called by memory event callback. */ 483 struct mlx5_mr_share_cache share_cache; 484 /* Shared DV/DR flow data section. */ 485 pthread_mutex_t dv_mutex; /* DV context mutex. */ 486 uint32_t dv_meta_mask; /* flow META metadata supported mask. */ 487 uint32_t dv_mark_mask; /* flow MARK metadata supported mask. */ 488 uint32_t dv_regc0_mask; /* available bits of metatada reg_c[0]. */ 489 uint32_t dv_refcnt; /* DV/DR data reference counter. */ 490 void *fdb_domain; /* FDB Direct Rules name space handle. */ 491 void *rx_domain; /* RX Direct Rules name space handle. */ 492 void *tx_domain; /* TX Direct Rules name space handle. */ 493 struct mlx5_hlist *flow_tbls; 494 /* Direct Rules tables for FDB, NIC TX+RX */ 495 void *esw_drop_action; /* Pointer to DR E-Switch drop action. */ 496 void *pop_vlan_action; /* Pointer to DR pop VLAN action. */ 497 uint32_t encaps_decaps; /* Encap/decap action indexed memory list. */ 498 LIST_HEAD(modify_cmd, mlx5_flow_dv_modify_hdr_resource) modify_cmds; 499 struct mlx5_hlist *tag_table; 500 uint32_t port_id_action_list; /* List of port ID actions. */ 501 uint32_t push_vlan_action_list; /* List of push VLAN actions. */ 502 struct mlx5_flow_counter_mng cmng; /* Counters management structure. */ 503 struct mlx5_indexed_pool *ipool[MLX5_IPOOL_MAX]; 504 /* Memory Pool for mlx5 flow resources. */ 505 /* Shared interrupt handler section. */ 506 pthread_mutex_t intr_mutex; /* Interrupt config mutex. */ 507 uint32_t intr_cnt; /* Interrupt handler reference counter. */ 508 struct rte_intr_handle intr_handle; /* Interrupt handler for device. */ 509 uint32_t devx_intr_cnt; /* Devx interrupt handler reference counter. */ 510 struct rte_intr_handle intr_handle_devx; /* DEVX interrupt handler. */ 511 struct mlx5dv_devx_cmd_comp *devx_comp; /* DEVX async comp obj. */ 512 struct mlx5_devx_obj *tis; /* TIS object. */ 513 struct mlx5_devx_obj *td; /* Transport domain. */ 514 struct mlx5_flow_id_pool *flow_id_pool; /* Flow ID pool. */ 515 struct mlx5_ibv_shared_port port[]; /* per device port data array. */ 516 }; 517 518 /* Per-process private structure. */ 519 struct mlx5_proc_priv { 520 size_t uar_table_sz; 521 /* Size of UAR register table. */ 522 void *uar_table[]; 523 /* Table of UAR registers for each process. */ 524 }; 525 526 /* MTR profile list. */ 527 TAILQ_HEAD(mlx5_mtr_profiles, mlx5_flow_meter_profile); 528 /* MTR list. */ 529 TAILQ_HEAD(mlx5_flow_meters, mlx5_flow_meter); 530 531 #define MLX5_PROC_PRIV(port_id) \ 532 ((struct mlx5_proc_priv *)rte_eth_devices[port_id].process_private) 533 534 struct mlx5_priv { 535 struct rte_eth_dev_data *dev_data; /* Pointer to device data. */ 536 struct mlx5_ibv_shared *sh; /* Shared IB device context. */ 537 uint32_t ibv_port; /* IB device port number. */ 538 struct rte_pci_device *pci_dev; /* Backend PCI device. */ 539 struct rte_ether_addr mac[MLX5_MAX_MAC_ADDRESSES]; /* MAC addresses. */ 540 BITFIELD_DECLARE(mac_own, uint64_t, MLX5_MAX_MAC_ADDRESSES); 541 /* Bit-field of MAC addresses owned by the PMD. */ 542 uint16_t vlan_filter[MLX5_MAX_VLAN_IDS]; /* VLAN filters table. */ 543 unsigned int vlan_filter_n; /* Number of configured VLAN filters. */ 544 /* Device properties. */ 545 uint16_t mtu; /* Configured MTU. */ 546 unsigned int isolated:1; /* Whether isolated mode is enabled. */ 547 unsigned int representor:1; /* Device is a port representor. */ 548 unsigned int master:1; /* Device is a E-Switch master. */ 549 unsigned int dr_shared:1; /* DV/DR data is shared. */ 550 unsigned int counter_fallback:1; /* Use counter fallback management. */ 551 unsigned int mtr_en:1; /* Whether support meter. */ 552 unsigned int mtr_reg_share:1; /* Whether support meter REG_C share. */ 553 uint16_t domain_id; /* Switch domain identifier. */ 554 uint16_t vport_id; /* Associated VF vport index (if any). */ 555 uint32_t vport_meta_tag; /* Used for vport index match ove VF LAG. */ 556 uint32_t vport_meta_mask; /* Used for vport index field match mask. */ 557 int32_t representor_id; /* Port representor identifier. */ 558 int32_t pf_bond; /* >=0 means PF index in bonding configuration. */ 559 unsigned int if_index; /* Associated kernel network device index. */ 560 /* RX/TX queues. */ 561 unsigned int rxqs_n; /* RX queues array size. */ 562 unsigned int txqs_n; /* TX queues array size. */ 563 struct mlx5_rxq_data *(*rxqs)[]; /* RX queues. */ 564 struct mlx5_txq_data *(*txqs)[]; /* TX queues. */ 565 struct rte_mempool *mprq_mp; /* Mempool for Multi-Packet RQ. */ 566 struct rte_eth_rss_conf rss_conf; /* RSS configuration. */ 567 unsigned int (*reta_idx)[]; /* RETA index table. */ 568 unsigned int reta_idx_n; /* RETA index size. */ 569 struct mlx5_drop drop_queue; /* Flow drop queues. */ 570 uint32_t flows; /* RTE Flow rules. */ 571 uint32_t ctrl_flows; /* Control flow rules. */ 572 void *inter_flows; /* Intermediate resources for flow creation. */ 573 void *rss_desc; /* Intermediate rss description resources. */ 574 int flow_idx; /* Intermediate device flow index. */ 575 int flow_nested_idx; /* Intermediate device flow index, nested. */ 576 LIST_HEAD(rxq, mlx5_rxq_ctrl) rxqsctrl; /* DPDK Rx queues. */ 577 LIST_HEAD(rxqobj, mlx5_rxq_obj) rxqsobj; /* Verbs/DevX Rx queues. */ 578 uint32_t hrxqs; /* Verbs Hash Rx queues. */ 579 LIST_HEAD(txq, mlx5_txq_ctrl) txqsctrl; /* DPDK Tx queues. */ 580 LIST_HEAD(txqobj, mlx5_txq_obj) txqsobj; /* Verbs/DevX Tx queues. */ 581 /* Indirection tables. */ 582 LIST_HEAD(ind_tables, mlx5_ind_table_obj) ind_tbls; 583 /* Pointer to next element. */ 584 rte_atomic32_t refcnt; /**< Reference counter. */ 585 struct ibv_flow_action *verbs_action; 586 /**< Verbs modify header action object. */ 587 uint8_t ft_type; /**< Flow table type, Rx or Tx. */ 588 uint8_t max_lro_msg_size; 589 /* Tags resources cache. */ 590 uint32_t link_speed_capa; /* Link speed capabilities. */ 591 struct mlx5_xstats_ctrl xstats_ctrl; /* Extended stats control. */ 592 struct mlx5_stats_ctrl stats_ctrl; /* Stats control. */ 593 struct mlx5_dev_config config; /* Device configuration. */ 594 struct mlx5_verbs_alloc_ctx verbs_alloc_ctx; 595 /* Context for Verbs allocator. */ 596 int nl_socket_rdma; /* Netlink socket (NETLINK_RDMA). */ 597 int nl_socket_route; /* Netlink socket (NETLINK_ROUTE). */ 598 LIST_HEAD(dbrpage, mlx5_devx_dbr_page) dbrpgs; /* Door-bell pages. */ 599 struct mlx5_nl_vlan_vmwa_context *vmwa_context; /* VLAN WA context. */ 600 struct mlx5_flow_id_pool *qrss_id_pool; 601 struct mlx5_hlist *mreg_cp_tbl; 602 /* Hash table of Rx metadata register copy table. */ 603 uint8_t mtr_sfx_reg; /* Meter prefix-suffix flow match REG_C. */ 604 uint8_t mtr_color_reg; /* Meter color match REG_C. */ 605 struct mlx5_mtr_profiles flow_meter_profiles; /* MTR profile list. */ 606 struct mlx5_flow_meters flow_meters; /* MTR list. */ 607 #ifndef RTE_ARCH_64 608 rte_spinlock_t uar_lock_cq; /* CQs share a common distinct UAR */ 609 rte_spinlock_t uar_lock[MLX5_UAR_PAGE_NUM_MAX]; 610 /* UAR same-page access control required in 32bit implementations. */ 611 #endif 612 uint8_t skip_default_rss_reta; /* Skip configuration of default reta. */ 613 uint8_t fdb_def_rule; /* Whether fdb jump to table 1 is configured. */ 614 struct mlx5_mp_id mp_id; /* ID of a multi-process process */ 615 LIST_HEAD(fdir, mlx5_fdir_flow) fdir_flows; /* fdir flows. */ 616 }; 617 618 #define PORT_ID(priv) ((priv)->dev_data->port_id) 619 #define ETH_DEV(priv) (&rte_eth_devices[PORT_ID(priv)]) 620 621 /* mlx5.c */ 622 623 int mlx5_getenv_int(const char *); 624 int mlx5_proc_priv_init(struct rte_eth_dev *dev); 625 int64_t mlx5_get_dbr(struct rte_eth_dev *dev, 626 struct mlx5_devx_dbr_page **dbr_page); 627 int32_t mlx5_release_dbr(struct rte_eth_dev *dev, uint32_t umem_id, 628 uint64_t offset); 629 int mlx5_udp_tunnel_port_add(struct rte_eth_dev *dev, 630 struct rte_eth_udp_tunnel *udp_tunnel); 631 uint16_t mlx5_eth_find_next(uint16_t port_id, struct rte_pci_device *pci_dev); 632 633 /* Macro to iterate over all valid ports for mlx5 driver. */ 634 #define MLX5_ETH_FOREACH_DEV(port_id, pci_dev) \ 635 for (port_id = mlx5_eth_find_next(0, pci_dev); \ 636 port_id < RTE_MAX_ETHPORTS; \ 637 port_id = mlx5_eth_find_next(port_id + 1, pci_dev)) 638 639 /* mlx5_ethdev.c */ 640 641 int mlx5_get_ifname(const struct rte_eth_dev *dev, char (*ifname)[IF_NAMESIZE]); 642 int mlx5_get_master_ifname(const char *ibdev_path, char (*ifname)[IF_NAMESIZE]); 643 unsigned int mlx5_ifindex(const struct rte_eth_dev *dev); 644 int mlx5_ifreq(const struct rte_eth_dev *dev, int req, struct ifreq *ifr); 645 int mlx5_get_mtu(struct rte_eth_dev *dev, uint16_t *mtu); 646 int mlx5_set_flags(struct rte_eth_dev *dev, unsigned int keep, 647 unsigned int flags); 648 int mlx5_dev_configure(struct rte_eth_dev *dev); 649 int mlx5_dev_infos_get(struct rte_eth_dev *dev, struct rte_eth_dev_info *info); 650 int mlx5_read_clock(struct rte_eth_dev *dev, uint64_t *clock); 651 int mlx5_fw_version_get(struct rte_eth_dev *dev, char *fw_ver, size_t fw_size); 652 const uint32_t *mlx5_dev_supported_ptypes_get(struct rte_eth_dev *dev); 653 int mlx5_link_update(struct rte_eth_dev *dev, int wait_to_complete); 654 int mlx5_force_link_status_change(struct rte_eth_dev *dev, int status); 655 int mlx5_dev_set_mtu(struct rte_eth_dev *dev, uint16_t mtu); 656 int mlx5_dev_get_flow_ctrl(struct rte_eth_dev *dev, 657 struct rte_eth_fc_conf *fc_conf); 658 int mlx5_dev_set_flow_ctrl(struct rte_eth_dev *dev, 659 struct rte_eth_fc_conf *fc_conf); 660 void mlx5_dev_link_status_handler(void *arg); 661 void mlx5_dev_interrupt_handler(void *arg); 662 void mlx5_dev_interrupt_handler_devx(void *arg); 663 void mlx5_dev_interrupt_handler_uninstall(struct rte_eth_dev *dev); 664 void mlx5_dev_interrupt_handler_install(struct rte_eth_dev *dev); 665 void mlx5_dev_interrupt_handler_devx_uninstall(struct rte_eth_dev *dev); 666 void mlx5_dev_interrupt_handler_devx_install(struct rte_eth_dev *dev); 667 int mlx5_set_link_down(struct rte_eth_dev *dev); 668 int mlx5_set_link_up(struct rte_eth_dev *dev); 669 int mlx5_is_removed(struct rte_eth_dev *dev); 670 eth_tx_burst_t mlx5_select_tx_function(struct rte_eth_dev *dev); 671 eth_rx_burst_t mlx5_select_rx_function(struct rte_eth_dev *dev); 672 struct mlx5_priv *mlx5_port_to_eswitch_info(uint16_t port, bool valid); 673 struct mlx5_priv *mlx5_dev_to_eswitch_info(struct rte_eth_dev *dev); 674 int mlx5_sysfs_switch_info(unsigned int ifindex, 675 struct mlx5_switch_info *info); 676 void mlx5_sysfs_check_switch_info(bool device_dir, 677 struct mlx5_switch_info *switch_info); 678 void mlx5_translate_port_name(const char *port_name_in, 679 struct mlx5_switch_info *port_info_out); 680 void mlx5_intr_callback_unregister(const struct rte_intr_handle *handle, 681 rte_intr_callback_fn cb_fn, void *cb_arg); 682 int mlx5_get_module_info(struct rte_eth_dev *dev, 683 struct rte_eth_dev_module_info *modinfo); 684 int mlx5_get_module_eeprom(struct rte_eth_dev *dev, 685 struct rte_dev_eeprom_info *info); 686 int mlx5_hairpin_cap_get(struct rte_eth_dev *dev, 687 struct rte_eth_hairpin_cap *cap); 688 int mlx5_dev_configure_rss_reta(struct rte_eth_dev *dev); 689 690 /* mlx5_mac.c */ 691 692 int mlx5_get_mac(struct rte_eth_dev *dev, uint8_t (*mac)[RTE_ETHER_ADDR_LEN]); 693 void mlx5_mac_addr_remove(struct rte_eth_dev *dev, uint32_t index); 694 int mlx5_mac_addr_add(struct rte_eth_dev *dev, struct rte_ether_addr *mac, 695 uint32_t index, uint32_t vmdq); 696 struct mlx5_nl_vlan_vmwa_context *mlx5_vlan_vmwa_init 697 (struct rte_eth_dev *dev, uint32_t ifindex); 698 int mlx5_mac_addr_set(struct rte_eth_dev *dev, struct rte_ether_addr *mac_addr); 699 int mlx5_set_mc_addr_list(struct rte_eth_dev *dev, 700 struct rte_ether_addr *mc_addr_set, 701 uint32_t nb_mc_addr); 702 703 /* mlx5_rss.c */ 704 705 int mlx5_rss_hash_update(struct rte_eth_dev *dev, 706 struct rte_eth_rss_conf *rss_conf); 707 int mlx5_rss_hash_conf_get(struct rte_eth_dev *dev, 708 struct rte_eth_rss_conf *rss_conf); 709 int mlx5_rss_reta_index_resize(struct rte_eth_dev *dev, unsigned int reta_size); 710 int mlx5_dev_rss_reta_query(struct rte_eth_dev *dev, 711 struct rte_eth_rss_reta_entry64 *reta_conf, 712 uint16_t reta_size); 713 int mlx5_dev_rss_reta_update(struct rte_eth_dev *dev, 714 struct rte_eth_rss_reta_entry64 *reta_conf, 715 uint16_t reta_size); 716 717 /* mlx5_rxmode.c */ 718 719 int mlx5_promiscuous_enable(struct rte_eth_dev *dev); 720 int mlx5_promiscuous_disable(struct rte_eth_dev *dev); 721 int mlx5_allmulticast_enable(struct rte_eth_dev *dev); 722 int mlx5_allmulticast_disable(struct rte_eth_dev *dev); 723 724 /* mlx5_stats.c */ 725 726 void mlx5_stats_init(struct rte_eth_dev *dev); 727 int mlx5_stats_get(struct rte_eth_dev *dev, struct rte_eth_stats *stats); 728 int mlx5_stats_reset(struct rte_eth_dev *dev); 729 int mlx5_xstats_get(struct rte_eth_dev *dev, struct rte_eth_xstat *stats, 730 unsigned int n); 731 int mlx5_xstats_reset(struct rte_eth_dev *dev); 732 int mlx5_xstats_get_names(struct rte_eth_dev *dev __rte_unused, 733 struct rte_eth_xstat_name *xstats_names, 734 unsigned int n); 735 736 /* mlx5_vlan.c */ 737 738 int mlx5_vlan_filter_set(struct rte_eth_dev *dev, uint16_t vlan_id, int on); 739 void mlx5_vlan_strip_queue_set(struct rte_eth_dev *dev, uint16_t queue, int on); 740 int mlx5_vlan_offload_set(struct rte_eth_dev *dev, int mask); 741 void mlx5_vlan_vmwa_exit(struct mlx5_nl_vlan_vmwa_context *ctx); 742 void mlx5_vlan_vmwa_release(struct rte_eth_dev *dev, 743 struct mlx5_vf_vlan *vf_vlan); 744 void mlx5_vlan_vmwa_acquire(struct rte_eth_dev *dev, 745 struct mlx5_vf_vlan *vf_vlan); 746 747 /* mlx5_trigger.c */ 748 749 int mlx5_dev_start(struct rte_eth_dev *dev); 750 void mlx5_dev_stop(struct rte_eth_dev *dev); 751 int mlx5_traffic_enable(struct rte_eth_dev *dev); 752 void mlx5_traffic_disable(struct rte_eth_dev *dev); 753 int mlx5_traffic_restart(struct rte_eth_dev *dev); 754 755 /* mlx5_flow.c */ 756 757 int mlx5_flow_discover_mreg_c(struct rte_eth_dev *eth_dev); 758 bool mlx5_flow_ext_mreg_supported(struct rte_eth_dev *dev); 759 int mlx5_flow_discover_priorities(struct rte_eth_dev *dev); 760 void mlx5_flow_print(struct rte_flow *flow); 761 int mlx5_flow_validate(struct rte_eth_dev *dev, 762 const struct rte_flow_attr *attr, 763 const struct rte_flow_item items[], 764 const struct rte_flow_action actions[], 765 struct rte_flow_error *error); 766 struct rte_flow *mlx5_flow_create(struct rte_eth_dev *dev, 767 const struct rte_flow_attr *attr, 768 const struct rte_flow_item items[], 769 const struct rte_flow_action actions[], 770 struct rte_flow_error *error); 771 int mlx5_flow_destroy(struct rte_eth_dev *dev, struct rte_flow *flow, 772 struct rte_flow_error *error); 773 void mlx5_flow_list_flush(struct rte_eth_dev *dev, uint32_t *list, bool active); 774 int mlx5_flow_flush(struct rte_eth_dev *dev, struct rte_flow_error *error); 775 int mlx5_flow_query(struct rte_eth_dev *dev, struct rte_flow *flow, 776 const struct rte_flow_action *action, void *data, 777 struct rte_flow_error *error); 778 int mlx5_flow_isolate(struct rte_eth_dev *dev, int enable, 779 struct rte_flow_error *error); 780 int mlx5_dev_filter_ctrl(struct rte_eth_dev *dev, 781 enum rte_filter_type filter_type, 782 enum rte_filter_op filter_op, 783 void *arg); 784 int mlx5_flow_start(struct rte_eth_dev *dev, uint32_t *list); 785 void mlx5_flow_stop(struct rte_eth_dev *dev, uint32_t *list); 786 int mlx5_flow_start_default(struct rte_eth_dev *dev); 787 void mlx5_flow_stop_default(struct rte_eth_dev *dev); 788 void mlx5_flow_alloc_intermediate(struct rte_eth_dev *dev); 789 void mlx5_flow_free_intermediate(struct rte_eth_dev *dev); 790 int mlx5_flow_verify(struct rte_eth_dev *dev); 791 int mlx5_ctrl_flow_source_queue(struct rte_eth_dev *dev, uint32_t queue); 792 int mlx5_ctrl_flow_vlan(struct rte_eth_dev *dev, 793 struct rte_flow_item_eth *eth_spec, 794 struct rte_flow_item_eth *eth_mask, 795 struct rte_flow_item_vlan *vlan_spec, 796 struct rte_flow_item_vlan *vlan_mask); 797 int mlx5_ctrl_flow(struct rte_eth_dev *dev, 798 struct rte_flow_item_eth *eth_spec, 799 struct rte_flow_item_eth *eth_mask); 800 struct rte_flow *mlx5_flow_create_esw_table_zero_flow(struct rte_eth_dev *dev); 801 int mlx5_flow_create_drop_queue(struct rte_eth_dev *dev); 802 void mlx5_flow_delete_drop_queue(struct rte_eth_dev *dev); 803 void mlx5_flow_async_pool_query_handle(struct mlx5_ibv_shared *sh, 804 uint64_t async_id, int status); 805 void mlx5_set_query_alarm(struct mlx5_ibv_shared *sh); 806 void mlx5_flow_query_alarm(void *arg); 807 uint32_t mlx5_counter_alloc(struct rte_eth_dev *dev); 808 void mlx5_counter_free(struct rte_eth_dev *dev, uint32_t cnt); 809 int mlx5_counter_query(struct rte_eth_dev *dev, uint32_t cnt, 810 bool clear, uint64_t *pkts, uint64_t *bytes); 811 int mlx5_flow_dev_dump(struct rte_eth_dev *dev, FILE *file, 812 struct rte_flow_error *error); 813 void mlx5_flow_rxq_dynf_metadata_set(struct rte_eth_dev *dev); 814 int mlx5_flow_get_aged_flows(struct rte_eth_dev *dev, void **contexts, 815 uint32_t nb_contexts, struct rte_flow_error *error); 816 817 /* mlx5_mp.c */ 818 int mlx5_mp_primary_handle(const struct rte_mp_msg *mp_msg, const void *peer); 819 int mlx5_mp_secondary_handle(const struct rte_mp_msg *mp_msg, const void *peer); 820 void mlx5_mp_req_start_rxtx(struct rte_eth_dev *dev); 821 void mlx5_mp_req_stop_rxtx(struct rte_eth_dev *dev); 822 823 /* mlx5_socket.c */ 824 825 int mlx5_pmd_socket_init(void); 826 827 /* mlx5_flow_meter.c */ 828 829 int mlx5_flow_meter_ops_get(struct rte_eth_dev *dev, void *arg); 830 struct mlx5_flow_meter *mlx5_flow_meter_find(struct mlx5_priv *priv, 831 uint32_t meter_id); 832 struct mlx5_flow_meter *mlx5_flow_meter_attach 833 (struct mlx5_priv *priv, 834 uint32_t meter_id, 835 const struct rte_flow_attr *attr, 836 struct rte_flow_error *error); 837 void mlx5_flow_meter_detach(struct mlx5_flow_meter *fm); 838 839 #endif /* RTE_PMD_MLX5_H_ */ 840