1 /* SPDX-License-Identifier: BSD-3-Clause 2 * Copyright 2015 6WIND S.A. 3 * Copyright 2015 Mellanox Technologies, Ltd 4 */ 5 6 #ifndef RTE_PMD_MLX5_H_ 7 #define RTE_PMD_MLX5_H_ 8 9 #include <stddef.h> 10 #include <stdbool.h> 11 #include <stdint.h> 12 #include <limits.h> 13 #include <sys/queue.h> 14 15 #include <rte_pci.h> 16 #include <rte_ether.h> 17 #include <ethdev_driver.h> 18 #include <rte_rwlock.h> 19 #include <rte_interrupts.h> 20 #include <rte_errno.h> 21 #include <rte_flow.h> 22 #include <rte_mtr.h> 23 24 #include <mlx5_glue.h> 25 #include <mlx5_devx_cmds.h> 26 #include <mlx5_prm.h> 27 #include <mlx5_common_mp.h> 28 #include <mlx5_common_mr.h> 29 #include <mlx5_common_devx.h> 30 #include <mlx5_common_defs.h> 31 32 #include "mlx5_defs.h" 33 #include "mlx5_utils.h" 34 #include "mlx5_os.h" 35 #include "mlx5_autoconf.h" 36 #include "rte_pmd_mlx5.h" 37 #if defined(HAVE_IBV_FLOW_DV_SUPPORT) || !defined(HAVE_INFINIBAND_VERBS_H) 38 #ifndef RTE_EXEC_ENV_WINDOWS 39 #define HAVE_MLX5_HWS_SUPPORT 1 40 #else 41 #define __be64 uint64_t 42 #endif 43 #include "hws/mlx5dr.h" 44 #endif 45 46 #define MLX5_SH(dev) (((struct mlx5_priv *)(dev)->data->dev_private)->sh) 47 48 #define MLX5_HW_INV_QUEUE UINT32_MAX 49 50 /* 51 * The default ipool threshold value indicates which per_core_cache 52 * value to set. 53 */ 54 #define MLX5_HW_IPOOL_SIZE_THRESHOLD (1 << 19) 55 /* The default min local cache size. */ 56 #define MLX5_HW_IPOOL_CACHE_MIN (1 << 9) 57 58 /* 59 * Number of modification commands. 60 * The maximal actions amount in FW is some constant, and it is 16 in the 61 * latest releases. In some old releases, it will be limited to 8. 62 * Since there is no interface to query the capacity, the maximal value should 63 * be used to allow PMD to create the flow. The validation will be done in the 64 * lower driver layer or FW. A failure will be returned if exceeds the maximal 65 * supported actions number on the root table. 66 * On non-root tables, there is no limitation, but 32 is enough right now. 67 */ 68 #define MLX5_MAX_MODIFY_NUM 32 69 #define MLX5_ROOT_TBL_MODIFY_NUM 16 70 71 /* Maximal number of flex items created on the port.*/ 72 #define MLX5_PORT_FLEX_ITEM_NUM 8 73 74 /* Maximal number of field/field parts to map into sample registers .*/ 75 #define MLX5_FLEX_ITEM_MAPPING_NUM 32 76 77 enum mlx5_ipool_index { 78 #if defined(HAVE_IBV_FLOW_DV_SUPPORT) || !defined(HAVE_INFINIBAND_VERBS_H) 79 MLX5_IPOOL_DECAP_ENCAP = 0, /* Pool for encap/decap resource. */ 80 MLX5_IPOOL_PUSH_VLAN, /* Pool for push vlan resource. */ 81 MLX5_IPOOL_TAG, /* Pool for tag resource. */ 82 MLX5_IPOOL_PORT_ID, /* Pool for port id resource. */ 83 MLX5_IPOOL_JUMP, /* Pool for SWS jump resource. */ 84 /* Pool for HWS group. Jump action will be created internally. */ 85 MLX5_IPOOL_HW_GRP = MLX5_IPOOL_JUMP, 86 MLX5_IPOOL_SAMPLE, /* Pool for sample resource. */ 87 MLX5_IPOOL_DEST_ARRAY, /* Pool for destination array resource. */ 88 MLX5_IPOOL_TUNNEL_ID, /* Pool for tunnel offload context */ 89 MLX5_IPOOL_TNL_TBL_ID, /* Pool for tunnel table ID. */ 90 #endif 91 MLX5_IPOOL_MTR, /* Pool for meter resource. */ 92 MLX5_IPOOL_MCP, /* Pool for metadata resource. */ 93 MLX5_IPOOL_HRXQ, /* Pool for hrxq resource. */ 94 MLX5_IPOOL_MLX5_FLOW, /* Pool for mlx5 flow handle. */ 95 MLX5_IPOOL_RTE_FLOW, /* Pool for rte_flow. */ 96 MLX5_IPOOL_RSS_EXPANTION_FLOW_ID, /* Pool for Queue/RSS flow ID. */ 97 MLX5_IPOOL_RSS_SHARED_ACTIONS, /* Pool for RSS shared actions. */ 98 MLX5_IPOOL_MTR_POLICY, /* Pool for meter policy resource. */ 99 MLX5_IPOOL_MAX, 100 }; 101 102 /* 103 * There are three reclaim memory mode supported. 104 * 0(none) means no memory reclaim. 105 * 1(light) means only PMD level reclaim. 106 * 2(aggressive) means both PMD and rdma-core level reclaim. 107 */ 108 enum mlx5_reclaim_mem_mode { 109 MLX5_RCM_NONE, /* Don't reclaim memory. */ 110 MLX5_RCM_LIGHT, /* Reclaim PMD level. */ 111 MLX5_RCM_AGGR, /* Reclaim PMD and rdma-core level. */ 112 }; 113 114 /* The type of flow. */ 115 enum mlx5_flow_type { 116 MLX5_FLOW_TYPE_CTL, /* Control flow. */ 117 MLX5_FLOW_TYPE_GEN, /* General flow. */ 118 MLX5_FLOW_TYPE_MCP, /* MCP flow. */ 119 MLX5_FLOW_TYPE_MAXI, 120 }; 121 122 /* The mode of delay drop for Rx queues. */ 123 enum mlx5_delay_drop_mode { 124 MLX5_DELAY_DROP_NONE = 0, /* All disabled. */ 125 MLX5_DELAY_DROP_STANDARD = RTE_BIT32(0), /* Standard queues enable. */ 126 MLX5_DELAY_DROP_HAIRPIN = RTE_BIT32(1), /* Hairpin queues enable. */ 127 }; 128 129 /* The HWS action type root/non-root. */ 130 enum mlx5_hw_action_flag_type { 131 MLX5_HW_ACTION_FLAG_ROOT, /* Root action. */ 132 MLX5_HW_ACTION_FLAG_NONE_ROOT, /* Non-root ation. */ 133 MLX5_HW_ACTION_FLAG_MAX, /* Maximum action flag. */ 134 }; 135 136 /* Hlist and list callback context. */ 137 struct mlx5_flow_cb_ctx { 138 struct rte_eth_dev *dev; 139 struct rte_flow_error *error; 140 void *data; 141 void *data2; 142 }; 143 144 struct flow_hw_port_info { 145 uint32_t regc_mask; 146 uint32_t regc_value; 147 uint32_t is_wire:1; 148 uint32_t direction:2; 149 }; 150 151 enum mlx5_vport_direction { 152 MLX5_VPORT_DIRECTION_ANY = 0, 153 MLX5_VPORT_DIRECTION_NORTH, 154 MLX5_VPORT_DIRECTION_SOUTH, 155 }; 156 157 /* Device capabilities structure which isn't changed in any stage. */ 158 struct mlx5_dev_cap { 159 int max_cq; /* Maximum number of supported CQs */ 160 int max_qp; /* Maximum number of supported QPs. */ 161 int max_qp_wr; /* Maximum number of outstanding WR on any WQ. */ 162 int max_sge; 163 /* Maximum number of s/g per WR for SQ & RQ of QP for non RDMA Read 164 * operations. 165 */ 166 int mps; /* Multi-packet send supported mode. */ 167 uint32_t vf:1; /* This is a VF. */ 168 uint32_t sf:1; /* This is a SF. */ 169 uint32_t txpp_en:1; /* Tx packet pacing is supported. */ 170 uint32_t mpls_en:1; /* MPLS over GRE/UDP is supported. */ 171 uint32_t cqe_comp:1; /* CQE compression is supported. */ 172 uint32_t hw_csum:1; /* Checksum offload is supported. */ 173 uint32_t hw_padding:1; /* End alignment padding is supported. */ 174 uint32_t dest_tir:1; /* Whether advanced DR API is available. */ 175 uint32_t dv_esw_en:1; /* E-Switch DV flow is supported. */ 176 uint32_t dv_flow_en:1; /* DV flow is supported. */ 177 uint32_t swp:3; /* Tx generic tunnel checksum and TSO offload. */ 178 uint32_t hw_vlan_strip:1; /* VLAN stripping is supported. */ 179 uint32_t scatter_fcs_w_decap_disable:1; 180 /* HW has bug working with tunnel packet decap and scatter FCS. */ 181 uint32_t hw_fcs_strip:1; /* FCS stripping is supported. */ 182 uint32_t rt_timestamp:1; /* Realtime timestamp format. */ 183 uint32_t rq_delay_drop_en:1; /* Enable RxQ delay drop. */ 184 uint32_t tunnel_en:3; 185 /* Whether tunnel stateless offloads are supported. */ 186 uint32_t ind_table_max_size; 187 /* Maximum receive WQ indirection table size. */ 188 uint32_t tso:1; /* Whether TSO is supported. */ 189 uint32_t tso_max_payload_sz; /* Maximum TCP payload for TSO. */ 190 struct { 191 uint32_t enabled:1; /* Whether MPRQ is enabled. */ 192 uint32_t log_min_stride_size; /* Log min size of a stride. */ 193 uint32_t log_max_stride_size; /* Log max size of a stride. */ 194 uint32_t log_min_stride_num; /* Log min num of strides. */ 195 uint32_t log_max_stride_num; /* Log max num of strides. */ 196 uint32_t log_min_stride_wqe_size; 197 /* Log min WQE size, (size of single stride)*(num of strides).*/ 198 } mprq; /* Capability for Multi-Packet RQ. */ 199 char fw_ver[64]; /* Firmware version of this device. */ 200 struct flow_hw_port_info esw_info; /* E-switch manager reg_c0. */ 201 }; 202 203 #define MLX5_MPESW_PORT_INVALID (-1) 204 205 /** Data associated with devices to spawn. */ 206 struct mlx5_dev_spawn_data { 207 uint32_t ifindex; /**< Network interface index. */ 208 uint32_t max_port; /**< Device maximal port index. */ 209 uint32_t phys_port; /**< Device physical port index. */ 210 int pf_bond; /**< bonding device PF index. < 0 - no bonding */ 211 int mpesw_port; /**< MPESW uplink index. Valid if mpesw_owner_port >= 0. */ 212 struct mlx5_switch_info info; /**< Switch information. */ 213 const char *phys_dev_name; /**< Name of physical device. */ 214 struct rte_eth_dev *eth_dev; /**< Associated Ethernet device. */ 215 struct rte_pci_device *pci_dev; /**< Backend PCI device. */ 216 struct mlx5_common_device *cdev; /**< Backend common device. */ 217 struct mlx5_bond_info *bond_info; 218 }; 219 220 /** 221 * Check if the port requested to be probed is MPESW physical device 222 * or a representor port. 223 * 224 * @param spawn 225 * Parameters of the probed port. 226 * 227 * @return 228 * True if the probed port is a physical device or representor in MPESW setup. 229 * False otherwise or MPESW was not configured. 230 */ 231 static inline bool 232 mlx5_is_probed_port_on_mpesw_device(struct mlx5_dev_spawn_data *spawn) 233 { 234 return spawn->mpesw_port >= 0; 235 } 236 237 /** Data associated with socket messages. */ 238 struct __rte_packed_begin mlx5_flow_dump_req { 239 uint32_t port_id; /**< There are plans in DPDK to extend port_id. */ 240 uint64_t flow_id; 241 } __rte_packed_end; 242 243 struct mlx5_flow_dump_ack { 244 int rc; /**< Return code. */ 245 }; 246 247 LIST_HEAD(mlx5_dev_list, mlx5_dev_ctx_shared); 248 249 /* Shared data between primary and secondary processes. */ 250 struct mlx5_shared_data { 251 rte_spinlock_t lock; 252 /* Global spinlock for primary and secondary processes. */ 253 int init_done; /* Whether primary has done initialization. */ 254 unsigned int secondary_cnt; /* Number of secondary processes init'd. */ 255 }; 256 257 /* Per-process data structure, not visible to other processes. */ 258 struct mlx5_local_data { 259 int init_done; /* Whether a secondary has done initialization. */ 260 }; 261 262 extern struct mlx5_shared_data *mlx5_shared_data; 263 264 /* Dev ops structs */ 265 extern const struct eth_dev_ops mlx5_dev_ops; 266 extern const struct eth_dev_ops mlx5_dev_sec_ops; 267 extern const struct eth_dev_ops mlx5_dev_ops_isolate; 268 269 struct mlx5_counter_ctrl { 270 /* Name of the counter. */ 271 char dpdk_name[RTE_ETH_XSTATS_NAME_SIZE]; 272 /* Name of the counter on the device table. */ 273 char ctr_name[RTE_ETH_XSTATS_NAME_SIZE]; 274 uint32_t dev:1; /**< Nonzero for dev counters. */ 275 }; 276 277 struct mlx5_xstats_ctrl { 278 /* Number of device stats. */ 279 uint16_t stats_n; 280 /* Number of device stats, for the 2nd port in bond. */ 281 uint16_t stats_n_2nd; 282 /* Number of device stats identified by PMD. */ 283 uint16_t mlx5_stats_n; 284 /* First device counters index. */ 285 uint16_t dev_cnt_start; 286 /* Index in the device counters table. */ 287 uint16_t dev_table_idx[MLX5_MAX_XSTATS]; 288 /* Index in the output table. */ 289 uint16_t xstats_o_idx[MLX5_MAX_XSTATS]; 290 uint64_t base[MLX5_MAX_XSTATS]; 291 uint64_t xstats[MLX5_MAX_XSTATS]; 292 uint64_t hw_stats[MLX5_MAX_XSTATS]; 293 struct mlx5_counter_ctrl info[MLX5_MAX_XSTATS]; 294 /* Index in the device counters table, for the 2nd port in bond. */ 295 uint16_t dev_table_idx_2nd[MLX5_MAX_XSTATS]; 296 /* Index in the output table, for the 2nd port in bond. */ 297 uint16_t xstats_o_idx_2nd[MLX5_MAX_XSTATS]; 298 }; 299 300 /* xstats array size. */ 301 extern const unsigned int xstats_n; 302 303 struct mlx5_stats_ctrl { 304 /* Base for imissed counter. */ 305 uint64_t imissed_base; 306 uint64_t imissed; 307 }; 308 309 /* Maximal size of coalesced segment for LRO is set in chunks of 256 Bytes. */ 310 #define MLX5_LRO_SEG_CHUNK_SIZE 256u 311 312 /* Maximal size of aggregated LRO packet. */ 313 #define MLX5_MAX_LRO_SIZE (UINT8_MAX * MLX5_LRO_SEG_CHUNK_SIZE) 314 315 /* Maximal number of segments to split. */ 316 #define MLX5_MAX_RXQ_NSEG (1u << MLX5_MAX_LOG_RQ_SEGS) 317 318 /* 319 * Port configuration structure. 320 * User device parameters disabled features. 321 * This structure contains all configurations coming from devargs which 322 * oriented to port. When probing again, devargs doesn't have to be compatible 323 * with primary devargs. It is updated for each port in spawn function. 324 */ 325 struct mlx5_port_config { 326 unsigned int hw_vlan_insert:1; /* VLAN insertion in WQE is supported. */ 327 unsigned int hw_padding:1; /* End alignment padding is supported. */ 328 unsigned int cqe_comp:1; /* CQE compression is enabled. */ 329 unsigned int enh_cqe_comp:1; /* Enhanced CQE compression is enabled. */ 330 unsigned int cqe_comp_fmt:3; /* CQE compression format. */ 331 unsigned int rx_vec_en:1; /* Rx vector is enabled. */ 332 unsigned int std_delay_drop:1; /* Enable standard Rxq delay drop. */ 333 unsigned int hp_delay_drop:1; /* Enable hairpin Rxq delay drop. */ 334 struct { 335 unsigned int enabled:1; /* Whether MPRQ is enabled. */ 336 unsigned int log_stride_num; /* Log number of strides. */ 337 unsigned int log_stride_size; /* Log size of a stride. */ 338 unsigned int max_memcpy_len; 339 /* Maximum packet size to memcpy Rx packets. */ 340 unsigned int min_rxqs_num; 341 /* Rx queue count threshold to enable MPRQ. */ 342 } mprq; /* Configurations for Multi-Packet RQ. */ 343 int mps; /* Multi-packet send supported mode. */ 344 unsigned int max_dump_files_num; /* Maximum dump files per queue. */ 345 unsigned int log_hp_size; /* Single hairpin queue data size in total. */ 346 unsigned int lro_timeout; /* LRO user configuration. */ 347 int txqs_inline; /* Queue number threshold for inlining. */ 348 int txq_inline_min; /* Minimal amount of data bytes to inline. */ 349 int txq_inline_max; /* Max packet size for inlining with SEND. */ 350 int txq_inline_mpw; /* Max packet size for inlining with eMPW. */ 351 }; 352 353 /* 354 * Share context device configuration structure. 355 * User device parameters disabled features. 356 * This structure updated once for device in mlx5_alloc_shared_dev_ctx() 357 * function and cannot change even when probing again. 358 */ 359 struct mlx5_sh_config { 360 int tx_pp; /* Timestamp scheduling granularity in nanoseconds. */ 361 int tx_skew; /* Tx scheduling skew between WQE and data on wire. */ 362 uint32_t reclaim_mode:2; /* Memory reclaim mode. */ 363 uint32_t dv_esw_en:1; /* Enable E-Switch DV flow. */ 364 /* Enable DV flow. 1 means SW steering, 2 means HW steering. */ 365 uint32_t dv_flow_en:2; /* Enable DV flow. */ 366 uint32_t dv_xmeta_en:3; /* Enable extensive flow metadata. */ 367 uint32_t dv_miss_info:1; /* Restore packet after partial hw miss. */ 368 uint32_t l3_vxlan_en:1; /* Enable L3 VXLAN flow creation. */ 369 uint32_t vf_nl_en:1; /* Enable Netlink requests in VF mode. */ 370 uint32_t lacp_by_user:1; /* Enable user to manage LACP traffic. */ 371 uint32_t decap_en:1; /* Whether decap will be used or not. */ 372 uint32_t hw_fcs_strip:1; /* FCS stripping is supported. */ 373 uint32_t allow_duplicate_pattern:1; 374 uint32_t lro_allowed:1; /* Whether LRO is allowed. */ 375 struct { 376 uint16_t service_core; 377 uint32_t cycle_time; /* query cycle time in milli-second. */ 378 } cnt_svc; /* configure for HW steering's counter's service. */ 379 /* Allow/Prevent the duplicate rules pattern. */ 380 uint32_t fdb_def_rule:1; /* Create FDB default jump rule */ 381 uint32_t repr_matching:1; /* Enable implicit vport matching in HWS FDB. */ 382 }; 383 384 /* Structure for VF VLAN workaround. */ 385 struct mlx5_vf_vlan { 386 uint32_t tag:12; 387 uint32_t created:1; 388 }; 389 390 /* Flow drop context necessary due to Verbs API. */ 391 struct mlx5_drop { 392 struct mlx5_hrxq *hrxq; /* Hash Rx queue queue. */ 393 struct mlx5_rxq_priv *rxq; /* Rx queue. */ 394 }; 395 396 /* Loopback dummy queue resources required due to Verbs API. */ 397 struct mlx5_lb_ctx { 398 struct ibv_qp *qp; /* QP object. */ 399 void *ibv_cq; /* Completion queue. */ 400 RTE_ATOMIC(uint16_t) refcnt; /* Reference count for representors. */ 401 }; 402 403 /* External queue descriptor. */ 404 struct mlx5_external_q { 405 uint32_t hw_id; /* Queue index in the Hardware. */ 406 RTE_ATOMIC(uint32_t) refcnt; /* Reference counter. */ 407 }; 408 409 /* HW steering queue job descriptor type. */ 410 enum mlx5_hw_job_type { 411 MLX5_HW_Q_JOB_TYPE_CREATE, /* Flow create job type. */ 412 MLX5_HW_Q_JOB_TYPE_DESTROY, /* Flow destroy job type. */ 413 MLX5_HW_Q_JOB_TYPE_UPDATE, /* Flow update job type. */ 414 MLX5_HW_Q_JOB_TYPE_QUERY, /* Flow query job type. */ 415 MLX5_HW_Q_JOB_TYPE_UPDATE_QUERY, /* Flow update and query job type. */ 416 MLX5_HW_Q_JOB_TYPE_RSZTBL_FLOW_CREATE, /* Non-optimized flow create job type. */ 417 MLX5_HW_Q_JOB_TYPE_RSZTBL_FLOW_DESTROY, /* Non-optimized destroy create job type. */ 418 MLX5_HW_Q_JOB_TYPE_RSZTBL_FLOW_MOVE, /* Move flow after table resize. */ 419 }; 420 421 enum mlx5_hw_indirect_type { 422 MLX5_HW_INDIRECT_TYPE_LEGACY, 423 MLX5_HW_INDIRECT_TYPE_LIST 424 }; 425 426 #define MLX5_HW_MAX_ITEMS (16) 427 428 #define MLX5_MHDR_MAX_CMD ((MLX5_MAX_MODIFY_NUM) * 2 + 1) 429 #define MLX5_PUSH_MAX_LEN 128 430 #define MLX5_ENCAP_MAX_LEN 132 431 432 /** Container for flow action data constructed during flow rule creation. */ 433 struct mlx5_flow_hw_action_params { 434 /** Array of constructed modify header commands. */ 435 struct mlx5_modification_cmd mhdr_cmd[MLX5_MHDR_MAX_CMD]; 436 /** Constructed encap/decap data buffer. */ 437 uint8_t encap_data[MLX5_ENCAP_MAX_LEN]; 438 /** Constructed IPv6 routing data buffer. */ 439 uint8_t ipv6_push_data[MLX5_PUSH_MAX_LEN]; 440 }; 441 442 /** Container for dynamically generated flow items used during flow rule creation. */ 443 struct mlx5_flow_hw_pattern_params { 444 /** Array of dynamically generated flow items. */ 445 struct rte_flow_item items[MLX5_HW_MAX_ITEMS]; 446 /** Temporary REPRESENTED_PORT item generated by PMD. */ 447 struct rte_flow_item_ethdev port_spec; 448 /** Temporary TAG item generated by PMD. */ 449 struct rte_flow_item_tag tag_spec; 450 }; 451 452 /* HW steering flow management job descriptor. */ 453 struct mlx5_hw_q_job { 454 uint32_t type; /* Job type. */ 455 uint32_t indirect_type; 456 const void *action; /* Indirect action attached to the job. */ 457 void *user_data; /* Job user data. */ 458 struct { 459 /* User memory for query output */ 460 void *user; 461 /* Data extracted from hardware */ 462 void *hw; 463 } query; 464 }; 465 466 /* HW steering job descriptor LIFO pool. */ 467 struct __rte_cache_aligned mlx5_hw_q { 468 uint32_t job_idx; /* Free job index. */ 469 uint32_t size; /* Job LIFO queue size. */ 470 uint32_t ongoing_flow_ops; /* Number of ongoing flow operations. */ 471 struct mlx5_hw_q_job **job; /* LIFO header. */ 472 struct rte_ring *indir_cq; /* Indirect action SW completion queue. */ 473 struct rte_ring *indir_iq; /* Indirect action SW in progress queue. */ 474 struct rte_ring *flow_transfer_pending; 475 struct rte_ring *flow_transfer_completed; 476 /* Action's ARGUMENT resource buffer for rule creation. */ 477 struct mlx5_flow_hw_action_params ap; 478 /* Holds spec value for any implicitly added item. */ 479 struct mlx5_flow_hw_pattern_params pp; 480 }; 481 482 483 #define MLX5_COUNTER_POOLS_MAX_NUM (1 << 15) 484 #define MLX5_COUNTERS_PER_POOL 512 485 #define MLX5_MAX_PENDING_QUERIES 4 486 #define MLX5_CNT_MR_ALLOC_BULK 64 487 #define MLX5_CNT_SHARED_OFFSET 0x80000000 488 #define IS_BATCH_CNT(cnt) (((cnt) & (MLX5_CNT_SHARED_OFFSET - 1)) >= \ 489 MLX5_CNT_BATCH_OFFSET) 490 #define MLX5_CNT_SIZE (sizeof(struct mlx5_flow_counter)) 491 #define MLX5_AGE_SIZE (sizeof(struct mlx5_age_param)) 492 493 #define MLX5_CNT_LEN(pool) \ 494 (MLX5_CNT_SIZE + \ 495 ((pool)->is_aged ? MLX5_AGE_SIZE : 0)) 496 #define MLX5_POOL_GET_CNT(pool, index) \ 497 ((struct mlx5_flow_counter *) \ 498 ((uint8_t *)((pool) + 1) + (index) * (MLX5_CNT_LEN(pool)))) 499 #define MLX5_CNT_ARRAY_IDX(pool, cnt) \ 500 ((int)(((uint8_t *)(cnt) - (uint8_t *)((pool) + 1)) / \ 501 MLX5_CNT_LEN(pool))) 502 #define MLX5_TS_MASK_SECS 8ull 503 /* timestamp wrapping in seconds, must be power of 2. */ 504 505 /* 506 * The pool index and offset of counter in the pool array makes up the 507 * counter index. In case the counter is from pool 0 and offset 0, it 508 * should plus 1 to avoid index 0, since 0 means invalid counter index 509 * currently. 510 */ 511 #define MLX5_MAKE_CNT_IDX(pi, offset) \ 512 ((pi) * MLX5_COUNTERS_PER_POOL + (offset) + 1) 513 #define MLX5_CNT_TO_AGE(cnt) \ 514 ((struct mlx5_age_param *)((cnt) + 1)) 515 /* 516 * The maximum single counter is 0x800000 as MLX5_CNT_BATCH_OFFSET 517 * defines. The pool size is 512, pool index should never reach 518 * INT16_MAX. 519 */ 520 #define POOL_IDX_INVALID UINT16_MAX 521 522 /* Age status. */ 523 enum { 524 AGE_FREE, /* Initialized state. */ 525 AGE_CANDIDATE, /* Counter assigned to flows. */ 526 AGE_TMOUT, /* Timeout, wait for rte_flow_get_aged_flows and destroy. */ 527 }; 528 529 enum mlx5_counter_type { 530 MLX5_COUNTER_TYPE_ORIGIN, 531 MLX5_COUNTER_TYPE_AGE, 532 MLX5_COUNTER_TYPE_MAX, 533 }; 534 535 /* Counter age parameter. */ 536 struct mlx5_age_param { 537 RTE_ATOMIC(uint16_t) state; /**< Age state (atomically accessed). */ 538 uint16_t port_id; /**< Port id of the counter. */ 539 uint32_t timeout:24; /**< Aging timeout in seconds. */ 540 RTE_ATOMIC(uint32_t) sec_since_last_hit; 541 /**< Time in seconds since last hit (atomically accessed). */ 542 void *context; /**< Flow counter age context. */ 543 }; 544 545 struct flow_counter_stats { 546 uint64_t hits; 547 uint64_t bytes; 548 }; 549 550 /* Shared counters information for counters. */ 551 struct mlx5_flow_counter_shared { 552 union { 553 RTE_ATOMIC(uint32_t) refcnt; /* Only for shared action management. */ 554 uint32_t id; /* User counter ID for legacy sharing. */ 555 }; 556 }; 557 558 struct mlx5_flow_counter_pool; 559 /* Generic counters information. */ 560 struct mlx5_flow_counter { 561 union { 562 /* 563 * User-defined counter shared info is only used during 564 * counter active time. And aging counter sharing is not 565 * supported, so active shared counter will not be chained 566 * to the aging list. For shared counter, only when it is 567 * released, the TAILQ entry memory will be used, at that 568 * time, shared memory is not used anymore. 569 * 570 * Similarly to none-batch counter dcs, since it doesn't 571 * support aging, while counter is allocated, the entry 572 * memory is not used anymore. In this case, as bytes 573 * memory is used only when counter is allocated, and 574 * entry memory is used only when counter is free. The 575 * dcs pointer can be saved to these two different place 576 * at different stage. It will eliminate the individual 577 * counter extend struct. 578 */ 579 TAILQ_ENTRY(mlx5_flow_counter) next; 580 /**< Pointer to the next flow counter structure. */ 581 struct { 582 struct mlx5_flow_counter_shared shared_info; 583 /**< Shared counter information. */ 584 void *dcs_when_active; 585 /* 586 * For non-batch mode, the dcs will be saved 587 * here when the counter is free. 588 */ 589 }; 590 }; 591 union { 592 uint64_t hits; /**< Reset value of hits packets. */ 593 struct mlx5_flow_counter_pool *pool; /**< Counter pool. */ 594 }; 595 union { 596 uint64_t bytes; /**< Reset value of bytes. */ 597 void *dcs_when_free; 598 /* 599 * For non-batch mode, the dcs will be saved here 600 * when the counter is free. 601 */ 602 }; 603 void *action; /**< Pointer to the dv action. */ 604 }; 605 606 TAILQ_HEAD(mlx5_counters, mlx5_flow_counter); 607 608 /* Generic counter pool structure - query is in pool resolution. */ 609 struct mlx5_flow_counter_pool { 610 TAILQ_ENTRY(mlx5_flow_counter_pool) next; 611 struct mlx5_counters counters[2]; /* Free counter list. */ 612 struct mlx5_devx_obj *min_dcs; 613 /* The devx object of the minimum counter ID. */ 614 uint64_t time_of_last_age_check; 615 /* System time (from rte_rdtsc()) read in the last aging check. */ 616 uint32_t index:30; /* Pool index in container. */ 617 uint32_t is_aged:1; /* Pool with aging counter. */ 618 volatile uint32_t query_gen:1; /* Query round. */ 619 rte_spinlock_t sl; /* The pool lock. */ 620 rte_spinlock_t csl; /* The pool counter free list lock. */ 621 struct mlx5_counter_stats_raw *raw; 622 struct mlx5_counter_stats_raw *raw_hw; 623 /* The raw on HW working. */ 624 }; 625 626 /* Memory management structure for group of counter statistics raws. */ 627 struct mlx5_counter_stats_mem_mng { 628 LIST_ENTRY(mlx5_counter_stats_mem_mng) next; 629 struct mlx5_counter_stats_raw *raws; 630 struct mlx5_pmd_wrapped_mr wm; 631 }; 632 633 /* Raw memory structure for the counter statistics values of a pool. */ 634 struct mlx5_counter_stats_raw { 635 LIST_ENTRY(mlx5_counter_stats_raw) next; 636 struct mlx5_counter_stats_mem_mng *mem_mng; 637 volatile struct flow_counter_stats *data; 638 }; 639 640 TAILQ_HEAD(mlx5_counter_pools, mlx5_flow_counter_pool); 641 642 /* Counter global management structure. */ 643 struct mlx5_flow_counter_mng { 644 volatile RTE_ATOMIC(uint16_t) n_valid; /* Number of valid pools. */ 645 uint16_t last_pool_idx; /* Last used pool index */ 646 int min_id; /* The minimum counter ID in the pools. */ 647 int max_id; /* The maximum counter ID in the pools. */ 648 rte_spinlock_t pool_update_sl; /* The pool update lock. */ 649 rte_spinlock_t csl[MLX5_COUNTER_TYPE_MAX]; 650 /* The counter free list lock. */ 651 struct mlx5_counters counters[MLX5_COUNTER_TYPE_MAX]; 652 /* Free counter list. */ 653 struct mlx5_flow_counter_pool **pools; /* Counter pool array. */ 654 struct mlx5_counter_stats_mem_mng *mem_mng; 655 /* Hold the memory management for the next allocated pools raws. */ 656 struct mlx5_counters flow_counters; /* Legacy flow counter list. */ 657 uint8_t pending_queries; 658 uint16_t pool_index; 659 uint8_t query_thread_on; 660 bool counter_fallback; /* Use counter fallback management. */ 661 LIST_HEAD(mem_mngs, mlx5_counter_stats_mem_mng) mem_mngs; 662 LIST_HEAD(stat_raws, mlx5_counter_stats_raw) free_stat_raws; 663 }; 664 665 /* ASO structures. */ 666 #define MLX5_ASO_QUEUE_LOG_DESC 10 667 668 struct mlx5_aso_cq { 669 uint16_t log_desc_n; 670 uint32_t cq_ci:24; 671 struct mlx5_devx_cq cq_obj; 672 uint64_t errors; 673 }; 674 675 struct mlx5_aso_sq_elem { 676 union { 677 struct { 678 struct mlx5_aso_age_pool *pool; 679 uint16_t burst_size; 680 }; 681 struct mlx5_aso_mtr *mtr; 682 struct { 683 struct mlx5_aso_ct_action *ct; 684 char *query_data; 685 }; 686 void *user_data; 687 struct mlx5_quota *quota_obj; 688 }; 689 }; 690 691 struct mlx5_aso_sq { 692 uint16_t log_desc_n; 693 rte_spinlock_t sqsl; 694 struct mlx5_aso_cq cq; 695 struct mlx5_devx_sq sq_obj; 696 struct mlx5_pmd_mr mr; 697 volatile struct mlx5_aso_wqe *db; 698 uint16_t pi; 699 uint16_t db_pi; 700 uint32_t head; 701 uint32_t tail; 702 uint32_t sqn; 703 struct mlx5_aso_sq_elem elts[1 << MLX5_ASO_QUEUE_LOG_DESC]; 704 uint16_t next; /* Pool index of the next pool to query. */ 705 }; 706 707 struct mlx5_aso_age_action { 708 LIST_ENTRY(mlx5_aso_age_action) next; 709 void *dr_action; 710 RTE_ATOMIC(uint32_t) refcnt; 711 /* Following fields relevant only when action is active. */ 712 uint16_t offset; /* Offset of ASO Flow Hit flag in DevX object. */ 713 struct mlx5_age_param age_params; 714 }; 715 716 #define MLX5_ASO_AGE_ACTIONS_PER_POOL 512 717 #define MLX5_ASO_AGE_CONTAINER_RESIZE 64 718 719 struct mlx5_aso_age_pool { 720 struct mlx5_devx_obj *flow_hit_aso_obj; 721 uint16_t index; /* Pool index in pools array. */ 722 uint64_t time_of_last_age_check; /* In seconds. */ 723 struct mlx5_aso_age_action actions[MLX5_ASO_AGE_ACTIONS_PER_POOL]; 724 }; 725 726 LIST_HEAD(aso_age_list, mlx5_aso_age_action); 727 728 struct mlx5_aso_age_mng { 729 struct mlx5_aso_age_pool **pools; 730 uint16_t n; /* Total number of pools. */ 731 uint16_t next; /* Number of pools in use, index of next free pool. */ 732 rte_rwlock_t resize_rwl; /* Lock for resize objects. */ 733 rte_spinlock_t free_sl; /* Lock for free list access. */ 734 struct aso_age_list free; /* Free age actions list - ready to use. */ 735 struct mlx5_aso_sq aso_sq; /* ASO queue objects. */ 736 }; 737 738 /* Management structure for geneve tlv option */ 739 struct mlx5_geneve_tlv_option_resource { 740 struct mlx5_devx_obj *obj; /* Pointer to the geneve tlv opt object. */ 741 rte_be16_t option_class; /* geneve tlv opt class.*/ 742 uint8_t option_type; /* geneve tlv opt type.*/ 743 uint8_t length; /* geneve tlv opt length. */ 744 RTE_ATOMIC(uint32_t) refcnt; /* geneve tlv object reference counter */ 745 }; 746 747 748 #define MLX5_AGE_EVENT_NEW 1 749 #define MLX5_AGE_TRIGGER 2 750 #define MLX5_AGE_SET(age_info, BIT) \ 751 ((age_info)->flags |= (1 << (BIT))) 752 #define MLX5_AGE_UNSET(age_info, BIT) \ 753 ((age_info)->flags &= ~(1 << (BIT))) 754 #define MLX5_AGE_GET(age_info, BIT) \ 755 ((age_info)->flags & (1 << (BIT))) 756 #define GET_PORT_AGE_INFO(priv) \ 757 (&((priv)->sh->port[(priv)->dev_port - 1].age_info)) 758 /* Current time in seconds. */ 759 #define MLX5_CURR_TIME_SEC (rte_rdtsc() / rte_get_tsc_hz()) 760 761 /* 762 * HW steering queue oriented AGE info. 763 * It contains an array of rings, one for each HWS queue. 764 */ 765 struct mlx5_hws_q_age_info { 766 uint16_t nb_rings; /* Number of aged-out ring lists. */ 767 struct rte_ring *aged_lists[]; /* Aged-out lists. */ 768 }; 769 770 /* 771 * HW steering AGE info. 772 * It has a ring list containing all aged out flow rules. 773 */ 774 struct mlx5_hws_age_info { 775 struct rte_ring *aged_list; /* Aged out lists. */ 776 }; 777 778 /* Aging information for per port. */ 779 struct mlx5_age_info { 780 uint8_t flags; /* Indicate if is new event or need to be triggered. */ 781 union { 782 /* SW/FW steering AGE info. */ 783 struct { 784 struct mlx5_counters aged_counters; 785 /* Aged counter list. */ 786 struct aso_age_list aged_aso; 787 /* Aged ASO actions list. */ 788 rte_spinlock_t aged_sl; /* Aged flow list lock. */ 789 }; 790 struct { 791 struct mlx5_indexed_pool *ages_ipool; 792 union { 793 struct mlx5_hws_age_info hw_age; 794 /* HW steering AGE info. */ 795 struct mlx5_hws_q_age_info *hw_q_age; 796 /* HW steering queue oriented AGE info. */ 797 }; 798 }; 799 }; 800 }; 801 802 /* Per port data of shared IB device. */ 803 struct mlx5_dev_shared_port { 804 uint32_t ih_port_id; 805 uint32_t devx_ih_port_id; 806 uint32_t nl_ih_port_id; 807 /* 808 * Interrupt handler port_id. Used by shared interrupt 809 * handler to find the corresponding rte_eth device 810 * by IB port index. If value is equal or greater 811 * RTE_MAX_ETHPORTS it means there is no subhandler 812 * installed for specified IB port index. 813 */ 814 struct mlx5_age_info age_info; 815 /* Aging information for per port. */ 816 }; 817 818 /* 819 * Max number of actions per DV flow. 820 * See CREATE_FLOW_MAX_FLOW_ACTIONS_SUPPORTED 821 * in rdma-core file providers/mlx5/verbs.c. 822 */ 823 #define MLX5_DV_MAX_NUMBER_OF_ACTIONS 8 824 825 /* ASO flow meter structures */ 826 /* Modify this value if enum rte_mtr_color changes. */ 827 #define RTE_MTR_DROPPED RTE_COLORS 828 /* Yellow is now supported. */ 829 #define MLX5_MTR_RTE_COLORS (RTE_COLOR_YELLOW + 1) 830 /* table_id 22 bits in mlx5_flow_tbl_key so limit policy number. */ 831 #define MLX5_MAX_SUB_POLICY_TBL_NUM 0x3FFFFF 832 #define MLX5_INVALID_POLICY_ID UINT32_MAX 833 /* Suffix table_id on MLX5_FLOW_TABLE_LEVEL_METER. */ 834 #define MLX5_MTR_TABLE_ID_SUFFIX 1 835 /* Drop table_id on MLX5_FLOW_TABLE_LEVEL_METER. */ 836 #define MLX5_MTR_TABLE_ID_DROP 2 837 /* Priority of the meter policy matcher. */ 838 #define MLX5_MTR_POLICY_MATCHER_PRIO 0 839 /* Green & yellow color valid for now. */ 840 #define MLX5_MTR_POLICY_MODE_ALL 0 841 /* Default policy. */ 842 #define MLX5_MTR_POLICY_MODE_DEF 1 843 /* Only green color valid. */ 844 #define MLX5_MTR_POLICY_MODE_OG 2 845 /* Only yellow color valid. */ 846 #define MLX5_MTR_POLICY_MODE_OY 3 847 848 /* Max number of meters. */ 849 #define MLX5_MTR_MAX(priv) (mlx5_flow_mtr_max_get(priv)) 850 /* Max number of meters allocated in non template mode. */ 851 #define MLX5_MTR_NT_MAX(priv) (MLX5_MTR_MAX(priv) >> 1) 852 /* Max number of connection tracking. */ 853 #define MLX5_CT_MAX(priv) (1 << (priv)->sh->cdev->config.hca_attr.log_max_conn_track_offload) 854 /* Max number of connection tracking allocated in non template mode. */ 855 #define MLX5_CT_NT_MAX(priv) (MLX5_CT_MAX(priv) >> 1) 856 /* Max number of counters. */ 857 #define MLX5_CNT_MAX(priv) ((priv)->sh->hws_max_nb_counters) 858 /* Max number of counters allocated in non template mode. */ 859 #define MLX5_CNT_NT_MAX(priv) (MLX5_CNT_MAX(priv) >> 1) 860 861 enum mlx5_meter_domain { 862 MLX5_MTR_DOMAIN_INGRESS, 863 MLX5_MTR_DOMAIN_EGRESS, 864 MLX5_MTR_DOMAIN_TRANSFER, 865 MLX5_MTR_DOMAIN_MAX, 866 }; 867 #define MLX5_MTR_DOMAIN_INGRESS_BIT (1 << MLX5_MTR_DOMAIN_INGRESS) 868 #define MLX5_MTR_DOMAIN_EGRESS_BIT (1 << MLX5_MTR_DOMAIN_EGRESS) 869 #define MLX5_MTR_DOMAIN_TRANSFER_BIT (1 << MLX5_MTR_DOMAIN_TRANSFER) 870 #define MLX5_MTR_ALL_DOMAIN_BIT (MLX5_MTR_DOMAIN_INGRESS_BIT | \ 871 MLX5_MTR_DOMAIN_EGRESS_BIT | \ 872 MLX5_MTR_DOMAIN_TRANSFER_BIT) 873 874 /* The color tag rule structure. */ 875 struct mlx5_sub_policy_color_rule { 876 void *rule; 877 /* The color rule. */ 878 struct mlx5_flow_dv_matcher *matcher; 879 /* The color matcher. */ 880 TAILQ_ENTRY(mlx5_sub_policy_color_rule) next_port; 881 /**< Pointer to the next color rule structure. */ 882 int32_t src_port; 883 /* On which src port this rule applied. */ 884 }; 885 886 TAILQ_HEAD(mlx5_sub_policy_color_rules, mlx5_sub_policy_color_rule); 887 888 /* 889 * Meter sub-policy structure. 890 * Each RSS TIR in meter policy need its own sub-policy resource. 891 */ 892 struct mlx5_flow_meter_sub_policy { 893 uint32_t main_policy_id:1; 894 /* Main policy id is same as this sub_policy id. */ 895 uint32_t idx:31; 896 /* Index to sub_policy ipool entity. */ 897 void *main_policy; 898 /* Point to struct mlx5_flow_meter_policy. */ 899 struct mlx5_flow_tbl_resource *tbl_rsc; 900 /* The sub-policy table resource. */ 901 uint32_t rix_hrxq[MLX5_MTR_RTE_COLORS]; 902 /* Index to TIR resource. */ 903 struct mlx5_flow_tbl_resource *jump_tbl[MLX5_MTR_RTE_COLORS]; 904 /* Meter jump/drop table. */ 905 struct mlx5_sub_policy_color_rules color_rules[RTE_COLORS]; 906 /* List for the color rules. */ 907 }; 908 909 struct mlx5_meter_policy_acts { 910 uint8_t actions_n; 911 /* Number of actions. */ 912 void *dv_actions[MLX5_DV_MAX_NUMBER_OF_ACTIONS]; 913 /* Action list. */ 914 }; 915 916 struct mlx5_meter_policy_action_container { 917 uint32_t rix_mark; 918 /* Index to the mark action. */ 919 struct mlx5_flow_dv_modify_hdr_resource *modify_hdr; 920 /* Pointer to modify header resource in cache. */ 921 uint8_t fate_action; 922 /* Fate action type. */ 923 union { 924 struct rte_flow_action *rss; 925 /* Rss action configuration. */ 926 uint32_t rix_port_id_action; 927 /* Index to port ID action resource. */ 928 void *dr_jump_action[MLX5_MTR_DOMAIN_MAX]; 929 /* Jump/drop action per color. */ 930 uint16_t queue; 931 /* Queue action configuration. */ 932 struct { 933 uint32_t next_mtr_id; 934 /* The next meter id. */ 935 void *next_sub_policy; 936 /* Next meter's sub-policy. */ 937 }; 938 }; 939 }; 940 941 /* Flow meter policy parameter structure. */ 942 struct mlx5_flow_meter_policy { 943 uint32_t is_rss:1; 944 /* Is RSS policy table. */ 945 uint32_t ingress:1; 946 /* Rule applies to ingress domain. */ 947 uint32_t egress:1; 948 /* Rule applies to egress domain. */ 949 uint32_t transfer:1; 950 /* Rule applies to transfer domain. */ 951 uint32_t is_queue:1; 952 /* Is queue action in policy table. */ 953 uint32_t is_hierarchy:1; 954 /* Is meter action in policy table. */ 955 uint32_t match_port:1; 956 /* If policy flows match src port. */ 957 uint32_t hierarchy_match_port:1; 958 /* Is any meter in hierarchy contains policy flow that matches src port. */ 959 uint32_t skip_r:1; 960 /* If red color policy is skipped. */ 961 uint32_t skip_y:1; 962 /* If yellow color policy is skipped. */ 963 uint32_t skip_g:1; 964 /* If green color policy is skipped. */ 965 uint32_t mark:1; 966 /* If policy contains mark action. */ 967 uint32_t initialized:1; 968 /* Initialized. */ 969 uint16_t group; 970 /* The group. */ 971 rte_spinlock_t sl; 972 RTE_ATOMIC(uint32_t) ref_cnt; 973 /* Use count. */ 974 struct rte_flow_pattern_template *hws_item_templ; 975 /* Hardware steering item templates. */ 976 struct rte_flow_actions_template *hws_act_templ[MLX5_MTR_DOMAIN_MAX]; 977 /* Hardware steering action templates. */ 978 struct rte_flow_template_table *hws_flow_table[MLX5_MTR_DOMAIN_MAX]; 979 /* Hardware steering tables. */ 980 struct rte_flow *hws_flow_rule[MLX5_MTR_DOMAIN_MAX][RTE_COLORS]; 981 /* Hardware steering rules. */ 982 struct mlx5_meter_policy_action_container act_cnt[MLX5_MTR_RTE_COLORS]; 983 /* Policy actions container. */ 984 void *dr_drop_action[MLX5_MTR_DOMAIN_MAX]; 985 /* drop action for red color. */ 986 uint16_t sub_policy_num; 987 /* Count sub policy tables, 3 bits per domain. */ 988 struct mlx5_flow_meter_sub_policy **sub_policys[MLX5_MTR_DOMAIN_MAX]; 989 /* Sub policy table array must be the end of struct. */ 990 }; 991 992 /* The maximum sub policy is relate to struct mlx5_rss_hash_fields[]. */ 993 #define MLX5_MTR_RSS_MAX_SUB_POLICY 7 994 #define MLX5_MTR_SUB_POLICY_NUM_SHIFT 3 995 #define MLX5_MTR_SUB_POLICY_NUM_MASK 0x7 996 #define MLX5_MTRS_DEFAULT_RULE_PRIORITY 0xFFFF 997 #define MLX5_MTR_CHAIN_MAX_NUM 8 998 999 /* Flow meter default policy parameter structure. 1000 * Policy index 0 is reserved by default policy table. 1001 * Action per color as below: 1002 * green - do nothing, yellow - do nothing, red - drop 1003 */ 1004 struct mlx5_flow_meter_def_policy { 1005 struct mlx5_flow_meter_sub_policy sub_policy; 1006 /* Policy rules jump to other tables. */ 1007 void *dr_jump_action[RTE_COLORS]; 1008 /* Jump action per color. */ 1009 }; 1010 1011 /* Meter parameter structure. */ 1012 struct mlx5_flow_meter_info { 1013 uint32_t meter_id; 1014 /**< Meter id. */ 1015 uint32_t policy_id; 1016 /* Policy id, the first sub_policy idx. */ 1017 struct mlx5_flow_meter_profile *profile; 1018 /**< Meter profile parameters. */ 1019 rte_spinlock_t sl; /**< Meter action spinlock. */ 1020 /** Set of stats counters to be enabled. 1021 * @see enum rte_mtr_stats_type 1022 */ 1023 uint32_t bytes_dropped:1; 1024 /** Set bytes dropped stats to be enabled. */ 1025 uint32_t pkts_dropped:1; 1026 /** Set packets dropped stats to be enabled. */ 1027 uint32_t active_state:1; 1028 /**< Meter hw active state. */ 1029 uint32_t shared:1; 1030 /**< Meter shared or not. */ 1031 uint32_t is_enable:1; 1032 /**< Meter disable/enable state. */ 1033 uint32_t ingress:1; 1034 /**< Rule applies to egress traffic. */ 1035 uint32_t egress:1; 1036 /** 1037 * Instead of simply matching the properties of traffic as it would 1038 * appear on a given DPDK port ID, enabling this attribute transfers 1039 * a flow rule to the lowest possible level of any device endpoints 1040 * found in the pattern. 1041 * 1042 * When supported, this effectively enables an application to 1043 * re-route traffic not necessarily intended for it (e.g. coming 1044 * from or addressed to different physical ports, VFs or 1045 * applications) at the device level. 1046 * 1047 * It complements the behavior of some pattern items such as 1048 * RTE_FLOW_ITEM_TYPE_REPRESENTED_PORT and is meaningless without them. 1049 * 1050 * When transferring flow rules, ingress and egress attributes keep 1051 * their original meaning, as if processing traffic emitted or 1052 * received by the application. 1053 */ 1054 uint32_t transfer:1; 1055 uint32_t def_policy:1; 1056 uint32_t initialized:1; 1057 /* Meter points to default policy. */ 1058 uint32_t color_aware:1; 1059 /* Meter is color aware mode. */ 1060 void *drop_rule[MLX5_MTR_DOMAIN_MAX]; 1061 /* Meter drop rule in drop table. */ 1062 uint32_t drop_cnt; 1063 /**< Color counter for drop. */ 1064 uint32_t ref_cnt; 1065 /**< Use count. */ 1066 struct mlx5_indexed_pool *flow_ipool; 1067 /**< Index pool for flow id. */ 1068 void *meter_action_g; 1069 /**< Flow meter action. */ 1070 void *meter_action_y; 1071 /**< Flow meter action for yellow init_color. */ 1072 uint32_t meter_offset; 1073 /**< Flow meter offset. */ 1074 uint16_t group; 1075 /**< Flow meter group. */ 1076 }; 1077 1078 /* PPS(packets per second) map to BPS(Bytes per second). 1079 * HW treat packet as 128bytes in PPS mode 1080 */ 1081 #define MLX5_MTRS_PPS_MAP_BPS_SHIFT 7 1082 1083 /* RFC2697 parameter structure. */ 1084 struct mlx5_flow_meter_srtcm_rfc2697_prm { 1085 rte_be32_t cbs_cir; 1086 /* 1087 * bit 24-28: cbs_exponent, bit 16-23 cbs_mantissa, 1088 * bit 8-12: cir_exponent, bit 0-7 cir_mantissa. 1089 */ 1090 rte_be32_t ebs_eir; 1091 /* 1092 * bit 24-28: ebs_exponent, bit 16-23 ebs_mantissa, 1093 * bit 8-12: eir_exponent, bit 0-7 eir_mantissa. 1094 */ 1095 }; 1096 1097 /* Flow meter profile structure. */ 1098 struct mlx5_flow_meter_profile { 1099 TAILQ_ENTRY(mlx5_flow_meter_profile) next; 1100 /**< Pointer to the next flow meter structure. */ 1101 uint32_t id; /**< Profile id. */ 1102 struct rte_mtr_meter_profile profile; /**< Profile detail. */ 1103 union { 1104 struct mlx5_flow_meter_srtcm_rfc2697_prm srtcm_prm; 1105 /**< srtcm_rfc2697 struct. */ 1106 }; 1107 RTE_ATOMIC(uint32_t) ref_cnt; /**< Use count. */ 1108 uint32_t g_support:1; /**< If G color will be generated. */ 1109 uint32_t y_support:1; /**< If Y color will be generated. */ 1110 uint32_t initialized:1; /**< Initialized. */ 1111 }; 1112 1113 /* 2 meters in each ASO cache line */ 1114 #define MLX5_MTRS_CONTAINER_RESIZE 64 1115 /* 1116 * The pool index and offset of meter in the pool array makes up the 1117 * meter index. In case the meter is from pool 0 and offset 0, it 1118 * should plus 1 to avoid index 0, since 0 means invalid meter index 1119 * currently. 1120 */ 1121 #define MLX5_MAKE_MTR_IDX(pi, offset) \ 1122 ((pi) * MLX5_ASO_MTRS_PER_POOL + (offset) + 1) 1123 1124 /*aso flow meter state*/ 1125 enum mlx5_aso_mtr_state { 1126 ASO_METER_FREE, /* In free list. */ 1127 ASO_METER_WAIT, /* ACCESS_ASO WQE in progress. */ 1128 ASO_METER_WAIT_ASYNC, /* CQE will be handled by async pull. */ 1129 ASO_METER_READY, /* CQE received. */ 1130 }; 1131 1132 /*aso flow meter type*/ 1133 enum mlx5_aso_mtr_type { 1134 ASO_METER_INDIRECT, 1135 ASO_METER_DIRECT, 1136 }; 1137 1138 /* Generic aso_flow_meter information. */ 1139 struct mlx5_aso_mtr { 1140 union { 1141 LIST_ENTRY(mlx5_aso_mtr) next; 1142 struct mlx5_aso_mtr_pool *pool; 1143 }; 1144 enum mlx5_aso_mtr_type type; 1145 struct mlx5_flow_meter_info fm; 1146 /**< Pointer to the next aso flow meter structure. */ 1147 RTE_ATOMIC(uint8_t) state; /**< ASO flow meter state. */ 1148 uint32_t offset; 1149 enum rte_color init_color; 1150 }; 1151 1152 /* Generic aso_flow_meter pool structure. */ 1153 struct mlx5_aso_mtr_pool { 1154 struct mlx5_aso_mtr mtrs[MLX5_ASO_MTRS_PER_POOL]; 1155 /*Must be the first in pool*/ 1156 struct mlx5_devx_obj *devx_obj; 1157 /* The devx object of the minimum aso flow meter ID. */ 1158 struct mlx5dr_action *action; /* HWS action. */ 1159 struct mlx5_indexed_pool *idx_pool; /* HWS index pool. */ 1160 uint32_t index; /* Pool index in management structure. */ 1161 uint32_t nb_sq; /* Number of ASO SQ. */ 1162 struct mlx5_aso_sq *sq; /* ASO SQs. */ 1163 }; 1164 1165 LIST_HEAD(aso_meter_list, mlx5_aso_mtr); 1166 /* Pools management structure for ASO flow meter pools. */ 1167 struct mlx5_aso_mtr_pools_mng { 1168 volatile uint16_t n_valid; /* Number of valid pools. */ 1169 uint16_t n; /* Number of pools. */ 1170 rte_spinlock_t mtrsl; /* The ASO flow meter free list lock. */ 1171 rte_rwlock_t resize_mtrwl; /* Lock for resize objects. */ 1172 struct aso_meter_list meters; /* Free ASO flow meter list. */ 1173 struct mlx5_aso_sq sq; /*SQ using by ASO flow meter. */ 1174 struct mlx5_aso_mtr_pool **pools; /* ASO flow meter pool array. */ 1175 }; 1176 1177 /* Bulk management structure for ASO flow meter. */ 1178 struct mlx5_mtr_bulk { 1179 uint32_t size; /* Number of ASO objects. */ 1180 struct mlx5dr_action *action; /* HWS action */ 1181 struct mlx5_devx_obj *devx_obj; /* DEVX object. */ 1182 struct mlx5_aso_mtr *aso; /* Array of ASO objects. */ 1183 }; 1184 1185 /* Meter management structure for global flow meter resource. */ 1186 struct mlx5_flow_mtr_mng { 1187 struct mlx5_aso_mtr_pools_mng pools_mng; 1188 /* Pools management structure for ASO flow meter pools. */ 1189 struct mlx5_flow_meter_def_policy *def_policy[MLX5_MTR_DOMAIN_MAX]; 1190 /* Default policy table. */ 1191 uint32_t def_policy_id; 1192 /* Default policy id. */ 1193 RTE_ATOMIC(uint32_t) def_policy_ref_cnt; 1194 /** def_policy meter use count. */ 1195 struct mlx5_flow_tbl_resource *drop_tbl[MLX5_MTR_DOMAIN_MAX]; 1196 /* Meter drop table. */ 1197 struct mlx5_flow_dv_matcher * 1198 drop_matcher[MLX5_MTR_DOMAIN_MAX][MLX5_REG_BITS]; 1199 /* Matcher meter in drop table. */ 1200 struct mlx5_flow_dv_matcher *def_matcher[MLX5_MTR_DOMAIN_MAX]; 1201 /* Default matcher in drop table. */ 1202 void *def_rule[MLX5_MTR_DOMAIN_MAX]; 1203 /* Default rule in drop table. */ 1204 uint8_t max_mtr_bits; 1205 /* Indicate how many bits are used by meter id at the most. */ 1206 uint8_t max_mtr_flow_bits; 1207 /* Indicate how many bits are used by meter flow id at the most. */ 1208 }; 1209 1210 /* Table key of the hash organization. */ 1211 union mlx5_flow_tbl_key { 1212 struct { 1213 /* Table ID should be at the lowest address. */ 1214 uint32_t level; /**< Level of the table. */ 1215 uint32_t id:22; /**< ID of the table. */ 1216 uint32_t dummy:1; /**< Dummy table for DV API. */ 1217 uint32_t is_fdb:1; /**< 1 - FDB, 0 - NIC TX/RX. */ 1218 uint32_t is_egress:1; /**< 1 - egress, 0 - ingress. */ 1219 uint32_t reserved:7; /**< must be zero for comparison. */ 1220 }; 1221 uint64_t v64; /**< full 64bits value of key */ 1222 }; 1223 1224 /* Table structure. */ 1225 struct mlx5_flow_tbl_resource { 1226 void *obj; /**< Pointer to DR table object. */ 1227 }; 1228 1229 #define MLX5_MAX_TABLES UINT16_MAX 1230 #define MLX5_HAIRPIN_TX_TABLE (UINT16_MAX - 1) 1231 /* Reserve the last two tables for metadata register copy. */ 1232 #define MLX5_FLOW_MREG_ACT_TABLE_GROUP (MLX5_MAX_TABLES - 1) 1233 #define MLX5_FLOW_MREG_CP_TABLE_GROUP (MLX5_MAX_TABLES - 2) 1234 /* Tables for metering splits should be added here. */ 1235 #define MLX5_FLOW_TABLE_LEVEL_METER (MLX5_MAX_TABLES - 3) 1236 #define MLX5_FLOW_TABLE_LEVEL_POLICY (MLX5_MAX_TABLES - 4) 1237 #define MLX5_MAX_TABLES_EXTERNAL MLX5_FLOW_TABLE_LEVEL_POLICY 1238 #define MLX5_FLOW_TABLE_HWS_POLICY (MLX5_MAX_TABLES - 10) 1239 #define MLX5_MAX_TABLES_FDB UINT16_MAX 1240 #define MLX5_FLOW_TABLE_PTYPE_RSS_NUM 1024 1241 #define MLX5_FLOW_TABLE_PTYPE_RSS_LAST (MLX5_MAX_TABLES - 11) 1242 #define MLX5_FLOW_TABLE_PTYPE_RSS_BASE \ 1243 (1 + MLX5_FLOW_TABLE_PTYPE_RSS_LAST - MLX5_FLOW_TABLE_PTYPE_RSS_NUM) 1244 #define MLX5_FLOW_TABLE_FACTOR 10 1245 1246 /* ID generation structure. */ 1247 struct mlx5_flow_id_pool { 1248 uint32_t *free_arr; /**< Pointer to the a array of free values. */ 1249 uint32_t base_index; 1250 /**< The next index that can be used without any free elements. */ 1251 uint32_t *curr; /**< Pointer to the index to pop. */ 1252 uint32_t *last; /**< Pointer to the last element in the empty array. */ 1253 uint32_t max_id; /**< Maximum id can be allocated from the pool. */ 1254 }; 1255 1256 /* Tx pacing queue structure - for Clock and Rearm queues. */ 1257 struct mlx5_txpp_wq { 1258 /* Completion Queue related data.*/ 1259 struct mlx5_devx_cq cq_obj; 1260 uint32_t cq_ci:24; 1261 uint32_t arm_sn:2; 1262 /* Send Queue related data.*/ 1263 struct mlx5_devx_sq sq_obj; 1264 uint16_t sq_size; /* Number of WQEs in the queue. */ 1265 uint16_t sq_ci; /* Next WQE to execute. */ 1266 }; 1267 1268 /* Tx packet pacing internal timestamp. */ 1269 struct mlx5_txpp_ts { 1270 RTE_ATOMIC(uint64_t) ci_ts; 1271 RTE_ATOMIC(uint64_t) ts; 1272 }; 1273 1274 /* Tx packet pacing structure. */ 1275 struct mlx5_dev_txpp { 1276 pthread_mutex_t mutex; /* Pacing create/destroy mutex. */ 1277 uint32_t refcnt; /* Pacing reference counter. */ 1278 uint32_t freq; /* Timestamp frequency, Hz. */ 1279 uint32_t tick; /* Completion tick duration in nanoseconds. */ 1280 uint32_t test; /* Packet pacing test mode. */ 1281 int32_t skew; /* Scheduling skew. */ 1282 struct rte_intr_handle *intr_handle; /* Periodic interrupt. */ 1283 void *echan; /* Event Channel. */ 1284 struct mlx5_txpp_wq clock_queue; /* Clock Queue. */ 1285 struct mlx5_txpp_wq rearm_queue; /* Clock Queue. */ 1286 void *pp; /* Packet pacing context. */ 1287 uint16_t pp_id; /* Packet pacing context index. */ 1288 uint16_t ts_n; /* Number of captured timestamps. */ 1289 uint16_t ts_p; /* Pointer to statistics timestamp. */ 1290 struct mlx5_txpp_ts *tsa; /* Timestamps sliding window stats. */ 1291 struct mlx5_txpp_ts ts; /* Cached completion id/timestamp. */ 1292 uint32_t sync_lost:1; /* ci/timestamp synchronization lost. */ 1293 /* Statistics counters. */ 1294 RTE_ATOMIC(uint64_t) err_miss_int; /* Missed service interrupt. */ 1295 RTE_ATOMIC(uint64_t) err_rearm_queue; /* Rearm Queue errors. */ 1296 RTE_ATOMIC(uint64_t) err_clock_queue; /* Clock Queue errors. */ 1297 RTE_ATOMIC(uint64_t) err_ts_past; /* Timestamp in the past. */ 1298 RTE_ATOMIC(uint64_t) err_ts_future; /* Timestamp in the distant future. */ 1299 RTE_ATOMIC(uint64_t) err_ts_order; /* Timestamp not in ascending order. */ 1300 }; 1301 1302 /* Sample ID information of eCPRI flex parser structure. */ 1303 struct mlx5_ecpri_parser_profile { 1304 uint32_t num; /* Actual number of samples. */ 1305 uint32_t ids[8]; /* Sample IDs for this profile. */ 1306 uint8_t offset[8]; /* Bytes offset of each parser. */ 1307 void *obj; /* Flex parser node object. */ 1308 }; 1309 1310 /* Max member ports per bonding device. */ 1311 #define MLX5_BOND_MAX_PORTS 2 1312 1313 /* Bonding device information. */ 1314 struct mlx5_bond_info { 1315 int n_port; /* Number of bond member ports. */ 1316 uint32_t ifindex; 1317 char ifname[MLX5_NAMESIZE + 1]; 1318 struct { 1319 char ifname[MLX5_NAMESIZE + 1]; 1320 uint32_t ifindex; 1321 struct rte_pci_addr pci_addr; 1322 } ports[MLX5_BOND_MAX_PORTS]; 1323 }; 1324 1325 /* Number of connection tracking objects per pool: must be a power of 2. */ 1326 #define MLX5_ASO_CT_ACTIONS_PER_POOL 64 1327 1328 /* Generate incremental and unique CT index from pool and offset. */ 1329 #define MLX5_MAKE_CT_IDX(pool, offset) \ 1330 ((pool) * MLX5_ASO_CT_ACTIONS_PER_POOL + (offset) + 1) 1331 1332 /* ASO Conntrack state. */ 1333 enum mlx5_aso_ct_state { 1334 ASO_CONNTRACK_FREE, /* Inactive, in the free list. */ 1335 ASO_CONNTRACK_WAIT, /* WQE sent in the SQ. */ 1336 ASO_CONNTRACK_WAIT_ASYNC, /* CQE will be handled by async pull. */ 1337 ASO_CONNTRACK_READY, /* CQE received w/o error. */ 1338 ASO_CONNTRACK_QUERY, /* WQE for query sent. */ 1339 ASO_CONNTRACK_MAX, /* Guard. */ 1340 }; 1341 1342 /* Generic ASO connection tracking structure. */ 1343 struct mlx5_aso_ct_action { 1344 union { 1345 /* SWS mode struct. */ 1346 struct { 1347 /* Pointer to the next ASO CT. Used only in SWS. */ 1348 LIST_ENTRY(mlx5_aso_ct_action) next; 1349 }; 1350 /* HWS mode struct. */ 1351 struct { 1352 /* Pointer to action pool. Used only in HWS. */ 1353 struct mlx5_aso_ct_pool *pool; 1354 }; 1355 }; 1356 /* General action object for original dir. */ 1357 void *dr_action_orig; 1358 /* General action object for reply dir. */ 1359 void *dr_action_rply; 1360 RTE_ATOMIC(uint32_t) refcnt; /* Action used count in device flows. */ 1361 uint32_t offset; /* Offset of ASO CT in DevX objects bulk. */ 1362 uint16_t peer; /* The only peer port index could also use this CT. */ 1363 RTE_ATOMIC(enum mlx5_aso_ct_state) state; /* ASO CT state. */ 1364 bool is_original; /* The direction of the DR action to be used. */ 1365 }; 1366 1367 /* CT action object state update. */ 1368 #define MLX5_ASO_CT_UPDATE_STATE(c, s) \ 1369 rte_atomic_store_explicit(&((c)->state), (s), rte_memory_order_relaxed) 1370 1371 #ifdef PEDANTIC 1372 #pragma GCC diagnostic ignored "-Wpedantic" 1373 #endif 1374 1375 /* ASO connection tracking software pool definition. */ 1376 struct mlx5_aso_ct_pool { 1377 uint16_t index; /* Pool index in pools array. */ 1378 /* Free ASO CT index in the pool. Used by HWS. */ 1379 struct mlx5_indexed_pool *cts; 1380 struct mlx5_devx_obj *devx_obj; 1381 union { 1382 void *dummy_action; 1383 /* Dummy action to increase the reference count in the driver. */ 1384 struct mlx5dr_action *dr_action; 1385 /* HWS action. */ 1386 }; 1387 struct mlx5_aso_sq *sq; /* Async ASO SQ. */ 1388 struct mlx5_aso_sq *shared_sq; /* Shared ASO SQ. */ 1389 struct mlx5_aso_ct_action actions[]; 1390 /* CT action structures bulk. */ 1391 }; 1392 1393 LIST_HEAD(aso_ct_list, mlx5_aso_ct_action); 1394 1395 #define MLX5_ASO_CT_SQ_NUM 16 1396 1397 /* Pools management structure for ASO connection tracking pools. */ 1398 struct mlx5_aso_ct_pools_mng { 1399 struct mlx5_aso_ct_pool **pools; 1400 uint16_t n; /* Total number of pools. */ 1401 uint16_t next; /* Number of pools in use, index of next free pool. */ 1402 uint32_t nb_sq; /* Number of ASO SQ. */ 1403 rte_spinlock_t ct_sl; /* The ASO CT free list lock. */ 1404 rte_rwlock_t resize_rwl; /* The ASO CT pool resize lock. */ 1405 struct aso_ct_list free_cts; /* Free ASO CT objects list. */ 1406 struct mlx5_aso_sq aso_sqs[]; /* ASO queue objects. */ 1407 }; 1408 1409 #ifdef PEDANTIC 1410 #pragma GCC diagnostic error "-Wpedantic" 1411 #endif 1412 1413 /* LAG attr. */ 1414 struct mlx5_lag { 1415 uint8_t tx_remap_affinity[16]; /* The PF port number of affinity */ 1416 uint8_t affinity_mode; /* TIS or hash based affinity */ 1417 }; 1418 1419 /* DevX flex parser context. */ 1420 struct mlx5_flex_parser_devx { 1421 struct mlx5_list_entry entry; /* List element at the beginning. */ 1422 uint32_t num_samples; 1423 uint8_t anchor_id; 1424 void *devx_obj; 1425 struct mlx5_devx_graph_node_attr devx_conf; 1426 uint32_t sample_ids[MLX5_GRAPH_NODE_SAMPLE_NUM]; 1427 struct mlx5_devx_match_sample_info_query_attr sample_info[MLX5_GRAPH_NODE_SAMPLE_NUM]; 1428 }; 1429 1430 /* Pattern field descriptor - how to translate flex pattern into samples. */ 1431 __extension__ 1432 struct mlx5_flex_pattern_field { 1433 uint16_t width:6; 1434 uint16_t shift:5; 1435 uint16_t reg_id:5; 1436 }; 1437 1438 #define MLX5_INVALID_SAMPLE_REG_ID 0x1F 1439 1440 /* Port flex item context. */ 1441 struct mlx5_flex_item { 1442 struct mlx5_flex_parser_devx *devx_fp; /* DevX flex parser object. */ 1443 RTE_ATOMIC(uint32_t) refcnt; /* Atomically accessed refcnt by flows. */ 1444 enum rte_flow_item_flex_tunnel_mode tunnel_mode; /* Tunnel mode. */ 1445 uint32_t mapnum; /* Number of pattern translation entries. */ 1446 struct mlx5_flex_pattern_field map[MLX5_FLEX_ITEM_MAPPING_NUM]; 1447 }; 1448 1449 /* 1450 * Sample an IPv6 address and the first dword of SRv6 header. 1451 * Then it is 16 + 4 = 20 bytes which is 5 dwords. 1452 */ 1453 #define MLX5_SRV6_SAMPLE_NUM 5 1454 /* Mlx5 internal flex parser profile structure. */ 1455 struct mlx5_internal_flex_parser_profile { 1456 RTE_ATOMIC(uint32_t) refcnt; 1457 struct mlx5_flex_item flex; /* Hold map info for modify field. */ 1458 }; 1459 1460 struct mlx5_send_to_kernel_action { 1461 void *action; 1462 void *tbl; 1463 }; 1464 1465 #define HWS_CNT_ASO_SQ_NUM 4 1466 1467 struct mlx5_hws_aso_mng { 1468 uint16_t sq_num; 1469 struct mlx5_aso_sq sqs[HWS_CNT_ASO_SQ_NUM]; 1470 }; 1471 1472 struct mlx5_hws_cnt_svc_mng { 1473 uint32_t refcnt; 1474 uint32_t service_core; 1475 uint32_t query_interval; 1476 rte_thread_t service_thread; 1477 uint8_t svc_running; 1478 alignas(RTE_CACHE_LINE_SIZE) struct mlx5_hws_aso_mng aso_mng; 1479 }; 1480 1481 #define MLX5_FLOW_HW_TAGS_MAX 12 1482 #define MLX5_FLOW_NAT64_REGS_MAX 3 1483 1484 struct mlx5_dev_registers { 1485 enum modify_reg aso_reg; 1486 enum modify_reg hw_avl_tags[MLX5_FLOW_HW_TAGS_MAX]; 1487 enum modify_reg nat64_regs[MLX5_FLOW_NAT64_REGS_MAX]; 1488 }; 1489 1490 #if defined(HAVE_MLX5DV_DR) && \ 1491 (defined(HAVE_MLX5_DR_CREATE_ACTION_FLOW_METER) || \ 1492 defined(HAVE_MLX5_DR_CREATE_ACTION_ASO)) 1493 #define HAVE_MLX5_DR_CREATE_ACTION_ASO_EXT 1494 #endif 1495 1496 struct mlx5_geneve_tlv_options; 1497 1498 enum mlx5_ipv6_tc_support { 1499 MLX5_IPV6_TC_UNKNOWN = 0, 1500 MLX5_IPV6_TC_FALLBACK, 1501 MLX5_IPV6_TC_OK, 1502 }; 1503 1504 struct mlx5_common_nic_config { 1505 enum mlx5_ipv6_tc_support ipv6_tc_fallback; 1506 /* Whether ipv6 traffic class should use old value. */ 1507 }; 1508 1509 /** 1510 * Physical device structure. 1511 * This device is created once per NIC to manage recourses shared by all ports 1512 * under same physical device. 1513 */ 1514 struct mlx5_physical_device { 1515 LIST_ENTRY(mlx5_physical_device) next; 1516 struct mlx5_dev_ctx_shared *sh; /* Created on sherd context. */ 1517 uint64_t guid; /* System image guid, the uniq ID of physical device. */ 1518 struct mlx5_geneve_tlv_options *tlv_options; 1519 struct mlx5_common_nic_config config; 1520 uint32_t refcnt; 1521 }; 1522 1523 /* 1524 * Shared Infiniband device context for Master/Representors 1525 * which belong to same IB device with multiple IB ports. 1526 **/ 1527 struct mlx5_dev_ctx_shared { 1528 LIST_ENTRY(mlx5_dev_ctx_shared) next; 1529 uint32_t refcnt; 1530 uint32_t esw_mode:1; /* Whether is E-Switch mode. */ 1531 uint32_t flow_hit_aso_en:1; /* Flow Hit ASO is supported. */ 1532 uint32_t steering_format_version:4; 1533 /* Indicates the device steering logic format. */ 1534 uint32_t meter_aso_en:1; /* Flow Meter ASO is supported. */ 1535 uint32_t ct_aso_en:1; /* Connection Tracking ASO is supported. */ 1536 uint32_t tunnel_header_0_1:1; /* tunnel_header_0_1 is supported. */ 1537 uint32_t tunnel_header_2_3:1; /* tunnel_header_2_3 is supported. */ 1538 uint32_t misc5_cap:1; /* misc5 matcher parameter is supported. */ 1539 uint32_t dr_root_drop_action_en:1; /* DR drop action is usable on root tables. */ 1540 uint32_t drop_action_check_flag:1; /* Check Flag for drop action. */ 1541 uint32_t flow_priority_check_flag:1; /* Check Flag for flow priority. */ 1542 uint32_t metadata_regc_check_flag:1; /* Check Flag for metadata REGC. */ 1543 uint32_t shared_mark_enabled:1; 1544 /* If mark action is enabled on Rxqs (shared E-Switch domain). */ 1545 uint32_t lag_rx_port_affinity_en:1; 1546 /* lag_rx_port_affinity is supported. */ 1547 uint32_t hws_max_log_bulk_sz:5; 1548 /* Log of minimal HWS counters created hard coded. */ 1549 uint32_t hws_max_nb_counters; /* Maximal number for HWS counters. */ 1550 uint32_t max_port; /* Maximal IB device port index. */ 1551 struct mlx5_bond_info bond; /* Bonding information. */ 1552 struct mlx5_common_device *cdev; /* Backend mlx5 device. */ 1553 struct mlx5_physical_device *phdev; /* Backend physical device. */ 1554 uint32_t tdn; /* Transport Domain number. */ 1555 char ibdev_name[MLX5_FS_NAME_MAX]; /* SYSFS dev name. */ 1556 char ibdev_path[MLX5_FS_PATH_MAX]; /* SYSFS dev path for secondary */ 1557 struct mlx5_dev_cap dev_cap; /* Device capabilities. */ 1558 struct mlx5_sh_config config; /* Device configuration. */ 1559 int numa_node; /* Numa node of backing physical device. */ 1560 /* Packet pacing related structure. */ 1561 struct mlx5_dev_txpp txpp; 1562 /* Shared DV/DR flow data section. */ 1563 uint32_t dv_meta_mask; /* flow META metadata supported mask. */ 1564 uint32_t dv_mark_mask; /* flow MARK metadata supported mask. */ 1565 uint32_t dv_regc0_mask; /* available bits of metadata reg_c[0]. */ 1566 void *fdb_domain; /* FDB Direct Rules name space handle. */ 1567 void *rx_domain; /* RX Direct Rules name space handle. */ 1568 void *tx_domain; /* TX Direct Rules name space handle. */ 1569 #ifndef RTE_ARCH_64 1570 rte_spinlock_t uar_lock_cq; /* CQs share a common distinct UAR. */ 1571 rte_spinlock_t uar_lock[MLX5_UAR_PAGE_NUM_MAX]; 1572 /* UAR same-page access control required in 32bit implementations. */ 1573 #endif 1574 union { 1575 struct mlx5_hlist *flow_tbls; /* SWS flow table. */ 1576 struct mlx5_hlist *groups; /* HWS flow group. */ 1577 }; 1578 struct mlx5_hlist *mreg_cp_tbl; 1579 /* Hash table of Rx metadata register copy table. */ 1580 struct mlx5_flow_tunnel_hub *tunnel_hub; 1581 /* Direct Rules tables for FDB, NIC TX+RX */ 1582 void *dr_drop_action; /* Pointer to DR drop action, any domain. */ 1583 void *pop_vlan_action; /* Pointer to DR pop VLAN action. */ 1584 #if defined(HAVE_IBV_FLOW_DV_SUPPORT) || !defined(HAVE_INFINIBAND_VERBS_H) 1585 struct mlx5_send_to_kernel_action send_to_kernel_action[MLX5DR_TABLE_TYPE_MAX]; 1586 #endif 1587 RTE_ATOMIC(struct mlx5_hlist *) encaps_decaps; /* Encap/decap action hash list. */ 1588 RTE_ATOMIC(struct mlx5_hlist *) modify_cmds; 1589 RTE_ATOMIC(struct mlx5_hlist *) tag_table; 1590 struct mlx5_list *port_id_action_list; /* Port ID action list. */ 1591 struct mlx5_list *push_vlan_action_list; /* Push VLAN actions. */ 1592 struct mlx5_list *sample_action_list; /* List of sample actions. */ 1593 struct mlx5_list *dest_array_list; 1594 struct mlx5_list *flex_parsers_dv; /* Flex Item parsers. */ 1595 /* List of destination array actions. */ 1596 struct mlx5_flow_counter_mng sws_cmng; 1597 /* SW steering counters management structure. */ 1598 void *default_miss_action; /* Default miss action. */ 1599 struct mlx5_indexed_pool *ipool[MLX5_IPOOL_MAX]; 1600 RTE_ATOMIC(struct mlx5_indexed_pool *) mdh_ipools[MLX5_MAX_MODIFY_NUM]; 1601 /* Shared interrupt handler section. */ 1602 struct rte_intr_handle *intr_handle; /* Interrupt handler for device. */ 1603 struct rte_intr_handle *intr_handle_devx; /* DEVX interrupt handler. */ 1604 struct rte_intr_handle *intr_handle_nl; /* Netlink interrupt handler. */ 1605 void *devx_comp; /* DEVX async comp obj. */ 1606 struct mlx5_devx_obj *tis[16]; /* TIS object. */ 1607 struct mlx5_devx_obj *td; /* Transport domain. */ 1608 struct mlx5_lag lag; /* LAG attributes */ 1609 struct mlx5_uar tx_uar; /* DevX UAR for Tx and Txpp and ASO SQs. */ 1610 struct mlx5_uar rx_uar; /* DevX UAR for Rx. */ 1611 struct mlx5_proc_priv *pppriv; /* Pointer to primary private process. */ 1612 struct mlx5_ecpri_parser_profile ecpri_parser; 1613 struct mlx5_internal_flex_parser_profile srh_flex_parser; /* srh flex parser structure. */ 1614 /* Flex parser profiles information. */ 1615 LIST_HEAD(shared_rxqs, mlx5_rxq_ctrl) shared_rxqs; /* Shared RXQs. */ 1616 struct mlx5_aso_age_mng *aso_age_mng; 1617 /* Management data for aging mechanism using ASO Flow Hit. */ 1618 struct mlx5_geneve_tlv_option_resource *geneve_tlv_option_resource; 1619 /* Management structure for geneve tlv option */ 1620 rte_spinlock_t geneve_tlv_opt_sl; /* Lock for geneve tlv resource */ 1621 struct mlx5_flow_mtr_mng *mtrmng; 1622 /* Meter management structure. */ 1623 struct mlx5_aso_ct_pools_mng *ct_mng; /* Management data for ASO CT in HWS only. */ 1624 struct mlx5_lb_ctx self_lb; /* QP to enable self loopback for Devx. */ 1625 unsigned int flow_max_priority; 1626 enum modify_reg flow_mreg_c[MLX5_MREG_C_NUM]; 1627 /* Availability of mreg_c's. */ 1628 void *devx_channel_lwm; 1629 struct rte_intr_handle *intr_handle_lwm; 1630 pthread_mutex_t lwm_config_lock; 1631 uint32_t host_shaper_rate:8; 1632 uint32_t lwm_triggered:1; 1633 struct mlx5_hws_cnt_svc_mng *cnt_svc; 1634 rte_spinlock_t cpool_lock; 1635 LIST_HEAD(hws_cpool_list, mlx5_hws_cnt_pool) hws_cpool_list; /* Count pool list. */ 1636 struct mlx5_dev_registers registers; 1637 struct mlx5_dev_shared_port port[]; /* per device port data array. */ 1638 }; 1639 1640 /* 1641 * Per-process private structure. 1642 * Caution, secondary process may rebuild the struct during port start. 1643 */ 1644 struct mlx5_proc_priv { 1645 RTE_ATOMIC(void *) hca_bar; 1646 /* Mapped HCA PCI BAR area. */ 1647 size_t uar_table_sz; 1648 /* Size of UAR register table. */ 1649 struct mlx5_uar_data uar_table[]; 1650 /* Table of UAR registers for each process. */ 1651 }; 1652 1653 /* MTR profile list. */ 1654 TAILQ_HEAD(mlx5_mtr_profiles, mlx5_flow_meter_profile); 1655 /* MTR list. */ 1656 TAILQ_HEAD(mlx5_legacy_flow_meters, mlx5_legacy_flow_meter); 1657 1658 struct mlx5_mtr_config { 1659 uint32_t nb_meters; /**< Number of configured meters */ 1660 uint32_t nb_meter_profiles; /**< Number of configured meter profiles */ 1661 uint32_t nb_meter_policies; /**< Number of configured meter policies */ 1662 }; 1663 1664 /* RSS description. */ 1665 struct mlx5_flow_rss_desc { 1666 bool symmetric_hash_function; /**< Symmetric hash function */ 1667 uint32_t level; 1668 uint32_t queue_num; /**< Number of entries in @p queue. */ 1669 uint64_t types; /**< Specific RSS hash types (see RTE_ETH_RSS_*). */ 1670 uint64_t hash_fields; /* Verbs Hash fields. */ 1671 uint8_t key[MLX5_RSS_HASH_KEY_LEN]; /**< RSS hash key. */ 1672 uint32_t key_len; /**< RSS hash key len. */ 1673 uint32_t hws_flags; /**< HW steering action. */ 1674 uint32_t tunnel; /**< Queue in tunnel. */ 1675 uint32_t shared_rss; /**< Shared RSS index. */ 1676 struct mlx5_ind_table_obj *ind_tbl; 1677 /**< Indirection table for shared RSS hash RX queues. */ 1678 union { 1679 uint16_t *queue; /**< Destination queues. */ 1680 const uint16_t *const_q; /**< Const pointer convert. */ 1681 }; 1682 }; 1683 1684 #define MLX5_PROC_PRIV(port_id) \ 1685 ((struct mlx5_proc_priv *)rte_eth_devices[port_id].process_private) 1686 1687 /* Verbs/DevX Rx queue elements. */ 1688 struct mlx5_rxq_obj { 1689 LIST_ENTRY(mlx5_rxq_obj) next; /* Pointer to the next element. */ 1690 struct mlx5_rxq_ctrl *rxq_ctrl; /* Back pointer to parent. */ 1691 int fd; /* File descriptor for event channel */ 1692 union { 1693 struct { 1694 void *wq; /* Work Queue. */ 1695 void *ibv_cq; /* Completion Queue. */ 1696 void *ibv_channel; 1697 }; 1698 struct mlx5_devx_obj *rq; /* DevX RQ object for hairpin. */ 1699 struct { 1700 struct mlx5_devx_rmp devx_rmp; /* RMP for shared RQ. */ 1701 struct mlx5_devx_cq cq_obj; /* DevX CQ object. */ 1702 void *devx_channel; 1703 }; 1704 }; 1705 }; 1706 1707 /* Indirection table. */ 1708 struct mlx5_ind_table_obj { 1709 LIST_ENTRY(mlx5_ind_table_obj) next; /* Pointer to the next element. */ 1710 RTE_ATOMIC(uint32_t) refcnt; /* Reference counter. */ 1711 union { 1712 void *ind_table; /**< Indirection table. */ 1713 struct mlx5_devx_obj *rqt; /* DevX RQT object. */ 1714 }; 1715 uint32_t queues_n; /**< Number of queues in the list. */ 1716 uint16_t *queues; /**< Queue list. */ 1717 }; 1718 1719 /* Hash Rx queue. */ 1720 __extension__ 1721 struct mlx5_hrxq { 1722 struct mlx5_list_entry entry; /* List entry. */ 1723 uint32_t standalone:1; /* This object used in shared action. */ 1724 struct mlx5_ind_table_obj *ind_table; /* Indirection table. */ 1725 union { 1726 void *qp; /* Verbs queue pair. */ 1727 struct mlx5_devx_obj *tir; /* DevX TIR object. */ 1728 }; 1729 #if defined(HAVE_IBV_FLOW_DV_SUPPORT) || !defined(HAVE_INFINIBAND_VERBS_H) 1730 void *action; /* DV QP action pointer. */ 1731 #endif 1732 bool symmetric_hash_function; /* Symmetric hash function */ 1733 uint32_t hws_flags; /* Hw steering flags. */ 1734 uint64_t hash_fields; /* Verbs Hash fields. */ 1735 uint32_t rss_key_len; /* Hash key length in bytes. */ 1736 uint32_t idx; /* Hash Rx queue index. */ 1737 uint8_t rss_key[]; /* Hash key. */ 1738 }; 1739 1740 /* Verbs/DevX Tx queue elements. */ 1741 struct mlx5_txq_obj { 1742 LIST_ENTRY(mlx5_txq_obj) next; /* Pointer to the next element. */ 1743 struct mlx5_txq_ctrl *txq_ctrl; /* Pointer to the control queue. */ 1744 union { 1745 struct { 1746 void *cq; /* Completion Queue. */ 1747 void *qp; /* Queue Pair. */ 1748 }; 1749 struct { 1750 struct mlx5_devx_obj *sq; 1751 /* DevX object for Sx queue. */ 1752 struct mlx5_devx_obj *tis; /* The TIS object. */ 1753 void *umem_buf_wq_buffer; 1754 void *umem_obj_wq_buffer; 1755 }; 1756 struct { 1757 struct rte_eth_dev *dev; 1758 struct mlx5_devx_cq cq_obj; 1759 /* DevX CQ object and its resources. */ 1760 struct mlx5_devx_sq sq_obj; 1761 /* DevX SQ object and its resources. */ 1762 }; 1763 }; 1764 }; 1765 1766 enum mlx5_rxq_modify_type { 1767 MLX5_RXQ_MOD_ERR2RST, /* modify state from error to reset. */ 1768 MLX5_RXQ_MOD_RST2RDY, /* modify state from reset to ready. */ 1769 MLX5_RXQ_MOD_RDY2ERR, /* modify state from ready to error. */ 1770 MLX5_RXQ_MOD_RDY2RST, /* modify state from ready to reset. */ 1771 MLX5_RXQ_MOD_RDY2RDY, /* modify state from ready to ready. */ 1772 }; 1773 1774 enum mlx5_txq_modify_type { 1775 MLX5_TXQ_MOD_RST2RDY, /* modify state from reset to ready. */ 1776 MLX5_TXQ_MOD_RDY2RST, /* modify state from ready to reset. */ 1777 MLX5_TXQ_MOD_ERR2RDY, /* modify state from error to ready. */ 1778 }; 1779 1780 struct mlx5_rxq_priv; 1781 struct mlx5_priv; 1782 1783 /* HW objects operations structure. */ 1784 struct mlx5_obj_ops { 1785 int (*rxq_obj_modify_vlan_strip)(struct mlx5_rxq_priv *rxq, int on); 1786 int (*rxq_obj_new)(struct mlx5_rxq_priv *rxq); 1787 int (*rxq_event_get)(struct mlx5_rxq_obj *rxq_obj); 1788 int (*rxq_obj_modify)(struct mlx5_rxq_priv *rxq, uint8_t type); 1789 void (*rxq_obj_release)(struct mlx5_rxq_priv *rxq); 1790 int (*rxq_event_get_lwm)(struct mlx5_priv *priv, int *rxq_idx, int *port_id); 1791 int (*ind_table_new)(struct rte_eth_dev *dev, const unsigned int log_n, 1792 struct mlx5_ind_table_obj *ind_tbl); 1793 int (*ind_table_modify)(struct rte_eth_dev *dev, 1794 const unsigned int log_n, 1795 const uint16_t *queues, const uint32_t queues_n, 1796 struct mlx5_ind_table_obj *ind_tbl); 1797 void (*ind_table_destroy)(struct mlx5_ind_table_obj *ind_tbl); 1798 int (*hrxq_new)(struct rte_eth_dev *dev, struct mlx5_hrxq *hrxq, 1799 int tunnel __rte_unused); 1800 int (*hrxq_modify)(struct rte_eth_dev *dev, struct mlx5_hrxq *hrxq, 1801 const uint8_t *rss_key, 1802 uint64_t hash_fields, 1803 bool symmetric_hash_function, 1804 const struct mlx5_ind_table_obj *ind_tbl); 1805 void (*hrxq_destroy)(struct mlx5_hrxq *hrxq); 1806 int (*drop_action_create)(struct rte_eth_dev *dev); 1807 void (*drop_action_destroy)(struct rte_eth_dev *dev); 1808 int (*txq_obj_new)(struct rte_eth_dev *dev, uint16_t idx); 1809 int (*txq_obj_modify)(struct mlx5_txq_obj *obj, 1810 enum mlx5_txq_modify_type type, uint8_t dev_port); 1811 void (*txq_obj_release)(struct mlx5_txq_obj *txq_obj); 1812 int (*lb_dummy_queue_create)(struct rte_eth_dev *dev); 1813 void (*lb_dummy_queue_release)(struct rte_eth_dev *dev); 1814 }; 1815 1816 #define MLX5_RSS_HASH_FIELDS_LEN RTE_DIM(mlx5_rss_hash_fields) 1817 1818 enum mlx5_ctrl_flow_type { 1819 MLX5_CTRL_FLOW_TYPE_GENERAL, 1820 MLX5_CTRL_FLOW_TYPE_SQ_MISS_ROOT, 1821 MLX5_CTRL_FLOW_TYPE_SQ_MISS, 1822 MLX5_CTRL_FLOW_TYPE_DEFAULT_JUMP, 1823 MLX5_CTRL_FLOW_TYPE_TX_META_COPY, 1824 MLX5_CTRL_FLOW_TYPE_TX_REPR_MATCH, 1825 MLX5_CTRL_FLOW_TYPE_LACP_RX, 1826 MLX5_CTRL_FLOW_TYPE_DEFAULT_RX_RSS, 1827 MLX5_CTRL_FLOW_TYPE_DEFAULT_RX_RSS_UNICAST_DMAC, 1828 MLX5_CTRL_FLOW_TYPE_DEFAULT_RX_RSS_UNICAST_DMAC_VLAN, 1829 }; 1830 1831 /** Additional info about control flow rule. */ 1832 struct mlx5_ctrl_flow_info { 1833 /** Determines the kind of control flow rule. */ 1834 enum mlx5_ctrl_flow_type type; 1835 union { 1836 /** 1837 * If control flow is a SQ miss flow (root or not), 1838 * then fields contains matching SQ number. 1839 */ 1840 uint32_t esw_mgr_sq; 1841 /** 1842 * If control flow is a Tx representor matching, 1843 * then fields contains matching SQ number. 1844 */ 1845 uint32_t tx_repr_sq; 1846 /** Contains data relevant for unicast control flow rules. */ 1847 struct { 1848 /** 1849 * If control flow is a unicast DMAC (or with VLAN) flow rule, 1850 * then this field contains DMAC. 1851 */ 1852 struct rte_ether_addr dmac; 1853 /** 1854 * If control flow is a unicast DMAC with VLAN flow rule, 1855 * then this field contains VLAN ID. 1856 */ 1857 uint16_t vlan; 1858 } uc; 1859 }; 1860 }; 1861 1862 /** Returns true if a control flow rule with unicast DMAC match on given address was created. */ 1863 bool mlx5_ctrl_flow_uc_dmac_exists(struct rte_eth_dev *dev, const struct rte_ether_addr *addr); 1864 1865 /** 1866 * Returns true if a control flow rule with unicast DMAC and VLAN match 1867 * on given values was created. 1868 */ 1869 bool mlx5_ctrl_flow_uc_dmac_vlan_exists(struct rte_eth_dev *dev, 1870 const struct rte_ether_addr *addr, 1871 const uint16_t vid); 1872 1873 /** Entry for tracking control flow rules in HWS. */ 1874 struct mlx5_ctrl_flow_entry { 1875 LIST_ENTRY(mlx5_ctrl_flow_entry) next; 1876 /** 1877 * Owner device is a port on behalf of which flow rule was created. 1878 * 1879 * It's different from the port which really created the flow rule 1880 * if and only if flow rule is created on transfer proxy port 1881 * on behalf of representor port. 1882 */ 1883 struct rte_eth_dev *owner_dev; 1884 /** Pointer to flow rule handle. */ 1885 struct rte_flow *flow; 1886 /** Additional information about the control flow rule. */ 1887 struct mlx5_ctrl_flow_info info; 1888 }; 1889 1890 /* HW Steering port configuration passed to rte_flow_configure(). */ 1891 struct mlx5_flow_hw_attr { 1892 struct rte_flow_port_attr port_attr; 1893 uint16_t nb_queue; 1894 struct rte_flow_queue_attr *queue_attr; 1895 bool nt_mode; 1896 }; 1897 1898 /* 1899 * Flow rule structure for flow engine mode control, focus on group 0. 1900 * Apply to all supported domains. 1901 */ 1902 struct mlx5_dv_flow_info { 1903 LIST_ENTRY(mlx5_dv_flow_info) next; 1904 uint32_t orig_prio; /* prio set by user */ 1905 uint32_t flow_idx_high_prio; 1906 /* flow index owned by standby mode. priority is lower unless DUP flags. */ 1907 uint32_t flow_idx_low_prio; 1908 struct rte_flow_item *items; 1909 struct rte_flow_action *actions; 1910 struct rte_flow_attr attr; 1911 }; 1912 1913 struct rte_pmd_mlx5_flow_engine_mode_info { 1914 enum rte_pmd_mlx5_flow_engine_mode mode; 1915 uint32_t mode_flag; 1916 /* The list is maintained in insertion order. */ 1917 LIST_HEAD(hot_up_info, mlx5_dv_flow_info) hot_upgrade; 1918 }; 1919 1920 struct mlx5_flow_hw_ctrl_rx; 1921 1922 enum mlx5_quota_state { 1923 MLX5_QUOTA_STATE_FREE, /* quota not in use */ 1924 MLX5_QUOTA_STATE_READY, /* quota is ready */ 1925 MLX5_QUOTA_STATE_WAIT /* quota waits WR completion */ 1926 }; 1927 1928 struct mlx5_quota { 1929 RTE_ATOMIC(uint8_t) state; /* object state */ 1930 uint8_t mode; /* metering mode */ 1931 /** 1932 * Keep track of application update types. 1933 * PMD does not allow 2 consecutive ADD updates. 1934 */ 1935 enum rte_flow_update_quota_op last_update; 1936 }; 1937 1938 /* Bulk management structure for flow quota. */ 1939 struct mlx5_quota_ctx { 1940 struct mlx5dr_action *dr_action; /* HWS action */ 1941 struct mlx5_devx_obj *devx_obj; /* DEVX ranged object. */ 1942 struct mlx5_pmd_mr mr; /* MR for READ from MTR ASO */ 1943 struct mlx5_aso_mtr_dseg **read_buf; /* Buffers for READ */ 1944 struct mlx5_aso_sq *sq; /* SQs for sync/async ACCESS_ASO WRs */ 1945 struct mlx5_indexed_pool *quota_ipool; /* Manage quota objects */ 1946 }; 1947 1948 struct mlx5_priv { 1949 struct rte_eth_dev_data *dev_data; /* Pointer to device data. */ 1950 struct mlx5_dev_ctx_shared *sh; /* Shared device context. */ 1951 uint32_t dev_port; /* Device port number. */ 1952 struct rte_pci_device *pci_dev; /* Backend PCI device. */ 1953 struct rte_ether_addr mac[MLX5_MAX_MAC_ADDRESSES]; /* MAC addresses. */ 1954 BITFIELD_DECLARE(mac_own, uint64_t, MLX5_MAX_MAC_ADDRESSES); 1955 /* Bit-field of MAC addresses owned by the PMD. */ 1956 uint16_t vlan_filter[MLX5_MAX_VLAN_IDS]; /* VLAN filters table. */ 1957 unsigned int vlan_filter_n; /* Number of configured VLAN filters. */ 1958 /* Device properties. */ 1959 uint16_t mtu; /* Configured MTU. */ 1960 unsigned int isolated:1; /* Whether isolated mode is enabled. */ 1961 unsigned int representor:1; /* Device is a port representor. */ 1962 unsigned int master:1; /* Device is a E-Switch master. */ 1963 unsigned int txpp_en:1; /* Tx packet pacing enabled. */ 1964 unsigned int sampler_en:1; /* Whether support sampler. */ 1965 unsigned int mtr_en:1; /* Whether support meter. */ 1966 unsigned int mtr_reg_share:1; /* Whether support meter REG_C share. */ 1967 unsigned int lb_used:1; /* Loopback queue is referred to. */ 1968 unsigned int rmv_notified:1; /* Notified about removal event */ 1969 uint32_t mark_enabled:1; /* If mark action is enabled on rxqs. */ 1970 uint32_t num_lag_ports:4; /* Number of ports can be bonded. */ 1971 uint32_t tunnel_enabled:1; /* If tunnel offloading is enabled on rxqs. */ 1972 uint16_t domain_id; /* Switch domain identifier. */ 1973 uint16_t vport_id; /* Associated VF vport index (if any). */ 1974 uint32_t vport_meta_tag; /* Used for vport index match ove VF LAG. */ 1975 uint32_t vport_meta_mask; /* Used for vport index field match mask. */ 1976 uint16_t representor_id; /* UINT16_MAX if not a representor. */ 1977 int32_t pf_bond; /* >=0, representor owner PF index in bonding. */ 1978 int32_t mpesw_owner; /* >=0, representor owner PF index in MPESW. */ 1979 int32_t mpesw_port; /* Related port index of MPESW device. < 0 - no MPESW. */ 1980 bool mpesw_uplink; /* If true, port is an uplink port. */ 1981 unsigned int if_index; /* Associated kernel network device index. */ 1982 /* RX/TX queues. */ 1983 unsigned int rxqs_n; /* RX queues array size. */ 1984 unsigned int txqs_n; /* TX queues array size. */ 1985 struct mlx5_external_q *ext_rxqs; /* External RX queues array. */ 1986 struct mlx5_external_q *ext_txqs; /* External TX queues array. */ 1987 struct mlx5_rxq_priv *(*rxq_privs)[]; /* RX queue non-shared data. */ 1988 struct mlx5_txq_data *(*txqs)[]; /* TX queues. */ 1989 struct rte_mempool *mprq_mp; /* Mempool for Multi-Packet RQ. */ 1990 struct rte_eth_rss_conf rss_conf; /* RSS configuration. */ 1991 unsigned int (*reta_idx)[]; /* RETA index table. */ 1992 unsigned int reta_idx_n; /* RETA index size. */ 1993 struct mlx5_drop drop_queue; /* Flow drop queues. */ 1994 void *root_drop_action; /* Pointer to root drop action. */ 1995 rte_spinlock_t hw_ctrl_lock; 1996 LIST_HEAD(hw_ctrl_flow, mlx5_ctrl_flow_entry) hw_ctrl_flows; 1997 LIST_HEAD(hw_ext_ctrl_flow, mlx5_ctrl_flow_entry) hw_ext_ctrl_flows; 1998 struct mlx5_flow_hw_ctrl_fdb *hw_ctrl_fdb; 1999 struct rte_flow_pattern_template *hw_tx_repr_tagging_pt; 2000 struct rte_flow_actions_template *hw_tx_repr_tagging_at; 2001 struct rte_flow_template_table *hw_tx_repr_tagging_tbl; 2002 struct mlx5_indexed_pool *flows[MLX5_FLOW_TYPE_MAXI]; 2003 /* RTE Flow rules. */ 2004 uint32_t ctrl_flows; /* Control flow rules. */ 2005 rte_spinlock_t flow_list_lock; 2006 struct mlx5_obj_ops obj_ops; /* HW objects operations. */ 2007 LIST_HEAD(rxqobj, mlx5_rxq_obj) rxqsobj; /* Verbs/DevX Rx queues. */ 2008 struct mlx5_list *hrxqs; /* Hash Rx queues. */ 2009 LIST_HEAD(txq, mlx5_txq_ctrl) txqsctrl; /* DPDK Tx queues. */ 2010 LIST_HEAD(txqobj, mlx5_txq_obj) txqsobj; /* Verbs/DevX Tx queues. */ 2011 /* Indirection tables. */ 2012 LIST_HEAD(ind_tables, mlx5_ind_table_obj) ind_tbls; 2013 /* Standalone indirect tables. */ 2014 LIST_HEAD(stdl_ind_tables, mlx5_ind_table_obj) standalone_ind_tbls; 2015 /* Objects created with indirect list action */ 2016 LIST_HEAD(indirect_list, mlx5_indirect_list) indirect_list_head; 2017 /* Pointer to next element. */ 2018 rte_rwlock_t ind_tbls_lock; 2019 uint32_t refcnt; /**< Reference counter. */ 2020 /**< Verbs modify header action object. */ 2021 uint8_t ft_type; /**< Flow table type, Rx or Tx. */ 2022 uint32_t max_lro_msg_size; 2023 uint32_t link_speed_capa; /* Link speed capabilities. */ 2024 struct mlx5_xstats_ctrl xstats_ctrl; /* Extended stats control. */ 2025 struct mlx5_stats_ctrl stats_ctrl; /* Stats control. */ 2026 struct mlx5_port_config config; /* Port configuration. */ 2027 /* Context for Verbs allocator. */ 2028 int nl_socket_rdma; /* Netlink socket (NETLINK_RDMA). */ 2029 int nl_socket_route; /* Netlink socket (NETLINK_ROUTE). */ 2030 struct mlx5_nl_vlan_vmwa_context *vmwa_context; /* VLAN WA context. */ 2031 struct mlx5_mtr_config mtr_config; /* Meter configuration */ 2032 uint8_t mtr_sfx_reg; /* Meter prefix-suffix flow match REG_C. */ 2033 struct mlx5_legacy_flow_meters flow_meters; /* MTR list. */ 2034 struct mlx5_l3t_tbl *mtr_profile_tbl; /* Meter index lookup table. */ 2035 struct mlx5_flow_meter_profile *mtr_profile_arr; /* Profile array. */ 2036 struct mlx5_l3t_tbl *policy_idx_tbl; /* Policy index lookup table. */ 2037 struct mlx5_flow_meter_policy *mtr_policy_arr; /* Policy array. */ 2038 struct mlx5_l3t_tbl *mtr_idx_tbl; /* Meter index lookup table. */ 2039 struct mlx5_mtr_bulk mtr_bulk; /* Meter index mapping for HWS */ 2040 struct mlx5_quota_ctx quota_ctx; /* Quota index mapping for HWS */ 2041 uint8_t skip_default_rss_reta; /* Skip configuration of default reta. */ 2042 uint8_t fdb_def_rule; /* Whether fdb jump to table 1 is configured. */ 2043 struct mlx5_mp_id mp_id; /* ID of a multi-process process */ 2044 LIST_HEAD(fdir, mlx5_fdir_flow) fdir_flows; /* fdir flows. */ 2045 rte_spinlock_t shared_act_sl; /* Shared actions spinlock. */ 2046 uint32_t rss_shared_actions; /* RSS shared actions. */ 2047 /* If true, indicates that we failed to allocate a q counter in the past. */ 2048 bool q_counters_allocation_failure; 2049 struct mlx5_devx_obj *q_counters; /* DevX queue counter object. */ 2050 uint32_t counter_set_id; /* Queue counter ID to set in DevX objects. */ 2051 /* DevX queue counter object for all hairpin queues of the port. */ 2052 struct mlx5_devx_obj *q_counters_hairpin; 2053 uint32_t lag_affinity_idx; /* LAG mode queue 0 affinity starting. */ 2054 rte_spinlock_t flex_item_sl; /* Flex item list spinlock. */ 2055 struct mlx5_flex_item flex_item[MLX5_PORT_FLEX_ITEM_NUM]; 2056 /* Flex items have been created on the port. */ 2057 uint32_t flex_item_map; /* Map of allocated flex item elements. */ 2058 uint32_t nb_queue; /* HW steering queue number. */ 2059 struct mlx5_hws_cnt_pool *hws_cpool; /* HW steering's counter pool. */ 2060 RTE_ATOMIC(uint32_t) hws_mark_refcnt; /* HWS mark action reference counter. */ 2061 struct rte_pmd_mlx5_flow_engine_mode_info mode_info; /* Process set flow engine info. */ 2062 struct mlx5_flow_hw_attr *hw_attr; /* HW Steering port configuration. */ 2063 bool hws_rule_flushing; /**< Whether this port is in rules flushing stage. */ 2064 #if defined(HAVE_IBV_FLOW_DV_SUPPORT) || !defined(HAVE_INFINIBAND_VERBS_H) 2065 /* Item template list. */ 2066 LIST_HEAD(flow_hw_itt, rte_flow_pattern_template) flow_hw_itt; 2067 /* Action template list. */ 2068 LIST_HEAD(flow_hw_at, rte_flow_actions_template) flow_hw_at; 2069 struct mlx5dr_context *dr_ctx; /**< HW steering DR context. */ 2070 /* Pointer to the GENEVE TLV options. */ 2071 struct mlx5_geneve_tlv_options *tlv_options; 2072 /* HW steering queue polling mechanism job descriptor LIFO. */ 2073 uint32_t hws_strict_queue:1; 2074 /**< Whether all operations strictly happen on the same HWS queue. */ 2075 uint32_t hws_age_req:1; /**< Whether this port has AGE indexed pool. */ 2076 struct mlx5_hw_q *hw_q; 2077 /* HW steering rte flow table list header. */ 2078 LIST_HEAD(flow_hw_tbl, rte_flow_template_table) flow_hw_tbl; 2079 /* HW steering rte flow group list header */ 2080 LIST_HEAD(flow_hw_grp, mlx5_flow_group) flow_hw_grp; 2081 struct mlx5dr_action *hw_push_vlan[MLX5DR_TABLE_TYPE_MAX]; 2082 struct mlx5dr_action *hw_pop_vlan[MLX5DR_TABLE_TYPE_MAX]; 2083 struct mlx5dr_action **hw_vport; 2084 /* HW steering global drop action. */ 2085 struct mlx5dr_action *hw_drop[2]; 2086 /* HW steering global tag action. */ 2087 struct mlx5dr_action *hw_tag[2]; 2088 /* HW steering global default miss action. */ 2089 struct mlx5dr_action *hw_def_miss; 2090 /* HW steering global send to kernel action. */ 2091 struct mlx5dr_action *hw_send_to_kernel[MLX5DR_TABLE_TYPE_MAX]; 2092 /* HW steering create ongoing rte flow table list header. */ 2093 LIST_HEAD(flow_hw_tbl_ongo, rte_flow_template_table) flow_hw_tbl_ongo; 2094 struct mlx5_indexed_pool *acts_ipool; /* Action data indexed pool. */ 2095 struct mlx5_aso_ct_pools_mng *ct_mng; 2096 /* Management data for ASO connection tracking. */ 2097 struct mlx5_aso_ct_pool *hws_ctpool; /* HW steering's CT pool. */ 2098 struct mlx5_aso_mtr_pool *hws_mpool; /* HW steering's Meter pool. */ 2099 struct mlx5_flow_hw_ctrl_rx *hw_ctrl_rx; 2100 /**< HW steering templates used to create control flow rules. */ 2101 2102 struct rte_flow_actions_template *action_template_drop[MLX5DR_TABLE_TYPE_MAX]; 2103 2104 /* 2105 * The NAT64 action can be shared among matchers per domain. 2106 * [0]: RTE_FLOW_NAT64_6TO4, [1]: RTE_FLOW_NAT64_4TO6 2107 * Todo: consider to add *_MAX macro. 2108 */ 2109 struct mlx5dr_action *action_nat64[MLX5DR_TABLE_TYPE_MAX][2]; 2110 struct mlx5_indexed_pool *ptype_rss_groups; 2111 #endif 2112 struct rte_eth_dev *shared_host; /* Host device for HW steering. */ 2113 RTE_ATOMIC(uint16_t) shared_refcnt; /* HW steering host reference counter. */ 2114 }; 2115 2116 static __rte_always_inline bool 2117 mlx5_hws_active(const struct rte_eth_dev *dev) 2118 { 2119 #if defined(HAVE_MLX5_HWS_SUPPORT) 2120 const struct mlx5_priv *priv = dev->data->dev_private; 2121 2122 return priv->sh->config.dv_flow_en == 2; 2123 #else 2124 RTE_SET_USED(dev); 2125 return false; 2126 #endif 2127 } 2128 2129 #define PORT_ID(priv) ((priv)->dev_data->port_id) 2130 #define ETH_DEV(priv) (&rte_eth_devices[PORT_ID(priv)]) 2131 #define CTRL_QUEUE_ID(priv) ((priv)->nb_queue - 1) 2132 2133 struct rte_hairpin_peer_info { 2134 uint32_t qp_id; 2135 uint32_t vhca_id; 2136 uint16_t peer_q; 2137 uint16_t tx_explicit; 2138 uint16_t manual_bind; 2139 }; 2140 2141 #define BUF_SIZE 1024 2142 enum dr_dump_rec_type { 2143 DR_DUMP_REC_TYPE_PMD_PKT_REFORMAT = 4410, 2144 DR_DUMP_REC_TYPE_PMD_MODIFY_HDR = 4420, 2145 DR_DUMP_REC_TYPE_PMD_COUNTER = 4430, 2146 }; 2147 2148 #if defined(HAVE_MLX5_HWS_SUPPORT) 2149 static __rte_always_inline struct mlx5_hw_q_job * 2150 flow_hw_job_get(struct mlx5_priv *priv, uint32_t queue) 2151 { 2152 MLX5_ASSERT(priv->hw_q[queue].job_idx <= priv->hw_q[queue].size); 2153 return priv->hw_q[queue].job_idx ? 2154 priv->hw_q[queue].job[--priv->hw_q[queue].job_idx] : NULL; 2155 } 2156 2157 static __rte_always_inline void 2158 flow_hw_job_put(struct mlx5_priv *priv, struct mlx5_hw_q_job *job, uint32_t queue) 2159 { 2160 MLX5_ASSERT(priv->hw_q[queue].job_idx < priv->hw_q[queue].size); 2161 priv->hw_q[queue].job[priv->hw_q[queue].job_idx++] = job; 2162 } 2163 2164 struct mlx5_hw_q_job * 2165 mlx5_flow_action_job_init(struct mlx5_priv *priv, uint32_t queue, 2166 const struct rte_flow_action_handle *handle, 2167 void *user_data, void *query_data, 2168 enum mlx5_hw_job_type type, 2169 struct rte_flow_error *error); 2170 #endif 2171 2172 /** 2173 * Indicates whether HW objects operations can be created by DevX. 2174 * 2175 * This function is used for both: 2176 * Before creation - deciding whether to create HW objects operations by DevX. 2177 * After creation - indicator if HW objects operations were created by DevX. 2178 * 2179 * @param sh 2180 * Pointer to shared device context. 2181 * 2182 * @return 2183 * True if HW objects were created by DevX, False otherwise. 2184 */ 2185 static inline bool 2186 mlx5_devx_obj_ops_en(struct mlx5_dev_ctx_shared *sh) 2187 { 2188 /* 2189 * When advanced DR API is available and DV flow is supported and 2190 * DevX is supported, HW objects operations are created by DevX. 2191 */ 2192 return (sh->cdev->config.devx && sh->config.dv_flow_en && 2193 sh->dev_cap.dest_tir); 2194 } 2195 2196 /** 2197 * Check if the port is either MPESW physical device or a representor port. 2198 * 2199 * @param priv 2200 * Pointer to port's private data. 2201 * 2202 * @return 2203 * True if the port is a physical device or representor in MPESW setup. 2204 * False otherwise or MPESW was not configured. 2205 */ 2206 static inline bool 2207 mlx5_is_port_on_mpesw_device(struct mlx5_priv *priv) 2208 { 2209 return priv->mpesw_port >= 0; 2210 } 2211 2212 /* mlx5.c */ 2213 2214 int mlx5_getenv_int(const char *); 2215 int mlx5_proc_priv_init(struct rte_eth_dev *dev); 2216 void mlx5_proc_priv_uninit(struct rte_eth_dev *dev); 2217 int mlx5_udp_tunnel_port_add(struct rte_eth_dev *dev, 2218 struct rte_eth_udp_tunnel *udp_tunnel); 2219 uint16_t mlx5_eth_find_next(uint16_t port_id, struct rte_device *odev); 2220 int mlx5_dev_close(struct rte_eth_dev *dev); 2221 int mlx5_net_remove(struct mlx5_common_device *cdev); 2222 bool mlx5_is_hpf(struct rte_eth_dev *dev); 2223 bool mlx5_is_sf_repr(struct rte_eth_dev *dev); 2224 void mlx5_age_event_prepare(struct mlx5_dev_ctx_shared *sh); 2225 int mlx5_lwm_setup(struct mlx5_priv *priv); 2226 void mlx5_lwm_unset(struct mlx5_dev_ctx_shared *sh); 2227 2228 /* Macro to iterate over all valid ports for mlx5 driver. */ 2229 #define MLX5_ETH_FOREACH_DEV(port_id, dev) \ 2230 for (port_id = mlx5_eth_find_next(0, dev); \ 2231 port_id < RTE_MAX_ETHPORTS; \ 2232 port_id = mlx5_eth_find_next(port_id + 1, dev)) 2233 void mlx5_rt_timestamp_config(struct mlx5_dev_ctx_shared *sh, 2234 struct mlx5_hca_attr *hca_attr); 2235 struct mlx5_dev_ctx_shared * 2236 mlx5_alloc_shared_dev_ctx(const struct mlx5_dev_spawn_data *spawn, 2237 struct mlx5_kvargs_ctrl *mkvlist); 2238 void mlx5_free_shared_dev_ctx(struct mlx5_dev_ctx_shared *sh); 2239 int mlx5_dev_ctx_shared_mempool_subscribe(struct rte_eth_dev *dev); 2240 void mlx5_free_table_hash_list(struct mlx5_priv *priv); 2241 int mlx5_alloc_table_hash_list(struct mlx5_priv *priv); 2242 void mlx5_set_min_inline(struct mlx5_priv *priv); 2243 void mlx5_set_metadata_mask(struct rte_eth_dev *dev); 2244 int mlx5_probe_again_args_validate(struct mlx5_common_device *cdev, 2245 struct mlx5_kvargs_ctrl *mkvlist); 2246 int mlx5_port_args_config(struct mlx5_priv *priv, 2247 struct mlx5_kvargs_ctrl *mkvlist, 2248 struct mlx5_port_config *config); 2249 void mlx5_port_args_set_used(const char *name, uint16_t port_id, 2250 struct mlx5_kvargs_ctrl *mkvlist); 2251 bool mlx5_flex_parser_ecpri_exist(struct rte_eth_dev *dev); 2252 int mlx5_flex_parser_ecpri_alloc(struct rte_eth_dev *dev); 2253 void mlx5_flow_counter_mode_config(struct rte_eth_dev *dev); 2254 int mlx5_flow_aso_age_mng_init(struct mlx5_dev_ctx_shared *sh); 2255 int mlx5_aso_flow_mtrs_mng_init(struct mlx5_dev_ctx_shared *sh); 2256 int mlx5_flow_aso_ct_mng_init(struct mlx5_dev_ctx_shared *sh); 2257 struct mlx5_physical_device * 2258 mlx5_get_locked_physical_device(struct mlx5_priv *priv); 2259 void mlx5_unlock_physical_device(void); 2260 2261 /* mlx5_ethdev.c */ 2262 2263 int mlx5_dev_configure(struct rte_eth_dev *dev); 2264 int mlx5_representor_info_get(struct rte_eth_dev *dev, 2265 struct rte_eth_representor_info *info); 2266 #define MLX5_REPRESENTOR_ID(pf, type, repr) \ 2267 (((pf) << 14) + ((type) << 12) + ((repr) & 0xfff)) 2268 #define MLX5_REPRESENTOR_REPR(repr_id) \ 2269 ((repr_id) & 0xfff) 2270 #define MLX5_REPRESENTOR_TYPE(repr_id) \ 2271 (((repr_id) >> 12) & 3) 2272 uint16_t mlx5_representor_id_encode(const struct mlx5_switch_info *info, 2273 enum rte_eth_representor_type hpf_type); 2274 int mlx5_dev_infos_get(struct rte_eth_dev *dev, struct rte_eth_dev_info *info); 2275 int mlx5_fw_version_get(struct rte_eth_dev *dev, char *fw_ver, size_t fw_size); 2276 const uint32_t *mlx5_dev_supported_ptypes_get(struct rte_eth_dev *dev, 2277 size_t *no_of_elements); 2278 int mlx5_dev_set_mtu(struct rte_eth_dev *dev, uint16_t mtu); 2279 int mlx5_hairpin_cap_get(struct rte_eth_dev *dev, 2280 struct rte_eth_hairpin_cap *cap); 2281 eth_rx_burst_t mlx5_select_rx_function(struct rte_eth_dev *dev); 2282 struct mlx5_priv *mlx5_port_to_eswitch_info(uint16_t port, bool valid); 2283 struct mlx5_priv *mlx5_dev_to_eswitch_info(struct rte_eth_dev *dev); 2284 int mlx5_dev_configure_rss_reta(struct rte_eth_dev *dev); 2285 uint64_t mlx5_get_restore_flags(struct rte_eth_dev *dev, 2286 enum rte_eth_dev_operation op); 2287 2288 /* mlx5_ethdev_os.c */ 2289 2290 int mlx5_get_ifname(const struct rte_eth_dev *dev, 2291 char (*ifname)[MLX5_NAMESIZE]); 2292 unsigned int mlx5_ifindex(const struct rte_eth_dev *dev); 2293 int mlx5_get_mac(struct rte_eth_dev *dev, uint8_t (*mac)[RTE_ETHER_ADDR_LEN]); 2294 int mlx5_get_mtu(struct rte_eth_dev *dev, uint16_t *mtu); 2295 int mlx5_set_mtu(struct rte_eth_dev *dev, uint16_t mtu); 2296 int mlx5_read_clock(struct rte_eth_dev *dev, uint64_t *clock); 2297 int mlx5_link_update(struct rte_eth_dev *dev, int wait_to_complete); 2298 int mlx5_dev_get_flow_ctrl(struct rte_eth_dev *dev, 2299 struct rte_eth_fc_conf *fc_conf); 2300 int mlx5_dev_set_flow_ctrl(struct rte_eth_dev *dev, 2301 struct rte_eth_fc_conf *fc_conf); 2302 void mlx5_dev_interrupt_handler(void *arg); 2303 void mlx5_dev_interrupt_handler_devx(void *arg); 2304 void mlx5_dev_interrupt_handler_nl(void *arg); 2305 int mlx5_set_link_down(struct rte_eth_dev *dev); 2306 int mlx5_set_link_up(struct rte_eth_dev *dev); 2307 int mlx5_is_removed(struct rte_eth_dev *dev); 2308 int mlx5_sysfs_switch_info(unsigned int ifindex, 2309 struct mlx5_switch_info *info); 2310 void mlx5_translate_port_name(const char *port_name_in, 2311 struct mlx5_switch_info *port_info_out); 2312 int mlx5_sysfs_bond_info(unsigned int pf_ifindex, unsigned int *ifindex, 2313 char *ifname); 2314 int mlx5_get_module_info(struct rte_eth_dev *dev, 2315 struct rte_eth_dev_module_info *modinfo); 2316 int mlx5_get_module_eeprom(struct rte_eth_dev *dev, 2317 struct rte_dev_eeprom_info *info); 2318 int mlx5_os_read_dev_stat(struct mlx5_priv *priv, 2319 const char *ctr_name, uint64_t *stat); 2320 int mlx5_os_read_dev_counters(struct rte_eth_dev *dev, bool bond_master, uint64_t *stats); 2321 int mlx5_os_get_stats_n(struct rte_eth_dev *dev, bool bond_master, 2322 uint16_t *n_stats, uint16_t *n_stats_sec); 2323 void mlx5_os_stats_init(struct rte_eth_dev *dev); 2324 int mlx5_get_flag_dropless_rq(struct rte_eth_dev *dev); 2325 2326 /* mlx5_mac.c */ 2327 2328 void mlx5_mac_addr_remove(struct rte_eth_dev *dev, uint32_t index); 2329 int mlx5_mac_addr_add(struct rte_eth_dev *dev, struct rte_ether_addr *mac, 2330 uint32_t index, uint32_t vmdq); 2331 int mlx5_mac_addr_set(struct rte_eth_dev *dev, struct rte_ether_addr *mac_addr); 2332 int mlx5_set_mc_addr_list(struct rte_eth_dev *dev, 2333 struct rte_ether_addr *mc_addr_set, 2334 uint32_t nb_mc_addr); 2335 2336 /* mlx5_rss.c */ 2337 2338 int mlx5_rss_hash_update(struct rte_eth_dev *dev, 2339 struct rte_eth_rss_conf *rss_conf); 2340 int mlx5_rss_hash_conf_get(struct rte_eth_dev *dev, 2341 struct rte_eth_rss_conf *rss_conf); 2342 int mlx5_rss_reta_index_resize(struct rte_eth_dev *dev, unsigned int reta_size); 2343 int mlx5_dev_rss_reta_query(struct rte_eth_dev *dev, 2344 struct rte_eth_rss_reta_entry64 *reta_conf, 2345 uint16_t reta_size); 2346 int mlx5_dev_rss_reta_update(struct rte_eth_dev *dev, 2347 struct rte_eth_rss_reta_entry64 *reta_conf, 2348 uint16_t reta_size); 2349 2350 /* mlx5_rxmode.c */ 2351 2352 int mlx5_promiscuous_enable(struct rte_eth_dev *dev); 2353 int mlx5_promiscuous_disable(struct rte_eth_dev *dev); 2354 int mlx5_allmulticast_enable(struct rte_eth_dev *dev); 2355 int mlx5_allmulticast_disable(struct rte_eth_dev *dev); 2356 2357 /* mlx5_stats.c */ 2358 2359 int mlx5_stats_get(struct rte_eth_dev *dev, struct rte_eth_stats *stats); 2360 int mlx5_stats_reset(struct rte_eth_dev *dev); 2361 int mlx5_xstats_get(struct rte_eth_dev *dev, struct rte_eth_xstat *stats, 2362 unsigned int n); 2363 int mlx5_xstats_reset(struct rte_eth_dev *dev); 2364 int mlx5_xstats_get_names(struct rte_eth_dev *dev __rte_unused, 2365 struct rte_eth_xstat_name *xstats_names, 2366 unsigned int n); 2367 2368 /* mlx5_vlan.c */ 2369 2370 int mlx5_vlan_filter_set(struct rte_eth_dev *dev, uint16_t vlan_id, int on); 2371 void mlx5_vlan_strip_queue_set(struct rte_eth_dev *dev, uint16_t queue, int on); 2372 int mlx5_vlan_offload_set(struct rte_eth_dev *dev, int mask); 2373 2374 /* mlx5_vlan_os.c */ 2375 2376 void mlx5_vlan_vmwa_exit(void *ctx); 2377 void mlx5_vlan_vmwa_release(struct rte_eth_dev *dev, 2378 struct mlx5_vf_vlan *vf_vlan); 2379 void mlx5_vlan_vmwa_acquire(struct rte_eth_dev *dev, 2380 struct mlx5_vf_vlan *vf_vlan); 2381 void *mlx5_vlan_vmwa_init(struct rte_eth_dev *dev, uint32_t ifindex); 2382 2383 /* mlx5_trigger.c */ 2384 2385 int mlx5_dev_start(struct rte_eth_dev *dev); 2386 int mlx5_dev_stop(struct rte_eth_dev *dev); 2387 int mlx5_traffic_enable(struct rte_eth_dev *dev); 2388 void mlx5_traffic_disable(struct rte_eth_dev *dev); 2389 int mlx5_traffic_restart(struct rte_eth_dev *dev); 2390 int mlx5_hairpin_queue_peer_update(struct rte_eth_dev *dev, uint16_t peer_queue, 2391 struct rte_hairpin_peer_info *current_info, 2392 struct rte_hairpin_peer_info *peer_info, 2393 uint32_t direction); 2394 int mlx5_hairpin_queue_peer_bind(struct rte_eth_dev *dev, uint16_t cur_queue, 2395 struct rte_hairpin_peer_info *peer_info, 2396 uint32_t direction); 2397 int mlx5_hairpin_queue_peer_unbind(struct rte_eth_dev *dev, uint16_t cur_queue, 2398 uint32_t direction); 2399 int mlx5_hairpin_bind(struct rte_eth_dev *dev, uint16_t rx_port); 2400 int mlx5_hairpin_unbind(struct rte_eth_dev *dev, uint16_t rx_port); 2401 int mlx5_hairpin_get_peer_ports(struct rte_eth_dev *dev, uint16_t *peer_ports, 2402 size_t len, uint32_t direction); 2403 int mlx5_traffic_mac_add(struct rte_eth_dev *dev, const struct rte_ether_addr *addr); 2404 int mlx5_traffic_mac_remove(struct rte_eth_dev *dev, const struct rte_ether_addr *addr); 2405 int mlx5_traffic_vlan_add(struct rte_eth_dev *dev, const uint16_t vid); 2406 int mlx5_traffic_vlan_remove(struct rte_eth_dev *dev, const uint16_t vid); 2407 2408 /* mlx5_flow.c */ 2409 2410 int mlx5_flow_discover_mreg_c(struct rte_eth_dev *eth_dev); 2411 bool mlx5_flow_ext_mreg_supported(struct rte_eth_dev *dev); 2412 void mlx5_flow_print(struct rte_flow *flow); 2413 int mlx5_flow_validate(struct rte_eth_dev *dev, 2414 const struct rte_flow_attr *attr, 2415 const struct rte_flow_item items[], 2416 const struct rte_flow_action actions[], 2417 struct rte_flow_error *error); 2418 uintptr_t 2419 mlx5_flow_list_create(struct rte_eth_dev *dev, enum mlx5_flow_type type, 2420 const struct rte_flow_attr *attr, 2421 const struct rte_flow_item items[], 2422 const struct rte_flow_action actions[], 2423 bool external, struct rte_flow_error *error); 2424 void 2425 mlx5_flow_list_destroy(struct rte_eth_dev *dev, enum mlx5_flow_type type, 2426 uintptr_t flow_idx); 2427 struct rte_flow *mlx5_flow_create(struct rte_eth_dev *dev, 2428 const struct rte_flow_attr *attr, 2429 const struct rte_flow_item items[], 2430 const struct rte_flow_action actions[], 2431 struct rte_flow_error *error); 2432 int mlx5_flow_destroy(struct rte_eth_dev *dev, struct rte_flow *flow, 2433 struct rte_flow_error *error); 2434 void mlx5_flow_list_flush(struct rte_eth_dev *dev, enum mlx5_flow_type type, 2435 bool active); 2436 int mlx5_flow_flush(struct rte_eth_dev *dev, struct rte_flow_error *error); 2437 int mlx5_flow_query(struct rte_eth_dev *dev, struct rte_flow *flow, 2438 const struct rte_flow_action *action, void *data, 2439 struct rte_flow_error *error); 2440 int mlx5_flow_isolate(struct rte_eth_dev *dev, int enable, 2441 struct rte_flow_error *error); 2442 int mlx5_flow_ops_get(struct rte_eth_dev *dev, const struct rte_flow_ops **ops); 2443 int mlx5_flow_start_default(struct rte_eth_dev *dev); 2444 void mlx5_flow_stop_default(struct rte_eth_dev *dev); 2445 int mlx5_flow_verify(struct rte_eth_dev *dev); 2446 int mlx5_ctrl_flow_source_queue(struct rte_eth_dev *dev, uint32_t sq_num); 2447 int mlx5_ctrl_flow_vlan(struct rte_eth_dev *dev, 2448 struct rte_flow_item_eth *eth_spec, 2449 struct rte_flow_item_eth *eth_mask, 2450 struct rte_flow_item_vlan *vlan_spec, 2451 struct rte_flow_item_vlan *vlan_mask); 2452 int mlx5_ctrl_flow(struct rte_eth_dev *dev, 2453 struct rte_flow_item_eth *eth_spec, 2454 struct rte_flow_item_eth *eth_mask); 2455 int mlx5_flow_lacp_miss(struct rte_eth_dev *dev); 2456 struct rte_flow *mlx5_flow_create_esw_table_zero_flow(struct rte_eth_dev *dev); 2457 uint32_t mlx5_flow_create_devx_sq_miss_flow(struct rte_eth_dev *dev, 2458 uint32_t sq_num); 2459 void mlx5_flow_async_pool_query_handle(struct mlx5_dev_ctx_shared *sh, 2460 uint64_t async_id, int status); 2461 void mlx5_set_query_alarm(struct mlx5_dev_ctx_shared *sh); 2462 void mlx5_flow_query_alarm(void *arg); 2463 uint32_t mlx5_counter_alloc(struct rte_eth_dev *dev); 2464 void mlx5_counter_free(struct rte_eth_dev *dev, uint32_t cnt); 2465 int mlx5_counter_query(struct rte_eth_dev *dev, uint32_t cnt, 2466 bool clear, uint64_t *pkts, uint64_t *bytes, void **action); 2467 int mlx5_flow_dev_dump(struct rte_eth_dev *dev, struct rte_flow *flow, 2468 FILE *file, struct rte_flow_error *error); 2469 int save_dump_file(const unsigned char *data, uint32_t size, 2470 uint32_t type, uint64_t id, void *arg, FILE *file); 2471 int mlx5_flow_query_counter(struct rte_eth_dev *dev, struct rte_flow *flow, 2472 struct rte_flow_query_count *count, struct rte_flow_error *error); 2473 #ifdef HAVE_IBV_FLOW_DV_SUPPORT 2474 int mlx5_flow_dev_dump_ipool(struct rte_eth_dev *dev, struct rte_flow *flow, 2475 FILE *file, struct rte_flow_error *error); 2476 #endif 2477 int mlx5_flow_rx_metadata_negotiate(struct rte_eth_dev *dev, 2478 uint64_t *features); 2479 void mlx5_flow_rxq_dynf_set(struct rte_eth_dev *dev); 2480 int mlx5_flow_get_aged_flows(struct rte_eth_dev *dev, void **contexts, 2481 uint32_t nb_contexts, struct rte_flow_error *error); 2482 int mlx5_validate_action_ct(struct rte_eth_dev *dev, 2483 const struct rte_flow_action_conntrack *conntrack, 2484 struct rte_flow_error *error); 2485 2486 int mlx5_flow_get_q_aged_flows(struct rte_eth_dev *dev, uint32_t queue_id, 2487 void **contexts, uint32_t nb_contexts, 2488 struct rte_flow_error *error); 2489 2490 /* mlx5_mp_os.c */ 2491 2492 int mlx5_mp_os_primary_handle(const struct rte_mp_msg *mp_msg, 2493 const void *peer); 2494 int mlx5_mp_os_secondary_handle(const struct rte_mp_msg *mp_msg, 2495 const void *peer); 2496 void mlx5_mp_os_req_start_rxtx(struct rte_eth_dev *dev); 2497 void mlx5_mp_os_req_stop_rxtx(struct rte_eth_dev *dev); 2498 int mlx5_mp_os_req_queue_control(struct rte_eth_dev *dev, uint16_t queue_id, 2499 enum mlx5_mp_req_type req_type); 2500 2501 /* mlx5_socket.c */ 2502 2503 int mlx5_pmd_socket_init(void); 2504 void mlx5_pmd_socket_uninit(void); 2505 2506 /* mlx5_flow_meter.c */ 2507 2508 int mlx5_flow_meter_init(struct rte_eth_dev *dev, 2509 uint32_t nb_meters, 2510 uint32_t nb_meter_profiles, 2511 uint32_t nb_meter_policies, 2512 uint32_t nb_queues); 2513 void mlx5_flow_meter_uninit(struct rte_eth_dev *dev); 2514 int mlx5_flow_meter_ops_get(struct rte_eth_dev *dev, void *arg); 2515 struct mlx5_flow_meter_info *mlx5_flow_meter_find(struct mlx5_priv *priv, 2516 uint32_t meter_id, uint32_t *mtr_idx); 2517 struct mlx5_flow_meter_info * 2518 flow_dv_meter_find_by_idx(struct mlx5_priv *priv, uint32_t idx); 2519 int mlx5_flow_meter_attach(struct mlx5_priv *priv, 2520 struct mlx5_flow_meter_info *fm, 2521 const struct rte_flow_attr *attr, 2522 struct rte_flow_error *error); 2523 void mlx5_flow_meter_detach(struct mlx5_priv *priv, 2524 struct mlx5_flow_meter_info *fm); 2525 struct mlx5_flow_meter_policy *mlx5_flow_meter_policy_find 2526 (struct rte_eth_dev *dev, 2527 uint32_t policy_id, 2528 uint32_t *policy_idx); 2529 struct mlx5_flow_meter_info * 2530 mlx5_flow_meter_hierarchy_next_meter(struct mlx5_priv *priv, 2531 struct mlx5_flow_meter_policy *policy, 2532 uint32_t *mtr_idx); 2533 struct mlx5_flow_meter_policy * 2534 mlx5_flow_meter_hierarchy_get_final_policy(struct rte_eth_dev *dev, 2535 struct mlx5_flow_meter_policy *policy); 2536 int mlx5_flow_meter_flush(struct rte_eth_dev *dev, 2537 struct rte_mtr_error *error); 2538 void mlx5_flow_meter_rxq_flush(struct rte_eth_dev *dev); 2539 uint32_t mlx5_flow_mtr_max_get(struct mlx5_priv *priv); 2540 2541 /* mlx5_os.c */ 2542 2543 struct rte_pci_driver; 2544 int mlx5_os_capabilities_prepare(struct mlx5_dev_ctx_shared *sh); 2545 void mlx5_os_free_shared_dr(struct mlx5_priv *priv); 2546 int mlx5_os_net_probe(struct mlx5_common_device *cdev, 2547 struct mlx5_kvargs_ctrl *mkvlist); 2548 void mlx5_os_dev_shared_handler_install(struct mlx5_dev_ctx_shared *sh); 2549 void mlx5_os_dev_shared_handler_uninstall(struct mlx5_dev_ctx_shared *sh); 2550 void mlx5_os_mac_addr_remove(struct rte_eth_dev *dev, uint32_t index); 2551 int mlx5_os_mac_addr_add(struct rte_eth_dev *dev, struct rte_ether_addr *mac, 2552 uint32_t index); 2553 int mlx5_os_vf_mac_addr_modify(struct mlx5_priv *priv, unsigned int iface_idx, 2554 struct rte_ether_addr *mac_addr, 2555 int vf_index); 2556 int mlx5_os_set_promisc(struct rte_eth_dev *dev, int enable); 2557 int mlx5_os_set_allmulti(struct rte_eth_dev *dev, int enable); 2558 int mlx5_os_set_nonblock_channel_fd(int fd); 2559 void mlx5_os_mac_addr_flush(struct rte_eth_dev *dev); 2560 void mlx5_os_net_cleanup(void); 2561 2562 /* mlx5_txpp.c */ 2563 2564 int mlx5_txpp_start(struct rte_eth_dev *dev); 2565 void mlx5_txpp_stop(struct rte_eth_dev *dev); 2566 int mlx5_txpp_read_clock(struct rte_eth_dev *dev, uint64_t *timestamp); 2567 int mlx5_txpp_xstats_get(struct rte_eth_dev *dev, 2568 struct rte_eth_xstat *stats, 2569 unsigned int n, unsigned int n_used); 2570 int mlx5_txpp_xstats_reset(struct rte_eth_dev *dev); 2571 int mlx5_txpp_xstats_get_names(struct rte_eth_dev *dev, 2572 struct rte_eth_xstat_name *xstats_names, 2573 unsigned int n, unsigned int n_used); 2574 void mlx5_txpp_interrupt_handler(void *cb_arg); 2575 int mlx5_txpp_map_hca_bar(struct rte_eth_dev *dev); 2576 void mlx5_txpp_unmap_hca_bar(struct rte_eth_dev *dev); 2577 2578 /* mlx5_rxtx.c */ 2579 2580 eth_tx_burst_t mlx5_select_tx_function(struct rte_eth_dev *dev); 2581 2582 /* mlx5_flow_aso.c */ 2583 2584 int mlx5_aso_mtr_queue_init(struct mlx5_dev_ctx_shared *sh, 2585 struct mlx5_aso_mtr_pool *hws_pool, 2586 struct mlx5_aso_mtr_pools_mng *pool_mng, 2587 uint32_t nb_queues); 2588 void mlx5_aso_mtr_queue_uninit(struct mlx5_dev_ctx_shared *sh, 2589 struct mlx5_aso_mtr_pool *hws_pool, 2590 struct mlx5_aso_mtr_pools_mng *pool_mng); 2591 int mlx5_aso_queue_init(struct mlx5_dev_ctx_shared *sh, 2592 enum mlx5_access_aso_opc_mod aso_opc_mode, 2593 uint32_t nb_queues); 2594 int mlx5_aso_flow_hit_queue_poll_start(struct mlx5_dev_ctx_shared *sh); 2595 int mlx5_aso_flow_hit_queue_poll_stop(struct mlx5_dev_ctx_shared *sh); 2596 void mlx5_aso_queue_uninit(struct mlx5_dev_ctx_shared *sh, 2597 enum mlx5_access_aso_opc_mod aso_opc_mod); 2598 int mlx5_aso_meter_update_by_wqe(struct mlx5_priv *priv, uint32_t queue, 2599 struct mlx5_aso_mtr *mtr, 2600 struct mlx5_mtr_bulk *bulk, 2601 struct mlx5_hw_q_job *job, bool push); 2602 int mlx5_aso_mtr_wait(struct mlx5_priv *priv, 2603 struct mlx5_aso_mtr *mtr, bool is_tmpl_api); 2604 int mlx5_aso_ct_update_by_wqe(struct mlx5_dev_ctx_shared *sh, uint32_t queue, 2605 struct mlx5_aso_ct_action *ct, 2606 const struct rte_flow_action_conntrack *profile, 2607 void *user_data, 2608 bool push); 2609 int mlx5_aso_ct_wait_ready(struct mlx5_dev_ctx_shared *sh, uint32_t queue, 2610 struct mlx5_aso_ct_action *ct); 2611 int mlx5_aso_ct_query_by_wqe(struct mlx5_dev_ctx_shared *sh, uint32_t queue, 2612 struct mlx5_aso_ct_action *ct, 2613 struct rte_flow_action_conntrack *profile, 2614 void *user_data, bool push); 2615 int mlx5_aso_ct_available(struct mlx5_dev_ctx_shared *sh, uint32_t queue, 2616 struct mlx5_aso_ct_action *ct); 2617 uint32_t 2618 mlx5_get_supported_sw_parsing_offloads(const struct mlx5_hca_attr *attr); 2619 uint32_t 2620 mlx5_get_supported_tunneling_offloads(const struct mlx5_hca_attr *attr); 2621 2622 void mlx5_aso_ct_obj_analyze(struct rte_flow_action_conntrack *profile, 2623 char *wdata); 2624 void mlx5_aso_push_wqe(struct mlx5_dev_ctx_shared *sh, 2625 struct mlx5_aso_sq *sq); 2626 int mlx5_aso_pull_completion(struct mlx5_aso_sq *sq, 2627 struct rte_flow_op_result res[], 2628 uint16_t n_res); 2629 int mlx5_aso_cnt_queue_init(struct mlx5_dev_ctx_shared *sh); 2630 void mlx5_aso_cnt_queue_uninit(struct mlx5_dev_ctx_shared *sh); 2631 int mlx5_aso_cnt_query(struct mlx5_dev_ctx_shared *sh, 2632 struct mlx5_hws_cnt_pool *cpool); 2633 int mlx5_aso_ct_queue_init(struct mlx5_dev_ctx_shared *sh, 2634 struct mlx5_aso_ct_pools_mng *ct_mng, 2635 uint32_t nb_queues); 2636 int mlx5_aso_ct_queue_uninit(struct mlx5_dev_ctx_shared *sh, 2637 struct mlx5_aso_ct_pools_mng *ct_mng); 2638 int 2639 mlx5_aso_sq_create(struct mlx5_common_device *cdev, struct mlx5_aso_sq *sq, 2640 void *uar, uint16_t log_desc_n); 2641 void 2642 mlx5_aso_destroy_sq(struct mlx5_aso_sq *sq); 2643 void 2644 mlx5_aso_mtr_init_sq(struct mlx5_aso_sq *sq); 2645 void 2646 mlx5_aso_cqe_err_handle(struct mlx5_aso_sq *sq); 2647 2648 /* mlx5_flow_flex.c */ 2649 2650 struct rte_flow_item_flex_handle * 2651 flow_dv_item_create(struct rte_eth_dev *dev, 2652 const struct rte_flow_item_flex_conf *conf, 2653 struct rte_flow_error *error); 2654 int flow_dv_item_release(struct rte_eth_dev *dev, 2655 const struct rte_flow_item_flex_handle *flex_handle, 2656 struct rte_flow_error *error); 2657 int mlx5_flex_item_port_init(struct rte_eth_dev *dev); 2658 void mlx5_flex_item_port_cleanup(struct rte_eth_dev *dev); 2659 void mlx5_flex_flow_translate_item(struct rte_eth_dev *dev, void *matcher, 2660 void *key, const struct rte_flow_item *item, 2661 bool is_inner); 2662 int mlx5_flex_get_sample_id(const struct mlx5_flex_item *tp, 2663 uint32_t idx, uint32_t *pos, bool is_inner); 2664 int mlx5_flex_get_parser_value_per_byte_off(const struct rte_flow_item_flex *item, 2665 void *flex, uint32_t byte_off, 2666 bool tunnel, uint32_t *value); 2667 int mlx5_flex_get_tunnel_mode(const struct rte_flow_item *item, 2668 enum rte_flow_item_flex_tunnel_mode *tunnel_mode); 2669 int mlx5_flex_acquire_index(struct rte_eth_dev *dev, 2670 struct rte_flow_item_flex_handle *handle, 2671 bool acquire); 2672 int mlx5_flex_release_index(struct rte_eth_dev *dev, int index); 2673 2674 /* Flex parser list callbacks. */ 2675 struct mlx5_list_entry *mlx5_flex_parser_create_cb(void *list_ctx, void *ctx); 2676 int mlx5_flex_parser_match_cb(void *list_ctx, 2677 struct mlx5_list_entry *iter, void *ctx); 2678 void mlx5_flex_parser_remove_cb(void *list_ctx, struct mlx5_list_entry *entry); 2679 struct mlx5_list_entry *mlx5_flex_parser_clone_cb(void *list_ctx, 2680 struct mlx5_list_entry *entry, 2681 void *ctx); 2682 void mlx5_flex_parser_clone_free_cb(void *tool_ctx, 2683 struct mlx5_list_entry *entry); 2684 2685 int 2686 mlx5_flow_quota_destroy(struct rte_eth_dev *dev); 2687 int 2688 mlx5_flow_quota_init(struct rte_eth_dev *dev, uint32_t nb_quotas); 2689 struct rte_flow_action_handle * 2690 mlx5_quota_alloc(struct rte_eth_dev *dev, uint32_t queue, 2691 const struct rte_flow_action_quota *conf, 2692 struct mlx5_hw_q_job *job, bool push, 2693 struct rte_flow_error *error); 2694 void 2695 mlx5_quota_async_completion(struct rte_eth_dev *dev, uint32_t queue, 2696 struct mlx5_hw_q_job *job); 2697 int 2698 mlx5_quota_query_update(struct rte_eth_dev *dev, uint32_t queue, 2699 struct rte_flow_action_handle *handle, 2700 const struct rte_flow_action *update, 2701 struct rte_flow_query_quota *query, 2702 struct mlx5_hw_q_job *async_job, bool push, 2703 struct rte_flow_error *error); 2704 int mlx5_quota_query(struct rte_eth_dev *dev, uint32_t queue, 2705 const struct rte_flow_action_handle *handle, 2706 struct rte_flow_query_quota *query, 2707 struct mlx5_hw_q_job *async_job, bool push, 2708 struct rte_flow_error *error); 2709 2710 int mlx5_alloc_srh_flex_parser(struct rte_eth_dev *dev); 2711 2712 void mlx5_free_srh_flex_parser(struct rte_eth_dev *dev); 2713 2714 /* mlx5_flow_hw.c */ 2715 struct rte_pmd_mlx5_host_action; 2716 2717 struct mlx5dr_action * 2718 mlx5_flow_hw_get_dr_action(struct rte_eth_dev *dev, 2719 struct rte_pmd_mlx5_host_action *action, 2720 void **release_data); 2721 2722 void 2723 mlx5_flow_hw_put_dr_action(struct rte_eth_dev *dev, 2724 enum rte_flow_action_type type, 2725 void *release_data); 2726 2727 bool 2728 mlx5_hw_ctx_validate(const struct rte_eth_dev *dev, 2729 struct rte_flow_error *error); 2730 2731 #endif /* RTE_PMD_MLX5_H_ */ 2732