1 /* SPDX-License-Identifier: BSD-3-Clause 2 * Copyright 2015 6WIND S.A. 3 * Copyright 2015 Mellanox Technologies, Ltd 4 */ 5 6 #ifndef RTE_PMD_MLX5_H_ 7 #define RTE_PMD_MLX5_H_ 8 9 #include <stddef.h> 10 #include <stdbool.h> 11 #include <stdint.h> 12 #include <limits.h> 13 #include <sys/queue.h> 14 15 #include <rte_pci.h> 16 #include <rte_ether.h> 17 #include <ethdev_driver.h> 18 #include <rte_rwlock.h> 19 #include <rte_interrupts.h> 20 #include <rte_errno.h> 21 #include <rte_flow.h> 22 #include <rte_mtr.h> 23 24 #include <mlx5_glue.h> 25 #include <mlx5_devx_cmds.h> 26 #include <mlx5_prm.h> 27 #include <mlx5_common_mp.h> 28 #include <mlx5_common_mr.h> 29 #include <mlx5_common_devx.h> 30 31 #include "mlx5_defs.h" 32 #include "mlx5_utils.h" 33 #include "mlx5_os.h" 34 #include "mlx5_autoconf.h" 35 36 37 #define MLX5_SH(dev) (((struct mlx5_priv *)(dev)->data->dev_private)->sh) 38 39 enum mlx5_ipool_index { 40 #if defined(HAVE_IBV_FLOW_DV_SUPPORT) || !defined(HAVE_INFINIBAND_VERBS_H) 41 MLX5_IPOOL_DECAP_ENCAP = 0, /* Pool for encap/decap resource. */ 42 MLX5_IPOOL_PUSH_VLAN, /* Pool for push vlan resource. */ 43 MLX5_IPOOL_TAG, /* Pool for tag resource. */ 44 MLX5_IPOOL_PORT_ID, /* Pool for port id resource. */ 45 MLX5_IPOOL_JUMP, /* Pool for jump resource. */ 46 MLX5_IPOOL_SAMPLE, /* Pool for sample resource. */ 47 MLX5_IPOOL_DEST_ARRAY, /* Pool for destination array resource. */ 48 MLX5_IPOOL_TUNNEL_ID, /* Pool for tunnel offload context */ 49 MLX5_IPOOL_TNL_TBL_ID, /* Pool for tunnel table ID. */ 50 #endif 51 MLX5_IPOOL_MTR, /* Pool for meter resource. */ 52 MLX5_IPOOL_MCP, /* Pool for metadata resource. */ 53 MLX5_IPOOL_HRXQ, /* Pool for hrxq resource. */ 54 MLX5_IPOOL_MLX5_FLOW, /* Pool for mlx5 flow handle. */ 55 MLX5_IPOOL_RTE_FLOW, /* Pool for rte_flow. */ 56 MLX5_IPOOL_RSS_EXPANTION_FLOW_ID, /* Pool for Queue/RSS flow ID. */ 57 MLX5_IPOOL_RSS_SHARED_ACTIONS, /* Pool for RSS shared actions. */ 58 MLX5_IPOOL_MTR_POLICY, /* Pool for meter policy resource. */ 59 MLX5_IPOOL_MAX, 60 }; 61 62 /* 63 * There are three reclaim memory mode supported. 64 * 0(none) means no memory reclaim. 65 * 1(light) means only PMD level reclaim. 66 * 2(aggressive) means both PMD and rdma-core level reclaim. 67 */ 68 enum mlx5_reclaim_mem_mode { 69 MLX5_RCM_NONE, /* Don't reclaim memory. */ 70 MLX5_RCM_LIGHT, /* Reclaim PMD level. */ 71 MLX5_RCM_AGGR, /* Reclaim PMD and rdma-core level. */ 72 }; 73 74 /* Hash and cache list callback context. */ 75 struct mlx5_flow_cb_ctx { 76 struct rte_eth_dev *dev; 77 struct rte_flow_error *error; 78 void *data; 79 }; 80 81 /* Device attributes used in mlx5 PMD */ 82 struct mlx5_dev_attr { 83 uint64_t device_cap_flags_ex; 84 int max_qp_wr; 85 int max_sge; 86 int max_cq; 87 int max_qp; 88 int max_cqe; 89 uint32_t max_pd; 90 uint32_t max_mr; 91 uint32_t max_srq; 92 uint32_t max_srq_wr; 93 uint32_t raw_packet_caps; 94 uint32_t max_rwq_indirection_table_size; 95 uint32_t max_tso; 96 uint32_t tso_supported_qpts; 97 uint64_t flags; 98 uint64_t comp_mask; 99 uint32_t sw_parsing_offloads; 100 uint32_t min_single_stride_log_num_of_bytes; 101 uint32_t max_single_stride_log_num_of_bytes; 102 uint32_t min_single_wqe_log_num_of_strides; 103 uint32_t max_single_wqe_log_num_of_strides; 104 uint32_t stride_supported_qpts; 105 uint32_t tunnel_offloads_caps; 106 char fw_ver[64]; 107 }; 108 109 /** Data associated with devices to spawn. */ 110 struct mlx5_dev_spawn_data { 111 uint32_t ifindex; /**< Network interface index. */ 112 uint32_t max_port; /**< Device maximal port index. */ 113 uint32_t phys_port; /**< Device physical port index. */ 114 int pf_bond; /**< bonding device PF index. < 0 - no bonding */ 115 struct mlx5_switch_info info; /**< Switch information. */ 116 void *phys_dev; /**< Associated physical device. */ 117 struct rte_eth_dev *eth_dev; /**< Associated Ethernet device. */ 118 struct rte_pci_device *pci_dev; /**< Backend PCI device. */ 119 struct mlx5_bond_info *bond_info; 120 }; 121 122 /** Data associated with socket messages. */ 123 struct mlx5_flow_dump_req { 124 uint32_t port_id; /**< There are plans in DPDK to extend port_id. */ 125 uint64_t flow_id; 126 } __rte_packed; 127 128 struct mlx5_flow_dump_ack { 129 int rc; /**< Return code. */ 130 }; 131 132 /** Key string for IPC. */ 133 #define MLX5_MP_NAME "net_mlx5_mp" 134 135 136 LIST_HEAD(mlx5_dev_list, mlx5_dev_ctx_shared); 137 138 /* Shared data between primary and secondary processes. */ 139 struct mlx5_shared_data { 140 rte_spinlock_t lock; 141 /* Global spinlock for primary and secondary processes. */ 142 int init_done; /* Whether primary has done initialization. */ 143 unsigned int secondary_cnt; /* Number of secondary processes init'd. */ 144 struct mlx5_dev_list mem_event_cb_list; 145 rte_rwlock_t mem_event_rwlock; 146 }; 147 148 /* Per-process data structure, not visible to other processes. */ 149 struct mlx5_local_data { 150 int init_done; /* Whether a secondary has done initialization. */ 151 }; 152 153 extern struct mlx5_shared_data *mlx5_shared_data; 154 155 /* Dev ops structs */ 156 extern const struct eth_dev_ops mlx5_dev_ops; 157 extern const struct eth_dev_ops mlx5_dev_sec_ops; 158 extern const struct eth_dev_ops mlx5_dev_ops_isolate; 159 160 struct mlx5_counter_ctrl { 161 /* Name of the counter. */ 162 char dpdk_name[RTE_ETH_XSTATS_NAME_SIZE]; 163 /* Name of the counter on the device table. */ 164 char ctr_name[RTE_ETH_XSTATS_NAME_SIZE]; 165 uint32_t dev:1; /**< Nonzero for dev counters. */ 166 }; 167 168 struct mlx5_xstats_ctrl { 169 /* Number of device stats. */ 170 uint16_t stats_n; 171 /* Number of device stats identified by PMD. */ 172 uint16_t mlx5_stats_n; 173 /* Index in the device counters table. */ 174 uint16_t dev_table_idx[MLX5_MAX_XSTATS]; 175 uint64_t base[MLX5_MAX_XSTATS]; 176 uint64_t xstats[MLX5_MAX_XSTATS]; 177 uint64_t hw_stats[MLX5_MAX_XSTATS]; 178 struct mlx5_counter_ctrl info[MLX5_MAX_XSTATS]; 179 }; 180 181 struct mlx5_stats_ctrl { 182 /* Base for imissed counter. */ 183 uint64_t imissed_base; 184 uint64_t imissed; 185 }; 186 187 /* Default PMD specific parameter value. */ 188 #define MLX5_ARG_UNSET (-1) 189 190 #define MLX5_LRO_SUPPORTED(dev) \ 191 (((struct mlx5_priv *)((dev)->data->dev_private))->config.lro.supported) 192 193 /* Maximal size of coalesced segment for LRO is set in chunks of 256 Bytes. */ 194 #define MLX5_LRO_SEG_CHUNK_SIZE 256u 195 196 /* Maximal size of aggregated LRO packet. */ 197 #define MLX5_MAX_LRO_SIZE (UINT8_MAX * MLX5_LRO_SEG_CHUNK_SIZE) 198 199 /* Maximal number of segments to split. */ 200 #define MLX5_MAX_RXQ_NSEG (1u << MLX5_MAX_LOG_RQ_SEGS) 201 202 /* LRO configurations structure. */ 203 struct mlx5_lro_config { 204 uint32_t supported:1; /* Whether LRO is supported. */ 205 uint32_t timeout; /* User configuration. */ 206 }; 207 208 /* 209 * Device configuration structure. 210 * 211 * Merged configuration from: 212 * 213 * - Device capabilities, 214 * - User device parameters disabled features. 215 */ 216 struct mlx5_dev_config { 217 unsigned int hw_csum:1; /* Checksum offload is supported. */ 218 unsigned int hw_vlan_strip:1; /* VLAN stripping is supported. */ 219 unsigned int hw_vlan_insert:1; /* VLAN insertion in WQE is supported. */ 220 unsigned int hw_fcs_strip:1; /* FCS stripping is supported. */ 221 unsigned int hw_padding:1; /* End alignment padding is supported. */ 222 unsigned int vf:1; /* This is a VF. */ 223 unsigned int tunnel_en:1; 224 /* Whether tunnel stateless offloads are supported. */ 225 unsigned int mpls_en:1; /* MPLS over GRE/UDP is enabled. */ 226 unsigned int cqe_comp:1; /* CQE compression is enabled. */ 227 unsigned int cqe_comp_fmt:3; /* CQE compression format. */ 228 unsigned int tso:1; /* Whether TSO is supported. */ 229 unsigned int rx_vec_en:1; /* Rx vector is enabled. */ 230 unsigned int mr_ext_memseg_en:1; 231 /* Whether memseg should be extended for MR creation. */ 232 unsigned int l3_vxlan_en:1; /* Enable L3 VXLAN flow creation. */ 233 unsigned int vf_nl_en:1; /* Enable Netlink requests in VF mode. */ 234 unsigned int dv_esw_en:1; /* Enable E-Switch DV flow. */ 235 unsigned int dv_flow_en:1; /* Enable DV flow. */ 236 unsigned int dv_xmeta_en:2; /* Enable extensive flow metadata. */ 237 unsigned int lacp_by_user:1; 238 /* Enable user to manage LACP traffic. */ 239 unsigned int swp:1; /* Tx generic tunnel checksum and TSO offload. */ 240 unsigned int devx:1; /* Whether devx interface is available or not. */ 241 unsigned int dest_tir:1; /* Whether advanced DR API is available. */ 242 unsigned int reclaim_mode:2; /* Memory reclaim mode. */ 243 unsigned int rt_timestamp:1; /* realtime timestamp format. */ 244 unsigned int sys_mem_en:1; /* The default memory allocator. */ 245 unsigned int decap_en:1; /* Whether decap will be used or not. */ 246 unsigned int dv_miss_info:1; /* restore packet after partial hw miss */ 247 struct { 248 unsigned int enabled:1; /* Whether MPRQ is enabled. */ 249 unsigned int stride_num_n; /* Number of strides. */ 250 unsigned int stride_size_n; /* Size of a stride. */ 251 unsigned int min_stride_size_n; /* Min size of a stride. */ 252 unsigned int max_stride_size_n; /* Max size of a stride. */ 253 unsigned int max_memcpy_len; 254 /* Maximum packet size to memcpy Rx packets. */ 255 unsigned int min_rxqs_num; 256 /* Rx queue count threshold to enable MPRQ. */ 257 } mprq; /* Configurations for Multi-Packet RQ. */ 258 int mps; /* Multi-packet send supported mode. */ 259 int dbnc; /* Skip doorbell register write barrier. */ 260 unsigned int flow_prio; /* Number of flow priorities. */ 261 enum modify_reg flow_mreg_c[MLX5_MREG_C_NUM]; 262 /* Availibility of mreg_c's. */ 263 unsigned int tso_max_payload_sz; /* Maximum TCP payload for TSO. */ 264 unsigned int ind_table_max_size; /* Maximum indirection table size. */ 265 unsigned int max_dump_files_num; /* Maximum dump files per queue. */ 266 unsigned int log_hp_size; /* Single hairpin queue data size in total. */ 267 int txqs_inline; /* Queue number threshold for inlining. */ 268 int txq_inline_min; /* Minimal amount of data bytes to inline. */ 269 int txq_inline_max; /* Max packet size for inlining with SEND. */ 270 int txq_inline_mpw; /* Max packet size for inlining with eMPW. */ 271 int tx_pp; /* Timestamp scheduling granularity in nanoseconds. */ 272 int tx_skew; /* Tx scheduling skew between WQE and data on wire. */ 273 struct mlx5_hca_attr hca_attr; /* HCA attributes. */ 274 struct mlx5_lro_config lro; /* LRO configuration. */ 275 }; 276 277 278 /* Structure for VF VLAN workaround. */ 279 struct mlx5_vf_vlan { 280 uint32_t tag:12; 281 uint32_t created:1; 282 }; 283 284 /* Flow drop context necessary due to Verbs API. */ 285 struct mlx5_drop { 286 struct mlx5_hrxq *hrxq; /* Hash Rx queue queue. */ 287 struct mlx5_rxq_obj *rxq; /* Rx queue object. */ 288 }; 289 290 /* Loopback dummy queue resources required due to Verbs API. */ 291 struct mlx5_lb_ctx { 292 struct ibv_qp *qp; /* QP object. */ 293 void *ibv_cq; /* Completion queue. */ 294 uint16_t refcnt; /* Reference count for representors. */ 295 }; 296 297 #define MLX5_COUNTERS_PER_POOL 512 298 #define MLX5_MAX_PENDING_QUERIES 4 299 #define MLX5_CNT_CONTAINER_RESIZE 64 300 #define MLX5_CNT_SHARED_OFFSET 0x80000000 301 #define IS_LEGACY_SHARED_CNT(cnt) (!!((cnt) & MLX5_CNT_SHARED_OFFSET)) 302 #define IS_BATCH_CNT(cnt) (((cnt) & (MLX5_CNT_SHARED_OFFSET - 1)) >= \ 303 MLX5_CNT_BATCH_OFFSET) 304 #define MLX5_CNT_SIZE (sizeof(struct mlx5_flow_counter)) 305 #define MLX5_AGE_SIZE (sizeof(struct mlx5_age_param)) 306 307 #define MLX5_CNT_LEN(pool) \ 308 (MLX5_CNT_SIZE + \ 309 ((pool)->is_aged ? MLX5_AGE_SIZE : 0)) 310 #define MLX5_POOL_GET_CNT(pool, index) \ 311 ((struct mlx5_flow_counter *) \ 312 ((uint8_t *)((pool) + 1) + (index) * (MLX5_CNT_LEN(pool)))) 313 #define MLX5_CNT_ARRAY_IDX(pool, cnt) \ 314 ((int)(((uint8_t *)(cnt) - (uint8_t *)((pool) + 1)) / \ 315 MLX5_CNT_LEN(pool))) 316 /* 317 * The pool index and offset of counter in the pool array makes up the 318 * counter index. In case the counter is from pool 0 and offset 0, it 319 * should plus 1 to avoid index 0, since 0 means invalid counter index 320 * currently. 321 */ 322 #define MLX5_MAKE_CNT_IDX(pi, offset) \ 323 ((pi) * MLX5_COUNTERS_PER_POOL + (offset) + 1) 324 #define MLX5_CNT_TO_AGE(cnt) \ 325 ((struct mlx5_age_param *)((cnt) + 1)) 326 /* 327 * The maximum single counter is 0x800000 as MLX5_CNT_BATCH_OFFSET 328 * defines. The pool size is 512, pool index should never reach 329 * INT16_MAX. 330 */ 331 #define POOL_IDX_INVALID UINT16_MAX 332 333 /* Age status. */ 334 enum { 335 AGE_FREE, /* Initialized state. */ 336 AGE_CANDIDATE, /* Counter assigned to flows. */ 337 AGE_TMOUT, /* Timeout, wait for rte_flow_get_aged_flows and destroy. */ 338 }; 339 340 enum mlx5_counter_type { 341 MLX5_COUNTER_TYPE_ORIGIN, 342 MLX5_COUNTER_TYPE_AGE, 343 MLX5_COUNTER_TYPE_MAX, 344 }; 345 346 /* Counter age parameter. */ 347 struct mlx5_age_param { 348 uint16_t state; /**< Age state (atomically accessed). */ 349 uint16_t port_id; /**< Port id of the counter. */ 350 uint32_t timeout:24; /**< Aging timeout in seconds. */ 351 uint32_t sec_since_last_hit; 352 /**< Time in seconds since last hit (atomically accessed). */ 353 void *context; /**< Flow counter age context. */ 354 }; 355 356 struct flow_counter_stats { 357 uint64_t hits; 358 uint64_t bytes; 359 }; 360 361 /* Shared counters information for counters. */ 362 struct mlx5_flow_counter_shared { 363 union { 364 uint32_t refcnt; /* Only for shared action management. */ 365 uint32_t id; /* User counter ID for legacy sharing. */ 366 }; 367 }; 368 369 /* Shared counter configuration. */ 370 struct mlx5_shared_counter_conf { 371 struct rte_eth_dev *dev; /* The device shared counter belongs to. */ 372 uint32_t id; /* The shared counter ID. */ 373 }; 374 375 struct mlx5_flow_counter_pool; 376 /* Generic counters information. */ 377 struct mlx5_flow_counter { 378 union { 379 /* 380 * User-defined counter shared info is only used during 381 * counter active time. And aging counter sharing is not 382 * supported, so active shared counter will not be chained 383 * to the aging list. For shared counter, only when it is 384 * released, the TAILQ entry memory will be used, at that 385 * time, shared memory is not used anymore. 386 * 387 * Similarly to none-batch counter dcs, since it doesn't 388 * support aging, while counter is allocated, the entry 389 * memory is not used anymore. In this case, as bytes 390 * memory is used only when counter is allocated, and 391 * entry memory is used only when counter is free. The 392 * dcs pointer can be saved to these two different place 393 * at different stage. It will eliminate the individual 394 * counter extend struct. 395 */ 396 TAILQ_ENTRY(mlx5_flow_counter) next; 397 /**< Pointer to the next flow counter structure. */ 398 struct { 399 struct mlx5_flow_counter_shared shared_info; 400 /**< Shared counter information. */ 401 void *dcs_when_active; 402 /* 403 * For non-batch mode, the dcs will be saved 404 * here when the counter is free. 405 */ 406 }; 407 }; 408 union { 409 uint64_t hits; /**< Reset value of hits packets. */ 410 struct mlx5_flow_counter_pool *pool; /**< Counter pool. */ 411 }; 412 union { 413 uint64_t bytes; /**< Reset value of bytes. */ 414 void *dcs_when_free; 415 /* 416 * For non-batch mode, the dcs will be saved here 417 * when the counter is free. 418 */ 419 }; 420 void *action; /**< Pointer to the dv action. */ 421 }; 422 423 TAILQ_HEAD(mlx5_counters, mlx5_flow_counter); 424 425 /* Generic counter pool structure - query is in pool resolution. */ 426 struct mlx5_flow_counter_pool { 427 TAILQ_ENTRY(mlx5_flow_counter_pool) next; 428 struct mlx5_counters counters[2]; /* Free counter list. */ 429 struct mlx5_devx_obj *min_dcs; 430 /* The devx object of the minimum counter ID. */ 431 uint64_t time_of_last_age_check; 432 /* System time (from rte_rdtsc()) read in the last aging check. */ 433 uint32_t index:30; /* Pool index in container. */ 434 uint32_t is_aged:1; /* Pool with aging counter. */ 435 volatile uint32_t query_gen:1; /* Query round. */ 436 rte_spinlock_t sl; /* The pool lock. */ 437 rte_spinlock_t csl; /* The pool counter free list lock. */ 438 struct mlx5_counter_stats_raw *raw; 439 struct mlx5_counter_stats_raw *raw_hw; 440 /* The raw on HW working. */ 441 }; 442 443 /* Memory management structure for group of counter statistics raws. */ 444 struct mlx5_counter_stats_mem_mng { 445 LIST_ENTRY(mlx5_counter_stats_mem_mng) next; 446 struct mlx5_counter_stats_raw *raws; 447 struct mlx5_devx_obj *dm; 448 void *umem; 449 }; 450 451 /* Raw memory structure for the counter statistics values of a pool. */ 452 struct mlx5_counter_stats_raw { 453 LIST_ENTRY(mlx5_counter_stats_raw) next; 454 struct mlx5_counter_stats_mem_mng *mem_mng; 455 volatile struct flow_counter_stats *data; 456 }; 457 458 TAILQ_HEAD(mlx5_counter_pools, mlx5_flow_counter_pool); 459 460 /* Counter global management structure. */ 461 struct mlx5_flow_counter_mng { 462 volatile uint16_t n_valid; /* Number of valid pools. */ 463 uint16_t n; /* Number of pools. */ 464 uint16_t last_pool_idx; /* Last used pool index */ 465 int min_id; /* The minimum counter ID in the pools. */ 466 int max_id; /* The maximum counter ID in the pools. */ 467 rte_spinlock_t pool_update_sl; /* The pool update lock. */ 468 rte_spinlock_t csl[MLX5_COUNTER_TYPE_MAX]; 469 /* The counter free list lock. */ 470 struct mlx5_counters counters[MLX5_COUNTER_TYPE_MAX]; 471 /* Free counter list. */ 472 struct mlx5_flow_counter_pool **pools; /* Counter pool array. */ 473 struct mlx5_counter_stats_mem_mng *mem_mng; 474 /* Hold the memory management for the next allocated pools raws. */ 475 struct mlx5_counters flow_counters; /* Legacy flow counter list. */ 476 uint8_t pending_queries; 477 uint16_t pool_index; 478 uint8_t query_thread_on; 479 bool relaxed_ordering_read; 480 bool relaxed_ordering_write; 481 bool counter_fallback; /* Use counter fallback management. */ 482 LIST_HEAD(mem_mngs, mlx5_counter_stats_mem_mng) mem_mngs; 483 LIST_HEAD(stat_raws, mlx5_counter_stats_raw) free_stat_raws; 484 }; 485 486 /* ASO structures. */ 487 #define MLX5_ASO_QUEUE_LOG_DESC 10 488 489 struct mlx5_aso_cq { 490 uint16_t log_desc_n; 491 uint32_t cq_ci:24; 492 struct mlx5_devx_cq cq_obj; 493 uint64_t errors; 494 }; 495 496 struct mlx5_aso_sq_elem { 497 union { 498 struct { 499 struct mlx5_aso_age_pool *pool; 500 uint16_t burst_size; 501 }; 502 struct mlx5_aso_mtr *mtr; 503 struct { 504 struct mlx5_aso_ct_action *ct; 505 char *query_data; 506 }; 507 }; 508 }; 509 510 struct mlx5_aso_sq { 511 uint16_t log_desc_n; 512 rte_spinlock_t sqsl; 513 struct mlx5_aso_cq cq; 514 struct mlx5_devx_sq sq_obj; 515 volatile uint64_t *uar_addr; 516 struct mlx5_pmd_mr mr; 517 uint16_t pi; 518 uint32_t head; 519 uint32_t tail; 520 uint32_t sqn; 521 struct mlx5_aso_sq_elem elts[1 << MLX5_ASO_QUEUE_LOG_DESC]; 522 uint16_t next; /* Pool index of the next pool to query. */ 523 }; 524 525 struct mlx5_aso_age_action { 526 LIST_ENTRY(mlx5_aso_age_action) next; 527 void *dr_action; 528 uint32_t refcnt; 529 /* Following fields relevant only when action is active. */ 530 uint16_t offset; /* Offset of ASO Flow Hit flag in DevX object. */ 531 struct mlx5_age_param age_params; 532 }; 533 534 #define MLX5_ASO_AGE_ACTIONS_PER_POOL 512 535 536 struct mlx5_aso_age_pool { 537 struct mlx5_devx_obj *flow_hit_aso_obj; 538 uint16_t index; /* Pool index in pools array. */ 539 uint64_t time_of_last_age_check; /* In seconds. */ 540 struct mlx5_aso_age_action actions[MLX5_ASO_AGE_ACTIONS_PER_POOL]; 541 }; 542 543 LIST_HEAD(aso_age_list, mlx5_aso_age_action); 544 545 struct mlx5_aso_age_mng { 546 struct mlx5_aso_age_pool **pools; 547 uint16_t n; /* Total number of pools. */ 548 uint16_t next; /* Number of pools in use, index of next free pool. */ 549 rte_spinlock_t resize_sl; /* Lock for resize objects. */ 550 rte_spinlock_t free_sl; /* Lock for free list access. */ 551 struct aso_age_list free; /* Free age actions list - ready to use. */ 552 struct mlx5_aso_sq aso_sq; /* ASO queue objects. */ 553 }; 554 555 /* Management structure for geneve tlv option */ 556 struct mlx5_geneve_tlv_option_resource { 557 struct mlx5_devx_obj *obj; /* Pointer to the geneve tlv opt object. */ 558 rte_be16_t option_class; /* geneve tlv opt class.*/ 559 uint8_t option_type; /* geneve tlv opt type.*/ 560 uint8_t length; /* geneve tlv opt length. */ 561 uint32_t refcnt; /* geneve tlv object reference counter */ 562 }; 563 564 565 #define MLX5_AGE_EVENT_NEW 1 566 #define MLX5_AGE_TRIGGER 2 567 #define MLX5_AGE_SET(age_info, BIT) \ 568 ((age_info)->flags |= (1 << (BIT))) 569 #define MLX5_AGE_UNSET(age_info, BIT) \ 570 ((age_info)->flags &= ~(1 << (BIT))) 571 #define MLX5_AGE_GET(age_info, BIT) \ 572 ((age_info)->flags & (1 << (BIT))) 573 #define GET_PORT_AGE_INFO(priv) \ 574 (&((priv)->sh->port[(priv)->dev_port - 1].age_info)) 575 /* Current time in seconds. */ 576 #define MLX5_CURR_TIME_SEC (rte_rdtsc() / rte_get_tsc_hz()) 577 578 /* Aging information for per port. */ 579 struct mlx5_age_info { 580 uint8_t flags; /* Indicate if is new event or need to be triggered. */ 581 struct mlx5_counters aged_counters; /* Aged counter list. */ 582 struct aso_age_list aged_aso; /* Aged ASO actions list. */ 583 rte_spinlock_t aged_sl; /* Aged flow list lock. */ 584 }; 585 586 /* Per port data of shared IB device. */ 587 struct mlx5_dev_shared_port { 588 uint32_t ih_port_id; 589 uint32_t devx_ih_port_id; 590 /* 591 * Interrupt handler port_id. Used by shared interrupt 592 * handler to find the corresponding rte_eth device 593 * by IB port index. If value is equal or greater 594 * RTE_MAX_ETHPORTS it means there is no subhandler 595 * installed for specified IB port index. 596 */ 597 struct mlx5_age_info age_info; 598 /* Aging information for per port. */ 599 }; 600 601 /* 602 * Max number of actions per DV flow. 603 * See CREATE_FLOW_MAX_FLOW_ACTIONS_SUPPORTED 604 * in rdma-core file providers/mlx5/verbs.c. 605 */ 606 #define MLX5_DV_MAX_NUMBER_OF_ACTIONS 8 607 608 /*ASO flow meter structures*/ 609 /* Modify this value if enum rte_mtr_color changes. */ 610 #define RTE_MTR_DROPPED RTE_COLORS 611 /* Yellow is not supported. */ 612 #define MLX5_MTR_RTE_COLORS (RTE_COLOR_GREEN + 1) 613 /* table_id 22 bits in mlx5_flow_tbl_key so limit policy number. */ 614 #define MLX5_MAX_SUB_POLICY_TBL_NUM 0x3FFFFF 615 #define MLX5_INVALID_POLICY_ID UINT32_MAX 616 /* Suffix table_id on MLX5_FLOW_TABLE_LEVEL_METER. */ 617 #define MLX5_MTR_TABLE_ID_SUFFIX 1 618 /* Drop table_id on MLX5_FLOW_TABLE_LEVEL_METER. */ 619 #define MLX5_MTR_TABLE_ID_DROP 2 620 621 enum mlx5_meter_domain { 622 MLX5_MTR_DOMAIN_INGRESS, 623 MLX5_MTR_DOMAIN_EGRESS, 624 MLX5_MTR_DOMAIN_TRANSFER, 625 MLX5_MTR_DOMAIN_MAX, 626 }; 627 #define MLX5_MTR_DOMAIN_INGRESS_BIT (1 << MLX5_MTR_DOMAIN_INGRESS) 628 #define MLX5_MTR_DOMAIN_EGRESS_BIT (1 << MLX5_MTR_DOMAIN_EGRESS) 629 #define MLX5_MTR_DOMAIN_TRANSFER_BIT (1 << MLX5_MTR_DOMAIN_TRANSFER) 630 #define MLX5_MTR_ALL_DOMAIN_BIT (MLX5_MTR_DOMAIN_INGRESS_BIT | \ 631 MLX5_MTR_DOMAIN_EGRESS_BIT | \ 632 MLX5_MTR_DOMAIN_TRANSFER_BIT) 633 634 /* 635 * Meter sub-policy structure. 636 * Each RSS TIR in meter policy need its own sub-policy resource. 637 */ 638 struct mlx5_flow_meter_sub_policy { 639 uint32_t main_policy_id:1; 640 /* Main policy id is same as this sub_policy id. */ 641 uint32_t idx:31; 642 /* Index to sub_policy ipool entity. */ 643 void *main_policy; 644 /* Point to struct mlx5_flow_meter_policy. */ 645 struct mlx5_flow_tbl_resource *tbl_rsc; 646 /* The sub-policy table resource. */ 647 uint32_t rix_hrxq[MLX5_MTR_RTE_COLORS]; 648 /* Index to TIR resource. */ 649 struct mlx5_flow_tbl_resource *jump_tbl[MLX5_MTR_RTE_COLORS]; 650 /* Meter jump/drop table. */ 651 struct mlx5_flow_dv_matcher *color_matcher[RTE_COLORS]; 652 /* Matcher for Color. */ 653 void *color_rule[RTE_COLORS]; 654 /* Meter green/yellow/drop rule. */ 655 }; 656 657 struct mlx5_meter_policy_acts { 658 uint8_t actions_n; 659 /* Number of actions. */ 660 void *dv_actions[MLX5_DV_MAX_NUMBER_OF_ACTIONS]; 661 /* Action list. */ 662 }; 663 664 struct mlx5_meter_policy_action_container { 665 uint32_t rix_mark; 666 /* Index to the mark action. */ 667 struct mlx5_flow_dv_modify_hdr_resource *modify_hdr; 668 /* Pointer to modify header resource in cache. */ 669 uint8_t fate_action; 670 /* Fate action type. */ 671 union { 672 struct rte_flow_action *rss; 673 /* Rss action configuration. */ 674 uint32_t rix_port_id_action; 675 /* Index to port ID action resource. */ 676 void *dr_jump_action[MLX5_MTR_DOMAIN_MAX]; 677 /* Jump/drop action per color. */ 678 uint16_t queue; 679 /* Queue action configuration. */ 680 }; 681 }; 682 683 /* Flow meter policy parameter structure. */ 684 struct mlx5_flow_meter_policy { 685 uint32_t is_rss:1; 686 /* Is RSS policy table. */ 687 uint32_t ingress:1; 688 /* Rule applies to ingress domain. */ 689 uint32_t egress:1; 690 /* Rule applies to egress domain. */ 691 uint32_t transfer:1; 692 /* Rule applies to transfer domain. */ 693 uint32_t is_queue:1; 694 /* Is queue action in policy table. */ 695 rte_spinlock_t sl; 696 uint32_t ref_cnt; 697 /* Use count. */ 698 struct mlx5_meter_policy_action_container act_cnt[MLX5_MTR_RTE_COLORS]; 699 /* Policy actions container. */ 700 void *dr_drop_action[MLX5_MTR_DOMAIN_MAX]; 701 /* drop action for red color. */ 702 uint16_t sub_policy_num; 703 /* Count sub policy tables, 3 bits per domain. */ 704 struct mlx5_flow_meter_sub_policy **sub_policys[MLX5_MTR_DOMAIN_MAX]; 705 /* Sub policy table array must be the end of struct. */ 706 }; 707 708 /* The maximum sub policy is relate to struct mlx5_rss_hash_fields[]. */ 709 #define MLX5_MTR_RSS_MAX_SUB_POLICY 7 710 #define MLX5_MTR_SUB_POLICY_NUM_SHIFT 3 711 #define MLX5_MTR_SUB_POLICY_NUM_MASK 0x7 712 #define MLX5_MTRS_DEFAULT_RULE_PRIORITY 0xFFFF 713 714 /* Flow meter default policy parameter structure. 715 * Policy index 0 is reserved by default policy table. 716 * Action per color as below: 717 * green - do nothing, yellow - do nothing, red - drop 718 */ 719 struct mlx5_flow_meter_def_policy { 720 struct mlx5_flow_meter_sub_policy sub_policy; 721 /* Policy rules jump to other tables. */ 722 void *dr_jump_action[RTE_COLORS]; 723 /* Jump action per color. */ 724 }; 725 726 /* Meter parameter structure. */ 727 struct mlx5_flow_meter_info { 728 uint32_t meter_id; 729 /**< Meter id. */ 730 uint32_t policy_id; 731 /* Policy id, the first sub_policy idx. */ 732 struct mlx5_flow_meter_profile *profile; 733 /**< Meter profile parameters. */ 734 rte_spinlock_t sl; /**< Meter action spinlock. */ 735 /** Set of stats counters to be enabled. 736 * @see enum rte_mtr_stats_type 737 */ 738 uint32_t bytes_dropped:1; 739 /** Set bytes dropped stats to be enabled. */ 740 uint32_t pkts_dropped:1; 741 /** Set packets dropped stats to be enabled. */ 742 uint32_t active_state:1; 743 /**< Meter hw active state. */ 744 uint32_t shared:1; 745 /**< Meter shared or not. */ 746 uint32_t is_enable:1; 747 /**< Meter disable/enable state. */ 748 uint32_t ingress:1; 749 /**< Rule applies to egress traffic. */ 750 uint32_t egress:1; 751 /** 752 * Instead of simply matching the properties of traffic as it would 753 * appear on a given DPDK port ID, enabling this attribute transfers 754 * a flow rule to the lowest possible level of any device endpoints 755 * found in the pattern. 756 * 757 * When supported, this effectively enables an application to 758 * re-route traffic not necessarily intended for it (e.g. coming 759 * from or addressed to different physical ports, VFs or 760 * applications) at the device level. 761 * 762 * It complements the behavior of some pattern items such as 763 * RTE_FLOW_ITEM_TYPE_PHY_PORT and is meaningless without them. 764 * 765 * When transferring flow rules, ingress and egress attributes keep 766 * their original meaning, as if processing traffic emitted or 767 * received by the application. 768 */ 769 uint32_t transfer:1; 770 uint32_t def_policy:1; 771 /* Meter points to default policy. */ 772 void *drop_rule[MLX5_MTR_DOMAIN_MAX]; 773 /* Meter drop rule in drop table. */ 774 uint32_t drop_cnt; 775 /**< Color counter for drop. */ 776 uint32_t ref_cnt; 777 /**< Use count. */ 778 struct mlx5_indexed_pool *flow_ipool; 779 /**< Index pool for flow id. */ 780 void *meter_action; 781 /**< Flow meter action. */ 782 }; 783 784 /* PPS(packets per second) map to BPS(Bytes per second). 785 * HW treat packet as 128bytes in PPS mode 786 */ 787 #define MLX5_MTRS_PPS_MAP_BPS_SHIFT 7 788 789 /* RFC2697 parameter structure. */ 790 struct mlx5_flow_meter_srtcm_rfc2697_prm { 791 rte_be32_t cbs_cir; 792 /* 793 * bit 24-28: cbs_exponent, bit 16-23 cbs_mantissa, 794 * bit 8-12: cir_exponent, bit 0-7 cir_mantissa. 795 */ 796 rte_be32_t ebs_eir; 797 /* 798 * bit 24-28: ebs_exponent, bit 16-23 ebs_mantissa, 799 * bit 8-12: eir_exponent, bit 0-7 eir_mantissa. 800 */ 801 }; 802 803 /* Flow meter profile structure. */ 804 struct mlx5_flow_meter_profile { 805 TAILQ_ENTRY(mlx5_flow_meter_profile) next; 806 /**< Pointer to the next flow meter structure. */ 807 uint32_t id; /**< Profile id. */ 808 struct rte_mtr_meter_profile profile; /**< Profile detail. */ 809 union { 810 struct mlx5_flow_meter_srtcm_rfc2697_prm srtcm_prm; 811 /**< srtcm_rfc2697 struct. */ 812 }; 813 uint32_t ref_cnt; /**< Use count. */ 814 }; 815 816 /* 2 meters in each ASO cache line */ 817 #define MLX5_MTRS_CONTAINER_RESIZE 64 818 /* 819 * The pool index and offset of meter in the pool array makes up the 820 * meter index. In case the meter is from pool 0 and offset 0, it 821 * should plus 1 to avoid index 0, since 0 means invalid meter index 822 * currently. 823 */ 824 #define MLX5_MAKE_MTR_IDX(pi, offset) \ 825 ((pi) * MLX5_ASO_MTRS_PER_POOL + (offset) + 1) 826 827 /*aso flow meter state*/ 828 enum mlx5_aso_mtr_state { 829 ASO_METER_FREE, /* In free list. */ 830 ASO_METER_WAIT, /* ACCESS_ASO WQE in progress. */ 831 ASO_METER_READY, /* CQE received. */ 832 }; 833 834 /* Generic aso_flow_meter information. */ 835 struct mlx5_aso_mtr { 836 LIST_ENTRY(mlx5_aso_mtr) next; 837 struct mlx5_flow_meter_info fm; 838 /**< Pointer to the next aso flow meter structure. */ 839 uint8_t state; /**< ASO flow meter state. */ 840 uint8_t offset; 841 }; 842 843 /* Generic aso_flow_meter pool structure. */ 844 struct mlx5_aso_mtr_pool { 845 struct mlx5_aso_mtr mtrs[MLX5_ASO_MTRS_PER_POOL]; 846 /*Must be the first in pool*/ 847 struct mlx5_devx_obj *devx_obj; 848 /* The devx object of the minimum aso flow meter ID. */ 849 uint32_t index; /* Pool index in management structure. */ 850 }; 851 852 LIST_HEAD(aso_meter_list, mlx5_aso_mtr); 853 /* Pools management structure for ASO flow meter pools. */ 854 struct mlx5_aso_mtr_pools_mng { 855 volatile uint16_t n_valid; /* Number of valid pools. */ 856 uint16_t n; /* Number of pools. */ 857 rte_spinlock_t mtrsl; /* The ASO flow meter free list lock. */ 858 struct aso_meter_list meters; /* Free ASO flow meter list. */ 859 struct mlx5_aso_sq sq; /*SQ using by ASO flow meter. */ 860 struct mlx5_aso_mtr_pool **pools; /* ASO flow meter pool array. */ 861 }; 862 863 /* Meter management structure for global flow meter resource. */ 864 struct mlx5_flow_mtr_mng { 865 struct mlx5_aso_mtr_pools_mng pools_mng; 866 /* Pools management structure for ASO flow meter pools. */ 867 struct mlx5_flow_meter_def_policy *def_policy[MLX5_MTR_DOMAIN_MAX]; 868 /* Default policy table. */ 869 uint32_t def_policy_id; 870 /* Default policy id. */ 871 uint32_t def_policy_ref_cnt; 872 /** def_policy meter use count. */ 873 struct mlx5_l3t_tbl *policy_idx_tbl; 874 /* Policy index lookup table. */ 875 struct mlx5_flow_tbl_resource *drop_tbl[MLX5_MTR_DOMAIN_MAX]; 876 /* Meter drop table. */ 877 struct mlx5_flow_dv_matcher * 878 drop_matcher[MLX5_MTR_DOMAIN_MAX][MLX5_REG_BITS]; 879 /* Matcher meter in drop table. */ 880 struct mlx5_flow_dv_matcher *def_matcher[MLX5_MTR_DOMAIN_MAX]; 881 /* Default matcher in drop table. */ 882 void *def_rule[MLX5_MTR_DOMAIN_MAX]; 883 /* Default rule in drop table. */ 884 uint8_t max_mtr_bits; 885 /* Indicate how many bits are used by meter id at the most. */ 886 uint8_t max_mtr_flow_bits; 887 /* Indicate how many bits are used by meter flow id at the most. */ 888 }; 889 890 /* Table key of the hash organization. */ 891 union mlx5_flow_tbl_key { 892 struct { 893 /* Table ID should be at the lowest address. */ 894 uint32_t level; /**< Level of the table. */ 895 uint32_t id:22; /**< ID of the table. */ 896 uint32_t dummy:1; /**< Dummy table for DV API. */ 897 uint32_t is_fdb:1; /**< 1 - FDB, 0 - NIC TX/RX. */ 898 uint32_t is_egress:1; /**< 1 - egress, 0 - ingress. */ 899 uint32_t reserved:7; /**< must be zero for comparison. */ 900 }; 901 uint64_t v64; /**< full 64bits value of key */ 902 }; 903 904 /* Table structure. */ 905 struct mlx5_flow_tbl_resource { 906 void *obj; /**< Pointer to DR table object. */ 907 uint32_t refcnt; /**< Reference counter. */ 908 }; 909 910 #define MLX5_MAX_TABLES UINT16_MAX 911 #define MLX5_HAIRPIN_TX_TABLE (UINT16_MAX - 1) 912 /* Reserve the last two tables for metadata register copy. */ 913 #define MLX5_FLOW_MREG_ACT_TABLE_GROUP (MLX5_MAX_TABLES - 1) 914 #define MLX5_FLOW_MREG_CP_TABLE_GROUP (MLX5_MAX_TABLES - 2) 915 /* Tables for metering splits should be added here. */ 916 #define MLX5_FLOW_TABLE_LEVEL_METER (MLX5_MAX_TABLES - 3) 917 #define MLX5_FLOW_TABLE_LEVEL_POLICY (MLX5_MAX_TABLES - 4) 918 #define MLX5_MAX_TABLES_EXTERNAL MLX5_FLOW_TABLE_LEVEL_POLICY 919 #define MLX5_MAX_TABLES_FDB UINT16_MAX 920 #define MLX5_FLOW_TABLE_FACTOR 10 921 922 /* ID generation structure. */ 923 struct mlx5_flow_id_pool { 924 uint32_t *free_arr; /**< Pointer to the a array of free values. */ 925 uint32_t base_index; 926 /**< The next index that can be used without any free elements. */ 927 uint32_t *curr; /**< Pointer to the index to pop. */ 928 uint32_t *last; /**< Pointer to the last element in the empty arrray. */ 929 uint32_t max_id; /**< Maximum id can be allocated from the pool. */ 930 }; 931 932 /* Tx pacing queue structure - for Clock and Rearm queues. */ 933 struct mlx5_txpp_wq { 934 /* Completion Queue related data.*/ 935 struct mlx5_devx_cq cq_obj; 936 uint32_t cq_ci:24; 937 uint32_t arm_sn:2; 938 /* Send Queue related data.*/ 939 struct mlx5_devx_sq sq_obj; 940 uint16_t sq_size; /* Number of WQEs in the queue. */ 941 uint16_t sq_ci; /* Next WQE to execute. */ 942 }; 943 944 /* Tx packet pacing internal timestamp. */ 945 struct mlx5_txpp_ts { 946 uint64_t ci_ts; 947 uint64_t ts; 948 }; 949 950 /* Tx packet pacing structure. */ 951 struct mlx5_dev_txpp { 952 pthread_mutex_t mutex; /* Pacing create/destroy mutex. */ 953 uint32_t refcnt; /* Pacing reference counter. */ 954 uint32_t freq; /* Timestamp frequency, Hz. */ 955 uint32_t tick; /* Completion tick duration in nanoseconds. */ 956 uint32_t test; /* Packet pacing test mode. */ 957 int32_t skew; /* Scheduling skew. */ 958 struct rte_intr_handle intr_handle; /* Periodic interrupt. */ 959 void *echan; /* Event Channel. */ 960 struct mlx5_txpp_wq clock_queue; /* Clock Queue. */ 961 struct mlx5_txpp_wq rearm_queue; /* Clock Queue. */ 962 void *pp; /* Packet pacing context. */ 963 uint16_t pp_id; /* Packet pacing context index. */ 964 uint16_t ts_n; /* Number of captured timestamps. */ 965 uint16_t ts_p; /* Pointer to statisticks timestamp. */ 966 struct mlx5_txpp_ts *tsa; /* Timestamps sliding window stats. */ 967 struct mlx5_txpp_ts ts; /* Cached completion id/timestamp. */ 968 uint32_t sync_lost:1; /* ci/timestamp synchronization lost. */ 969 /* Statistics counters. */ 970 uint64_t err_miss_int; /* Missed service interrupt. */ 971 uint64_t err_rearm_queue; /* Rearm Queue errors. */ 972 uint64_t err_clock_queue; /* Clock Queue errors. */ 973 uint64_t err_ts_past; /* Timestamp in the past. */ 974 uint64_t err_ts_future; /* Timestamp in the distant future. */ 975 }; 976 977 /* Supported flex parser profile ID. */ 978 enum mlx5_flex_parser_profile_id { 979 MLX5_FLEX_PARSER_ECPRI_0 = 0, 980 MLX5_FLEX_PARSER_MAX = 8, 981 }; 982 983 /* Sample ID information of flex parser structure. */ 984 struct mlx5_flex_parser_profiles { 985 uint32_t num; /* Actual number of samples. */ 986 uint32_t ids[8]; /* Sample IDs for this profile. */ 987 uint8_t offset[8]; /* Bytes offset of each parser. */ 988 void *obj; /* Flex parser node object. */ 989 }; 990 991 /* Max member ports per bonding device. */ 992 #define MLX5_BOND_MAX_PORTS 2 993 994 /* Bonding device information. */ 995 struct mlx5_bond_info { 996 int n_port; /* Number of bond member ports. */ 997 uint32_t ifindex; 998 char ifname[MLX5_NAMESIZE + 1]; 999 struct { 1000 char ifname[MLX5_NAMESIZE + 1]; 1001 uint32_t ifindex; 1002 struct rte_pci_addr pci_addr; 1003 } ports[MLX5_BOND_MAX_PORTS]; 1004 }; 1005 1006 /* Number of connection tracking objects per pool: must be a power of 2. */ 1007 #define MLX5_ASO_CT_ACTIONS_PER_POOL 64 1008 1009 /* Generate incremental and unique CT index from pool and offset. */ 1010 #define MLX5_MAKE_CT_IDX(pool, offset) \ 1011 ((pool) * MLX5_ASO_CT_ACTIONS_PER_POOL + (offset) + 1) 1012 1013 /* ASO Conntrack state. */ 1014 enum mlx5_aso_ct_state { 1015 ASO_CONNTRACK_FREE, /* Inactive, in the free list. */ 1016 ASO_CONNTRACK_WAIT, /* WQE sent in the SQ. */ 1017 ASO_CONNTRACK_READY, /* CQE received w/o error. */ 1018 ASO_CONNTRACK_QUERY, /* WQE for query sent. */ 1019 ASO_CONNTRACK_MAX, /* Guard. */ 1020 }; 1021 1022 /* Generic ASO connection tracking structure. */ 1023 struct mlx5_aso_ct_action { 1024 LIST_ENTRY(mlx5_aso_ct_action) next; /* Pointer to the next ASO CT. */ 1025 void *dr_action_orig; /* General action object for original dir. */ 1026 void *dr_action_rply; /* General action object for reply dir. */ 1027 uint32_t refcnt; /* Action used count in device flows. */ 1028 uint16_t offset; /* Offset of ASO CT in DevX objects bulk. */ 1029 uint16_t peer; /* The only peer port index could also use this CT. */ 1030 enum mlx5_aso_ct_state state; /* ASO CT state. */ 1031 bool is_original; /* The direction of the DR action to be used. */ 1032 }; 1033 1034 /* CT action object state update. */ 1035 #define MLX5_ASO_CT_UPDATE_STATE(c, s) \ 1036 __atomic_store_n(&((c)->state), (s), __ATOMIC_RELAXED) 1037 1038 /* ASO connection tracking software pool definition. */ 1039 struct mlx5_aso_ct_pool { 1040 uint16_t index; /* Pool index in pools array. */ 1041 struct mlx5_devx_obj *devx_obj; 1042 /* The first devx object in the bulk, used for freeing (not yet). */ 1043 struct mlx5_aso_ct_action actions[MLX5_ASO_CT_ACTIONS_PER_POOL]; 1044 /* CT action structures bulk. */ 1045 }; 1046 1047 LIST_HEAD(aso_ct_list, mlx5_aso_ct_action); 1048 1049 /* Pools management structure for ASO connection tracking pools. */ 1050 struct mlx5_aso_ct_pools_mng { 1051 struct mlx5_aso_ct_pool **pools; 1052 uint16_t n; /* Total number of pools. */ 1053 uint16_t next; /* Number of pools in use, index of next free pool. */ 1054 rte_spinlock_t ct_sl; /* The ASO CT free list lock. */ 1055 rte_rwlock_t resize_rwl; /* The ASO CT pool resize lock. */ 1056 struct aso_ct_list free_cts; /* Free ASO CT objects list. */ 1057 struct mlx5_aso_sq aso_sq; /* ASO queue objects. */ 1058 }; 1059 1060 /* 1061 * Shared Infiniband device context for Master/Representors 1062 * which belong to same IB device with multiple IB ports. 1063 **/ 1064 struct mlx5_dev_ctx_shared { 1065 LIST_ENTRY(mlx5_dev_ctx_shared) next; 1066 uint32_t refcnt; 1067 uint32_t devx:1; /* Opened with DV. */ 1068 uint32_t flow_hit_aso_en:1; /* Flow Hit ASO is supported. */ 1069 uint32_t rq_ts_format:2; /* RQ timestamp formats supported. */ 1070 uint32_t sq_ts_format:2; /* SQ timestamp formats supported. */ 1071 uint32_t qp_ts_format:2; /* QP timestamp formats supported. */ 1072 uint32_t meter_aso_en:1; /* Flow Meter ASO is supported. */ 1073 uint32_t ct_aso_en:1; /* Connection Tracking ASO is supported. */ 1074 uint32_t max_port; /* Maximal IB device port index. */ 1075 struct mlx5_bond_info bond; /* Bonding information. */ 1076 void *ctx; /* Verbs/DV/DevX context. */ 1077 void *pd; /* Protection Domain. */ 1078 uint32_t pdn; /* Protection Domain number. */ 1079 uint32_t tdn; /* Transport Domain number. */ 1080 char ibdev_name[MLX5_FS_NAME_MAX]; /* SYSFS dev name. */ 1081 char ibdev_path[MLX5_FS_PATH_MAX]; /* SYSFS dev path for secondary */ 1082 struct mlx5_dev_attr device_attr; /* Device properties. */ 1083 int numa_node; /* Numa node of backing physical device. */ 1084 LIST_ENTRY(mlx5_dev_ctx_shared) mem_event_cb; 1085 /**< Called by memory event callback. */ 1086 struct mlx5_mr_share_cache share_cache; 1087 /* Packet pacing related structure. */ 1088 struct mlx5_dev_txpp txpp; 1089 /* Shared DV/DR flow data section. */ 1090 uint32_t dv_meta_mask; /* flow META metadata supported mask. */ 1091 uint32_t dv_mark_mask; /* flow MARK metadata supported mask. */ 1092 uint32_t dv_regc0_mask; /* available bits of metatada reg_c[0]. */ 1093 void *fdb_domain; /* FDB Direct Rules name space handle. */ 1094 void *rx_domain; /* RX Direct Rules name space handle. */ 1095 void *tx_domain; /* TX Direct Rules name space handle. */ 1096 #ifndef RTE_ARCH_64 1097 rte_spinlock_t uar_lock_cq; /* CQs share a common distinct UAR */ 1098 rte_spinlock_t uar_lock[MLX5_UAR_PAGE_NUM_MAX]; 1099 /* UAR same-page access control required in 32bit implementations. */ 1100 #endif 1101 struct mlx5_hlist *flow_tbls; 1102 struct mlx5_flow_tunnel_hub *tunnel_hub; 1103 /* Direct Rules tables for FDB, NIC TX+RX */ 1104 void *dr_drop_action; /* Pointer to DR drop action, any domain. */ 1105 void *pop_vlan_action; /* Pointer to DR pop VLAN action. */ 1106 struct mlx5_hlist *encaps_decaps; /* Encap/decap action hash list. */ 1107 struct mlx5_hlist *modify_cmds; 1108 struct mlx5_hlist *tag_table; 1109 struct mlx5_cache_list port_id_action_list; /* Port ID action cache. */ 1110 struct mlx5_cache_list push_vlan_action_list; /* Push VLAN actions. */ 1111 struct mlx5_cache_list sample_action_list; /* List of sample actions. */ 1112 struct mlx5_cache_list dest_array_list; 1113 /* List of destination array actions. */ 1114 struct mlx5_flow_counter_mng cmng; /* Counters management structure. */ 1115 void *default_miss_action; /* Default miss action. */ 1116 struct mlx5_indexed_pool *ipool[MLX5_IPOOL_MAX]; 1117 /* Memory Pool for mlx5 flow resources. */ 1118 struct mlx5_l3t_tbl *cnt_id_tbl; /* Shared counter lookup table. */ 1119 /* Shared interrupt handler section. */ 1120 struct rte_intr_handle intr_handle; /* Interrupt handler for device. */ 1121 struct rte_intr_handle intr_handle_devx; /* DEVX interrupt handler. */ 1122 void *devx_comp; /* DEVX async comp obj. */ 1123 struct mlx5_devx_obj *tis; /* TIS object. */ 1124 struct mlx5_devx_obj *td; /* Transport domain. */ 1125 void *tx_uar; /* Tx/packet pacing shared UAR. */ 1126 struct mlx5_flex_parser_profiles fp[MLX5_FLEX_PARSER_MAX]; 1127 /* Flex parser profiles information. */ 1128 void *devx_rx_uar; /* DevX UAR for Rx. */ 1129 struct mlx5_aso_age_mng *aso_age_mng; 1130 /* Management data for aging mechanism using ASO Flow Hit. */ 1131 struct mlx5_geneve_tlv_option_resource *geneve_tlv_option_resource; 1132 /* Management structure for geneve tlv option */ 1133 rte_spinlock_t geneve_tlv_opt_sl; /* Lock for geneve tlv resource */ 1134 struct mlx5_flow_mtr_mng *mtrmng; 1135 /* Meter management structure. */ 1136 struct mlx5_aso_ct_pools_mng *ct_mng; 1137 /* Management data for ASO connection tracking. */ 1138 struct mlx5_lb_ctx self_lb; /* QP to enable self loopback for Devx. */ 1139 struct mlx5_dev_shared_port port[]; /* per device port data array. */ 1140 }; 1141 1142 /* 1143 * Per-process private structure. 1144 * Caution, secondary process may rebuild the struct during port start. 1145 */ 1146 struct mlx5_proc_priv { 1147 size_t uar_table_sz; 1148 /* Size of UAR register table. */ 1149 void *uar_table[]; 1150 /* Table of UAR registers for each process. */ 1151 }; 1152 1153 /* MTR profile list. */ 1154 TAILQ_HEAD(mlx5_mtr_profiles, mlx5_flow_meter_profile); 1155 /* MTR list. */ 1156 TAILQ_HEAD(mlx5_legacy_flow_meters, mlx5_legacy_flow_meter); 1157 1158 /* RSS description. */ 1159 struct mlx5_flow_rss_desc { 1160 uint32_t level; 1161 uint32_t queue_num; /**< Number of entries in @p queue. */ 1162 uint64_t types; /**< Specific RSS hash types (see ETH_RSS_*). */ 1163 uint64_t hash_fields; /* Verbs Hash fields. */ 1164 uint8_t key[MLX5_RSS_HASH_KEY_LEN]; /**< RSS hash key. */ 1165 uint32_t key_len; /**< RSS hash key len. */ 1166 uint32_t tunnel; /**< Queue in tunnel. */ 1167 uint32_t shared_rss; /**< Shared RSS index. */ 1168 struct mlx5_ind_table_obj *ind_tbl; 1169 /**< Indirection table for shared RSS hash RX queues. */ 1170 union { 1171 uint16_t *queue; /**< Destination queues. */ 1172 const uint16_t *const_q; /**< Const pointer convert. */ 1173 }; 1174 }; 1175 1176 #define MLX5_PROC_PRIV(port_id) \ 1177 ((struct mlx5_proc_priv *)rte_eth_devices[port_id].process_private) 1178 1179 /* Verbs/DevX Rx queue elements. */ 1180 struct mlx5_rxq_obj { 1181 LIST_ENTRY(mlx5_rxq_obj) next; /* Pointer to the next element. */ 1182 struct mlx5_rxq_ctrl *rxq_ctrl; /* Back pointer to parent. */ 1183 int fd; /* File descriptor for event channel */ 1184 RTE_STD_C11 1185 union { 1186 struct { 1187 void *wq; /* Work Queue. */ 1188 void *ibv_cq; /* Completion Queue. */ 1189 void *ibv_channel; 1190 }; 1191 struct mlx5_devx_obj *rq; /* DevX RQ object for hairpin. */ 1192 struct { 1193 struct mlx5_devx_rq rq_obj; /* DevX RQ object. */ 1194 struct mlx5_devx_cq cq_obj; /* DevX CQ object. */ 1195 void *devx_channel; 1196 }; 1197 }; 1198 }; 1199 1200 /* Indirection table. */ 1201 struct mlx5_ind_table_obj { 1202 LIST_ENTRY(mlx5_ind_table_obj) next; /* Pointer to the next element. */ 1203 uint32_t refcnt; /* Reference counter. */ 1204 RTE_STD_C11 1205 union { 1206 void *ind_table; /**< Indirection table. */ 1207 struct mlx5_devx_obj *rqt; /* DevX RQT object. */ 1208 }; 1209 uint32_t queues_n; /**< Number of queues in the list. */ 1210 uint16_t *queues; /**< Queue list. */ 1211 }; 1212 1213 /* Hash Rx queue. */ 1214 __extension__ 1215 struct mlx5_hrxq { 1216 struct mlx5_cache_entry entry; /* Cache entry. */ 1217 uint32_t standalone:1; /* This object used in shared action. */ 1218 struct mlx5_ind_table_obj *ind_table; /* Indirection table. */ 1219 RTE_STD_C11 1220 union { 1221 void *qp; /* Verbs queue pair. */ 1222 struct mlx5_devx_obj *tir; /* DevX TIR object. */ 1223 }; 1224 #if defined(HAVE_IBV_FLOW_DV_SUPPORT) || !defined(HAVE_INFINIBAND_VERBS_H) 1225 void *action; /* DV QP action pointer. */ 1226 #endif 1227 uint64_t hash_fields; /* Verbs Hash fields. */ 1228 uint32_t rss_key_len; /* Hash key length in bytes. */ 1229 uint32_t idx; /* Hash Rx queue index. */ 1230 uint8_t rss_key[]; /* Hash key. */ 1231 }; 1232 1233 /* Verbs/DevX Tx queue elements. */ 1234 struct mlx5_txq_obj { 1235 LIST_ENTRY(mlx5_txq_obj) next; /* Pointer to the next element. */ 1236 struct mlx5_txq_ctrl *txq_ctrl; /* Pointer to the control queue. */ 1237 RTE_STD_C11 1238 union { 1239 struct { 1240 void *cq; /* Completion Queue. */ 1241 void *qp; /* Queue Pair. */ 1242 }; 1243 struct { 1244 struct mlx5_devx_obj *sq; 1245 /* DevX object for Sx queue. */ 1246 struct mlx5_devx_obj *tis; /* The TIS object. */ 1247 }; 1248 struct { 1249 struct rte_eth_dev *dev; 1250 struct mlx5_devx_cq cq_obj; 1251 /* DevX CQ object and its resources. */ 1252 struct mlx5_devx_sq sq_obj; 1253 /* DevX SQ object and its resources. */ 1254 }; 1255 }; 1256 }; 1257 1258 enum mlx5_rxq_modify_type { 1259 MLX5_RXQ_MOD_ERR2RST, /* modify state from error to reset. */ 1260 MLX5_RXQ_MOD_RST2RDY, /* modify state from reset to ready. */ 1261 MLX5_RXQ_MOD_RDY2ERR, /* modify state from ready to error. */ 1262 MLX5_RXQ_MOD_RDY2RST, /* modify state from ready to reset. */ 1263 }; 1264 1265 enum mlx5_txq_modify_type { 1266 MLX5_TXQ_MOD_RST2RDY, /* modify state from reset to ready. */ 1267 MLX5_TXQ_MOD_RDY2RST, /* modify state from ready to reset. */ 1268 MLX5_TXQ_MOD_ERR2RDY, /* modify state from error to ready. */ 1269 }; 1270 1271 /* HW objects operations structure. */ 1272 struct mlx5_obj_ops { 1273 int (*rxq_obj_modify_vlan_strip)(struct mlx5_rxq_obj *rxq_obj, int on); 1274 int (*rxq_obj_new)(struct rte_eth_dev *dev, uint16_t idx); 1275 int (*rxq_event_get)(struct mlx5_rxq_obj *rxq_obj); 1276 int (*rxq_obj_modify)(struct mlx5_rxq_obj *rxq_obj, uint8_t type); 1277 void (*rxq_obj_release)(struct mlx5_rxq_obj *rxq_obj); 1278 int (*ind_table_new)(struct rte_eth_dev *dev, const unsigned int log_n, 1279 struct mlx5_ind_table_obj *ind_tbl); 1280 int (*ind_table_modify)(struct rte_eth_dev *dev, 1281 const unsigned int log_n, 1282 const uint16_t *queues, const uint32_t queues_n, 1283 struct mlx5_ind_table_obj *ind_tbl); 1284 void (*ind_table_destroy)(struct mlx5_ind_table_obj *ind_tbl); 1285 int (*hrxq_new)(struct rte_eth_dev *dev, struct mlx5_hrxq *hrxq, 1286 int tunnel __rte_unused); 1287 int (*hrxq_modify)(struct rte_eth_dev *dev, struct mlx5_hrxq *hrxq, 1288 const uint8_t *rss_key, 1289 uint64_t hash_fields, 1290 const struct mlx5_ind_table_obj *ind_tbl); 1291 void (*hrxq_destroy)(struct mlx5_hrxq *hrxq); 1292 int (*drop_action_create)(struct rte_eth_dev *dev); 1293 void (*drop_action_destroy)(struct rte_eth_dev *dev); 1294 int (*txq_obj_new)(struct rte_eth_dev *dev, uint16_t idx); 1295 int (*txq_obj_modify)(struct mlx5_txq_obj *obj, 1296 enum mlx5_txq_modify_type type, uint8_t dev_port); 1297 void (*txq_obj_release)(struct mlx5_txq_obj *txq_obj); 1298 int (*lb_dummy_queue_create)(struct rte_eth_dev *dev); 1299 void (*lb_dummy_queue_release)(struct rte_eth_dev *dev); 1300 }; 1301 1302 #define MLX5_RSS_HASH_FIELDS_LEN RTE_DIM(mlx5_rss_hash_fields) 1303 1304 /* MR operations structure. */ 1305 struct mlx5_mr_ops { 1306 mlx5_reg_mr_t reg_mr; 1307 mlx5_dereg_mr_t dereg_mr; 1308 }; 1309 1310 struct mlx5_priv { 1311 struct rte_eth_dev_data *dev_data; /* Pointer to device data. */ 1312 struct mlx5_dev_ctx_shared *sh; /* Shared device context. */ 1313 uint32_t dev_port; /* Device port number. */ 1314 struct rte_pci_device *pci_dev; /* Backend PCI device. */ 1315 struct rte_ether_addr mac[MLX5_MAX_MAC_ADDRESSES]; /* MAC addresses. */ 1316 BITFIELD_DECLARE(mac_own, uint64_t, MLX5_MAX_MAC_ADDRESSES); 1317 /* Bit-field of MAC addresses owned by the PMD. */ 1318 uint16_t vlan_filter[MLX5_MAX_VLAN_IDS]; /* VLAN filters table. */ 1319 unsigned int vlan_filter_n; /* Number of configured VLAN filters. */ 1320 /* Device properties. */ 1321 uint16_t mtu; /* Configured MTU. */ 1322 unsigned int isolated:1; /* Whether isolated mode is enabled. */ 1323 unsigned int representor:1; /* Device is a port representor. */ 1324 unsigned int master:1; /* Device is a E-Switch master. */ 1325 unsigned int txpp_en:1; /* Tx packet pacing enabled. */ 1326 unsigned int sampler_en:1; /* Whether support sampler. */ 1327 unsigned int mtr_en:1; /* Whether support meter. */ 1328 unsigned int mtr_reg_share:1; /* Whether support meter REG_C share. */ 1329 unsigned int lb_used:1; /* Loopback queue is referred to. */ 1330 uint16_t domain_id; /* Switch domain identifier. */ 1331 uint16_t vport_id; /* Associated VF vport index (if any). */ 1332 uint32_t vport_meta_tag; /* Used for vport index match ove VF LAG. */ 1333 uint32_t vport_meta_mask; /* Used for vport index field match mask. */ 1334 int32_t representor_id; /* -1 if not a representor. */ 1335 int32_t pf_bond; /* >=0, representor owner PF index in bonding. */ 1336 unsigned int if_index; /* Associated kernel network device index. */ 1337 /* RX/TX queues. */ 1338 unsigned int rxqs_n; /* RX queues array size. */ 1339 unsigned int txqs_n; /* TX queues array size. */ 1340 struct mlx5_rxq_data *(*rxqs)[]; /* RX queues. */ 1341 struct mlx5_txq_data *(*txqs)[]; /* TX queues. */ 1342 struct rte_mempool *mprq_mp; /* Mempool for Multi-Packet RQ. */ 1343 struct rte_eth_rss_conf rss_conf; /* RSS configuration. */ 1344 unsigned int (*reta_idx)[]; /* RETA index table. */ 1345 unsigned int reta_idx_n; /* RETA index size. */ 1346 struct mlx5_drop drop_queue; /* Flow drop queues. */ 1347 uint32_t flows; /* RTE Flow rules. */ 1348 uint32_t ctrl_flows; /* Control flow rules. */ 1349 rte_spinlock_t flow_list_lock; 1350 struct mlx5_obj_ops obj_ops; /* HW objects operations. */ 1351 LIST_HEAD(rxq, mlx5_rxq_ctrl) rxqsctrl; /* DPDK Rx queues. */ 1352 LIST_HEAD(rxqobj, mlx5_rxq_obj) rxqsobj; /* Verbs/DevX Rx queues. */ 1353 struct mlx5_cache_list hrxqs; /* Hash Rx queues. */ 1354 LIST_HEAD(txq, mlx5_txq_ctrl) txqsctrl; /* DPDK Tx queues. */ 1355 LIST_HEAD(txqobj, mlx5_txq_obj) txqsobj; /* Verbs/DevX Tx queues. */ 1356 /* Indirection tables. */ 1357 LIST_HEAD(ind_tables, mlx5_ind_table_obj) ind_tbls; 1358 /* Pointer to next element. */ 1359 uint32_t refcnt; /**< Reference counter. */ 1360 /**< Verbs modify header action object. */ 1361 uint8_t ft_type; /**< Flow table type, Rx or Tx. */ 1362 uint8_t max_lro_msg_size; 1363 /* Tags resources cache. */ 1364 uint32_t link_speed_capa; /* Link speed capabilities. */ 1365 struct mlx5_xstats_ctrl xstats_ctrl; /* Extended stats control. */ 1366 struct mlx5_stats_ctrl stats_ctrl; /* Stats control. */ 1367 struct mlx5_dev_config config; /* Device configuration. */ 1368 /* Context for Verbs allocator. */ 1369 int nl_socket_rdma; /* Netlink socket (NETLINK_RDMA). */ 1370 int nl_socket_route; /* Netlink socket (NETLINK_ROUTE). */ 1371 struct mlx5_nl_vlan_vmwa_context *vmwa_context; /* VLAN WA context. */ 1372 struct mlx5_hlist *mreg_cp_tbl; 1373 /* Hash table of Rx metadata register copy table. */ 1374 uint8_t mtr_sfx_reg; /* Meter prefix-suffix flow match REG_C. */ 1375 uint8_t mtr_color_reg; /* Meter color match REG_C. */ 1376 struct mlx5_mtr_profiles flow_meter_profiles; /* MTR profile list. */ 1377 struct mlx5_legacy_flow_meters flow_meters; /* MTR list. */ 1378 struct mlx5_l3t_tbl *mtr_idx_tbl; /* Meter index lookup table. */ 1379 uint8_t skip_default_rss_reta; /* Skip configuration of default reta. */ 1380 uint8_t fdb_def_rule; /* Whether fdb jump to table 1 is configured. */ 1381 struct mlx5_mp_id mp_id; /* ID of a multi-process process */ 1382 LIST_HEAD(fdir, mlx5_fdir_flow) fdir_flows; /* fdir flows. */ 1383 rte_spinlock_t shared_act_sl; /* Shared actions spinlock. */ 1384 uint32_t rss_shared_actions; /* RSS shared actions. */ 1385 struct mlx5_devx_obj *q_counters; /* DevX queue counter object. */ 1386 uint32_t counter_set_id; /* Queue counter ID to set in DevX objects. */ 1387 }; 1388 1389 #define PORT_ID(priv) ((priv)->dev_data->port_id) 1390 #define ETH_DEV(priv) (&rte_eth_devices[PORT_ID(priv)]) 1391 1392 struct rte_hairpin_peer_info { 1393 uint32_t qp_id; 1394 uint32_t vhca_id; 1395 uint16_t peer_q; 1396 uint16_t tx_explicit; 1397 uint16_t manual_bind; 1398 }; 1399 1400 /* mlx5.c */ 1401 1402 int mlx5_getenv_int(const char *); 1403 int mlx5_proc_priv_init(struct rte_eth_dev *dev); 1404 void mlx5_proc_priv_uninit(struct rte_eth_dev *dev); 1405 int mlx5_udp_tunnel_port_add(struct rte_eth_dev *dev, 1406 struct rte_eth_udp_tunnel *udp_tunnel); 1407 uint16_t mlx5_eth_find_next(uint16_t port_id, struct rte_pci_device *pci_dev); 1408 int mlx5_dev_close(struct rte_eth_dev *dev); 1409 bool mlx5_is_hpf(struct rte_eth_dev *dev); 1410 void mlx5_age_event_prepare(struct mlx5_dev_ctx_shared *sh); 1411 1412 /* Macro to iterate over all valid ports for mlx5 driver. */ 1413 #define MLX5_ETH_FOREACH_DEV(port_id, pci_dev) \ 1414 for (port_id = mlx5_eth_find_next(0, pci_dev); \ 1415 port_id < RTE_MAX_ETHPORTS; \ 1416 port_id = mlx5_eth_find_next(port_id + 1, pci_dev)) 1417 int mlx5_args(struct mlx5_dev_config *config, struct rte_devargs *devargs); 1418 struct mlx5_dev_ctx_shared * 1419 mlx5_alloc_shared_dev_ctx(const struct mlx5_dev_spawn_data *spawn, 1420 const struct mlx5_dev_config *config); 1421 void mlx5_free_shared_dev_ctx(struct mlx5_dev_ctx_shared *sh); 1422 void mlx5_free_table_hash_list(struct mlx5_priv *priv); 1423 int mlx5_alloc_table_hash_list(struct mlx5_priv *priv); 1424 void mlx5_set_min_inline(struct mlx5_dev_spawn_data *spawn, 1425 struct mlx5_dev_config *config); 1426 void mlx5_set_metadata_mask(struct rte_eth_dev *dev); 1427 int mlx5_dev_check_sibling_config(struct mlx5_priv *priv, 1428 struct mlx5_dev_config *config); 1429 int mlx5_dev_configure(struct rte_eth_dev *dev); 1430 int mlx5_dev_infos_get(struct rte_eth_dev *dev, struct rte_eth_dev_info *info); 1431 int mlx5_fw_version_get(struct rte_eth_dev *dev, char *fw_ver, size_t fw_size); 1432 int mlx5_dev_set_mtu(struct rte_eth_dev *dev, uint16_t mtu); 1433 int mlx5_hairpin_cap_get(struct rte_eth_dev *dev, 1434 struct rte_eth_hairpin_cap *cap); 1435 bool mlx5_flex_parser_ecpri_exist(struct rte_eth_dev *dev); 1436 int mlx5_flex_parser_ecpri_alloc(struct rte_eth_dev *dev); 1437 int mlx5_flow_aso_age_mng_init(struct mlx5_dev_ctx_shared *sh); 1438 int mlx5_aso_flow_mtrs_mng_init(struct mlx5_dev_ctx_shared *sh); 1439 int mlx5_flow_aso_ct_mng_init(struct mlx5_dev_ctx_shared *sh); 1440 1441 /* mlx5_ethdev.c */ 1442 1443 int mlx5_dev_configure(struct rte_eth_dev *dev); 1444 int mlx5_representor_info_get(struct rte_eth_dev *dev, 1445 struct rte_eth_representor_info *info); 1446 #define MLX5_REPRESENTOR_ID(pf, type, repr) \ 1447 (((pf) << 14) + ((type) << 12) + ((repr) & 0xfff)) 1448 #define MLX5_REPRESENTOR_REPR(repr_id) \ 1449 ((repr_id) & 0xfff) 1450 #define MLX5_REPRESENTOR_TYPE(repr_id) \ 1451 (((repr_id) >> 12) & 3) 1452 uint16_t mlx5_representor_id_encode(const struct mlx5_switch_info *info, 1453 enum rte_eth_representor_type hpf_type); 1454 int mlx5_fw_version_get(struct rte_eth_dev *dev, char *fw_ver, 1455 size_t fw_size); 1456 int mlx5_dev_infos_get(struct rte_eth_dev *dev, 1457 struct rte_eth_dev_info *info); 1458 const uint32_t *mlx5_dev_supported_ptypes_get(struct rte_eth_dev *dev); 1459 int mlx5_dev_set_mtu(struct rte_eth_dev *dev, uint16_t mtu); 1460 int mlx5_hairpin_cap_get(struct rte_eth_dev *dev, 1461 struct rte_eth_hairpin_cap *cap); 1462 eth_rx_burst_t mlx5_select_rx_function(struct rte_eth_dev *dev); 1463 struct mlx5_priv *mlx5_port_to_eswitch_info(uint16_t port, bool valid); 1464 struct mlx5_priv *mlx5_dev_to_eswitch_info(struct rte_eth_dev *dev); 1465 int mlx5_dev_configure_rss_reta(struct rte_eth_dev *dev); 1466 1467 /* mlx5_ethdev_os.c */ 1468 1469 int mlx5_get_ifname(const struct rte_eth_dev *dev, 1470 char (*ifname)[MLX5_NAMESIZE]); 1471 unsigned int mlx5_ifindex(const struct rte_eth_dev *dev); 1472 int mlx5_get_mac(struct rte_eth_dev *dev, uint8_t (*mac)[RTE_ETHER_ADDR_LEN]); 1473 int mlx5_get_mtu(struct rte_eth_dev *dev, uint16_t *mtu); 1474 int mlx5_set_mtu(struct rte_eth_dev *dev, uint16_t mtu); 1475 int mlx5_read_clock(struct rte_eth_dev *dev, uint64_t *clock); 1476 int mlx5_link_update(struct rte_eth_dev *dev, int wait_to_complete); 1477 int mlx5_dev_get_flow_ctrl(struct rte_eth_dev *dev, 1478 struct rte_eth_fc_conf *fc_conf); 1479 int mlx5_dev_set_flow_ctrl(struct rte_eth_dev *dev, 1480 struct rte_eth_fc_conf *fc_conf); 1481 void mlx5_dev_interrupt_handler(void *arg); 1482 void mlx5_dev_interrupt_handler_devx(void *arg); 1483 int mlx5_set_link_down(struct rte_eth_dev *dev); 1484 int mlx5_set_link_up(struct rte_eth_dev *dev); 1485 int mlx5_is_removed(struct rte_eth_dev *dev); 1486 int mlx5_sysfs_switch_info(unsigned int ifindex, 1487 struct mlx5_switch_info *info); 1488 void mlx5_translate_port_name(const char *port_name_in, 1489 struct mlx5_switch_info *port_info_out); 1490 void mlx5_intr_callback_unregister(const struct rte_intr_handle *handle, 1491 rte_intr_callback_fn cb_fn, void *cb_arg); 1492 int mlx5_sysfs_bond_info(unsigned int pf_ifindex, unsigned int *ifindex, 1493 char *ifname); 1494 int mlx5_get_module_info(struct rte_eth_dev *dev, 1495 struct rte_eth_dev_module_info *modinfo); 1496 int mlx5_get_module_eeprom(struct rte_eth_dev *dev, 1497 struct rte_dev_eeprom_info *info); 1498 int mlx5_os_read_dev_stat(struct mlx5_priv *priv, 1499 const char *ctr_name, uint64_t *stat); 1500 int mlx5_os_read_dev_counters(struct rte_eth_dev *dev, uint64_t *stats); 1501 int mlx5_os_get_stats_n(struct rte_eth_dev *dev); 1502 void mlx5_os_stats_init(struct rte_eth_dev *dev); 1503 1504 /* mlx5_mac.c */ 1505 1506 void mlx5_mac_addr_remove(struct rte_eth_dev *dev, uint32_t index); 1507 int mlx5_mac_addr_add(struct rte_eth_dev *dev, struct rte_ether_addr *mac, 1508 uint32_t index, uint32_t vmdq); 1509 int mlx5_mac_addr_set(struct rte_eth_dev *dev, struct rte_ether_addr *mac_addr); 1510 int mlx5_set_mc_addr_list(struct rte_eth_dev *dev, 1511 struct rte_ether_addr *mc_addr_set, 1512 uint32_t nb_mc_addr); 1513 1514 /* mlx5_rss.c */ 1515 1516 int mlx5_rss_hash_update(struct rte_eth_dev *dev, 1517 struct rte_eth_rss_conf *rss_conf); 1518 int mlx5_rss_hash_conf_get(struct rte_eth_dev *dev, 1519 struct rte_eth_rss_conf *rss_conf); 1520 int mlx5_rss_reta_index_resize(struct rte_eth_dev *dev, unsigned int reta_size); 1521 int mlx5_dev_rss_reta_query(struct rte_eth_dev *dev, 1522 struct rte_eth_rss_reta_entry64 *reta_conf, 1523 uint16_t reta_size); 1524 int mlx5_dev_rss_reta_update(struct rte_eth_dev *dev, 1525 struct rte_eth_rss_reta_entry64 *reta_conf, 1526 uint16_t reta_size); 1527 1528 /* mlx5_rxmode.c */ 1529 1530 int mlx5_promiscuous_enable(struct rte_eth_dev *dev); 1531 int mlx5_promiscuous_disable(struct rte_eth_dev *dev); 1532 int mlx5_allmulticast_enable(struct rte_eth_dev *dev); 1533 int mlx5_allmulticast_disable(struct rte_eth_dev *dev); 1534 1535 /* mlx5_stats.c */ 1536 1537 int mlx5_stats_get(struct rte_eth_dev *dev, struct rte_eth_stats *stats); 1538 int mlx5_stats_reset(struct rte_eth_dev *dev); 1539 int mlx5_xstats_get(struct rte_eth_dev *dev, struct rte_eth_xstat *stats, 1540 unsigned int n); 1541 int mlx5_xstats_reset(struct rte_eth_dev *dev); 1542 int mlx5_xstats_get_names(struct rte_eth_dev *dev __rte_unused, 1543 struct rte_eth_xstat_name *xstats_names, 1544 unsigned int n); 1545 1546 /* mlx5_vlan.c */ 1547 1548 int mlx5_vlan_filter_set(struct rte_eth_dev *dev, uint16_t vlan_id, int on); 1549 void mlx5_vlan_strip_queue_set(struct rte_eth_dev *dev, uint16_t queue, int on); 1550 int mlx5_vlan_offload_set(struct rte_eth_dev *dev, int mask); 1551 1552 /* mlx5_vlan_os.c */ 1553 1554 void mlx5_vlan_vmwa_exit(void *ctx); 1555 void mlx5_vlan_vmwa_release(struct rte_eth_dev *dev, 1556 struct mlx5_vf_vlan *vf_vlan); 1557 void mlx5_vlan_vmwa_acquire(struct rte_eth_dev *dev, 1558 struct mlx5_vf_vlan *vf_vlan); 1559 void *mlx5_vlan_vmwa_init(struct rte_eth_dev *dev, uint32_t ifindex); 1560 1561 /* mlx5_trigger.c */ 1562 1563 int mlx5_dev_start(struct rte_eth_dev *dev); 1564 int mlx5_dev_stop(struct rte_eth_dev *dev); 1565 int mlx5_traffic_enable(struct rte_eth_dev *dev); 1566 void mlx5_traffic_disable(struct rte_eth_dev *dev); 1567 int mlx5_traffic_restart(struct rte_eth_dev *dev); 1568 int mlx5_hairpin_queue_peer_update(struct rte_eth_dev *dev, uint16_t peer_queue, 1569 struct rte_hairpin_peer_info *current_info, 1570 struct rte_hairpin_peer_info *peer_info, 1571 uint32_t direction); 1572 int mlx5_hairpin_queue_peer_bind(struct rte_eth_dev *dev, uint16_t cur_queue, 1573 struct rte_hairpin_peer_info *peer_info, 1574 uint32_t direction); 1575 int mlx5_hairpin_queue_peer_unbind(struct rte_eth_dev *dev, uint16_t cur_queue, 1576 uint32_t direction); 1577 int mlx5_hairpin_bind(struct rte_eth_dev *dev, uint16_t rx_port); 1578 int mlx5_hairpin_unbind(struct rte_eth_dev *dev, uint16_t rx_port); 1579 int mlx5_hairpin_get_peer_ports(struct rte_eth_dev *dev, uint16_t *peer_ports, 1580 size_t len, uint32_t direction); 1581 1582 /* mlx5_flow.c */ 1583 1584 int mlx5_flow_discover_mreg_c(struct rte_eth_dev *eth_dev); 1585 bool mlx5_flow_ext_mreg_supported(struct rte_eth_dev *dev); 1586 void mlx5_flow_print(struct rte_flow *flow); 1587 int mlx5_flow_validate(struct rte_eth_dev *dev, 1588 const struct rte_flow_attr *attr, 1589 const struct rte_flow_item items[], 1590 const struct rte_flow_action actions[], 1591 struct rte_flow_error *error); 1592 struct rte_flow *mlx5_flow_create(struct rte_eth_dev *dev, 1593 const struct rte_flow_attr *attr, 1594 const struct rte_flow_item items[], 1595 const struct rte_flow_action actions[], 1596 struct rte_flow_error *error); 1597 int mlx5_flow_destroy(struct rte_eth_dev *dev, struct rte_flow *flow, 1598 struct rte_flow_error *error); 1599 void mlx5_flow_list_flush(struct rte_eth_dev *dev, uint32_t *list, bool active); 1600 int mlx5_flow_flush(struct rte_eth_dev *dev, struct rte_flow_error *error); 1601 int mlx5_flow_query(struct rte_eth_dev *dev, struct rte_flow *flow, 1602 const struct rte_flow_action *action, void *data, 1603 struct rte_flow_error *error); 1604 int mlx5_flow_isolate(struct rte_eth_dev *dev, int enable, 1605 struct rte_flow_error *error); 1606 int mlx5_flow_ops_get(struct rte_eth_dev *dev, const struct rte_flow_ops **ops); 1607 int mlx5_flow_start_default(struct rte_eth_dev *dev); 1608 void mlx5_flow_stop_default(struct rte_eth_dev *dev); 1609 int mlx5_flow_verify(struct rte_eth_dev *dev); 1610 int mlx5_ctrl_flow_source_queue(struct rte_eth_dev *dev, uint32_t queue); 1611 int mlx5_ctrl_flow_vlan(struct rte_eth_dev *dev, 1612 struct rte_flow_item_eth *eth_spec, 1613 struct rte_flow_item_eth *eth_mask, 1614 struct rte_flow_item_vlan *vlan_spec, 1615 struct rte_flow_item_vlan *vlan_mask); 1616 int mlx5_ctrl_flow(struct rte_eth_dev *dev, 1617 struct rte_flow_item_eth *eth_spec, 1618 struct rte_flow_item_eth *eth_mask); 1619 int mlx5_flow_lacp_miss(struct rte_eth_dev *dev); 1620 struct rte_flow *mlx5_flow_create_esw_table_zero_flow(struct rte_eth_dev *dev); 1621 void mlx5_flow_async_pool_query_handle(struct mlx5_dev_ctx_shared *sh, 1622 uint64_t async_id, int status); 1623 void mlx5_set_query_alarm(struct mlx5_dev_ctx_shared *sh); 1624 void mlx5_flow_query_alarm(void *arg); 1625 uint32_t mlx5_counter_alloc(struct rte_eth_dev *dev); 1626 void mlx5_counter_free(struct rte_eth_dev *dev, uint32_t cnt); 1627 int mlx5_counter_query(struct rte_eth_dev *dev, uint32_t cnt, 1628 bool clear, uint64_t *pkts, uint64_t *bytes); 1629 int mlx5_flow_dev_dump(struct rte_eth_dev *dev, struct rte_flow *flow, 1630 FILE *file, struct rte_flow_error *error); 1631 void mlx5_flow_rxq_dynf_metadata_set(struct rte_eth_dev *dev); 1632 int mlx5_flow_get_aged_flows(struct rte_eth_dev *dev, void **contexts, 1633 uint32_t nb_contexts, struct rte_flow_error *error); 1634 int mlx5_validate_action_ct(struct rte_eth_dev *dev, 1635 const struct rte_flow_action_conntrack *conntrack, 1636 struct rte_flow_error *error); 1637 1638 1639 /* mlx5_mp_os.c */ 1640 1641 int mlx5_mp_os_primary_handle(const struct rte_mp_msg *mp_msg, 1642 const void *peer); 1643 int mlx5_mp_os_secondary_handle(const struct rte_mp_msg *mp_msg, 1644 const void *peer); 1645 void mlx5_mp_os_req_start_rxtx(struct rte_eth_dev *dev); 1646 void mlx5_mp_os_req_stop_rxtx(struct rte_eth_dev *dev); 1647 int mlx5_mp_os_req_queue_control(struct rte_eth_dev *dev, uint16_t queue_id, 1648 enum mlx5_mp_req_type req_type); 1649 1650 /* mlx5_socket.c */ 1651 1652 int mlx5_pmd_socket_init(void); 1653 1654 /* mlx5_flow_meter.c */ 1655 1656 int mlx5_flow_meter_ops_get(struct rte_eth_dev *dev, void *arg); 1657 struct mlx5_flow_meter_info *mlx5_flow_meter_find(struct mlx5_priv *priv, 1658 uint32_t meter_id, uint32_t *mtr_idx); 1659 struct mlx5_flow_meter_info * 1660 flow_dv_meter_find_by_idx(struct mlx5_priv *priv, uint32_t idx); 1661 int mlx5_flow_meter_attach(struct mlx5_priv *priv, 1662 struct mlx5_flow_meter_info *fm, 1663 const struct rte_flow_attr *attr, 1664 struct rte_flow_error *error); 1665 void mlx5_flow_meter_detach(struct mlx5_priv *priv, 1666 struct mlx5_flow_meter_info *fm); 1667 struct mlx5_flow_meter_policy *mlx5_flow_meter_policy_find 1668 (struct rte_eth_dev *dev, 1669 uint32_t policy_id, 1670 uint32_t *policy_idx); 1671 int mlx5_flow_meter_flush(struct rte_eth_dev *dev, 1672 struct rte_mtr_error *error); 1673 void mlx5_flow_meter_rxq_flush(struct rte_eth_dev *dev); 1674 1675 /* mlx5_os.c */ 1676 struct rte_pci_driver; 1677 int mlx5_os_get_dev_attr(void *ctx, struct mlx5_dev_attr *dev_attr); 1678 void mlx5_os_free_shared_dr(struct mlx5_priv *priv); 1679 int mlx5_os_open_device(const struct mlx5_dev_spawn_data *spawn, 1680 const struct mlx5_dev_config *config, 1681 struct mlx5_dev_ctx_shared *sh); 1682 int mlx5_os_get_pdn(void *pd, uint32_t *pdn); 1683 int mlx5_os_pci_probe(struct rte_pci_driver *pci_drv __rte_unused, 1684 struct rte_pci_device *pci_dev); 1685 void mlx5_os_dev_shared_handler_install(struct mlx5_dev_ctx_shared *sh); 1686 void mlx5_os_dev_shared_handler_uninstall(struct mlx5_dev_ctx_shared *sh); 1687 void mlx5_os_set_reg_mr_cb(mlx5_reg_mr_t *reg_mr_cb, 1688 mlx5_dereg_mr_t *dereg_mr_cb); 1689 void mlx5_os_mac_addr_remove(struct rte_eth_dev *dev, uint32_t index); 1690 int mlx5_os_mac_addr_add(struct rte_eth_dev *dev, struct rte_ether_addr *mac, 1691 uint32_t index); 1692 int mlx5_os_vf_mac_addr_modify(struct mlx5_priv *priv, unsigned int iface_idx, 1693 struct rte_ether_addr *mac_addr, 1694 int vf_index); 1695 int mlx5_os_set_promisc(struct rte_eth_dev *dev, int enable); 1696 int mlx5_os_set_allmulti(struct rte_eth_dev *dev, int enable); 1697 int mlx5_os_set_nonblock_channel_fd(int fd); 1698 void mlx5_os_mac_addr_flush(struct rte_eth_dev *dev); 1699 1700 /* mlx5_txpp.c */ 1701 1702 int mlx5_txpp_start(struct rte_eth_dev *dev); 1703 void mlx5_txpp_stop(struct rte_eth_dev *dev); 1704 int mlx5_txpp_read_clock(struct rte_eth_dev *dev, uint64_t *timestamp); 1705 int mlx5_txpp_xstats_get(struct rte_eth_dev *dev, 1706 struct rte_eth_xstat *stats, 1707 unsigned int n, unsigned int n_used); 1708 int mlx5_txpp_xstats_reset(struct rte_eth_dev *dev); 1709 int mlx5_txpp_xstats_get_names(struct rte_eth_dev *dev, 1710 struct rte_eth_xstat_name *xstats_names, 1711 unsigned int n, unsigned int n_used); 1712 void mlx5_txpp_interrupt_handler(void *cb_arg); 1713 1714 /* mlx5_rxtx.c */ 1715 1716 eth_tx_burst_t mlx5_select_tx_function(struct rte_eth_dev *dev); 1717 1718 /* mlx5_flow_aso.c */ 1719 1720 int mlx5_aso_queue_init(struct mlx5_dev_ctx_shared *sh, 1721 enum mlx5_access_aso_opc_mod aso_opc_mod); 1722 int mlx5_aso_flow_hit_queue_poll_start(struct mlx5_dev_ctx_shared *sh); 1723 int mlx5_aso_flow_hit_queue_poll_stop(struct mlx5_dev_ctx_shared *sh); 1724 void mlx5_aso_queue_uninit(struct mlx5_dev_ctx_shared *sh, 1725 enum mlx5_access_aso_opc_mod aso_opc_mod); 1726 int mlx5_aso_meter_update_by_wqe(struct mlx5_dev_ctx_shared *sh, 1727 struct mlx5_aso_mtr *mtr); 1728 int mlx5_aso_mtr_wait(struct mlx5_dev_ctx_shared *sh, 1729 struct mlx5_aso_mtr *mtr); 1730 int mlx5_aso_ct_update_by_wqe(struct mlx5_dev_ctx_shared *sh, 1731 struct mlx5_aso_ct_action *ct, 1732 const struct rte_flow_action_conntrack *profile); 1733 int mlx5_aso_ct_wait_ready(struct mlx5_dev_ctx_shared *sh, 1734 struct mlx5_aso_ct_action *ct); 1735 int mlx5_aso_ct_query_by_wqe(struct mlx5_dev_ctx_shared *sh, 1736 struct mlx5_aso_ct_action *ct, 1737 struct rte_flow_action_conntrack *profile); 1738 int mlx5_aso_ct_available(struct mlx5_dev_ctx_shared *sh, 1739 struct mlx5_aso_ct_action *ct); 1740 1741 #endif /* RTE_PMD_MLX5_H_ */ 1742