1 /* SPDX-License-Identifier: BSD-3-Clause 2 * Copyright 2015 6WIND S.A. 3 * Copyright 2015 Mellanox Technologies, Ltd 4 */ 5 6 #ifndef RTE_PMD_MLX5_H_ 7 #define RTE_PMD_MLX5_H_ 8 9 #include <stddef.h> 10 #include <stdbool.h> 11 #include <stdint.h> 12 #include <limits.h> 13 #include <sys/queue.h> 14 15 #include <rte_pci.h> 16 #include <rte_ether.h> 17 #include <ethdev_driver.h> 18 #include <rte_rwlock.h> 19 #include <rte_interrupts.h> 20 #include <rte_errno.h> 21 #include <rte_flow.h> 22 #include <rte_mtr.h> 23 24 #include <mlx5_glue.h> 25 #include <mlx5_devx_cmds.h> 26 #include <mlx5_prm.h> 27 #include <mlx5_common_mp.h> 28 #include <mlx5_common_mr.h> 29 #include <mlx5_common_devx.h> 30 #include <mlx5_common_defs.h> 31 32 #include "mlx5_defs.h" 33 #include "mlx5_utils.h" 34 #include "mlx5_os.h" 35 #include "mlx5_autoconf.h" 36 #include "rte_pmd_mlx5.h" 37 #if defined(HAVE_IBV_FLOW_DV_SUPPORT) || !defined(HAVE_INFINIBAND_VERBS_H) 38 #ifndef RTE_EXEC_ENV_WINDOWS 39 #define HAVE_MLX5_HWS_SUPPORT 1 40 #else 41 #define __be64 uint64_t 42 #endif 43 #include "hws/mlx5dr.h" 44 #endif 45 46 #define MLX5_SH(dev) (((struct mlx5_priv *)(dev)->data->dev_private)->sh) 47 48 #define MLX5_HW_INV_QUEUE UINT32_MAX 49 50 /* 51 * The default ipool threshold value indicates which per_core_cache 52 * value to set. 53 */ 54 #define MLX5_HW_IPOOL_SIZE_THRESHOLD (1 << 19) 55 /* The default min local cache size. */ 56 #define MLX5_HW_IPOOL_CACHE_MIN (1 << 9) 57 58 /* 59 * Number of modification commands. 60 * The maximal actions amount in FW is some constant, and it is 16 in the 61 * latest releases. In some old releases, it will be limited to 8. 62 * Since there is no interface to query the capacity, the maximal value should 63 * be used to allow PMD to create the flow. The validation will be done in the 64 * lower driver layer or FW. A failure will be returned if exceeds the maximal 65 * supported actions number on the root table. 66 * On non-root tables, there is no limitation, but 32 is enough right now. 67 */ 68 #define MLX5_MAX_MODIFY_NUM 32 69 #define MLX5_ROOT_TBL_MODIFY_NUM 16 70 71 /* Maximal number of flex items created on the port.*/ 72 #define MLX5_PORT_FLEX_ITEM_NUM 4 73 74 /* Maximal number of field/field parts to map into sample registers .*/ 75 #define MLX5_FLEX_ITEM_MAPPING_NUM 32 76 77 enum mlx5_ipool_index { 78 #if defined(HAVE_IBV_FLOW_DV_SUPPORT) || !defined(HAVE_INFINIBAND_VERBS_H) 79 MLX5_IPOOL_DECAP_ENCAP = 0, /* Pool for encap/decap resource. */ 80 MLX5_IPOOL_PUSH_VLAN, /* Pool for push vlan resource. */ 81 MLX5_IPOOL_TAG, /* Pool for tag resource. */ 82 MLX5_IPOOL_PORT_ID, /* Pool for port id resource. */ 83 MLX5_IPOOL_JUMP, /* Pool for SWS jump resource. */ 84 /* Pool for HWS group. Jump action will be created internally. */ 85 MLX5_IPOOL_HW_GRP = MLX5_IPOOL_JUMP, 86 MLX5_IPOOL_SAMPLE, /* Pool for sample resource. */ 87 MLX5_IPOOL_DEST_ARRAY, /* Pool for destination array resource. */ 88 MLX5_IPOOL_TUNNEL_ID, /* Pool for tunnel offload context */ 89 MLX5_IPOOL_TNL_TBL_ID, /* Pool for tunnel table ID. */ 90 #endif 91 MLX5_IPOOL_MTR, /* Pool for meter resource. */ 92 MLX5_IPOOL_MCP, /* Pool for metadata resource. */ 93 MLX5_IPOOL_HRXQ, /* Pool for hrxq resource. */ 94 MLX5_IPOOL_MLX5_FLOW, /* Pool for mlx5 flow handle. */ 95 MLX5_IPOOL_RTE_FLOW, /* Pool for rte_flow. */ 96 MLX5_IPOOL_RSS_EXPANTION_FLOW_ID, /* Pool for Queue/RSS flow ID. */ 97 MLX5_IPOOL_RSS_SHARED_ACTIONS, /* Pool for RSS shared actions. */ 98 MLX5_IPOOL_MTR_POLICY, /* Pool for meter policy resource. */ 99 MLX5_IPOOL_MAX, 100 }; 101 102 /* 103 * There are three reclaim memory mode supported. 104 * 0(none) means no memory reclaim. 105 * 1(light) means only PMD level reclaim. 106 * 2(aggressive) means both PMD and rdma-core level reclaim. 107 */ 108 enum mlx5_reclaim_mem_mode { 109 MLX5_RCM_NONE, /* Don't reclaim memory. */ 110 MLX5_RCM_LIGHT, /* Reclaim PMD level. */ 111 MLX5_RCM_AGGR, /* Reclaim PMD and rdma-core level. */ 112 }; 113 114 /* The type of flow. */ 115 enum mlx5_flow_type { 116 MLX5_FLOW_TYPE_CTL, /* Control flow. */ 117 MLX5_FLOW_TYPE_GEN, /* General flow. */ 118 MLX5_FLOW_TYPE_MCP, /* MCP flow. */ 119 MLX5_FLOW_TYPE_MAXI, 120 }; 121 122 /* The mode of delay drop for Rx queues. */ 123 enum mlx5_delay_drop_mode { 124 MLX5_DELAY_DROP_NONE = 0, /* All disabled. */ 125 MLX5_DELAY_DROP_STANDARD = RTE_BIT32(0), /* Standard queues enable. */ 126 MLX5_DELAY_DROP_HAIRPIN = RTE_BIT32(1), /* Hairpin queues enable. */ 127 }; 128 129 /* The HWS action type root/non-root. */ 130 enum mlx5_hw_action_flag_type { 131 MLX5_HW_ACTION_FLAG_ROOT, /* Root action. */ 132 MLX5_HW_ACTION_FLAG_NONE_ROOT, /* Non-root ation. */ 133 MLX5_HW_ACTION_FLAG_MAX, /* Maximum action flag. */ 134 }; 135 136 /* Hlist and list callback context. */ 137 struct mlx5_flow_cb_ctx { 138 struct rte_eth_dev *dev; 139 struct rte_flow_error *error; 140 void *data; 141 void *data2; 142 }; 143 144 /* Device capabilities structure which isn't changed in any stage. */ 145 struct mlx5_dev_cap { 146 int max_cq; /* Maximum number of supported CQs */ 147 int max_qp; /* Maximum number of supported QPs. */ 148 int max_qp_wr; /* Maximum number of outstanding WR on any WQ. */ 149 int max_sge; 150 /* Maximum number of s/g per WR for SQ & RQ of QP for non RDMA Read 151 * operations. 152 */ 153 int mps; /* Multi-packet send supported mode. */ 154 uint32_t vf:1; /* This is a VF. */ 155 uint32_t sf:1; /* This is a SF. */ 156 uint32_t txpp_en:1; /* Tx packet pacing is supported. */ 157 uint32_t mpls_en:1; /* MPLS over GRE/UDP is supported. */ 158 uint32_t cqe_comp:1; /* CQE compression is supported. */ 159 uint32_t hw_csum:1; /* Checksum offload is supported. */ 160 uint32_t hw_padding:1; /* End alignment padding is supported. */ 161 uint32_t dest_tir:1; /* Whether advanced DR API is available. */ 162 uint32_t dv_esw_en:1; /* E-Switch DV flow is supported. */ 163 uint32_t dv_flow_en:1; /* DV flow is supported. */ 164 uint32_t swp:3; /* Tx generic tunnel checksum and TSO offload. */ 165 uint32_t hw_vlan_strip:1; /* VLAN stripping is supported. */ 166 uint32_t scatter_fcs_w_decap_disable:1; 167 /* HW has bug working with tunnel packet decap and scatter FCS. */ 168 uint32_t hw_fcs_strip:1; /* FCS stripping is supported. */ 169 uint32_t rt_timestamp:1; /* Realtime timestamp format. */ 170 uint32_t rq_delay_drop_en:1; /* Enable RxQ delay drop. */ 171 uint32_t tunnel_en:3; 172 /* Whether tunnel stateless offloads are supported. */ 173 uint32_t ind_table_max_size; 174 /* Maximum receive WQ indirection table size. */ 175 uint32_t tso:1; /* Whether TSO is supported. */ 176 uint32_t tso_max_payload_sz; /* Maximum TCP payload for TSO. */ 177 struct { 178 uint32_t enabled:1; /* Whether MPRQ is enabled. */ 179 uint32_t log_min_stride_size; /* Log min size of a stride. */ 180 uint32_t log_max_stride_size; /* Log max size of a stride. */ 181 uint32_t log_min_stride_num; /* Log min num of strides. */ 182 uint32_t log_max_stride_num; /* Log max num of strides. */ 183 uint32_t log_min_stride_wqe_size; 184 /* Log min WQE size, (size of single stride)*(num of strides).*/ 185 } mprq; /* Capability for Multi-Packet RQ. */ 186 char fw_ver[64]; /* Firmware version of this device. */ 187 }; 188 189 #define MLX5_MPESW_PORT_INVALID (-1) 190 191 /** Data associated with devices to spawn. */ 192 struct mlx5_dev_spawn_data { 193 uint32_t ifindex; /**< Network interface index. */ 194 uint32_t max_port; /**< Device maximal port index. */ 195 uint32_t phys_port; /**< Device physical port index. */ 196 int pf_bond; /**< bonding device PF index. < 0 - no bonding */ 197 int mpesw_port; /**< MPESW uplink index. Valid if mpesw_owner_port >= 0. */ 198 struct mlx5_switch_info info; /**< Switch information. */ 199 const char *phys_dev_name; /**< Name of physical device. */ 200 struct rte_eth_dev *eth_dev; /**< Associated Ethernet device. */ 201 struct rte_pci_device *pci_dev; /**< Backend PCI device. */ 202 struct mlx5_common_device *cdev; /**< Backend common device. */ 203 struct mlx5_bond_info *bond_info; 204 }; 205 206 /** 207 * Check if the port requested to be probed is MPESW physical device 208 * or a representor port. 209 * 210 * @param spawn 211 * Parameters of the probed port. 212 * 213 * @return 214 * True if the probed port is a physical device or representor in MPESW setup. 215 * False otherwise or MPESW was not configured. 216 */ 217 static inline bool 218 mlx5_is_probed_port_on_mpesw_device(struct mlx5_dev_spawn_data *spawn) 219 { 220 return spawn->mpesw_port >= 0; 221 } 222 223 /** Data associated with socket messages. */ 224 struct mlx5_flow_dump_req { 225 uint32_t port_id; /**< There are plans in DPDK to extend port_id. */ 226 uint64_t flow_id; 227 } __rte_packed; 228 229 struct mlx5_flow_dump_ack { 230 int rc; /**< Return code. */ 231 }; 232 233 LIST_HEAD(mlx5_dev_list, mlx5_dev_ctx_shared); 234 235 /* Shared data between primary and secondary processes. */ 236 struct mlx5_shared_data { 237 rte_spinlock_t lock; 238 /* Global spinlock for primary and secondary processes. */ 239 int init_done; /* Whether primary has done initialization. */ 240 unsigned int secondary_cnt; /* Number of secondary processes init'd. */ 241 }; 242 243 /* Per-process data structure, not visible to other processes. */ 244 struct mlx5_local_data { 245 int init_done; /* Whether a secondary has done initialization. */ 246 }; 247 248 extern struct mlx5_shared_data *mlx5_shared_data; 249 250 /* Dev ops structs */ 251 extern const struct eth_dev_ops mlx5_dev_ops; 252 extern const struct eth_dev_ops mlx5_dev_sec_ops; 253 extern const struct eth_dev_ops mlx5_dev_ops_isolate; 254 255 struct mlx5_counter_ctrl { 256 /* Name of the counter. */ 257 char dpdk_name[RTE_ETH_XSTATS_NAME_SIZE]; 258 /* Name of the counter on the device table. */ 259 char ctr_name[RTE_ETH_XSTATS_NAME_SIZE]; 260 uint32_t dev:1; /**< Nonzero for dev counters. */ 261 }; 262 263 struct mlx5_xstats_ctrl { 264 /* Number of device stats. */ 265 uint16_t stats_n; 266 /* Number of device stats identified by PMD. */ 267 uint16_t mlx5_stats_n; 268 /* Index in the device counters table. */ 269 uint16_t dev_table_idx[MLX5_MAX_XSTATS]; 270 uint64_t base[MLX5_MAX_XSTATS]; 271 uint64_t xstats[MLX5_MAX_XSTATS]; 272 uint64_t hw_stats[MLX5_MAX_XSTATS]; 273 struct mlx5_counter_ctrl info[MLX5_MAX_XSTATS]; 274 }; 275 276 struct mlx5_stats_ctrl { 277 /* Base for imissed counter. */ 278 uint64_t imissed_base; 279 uint64_t imissed; 280 }; 281 282 /* Maximal size of coalesced segment for LRO is set in chunks of 256 Bytes. */ 283 #define MLX5_LRO_SEG_CHUNK_SIZE 256u 284 285 /* Maximal size of aggregated LRO packet. */ 286 #define MLX5_MAX_LRO_SIZE (UINT8_MAX * MLX5_LRO_SEG_CHUNK_SIZE) 287 288 /* Maximal number of segments to split. */ 289 #define MLX5_MAX_RXQ_NSEG (1u << MLX5_MAX_LOG_RQ_SEGS) 290 291 /* 292 * Port configuration structure. 293 * User device parameters disabled features. 294 * This structure contains all configurations coming from devargs which 295 * oriented to port. When probing again, devargs doesn't have to be compatible 296 * with primary devargs. It is updated for each port in spawn function. 297 */ 298 struct mlx5_port_config { 299 unsigned int hw_vlan_insert:1; /* VLAN insertion in WQE is supported. */ 300 unsigned int hw_padding:1; /* End alignment padding is supported. */ 301 unsigned int cqe_comp:1; /* CQE compression is enabled. */ 302 unsigned int enh_cqe_comp:1; /* Enhanced CQE compression is enabled. */ 303 unsigned int cqe_comp_fmt:3; /* CQE compression format. */ 304 unsigned int rx_vec_en:1; /* Rx vector is enabled. */ 305 unsigned int std_delay_drop:1; /* Enable standard Rxq delay drop. */ 306 unsigned int hp_delay_drop:1; /* Enable hairpin Rxq delay drop. */ 307 struct { 308 unsigned int enabled:1; /* Whether MPRQ is enabled. */ 309 unsigned int log_stride_num; /* Log number of strides. */ 310 unsigned int log_stride_size; /* Log size of a stride. */ 311 unsigned int max_memcpy_len; 312 /* Maximum packet size to memcpy Rx packets. */ 313 unsigned int min_rxqs_num; 314 /* Rx queue count threshold to enable MPRQ. */ 315 } mprq; /* Configurations for Multi-Packet RQ. */ 316 int mps; /* Multi-packet send supported mode. */ 317 unsigned int max_dump_files_num; /* Maximum dump files per queue. */ 318 unsigned int log_hp_size; /* Single hairpin queue data size in total. */ 319 unsigned int lro_timeout; /* LRO user configuration. */ 320 int txqs_inline; /* Queue number threshold for inlining. */ 321 int txq_inline_min; /* Minimal amount of data bytes to inline. */ 322 int txq_inline_max; /* Max packet size for inlining with SEND. */ 323 int txq_inline_mpw; /* Max packet size for inlining with eMPW. */ 324 }; 325 326 /* 327 * Share context device configuration structure. 328 * User device parameters disabled features. 329 * This structure updated once for device in mlx5_alloc_shared_dev_ctx() 330 * function and cannot change even when probing again. 331 */ 332 struct mlx5_sh_config { 333 int tx_pp; /* Timestamp scheduling granularity in nanoseconds. */ 334 int tx_skew; /* Tx scheduling skew between WQE and data on wire. */ 335 uint32_t reclaim_mode:2; /* Memory reclaim mode. */ 336 uint32_t dv_esw_en:1; /* Enable E-Switch DV flow. */ 337 /* Enable DV flow. 1 means SW steering, 2 means HW steering. */ 338 uint32_t dv_flow_en:2; /* Enable DV flow. */ 339 uint32_t dv_xmeta_en:3; /* Enable extensive flow metadata. */ 340 uint32_t dv_miss_info:1; /* Restore packet after partial hw miss. */ 341 uint32_t l3_vxlan_en:1; /* Enable L3 VXLAN flow creation. */ 342 uint32_t vf_nl_en:1; /* Enable Netlink requests in VF mode. */ 343 uint32_t lacp_by_user:1; /* Enable user to manage LACP traffic. */ 344 uint32_t decap_en:1; /* Whether decap will be used or not. */ 345 uint32_t hw_fcs_strip:1; /* FCS stripping is supported. */ 346 uint32_t allow_duplicate_pattern:1; 347 uint32_t lro_allowed:1; /* Whether LRO is allowed. */ 348 struct { 349 uint16_t service_core; 350 uint32_t cycle_time; /* query cycle time in milli-second. */ 351 } cnt_svc; /* configure for HW steering's counter's service. */ 352 /* Allow/Prevent the duplicate rules pattern. */ 353 uint32_t fdb_def_rule:1; /* Create FDB default jump rule */ 354 uint32_t repr_matching:1; /* Enable implicit vport matching in HWS FDB. */ 355 }; 356 357 /* Structure for VF VLAN workaround. */ 358 struct mlx5_vf_vlan { 359 uint32_t tag:12; 360 uint32_t created:1; 361 }; 362 363 /* Flow drop context necessary due to Verbs API. */ 364 struct mlx5_drop { 365 struct mlx5_hrxq *hrxq; /* Hash Rx queue queue. */ 366 struct mlx5_rxq_priv *rxq; /* Rx queue. */ 367 }; 368 369 /* Loopback dummy queue resources required due to Verbs API. */ 370 struct mlx5_lb_ctx { 371 struct ibv_qp *qp; /* QP object. */ 372 void *ibv_cq; /* Completion queue. */ 373 uint16_t refcnt; /* Reference count for representors. */ 374 }; 375 376 /* HW steering queue job descriptor type. */ 377 enum mlx5_hw_job_type { 378 MLX5_HW_Q_JOB_TYPE_CREATE, /* Flow create job type. */ 379 MLX5_HW_Q_JOB_TYPE_DESTROY, /* Flow destroy job type. */ 380 MLX5_HW_Q_JOB_TYPE_UPDATE, /* Flow update job type. */ 381 MLX5_HW_Q_JOB_TYPE_QUERY, /* Flow query job type. */ 382 MLX5_HW_Q_JOB_TYPE_UPDATE_QUERY, /* Flow update and query job type. */ 383 }; 384 385 enum mlx5_hw_indirect_type { 386 MLX5_HW_INDIRECT_TYPE_LEGACY, 387 MLX5_HW_INDIRECT_TYPE_LIST 388 }; 389 390 #define MLX5_HW_MAX_ITEMS (16) 391 392 /* HW steering flow management job descriptor. */ 393 struct mlx5_hw_q_job { 394 uint32_t type; /* Job type. */ 395 uint32_t indirect_type; 396 union { 397 struct rte_flow_hw *flow; /* Flow attached to the job. */ 398 const void *action; /* Indirect action attached to the job. */ 399 }; 400 void *user_data; /* Job user data. */ 401 uint8_t *encap_data; /* Encap data. */ 402 uint8_t *push_data; /* IPv6 routing push data. */ 403 struct mlx5_modification_cmd *mhdr_cmd; 404 struct rte_flow_item *items; 405 union { 406 struct { 407 /* User memory for query output */ 408 void *user; 409 /* Data extracted from hardware */ 410 void *hw; 411 } __rte_packed query; 412 struct rte_flow_item_ethdev port_spec; 413 struct rte_flow_item_tag tag_spec; 414 } __rte_packed; 415 struct rte_flow_hw *upd_flow; /* Flow with updated values. */ 416 }; 417 418 /* HW steering job descriptor LIFO pool. */ 419 struct mlx5_hw_q { 420 uint32_t job_idx; /* Free job index. */ 421 uint32_t size; /* LIFO size. */ 422 struct mlx5_hw_q_job **job; /* LIFO header. */ 423 struct rte_ring *indir_cq; /* Indirect action SW completion queue. */ 424 struct rte_ring *indir_iq; /* Indirect action SW in progress queue. */ 425 } __rte_cache_aligned; 426 427 428 #define MLX5_COUNTER_POOLS_MAX_NUM (1 << 15) 429 #define MLX5_COUNTERS_PER_POOL 512 430 #define MLX5_MAX_PENDING_QUERIES 4 431 #define MLX5_CNT_MR_ALLOC_BULK 64 432 #define MLX5_CNT_SHARED_OFFSET 0x80000000 433 #define IS_BATCH_CNT(cnt) (((cnt) & (MLX5_CNT_SHARED_OFFSET - 1)) >= \ 434 MLX5_CNT_BATCH_OFFSET) 435 #define MLX5_CNT_SIZE (sizeof(struct mlx5_flow_counter)) 436 #define MLX5_AGE_SIZE (sizeof(struct mlx5_age_param)) 437 438 #define MLX5_CNT_LEN(pool) \ 439 (MLX5_CNT_SIZE + \ 440 ((pool)->is_aged ? MLX5_AGE_SIZE : 0)) 441 #define MLX5_POOL_GET_CNT(pool, index) \ 442 ((struct mlx5_flow_counter *) \ 443 ((uint8_t *)((pool) + 1) + (index) * (MLX5_CNT_LEN(pool)))) 444 #define MLX5_CNT_ARRAY_IDX(pool, cnt) \ 445 ((int)(((uint8_t *)(cnt) - (uint8_t *)((pool) + 1)) / \ 446 MLX5_CNT_LEN(pool))) 447 #define MLX5_TS_MASK_SECS 8ull 448 /* timestamp wrapping in seconds, must be power of 2. */ 449 450 /* 451 * The pool index and offset of counter in the pool array makes up the 452 * counter index. In case the counter is from pool 0 and offset 0, it 453 * should plus 1 to avoid index 0, since 0 means invalid counter index 454 * currently. 455 */ 456 #define MLX5_MAKE_CNT_IDX(pi, offset) \ 457 ((pi) * MLX5_COUNTERS_PER_POOL + (offset) + 1) 458 #define MLX5_CNT_TO_AGE(cnt) \ 459 ((struct mlx5_age_param *)((cnt) + 1)) 460 /* 461 * The maximum single counter is 0x800000 as MLX5_CNT_BATCH_OFFSET 462 * defines. The pool size is 512, pool index should never reach 463 * INT16_MAX. 464 */ 465 #define POOL_IDX_INVALID UINT16_MAX 466 467 /* Age status. */ 468 enum { 469 AGE_FREE, /* Initialized state. */ 470 AGE_CANDIDATE, /* Counter assigned to flows. */ 471 AGE_TMOUT, /* Timeout, wait for rte_flow_get_aged_flows and destroy. */ 472 }; 473 474 enum mlx5_counter_type { 475 MLX5_COUNTER_TYPE_ORIGIN, 476 MLX5_COUNTER_TYPE_AGE, 477 MLX5_COUNTER_TYPE_MAX, 478 }; 479 480 /* Counter age parameter. */ 481 struct mlx5_age_param { 482 uint16_t state; /**< Age state (atomically accessed). */ 483 uint16_t port_id; /**< Port id of the counter. */ 484 uint32_t timeout:24; /**< Aging timeout in seconds. */ 485 uint32_t sec_since_last_hit; 486 /**< Time in seconds since last hit (atomically accessed). */ 487 void *context; /**< Flow counter age context. */ 488 }; 489 490 struct flow_counter_stats { 491 uint64_t hits; 492 uint64_t bytes; 493 }; 494 495 /* Shared counters information for counters. */ 496 struct mlx5_flow_counter_shared { 497 union { 498 uint32_t refcnt; /* Only for shared action management. */ 499 uint32_t id; /* User counter ID for legacy sharing. */ 500 }; 501 }; 502 503 struct mlx5_flow_counter_pool; 504 /* Generic counters information. */ 505 struct mlx5_flow_counter { 506 union { 507 /* 508 * User-defined counter shared info is only used during 509 * counter active time. And aging counter sharing is not 510 * supported, so active shared counter will not be chained 511 * to the aging list. For shared counter, only when it is 512 * released, the TAILQ entry memory will be used, at that 513 * time, shared memory is not used anymore. 514 * 515 * Similarly to none-batch counter dcs, since it doesn't 516 * support aging, while counter is allocated, the entry 517 * memory is not used anymore. In this case, as bytes 518 * memory is used only when counter is allocated, and 519 * entry memory is used only when counter is free. The 520 * dcs pointer can be saved to these two different place 521 * at different stage. It will eliminate the individual 522 * counter extend struct. 523 */ 524 TAILQ_ENTRY(mlx5_flow_counter) next; 525 /**< Pointer to the next flow counter structure. */ 526 struct { 527 struct mlx5_flow_counter_shared shared_info; 528 /**< Shared counter information. */ 529 void *dcs_when_active; 530 /* 531 * For non-batch mode, the dcs will be saved 532 * here when the counter is free. 533 */ 534 }; 535 }; 536 union { 537 uint64_t hits; /**< Reset value of hits packets. */ 538 struct mlx5_flow_counter_pool *pool; /**< Counter pool. */ 539 }; 540 union { 541 uint64_t bytes; /**< Reset value of bytes. */ 542 void *dcs_when_free; 543 /* 544 * For non-batch mode, the dcs will be saved here 545 * when the counter is free. 546 */ 547 }; 548 void *action; /**< Pointer to the dv action. */ 549 }; 550 551 TAILQ_HEAD(mlx5_counters, mlx5_flow_counter); 552 553 /* Generic counter pool structure - query is in pool resolution. */ 554 struct mlx5_flow_counter_pool { 555 TAILQ_ENTRY(mlx5_flow_counter_pool) next; 556 struct mlx5_counters counters[2]; /* Free counter list. */ 557 struct mlx5_devx_obj *min_dcs; 558 /* The devx object of the minimum counter ID. */ 559 uint64_t time_of_last_age_check; 560 /* System time (from rte_rdtsc()) read in the last aging check. */ 561 uint32_t index:30; /* Pool index in container. */ 562 uint32_t is_aged:1; /* Pool with aging counter. */ 563 volatile uint32_t query_gen:1; /* Query round. */ 564 rte_spinlock_t sl; /* The pool lock. */ 565 rte_spinlock_t csl; /* The pool counter free list lock. */ 566 struct mlx5_counter_stats_raw *raw; 567 struct mlx5_counter_stats_raw *raw_hw; 568 /* The raw on HW working. */ 569 }; 570 571 /* Memory management structure for group of counter statistics raws. */ 572 struct mlx5_counter_stats_mem_mng { 573 LIST_ENTRY(mlx5_counter_stats_mem_mng) next; 574 struct mlx5_counter_stats_raw *raws; 575 struct mlx5_pmd_wrapped_mr wm; 576 }; 577 578 /* Raw memory structure for the counter statistics values of a pool. */ 579 struct mlx5_counter_stats_raw { 580 LIST_ENTRY(mlx5_counter_stats_raw) next; 581 struct mlx5_counter_stats_mem_mng *mem_mng; 582 volatile struct flow_counter_stats *data; 583 }; 584 585 TAILQ_HEAD(mlx5_counter_pools, mlx5_flow_counter_pool); 586 587 /* Counter global management structure. */ 588 struct mlx5_flow_counter_mng { 589 volatile uint16_t n_valid; /* Number of valid pools. */ 590 uint16_t last_pool_idx; /* Last used pool index */ 591 int min_id; /* The minimum counter ID in the pools. */ 592 int max_id; /* The maximum counter ID in the pools. */ 593 rte_spinlock_t pool_update_sl; /* The pool update lock. */ 594 rte_spinlock_t csl[MLX5_COUNTER_TYPE_MAX]; 595 /* The counter free list lock. */ 596 struct mlx5_counters counters[MLX5_COUNTER_TYPE_MAX]; 597 /* Free counter list. */ 598 struct mlx5_flow_counter_pool **pools; /* Counter pool array. */ 599 struct mlx5_counter_stats_mem_mng *mem_mng; 600 /* Hold the memory management for the next allocated pools raws. */ 601 struct mlx5_counters flow_counters; /* Legacy flow counter list. */ 602 uint8_t pending_queries; 603 uint16_t pool_index; 604 uint8_t query_thread_on; 605 bool counter_fallback; /* Use counter fallback management. */ 606 LIST_HEAD(mem_mngs, mlx5_counter_stats_mem_mng) mem_mngs; 607 LIST_HEAD(stat_raws, mlx5_counter_stats_raw) free_stat_raws; 608 }; 609 610 /* ASO structures. */ 611 #define MLX5_ASO_QUEUE_LOG_DESC 10 612 613 struct mlx5_aso_cq { 614 uint16_t log_desc_n; 615 uint32_t cq_ci:24; 616 struct mlx5_devx_cq cq_obj; 617 uint64_t errors; 618 }; 619 620 struct mlx5_aso_sq_elem { 621 union { 622 struct { 623 struct mlx5_aso_age_pool *pool; 624 uint16_t burst_size; 625 }; 626 struct mlx5_aso_mtr *mtr; 627 struct { 628 struct mlx5_aso_ct_action *ct; 629 char *query_data; 630 }; 631 void *user_data; 632 struct mlx5_quota *quota_obj; 633 }; 634 }; 635 636 struct mlx5_aso_sq { 637 uint16_t log_desc_n; 638 rte_spinlock_t sqsl; 639 struct mlx5_aso_cq cq; 640 struct mlx5_devx_sq sq_obj; 641 struct mlx5_pmd_mr mr; 642 volatile struct mlx5_aso_wqe *db; 643 uint16_t pi; 644 uint16_t db_pi; 645 uint32_t head; 646 uint32_t tail; 647 uint32_t sqn; 648 struct mlx5_aso_sq_elem elts[1 << MLX5_ASO_QUEUE_LOG_DESC]; 649 uint16_t next; /* Pool index of the next pool to query. */ 650 }; 651 652 struct mlx5_aso_age_action { 653 LIST_ENTRY(mlx5_aso_age_action) next; 654 void *dr_action; 655 uint32_t refcnt; 656 /* Following fields relevant only when action is active. */ 657 uint16_t offset; /* Offset of ASO Flow Hit flag in DevX object. */ 658 struct mlx5_age_param age_params; 659 }; 660 661 #define MLX5_ASO_AGE_ACTIONS_PER_POOL 512 662 #define MLX5_ASO_AGE_CONTAINER_RESIZE 64 663 664 struct mlx5_aso_age_pool { 665 struct mlx5_devx_obj *flow_hit_aso_obj; 666 uint16_t index; /* Pool index in pools array. */ 667 uint64_t time_of_last_age_check; /* In seconds. */ 668 struct mlx5_aso_age_action actions[MLX5_ASO_AGE_ACTIONS_PER_POOL]; 669 }; 670 671 LIST_HEAD(aso_age_list, mlx5_aso_age_action); 672 673 struct mlx5_aso_age_mng { 674 struct mlx5_aso_age_pool **pools; 675 uint16_t n; /* Total number of pools. */ 676 uint16_t next; /* Number of pools in use, index of next free pool. */ 677 rte_rwlock_t resize_rwl; /* Lock for resize objects. */ 678 rte_spinlock_t free_sl; /* Lock for free list access. */ 679 struct aso_age_list free; /* Free age actions list - ready to use. */ 680 struct mlx5_aso_sq aso_sq; /* ASO queue objects. */ 681 }; 682 683 /* Management structure for geneve tlv option */ 684 struct mlx5_geneve_tlv_option_resource { 685 struct mlx5_devx_obj *obj; /* Pointer to the geneve tlv opt object. */ 686 rte_be16_t option_class; /* geneve tlv opt class.*/ 687 uint8_t option_type; /* geneve tlv opt type.*/ 688 uint8_t length; /* geneve tlv opt length. */ 689 uint32_t refcnt; /* geneve tlv object reference counter */ 690 }; 691 692 693 #define MLX5_AGE_EVENT_NEW 1 694 #define MLX5_AGE_TRIGGER 2 695 #define MLX5_AGE_SET(age_info, BIT) \ 696 ((age_info)->flags |= (1 << (BIT))) 697 #define MLX5_AGE_UNSET(age_info, BIT) \ 698 ((age_info)->flags &= ~(1 << (BIT))) 699 #define MLX5_AGE_GET(age_info, BIT) \ 700 ((age_info)->flags & (1 << (BIT))) 701 #define GET_PORT_AGE_INFO(priv) \ 702 (&((priv)->sh->port[(priv)->dev_port - 1].age_info)) 703 /* Current time in seconds. */ 704 #define MLX5_CURR_TIME_SEC (rte_rdtsc() / rte_get_tsc_hz()) 705 706 /* 707 * HW steering queue oriented AGE info. 708 * It contains an array of rings, one for each HWS queue. 709 */ 710 struct mlx5_hws_q_age_info { 711 uint16_t nb_rings; /* Number of aged-out ring lists. */ 712 struct rte_ring *aged_lists[]; /* Aged-out lists. */ 713 }; 714 715 /* 716 * HW steering AGE info. 717 * It has a ring list containing all aged out flow rules. 718 */ 719 struct mlx5_hws_age_info { 720 struct rte_ring *aged_list; /* Aged out lists. */ 721 }; 722 723 /* Aging information for per port. */ 724 struct mlx5_age_info { 725 uint8_t flags; /* Indicate if is new event or need to be triggered. */ 726 union { 727 /* SW/FW steering AGE info. */ 728 struct { 729 struct mlx5_counters aged_counters; 730 /* Aged counter list. */ 731 struct aso_age_list aged_aso; 732 /* Aged ASO actions list. */ 733 rte_spinlock_t aged_sl; /* Aged flow list lock. */ 734 }; 735 struct { 736 struct mlx5_indexed_pool *ages_ipool; 737 union { 738 struct mlx5_hws_age_info hw_age; 739 /* HW steering AGE info. */ 740 struct mlx5_hws_q_age_info *hw_q_age; 741 /* HW steering queue oriented AGE info. */ 742 }; 743 }; 744 }; 745 }; 746 747 /* Per port data of shared IB device. */ 748 struct mlx5_dev_shared_port { 749 uint32_t ih_port_id; 750 uint32_t devx_ih_port_id; 751 uint32_t nl_ih_port_id; 752 /* 753 * Interrupt handler port_id. Used by shared interrupt 754 * handler to find the corresponding rte_eth device 755 * by IB port index. If value is equal or greater 756 * RTE_MAX_ETHPORTS it means there is no subhandler 757 * installed for specified IB port index. 758 */ 759 struct mlx5_age_info age_info; 760 /* Aging information for per port. */ 761 }; 762 763 /* 764 * Max number of actions per DV flow. 765 * See CREATE_FLOW_MAX_FLOW_ACTIONS_SUPPORTED 766 * in rdma-core file providers/mlx5/verbs.c. 767 */ 768 #define MLX5_DV_MAX_NUMBER_OF_ACTIONS 8 769 770 /* ASO flow meter structures */ 771 /* Modify this value if enum rte_mtr_color changes. */ 772 #define RTE_MTR_DROPPED RTE_COLORS 773 /* Yellow is now supported. */ 774 #define MLX5_MTR_RTE_COLORS (RTE_COLOR_YELLOW + 1) 775 /* table_id 22 bits in mlx5_flow_tbl_key so limit policy number. */ 776 #define MLX5_MAX_SUB_POLICY_TBL_NUM 0x3FFFFF 777 #define MLX5_INVALID_POLICY_ID UINT32_MAX 778 /* Suffix table_id on MLX5_FLOW_TABLE_LEVEL_METER. */ 779 #define MLX5_MTR_TABLE_ID_SUFFIX 1 780 /* Drop table_id on MLX5_FLOW_TABLE_LEVEL_METER. */ 781 #define MLX5_MTR_TABLE_ID_DROP 2 782 /* Priority of the meter policy matcher. */ 783 #define MLX5_MTR_POLICY_MATCHER_PRIO 0 784 /* Green & yellow color valid for now. */ 785 #define MLX5_MTR_POLICY_MODE_ALL 0 786 /* Default policy. */ 787 #define MLX5_MTR_POLICY_MODE_DEF 1 788 /* Only green color valid. */ 789 #define MLX5_MTR_POLICY_MODE_OG 2 790 /* Only yellow color valid. */ 791 #define MLX5_MTR_POLICY_MODE_OY 3 792 793 enum mlx5_meter_domain { 794 MLX5_MTR_DOMAIN_INGRESS, 795 MLX5_MTR_DOMAIN_EGRESS, 796 MLX5_MTR_DOMAIN_TRANSFER, 797 MLX5_MTR_DOMAIN_MAX, 798 }; 799 #define MLX5_MTR_DOMAIN_INGRESS_BIT (1 << MLX5_MTR_DOMAIN_INGRESS) 800 #define MLX5_MTR_DOMAIN_EGRESS_BIT (1 << MLX5_MTR_DOMAIN_EGRESS) 801 #define MLX5_MTR_DOMAIN_TRANSFER_BIT (1 << MLX5_MTR_DOMAIN_TRANSFER) 802 #define MLX5_MTR_ALL_DOMAIN_BIT (MLX5_MTR_DOMAIN_INGRESS_BIT | \ 803 MLX5_MTR_DOMAIN_EGRESS_BIT | \ 804 MLX5_MTR_DOMAIN_TRANSFER_BIT) 805 806 /* The color tag rule structure. */ 807 struct mlx5_sub_policy_color_rule { 808 void *rule; 809 /* The color rule. */ 810 struct mlx5_flow_dv_matcher *matcher; 811 /* The color matcher. */ 812 TAILQ_ENTRY(mlx5_sub_policy_color_rule) next_port; 813 /**< Pointer to the next color rule structure. */ 814 int32_t src_port; 815 /* On which src port this rule applied. */ 816 }; 817 818 TAILQ_HEAD(mlx5_sub_policy_color_rules, mlx5_sub_policy_color_rule); 819 820 /* 821 * Meter sub-policy structure. 822 * Each RSS TIR in meter policy need its own sub-policy resource. 823 */ 824 struct mlx5_flow_meter_sub_policy { 825 uint32_t main_policy_id:1; 826 /* Main policy id is same as this sub_policy id. */ 827 uint32_t idx:31; 828 /* Index to sub_policy ipool entity. */ 829 void *main_policy; 830 /* Point to struct mlx5_flow_meter_policy. */ 831 struct mlx5_flow_tbl_resource *tbl_rsc; 832 /* The sub-policy table resource. */ 833 uint32_t rix_hrxq[MLX5_MTR_RTE_COLORS]; 834 /* Index to TIR resource. */ 835 struct mlx5_flow_tbl_resource *jump_tbl[MLX5_MTR_RTE_COLORS]; 836 /* Meter jump/drop table. */ 837 struct mlx5_sub_policy_color_rules color_rules[RTE_COLORS]; 838 /* List for the color rules. */ 839 }; 840 841 struct mlx5_meter_policy_acts { 842 uint8_t actions_n; 843 /* Number of actions. */ 844 void *dv_actions[MLX5_DV_MAX_NUMBER_OF_ACTIONS]; 845 /* Action list. */ 846 }; 847 848 struct mlx5_meter_policy_action_container { 849 uint32_t rix_mark; 850 /* Index to the mark action. */ 851 struct mlx5_flow_dv_modify_hdr_resource *modify_hdr; 852 /* Pointer to modify header resource in cache. */ 853 uint8_t fate_action; 854 /* Fate action type. */ 855 union { 856 struct rte_flow_action *rss; 857 /* Rss action configuration. */ 858 uint32_t rix_port_id_action; 859 /* Index to port ID action resource. */ 860 void *dr_jump_action[MLX5_MTR_DOMAIN_MAX]; 861 /* Jump/drop action per color. */ 862 uint16_t queue; 863 /* Queue action configuration. */ 864 struct { 865 uint32_t next_mtr_id; 866 /* The next meter id. */ 867 void *next_sub_policy; 868 /* Next meter's sub-policy. */ 869 }; 870 }; 871 }; 872 873 /* Flow meter policy parameter structure. */ 874 struct mlx5_flow_meter_policy { 875 uint32_t is_rss:1; 876 /* Is RSS policy table. */ 877 uint32_t ingress:1; 878 /* Rule applies to ingress domain. */ 879 uint32_t egress:1; 880 /* Rule applies to egress domain. */ 881 uint32_t transfer:1; 882 /* Rule applies to transfer domain. */ 883 uint32_t is_queue:1; 884 /* Is queue action in policy table. */ 885 uint32_t is_hierarchy:1; 886 /* Is meter action in policy table. */ 887 uint32_t match_port:1; 888 /* If policy flows match src port. */ 889 uint32_t hierarchy_match_port:1; 890 /* Is any meter in hierarchy contains policy flow that matches src port. */ 891 uint32_t skip_r:1; 892 /* If red color policy is skipped. */ 893 uint32_t skip_y:1; 894 /* If yellow color policy is skipped. */ 895 uint32_t skip_g:1; 896 /* If green color policy is skipped. */ 897 uint32_t mark:1; 898 /* If policy contains mark action. */ 899 uint32_t initialized:1; 900 /* Initialized. */ 901 uint16_t group; 902 /* The group. */ 903 rte_spinlock_t sl; 904 uint32_t ref_cnt; 905 /* Use count. */ 906 struct rte_flow_pattern_template *hws_item_templ; 907 /* Hardware steering item templates. */ 908 struct rte_flow_actions_template *hws_act_templ[MLX5_MTR_DOMAIN_MAX]; 909 /* Hardware steering action templates. */ 910 struct rte_flow_template_table *hws_flow_table[MLX5_MTR_DOMAIN_MAX]; 911 /* Hardware steering tables. */ 912 struct rte_flow *hws_flow_rule[MLX5_MTR_DOMAIN_MAX][RTE_COLORS]; 913 /* Hardware steering rules. */ 914 struct mlx5_meter_policy_action_container act_cnt[MLX5_MTR_RTE_COLORS]; 915 /* Policy actions container. */ 916 void *dr_drop_action[MLX5_MTR_DOMAIN_MAX]; 917 /* drop action for red color. */ 918 uint16_t sub_policy_num; 919 /* Count sub policy tables, 3 bits per domain. */ 920 struct mlx5_flow_meter_sub_policy **sub_policys[MLX5_MTR_DOMAIN_MAX]; 921 /* Sub policy table array must be the end of struct. */ 922 }; 923 924 /* The maximum sub policy is relate to struct mlx5_rss_hash_fields[]. */ 925 #define MLX5_MTR_RSS_MAX_SUB_POLICY 7 926 #define MLX5_MTR_SUB_POLICY_NUM_SHIFT 3 927 #define MLX5_MTR_SUB_POLICY_NUM_MASK 0x7 928 #define MLX5_MTRS_DEFAULT_RULE_PRIORITY 0xFFFF 929 #define MLX5_MTR_CHAIN_MAX_NUM 8 930 931 /* Flow meter default policy parameter structure. 932 * Policy index 0 is reserved by default policy table. 933 * Action per color as below: 934 * green - do nothing, yellow - do nothing, red - drop 935 */ 936 struct mlx5_flow_meter_def_policy { 937 struct mlx5_flow_meter_sub_policy sub_policy; 938 /* Policy rules jump to other tables. */ 939 void *dr_jump_action[RTE_COLORS]; 940 /* Jump action per color. */ 941 }; 942 943 /* Meter parameter structure. */ 944 struct mlx5_flow_meter_info { 945 uint32_t meter_id; 946 /**< Meter id. */ 947 uint32_t policy_id; 948 /* Policy id, the first sub_policy idx. */ 949 struct mlx5_flow_meter_profile *profile; 950 /**< Meter profile parameters. */ 951 rte_spinlock_t sl; /**< Meter action spinlock. */ 952 /** Set of stats counters to be enabled. 953 * @see enum rte_mtr_stats_type 954 */ 955 uint32_t bytes_dropped:1; 956 /** Set bytes dropped stats to be enabled. */ 957 uint32_t pkts_dropped:1; 958 /** Set packets dropped stats to be enabled. */ 959 uint32_t active_state:1; 960 /**< Meter hw active state. */ 961 uint32_t shared:1; 962 /**< Meter shared or not. */ 963 uint32_t is_enable:1; 964 /**< Meter disable/enable state. */ 965 uint32_t ingress:1; 966 /**< Rule applies to egress traffic. */ 967 uint32_t egress:1; 968 /** 969 * Instead of simply matching the properties of traffic as it would 970 * appear on a given DPDK port ID, enabling this attribute transfers 971 * a flow rule to the lowest possible level of any device endpoints 972 * found in the pattern. 973 * 974 * When supported, this effectively enables an application to 975 * re-route traffic not necessarily intended for it (e.g. coming 976 * from or addressed to different physical ports, VFs or 977 * applications) at the device level. 978 * 979 * It complements the behavior of some pattern items such as 980 * RTE_FLOW_ITEM_TYPE_REPRESENTED_PORT and is meaningless without them. 981 * 982 * When transferring flow rules, ingress and egress attributes keep 983 * their original meaning, as if processing traffic emitted or 984 * received by the application. 985 */ 986 uint32_t transfer:1; 987 uint32_t def_policy:1; 988 uint32_t initialized:1; 989 /* Meter points to default policy. */ 990 uint32_t color_aware:1; 991 /* Meter is color aware mode. */ 992 void *drop_rule[MLX5_MTR_DOMAIN_MAX]; 993 /* Meter drop rule in drop table. */ 994 uint32_t drop_cnt; 995 /**< Color counter for drop. */ 996 uint32_t ref_cnt; 997 /**< Use count. */ 998 struct mlx5_indexed_pool *flow_ipool; 999 /**< Index pool for flow id. */ 1000 void *meter_action_g; 1001 /**< Flow meter action. */ 1002 void *meter_action_y; 1003 /**< Flow meter action for yellow init_color. */ 1004 uint32_t meter_offset; 1005 /**< Flow meter offset. */ 1006 uint16_t group; 1007 /**< Flow meter group. */ 1008 }; 1009 1010 /* PPS(packets per second) map to BPS(Bytes per second). 1011 * HW treat packet as 128bytes in PPS mode 1012 */ 1013 #define MLX5_MTRS_PPS_MAP_BPS_SHIFT 7 1014 1015 /* RFC2697 parameter structure. */ 1016 struct mlx5_flow_meter_srtcm_rfc2697_prm { 1017 rte_be32_t cbs_cir; 1018 /* 1019 * bit 24-28: cbs_exponent, bit 16-23 cbs_mantissa, 1020 * bit 8-12: cir_exponent, bit 0-7 cir_mantissa. 1021 */ 1022 rte_be32_t ebs_eir; 1023 /* 1024 * bit 24-28: ebs_exponent, bit 16-23 ebs_mantissa, 1025 * bit 8-12: eir_exponent, bit 0-7 eir_mantissa. 1026 */ 1027 }; 1028 1029 /* Flow meter profile structure. */ 1030 struct mlx5_flow_meter_profile { 1031 TAILQ_ENTRY(mlx5_flow_meter_profile) next; 1032 /**< Pointer to the next flow meter structure. */ 1033 uint32_t id; /**< Profile id. */ 1034 struct rte_mtr_meter_profile profile; /**< Profile detail. */ 1035 union { 1036 struct mlx5_flow_meter_srtcm_rfc2697_prm srtcm_prm; 1037 /**< srtcm_rfc2697 struct. */ 1038 }; 1039 uint32_t ref_cnt; /**< Use count. */ 1040 uint32_t g_support:1; /**< If G color will be generated. */ 1041 uint32_t y_support:1; /**< If Y color will be generated. */ 1042 uint32_t initialized:1; /**< Initialized. */ 1043 }; 1044 1045 /* 2 meters in each ASO cache line */ 1046 #define MLX5_MTRS_CONTAINER_RESIZE 64 1047 /* 1048 * The pool index and offset of meter in the pool array makes up the 1049 * meter index. In case the meter is from pool 0 and offset 0, it 1050 * should plus 1 to avoid index 0, since 0 means invalid meter index 1051 * currently. 1052 */ 1053 #define MLX5_MAKE_MTR_IDX(pi, offset) \ 1054 ((pi) * MLX5_ASO_MTRS_PER_POOL + (offset) + 1) 1055 1056 /*aso flow meter state*/ 1057 enum mlx5_aso_mtr_state { 1058 ASO_METER_FREE, /* In free list. */ 1059 ASO_METER_WAIT, /* ACCESS_ASO WQE in progress. */ 1060 ASO_METER_WAIT_ASYNC, /* CQE will be handled by async pull. */ 1061 ASO_METER_READY, /* CQE received. */ 1062 }; 1063 1064 /*aso flow meter type*/ 1065 enum mlx5_aso_mtr_type { 1066 ASO_METER_INDIRECT, 1067 ASO_METER_DIRECT, 1068 }; 1069 1070 /* Generic aso_flow_meter information. */ 1071 struct mlx5_aso_mtr { 1072 union { 1073 LIST_ENTRY(mlx5_aso_mtr) next; 1074 struct mlx5_aso_mtr_pool *pool; 1075 }; 1076 enum mlx5_aso_mtr_type type; 1077 struct mlx5_flow_meter_info fm; 1078 /**< Pointer to the next aso flow meter structure. */ 1079 uint8_t state; /**< ASO flow meter state. */ 1080 uint32_t offset; 1081 enum rte_color init_color; 1082 }; 1083 1084 /* Generic aso_flow_meter pool structure. */ 1085 struct mlx5_aso_mtr_pool { 1086 struct mlx5_aso_mtr mtrs[MLX5_ASO_MTRS_PER_POOL]; 1087 /*Must be the first in pool*/ 1088 struct mlx5_devx_obj *devx_obj; 1089 /* The devx object of the minimum aso flow meter ID. */ 1090 struct mlx5dr_action *action; /* HWS action. */ 1091 struct mlx5_indexed_pool *idx_pool; /* HWS index pool. */ 1092 uint32_t index; /* Pool index in management structure. */ 1093 uint32_t nb_sq; /* Number of ASO SQ. */ 1094 struct mlx5_aso_sq *sq; /* ASO SQs. */ 1095 }; 1096 1097 LIST_HEAD(aso_meter_list, mlx5_aso_mtr); 1098 /* Pools management structure for ASO flow meter pools. */ 1099 struct mlx5_aso_mtr_pools_mng { 1100 volatile uint16_t n_valid; /* Number of valid pools. */ 1101 uint16_t n; /* Number of pools. */ 1102 rte_spinlock_t mtrsl; /* The ASO flow meter free list lock. */ 1103 rte_rwlock_t resize_mtrwl; /* Lock for resize objects. */ 1104 struct aso_meter_list meters; /* Free ASO flow meter list. */ 1105 struct mlx5_aso_sq sq; /*SQ using by ASO flow meter. */ 1106 struct mlx5_aso_mtr_pool **pools; /* ASO flow meter pool array. */ 1107 }; 1108 1109 /* Bulk management structure for ASO flow meter. */ 1110 struct mlx5_mtr_bulk { 1111 uint32_t size; /* Number of ASO objects. */ 1112 struct mlx5dr_action *action; /* HWS action */ 1113 struct mlx5_devx_obj *devx_obj; /* DEVX object. */ 1114 struct mlx5_aso_mtr *aso; /* Array of ASO objects. */ 1115 }; 1116 1117 /* Meter management structure for global flow meter resource. */ 1118 struct mlx5_flow_mtr_mng { 1119 struct mlx5_aso_mtr_pools_mng pools_mng; 1120 /* Pools management structure for ASO flow meter pools. */ 1121 struct mlx5_flow_meter_def_policy *def_policy[MLX5_MTR_DOMAIN_MAX]; 1122 /* Default policy table. */ 1123 uint32_t def_policy_id; 1124 /* Default policy id. */ 1125 uint32_t def_policy_ref_cnt; 1126 /** def_policy meter use count. */ 1127 struct mlx5_flow_tbl_resource *drop_tbl[MLX5_MTR_DOMAIN_MAX]; 1128 /* Meter drop table. */ 1129 struct mlx5_flow_dv_matcher * 1130 drop_matcher[MLX5_MTR_DOMAIN_MAX][MLX5_REG_BITS]; 1131 /* Matcher meter in drop table. */ 1132 struct mlx5_flow_dv_matcher *def_matcher[MLX5_MTR_DOMAIN_MAX]; 1133 /* Default matcher in drop table. */ 1134 void *def_rule[MLX5_MTR_DOMAIN_MAX]; 1135 /* Default rule in drop table. */ 1136 uint8_t max_mtr_bits; 1137 /* Indicate how many bits are used by meter id at the most. */ 1138 uint8_t max_mtr_flow_bits; 1139 /* Indicate how many bits are used by meter flow id at the most. */ 1140 }; 1141 1142 /* Table key of the hash organization. */ 1143 union mlx5_flow_tbl_key { 1144 struct { 1145 /* Table ID should be at the lowest address. */ 1146 uint32_t level; /**< Level of the table. */ 1147 uint32_t id:22; /**< ID of the table. */ 1148 uint32_t dummy:1; /**< Dummy table for DV API. */ 1149 uint32_t is_fdb:1; /**< 1 - FDB, 0 - NIC TX/RX. */ 1150 uint32_t is_egress:1; /**< 1 - egress, 0 - ingress. */ 1151 uint32_t reserved:7; /**< must be zero for comparison. */ 1152 }; 1153 uint64_t v64; /**< full 64bits value of key */ 1154 }; 1155 1156 /* Table structure. */ 1157 struct mlx5_flow_tbl_resource { 1158 void *obj; /**< Pointer to DR table object. */ 1159 }; 1160 1161 #define MLX5_MAX_TABLES UINT16_MAX 1162 #define MLX5_HAIRPIN_TX_TABLE (UINT16_MAX - 1) 1163 /* Reserve the last two tables for metadata register copy. */ 1164 #define MLX5_FLOW_MREG_ACT_TABLE_GROUP (MLX5_MAX_TABLES - 1) 1165 #define MLX5_FLOW_MREG_CP_TABLE_GROUP (MLX5_MAX_TABLES - 2) 1166 /* Tables for metering splits should be added here. */ 1167 #define MLX5_FLOW_TABLE_LEVEL_METER (MLX5_MAX_TABLES - 3) 1168 #define MLX5_FLOW_TABLE_LEVEL_POLICY (MLX5_MAX_TABLES - 4) 1169 #define MLX5_MAX_TABLES_EXTERNAL MLX5_FLOW_TABLE_LEVEL_POLICY 1170 #define MLX5_FLOW_TABLE_HWS_POLICY (MLX5_MAX_TABLES - 10) 1171 #define MLX5_MAX_TABLES_FDB UINT16_MAX 1172 #define MLX5_FLOW_TABLE_FACTOR 10 1173 1174 /* ID generation structure. */ 1175 struct mlx5_flow_id_pool { 1176 uint32_t *free_arr; /**< Pointer to the a array of free values. */ 1177 uint32_t base_index; 1178 /**< The next index that can be used without any free elements. */ 1179 uint32_t *curr; /**< Pointer to the index to pop. */ 1180 uint32_t *last; /**< Pointer to the last element in the empty array. */ 1181 uint32_t max_id; /**< Maximum id can be allocated from the pool. */ 1182 }; 1183 1184 /* Tx pacing queue structure - for Clock and Rearm queues. */ 1185 struct mlx5_txpp_wq { 1186 /* Completion Queue related data.*/ 1187 struct mlx5_devx_cq cq_obj; 1188 uint32_t cq_ci:24; 1189 uint32_t arm_sn:2; 1190 /* Send Queue related data.*/ 1191 struct mlx5_devx_sq sq_obj; 1192 uint16_t sq_size; /* Number of WQEs in the queue. */ 1193 uint16_t sq_ci; /* Next WQE to execute. */ 1194 }; 1195 1196 /* Tx packet pacing internal timestamp. */ 1197 struct mlx5_txpp_ts { 1198 uint64_t ci_ts; 1199 uint64_t ts; 1200 }; 1201 1202 /* Tx packet pacing structure. */ 1203 struct mlx5_dev_txpp { 1204 pthread_mutex_t mutex; /* Pacing create/destroy mutex. */ 1205 uint32_t refcnt; /* Pacing reference counter. */ 1206 uint32_t freq; /* Timestamp frequency, Hz. */ 1207 uint32_t tick; /* Completion tick duration in nanoseconds. */ 1208 uint32_t test; /* Packet pacing test mode. */ 1209 int32_t skew; /* Scheduling skew. */ 1210 struct rte_intr_handle *intr_handle; /* Periodic interrupt. */ 1211 void *echan; /* Event Channel. */ 1212 struct mlx5_txpp_wq clock_queue; /* Clock Queue. */ 1213 struct mlx5_txpp_wq rearm_queue; /* Clock Queue. */ 1214 void *pp; /* Packet pacing context. */ 1215 uint16_t pp_id; /* Packet pacing context index. */ 1216 uint16_t ts_n; /* Number of captured timestamps. */ 1217 uint16_t ts_p; /* Pointer to statistics timestamp. */ 1218 struct mlx5_txpp_ts *tsa; /* Timestamps sliding window stats. */ 1219 struct mlx5_txpp_ts ts; /* Cached completion id/timestamp. */ 1220 uint32_t sync_lost:1; /* ci/timestamp synchronization lost. */ 1221 /* Statistics counters. */ 1222 uint64_t err_miss_int; /* Missed service interrupt. */ 1223 uint64_t err_rearm_queue; /* Rearm Queue errors. */ 1224 uint64_t err_clock_queue; /* Clock Queue errors. */ 1225 uint64_t err_ts_past; /* Timestamp in the past. */ 1226 uint64_t err_ts_future; /* Timestamp in the distant future. */ 1227 uint64_t err_ts_order; /* Timestamp not in ascending order. */ 1228 }; 1229 1230 /* Sample ID information of eCPRI flex parser structure. */ 1231 struct mlx5_ecpri_parser_profile { 1232 uint32_t num; /* Actual number of samples. */ 1233 uint32_t ids[8]; /* Sample IDs for this profile. */ 1234 uint8_t offset[8]; /* Bytes offset of each parser. */ 1235 void *obj; /* Flex parser node object. */ 1236 }; 1237 1238 /* Max member ports per bonding device. */ 1239 #define MLX5_BOND_MAX_PORTS 2 1240 1241 /* Bonding device information. */ 1242 struct mlx5_bond_info { 1243 int n_port; /* Number of bond member ports. */ 1244 uint32_t ifindex; 1245 char ifname[MLX5_NAMESIZE + 1]; 1246 struct { 1247 char ifname[MLX5_NAMESIZE + 1]; 1248 uint32_t ifindex; 1249 struct rte_pci_addr pci_addr; 1250 } ports[MLX5_BOND_MAX_PORTS]; 1251 }; 1252 1253 /* Number of connection tracking objects per pool: must be a power of 2. */ 1254 #define MLX5_ASO_CT_ACTIONS_PER_POOL 64 1255 1256 /* Generate incremental and unique CT index from pool and offset. */ 1257 #define MLX5_MAKE_CT_IDX(pool, offset) \ 1258 ((pool) * MLX5_ASO_CT_ACTIONS_PER_POOL + (offset) + 1) 1259 1260 /* ASO Conntrack state. */ 1261 enum mlx5_aso_ct_state { 1262 ASO_CONNTRACK_FREE, /* Inactive, in the free list. */ 1263 ASO_CONNTRACK_WAIT, /* WQE sent in the SQ. */ 1264 ASO_CONNTRACK_WAIT_ASYNC, /* CQE will be handled by async pull. */ 1265 ASO_CONNTRACK_READY, /* CQE received w/o error. */ 1266 ASO_CONNTRACK_QUERY, /* WQE for query sent. */ 1267 ASO_CONNTRACK_MAX, /* Guard. */ 1268 }; 1269 1270 /* Generic ASO connection tracking structure. */ 1271 struct mlx5_aso_ct_action { 1272 union { 1273 /* SWS mode struct. */ 1274 struct { 1275 /* Pointer to the next ASO CT. Used only in SWS. */ 1276 LIST_ENTRY(mlx5_aso_ct_action) next; 1277 }; 1278 /* HWS mode struct. */ 1279 struct { 1280 /* Pointer to action pool. Used only in HWS. */ 1281 struct mlx5_aso_ct_pool *pool; 1282 }; 1283 }; 1284 /* General action object for original dir. */ 1285 void *dr_action_orig; 1286 /* General action object for reply dir. */ 1287 void *dr_action_rply; 1288 uint32_t refcnt; /* Action used count in device flows. */ 1289 uint32_t offset; /* Offset of ASO CT in DevX objects bulk. */ 1290 uint16_t peer; /* The only peer port index could also use this CT. */ 1291 enum mlx5_aso_ct_state state; /* ASO CT state. */ 1292 bool is_original; /* The direction of the DR action to be used. */ 1293 }; 1294 1295 /* CT action object state update. */ 1296 #define MLX5_ASO_CT_UPDATE_STATE(c, s) \ 1297 __atomic_store_n(&((c)->state), (s), __ATOMIC_RELAXED) 1298 1299 #ifdef PEDANTIC 1300 #pragma GCC diagnostic ignored "-Wpedantic" 1301 #endif 1302 1303 /* ASO connection tracking software pool definition. */ 1304 struct mlx5_aso_ct_pool { 1305 uint16_t index; /* Pool index in pools array. */ 1306 /* Free ASO CT index in the pool. Used by HWS. */ 1307 struct mlx5_indexed_pool *cts; 1308 struct mlx5_devx_obj *devx_obj; 1309 union { 1310 void *dummy_action; 1311 /* Dummy action to increase the reference count in the driver. */ 1312 struct mlx5dr_action *dr_action; 1313 /* HWS action. */ 1314 }; 1315 struct mlx5_aso_sq *sq; /* Async ASO SQ. */ 1316 struct mlx5_aso_sq *shared_sq; /* Shared ASO SQ. */ 1317 struct mlx5_aso_ct_action actions[]; 1318 /* CT action structures bulk. */ 1319 }; 1320 1321 LIST_HEAD(aso_ct_list, mlx5_aso_ct_action); 1322 1323 #define MLX5_ASO_CT_SQ_NUM 16 1324 1325 /* Pools management structure for ASO connection tracking pools. */ 1326 struct mlx5_aso_ct_pools_mng { 1327 struct mlx5_aso_ct_pool **pools; 1328 uint16_t n; /* Total number of pools. */ 1329 uint16_t next; /* Number of pools in use, index of next free pool. */ 1330 uint32_t nb_sq; /* Number of ASO SQ. */ 1331 rte_spinlock_t ct_sl; /* The ASO CT free list lock. */ 1332 rte_rwlock_t resize_rwl; /* The ASO CT pool resize lock. */ 1333 struct aso_ct_list free_cts; /* Free ASO CT objects list. */ 1334 struct mlx5_aso_sq aso_sqs[]; /* ASO queue objects. */ 1335 }; 1336 1337 #ifdef PEDANTIC 1338 #pragma GCC diagnostic error "-Wpedantic" 1339 #endif 1340 1341 /* LAG attr. */ 1342 struct mlx5_lag { 1343 uint8_t tx_remap_affinity[16]; /* The PF port number of affinity */ 1344 uint8_t affinity_mode; /* TIS or hash based affinity */ 1345 }; 1346 1347 /* DevX flex parser context. */ 1348 struct mlx5_flex_parser_devx { 1349 struct mlx5_list_entry entry; /* List element at the beginning. */ 1350 uint32_t num_samples; 1351 uint8_t anchor_id; 1352 void *devx_obj; 1353 struct mlx5_devx_graph_node_attr devx_conf; 1354 uint32_t sample_ids[MLX5_GRAPH_NODE_SAMPLE_NUM]; 1355 struct mlx5_devx_match_sample_info_query_attr sample_info[MLX5_GRAPH_NODE_SAMPLE_NUM]; 1356 }; 1357 1358 /* Pattern field descriptor - how to translate flex pattern into samples. */ 1359 __extension__ 1360 struct mlx5_flex_pattern_field { 1361 uint16_t width:6; 1362 uint16_t shift:5; 1363 uint16_t reg_id:5; 1364 }; 1365 1366 #define MLX5_INVALID_SAMPLE_REG_ID 0x1F 1367 1368 /* Port flex item context. */ 1369 struct mlx5_flex_item { 1370 struct mlx5_flex_parser_devx *devx_fp; /* DevX flex parser object. */ 1371 uint32_t refcnt; /* Atomically accessed refcnt by flows. */ 1372 enum rte_flow_item_flex_tunnel_mode tunnel_mode; /* Tunnel mode. */ 1373 uint32_t mapnum; /* Number of pattern translation entries. */ 1374 struct mlx5_flex_pattern_field map[MLX5_FLEX_ITEM_MAPPING_NUM]; 1375 }; 1376 1377 /* 1378 * Sample an IPv6 address and the first dword of SRv6 header. 1379 * Then it is 16 + 4 = 20 bytes which is 5 dwords. 1380 */ 1381 #define MLX5_SRV6_SAMPLE_NUM 5 1382 /* Mlx5 internal flex parser profile structure. */ 1383 struct mlx5_internal_flex_parser_profile { 1384 uint32_t refcnt; 1385 struct mlx5_flex_item flex; /* Hold map info for modify field. */ 1386 }; 1387 1388 struct mlx5_send_to_kernel_action { 1389 void *action; 1390 void *tbl; 1391 }; 1392 1393 #define HWS_CNT_ASO_SQ_NUM 4 1394 1395 struct mlx5_hws_aso_mng { 1396 uint16_t sq_num; 1397 struct mlx5_aso_sq sqs[HWS_CNT_ASO_SQ_NUM]; 1398 }; 1399 1400 struct mlx5_hws_cnt_svc_mng { 1401 uint32_t refcnt; 1402 uint32_t service_core; 1403 uint32_t query_interval; 1404 rte_thread_t service_thread; 1405 uint8_t svc_running; 1406 struct mlx5_hws_aso_mng aso_mng __rte_cache_aligned; 1407 }; 1408 1409 #define MLX5_FLOW_HW_TAGS_MAX 12 1410 1411 struct mlx5_dev_registers { 1412 enum modify_reg aso_reg; 1413 enum modify_reg hw_avl_tags[MLX5_FLOW_HW_TAGS_MAX]; 1414 }; 1415 1416 #if defined(HAVE_MLX5DV_DR) && \ 1417 (defined(HAVE_MLX5_DR_CREATE_ACTION_FLOW_METER) || \ 1418 defined(HAVE_MLX5_DR_CREATE_ACTION_ASO)) 1419 #define HAVE_MLX5_DR_CREATE_ACTION_ASO_EXT 1420 #endif 1421 1422 /* 1423 * Shared Infiniband device context for Master/Representors 1424 * which belong to same IB device with multiple IB ports. 1425 **/ 1426 struct mlx5_dev_ctx_shared { 1427 LIST_ENTRY(mlx5_dev_ctx_shared) next; 1428 uint32_t refcnt; 1429 uint32_t esw_mode:1; /* Whether is E-Switch mode. */ 1430 uint32_t flow_hit_aso_en:1; /* Flow Hit ASO is supported. */ 1431 uint32_t steering_format_version:4; 1432 /* Indicates the device steering logic format. */ 1433 uint32_t meter_aso_en:1; /* Flow Meter ASO is supported. */ 1434 uint32_t ct_aso_en:1; /* Connection Tracking ASO is supported. */ 1435 uint32_t tunnel_header_0_1:1; /* tunnel_header_0_1 is supported. */ 1436 uint32_t tunnel_header_2_3:1; /* tunnel_header_2_3 is supported. */ 1437 uint32_t misc5_cap:1; /* misc5 matcher parameter is supported. */ 1438 uint32_t dr_root_drop_action_en:1; /* DR drop action is usable on root tables. */ 1439 uint32_t drop_action_check_flag:1; /* Check Flag for drop action. */ 1440 uint32_t flow_priority_check_flag:1; /* Check Flag for flow priority. */ 1441 uint32_t metadata_regc_check_flag:1; /* Check Flag for metadata REGC. */ 1442 uint32_t shared_mark_enabled:1; 1443 /* If mark action is enabled on Rxqs (shared E-Switch domain). */ 1444 uint32_t lag_rx_port_affinity_en:1; 1445 /* lag_rx_port_affinity is supported. */ 1446 uint32_t hws_max_log_bulk_sz:5; 1447 /* Log of minimal HWS counters created hard coded. */ 1448 uint32_t hws_max_nb_counters; /* Maximal number for HWS counters. */ 1449 uint32_t max_port; /* Maximal IB device port index. */ 1450 struct mlx5_bond_info bond; /* Bonding information. */ 1451 struct mlx5_common_device *cdev; /* Backend mlx5 device. */ 1452 uint32_t tdn; /* Transport Domain number. */ 1453 char ibdev_name[MLX5_FS_NAME_MAX]; /* SYSFS dev name. */ 1454 char ibdev_path[MLX5_FS_PATH_MAX]; /* SYSFS dev path for secondary */ 1455 struct mlx5_dev_cap dev_cap; /* Device capabilities. */ 1456 struct mlx5_sh_config config; /* Device configuration. */ 1457 int numa_node; /* Numa node of backing physical device. */ 1458 /* Packet pacing related structure. */ 1459 struct mlx5_dev_txpp txpp; 1460 /* Shared DV/DR flow data section. */ 1461 uint32_t dv_meta_mask; /* flow META metadata supported mask. */ 1462 uint32_t dv_mark_mask; /* flow MARK metadata supported mask. */ 1463 uint32_t dv_regc0_mask; /* available bits of metadata reg_c[0]. */ 1464 void *fdb_domain; /* FDB Direct Rules name space handle. */ 1465 void *rx_domain; /* RX Direct Rules name space handle. */ 1466 void *tx_domain; /* TX Direct Rules name space handle. */ 1467 #ifndef RTE_ARCH_64 1468 rte_spinlock_t uar_lock_cq; /* CQs share a common distinct UAR. */ 1469 rte_spinlock_t uar_lock[MLX5_UAR_PAGE_NUM_MAX]; 1470 /* UAR same-page access control required in 32bit implementations. */ 1471 #endif 1472 union { 1473 struct mlx5_hlist *flow_tbls; /* SWS flow table. */ 1474 struct mlx5_hlist *groups; /* HWS flow group. */ 1475 }; 1476 struct mlx5_flow_tunnel_hub *tunnel_hub; 1477 /* Direct Rules tables for FDB, NIC TX+RX */ 1478 void *dr_drop_action; /* Pointer to DR drop action, any domain. */ 1479 void *pop_vlan_action; /* Pointer to DR pop VLAN action. */ 1480 #if defined(HAVE_IBV_FLOW_DV_SUPPORT) || !defined(HAVE_INFINIBAND_VERBS_H) 1481 struct mlx5_send_to_kernel_action send_to_kernel_action[MLX5DR_TABLE_TYPE_MAX]; 1482 #endif 1483 struct mlx5_hlist *encaps_decaps; /* Encap/decap action hash list. */ 1484 struct mlx5_hlist *modify_cmds; 1485 struct mlx5_hlist *tag_table; 1486 struct mlx5_list *port_id_action_list; /* Port ID action list. */ 1487 struct mlx5_list *push_vlan_action_list; /* Push VLAN actions. */ 1488 struct mlx5_list *sample_action_list; /* List of sample actions. */ 1489 struct mlx5_list *dest_array_list; 1490 struct mlx5_list *flex_parsers_dv; /* Flex Item parsers. */ 1491 /* List of destination array actions. */ 1492 struct mlx5_flow_counter_mng sws_cmng; 1493 /* SW steering counters management structure. */ 1494 void *default_miss_action; /* Default miss action. */ 1495 struct mlx5_indexed_pool *ipool[MLX5_IPOOL_MAX]; 1496 struct mlx5_indexed_pool *mdh_ipools[MLX5_MAX_MODIFY_NUM]; 1497 /* Shared interrupt handler section. */ 1498 struct rte_intr_handle *intr_handle; /* Interrupt handler for device. */ 1499 struct rte_intr_handle *intr_handle_devx; /* DEVX interrupt handler. */ 1500 struct rte_intr_handle *intr_handle_nl; /* Netlink interrupt handler. */ 1501 void *devx_comp; /* DEVX async comp obj. */ 1502 struct mlx5_devx_obj *tis[16]; /* TIS object. */ 1503 struct mlx5_devx_obj *td; /* Transport domain. */ 1504 struct mlx5_lag lag; /* LAG attributes */ 1505 struct mlx5_uar tx_uar; /* DevX UAR for Tx and Txpp and ASO SQs. */ 1506 struct mlx5_uar rx_uar; /* DevX UAR for Rx. */ 1507 struct mlx5_proc_priv *pppriv; /* Pointer to primary private process. */ 1508 struct mlx5_ecpri_parser_profile ecpri_parser; 1509 struct mlx5_internal_flex_parser_profile srh_flex_parser; /* srh flex parser structure. */ 1510 /* Flex parser profiles information. */ 1511 LIST_HEAD(shared_rxqs, mlx5_rxq_ctrl) shared_rxqs; /* Shared RXQs. */ 1512 struct mlx5_aso_age_mng *aso_age_mng; 1513 /* Management data for aging mechanism using ASO Flow Hit. */ 1514 struct mlx5_geneve_tlv_option_resource *geneve_tlv_option_resource; 1515 /* Management structure for geneve tlv option */ 1516 rte_spinlock_t geneve_tlv_opt_sl; /* Lock for geneve tlv resource */ 1517 struct mlx5_flow_mtr_mng *mtrmng; 1518 /* Meter management structure. */ 1519 struct mlx5_aso_ct_pools_mng *ct_mng; /* Management data for ASO CT in HWS only. */ 1520 struct mlx5_lb_ctx self_lb; /* QP to enable self loopback for Devx. */ 1521 unsigned int flow_max_priority; 1522 enum modify_reg flow_mreg_c[MLX5_MREG_C_NUM]; 1523 /* Availability of mreg_c's. */ 1524 void *devx_channel_lwm; 1525 struct rte_intr_handle *intr_handle_lwm; 1526 pthread_mutex_t lwm_config_lock; 1527 uint32_t host_shaper_rate:8; 1528 uint32_t lwm_triggered:1; 1529 struct mlx5_hws_cnt_svc_mng *cnt_svc; 1530 rte_spinlock_t cpool_lock; 1531 LIST_HEAD(hws_cpool_list, mlx5_hws_cnt_pool) hws_cpool_list; /* Count pool list. */ 1532 struct mlx5_dev_registers registers; 1533 struct mlx5_dev_shared_port port[]; /* per device port data array. */ 1534 }; 1535 1536 /* 1537 * Per-process private structure. 1538 * Caution, secondary process may rebuild the struct during port start. 1539 */ 1540 struct mlx5_proc_priv { 1541 void *hca_bar; 1542 /* Mapped HCA PCI BAR area. */ 1543 size_t uar_table_sz; 1544 /* Size of UAR register table. */ 1545 struct mlx5_uar_data uar_table[]; 1546 /* Table of UAR registers for each process. */ 1547 }; 1548 1549 /* MTR profile list. */ 1550 TAILQ_HEAD(mlx5_mtr_profiles, mlx5_flow_meter_profile); 1551 /* MTR list. */ 1552 TAILQ_HEAD(mlx5_legacy_flow_meters, mlx5_legacy_flow_meter); 1553 1554 struct mlx5_mtr_config { 1555 uint32_t nb_meters; /**< Number of configured meters */ 1556 uint32_t nb_meter_profiles; /**< Number of configured meter profiles */ 1557 uint32_t nb_meter_policies; /**< Number of configured meter policies */ 1558 }; 1559 1560 /* RSS description. */ 1561 struct mlx5_flow_rss_desc { 1562 bool symmetric_hash_function; /**< Symmetric hash function */ 1563 uint32_t level; 1564 uint32_t queue_num; /**< Number of entries in @p queue. */ 1565 uint64_t types; /**< Specific RSS hash types (see RTE_ETH_RSS_*). */ 1566 uint64_t hash_fields; /* Verbs Hash fields. */ 1567 uint8_t key[MLX5_RSS_HASH_KEY_LEN]; /**< RSS hash key. */ 1568 uint32_t key_len; /**< RSS hash key len. */ 1569 uint32_t hws_flags; /**< HW steering action. */ 1570 uint32_t tunnel; /**< Queue in tunnel. */ 1571 uint32_t shared_rss; /**< Shared RSS index. */ 1572 struct mlx5_ind_table_obj *ind_tbl; 1573 /**< Indirection table for shared RSS hash RX queues. */ 1574 union { 1575 uint16_t *queue; /**< Destination queues. */ 1576 const uint16_t *const_q; /**< Const pointer convert. */ 1577 }; 1578 }; 1579 1580 #define MLX5_PROC_PRIV(port_id) \ 1581 ((struct mlx5_proc_priv *)rte_eth_devices[port_id].process_private) 1582 1583 /* Verbs/DevX Rx queue elements. */ 1584 struct mlx5_rxq_obj { 1585 LIST_ENTRY(mlx5_rxq_obj) next; /* Pointer to the next element. */ 1586 struct mlx5_rxq_ctrl *rxq_ctrl; /* Back pointer to parent. */ 1587 int fd; /* File descriptor for event channel */ 1588 union { 1589 struct { 1590 void *wq; /* Work Queue. */ 1591 void *ibv_cq; /* Completion Queue. */ 1592 void *ibv_channel; 1593 }; 1594 struct mlx5_devx_obj *rq; /* DevX RQ object for hairpin. */ 1595 struct { 1596 struct mlx5_devx_rmp devx_rmp; /* RMP for shared RQ. */ 1597 struct mlx5_devx_cq cq_obj; /* DevX CQ object. */ 1598 void *devx_channel; 1599 }; 1600 }; 1601 }; 1602 1603 /* Indirection table. */ 1604 struct mlx5_ind_table_obj { 1605 LIST_ENTRY(mlx5_ind_table_obj) next; /* Pointer to the next element. */ 1606 uint32_t refcnt; /* Reference counter. */ 1607 union { 1608 void *ind_table; /**< Indirection table. */ 1609 struct mlx5_devx_obj *rqt; /* DevX RQT object. */ 1610 }; 1611 uint32_t queues_n; /**< Number of queues in the list. */ 1612 uint16_t *queues; /**< Queue list. */ 1613 }; 1614 1615 /* Hash Rx queue. */ 1616 __extension__ 1617 struct mlx5_hrxq { 1618 struct mlx5_list_entry entry; /* List entry. */ 1619 uint32_t standalone:1; /* This object used in shared action. */ 1620 struct mlx5_ind_table_obj *ind_table; /* Indirection table. */ 1621 union { 1622 void *qp; /* Verbs queue pair. */ 1623 struct mlx5_devx_obj *tir; /* DevX TIR object. */ 1624 }; 1625 #if defined(HAVE_IBV_FLOW_DV_SUPPORT) || !defined(HAVE_INFINIBAND_VERBS_H) 1626 void *action; /* DV QP action pointer. */ 1627 #endif 1628 bool symmetric_hash_function; /* Symmetric hash function */ 1629 uint32_t hws_flags; /* Hw steering flags. */ 1630 uint64_t hash_fields; /* Verbs Hash fields. */ 1631 uint32_t rss_key_len; /* Hash key length in bytes. */ 1632 uint32_t idx; /* Hash Rx queue index. */ 1633 uint8_t rss_key[]; /* Hash key. */ 1634 }; 1635 1636 /* Verbs/DevX Tx queue elements. */ 1637 struct mlx5_txq_obj { 1638 LIST_ENTRY(mlx5_txq_obj) next; /* Pointer to the next element. */ 1639 struct mlx5_txq_ctrl *txq_ctrl; /* Pointer to the control queue. */ 1640 union { 1641 struct { 1642 void *cq; /* Completion Queue. */ 1643 void *qp; /* Queue Pair. */ 1644 }; 1645 struct { 1646 struct mlx5_devx_obj *sq; 1647 /* DevX object for Sx queue. */ 1648 struct mlx5_devx_obj *tis; /* The TIS object. */ 1649 void *umem_buf_wq_buffer; 1650 void *umem_obj_wq_buffer; 1651 }; 1652 struct { 1653 struct rte_eth_dev *dev; 1654 struct mlx5_devx_cq cq_obj; 1655 /* DevX CQ object and its resources. */ 1656 struct mlx5_devx_sq sq_obj; 1657 /* DevX SQ object and its resources. */ 1658 }; 1659 }; 1660 }; 1661 1662 enum mlx5_rxq_modify_type { 1663 MLX5_RXQ_MOD_ERR2RST, /* modify state from error to reset. */ 1664 MLX5_RXQ_MOD_RST2RDY, /* modify state from reset to ready. */ 1665 MLX5_RXQ_MOD_RDY2ERR, /* modify state from ready to error. */ 1666 MLX5_RXQ_MOD_RDY2RST, /* modify state from ready to reset. */ 1667 MLX5_RXQ_MOD_RDY2RDY, /* modify state from ready to ready. */ 1668 }; 1669 1670 enum mlx5_txq_modify_type { 1671 MLX5_TXQ_MOD_RST2RDY, /* modify state from reset to ready. */ 1672 MLX5_TXQ_MOD_RDY2RST, /* modify state from ready to reset. */ 1673 MLX5_TXQ_MOD_ERR2RDY, /* modify state from error to ready. */ 1674 }; 1675 1676 struct mlx5_rxq_priv; 1677 struct mlx5_priv; 1678 1679 /* HW objects operations structure. */ 1680 struct mlx5_obj_ops { 1681 int (*rxq_obj_modify_vlan_strip)(struct mlx5_rxq_priv *rxq, int on); 1682 int (*rxq_obj_new)(struct mlx5_rxq_priv *rxq); 1683 int (*rxq_event_get)(struct mlx5_rxq_obj *rxq_obj); 1684 int (*rxq_obj_modify)(struct mlx5_rxq_priv *rxq, uint8_t type); 1685 void (*rxq_obj_release)(struct mlx5_rxq_priv *rxq); 1686 int (*rxq_event_get_lwm)(struct mlx5_priv *priv, int *rxq_idx, int *port_id); 1687 int (*ind_table_new)(struct rte_eth_dev *dev, const unsigned int log_n, 1688 struct mlx5_ind_table_obj *ind_tbl); 1689 int (*ind_table_modify)(struct rte_eth_dev *dev, 1690 const unsigned int log_n, 1691 const uint16_t *queues, const uint32_t queues_n, 1692 struct mlx5_ind_table_obj *ind_tbl); 1693 void (*ind_table_destroy)(struct mlx5_ind_table_obj *ind_tbl); 1694 int (*hrxq_new)(struct rte_eth_dev *dev, struct mlx5_hrxq *hrxq, 1695 int tunnel __rte_unused); 1696 int (*hrxq_modify)(struct rte_eth_dev *dev, struct mlx5_hrxq *hrxq, 1697 const uint8_t *rss_key, 1698 uint64_t hash_fields, 1699 bool symmetric_hash_function, 1700 const struct mlx5_ind_table_obj *ind_tbl); 1701 void (*hrxq_destroy)(struct mlx5_hrxq *hrxq); 1702 int (*drop_action_create)(struct rte_eth_dev *dev); 1703 void (*drop_action_destroy)(struct rte_eth_dev *dev); 1704 int (*txq_obj_new)(struct rte_eth_dev *dev, uint16_t idx); 1705 int (*txq_obj_modify)(struct mlx5_txq_obj *obj, 1706 enum mlx5_txq_modify_type type, uint8_t dev_port); 1707 void (*txq_obj_release)(struct mlx5_txq_obj *txq_obj); 1708 int (*lb_dummy_queue_create)(struct rte_eth_dev *dev); 1709 void (*lb_dummy_queue_release)(struct rte_eth_dev *dev); 1710 }; 1711 1712 #define MLX5_RSS_HASH_FIELDS_LEN RTE_DIM(mlx5_rss_hash_fields) 1713 1714 enum mlx5_hw_ctrl_flow_type { 1715 MLX5_HW_CTRL_FLOW_TYPE_GENERAL, 1716 MLX5_HW_CTRL_FLOW_TYPE_SQ_MISS_ROOT, 1717 MLX5_HW_CTRL_FLOW_TYPE_SQ_MISS, 1718 MLX5_HW_CTRL_FLOW_TYPE_DEFAULT_JUMP, 1719 MLX5_HW_CTRL_FLOW_TYPE_TX_META_COPY, 1720 MLX5_HW_CTRL_FLOW_TYPE_TX_REPR_MATCH, 1721 MLX5_HW_CTRL_FLOW_TYPE_LACP_RX, 1722 MLX5_HW_CTRL_FLOW_TYPE_DEFAULT_RX_RSS, 1723 }; 1724 1725 /** Additional info about control flow rule. */ 1726 struct mlx5_hw_ctrl_flow_info { 1727 /** Determines the kind of control flow rule. */ 1728 enum mlx5_hw_ctrl_flow_type type; 1729 union { 1730 /** 1731 * If control flow is a SQ miss flow (root or not), 1732 * then fields contains matching SQ number. 1733 */ 1734 uint32_t esw_mgr_sq; 1735 /** 1736 * If control flow is a Tx representor matching, 1737 * then fields contains matching SQ number. 1738 */ 1739 uint32_t tx_repr_sq; 1740 }; 1741 }; 1742 1743 /** Entry for tracking control flow rules in HWS. */ 1744 struct mlx5_hw_ctrl_flow { 1745 LIST_ENTRY(mlx5_hw_ctrl_flow) next; 1746 /** 1747 * Owner device is a port on behalf of which flow rule was created. 1748 * 1749 * It's different from the port which really created the flow rule 1750 * if and only if flow rule is created on transfer proxy port 1751 * on behalf of representor port. 1752 */ 1753 struct rte_eth_dev *owner_dev; 1754 /** Pointer to flow rule handle. */ 1755 struct rte_flow *flow; 1756 /** Additional information about the control flow rule. */ 1757 struct mlx5_hw_ctrl_flow_info info; 1758 }; 1759 1760 /* 1761 * Flow rule structure for flow engine mode control, focus on group 0. 1762 * Apply to all supported domains. 1763 */ 1764 struct mlx5_dv_flow_info { 1765 LIST_ENTRY(mlx5_dv_flow_info) next; 1766 uint32_t orig_prio; /* prio set by user */ 1767 uint32_t flow_idx_high_prio; 1768 /* flow index owned by standby mode. priority is lower unless DUP flags. */ 1769 uint32_t flow_idx_low_prio; 1770 struct rte_flow_item *items; 1771 struct rte_flow_action *actions; 1772 struct rte_flow_attr attr; 1773 }; 1774 1775 struct rte_pmd_mlx5_flow_engine_mode_info { 1776 enum rte_pmd_mlx5_flow_engine_mode mode; 1777 uint32_t mode_flag; 1778 /* The list is maintained in insertion order. */ 1779 LIST_HEAD(hot_up_info, mlx5_dv_flow_info) hot_upgrade; 1780 }; 1781 /* HW Steering port configuration passed to rte_flow_configure(). */ 1782 struct mlx5_flow_hw_attr { 1783 struct rte_flow_port_attr port_attr; 1784 uint16_t nb_queue; 1785 struct rte_flow_queue_attr *queue_attr; 1786 }; 1787 1788 struct mlx5_flow_hw_ctrl_rx; 1789 1790 enum mlx5_quota_state { 1791 MLX5_QUOTA_STATE_FREE, /* quota not in use */ 1792 MLX5_QUOTA_STATE_READY, /* quota is ready */ 1793 MLX5_QUOTA_STATE_WAIT /* quota waits WR completion */ 1794 }; 1795 1796 struct mlx5_quota { 1797 uint8_t state; /* object state */ 1798 uint8_t mode; /* metering mode */ 1799 /** 1800 * Keep track of application update types. 1801 * PMD does not allow 2 consecutive ADD updates. 1802 */ 1803 enum rte_flow_update_quota_op last_update; 1804 }; 1805 1806 /* Bulk management structure for flow quota. */ 1807 struct mlx5_quota_ctx { 1808 struct mlx5dr_action *dr_action; /* HWS action */ 1809 struct mlx5_devx_obj *devx_obj; /* DEVX ranged object. */ 1810 struct mlx5_pmd_mr mr; /* MR for READ from MTR ASO */ 1811 struct mlx5_aso_mtr_dseg **read_buf; /* Buffers for READ */ 1812 struct mlx5_aso_sq *sq; /* SQs for sync/async ACCESS_ASO WRs */ 1813 struct mlx5_indexed_pool *quota_ipool; /* Manage quota objects */ 1814 }; 1815 1816 struct mlx5_priv { 1817 struct rte_eth_dev_data *dev_data; /* Pointer to device data. */ 1818 struct mlx5_dev_ctx_shared *sh; /* Shared device context. */ 1819 uint32_t dev_port; /* Device port number. */ 1820 struct rte_pci_device *pci_dev; /* Backend PCI device. */ 1821 struct rte_ether_addr mac[MLX5_MAX_MAC_ADDRESSES]; /* MAC addresses. */ 1822 BITFIELD_DECLARE(mac_own, uint64_t, MLX5_MAX_MAC_ADDRESSES); 1823 /* Bit-field of MAC addresses owned by the PMD. */ 1824 uint16_t vlan_filter[MLX5_MAX_VLAN_IDS]; /* VLAN filters table. */ 1825 unsigned int vlan_filter_n; /* Number of configured VLAN filters. */ 1826 /* Device properties. */ 1827 uint16_t mtu; /* Configured MTU. */ 1828 unsigned int isolated:1; /* Whether isolated mode is enabled. */ 1829 unsigned int representor:1; /* Device is a port representor. */ 1830 unsigned int master:1; /* Device is a E-Switch master. */ 1831 unsigned int txpp_en:1; /* Tx packet pacing enabled. */ 1832 unsigned int sampler_en:1; /* Whether support sampler. */ 1833 unsigned int mtr_en:1; /* Whether support meter. */ 1834 unsigned int mtr_reg_share:1; /* Whether support meter REG_C share. */ 1835 unsigned int lb_used:1; /* Loopback queue is referred to. */ 1836 unsigned int rmv_notified:1; /* Notified about removal event */ 1837 uint32_t mark_enabled:1; /* If mark action is enabled on rxqs. */ 1838 uint32_t num_lag_ports:4; /* Number of ports can be bonded. */ 1839 uint32_t tunnel_enabled:1; /* If tunnel offloading is enabled on rxqs. */ 1840 uint16_t domain_id; /* Switch domain identifier. */ 1841 uint16_t vport_id; /* Associated VF vport index (if any). */ 1842 uint32_t vport_meta_tag; /* Used for vport index match ove VF LAG. */ 1843 uint32_t vport_meta_mask; /* Used for vport index field match mask. */ 1844 uint16_t representor_id; /* UINT16_MAX if not a representor. */ 1845 int32_t pf_bond; /* >=0, representor owner PF index in bonding. */ 1846 int32_t mpesw_owner; /* >=0, representor owner PF index in MPESW. */ 1847 int32_t mpesw_port; /* Related port index of MPESW device. < 0 - no MPESW. */ 1848 bool mpesw_uplink; /* If true, port is an uplink port. */ 1849 unsigned int if_index; /* Associated kernel network device index. */ 1850 /* RX/TX queues. */ 1851 unsigned int rxqs_n; /* RX queues array size. */ 1852 unsigned int txqs_n; /* TX queues array size. */ 1853 struct mlx5_external_rxq *ext_rxqs; /* External RX queues array. */ 1854 struct mlx5_rxq_priv *(*rxq_privs)[]; /* RX queue non-shared data. */ 1855 struct mlx5_txq_data *(*txqs)[]; /* TX queues. */ 1856 struct rte_mempool *mprq_mp; /* Mempool for Multi-Packet RQ. */ 1857 struct rte_eth_rss_conf rss_conf; /* RSS configuration. */ 1858 unsigned int (*reta_idx)[]; /* RETA index table. */ 1859 unsigned int reta_idx_n; /* RETA index size. */ 1860 struct mlx5_drop drop_queue; /* Flow drop queues. */ 1861 void *root_drop_action; /* Pointer to root drop action. */ 1862 rte_spinlock_t hw_ctrl_lock; 1863 LIST_HEAD(hw_ctrl_flow, mlx5_hw_ctrl_flow) hw_ctrl_flows; 1864 LIST_HEAD(hw_ext_ctrl_flow, mlx5_hw_ctrl_flow) hw_ext_ctrl_flows; 1865 struct rte_flow_template_table *hw_esw_sq_miss_root_tbl; 1866 struct rte_flow_template_table *hw_esw_sq_miss_tbl; 1867 struct rte_flow_template_table *hw_esw_zero_tbl; 1868 struct rte_flow_template_table *hw_tx_meta_cpy_tbl; 1869 struct rte_flow_template_table *hw_lacp_rx_tbl; 1870 struct rte_flow_pattern_template *hw_tx_repr_tagging_pt; 1871 struct rte_flow_actions_template *hw_tx_repr_tagging_at; 1872 struct rte_flow_template_table *hw_tx_repr_tagging_tbl; 1873 struct mlx5_indexed_pool *flows[MLX5_FLOW_TYPE_MAXI]; 1874 /* RTE Flow rules. */ 1875 uint32_t ctrl_flows; /* Control flow rules. */ 1876 rte_spinlock_t flow_list_lock; 1877 struct mlx5_obj_ops obj_ops; /* HW objects operations. */ 1878 LIST_HEAD(rxq, mlx5_rxq_ctrl) rxqsctrl; /* DPDK Rx queues. */ 1879 LIST_HEAD(rxqobj, mlx5_rxq_obj) rxqsobj; /* Verbs/DevX Rx queues. */ 1880 struct mlx5_list *hrxqs; /* Hash Rx queues. */ 1881 LIST_HEAD(txq, mlx5_txq_ctrl) txqsctrl; /* DPDK Tx queues. */ 1882 LIST_HEAD(txqobj, mlx5_txq_obj) txqsobj; /* Verbs/DevX Tx queues. */ 1883 /* Indirection tables. */ 1884 LIST_HEAD(ind_tables, mlx5_ind_table_obj) ind_tbls; 1885 /* Standalone indirect tables. */ 1886 LIST_HEAD(stdl_ind_tables, mlx5_ind_table_obj) standalone_ind_tbls; 1887 /* Objects created with indirect list action */ 1888 LIST_HEAD(indirect_list, mlx5_indirect_list) indirect_list_head; 1889 /* Pointer to next element. */ 1890 rte_rwlock_t ind_tbls_lock; 1891 uint32_t refcnt; /**< Reference counter. */ 1892 /**< Verbs modify header action object. */ 1893 uint8_t ft_type; /**< Flow table type, Rx or Tx. */ 1894 uint32_t max_lro_msg_size; 1895 uint32_t link_speed_capa; /* Link speed capabilities. */ 1896 struct mlx5_xstats_ctrl xstats_ctrl; /* Extended stats control. */ 1897 struct mlx5_stats_ctrl stats_ctrl; /* Stats control. */ 1898 struct mlx5_port_config config; /* Port configuration. */ 1899 /* Context for Verbs allocator. */ 1900 int nl_socket_rdma; /* Netlink socket (NETLINK_RDMA). */ 1901 int nl_socket_route; /* Netlink socket (NETLINK_ROUTE). */ 1902 struct mlx5_nl_vlan_vmwa_context *vmwa_context; /* VLAN WA context. */ 1903 struct mlx5_hlist *mreg_cp_tbl; 1904 /* Hash table of Rx metadata register copy table. */ 1905 struct mlx5_mtr_config mtr_config; /* Meter configuration */ 1906 uint8_t mtr_sfx_reg; /* Meter prefix-suffix flow match REG_C. */ 1907 struct mlx5_legacy_flow_meters flow_meters; /* MTR list. */ 1908 struct mlx5_l3t_tbl *mtr_profile_tbl; /* Meter index lookup table. */ 1909 struct mlx5_flow_meter_profile *mtr_profile_arr; /* Profile array. */ 1910 struct mlx5_l3t_tbl *policy_idx_tbl; /* Policy index lookup table. */ 1911 struct mlx5_flow_meter_policy *mtr_policy_arr; /* Policy array. */ 1912 struct mlx5_l3t_tbl *mtr_idx_tbl; /* Meter index lookup table. */ 1913 struct mlx5_mtr_bulk mtr_bulk; /* Meter index mapping for HWS */ 1914 struct mlx5_quota_ctx quota_ctx; /* Quota index mapping for HWS */ 1915 uint8_t skip_default_rss_reta; /* Skip configuration of default reta. */ 1916 uint8_t fdb_def_rule; /* Whether fdb jump to table 1 is configured. */ 1917 struct mlx5_mp_id mp_id; /* ID of a multi-process process */ 1918 LIST_HEAD(fdir, mlx5_fdir_flow) fdir_flows; /* fdir flows. */ 1919 rte_spinlock_t shared_act_sl; /* Shared actions spinlock. */ 1920 uint32_t rss_shared_actions; /* RSS shared actions. */ 1921 struct mlx5_devx_obj *q_counters; /* DevX queue counter object. */ 1922 uint32_t counter_set_id; /* Queue counter ID to set in DevX objects. */ 1923 uint32_t lag_affinity_idx; /* LAG mode queue 0 affinity starting. */ 1924 rte_spinlock_t flex_item_sl; /* Flex item list spinlock. */ 1925 struct mlx5_flex_item flex_item[MLX5_PORT_FLEX_ITEM_NUM]; 1926 /* Flex items have been created on the port. */ 1927 uint32_t flex_item_map; /* Map of allocated flex item elements. */ 1928 uint32_t nb_queue; /* HW steering queue number. */ 1929 struct mlx5_hws_cnt_pool *hws_cpool; /* HW steering's counter pool. */ 1930 uint32_t hws_mark_refcnt; /* HWS mark action reference counter. */ 1931 struct rte_pmd_mlx5_flow_engine_mode_info mode_info; /* Process set flow engine info. */ 1932 struct mlx5_flow_hw_attr *hw_attr; /* HW Steering port configuration. */ 1933 #if defined(HAVE_IBV_FLOW_DV_SUPPORT) || !defined(HAVE_INFINIBAND_VERBS_H) 1934 /* Item template list. */ 1935 LIST_HEAD(flow_hw_itt, rte_flow_pattern_template) flow_hw_itt; 1936 /* Action template list. */ 1937 LIST_HEAD(flow_hw_at, rte_flow_actions_template) flow_hw_at; 1938 struct mlx5dr_context *dr_ctx; /**< HW steering DR context. */ 1939 /* HW steering queue polling mechanism job descriptor LIFO. */ 1940 uint32_t hws_strict_queue:1; 1941 /**< Whether all operations strictly happen on the same HWS queue. */ 1942 uint32_t hws_age_req:1; /**< Whether this port has AGE indexed pool. */ 1943 struct mlx5_hw_q *hw_q; 1944 /* HW steering rte flow table list header. */ 1945 LIST_HEAD(flow_hw_tbl, rte_flow_template_table) flow_hw_tbl; 1946 /* HW steering rte flow group list header */ 1947 LIST_HEAD(flow_hw_grp, mlx5_flow_group) flow_hw_grp; 1948 struct mlx5dr_action *hw_push_vlan[MLX5DR_TABLE_TYPE_MAX]; 1949 struct mlx5dr_action *hw_pop_vlan[MLX5DR_TABLE_TYPE_MAX]; 1950 struct mlx5dr_action **hw_vport; 1951 /* HW steering global drop action. */ 1952 struct mlx5dr_action *hw_drop[2]; 1953 /* HW steering global tag action. */ 1954 struct mlx5dr_action *hw_tag[2]; 1955 /* HW steering global default miss action. */ 1956 struct mlx5dr_action *hw_def_miss; 1957 /* HW steering global send to kernel action. */ 1958 struct mlx5dr_action *hw_send_to_kernel[MLX5DR_TABLE_TYPE_MAX]; 1959 /* HW steering create ongoing rte flow table list header. */ 1960 LIST_HEAD(flow_hw_tbl_ongo, rte_flow_template_table) flow_hw_tbl_ongo; 1961 struct mlx5_indexed_pool *acts_ipool; /* Action data indexed pool. */ 1962 struct mlx5_aso_ct_pools_mng *ct_mng; 1963 /* Management data for ASO connection tracking. */ 1964 struct mlx5_aso_ct_pool *hws_ctpool; /* HW steering's CT pool. */ 1965 struct mlx5_aso_mtr_pool *hws_mpool; /* HW steering's Meter pool. */ 1966 struct mlx5_flow_hw_ctrl_rx *hw_ctrl_rx; 1967 /**< HW steering templates used to create control flow rules. */ 1968 #endif 1969 struct rte_eth_dev *shared_host; /* Host device for HW steering. */ 1970 uint16_t shared_refcnt; /* HW steering host reference counter. */ 1971 }; 1972 1973 #define PORT_ID(priv) ((priv)->dev_data->port_id) 1974 #define ETH_DEV(priv) (&rte_eth_devices[PORT_ID(priv)]) 1975 #define CTRL_QUEUE_ID(priv) ((priv)->nb_queue - 1) 1976 1977 struct rte_hairpin_peer_info { 1978 uint32_t qp_id; 1979 uint32_t vhca_id; 1980 uint16_t peer_q; 1981 uint16_t tx_explicit; 1982 uint16_t manual_bind; 1983 }; 1984 1985 #define BUF_SIZE 1024 1986 enum dr_dump_rec_type { 1987 DR_DUMP_REC_TYPE_PMD_PKT_REFORMAT = 4410, 1988 DR_DUMP_REC_TYPE_PMD_MODIFY_HDR = 4420, 1989 DR_DUMP_REC_TYPE_PMD_COUNTER = 4430, 1990 }; 1991 1992 /** 1993 * Indicates whether HW objects operations can be created by DevX. 1994 * 1995 * This function is used for both: 1996 * Before creation - deciding whether to create HW objects operations by DevX. 1997 * After creation - indicator if HW objects operations were created by DevX. 1998 * 1999 * @param sh 2000 * Pointer to shared device context. 2001 * 2002 * @return 2003 * True if HW objects were created by DevX, False otherwise. 2004 */ 2005 static inline bool 2006 mlx5_devx_obj_ops_en(struct mlx5_dev_ctx_shared *sh) 2007 { 2008 /* 2009 * When advanced DR API is available and DV flow is supported and 2010 * DevX is supported, HW objects operations are created by DevX. 2011 */ 2012 return (sh->cdev->config.devx && sh->config.dv_flow_en && 2013 sh->dev_cap.dest_tir); 2014 } 2015 2016 /** 2017 * Check if the port is either MPESW physical device or a representor port. 2018 * 2019 * @param priv 2020 * Pointer to port's private data. 2021 * 2022 * @return 2023 * True if the port is a physical device or representor in MPESW setup. 2024 * False otherwise or MPESW was not configured. 2025 */ 2026 static inline bool 2027 mlx5_is_port_on_mpesw_device(struct mlx5_priv *priv) 2028 { 2029 return priv->mpesw_port >= 0; 2030 } 2031 2032 /* mlx5.c */ 2033 2034 int mlx5_getenv_int(const char *); 2035 int mlx5_proc_priv_init(struct rte_eth_dev *dev); 2036 void mlx5_proc_priv_uninit(struct rte_eth_dev *dev); 2037 int mlx5_udp_tunnel_port_add(struct rte_eth_dev *dev, 2038 struct rte_eth_udp_tunnel *udp_tunnel); 2039 uint16_t mlx5_eth_find_next(uint16_t port_id, struct rte_device *odev); 2040 int mlx5_dev_close(struct rte_eth_dev *dev); 2041 int mlx5_net_remove(struct mlx5_common_device *cdev); 2042 bool mlx5_is_hpf(struct rte_eth_dev *dev); 2043 bool mlx5_is_sf_repr(struct rte_eth_dev *dev); 2044 void mlx5_age_event_prepare(struct mlx5_dev_ctx_shared *sh); 2045 int mlx5_lwm_setup(struct mlx5_priv *priv); 2046 void mlx5_lwm_unset(struct mlx5_dev_ctx_shared *sh); 2047 2048 /* Macro to iterate over all valid ports for mlx5 driver. */ 2049 #define MLX5_ETH_FOREACH_DEV(port_id, dev) \ 2050 for (port_id = mlx5_eth_find_next(0, dev); \ 2051 port_id < RTE_MAX_ETHPORTS; \ 2052 port_id = mlx5_eth_find_next(port_id + 1, dev)) 2053 void mlx5_rt_timestamp_config(struct mlx5_dev_ctx_shared *sh, 2054 struct mlx5_hca_attr *hca_attr); 2055 struct mlx5_dev_ctx_shared * 2056 mlx5_alloc_shared_dev_ctx(const struct mlx5_dev_spawn_data *spawn, 2057 struct mlx5_kvargs_ctrl *mkvlist); 2058 void mlx5_free_shared_dev_ctx(struct mlx5_dev_ctx_shared *sh); 2059 int mlx5_dev_ctx_shared_mempool_subscribe(struct rte_eth_dev *dev); 2060 void mlx5_free_table_hash_list(struct mlx5_priv *priv); 2061 int mlx5_alloc_table_hash_list(struct mlx5_priv *priv); 2062 void mlx5_set_min_inline(struct mlx5_priv *priv); 2063 void mlx5_set_metadata_mask(struct rte_eth_dev *dev); 2064 int mlx5_probe_again_args_validate(struct mlx5_common_device *cdev, 2065 struct mlx5_kvargs_ctrl *mkvlist); 2066 int mlx5_port_args_config(struct mlx5_priv *priv, 2067 struct mlx5_kvargs_ctrl *mkvlist, 2068 struct mlx5_port_config *config); 2069 void mlx5_port_args_set_used(const char *name, uint16_t port_id, 2070 struct mlx5_kvargs_ctrl *mkvlist); 2071 bool mlx5_flex_parser_ecpri_exist(struct rte_eth_dev *dev); 2072 int mlx5_flex_parser_ecpri_alloc(struct rte_eth_dev *dev); 2073 void mlx5_flow_counter_mode_config(struct rte_eth_dev *dev); 2074 int mlx5_flow_aso_age_mng_init(struct mlx5_dev_ctx_shared *sh); 2075 int mlx5_aso_flow_mtrs_mng_init(struct mlx5_dev_ctx_shared *sh); 2076 int mlx5_flow_aso_ct_mng_init(struct mlx5_dev_ctx_shared *sh); 2077 2078 /* mlx5_ethdev.c */ 2079 2080 int mlx5_dev_configure(struct rte_eth_dev *dev); 2081 int mlx5_representor_info_get(struct rte_eth_dev *dev, 2082 struct rte_eth_representor_info *info); 2083 #define MLX5_REPRESENTOR_ID(pf, type, repr) \ 2084 (((pf) << 14) + ((type) << 12) + ((repr) & 0xfff)) 2085 #define MLX5_REPRESENTOR_REPR(repr_id) \ 2086 ((repr_id) & 0xfff) 2087 #define MLX5_REPRESENTOR_TYPE(repr_id) \ 2088 (((repr_id) >> 12) & 3) 2089 uint16_t mlx5_representor_id_encode(const struct mlx5_switch_info *info, 2090 enum rte_eth_representor_type hpf_type); 2091 int mlx5_dev_infos_get(struct rte_eth_dev *dev, struct rte_eth_dev_info *info); 2092 int mlx5_fw_version_get(struct rte_eth_dev *dev, char *fw_ver, size_t fw_size); 2093 const uint32_t *mlx5_dev_supported_ptypes_get(struct rte_eth_dev *dev); 2094 int mlx5_dev_set_mtu(struct rte_eth_dev *dev, uint16_t mtu); 2095 int mlx5_hairpin_cap_get(struct rte_eth_dev *dev, 2096 struct rte_eth_hairpin_cap *cap); 2097 eth_rx_burst_t mlx5_select_rx_function(struct rte_eth_dev *dev); 2098 struct mlx5_priv *mlx5_port_to_eswitch_info(uint16_t port, bool valid); 2099 struct mlx5_priv *mlx5_dev_to_eswitch_info(struct rte_eth_dev *dev); 2100 int mlx5_dev_configure_rss_reta(struct rte_eth_dev *dev); 2101 2102 /* mlx5_ethdev_os.c */ 2103 2104 int mlx5_get_ifname(const struct rte_eth_dev *dev, 2105 char (*ifname)[MLX5_NAMESIZE]); 2106 unsigned int mlx5_ifindex(const struct rte_eth_dev *dev); 2107 int mlx5_get_mac(struct rte_eth_dev *dev, uint8_t (*mac)[RTE_ETHER_ADDR_LEN]); 2108 int mlx5_get_mtu(struct rte_eth_dev *dev, uint16_t *mtu); 2109 int mlx5_set_mtu(struct rte_eth_dev *dev, uint16_t mtu); 2110 int mlx5_read_clock(struct rte_eth_dev *dev, uint64_t *clock); 2111 int mlx5_link_update(struct rte_eth_dev *dev, int wait_to_complete); 2112 int mlx5_dev_get_flow_ctrl(struct rte_eth_dev *dev, 2113 struct rte_eth_fc_conf *fc_conf); 2114 int mlx5_dev_set_flow_ctrl(struct rte_eth_dev *dev, 2115 struct rte_eth_fc_conf *fc_conf); 2116 void mlx5_dev_interrupt_handler(void *arg); 2117 void mlx5_dev_interrupt_handler_devx(void *arg); 2118 void mlx5_dev_interrupt_handler_nl(void *arg); 2119 int mlx5_set_link_down(struct rte_eth_dev *dev); 2120 int mlx5_set_link_up(struct rte_eth_dev *dev); 2121 int mlx5_is_removed(struct rte_eth_dev *dev); 2122 int mlx5_sysfs_switch_info(unsigned int ifindex, 2123 struct mlx5_switch_info *info); 2124 void mlx5_translate_port_name(const char *port_name_in, 2125 struct mlx5_switch_info *port_info_out); 2126 int mlx5_sysfs_bond_info(unsigned int pf_ifindex, unsigned int *ifindex, 2127 char *ifname); 2128 int mlx5_get_module_info(struct rte_eth_dev *dev, 2129 struct rte_eth_dev_module_info *modinfo); 2130 int mlx5_get_module_eeprom(struct rte_eth_dev *dev, 2131 struct rte_dev_eeprom_info *info); 2132 int mlx5_os_read_dev_stat(struct mlx5_priv *priv, 2133 const char *ctr_name, uint64_t *stat); 2134 int mlx5_os_read_dev_counters(struct rte_eth_dev *dev, uint64_t *stats); 2135 int mlx5_os_get_stats_n(struct rte_eth_dev *dev); 2136 void mlx5_os_stats_init(struct rte_eth_dev *dev); 2137 int mlx5_get_flag_dropless_rq(struct rte_eth_dev *dev); 2138 2139 /* mlx5_mac.c */ 2140 2141 void mlx5_mac_addr_remove(struct rte_eth_dev *dev, uint32_t index); 2142 int mlx5_mac_addr_add(struct rte_eth_dev *dev, struct rte_ether_addr *mac, 2143 uint32_t index, uint32_t vmdq); 2144 int mlx5_mac_addr_set(struct rte_eth_dev *dev, struct rte_ether_addr *mac_addr); 2145 int mlx5_set_mc_addr_list(struct rte_eth_dev *dev, 2146 struct rte_ether_addr *mc_addr_set, 2147 uint32_t nb_mc_addr); 2148 2149 /* mlx5_rss.c */ 2150 2151 int mlx5_rss_hash_update(struct rte_eth_dev *dev, 2152 struct rte_eth_rss_conf *rss_conf); 2153 int mlx5_rss_hash_conf_get(struct rte_eth_dev *dev, 2154 struct rte_eth_rss_conf *rss_conf); 2155 int mlx5_rss_reta_index_resize(struct rte_eth_dev *dev, unsigned int reta_size); 2156 int mlx5_dev_rss_reta_query(struct rte_eth_dev *dev, 2157 struct rte_eth_rss_reta_entry64 *reta_conf, 2158 uint16_t reta_size); 2159 int mlx5_dev_rss_reta_update(struct rte_eth_dev *dev, 2160 struct rte_eth_rss_reta_entry64 *reta_conf, 2161 uint16_t reta_size); 2162 2163 /* mlx5_rxmode.c */ 2164 2165 int mlx5_promiscuous_enable(struct rte_eth_dev *dev); 2166 int mlx5_promiscuous_disable(struct rte_eth_dev *dev); 2167 int mlx5_allmulticast_enable(struct rte_eth_dev *dev); 2168 int mlx5_allmulticast_disable(struct rte_eth_dev *dev); 2169 2170 /* mlx5_stats.c */ 2171 2172 int mlx5_stats_get(struct rte_eth_dev *dev, struct rte_eth_stats *stats); 2173 int mlx5_stats_reset(struct rte_eth_dev *dev); 2174 int mlx5_xstats_get(struct rte_eth_dev *dev, struct rte_eth_xstat *stats, 2175 unsigned int n); 2176 int mlx5_xstats_reset(struct rte_eth_dev *dev); 2177 int mlx5_xstats_get_names(struct rte_eth_dev *dev __rte_unused, 2178 struct rte_eth_xstat_name *xstats_names, 2179 unsigned int n); 2180 2181 /* mlx5_vlan.c */ 2182 2183 int mlx5_vlan_filter_set(struct rte_eth_dev *dev, uint16_t vlan_id, int on); 2184 void mlx5_vlan_strip_queue_set(struct rte_eth_dev *dev, uint16_t queue, int on); 2185 int mlx5_vlan_offload_set(struct rte_eth_dev *dev, int mask); 2186 2187 /* mlx5_vlan_os.c */ 2188 2189 void mlx5_vlan_vmwa_exit(void *ctx); 2190 void mlx5_vlan_vmwa_release(struct rte_eth_dev *dev, 2191 struct mlx5_vf_vlan *vf_vlan); 2192 void mlx5_vlan_vmwa_acquire(struct rte_eth_dev *dev, 2193 struct mlx5_vf_vlan *vf_vlan); 2194 void *mlx5_vlan_vmwa_init(struct rte_eth_dev *dev, uint32_t ifindex); 2195 2196 /* mlx5_trigger.c */ 2197 2198 int mlx5_dev_start(struct rte_eth_dev *dev); 2199 int mlx5_dev_stop(struct rte_eth_dev *dev); 2200 int mlx5_traffic_enable(struct rte_eth_dev *dev); 2201 void mlx5_traffic_disable(struct rte_eth_dev *dev); 2202 int mlx5_traffic_restart(struct rte_eth_dev *dev); 2203 int mlx5_hairpin_queue_peer_update(struct rte_eth_dev *dev, uint16_t peer_queue, 2204 struct rte_hairpin_peer_info *current_info, 2205 struct rte_hairpin_peer_info *peer_info, 2206 uint32_t direction); 2207 int mlx5_hairpin_queue_peer_bind(struct rte_eth_dev *dev, uint16_t cur_queue, 2208 struct rte_hairpin_peer_info *peer_info, 2209 uint32_t direction); 2210 int mlx5_hairpin_queue_peer_unbind(struct rte_eth_dev *dev, uint16_t cur_queue, 2211 uint32_t direction); 2212 int mlx5_hairpin_bind(struct rte_eth_dev *dev, uint16_t rx_port); 2213 int mlx5_hairpin_unbind(struct rte_eth_dev *dev, uint16_t rx_port); 2214 int mlx5_hairpin_get_peer_ports(struct rte_eth_dev *dev, uint16_t *peer_ports, 2215 size_t len, uint32_t direction); 2216 2217 /* mlx5_flow.c */ 2218 2219 int mlx5_flow_discover_mreg_c(struct rte_eth_dev *eth_dev); 2220 bool mlx5_flow_ext_mreg_supported(struct rte_eth_dev *dev); 2221 void mlx5_flow_print(struct rte_flow *flow); 2222 int mlx5_flow_validate(struct rte_eth_dev *dev, 2223 const struct rte_flow_attr *attr, 2224 const struct rte_flow_item items[], 2225 const struct rte_flow_action actions[], 2226 struct rte_flow_error *error); 2227 struct rte_flow *mlx5_flow_create(struct rte_eth_dev *dev, 2228 const struct rte_flow_attr *attr, 2229 const struct rte_flow_item items[], 2230 const struct rte_flow_action actions[], 2231 struct rte_flow_error *error); 2232 int mlx5_flow_destroy(struct rte_eth_dev *dev, struct rte_flow *flow, 2233 struct rte_flow_error *error); 2234 void mlx5_flow_list_flush(struct rte_eth_dev *dev, enum mlx5_flow_type type, 2235 bool active); 2236 int mlx5_flow_flush(struct rte_eth_dev *dev, struct rte_flow_error *error); 2237 int mlx5_flow_query(struct rte_eth_dev *dev, struct rte_flow *flow, 2238 const struct rte_flow_action *action, void *data, 2239 struct rte_flow_error *error); 2240 int mlx5_flow_isolate(struct rte_eth_dev *dev, int enable, 2241 struct rte_flow_error *error); 2242 int mlx5_flow_ops_get(struct rte_eth_dev *dev, const struct rte_flow_ops **ops); 2243 int mlx5_flow_start_default(struct rte_eth_dev *dev); 2244 void mlx5_flow_stop_default(struct rte_eth_dev *dev); 2245 int mlx5_flow_verify(struct rte_eth_dev *dev); 2246 int mlx5_ctrl_flow_source_queue(struct rte_eth_dev *dev, uint32_t sq_num); 2247 int mlx5_ctrl_flow_vlan(struct rte_eth_dev *dev, 2248 struct rte_flow_item_eth *eth_spec, 2249 struct rte_flow_item_eth *eth_mask, 2250 struct rte_flow_item_vlan *vlan_spec, 2251 struct rte_flow_item_vlan *vlan_mask); 2252 int mlx5_ctrl_flow(struct rte_eth_dev *dev, 2253 struct rte_flow_item_eth *eth_spec, 2254 struct rte_flow_item_eth *eth_mask); 2255 int mlx5_flow_lacp_miss(struct rte_eth_dev *dev); 2256 struct rte_flow *mlx5_flow_create_esw_table_zero_flow(struct rte_eth_dev *dev); 2257 uint32_t mlx5_flow_create_devx_sq_miss_flow(struct rte_eth_dev *dev, 2258 uint32_t sq_num); 2259 void mlx5_flow_async_pool_query_handle(struct mlx5_dev_ctx_shared *sh, 2260 uint64_t async_id, int status); 2261 void mlx5_set_query_alarm(struct mlx5_dev_ctx_shared *sh); 2262 void mlx5_flow_query_alarm(void *arg); 2263 uint32_t mlx5_counter_alloc(struct rte_eth_dev *dev); 2264 void mlx5_counter_free(struct rte_eth_dev *dev, uint32_t cnt); 2265 int mlx5_counter_query(struct rte_eth_dev *dev, uint32_t cnt, 2266 bool clear, uint64_t *pkts, uint64_t *bytes, void **action); 2267 int mlx5_flow_dev_dump(struct rte_eth_dev *dev, struct rte_flow *flow, 2268 FILE *file, struct rte_flow_error *error); 2269 int save_dump_file(const unsigned char *data, uint32_t size, 2270 uint32_t type, uint64_t id, void *arg, FILE *file); 2271 int mlx5_flow_query_counter(struct rte_eth_dev *dev, struct rte_flow *flow, 2272 struct rte_flow_query_count *count, struct rte_flow_error *error); 2273 #ifdef HAVE_IBV_FLOW_DV_SUPPORT 2274 int mlx5_flow_dev_dump_ipool(struct rte_eth_dev *dev, struct rte_flow *flow, 2275 FILE *file, struct rte_flow_error *error); 2276 #endif 2277 int mlx5_flow_rx_metadata_negotiate(struct rte_eth_dev *dev, 2278 uint64_t *features); 2279 void mlx5_flow_rxq_dynf_set(struct rte_eth_dev *dev); 2280 int mlx5_flow_get_aged_flows(struct rte_eth_dev *dev, void **contexts, 2281 uint32_t nb_contexts, struct rte_flow_error *error); 2282 int mlx5_validate_action_ct(struct rte_eth_dev *dev, 2283 const struct rte_flow_action_conntrack *conntrack, 2284 struct rte_flow_error *error); 2285 2286 int mlx5_flow_get_q_aged_flows(struct rte_eth_dev *dev, uint32_t queue_id, 2287 void **contexts, uint32_t nb_contexts, 2288 struct rte_flow_error *error); 2289 2290 /* mlx5_mp_os.c */ 2291 2292 int mlx5_mp_os_primary_handle(const struct rte_mp_msg *mp_msg, 2293 const void *peer); 2294 int mlx5_mp_os_secondary_handle(const struct rte_mp_msg *mp_msg, 2295 const void *peer); 2296 void mlx5_mp_os_req_start_rxtx(struct rte_eth_dev *dev); 2297 void mlx5_mp_os_req_stop_rxtx(struct rte_eth_dev *dev); 2298 int mlx5_mp_os_req_queue_control(struct rte_eth_dev *dev, uint16_t queue_id, 2299 enum mlx5_mp_req_type req_type); 2300 2301 /* mlx5_socket.c */ 2302 2303 int mlx5_pmd_socket_init(void); 2304 void mlx5_pmd_socket_uninit(void); 2305 2306 /* mlx5_flow_meter.c */ 2307 2308 int mlx5_flow_meter_init(struct rte_eth_dev *dev, 2309 uint32_t nb_meters, 2310 uint32_t nb_meter_profiles, 2311 uint32_t nb_meter_policies, 2312 uint32_t nb_queues); 2313 void mlx5_flow_meter_uninit(struct rte_eth_dev *dev); 2314 int mlx5_flow_meter_ops_get(struct rte_eth_dev *dev, void *arg); 2315 struct mlx5_flow_meter_info *mlx5_flow_meter_find(struct mlx5_priv *priv, 2316 uint32_t meter_id, uint32_t *mtr_idx); 2317 struct mlx5_flow_meter_info * 2318 flow_dv_meter_find_by_idx(struct mlx5_priv *priv, uint32_t idx); 2319 int mlx5_flow_meter_attach(struct mlx5_priv *priv, 2320 struct mlx5_flow_meter_info *fm, 2321 const struct rte_flow_attr *attr, 2322 struct rte_flow_error *error); 2323 void mlx5_flow_meter_detach(struct mlx5_priv *priv, 2324 struct mlx5_flow_meter_info *fm); 2325 struct mlx5_flow_meter_policy *mlx5_flow_meter_policy_find 2326 (struct rte_eth_dev *dev, 2327 uint32_t policy_id, 2328 uint32_t *policy_idx); 2329 struct mlx5_flow_meter_info * 2330 mlx5_flow_meter_hierarchy_next_meter(struct mlx5_priv *priv, 2331 struct mlx5_flow_meter_policy *policy, 2332 uint32_t *mtr_idx); 2333 struct mlx5_flow_meter_policy * 2334 mlx5_flow_meter_hierarchy_get_final_policy(struct rte_eth_dev *dev, 2335 struct mlx5_flow_meter_policy *policy); 2336 int mlx5_flow_meter_flush(struct rte_eth_dev *dev, 2337 struct rte_mtr_error *error); 2338 void mlx5_flow_meter_rxq_flush(struct rte_eth_dev *dev); 2339 2340 /* mlx5_os.c */ 2341 2342 struct rte_pci_driver; 2343 int mlx5_os_capabilities_prepare(struct mlx5_dev_ctx_shared *sh); 2344 void mlx5_os_free_shared_dr(struct mlx5_priv *priv); 2345 int mlx5_os_net_probe(struct mlx5_common_device *cdev, 2346 struct mlx5_kvargs_ctrl *mkvlist); 2347 void mlx5_os_dev_shared_handler_install(struct mlx5_dev_ctx_shared *sh); 2348 void mlx5_os_dev_shared_handler_uninstall(struct mlx5_dev_ctx_shared *sh); 2349 void mlx5_os_mac_addr_remove(struct rte_eth_dev *dev, uint32_t index); 2350 int mlx5_os_mac_addr_add(struct rte_eth_dev *dev, struct rte_ether_addr *mac, 2351 uint32_t index); 2352 int mlx5_os_vf_mac_addr_modify(struct mlx5_priv *priv, unsigned int iface_idx, 2353 struct rte_ether_addr *mac_addr, 2354 int vf_index); 2355 int mlx5_os_set_promisc(struct rte_eth_dev *dev, int enable); 2356 int mlx5_os_set_allmulti(struct rte_eth_dev *dev, int enable); 2357 int mlx5_os_set_nonblock_channel_fd(int fd); 2358 void mlx5_os_mac_addr_flush(struct rte_eth_dev *dev); 2359 void mlx5_os_net_cleanup(void); 2360 2361 /* mlx5_txpp.c */ 2362 2363 int mlx5_txpp_start(struct rte_eth_dev *dev); 2364 void mlx5_txpp_stop(struct rte_eth_dev *dev); 2365 int mlx5_txpp_read_clock(struct rte_eth_dev *dev, uint64_t *timestamp); 2366 int mlx5_txpp_xstats_get(struct rte_eth_dev *dev, 2367 struct rte_eth_xstat *stats, 2368 unsigned int n, unsigned int n_used); 2369 int mlx5_txpp_xstats_reset(struct rte_eth_dev *dev); 2370 int mlx5_txpp_xstats_get_names(struct rte_eth_dev *dev, 2371 struct rte_eth_xstat_name *xstats_names, 2372 unsigned int n, unsigned int n_used); 2373 void mlx5_txpp_interrupt_handler(void *cb_arg); 2374 int mlx5_txpp_map_hca_bar(struct rte_eth_dev *dev); 2375 void mlx5_txpp_unmap_hca_bar(struct rte_eth_dev *dev); 2376 2377 /* mlx5_rxtx.c */ 2378 2379 eth_tx_burst_t mlx5_select_tx_function(struct rte_eth_dev *dev); 2380 2381 /* mlx5_flow_aso.c */ 2382 2383 int mlx5_aso_mtr_queue_init(struct mlx5_dev_ctx_shared *sh, 2384 struct mlx5_aso_mtr_pool *hws_pool, 2385 struct mlx5_aso_mtr_pools_mng *pool_mng, 2386 uint32_t nb_queues); 2387 void mlx5_aso_mtr_queue_uninit(struct mlx5_dev_ctx_shared *sh, 2388 struct mlx5_aso_mtr_pool *hws_pool, 2389 struct mlx5_aso_mtr_pools_mng *pool_mng); 2390 int mlx5_aso_queue_init(struct mlx5_dev_ctx_shared *sh, 2391 enum mlx5_access_aso_opc_mod aso_opc_mode, 2392 uint32_t nb_queues); 2393 int mlx5_aso_flow_hit_queue_poll_start(struct mlx5_dev_ctx_shared *sh); 2394 int mlx5_aso_flow_hit_queue_poll_stop(struct mlx5_dev_ctx_shared *sh); 2395 void mlx5_aso_queue_uninit(struct mlx5_dev_ctx_shared *sh, 2396 enum mlx5_access_aso_opc_mod aso_opc_mod); 2397 int mlx5_aso_meter_update_by_wqe(struct mlx5_dev_ctx_shared *sh, uint32_t queue, 2398 struct mlx5_aso_mtr *mtr, struct mlx5_mtr_bulk *bulk, 2399 void *user_data, bool push); 2400 int mlx5_aso_mtr_wait(struct mlx5_dev_ctx_shared *sh, uint32_t queue, 2401 struct mlx5_aso_mtr *mtr); 2402 int mlx5_aso_ct_update_by_wqe(struct mlx5_dev_ctx_shared *sh, uint32_t queue, 2403 struct mlx5_aso_ct_action *ct, 2404 const struct rte_flow_action_conntrack *profile, 2405 void *user_data, 2406 bool push); 2407 int mlx5_aso_ct_wait_ready(struct mlx5_dev_ctx_shared *sh, uint32_t queue, 2408 struct mlx5_aso_ct_action *ct); 2409 int mlx5_aso_ct_query_by_wqe(struct mlx5_dev_ctx_shared *sh, uint32_t queue, 2410 struct mlx5_aso_ct_action *ct, 2411 struct rte_flow_action_conntrack *profile, 2412 void *user_data, bool push); 2413 int mlx5_aso_ct_available(struct mlx5_dev_ctx_shared *sh, uint32_t queue, 2414 struct mlx5_aso_ct_action *ct); 2415 uint32_t 2416 mlx5_get_supported_sw_parsing_offloads(const struct mlx5_hca_attr *attr); 2417 uint32_t 2418 mlx5_get_supported_tunneling_offloads(const struct mlx5_hca_attr *attr); 2419 2420 void mlx5_aso_ct_obj_analyze(struct rte_flow_action_conntrack *profile, 2421 char *wdata); 2422 void mlx5_aso_push_wqe(struct mlx5_dev_ctx_shared *sh, 2423 struct mlx5_aso_sq *sq); 2424 int mlx5_aso_pull_completion(struct mlx5_aso_sq *sq, 2425 struct rte_flow_op_result res[], 2426 uint16_t n_res); 2427 int mlx5_aso_cnt_queue_init(struct mlx5_dev_ctx_shared *sh); 2428 void mlx5_aso_cnt_queue_uninit(struct mlx5_dev_ctx_shared *sh); 2429 int mlx5_aso_cnt_query(struct mlx5_dev_ctx_shared *sh, 2430 struct mlx5_hws_cnt_pool *cpool); 2431 int mlx5_aso_ct_queue_init(struct mlx5_dev_ctx_shared *sh, 2432 struct mlx5_aso_ct_pools_mng *ct_mng, 2433 uint32_t nb_queues); 2434 int mlx5_aso_ct_queue_uninit(struct mlx5_dev_ctx_shared *sh, 2435 struct mlx5_aso_ct_pools_mng *ct_mng); 2436 int 2437 mlx5_aso_sq_create(struct mlx5_common_device *cdev, struct mlx5_aso_sq *sq, 2438 void *uar, uint16_t log_desc_n); 2439 void 2440 mlx5_aso_destroy_sq(struct mlx5_aso_sq *sq); 2441 void 2442 mlx5_aso_mtr_init_sq(struct mlx5_aso_sq *sq); 2443 void 2444 mlx5_aso_cqe_err_handle(struct mlx5_aso_sq *sq); 2445 2446 /* mlx5_flow_flex.c */ 2447 2448 struct rte_flow_item_flex_handle * 2449 flow_dv_item_create(struct rte_eth_dev *dev, 2450 const struct rte_flow_item_flex_conf *conf, 2451 struct rte_flow_error *error); 2452 int flow_dv_item_release(struct rte_eth_dev *dev, 2453 const struct rte_flow_item_flex_handle *flex_handle, 2454 struct rte_flow_error *error); 2455 int mlx5_flex_item_port_init(struct rte_eth_dev *dev); 2456 void mlx5_flex_item_port_cleanup(struct rte_eth_dev *dev); 2457 void mlx5_flex_flow_translate_item(struct rte_eth_dev *dev, void *matcher, 2458 void *key, const struct rte_flow_item *item, 2459 bool is_inner); 2460 int mlx5_flex_get_sample_id(const struct mlx5_flex_item *tp, 2461 uint32_t idx, uint32_t *pos, 2462 bool is_inner, uint32_t *def); 2463 int mlx5_flex_get_parser_value_per_byte_off(const struct rte_flow_item_flex *item, 2464 void *flex, uint32_t byte_off, 2465 bool is_mask, bool tunnel, uint32_t *value); 2466 int mlx5_flex_acquire_index(struct rte_eth_dev *dev, 2467 struct rte_flow_item_flex_handle *handle, 2468 bool acquire); 2469 int mlx5_flex_release_index(struct rte_eth_dev *dev, int index); 2470 2471 /* Flex parser list callbacks. */ 2472 struct mlx5_list_entry *mlx5_flex_parser_create_cb(void *list_ctx, void *ctx); 2473 int mlx5_flex_parser_match_cb(void *list_ctx, 2474 struct mlx5_list_entry *iter, void *ctx); 2475 void mlx5_flex_parser_remove_cb(void *list_ctx, struct mlx5_list_entry *entry); 2476 struct mlx5_list_entry *mlx5_flex_parser_clone_cb(void *list_ctx, 2477 struct mlx5_list_entry *entry, 2478 void *ctx); 2479 void mlx5_flex_parser_clone_free_cb(void *tool_ctx, 2480 struct mlx5_list_entry *entry); 2481 2482 int 2483 mlx5_flow_quota_destroy(struct rte_eth_dev *dev); 2484 int 2485 mlx5_flow_quota_init(struct rte_eth_dev *dev, uint32_t nb_quotas); 2486 struct rte_flow_action_handle * 2487 mlx5_quota_alloc(struct rte_eth_dev *dev, uint32_t queue, 2488 const struct rte_flow_action_quota *conf, 2489 struct mlx5_hw_q_job *job, bool push, 2490 struct rte_flow_error *error); 2491 void 2492 mlx5_quota_async_completion(struct rte_eth_dev *dev, uint32_t queue, 2493 struct mlx5_hw_q_job *job); 2494 int 2495 mlx5_quota_query_update(struct rte_eth_dev *dev, uint32_t queue, 2496 struct rte_flow_action_handle *handle, 2497 const struct rte_flow_action *update, 2498 struct rte_flow_query_quota *query, 2499 struct mlx5_hw_q_job *async_job, bool push, 2500 struct rte_flow_error *error); 2501 int mlx5_quota_query(struct rte_eth_dev *dev, uint32_t queue, 2502 const struct rte_flow_action_handle *handle, 2503 struct rte_flow_query_quota *query, 2504 struct mlx5_hw_q_job *async_job, bool push, 2505 struct rte_flow_error *error); 2506 2507 int mlx5_alloc_srh_flex_parser(struct rte_eth_dev *dev); 2508 2509 void mlx5_free_srh_flex_parser(struct rte_eth_dev *dev); 2510 #endif /* RTE_PMD_MLX5_H_ */ 2511