1 /* SPDX-License-Identifier: BSD-3-Clause 2 * Copyright 2015 6WIND S.A. 3 * Copyright 2015 Mellanox Technologies, Ltd 4 */ 5 6 #ifndef RTE_PMD_MLX5_H_ 7 #define RTE_PMD_MLX5_H_ 8 9 #include <stddef.h> 10 #include <stdbool.h> 11 #include <stdint.h> 12 #include <limits.h> 13 #include <sys/queue.h> 14 15 #include <rte_pci.h> 16 #include <rte_ether.h> 17 #include <ethdev_driver.h> 18 #include <rte_rwlock.h> 19 #include <rte_interrupts.h> 20 #include <rte_errno.h> 21 #include <rte_flow.h> 22 #include <rte_mtr.h> 23 24 #include <mlx5_glue.h> 25 #include <mlx5_devx_cmds.h> 26 #include <mlx5_prm.h> 27 #include <mlx5_common_mp.h> 28 #include <mlx5_common_mr.h> 29 #include <mlx5_common_devx.h> 30 #include <mlx5_common_defs.h> 31 32 #include "mlx5_defs.h" 33 #include "mlx5_utils.h" 34 #include "mlx5_os.h" 35 #include "mlx5_autoconf.h" 36 37 38 #define MLX5_SH(dev) (((struct mlx5_priv *)(dev)->data->dev_private)->sh) 39 40 /* 41 * Number of modification commands. 42 * The maximal actions amount in FW is some constant, and it is 16 in the 43 * latest releases. In some old releases, it will be limited to 8. 44 * Since there is no interface to query the capacity, the maximal value should 45 * be used to allow PMD to create the flow. The validation will be done in the 46 * lower driver layer or FW. A failure will be returned if exceeds the maximal 47 * supported actions number on the root table. 48 * On non-root tables, there is no limitation, but 32 is enough right now. 49 */ 50 #define MLX5_MAX_MODIFY_NUM 32 51 #define MLX5_ROOT_TBL_MODIFY_NUM 16 52 53 /* Maximal number of flex items created on the port.*/ 54 #define MLX5_PORT_FLEX_ITEM_NUM 4 55 56 /* Maximal number of field/field parts to map into sample registers .*/ 57 #define MLX5_FLEX_ITEM_MAPPING_NUM 32 58 59 enum mlx5_ipool_index { 60 #if defined(HAVE_IBV_FLOW_DV_SUPPORT) || !defined(HAVE_INFINIBAND_VERBS_H) 61 MLX5_IPOOL_DECAP_ENCAP = 0, /* Pool for encap/decap resource. */ 62 MLX5_IPOOL_PUSH_VLAN, /* Pool for push vlan resource. */ 63 MLX5_IPOOL_TAG, /* Pool for tag resource. */ 64 MLX5_IPOOL_PORT_ID, /* Pool for port id resource. */ 65 MLX5_IPOOL_JUMP, /* Pool for jump resource. */ 66 MLX5_IPOOL_SAMPLE, /* Pool for sample resource. */ 67 MLX5_IPOOL_DEST_ARRAY, /* Pool for destination array resource. */ 68 MLX5_IPOOL_TUNNEL_ID, /* Pool for tunnel offload context */ 69 MLX5_IPOOL_TNL_TBL_ID, /* Pool for tunnel table ID. */ 70 #endif 71 MLX5_IPOOL_MTR, /* Pool for meter resource. */ 72 MLX5_IPOOL_MCP, /* Pool for metadata resource. */ 73 MLX5_IPOOL_HRXQ, /* Pool for hrxq resource. */ 74 MLX5_IPOOL_MLX5_FLOW, /* Pool for mlx5 flow handle. */ 75 MLX5_IPOOL_RTE_FLOW, /* Pool for rte_flow. */ 76 MLX5_IPOOL_RSS_EXPANTION_FLOW_ID, /* Pool for Queue/RSS flow ID. */ 77 MLX5_IPOOL_RSS_SHARED_ACTIONS, /* Pool for RSS shared actions. */ 78 MLX5_IPOOL_MTR_POLICY, /* Pool for meter policy resource. */ 79 MLX5_IPOOL_MAX, 80 }; 81 82 /* 83 * There are three reclaim memory mode supported. 84 * 0(none) means no memory reclaim. 85 * 1(light) means only PMD level reclaim. 86 * 2(aggressive) means both PMD and rdma-core level reclaim. 87 */ 88 enum mlx5_reclaim_mem_mode { 89 MLX5_RCM_NONE, /* Don't reclaim memory. */ 90 MLX5_RCM_LIGHT, /* Reclaim PMD level. */ 91 MLX5_RCM_AGGR, /* Reclaim PMD and rdma-core level. */ 92 }; 93 94 /* The type of flow. */ 95 enum mlx5_flow_type { 96 MLX5_FLOW_TYPE_CTL, /* Control flow. */ 97 MLX5_FLOW_TYPE_GEN, /* General flow. */ 98 MLX5_FLOW_TYPE_MCP, /* MCP flow. */ 99 MLX5_FLOW_TYPE_MAXI, 100 }; 101 102 /* The mode of delay drop for Rx queues. */ 103 enum mlx5_delay_drop_mode { 104 MLX5_DELAY_DROP_NONE = 0, /* All disabled. */ 105 MLX5_DELAY_DROP_STANDARD = RTE_BIT32(0), /* Standard queues enable. */ 106 MLX5_DELAY_DROP_HAIRPIN = RTE_BIT32(1), /* Hairpin queues enable. */ 107 }; 108 109 /* Hlist and list callback context. */ 110 struct mlx5_flow_cb_ctx { 111 struct rte_eth_dev *dev; 112 struct rte_flow_error *error; 113 void *data; 114 void *data2; 115 }; 116 117 /* Device attributes used in mlx5 PMD */ 118 struct mlx5_dev_attr { 119 uint64_t device_cap_flags_ex; 120 int max_qp_wr; 121 int max_sge; 122 int max_cq; 123 int max_qp; 124 int max_cqe; 125 uint32_t max_pd; 126 uint32_t max_mr; 127 uint32_t max_srq; 128 uint32_t max_srq_wr; 129 uint32_t raw_packet_caps; 130 uint32_t max_rwq_indirection_table_size; 131 uint32_t max_tso; 132 uint32_t tso_supported_qpts; 133 uint64_t flags; 134 uint64_t comp_mask; 135 uint32_t sw_parsing_offloads; 136 uint32_t min_single_stride_log_num_of_bytes; 137 uint32_t max_single_stride_log_num_of_bytes; 138 uint32_t min_single_wqe_log_num_of_strides; 139 uint32_t max_single_wqe_log_num_of_strides; 140 uint32_t stride_supported_qpts; 141 uint32_t tunnel_offloads_caps; 142 char fw_ver[64]; 143 }; 144 145 /** Data associated with devices to spawn. */ 146 struct mlx5_dev_spawn_data { 147 uint32_t ifindex; /**< Network interface index. */ 148 uint32_t max_port; /**< Device maximal port index. */ 149 uint32_t phys_port; /**< Device physical port index. */ 150 int pf_bond; /**< bonding device PF index. < 0 - no bonding */ 151 struct mlx5_switch_info info; /**< Switch information. */ 152 const char *phys_dev_name; /**< Name of physical device. */ 153 struct rte_eth_dev *eth_dev; /**< Associated Ethernet device. */ 154 struct rte_pci_device *pci_dev; /**< Backend PCI device. */ 155 struct mlx5_common_device *cdev; /**< Backend common device. */ 156 struct mlx5_bond_info *bond_info; 157 }; 158 159 /** Data associated with socket messages. */ 160 struct mlx5_flow_dump_req { 161 uint32_t port_id; /**< There are plans in DPDK to extend port_id. */ 162 uint64_t flow_id; 163 } __rte_packed; 164 165 struct mlx5_flow_dump_ack { 166 int rc; /**< Return code. */ 167 }; 168 169 LIST_HEAD(mlx5_dev_list, mlx5_dev_ctx_shared); 170 171 /* Shared data between primary and secondary processes. */ 172 struct mlx5_shared_data { 173 rte_spinlock_t lock; 174 /* Global spinlock for primary and secondary processes. */ 175 int init_done; /* Whether primary has done initialization. */ 176 unsigned int secondary_cnt; /* Number of secondary processes init'd. */ 177 }; 178 179 /* Per-process data structure, not visible to other processes. */ 180 struct mlx5_local_data { 181 int init_done; /* Whether a secondary has done initialization. */ 182 }; 183 184 extern struct mlx5_shared_data *mlx5_shared_data; 185 186 /* Dev ops structs */ 187 extern const struct eth_dev_ops mlx5_dev_ops; 188 extern const struct eth_dev_ops mlx5_dev_sec_ops; 189 extern const struct eth_dev_ops mlx5_dev_ops_isolate; 190 191 struct mlx5_counter_ctrl { 192 /* Name of the counter. */ 193 char dpdk_name[RTE_ETH_XSTATS_NAME_SIZE]; 194 /* Name of the counter on the device table. */ 195 char ctr_name[RTE_ETH_XSTATS_NAME_SIZE]; 196 uint32_t dev:1; /**< Nonzero for dev counters. */ 197 }; 198 199 struct mlx5_xstats_ctrl { 200 /* Number of device stats. */ 201 uint16_t stats_n; 202 /* Number of device stats identified by PMD. */ 203 uint16_t mlx5_stats_n; 204 /* Index in the device counters table. */ 205 uint16_t dev_table_idx[MLX5_MAX_XSTATS]; 206 uint64_t base[MLX5_MAX_XSTATS]; 207 uint64_t xstats[MLX5_MAX_XSTATS]; 208 uint64_t hw_stats[MLX5_MAX_XSTATS]; 209 struct mlx5_counter_ctrl info[MLX5_MAX_XSTATS]; 210 }; 211 212 struct mlx5_stats_ctrl { 213 /* Base for imissed counter. */ 214 uint64_t imissed_base; 215 uint64_t imissed; 216 }; 217 218 #define MLX5_LRO_SUPPORTED(dev) \ 219 (((struct mlx5_priv *)((dev)->data->dev_private))->config.lro.supported) 220 221 /* Maximal size of coalesced segment for LRO is set in chunks of 256 Bytes. */ 222 #define MLX5_LRO_SEG_CHUNK_SIZE 256u 223 224 /* Maximal size of aggregated LRO packet. */ 225 #define MLX5_MAX_LRO_SIZE (UINT8_MAX * MLX5_LRO_SEG_CHUNK_SIZE) 226 227 /* Maximal number of segments to split. */ 228 #define MLX5_MAX_RXQ_NSEG (1u << MLX5_MAX_LOG_RQ_SEGS) 229 230 /* LRO configurations structure. */ 231 struct mlx5_lro_config { 232 uint32_t supported:1; /* Whether LRO is supported. */ 233 uint32_t timeout; /* User configuration. */ 234 }; 235 236 /* 237 * Device configuration structure. 238 * 239 * Merged configuration from: 240 * 241 * - Device capabilities, 242 * - User device parameters disabled features. 243 */ 244 struct mlx5_dev_config { 245 unsigned int hw_csum:1; /* Checksum offload is supported. */ 246 unsigned int hw_vlan_strip:1; /* VLAN stripping is supported. */ 247 unsigned int hw_vlan_insert:1; /* VLAN insertion in WQE is supported. */ 248 unsigned int hw_fcs_strip:1; /* FCS stripping is supported. */ 249 unsigned int hw_padding:1; /* End alignment padding is supported. */ 250 unsigned int vf:1; /* This is a VF. */ 251 unsigned int sf:1; /* This is a SF. */ 252 unsigned int tunnel_en:3; 253 /* Whether tunnel stateless offloads are supported. */ 254 unsigned int mpls_en:1; /* MPLS over GRE/UDP is enabled. */ 255 unsigned int cqe_comp:1; /* CQE compression is enabled. */ 256 unsigned int cqe_comp_fmt:3; /* CQE compression format. */ 257 unsigned int tso:1; /* Whether TSO is supported. */ 258 unsigned int rx_vec_en:1; /* Rx vector is enabled. */ 259 unsigned int l3_vxlan_en:1; /* Enable L3 VXLAN flow creation. */ 260 unsigned int vf_nl_en:1; /* Enable Netlink requests in VF mode. */ 261 unsigned int dv_esw_en:1; /* Enable E-Switch DV flow. */ 262 unsigned int dv_flow_en:1; /* Enable DV flow. */ 263 unsigned int dv_xmeta_en:2; /* Enable extensive flow metadata. */ 264 unsigned int lacp_by_user:1; 265 /* Enable user to manage LACP traffic. */ 266 unsigned int swp:3; /* Tx generic tunnel checksum and TSO offload. */ 267 unsigned int dest_tir:1; /* Whether advanced DR API is available. */ 268 unsigned int reclaim_mode:2; /* Memory reclaim mode. */ 269 unsigned int rt_timestamp:1; /* realtime timestamp format. */ 270 unsigned int decap_en:1; /* Whether decap will be used or not. */ 271 unsigned int dv_miss_info:1; /* restore packet after partial hw miss */ 272 unsigned int allow_duplicate_pattern:1; 273 /* Allow/Prevent the duplicate rules pattern. */ 274 unsigned int std_delay_drop:1; /* Enable standard Rxq delay drop. */ 275 unsigned int hp_delay_drop:1; /* Enable hairpin Rxq delay drop. */ 276 struct { 277 unsigned int enabled:1; /* Whether MPRQ is enabled. */ 278 unsigned int stride_num_n; /* Number of strides. */ 279 unsigned int stride_size_n; /* Size of a stride. */ 280 unsigned int min_stride_size_n; /* Min size of a stride. */ 281 unsigned int max_stride_size_n; /* Max size of a stride. */ 282 unsigned int max_memcpy_len; 283 /* Maximum packet size to memcpy Rx packets. */ 284 unsigned int min_rxqs_num; 285 /* Rx queue count threshold to enable MPRQ. */ 286 } mprq; /* Configurations for Multi-Packet RQ. */ 287 int mps; /* Multi-packet send supported mode. */ 288 unsigned int tso_max_payload_sz; /* Maximum TCP payload for TSO. */ 289 unsigned int ind_table_max_size; /* Maximum indirection table size. */ 290 unsigned int max_dump_files_num; /* Maximum dump files per queue. */ 291 unsigned int log_hp_size; /* Single hairpin queue data size in total. */ 292 int txqs_inline; /* Queue number threshold for inlining. */ 293 int txq_inline_min; /* Minimal amount of data bytes to inline. */ 294 int txq_inline_max; /* Max packet size for inlining with SEND. */ 295 int txq_inline_mpw; /* Max packet size for inlining with eMPW. */ 296 int tx_pp; /* Timestamp scheduling granularity in nanoseconds. */ 297 int tx_skew; /* Tx scheduling skew between WQE and data on wire. */ 298 struct mlx5_hca_attr hca_attr; /* HCA attributes. */ 299 struct mlx5_lro_config lro; /* LRO configuration. */ 300 }; 301 302 303 /* Structure for VF VLAN workaround. */ 304 struct mlx5_vf_vlan { 305 uint32_t tag:12; 306 uint32_t created:1; 307 }; 308 309 /* Flow drop context necessary due to Verbs API. */ 310 struct mlx5_drop { 311 struct mlx5_hrxq *hrxq; /* Hash Rx queue queue. */ 312 struct mlx5_rxq_priv *rxq; /* Rx queue. */ 313 }; 314 315 /* Loopback dummy queue resources required due to Verbs API. */ 316 struct mlx5_lb_ctx { 317 struct ibv_qp *qp; /* QP object. */ 318 void *ibv_cq; /* Completion queue. */ 319 uint16_t refcnt; /* Reference count for representors. */ 320 }; 321 322 #define MLX5_COUNTERS_PER_POOL 512 323 #define MLX5_MAX_PENDING_QUERIES 4 324 #define MLX5_CNT_CONTAINER_RESIZE 64 325 #define MLX5_CNT_SHARED_OFFSET 0x80000000 326 #define IS_BATCH_CNT(cnt) (((cnt) & (MLX5_CNT_SHARED_OFFSET - 1)) >= \ 327 MLX5_CNT_BATCH_OFFSET) 328 #define MLX5_CNT_SIZE (sizeof(struct mlx5_flow_counter)) 329 #define MLX5_AGE_SIZE (sizeof(struct mlx5_age_param)) 330 331 #define MLX5_CNT_LEN(pool) \ 332 (MLX5_CNT_SIZE + \ 333 ((pool)->is_aged ? MLX5_AGE_SIZE : 0)) 334 #define MLX5_POOL_GET_CNT(pool, index) \ 335 ((struct mlx5_flow_counter *) \ 336 ((uint8_t *)((pool) + 1) + (index) * (MLX5_CNT_LEN(pool)))) 337 #define MLX5_CNT_ARRAY_IDX(pool, cnt) \ 338 ((int)(((uint8_t *)(cnt) - (uint8_t *)((pool) + 1)) / \ 339 MLX5_CNT_LEN(pool))) 340 /* 341 * The pool index and offset of counter in the pool array makes up the 342 * counter index. In case the counter is from pool 0 and offset 0, it 343 * should plus 1 to avoid index 0, since 0 means invalid counter index 344 * currently. 345 */ 346 #define MLX5_MAKE_CNT_IDX(pi, offset) \ 347 ((pi) * MLX5_COUNTERS_PER_POOL + (offset) + 1) 348 #define MLX5_CNT_TO_AGE(cnt) \ 349 ((struct mlx5_age_param *)((cnt) + 1)) 350 /* 351 * The maximum single counter is 0x800000 as MLX5_CNT_BATCH_OFFSET 352 * defines. The pool size is 512, pool index should never reach 353 * INT16_MAX. 354 */ 355 #define POOL_IDX_INVALID UINT16_MAX 356 357 /* Age status. */ 358 enum { 359 AGE_FREE, /* Initialized state. */ 360 AGE_CANDIDATE, /* Counter assigned to flows. */ 361 AGE_TMOUT, /* Timeout, wait for rte_flow_get_aged_flows and destroy. */ 362 }; 363 364 enum mlx5_counter_type { 365 MLX5_COUNTER_TYPE_ORIGIN, 366 MLX5_COUNTER_TYPE_AGE, 367 MLX5_COUNTER_TYPE_MAX, 368 }; 369 370 /* Counter age parameter. */ 371 struct mlx5_age_param { 372 uint16_t state; /**< Age state (atomically accessed). */ 373 uint16_t port_id; /**< Port id of the counter. */ 374 uint32_t timeout:24; /**< Aging timeout in seconds. */ 375 uint32_t sec_since_last_hit; 376 /**< Time in seconds since last hit (atomically accessed). */ 377 void *context; /**< Flow counter age context. */ 378 }; 379 380 struct flow_counter_stats { 381 uint64_t hits; 382 uint64_t bytes; 383 }; 384 385 /* Shared counters information for counters. */ 386 struct mlx5_flow_counter_shared { 387 union { 388 uint32_t refcnt; /* Only for shared action management. */ 389 uint32_t id; /* User counter ID for legacy sharing. */ 390 }; 391 }; 392 393 struct mlx5_flow_counter_pool; 394 /* Generic counters information. */ 395 struct mlx5_flow_counter { 396 union { 397 /* 398 * User-defined counter shared info is only used during 399 * counter active time. And aging counter sharing is not 400 * supported, so active shared counter will not be chained 401 * to the aging list. For shared counter, only when it is 402 * released, the TAILQ entry memory will be used, at that 403 * time, shared memory is not used anymore. 404 * 405 * Similarly to none-batch counter dcs, since it doesn't 406 * support aging, while counter is allocated, the entry 407 * memory is not used anymore. In this case, as bytes 408 * memory is used only when counter is allocated, and 409 * entry memory is used only when counter is free. The 410 * dcs pointer can be saved to these two different place 411 * at different stage. It will eliminate the individual 412 * counter extend struct. 413 */ 414 TAILQ_ENTRY(mlx5_flow_counter) next; 415 /**< Pointer to the next flow counter structure. */ 416 struct { 417 struct mlx5_flow_counter_shared shared_info; 418 /**< Shared counter information. */ 419 void *dcs_when_active; 420 /* 421 * For non-batch mode, the dcs will be saved 422 * here when the counter is free. 423 */ 424 }; 425 }; 426 union { 427 uint64_t hits; /**< Reset value of hits packets. */ 428 struct mlx5_flow_counter_pool *pool; /**< Counter pool. */ 429 }; 430 union { 431 uint64_t bytes; /**< Reset value of bytes. */ 432 void *dcs_when_free; 433 /* 434 * For non-batch mode, the dcs will be saved here 435 * when the counter is free. 436 */ 437 }; 438 void *action; /**< Pointer to the dv action. */ 439 }; 440 441 TAILQ_HEAD(mlx5_counters, mlx5_flow_counter); 442 443 /* Generic counter pool structure - query is in pool resolution. */ 444 struct mlx5_flow_counter_pool { 445 TAILQ_ENTRY(mlx5_flow_counter_pool) next; 446 struct mlx5_counters counters[2]; /* Free counter list. */ 447 struct mlx5_devx_obj *min_dcs; 448 /* The devx object of the minimum counter ID. */ 449 uint64_t time_of_last_age_check; 450 /* System time (from rte_rdtsc()) read in the last aging check. */ 451 uint32_t index:30; /* Pool index in container. */ 452 uint32_t is_aged:1; /* Pool with aging counter. */ 453 volatile uint32_t query_gen:1; /* Query round. */ 454 rte_spinlock_t sl; /* The pool lock. */ 455 rte_spinlock_t csl; /* The pool counter free list lock. */ 456 struct mlx5_counter_stats_raw *raw; 457 struct mlx5_counter_stats_raw *raw_hw; 458 /* The raw on HW working. */ 459 }; 460 461 /* Memory management structure for group of counter statistics raws. */ 462 struct mlx5_counter_stats_mem_mng { 463 LIST_ENTRY(mlx5_counter_stats_mem_mng) next; 464 struct mlx5_counter_stats_raw *raws; 465 struct mlx5_pmd_wrapped_mr wm; 466 }; 467 468 /* Raw memory structure for the counter statistics values of a pool. */ 469 struct mlx5_counter_stats_raw { 470 LIST_ENTRY(mlx5_counter_stats_raw) next; 471 struct mlx5_counter_stats_mem_mng *mem_mng; 472 volatile struct flow_counter_stats *data; 473 }; 474 475 TAILQ_HEAD(mlx5_counter_pools, mlx5_flow_counter_pool); 476 477 /* Counter global management structure. */ 478 struct mlx5_flow_counter_mng { 479 volatile uint16_t n_valid; /* Number of valid pools. */ 480 uint16_t n; /* Number of pools. */ 481 uint16_t last_pool_idx; /* Last used pool index */ 482 int min_id; /* The minimum counter ID in the pools. */ 483 int max_id; /* The maximum counter ID in the pools. */ 484 rte_spinlock_t pool_update_sl; /* The pool update lock. */ 485 rte_spinlock_t csl[MLX5_COUNTER_TYPE_MAX]; 486 /* The counter free list lock. */ 487 struct mlx5_counters counters[MLX5_COUNTER_TYPE_MAX]; 488 /* Free counter list. */ 489 struct mlx5_flow_counter_pool **pools; /* Counter pool array. */ 490 struct mlx5_counter_stats_mem_mng *mem_mng; 491 /* Hold the memory management for the next allocated pools raws. */ 492 struct mlx5_counters flow_counters; /* Legacy flow counter list. */ 493 uint8_t pending_queries; 494 uint16_t pool_index; 495 uint8_t query_thread_on; 496 bool counter_fallback; /* Use counter fallback management. */ 497 LIST_HEAD(mem_mngs, mlx5_counter_stats_mem_mng) mem_mngs; 498 LIST_HEAD(stat_raws, mlx5_counter_stats_raw) free_stat_raws; 499 }; 500 501 /* ASO structures. */ 502 #define MLX5_ASO_QUEUE_LOG_DESC 10 503 504 struct mlx5_aso_cq { 505 uint16_t log_desc_n; 506 uint32_t cq_ci:24; 507 struct mlx5_devx_cq cq_obj; 508 uint64_t errors; 509 }; 510 511 struct mlx5_aso_sq_elem { 512 union { 513 struct { 514 struct mlx5_aso_age_pool *pool; 515 uint16_t burst_size; 516 }; 517 struct mlx5_aso_mtr *mtr; 518 struct { 519 struct mlx5_aso_ct_action *ct; 520 char *query_data; 521 }; 522 }; 523 }; 524 525 struct mlx5_aso_sq { 526 uint16_t log_desc_n; 527 rte_spinlock_t sqsl; 528 struct mlx5_aso_cq cq; 529 struct mlx5_devx_sq sq_obj; 530 struct mlx5_pmd_mr mr; 531 uint16_t pi; 532 uint32_t head; 533 uint32_t tail; 534 uint32_t sqn; 535 struct mlx5_aso_sq_elem elts[1 << MLX5_ASO_QUEUE_LOG_DESC]; 536 uint16_t next; /* Pool index of the next pool to query. */ 537 }; 538 539 struct mlx5_aso_age_action { 540 LIST_ENTRY(mlx5_aso_age_action) next; 541 void *dr_action; 542 uint32_t refcnt; 543 /* Following fields relevant only when action is active. */ 544 uint16_t offset; /* Offset of ASO Flow Hit flag in DevX object. */ 545 struct mlx5_age_param age_params; 546 }; 547 548 #define MLX5_ASO_AGE_ACTIONS_PER_POOL 512 549 550 struct mlx5_aso_age_pool { 551 struct mlx5_devx_obj *flow_hit_aso_obj; 552 uint16_t index; /* Pool index in pools array. */ 553 uint64_t time_of_last_age_check; /* In seconds. */ 554 struct mlx5_aso_age_action actions[MLX5_ASO_AGE_ACTIONS_PER_POOL]; 555 }; 556 557 LIST_HEAD(aso_age_list, mlx5_aso_age_action); 558 559 struct mlx5_aso_age_mng { 560 struct mlx5_aso_age_pool **pools; 561 uint16_t n; /* Total number of pools. */ 562 uint16_t next; /* Number of pools in use, index of next free pool. */ 563 rte_rwlock_t resize_rwl; /* Lock for resize objects. */ 564 rte_spinlock_t free_sl; /* Lock for free list access. */ 565 struct aso_age_list free; /* Free age actions list - ready to use. */ 566 struct mlx5_aso_sq aso_sq; /* ASO queue objects. */ 567 }; 568 569 /* Management structure for geneve tlv option */ 570 struct mlx5_geneve_tlv_option_resource { 571 struct mlx5_devx_obj *obj; /* Pointer to the geneve tlv opt object. */ 572 rte_be16_t option_class; /* geneve tlv opt class.*/ 573 uint8_t option_type; /* geneve tlv opt type.*/ 574 uint8_t length; /* geneve tlv opt length. */ 575 uint32_t refcnt; /* geneve tlv object reference counter */ 576 }; 577 578 579 #define MLX5_AGE_EVENT_NEW 1 580 #define MLX5_AGE_TRIGGER 2 581 #define MLX5_AGE_SET(age_info, BIT) \ 582 ((age_info)->flags |= (1 << (BIT))) 583 #define MLX5_AGE_UNSET(age_info, BIT) \ 584 ((age_info)->flags &= ~(1 << (BIT))) 585 #define MLX5_AGE_GET(age_info, BIT) \ 586 ((age_info)->flags & (1 << (BIT))) 587 #define GET_PORT_AGE_INFO(priv) \ 588 (&((priv)->sh->port[(priv)->dev_port - 1].age_info)) 589 /* Current time in seconds. */ 590 #define MLX5_CURR_TIME_SEC (rte_rdtsc() / rte_get_tsc_hz()) 591 592 /* Aging information for per port. */ 593 struct mlx5_age_info { 594 uint8_t flags; /* Indicate if is new event or need to be triggered. */ 595 struct mlx5_counters aged_counters; /* Aged counter list. */ 596 struct aso_age_list aged_aso; /* Aged ASO actions list. */ 597 rte_spinlock_t aged_sl; /* Aged flow list lock. */ 598 }; 599 600 /* Per port data of shared IB device. */ 601 struct mlx5_dev_shared_port { 602 uint32_t ih_port_id; 603 uint32_t devx_ih_port_id; 604 /* 605 * Interrupt handler port_id. Used by shared interrupt 606 * handler to find the corresponding rte_eth device 607 * by IB port index. If value is equal or greater 608 * RTE_MAX_ETHPORTS it means there is no subhandler 609 * installed for specified IB port index. 610 */ 611 struct mlx5_age_info age_info; 612 /* Aging information for per port. */ 613 }; 614 615 /* 616 * Max number of actions per DV flow. 617 * See CREATE_FLOW_MAX_FLOW_ACTIONS_SUPPORTED 618 * in rdma-core file providers/mlx5/verbs.c. 619 */ 620 #define MLX5_DV_MAX_NUMBER_OF_ACTIONS 8 621 622 /* ASO flow meter structures */ 623 /* Modify this value if enum rte_mtr_color changes. */ 624 #define RTE_MTR_DROPPED RTE_COLORS 625 /* Yellow is now supported. */ 626 #define MLX5_MTR_RTE_COLORS (RTE_COLOR_YELLOW + 1) 627 /* table_id 22 bits in mlx5_flow_tbl_key so limit policy number. */ 628 #define MLX5_MAX_SUB_POLICY_TBL_NUM 0x3FFFFF 629 #define MLX5_INVALID_POLICY_ID UINT32_MAX 630 /* Suffix table_id on MLX5_FLOW_TABLE_LEVEL_METER. */ 631 #define MLX5_MTR_TABLE_ID_SUFFIX 1 632 /* Drop table_id on MLX5_FLOW_TABLE_LEVEL_METER. */ 633 #define MLX5_MTR_TABLE_ID_DROP 2 634 /* Priority of the meter policy matcher. */ 635 #define MLX5_MTR_POLICY_MATCHER_PRIO 0 636 /* Green & yellow color valid for now. */ 637 #define MLX5_MTR_POLICY_MODE_ALL 0 638 /* Default policy. */ 639 #define MLX5_MTR_POLICY_MODE_DEF 1 640 /* Only green color valid. */ 641 #define MLX5_MTR_POLICY_MODE_OG 2 642 /* Only yellow color valid. */ 643 #define MLX5_MTR_POLICY_MODE_OY 3 644 645 enum mlx5_meter_domain { 646 MLX5_MTR_DOMAIN_INGRESS, 647 MLX5_MTR_DOMAIN_EGRESS, 648 MLX5_MTR_DOMAIN_TRANSFER, 649 MLX5_MTR_DOMAIN_MAX, 650 }; 651 #define MLX5_MTR_DOMAIN_INGRESS_BIT (1 << MLX5_MTR_DOMAIN_INGRESS) 652 #define MLX5_MTR_DOMAIN_EGRESS_BIT (1 << MLX5_MTR_DOMAIN_EGRESS) 653 #define MLX5_MTR_DOMAIN_TRANSFER_BIT (1 << MLX5_MTR_DOMAIN_TRANSFER) 654 #define MLX5_MTR_ALL_DOMAIN_BIT (MLX5_MTR_DOMAIN_INGRESS_BIT | \ 655 MLX5_MTR_DOMAIN_EGRESS_BIT | \ 656 MLX5_MTR_DOMAIN_TRANSFER_BIT) 657 658 /* The color tag rule structure. */ 659 struct mlx5_sub_policy_color_rule { 660 void *rule; 661 /* The color rule. */ 662 struct mlx5_flow_dv_matcher *matcher; 663 /* The color matcher. */ 664 TAILQ_ENTRY(mlx5_sub_policy_color_rule) next_port; 665 /**< Pointer to the next color rule structure. */ 666 int32_t src_port; 667 /* On which src port this rule applied. */ 668 }; 669 670 TAILQ_HEAD(mlx5_sub_policy_color_rules, mlx5_sub_policy_color_rule); 671 672 /* 673 * Meter sub-policy structure. 674 * Each RSS TIR in meter policy need its own sub-policy resource. 675 */ 676 struct mlx5_flow_meter_sub_policy { 677 uint32_t main_policy_id:1; 678 /* Main policy id is same as this sub_policy id. */ 679 uint32_t idx:31; 680 /* Index to sub_policy ipool entity. */ 681 void *main_policy; 682 /* Point to struct mlx5_flow_meter_policy. */ 683 struct mlx5_flow_tbl_resource *tbl_rsc; 684 /* The sub-policy table resource. */ 685 uint32_t rix_hrxq[MLX5_MTR_RTE_COLORS]; 686 /* Index to TIR resource. */ 687 struct mlx5_flow_tbl_resource *jump_tbl[MLX5_MTR_RTE_COLORS]; 688 /* Meter jump/drop table. */ 689 struct mlx5_sub_policy_color_rules color_rules[RTE_COLORS]; 690 /* List for the color rules. */ 691 }; 692 693 struct mlx5_meter_policy_acts { 694 uint8_t actions_n; 695 /* Number of actions. */ 696 void *dv_actions[MLX5_DV_MAX_NUMBER_OF_ACTIONS]; 697 /* Action list. */ 698 }; 699 700 struct mlx5_meter_policy_action_container { 701 uint32_t rix_mark; 702 /* Index to the mark action. */ 703 struct mlx5_flow_dv_modify_hdr_resource *modify_hdr; 704 /* Pointer to modify header resource in cache. */ 705 uint8_t fate_action; 706 /* Fate action type. */ 707 union { 708 struct rte_flow_action *rss; 709 /* Rss action configuration. */ 710 uint32_t rix_port_id_action; 711 /* Index to port ID action resource. */ 712 void *dr_jump_action[MLX5_MTR_DOMAIN_MAX]; 713 /* Jump/drop action per color. */ 714 uint16_t queue; 715 /* Queue action configuration. */ 716 struct { 717 uint32_t next_mtr_id; 718 /* The next meter id. */ 719 void *next_sub_policy; 720 /* Next meter's sub-policy. */ 721 }; 722 }; 723 }; 724 725 /* Flow meter policy parameter structure. */ 726 struct mlx5_flow_meter_policy { 727 struct rte_eth_dev *dev; 728 /* The port dev on which policy is created. */ 729 uint32_t is_rss:1; 730 /* Is RSS policy table. */ 731 uint32_t ingress:1; 732 /* Rule applies to ingress domain. */ 733 uint32_t egress:1; 734 /* Rule applies to egress domain. */ 735 uint32_t transfer:1; 736 /* Rule applies to transfer domain. */ 737 uint32_t is_queue:1; 738 /* Is queue action in policy table. */ 739 uint32_t is_hierarchy:1; 740 /* Is meter action in policy table. */ 741 uint32_t skip_y:1; 742 /* If yellow color policy is skipped. */ 743 uint32_t skip_g:1; 744 /* If green color policy is skipped. */ 745 rte_spinlock_t sl; 746 uint32_t ref_cnt; 747 /* Use count. */ 748 struct mlx5_meter_policy_action_container act_cnt[MLX5_MTR_RTE_COLORS]; 749 /* Policy actions container. */ 750 void *dr_drop_action[MLX5_MTR_DOMAIN_MAX]; 751 /* drop action for red color. */ 752 uint16_t sub_policy_num; 753 /* Count sub policy tables, 3 bits per domain. */ 754 struct mlx5_flow_meter_sub_policy **sub_policys[MLX5_MTR_DOMAIN_MAX]; 755 /* Sub policy table array must be the end of struct. */ 756 }; 757 758 /* The maximum sub policy is relate to struct mlx5_rss_hash_fields[]. */ 759 #define MLX5_MTR_RSS_MAX_SUB_POLICY 7 760 #define MLX5_MTR_SUB_POLICY_NUM_SHIFT 3 761 #define MLX5_MTR_SUB_POLICY_NUM_MASK 0x7 762 #define MLX5_MTRS_DEFAULT_RULE_PRIORITY 0xFFFF 763 #define MLX5_MTR_CHAIN_MAX_NUM 8 764 765 /* Flow meter default policy parameter structure. 766 * Policy index 0 is reserved by default policy table. 767 * Action per color as below: 768 * green - do nothing, yellow - do nothing, red - drop 769 */ 770 struct mlx5_flow_meter_def_policy { 771 struct mlx5_flow_meter_sub_policy sub_policy; 772 /* Policy rules jump to other tables. */ 773 void *dr_jump_action[RTE_COLORS]; 774 /* Jump action per color. */ 775 }; 776 777 /* Meter parameter structure. */ 778 struct mlx5_flow_meter_info { 779 uint32_t meter_id; 780 /**< Meter id. */ 781 uint32_t policy_id; 782 /* Policy id, the first sub_policy idx. */ 783 struct mlx5_flow_meter_profile *profile; 784 /**< Meter profile parameters. */ 785 rte_spinlock_t sl; /**< Meter action spinlock. */ 786 /** Set of stats counters to be enabled. 787 * @see enum rte_mtr_stats_type 788 */ 789 uint32_t bytes_dropped:1; 790 /** Set bytes dropped stats to be enabled. */ 791 uint32_t pkts_dropped:1; 792 /** Set packets dropped stats to be enabled. */ 793 uint32_t active_state:1; 794 /**< Meter hw active state. */ 795 uint32_t shared:1; 796 /**< Meter shared or not. */ 797 uint32_t is_enable:1; 798 /**< Meter disable/enable state. */ 799 uint32_t ingress:1; 800 /**< Rule applies to egress traffic. */ 801 uint32_t egress:1; 802 /** 803 * Instead of simply matching the properties of traffic as it would 804 * appear on a given DPDK port ID, enabling this attribute transfers 805 * a flow rule to the lowest possible level of any device endpoints 806 * found in the pattern. 807 * 808 * When supported, this effectively enables an application to 809 * re-route traffic not necessarily intended for it (e.g. coming 810 * from or addressed to different physical ports, VFs or 811 * applications) at the device level. 812 * 813 * It complements the behavior of some pattern items such as 814 * RTE_FLOW_ITEM_TYPE_PHY_PORT and is meaningless without them. 815 * 816 * When transferring flow rules, ingress and egress attributes keep 817 * their original meaning, as if processing traffic emitted or 818 * received by the application. 819 */ 820 uint32_t transfer:1; 821 uint32_t def_policy:1; 822 /* Meter points to default policy. */ 823 void *drop_rule[MLX5_MTR_DOMAIN_MAX]; 824 /* Meter drop rule in drop table. */ 825 uint32_t drop_cnt; 826 /**< Color counter for drop. */ 827 uint32_t ref_cnt; 828 /**< Use count. */ 829 struct mlx5_indexed_pool *flow_ipool; 830 /**< Index pool for flow id. */ 831 void *meter_action; 832 /**< Flow meter action. */ 833 }; 834 835 /* PPS(packets per second) map to BPS(Bytes per second). 836 * HW treat packet as 128bytes in PPS mode 837 */ 838 #define MLX5_MTRS_PPS_MAP_BPS_SHIFT 7 839 840 /* RFC2697 parameter structure. */ 841 struct mlx5_flow_meter_srtcm_rfc2697_prm { 842 rte_be32_t cbs_cir; 843 /* 844 * bit 24-28: cbs_exponent, bit 16-23 cbs_mantissa, 845 * bit 8-12: cir_exponent, bit 0-7 cir_mantissa. 846 */ 847 rte_be32_t ebs_eir; 848 /* 849 * bit 24-28: ebs_exponent, bit 16-23 ebs_mantissa, 850 * bit 8-12: eir_exponent, bit 0-7 eir_mantissa. 851 */ 852 }; 853 854 /* Flow meter profile structure. */ 855 struct mlx5_flow_meter_profile { 856 TAILQ_ENTRY(mlx5_flow_meter_profile) next; 857 /**< Pointer to the next flow meter structure. */ 858 uint32_t id; /**< Profile id. */ 859 struct rte_mtr_meter_profile profile; /**< Profile detail. */ 860 union { 861 struct mlx5_flow_meter_srtcm_rfc2697_prm srtcm_prm; 862 /**< srtcm_rfc2697 struct. */ 863 }; 864 uint32_t ref_cnt; /**< Use count. */ 865 uint32_t g_support:1; /**< If G color will be generated. */ 866 uint32_t y_support:1; /**< If Y color will be generated. */ 867 }; 868 869 /* 2 meters in each ASO cache line */ 870 #define MLX5_MTRS_CONTAINER_RESIZE 64 871 /* 872 * The pool index and offset of meter in the pool array makes up the 873 * meter index. In case the meter is from pool 0 and offset 0, it 874 * should plus 1 to avoid index 0, since 0 means invalid meter index 875 * currently. 876 */ 877 #define MLX5_MAKE_MTR_IDX(pi, offset) \ 878 ((pi) * MLX5_ASO_MTRS_PER_POOL + (offset) + 1) 879 880 /*aso flow meter state*/ 881 enum mlx5_aso_mtr_state { 882 ASO_METER_FREE, /* In free list. */ 883 ASO_METER_WAIT, /* ACCESS_ASO WQE in progress. */ 884 ASO_METER_READY, /* CQE received. */ 885 }; 886 887 /* Generic aso_flow_meter information. */ 888 struct mlx5_aso_mtr { 889 LIST_ENTRY(mlx5_aso_mtr) next; 890 struct mlx5_flow_meter_info fm; 891 /**< Pointer to the next aso flow meter structure. */ 892 uint8_t state; /**< ASO flow meter state. */ 893 uint8_t offset; 894 }; 895 896 /* Generic aso_flow_meter pool structure. */ 897 struct mlx5_aso_mtr_pool { 898 struct mlx5_aso_mtr mtrs[MLX5_ASO_MTRS_PER_POOL]; 899 /*Must be the first in pool*/ 900 struct mlx5_devx_obj *devx_obj; 901 /* The devx object of the minimum aso flow meter ID. */ 902 uint32_t index; /* Pool index in management structure. */ 903 }; 904 905 LIST_HEAD(aso_meter_list, mlx5_aso_mtr); 906 /* Pools management structure for ASO flow meter pools. */ 907 struct mlx5_aso_mtr_pools_mng { 908 volatile uint16_t n_valid; /* Number of valid pools. */ 909 uint16_t n; /* Number of pools. */ 910 rte_spinlock_t mtrsl; /* The ASO flow meter free list lock. */ 911 rte_rwlock_t resize_mtrwl; /* Lock for resize objects. */ 912 struct aso_meter_list meters; /* Free ASO flow meter list. */ 913 struct mlx5_aso_sq sq; /*SQ using by ASO flow meter. */ 914 struct mlx5_aso_mtr_pool **pools; /* ASO flow meter pool array. */ 915 }; 916 917 /* Meter management structure for global flow meter resource. */ 918 struct mlx5_flow_mtr_mng { 919 struct mlx5_aso_mtr_pools_mng pools_mng; 920 /* Pools management structure for ASO flow meter pools. */ 921 struct mlx5_flow_meter_def_policy *def_policy[MLX5_MTR_DOMAIN_MAX]; 922 /* Default policy table. */ 923 uint32_t def_policy_id; 924 /* Default policy id. */ 925 uint32_t def_policy_ref_cnt; 926 /** def_policy meter use count. */ 927 struct mlx5_flow_tbl_resource *drop_tbl[MLX5_MTR_DOMAIN_MAX]; 928 /* Meter drop table. */ 929 struct mlx5_flow_dv_matcher * 930 drop_matcher[MLX5_MTR_DOMAIN_MAX][MLX5_REG_BITS]; 931 /* Matcher meter in drop table. */ 932 struct mlx5_flow_dv_matcher *def_matcher[MLX5_MTR_DOMAIN_MAX]; 933 /* Default matcher in drop table. */ 934 void *def_rule[MLX5_MTR_DOMAIN_MAX]; 935 /* Default rule in drop table. */ 936 uint8_t max_mtr_bits; 937 /* Indicate how many bits are used by meter id at the most. */ 938 uint8_t max_mtr_flow_bits; 939 /* Indicate how many bits are used by meter flow id at the most. */ 940 }; 941 942 /* Table key of the hash organization. */ 943 union mlx5_flow_tbl_key { 944 struct { 945 /* Table ID should be at the lowest address. */ 946 uint32_t level; /**< Level of the table. */ 947 uint32_t id:22; /**< ID of the table. */ 948 uint32_t dummy:1; /**< Dummy table for DV API. */ 949 uint32_t is_fdb:1; /**< 1 - FDB, 0 - NIC TX/RX. */ 950 uint32_t is_egress:1; /**< 1 - egress, 0 - ingress. */ 951 uint32_t reserved:7; /**< must be zero for comparison. */ 952 }; 953 uint64_t v64; /**< full 64bits value of key */ 954 }; 955 956 /* Table structure. */ 957 struct mlx5_flow_tbl_resource { 958 void *obj; /**< Pointer to DR table object. */ 959 uint32_t refcnt; /**< Reference counter. */ 960 }; 961 962 #define MLX5_MAX_TABLES UINT16_MAX 963 #define MLX5_HAIRPIN_TX_TABLE (UINT16_MAX - 1) 964 /* Reserve the last two tables for metadata register copy. */ 965 #define MLX5_FLOW_MREG_ACT_TABLE_GROUP (MLX5_MAX_TABLES - 1) 966 #define MLX5_FLOW_MREG_CP_TABLE_GROUP (MLX5_MAX_TABLES - 2) 967 /* Tables for metering splits should be added here. */ 968 #define MLX5_FLOW_TABLE_LEVEL_METER (MLX5_MAX_TABLES - 3) 969 #define MLX5_FLOW_TABLE_LEVEL_POLICY (MLX5_MAX_TABLES - 4) 970 #define MLX5_MAX_TABLES_EXTERNAL MLX5_FLOW_TABLE_LEVEL_POLICY 971 #define MLX5_MAX_TABLES_FDB UINT16_MAX 972 #define MLX5_FLOW_TABLE_FACTOR 10 973 974 /* ID generation structure. */ 975 struct mlx5_flow_id_pool { 976 uint32_t *free_arr; /**< Pointer to the a array of free values. */ 977 uint32_t base_index; 978 /**< The next index that can be used without any free elements. */ 979 uint32_t *curr; /**< Pointer to the index to pop. */ 980 uint32_t *last; /**< Pointer to the last element in the empty arrray. */ 981 uint32_t max_id; /**< Maximum id can be allocated from the pool. */ 982 }; 983 984 /* Tx pacing queue structure - for Clock and Rearm queues. */ 985 struct mlx5_txpp_wq { 986 /* Completion Queue related data.*/ 987 struct mlx5_devx_cq cq_obj; 988 uint32_t cq_ci:24; 989 uint32_t arm_sn:2; 990 /* Send Queue related data.*/ 991 struct mlx5_devx_sq sq_obj; 992 uint16_t sq_size; /* Number of WQEs in the queue. */ 993 uint16_t sq_ci; /* Next WQE to execute. */ 994 }; 995 996 /* Tx packet pacing internal timestamp. */ 997 struct mlx5_txpp_ts { 998 uint64_t ci_ts; 999 uint64_t ts; 1000 }; 1001 1002 /* Tx packet pacing structure. */ 1003 struct mlx5_dev_txpp { 1004 pthread_mutex_t mutex; /* Pacing create/destroy mutex. */ 1005 uint32_t refcnt; /* Pacing reference counter. */ 1006 uint32_t freq; /* Timestamp frequency, Hz. */ 1007 uint32_t tick; /* Completion tick duration in nanoseconds. */ 1008 uint32_t test; /* Packet pacing test mode. */ 1009 int32_t skew; /* Scheduling skew. */ 1010 struct rte_intr_handle *intr_handle; /* Periodic interrupt. */ 1011 void *echan; /* Event Channel. */ 1012 struct mlx5_txpp_wq clock_queue; /* Clock Queue. */ 1013 struct mlx5_txpp_wq rearm_queue; /* Clock Queue. */ 1014 void *pp; /* Packet pacing context. */ 1015 uint16_t pp_id; /* Packet pacing context index. */ 1016 uint16_t ts_n; /* Number of captured timestamps. */ 1017 uint16_t ts_p; /* Pointer to statisticks timestamp. */ 1018 struct mlx5_txpp_ts *tsa; /* Timestamps sliding window stats. */ 1019 struct mlx5_txpp_ts ts; /* Cached completion id/timestamp. */ 1020 uint32_t sync_lost:1; /* ci/timestamp synchronization lost. */ 1021 /* Statistics counters. */ 1022 uint64_t err_miss_int; /* Missed service interrupt. */ 1023 uint64_t err_rearm_queue; /* Rearm Queue errors. */ 1024 uint64_t err_clock_queue; /* Clock Queue errors. */ 1025 uint64_t err_ts_past; /* Timestamp in the past. */ 1026 uint64_t err_ts_future; /* Timestamp in the distant future. */ 1027 }; 1028 1029 /* Sample ID information of eCPRI flex parser structure. */ 1030 struct mlx5_ecpri_parser_profile { 1031 uint32_t num; /* Actual number of samples. */ 1032 uint32_t ids[8]; /* Sample IDs for this profile. */ 1033 uint8_t offset[8]; /* Bytes offset of each parser. */ 1034 void *obj; /* Flex parser node object. */ 1035 }; 1036 1037 /* Max member ports per bonding device. */ 1038 #define MLX5_BOND_MAX_PORTS 2 1039 1040 /* Bonding device information. */ 1041 struct mlx5_bond_info { 1042 int n_port; /* Number of bond member ports. */ 1043 uint32_t ifindex; 1044 char ifname[MLX5_NAMESIZE + 1]; 1045 struct { 1046 char ifname[MLX5_NAMESIZE + 1]; 1047 uint32_t ifindex; 1048 struct rte_pci_addr pci_addr; 1049 } ports[MLX5_BOND_MAX_PORTS]; 1050 }; 1051 1052 /* Number of connection tracking objects per pool: must be a power of 2. */ 1053 #define MLX5_ASO_CT_ACTIONS_PER_POOL 64 1054 1055 /* Generate incremental and unique CT index from pool and offset. */ 1056 #define MLX5_MAKE_CT_IDX(pool, offset) \ 1057 ((pool) * MLX5_ASO_CT_ACTIONS_PER_POOL + (offset) + 1) 1058 1059 /* ASO Conntrack state. */ 1060 enum mlx5_aso_ct_state { 1061 ASO_CONNTRACK_FREE, /* Inactive, in the free list. */ 1062 ASO_CONNTRACK_WAIT, /* WQE sent in the SQ. */ 1063 ASO_CONNTRACK_READY, /* CQE received w/o error. */ 1064 ASO_CONNTRACK_QUERY, /* WQE for query sent. */ 1065 ASO_CONNTRACK_MAX, /* Guard. */ 1066 }; 1067 1068 /* Generic ASO connection tracking structure. */ 1069 struct mlx5_aso_ct_action { 1070 LIST_ENTRY(mlx5_aso_ct_action) next; /* Pointer to the next ASO CT. */ 1071 void *dr_action_orig; /* General action object for original dir. */ 1072 void *dr_action_rply; /* General action object for reply dir. */ 1073 uint32_t refcnt; /* Action used count in device flows. */ 1074 uint16_t offset; /* Offset of ASO CT in DevX objects bulk. */ 1075 uint16_t peer; /* The only peer port index could also use this CT. */ 1076 enum mlx5_aso_ct_state state; /* ASO CT state. */ 1077 bool is_original; /* The direction of the DR action to be used. */ 1078 }; 1079 1080 /* CT action object state update. */ 1081 #define MLX5_ASO_CT_UPDATE_STATE(c, s) \ 1082 __atomic_store_n(&((c)->state), (s), __ATOMIC_RELAXED) 1083 1084 /* ASO connection tracking software pool definition. */ 1085 struct mlx5_aso_ct_pool { 1086 uint16_t index; /* Pool index in pools array. */ 1087 struct mlx5_devx_obj *devx_obj; 1088 /* The first devx object in the bulk, used for freeing (not yet). */ 1089 struct mlx5_aso_ct_action actions[MLX5_ASO_CT_ACTIONS_PER_POOL]; 1090 /* CT action structures bulk. */ 1091 }; 1092 1093 LIST_HEAD(aso_ct_list, mlx5_aso_ct_action); 1094 1095 /* Pools management structure for ASO connection tracking pools. */ 1096 struct mlx5_aso_ct_pools_mng { 1097 struct mlx5_aso_ct_pool **pools; 1098 uint16_t n; /* Total number of pools. */ 1099 uint16_t next; /* Number of pools in use, index of next free pool. */ 1100 rte_spinlock_t ct_sl; /* The ASO CT free list lock. */ 1101 rte_rwlock_t resize_rwl; /* The ASO CT pool resize lock. */ 1102 struct aso_ct_list free_cts; /* Free ASO CT objects list. */ 1103 struct mlx5_aso_sq aso_sq; /* ASO queue objects. */ 1104 }; 1105 1106 /* LAG attr. */ 1107 struct mlx5_lag { 1108 uint8_t tx_remap_affinity[16]; /* The PF port number of affinity */ 1109 uint8_t affinity_mode; /* TIS or hash based affinity */ 1110 }; 1111 1112 /* DevX flex parser context. */ 1113 struct mlx5_flex_parser_devx { 1114 struct mlx5_list_entry entry; /* List element at the beginning. */ 1115 uint32_t num_samples; 1116 void *devx_obj; 1117 struct mlx5_devx_graph_node_attr devx_conf; 1118 uint32_t sample_ids[MLX5_GRAPH_NODE_SAMPLE_NUM]; 1119 }; 1120 1121 /* Pattern field dscriptor - how to translate flex pattern into samples. */ 1122 __extension__ 1123 struct mlx5_flex_pattern_field { 1124 uint16_t width:6; 1125 uint16_t shift:5; 1126 uint16_t reg_id:5; 1127 }; 1128 #define MLX5_INVALID_SAMPLE_REG_ID 0x1F 1129 1130 /* Port flex item context. */ 1131 struct mlx5_flex_item { 1132 struct mlx5_flex_parser_devx *devx_fp; /* DevX flex parser object. */ 1133 uint32_t refcnt; /* Atomically accessed refcnt by flows. */ 1134 enum rte_flow_item_flex_tunnel_mode tunnel_mode; /* Tunnel mode. */ 1135 uint32_t mapnum; /* Number of pattern translation entries. */ 1136 struct mlx5_flex_pattern_field map[MLX5_FLEX_ITEM_MAPPING_NUM]; 1137 }; 1138 1139 /* 1140 * Shared Infiniband device context for Master/Representors 1141 * which belong to same IB device with multiple IB ports. 1142 **/ 1143 struct mlx5_dev_ctx_shared { 1144 LIST_ENTRY(mlx5_dev_ctx_shared) next; 1145 uint32_t refcnt; 1146 uint32_t devx:1; /* Opened with DV. */ 1147 uint32_t flow_hit_aso_en:1; /* Flow Hit ASO is supported. */ 1148 uint32_t steering_format_version:4; 1149 /* Indicates the device steering logic format. */ 1150 uint32_t meter_aso_en:1; /* Flow Meter ASO is supported. */ 1151 uint32_t ct_aso_en:1; /* Connection Tracking ASO is supported. */ 1152 uint32_t tunnel_header_0_1:1; /* tunnel_header_0_1 is supported. */ 1153 uint32_t misc5_cap:1; /* misc5 matcher parameter is supported. */ 1154 uint32_t reclaim_mode:1; /* Reclaim memory. */ 1155 uint32_t dr_drop_action_en:1; /* Use DR drop action. */ 1156 uint32_t drop_action_check_flag:1; /* Check Flag for drop action. */ 1157 uint32_t flow_priority_check_flag:1; /* Check Flag for flow priority. */ 1158 uint32_t metadata_regc_check_flag:1; /* Check Flag for metadata REGC. */ 1159 uint32_t max_port; /* Maximal IB device port index. */ 1160 struct mlx5_bond_info bond; /* Bonding information. */ 1161 struct mlx5_common_device *cdev; /* Backend mlx5 device. */ 1162 uint32_t tdn; /* Transport Domain number. */ 1163 char ibdev_name[MLX5_FS_NAME_MAX]; /* SYSFS dev name. */ 1164 char ibdev_path[MLX5_FS_PATH_MAX]; /* SYSFS dev path for secondary */ 1165 struct mlx5_dev_attr device_attr; /* Device properties. */ 1166 int numa_node; /* Numa node of backing physical device. */ 1167 /* Packet pacing related structure. */ 1168 struct mlx5_dev_txpp txpp; 1169 /* Shared DV/DR flow data section. */ 1170 uint32_t dv_meta_mask; /* flow META metadata supported mask. */ 1171 uint32_t dv_mark_mask; /* flow MARK metadata supported mask. */ 1172 uint32_t dv_regc0_mask; /* available bits of metatada reg_c[0]. */ 1173 void *fdb_domain; /* FDB Direct Rules name space handle. */ 1174 void *rx_domain; /* RX Direct Rules name space handle. */ 1175 void *tx_domain; /* TX Direct Rules name space handle. */ 1176 #ifndef RTE_ARCH_64 1177 rte_spinlock_t uar_lock_cq; /* CQs share a common distinct UAR. */ 1178 rte_spinlock_t uar_lock[MLX5_UAR_PAGE_NUM_MAX]; 1179 /* UAR same-page access control required in 32bit implementations. */ 1180 #endif 1181 struct mlx5_hlist *flow_tbls; 1182 struct mlx5_flow_tunnel_hub *tunnel_hub; 1183 /* Direct Rules tables for FDB, NIC TX+RX */ 1184 void *dr_drop_action; /* Pointer to DR drop action, any domain. */ 1185 void *pop_vlan_action; /* Pointer to DR pop VLAN action. */ 1186 struct mlx5_hlist *encaps_decaps; /* Encap/decap action hash list. */ 1187 struct mlx5_hlist *modify_cmds; 1188 struct mlx5_hlist *tag_table; 1189 struct mlx5_list *port_id_action_list; /* Port ID action list. */ 1190 struct mlx5_list *push_vlan_action_list; /* Push VLAN actions. */ 1191 struct mlx5_list *sample_action_list; /* List of sample actions. */ 1192 struct mlx5_list *dest_array_list; 1193 struct mlx5_list *flex_parsers_dv; /* Flex Item parsers. */ 1194 /* List of destination array actions. */ 1195 struct mlx5_flow_counter_mng cmng; /* Counters management structure. */ 1196 void *default_miss_action; /* Default miss action. */ 1197 struct mlx5_indexed_pool *ipool[MLX5_IPOOL_MAX]; 1198 struct mlx5_indexed_pool *mdh_ipools[MLX5_MAX_MODIFY_NUM]; 1199 /* Shared interrupt handler section. */ 1200 struct rte_intr_handle *intr_handle; /* Interrupt handler for device. */ 1201 struct rte_intr_handle *intr_handle_devx; /* DEVX interrupt handler. */ 1202 void *devx_comp; /* DEVX async comp obj. */ 1203 struct mlx5_devx_obj *tis[16]; /* TIS object. */ 1204 struct mlx5_devx_obj *td; /* Transport domain. */ 1205 struct mlx5_lag lag; /* LAG attributes */ 1206 struct mlx5_uar tx_uar; /* DevX UAR for Tx and Txpp and ASO SQs. */ 1207 struct mlx5_uar rx_uar; /* DevX UAR for Rx. */ 1208 struct mlx5_proc_priv *pppriv; /* Pointer to primary private process. */ 1209 struct mlx5_ecpri_parser_profile ecpri_parser; 1210 /* Flex parser profiles information. */ 1211 LIST_HEAD(shared_rxqs, mlx5_rxq_ctrl) shared_rxqs; /* Shared RXQs. */ 1212 struct mlx5_aso_age_mng *aso_age_mng; 1213 /* Management data for aging mechanism using ASO Flow Hit. */ 1214 struct mlx5_geneve_tlv_option_resource *geneve_tlv_option_resource; 1215 /* Management structure for geneve tlv option */ 1216 rte_spinlock_t geneve_tlv_opt_sl; /* Lock for geneve tlv resource */ 1217 struct mlx5_flow_mtr_mng *mtrmng; 1218 /* Meter management structure. */ 1219 struct mlx5_aso_ct_pools_mng *ct_mng; 1220 /* Management data for ASO connection tracking. */ 1221 struct mlx5_lb_ctx self_lb; /* QP to enable self loopback for Devx. */ 1222 unsigned int flow_max_priority; 1223 enum modify_reg flow_mreg_c[MLX5_MREG_C_NUM]; 1224 /* Availability of mreg_c's. */ 1225 struct mlx5_dev_shared_port port[]; /* per device port data array. */ 1226 }; 1227 1228 /* 1229 * Per-process private structure. 1230 * Caution, secondary process may rebuild the struct during port start. 1231 */ 1232 struct mlx5_proc_priv { 1233 size_t uar_table_sz; 1234 /* Size of UAR register table. */ 1235 struct mlx5_uar_data uar_table[]; 1236 /* Table of UAR registers for each process. */ 1237 }; 1238 1239 /* MTR profile list. */ 1240 TAILQ_HEAD(mlx5_mtr_profiles, mlx5_flow_meter_profile); 1241 /* MTR list. */ 1242 TAILQ_HEAD(mlx5_legacy_flow_meters, mlx5_legacy_flow_meter); 1243 1244 /* RSS description. */ 1245 struct mlx5_flow_rss_desc { 1246 uint32_t level; 1247 uint32_t queue_num; /**< Number of entries in @p queue. */ 1248 uint64_t types; /**< Specific RSS hash types (see RTE_ETH_RSS_*). */ 1249 uint64_t hash_fields; /* Verbs Hash fields. */ 1250 uint8_t key[MLX5_RSS_HASH_KEY_LEN]; /**< RSS hash key. */ 1251 uint32_t key_len; /**< RSS hash key len. */ 1252 uint32_t tunnel; /**< Queue in tunnel. */ 1253 uint32_t shared_rss; /**< Shared RSS index. */ 1254 struct mlx5_ind_table_obj *ind_tbl; 1255 /**< Indirection table for shared RSS hash RX queues. */ 1256 union { 1257 uint16_t *queue; /**< Destination queues. */ 1258 const uint16_t *const_q; /**< Const pointer convert. */ 1259 }; 1260 }; 1261 1262 #define MLX5_PROC_PRIV(port_id) \ 1263 ((struct mlx5_proc_priv *)rte_eth_devices[port_id].process_private) 1264 1265 /* Verbs/DevX Rx queue elements. */ 1266 struct mlx5_rxq_obj { 1267 LIST_ENTRY(mlx5_rxq_obj) next; /* Pointer to the next element. */ 1268 struct mlx5_rxq_ctrl *rxq_ctrl; /* Back pointer to parent. */ 1269 int fd; /* File descriptor for event channel */ 1270 RTE_STD_C11 1271 union { 1272 struct { 1273 void *wq; /* Work Queue. */ 1274 void *ibv_cq; /* Completion Queue. */ 1275 void *ibv_channel; 1276 }; 1277 struct mlx5_devx_obj *rq; /* DevX RQ object for hairpin. */ 1278 struct { 1279 struct mlx5_devx_rmp devx_rmp; /* RMP for shared RQ. */ 1280 struct mlx5_devx_cq cq_obj; /* DevX CQ object. */ 1281 void *devx_channel; 1282 }; 1283 }; 1284 }; 1285 1286 /* Indirection table. */ 1287 struct mlx5_ind_table_obj { 1288 LIST_ENTRY(mlx5_ind_table_obj) next; /* Pointer to the next element. */ 1289 uint32_t refcnt; /* Reference counter. */ 1290 RTE_STD_C11 1291 union { 1292 void *ind_table; /**< Indirection table. */ 1293 struct mlx5_devx_obj *rqt; /* DevX RQT object. */ 1294 }; 1295 uint32_t queues_n; /**< Number of queues in the list. */ 1296 uint16_t *queues; /**< Queue list. */ 1297 }; 1298 1299 /* Hash Rx queue. */ 1300 __extension__ 1301 struct mlx5_hrxq { 1302 struct mlx5_list_entry entry; /* List entry. */ 1303 uint32_t standalone:1; /* This object used in shared action. */ 1304 struct mlx5_ind_table_obj *ind_table; /* Indirection table. */ 1305 RTE_STD_C11 1306 union { 1307 void *qp; /* Verbs queue pair. */ 1308 struct mlx5_devx_obj *tir; /* DevX TIR object. */ 1309 }; 1310 #if defined(HAVE_IBV_FLOW_DV_SUPPORT) || !defined(HAVE_INFINIBAND_VERBS_H) 1311 void *action; /* DV QP action pointer. */ 1312 #endif 1313 uint64_t hash_fields; /* Verbs Hash fields. */ 1314 uint32_t rss_key_len; /* Hash key length in bytes. */ 1315 uint32_t idx; /* Hash Rx queue index. */ 1316 uint8_t rss_key[]; /* Hash key. */ 1317 }; 1318 1319 /* Verbs/DevX Tx queue elements. */ 1320 struct mlx5_txq_obj { 1321 LIST_ENTRY(mlx5_txq_obj) next; /* Pointer to the next element. */ 1322 struct mlx5_txq_ctrl *txq_ctrl; /* Pointer to the control queue. */ 1323 RTE_STD_C11 1324 union { 1325 struct { 1326 void *cq; /* Completion Queue. */ 1327 void *qp; /* Queue Pair. */ 1328 }; 1329 struct { 1330 struct mlx5_devx_obj *sq; 1331 /* DevX object for Sx queue. */ 1332 struct mlx5_devx_obj *tis; /* The TIS object. */ 1333 }; 1334 struct { 1335 struct rte_eth_dev *dev; 1336 struct mlx5_devx_cq cq_obj; 1337 /* DevX CQ object and its resources. */ 1338 struct mlx5_devx_sq sq_obj; 1339 /* DevX SQ object and its resources. */ 1340 }; 1341 }; 1342 }; 1343 1344 enum mlx5_rxq_modify_type { 1345 MLX5_RXQ_MOD_ERR2RST, /* modify state from error to reset. */ 1346 MLX5_RXQ_MOD_RST2RDY, /* modify state from reset to ready. */ 1347 MLX5_RXQ_MOD_RDY2ERR, /* modify state from ready to error. */ 1348 MLX5_RXQ_MOD_RDY2RST, /* modify state from ready to reset. */ 1349 }; 1350 1351 enum mlx5_txq_modify_type { 1352 MLX5_TXQ_MOD_RST2RDY, /* modify state from reset to ready. */ 1353 MLX5_TXQ_MOD_RDY2RST, /* modify state from ready to reset. */ 1354 MLX5_TXQ_MOD_ERR2RDY, /* modify state from error to ready. */ 1355 }; 1356 1357 struct mlx5_rxq_priv; 1358 1359 /* HW objects operations structure. */ 1360 struct mlx5_obj_ops { 1361 int (*rxq_obj_modify_vlan_strip)(struct mlx5_rxq_priv *rxq, int on); 1362 int (*rxq_obj_new)(struct mlx5_rxq_priv *rxq); 1363 int (*rxq_event_get)(struct mlx5_rxq_obj *rxq_obj); 1364 int (*rxq_obj_modify)(struct mlx5_rxq_priv *rxq, uint8_t type); 1365 void (*rxq_obj_release)(struct mlx5_rxq_priv *rxq); 1366 int (*ind_table_new)(struct rte_eth_dev *dev, const unsigned int log_n, 1367 struct mlx5_ind_table_obj *ind_tbl); 1368 int (*ind_table_modify)(struct rte_eth_dev *dev, 1369 const unsigned int log_n, 1370 const uint16_t *queues, const uint32_t queues_n, 1371 struct mlx5_ind_table_obj *ind_tbl); 1372 void (*ind_table_destroy)(struct mlx5_ind_table_obj *ind_tbl); 1373 int (*hrxq_new)(struct rte_eth_dev *dev, struct mlx5_hrxq *hrxq, 1374 int tunnel __rte_unused); 1375 int (*hrxq_modify)(struct rte_eth_dev *dev, struct mlx5_hrxq *hrxq, 1376 const uint8_t *rss_key, 1377 uint64_t hash_fields, 1378 const struct mlx5_ind_table_obj *ind_tbl); 1379 void (*hrxq_destroy)(struct mlx5_hrxq *hrxq); 1380 int (*drop_action_create)(struct rte_eth_dev *dev); 1381 void (*drop_action_destroy)(struct rte_eth_dev *dev); 1382 int (*txq_obj_new)(struct rte_eth_dev *dev, uint16_t idx); 1383 int (*txq_obj_modify)(struct mlx5_txq_obj *obj, 1384 enum mlx5_txq_modify_type type, uint8_t dev_port); 1385 void (*txq_obj_release)(struct mlx5_txq_obj *txq_obj); 1386 int (*lb_dummy_queue_create)(struct rte_eth_dev *dev); 1387 void (*lb_dummy_queue_release)(struct rte_eth_dev *dev); 1388 }; 1389 1390 #define MLX5_RSS_HASH_FIELDS_LEN RTE_DIM(mlx5_rss_hash_fields) 1391 1392 struct mlx5_priv { 1393 struct rte_eth_dev_data *dev_data; /* Pointer to device data. */ 1394 struct mlx5_dev_ctx_shared *sh; /* Shared device context. */ 1395 uint32_t dev_port; /* Device port number. */ 1396 struct rte_pci_device *pci_dev; /* Backend PCI device. */ 1397 struct rte_ether_addr mac[MLX5_MAX_MAC_ADDRESSES]; /* MAC addresses. */ 1398 BITFIELD_DECLARE(mac_own, uint64_t, MLX5_MAX_MAC_ADDRESSES); 1399 /* Bit-field of MAC addresses owned by the PMD. */ 1400 uint16_t vlan_filter[MLX5_MAX_VLAN_IDS]; /* VLAN filters table. */ 1401 unsigned int vlan_filter_n; /* Number of configured VLAN filters. */ 1402 /* Device properties. */ 1403 uint16_t mtu; /* Configured MTU. */ 1404 unsigned int isolated:1; /* Whether isolated mode is enabled. */ 1405 unsigned int representor:1; /* Device is a port representor. */ 1406 unsigned int master:1; /* Device is a E-Switch master. */ 1407 unsigned int txpp_en:1; /* Tx packet pacing enabled. */ 1408 unsigned int sampler_en:1; /* Whether support sampler. */ 1409 unsigned int mtr_en:1; /* Whether support meter. */ 1410 unsigned int mtr_reg_share:1; /* Whether support meter REG_C share. */ 1411 unsigned int lb_used:1; /* Loopback queue is referred to. */ 1412 uint16_t domain_id; /* Switch domain identifier. */ 1413 uint16_t vport_id; /* Associated VF vport index (if any). */ 1414 uint32_t vport_meta_tag; /* Used for vport index match ove VF LAG. */ 1415 uint32_t vport_meta_mask; /* Used for vport index field match mask. */ 1416 uint16_t representor_id; /* UINT16_MAX if not a representor. */ 1417 int32_t pf_bond; /* >=0, representor owner PF index in bonding. */ 1418 unsigned int if_index; /* Associated kernel network device index. */ 1419 /* RX/TX queues. */ 1420 unsigned int rxqs_n; /* RX queues array size. */ 1421 unsigned int txqs_n; /* TX queues array size. */ 1422 struct mlx5_rxq_priv *(*rxq_privs)[]; /* RX queue non-shared data. */ 1423 struct mlx5_txq_data *(*txqs)[]; /* TX queues. */ 1424 struct rte_mempool *mprq_mp; /* Mempool for Multi-Packet RQ. */ 1425 struct rte_eth_rss_conf rss_conf; /* RSS configuration. */ 1426 unsigned int (*reta_idx)[]; /* RETA index table. */ 1427 unsigned int reta_idx_n; /* RETA index size. */ 1428 struct mlx5_drop drop_queue; /* Flow drop queues. */ 1429 void *root_drop_action; /* Pointer to root drop action. */ 1430 struct mlx5_indexed_pool *flows[MLX5_FLOW_TYPE_MAXI]; 1431 /* RTE Flow rules. */ 1432 uint32_t ctrl_flows; /* Control flow rules. */ 1433 rte_spinlock_t flow_list_lock; 1434 struct mlx5_obj_ops obj_ops; /* HW objects operations. */ 1435 LIST_HEAD(rxq, mlx5_rxq_ctrl) rxqsctrl; /* DPDK Rx queues. */ 1436 LIST_HEAD(rxqobj, mlx5_rxq_obj) rxqsobj; /* Verbs/DevX Rx queues. */ 1437 struct mlx5_list *hrxqs; /* Hash Rx queues. */ 1438 LIST_HEAD(txq, mlx5_txq_ctrl) txqsctrl; /* DPDK Tx queues. */ 1439 LIST_HEAD(txqobj, mlx5_txq_obj) txqsobj; /* Verbs/DevX Tx queues. */ 1440 /* Indirection tables. */ 1441 LIST_HEAD(ind_tables, mlx5_ind_table_obj) ind_tbls; 1442 /* Pointer to next element. */ 1443 rte_rwlock_t ind_tbls_lock; 1444 uint32_t refcnt; /**< Reference counter. */ 1445 /**< Verbs modify header action object. */ 1446 uint8_t ft_type; /**< Flow table type, Rx or Tx. */ 1447 uint8_t max_lro_msg_size; 1448 uint32_t link_speed_capa; /* Link speed capabilities. */ 1449 struct mlx5_xstats_ctrl xstats_ctrl; /* Extended stats control. */ 1450 struct mlx5_stats_ctrl stats_ctrl; /* Stats control. */ 1451 struct mlx5_dev_config config; /* Device configuration. */ 1452 /* Context for Verbs allocator. */ 1453 int nl_socket_rdma; /* Netlink socket (NETLINK_RDMA). */ 1454 int nl_socket_route; /* Netlink socket (NETLINK_ROUTE). */ 1455 struct mlx5_nl_vlan_vmwa_context *vmwa_context; /* VLAN WA context. */ 1456 struct mlx5_hlist *mreg_cp_tbl; 1457 /* Hash table of Rx metadata register copy table. */ 1458 uint8_t mtr_sfx_reg; /* Meter prefix-suffix flow match REG_C. */ 1459 uint8_t mtr_color_reg; /* Meter color match REG_C. */ 1460 struct mlx5_legacy_flow_meters flow_meters; /* MTR list. */ 1461 struct mlx5_l3t_tbl *mtr_profile_tbl; /* Meter index lookup table. */ 1462 struct mlx5_l3t_tbl *policy_idx_tbl; /* Policy index lookup table. */ 1463 struct mlx5_l3t_tbl *mtr_idx_tbl; /* Meter index lookup table. */ 1464 uint8_t skip_default_rss_reta; /* Skip configuration of default reta. */ 1465 uint8_t fdb_def_rule; /* Whether fdb jump to table 1 is configured. */ 1466 struct mlx5_mp_id mp_id; /* ID of a multi-process process */ 1467 LIST_HEAD(fdir, mlx5_fdir_flow) fdir_flows; /* fdir flows. */ 1468 rte_spinlock_t shared_act_sl; /* Shared actions spinlock. */ 1469 uint32_t rss_shared_actions; /* RSS shared actions. */ 1470 struct mlx5_devx_obj *q_counters; /* DevX queue counter object. */ 1471 uint32_t counter_set_id; /* Queue counter ID to set in DevX objects. */ 1472 uint32_t lag_affinity_idx; /* LAG mode queue 0 affinity starting. */ 1473 rte_spinlock_t flex_item_sl; /* Flex item list spinlock. */ 1474 struct mlx5_flex_item flex_item[MLX5_PORT_FLEX_ITEM_NUM]; 1475 /* Flex items have been created on the port. */ 1476 uint32_t flex_item_map; /* Map of allocated flex item elements. */ 1477 }; 1478 1479 #define PORT_ID(priv) ((priv)->dev_data->port_id) 1480 #define ETH_DEV(priv) (&rte_eth_devices[PORT_ID(priv)]) 1481 1482 struct rte_hairpin_peer_info { 1483 uint32_t qp_id; 1484 uint32_t vhca_id; 1485 uint16_t peer_q; 1486 uint16_t tx_explicit; 1487 uint16_t manual_bind; 1488 }; 1489 1490 #define BUF_SIZE 1024 1491 enum dr_dump_rec_type { 1492 DR_DUMP_REC_TYPE_PMD_PKT_REFORMAT = 4410, 1493 DR_DUMP_REC_TYPE_PMD_MODIFY_HDR = 4420, 1494 DR_DUMP_REC_TYPE_PMD_COUNTER = 4430, 1495 }; 1496 1497 /* mlx5.c */ 1498 1499 int mlx5_getenv_int(const char *); 1500 int mlx5_proc_priv_init(struct rte_eth_dev *dev); 1501 void mlx5_proc_priv_uninit(struct rte_eth_dev *dev); 1502 int mlx5_udp_tunnel_port_add(struct rte_eth_dev *dev, 1503 struct rte_eth_udp_tunnel *udp_tunnel); 1504 uint16_t mlx5_eth_find_next(uint16_t port_id, struct rte_device *odev); 1505 int mlx5_dev_close(struct rte_eth_dev *dev); 1506 int mlx5_net_remove(struct mlx5_common_device *cdev); 1507 bool mlx5_is_hpf(struct rte_eth_dev *dev); 1508 bool mlx5_is_sf_repr(struct rte_eth_dev *dev); 1509 void mlx5_age_event_prepare(struct mlx5_dev_ctx_shared *sh); 1510 1511 /* Macro to iterate over all valid ports for mlx5 driver. */ 1512 #define MLX5_ETH_FOREACH_DEV(port_id, dev) \ 1513 for (port_id = mlx5_eth_find_next(0, dev); \ 1514 port_id < RTE_MAX_ETHPORTS; \ 1515 port_id = mlx5_eth_find_next(port_id + 1, dev)) 1516 int mlx5_args(struct mlx5_dev_config *config, struct rte_devargs *devargs); 1517 struct mlx5_dev_ctx_shared * 1518 mlx5_alloc_shared_dev_ctx(const struct mlx5_dev_spawn_data *spawn, 1519 const struct mlx5_dev_config *config); 1520 void mlx5_free_shared_dev_ctx(struct mlx5_dev_ctx_shared *sh); 1521 int mlx5_dev_ctx_shared_mempool_subscribe(struct rte_eth_dev *dev); 1522 void mlx5_free_table_hash_list(struct mlx5_priv *priv); 1523 int mlx5_alloc_table_hash_list(struct mlx5_priv *priv); 1524 void mlx5_set_min_inline(struct mlx5_dev_spawn_data *spawn, 1525 struct mlx5_dev_config *config); 1526 void mlx5_set_metadata_mask(struct rte_eth_dev *dev); 1527 int mlx5_dev_check_sibling_config(struct mlx5_priv *priv, 1528 struct mlx5_dev_config *config, 1529 struct rte_device *dpdk_dev); 1530 int mlx5_dev_infos_get(struct rte_eth_dev *dev, struct rte_eth_dev_info *info); 1531 int mlx5_fw_version_get(struct rte_eth_dev *dev, char *fw_ver, size_t fw_size); 1532 int mlx5_dev_set_mtu(struct rte_eth_dev *dev, uint16_t mtu); 1533 int mlx5_hairpin_cap_get(struct rte_eth_dev *dev, 1534 struct rte_eth_hairpin_cap *cap); 1535 bool mlx5_flex_parser_ecpri_exist(struct rte_eth_dev *dev); 1536 int mlx5_flex_parser_ecpri_alloc(struct rte_eth_dev *dev); 1537 int mlx5_flow_aso_age_mng_init(struct mlx5_dev_ctx_shared *sh); 1538 int mlx5_aso_flow_mtrs_mng_init(struct mlx5_dev_ctx_shared *sh); 1539 int mlx5_flow_aso_ct_mng_init(struct mlx5_dev_ctx_shared *sh); 1540 1541 /* mlx5_ethdev.c */ 1542 1543 int mlx5_dev_configure(struct rte_eth_dev *dev); 1544 int mlx5_representor_info_get(struct rte_eth_dev *dev, 1545 struct rte_eth_representor_info *info); 1546 #define MLX5_REPRESENTOR_ID(pf, type, repr) \ 1547 (((pf) << 14) + ((type) << 12) + ((repr) & 0xfff)) 1548 #define MLX5_REPRESENTOR_REPR(repr_id) \ 1549 ((repr_id) & 0xfff) 1550 #define MLX5_REPRESENTOR_TYPE(repr_id) \ 1551 (((repr_id) >> 12) & 3) 1552 uint16_t mlx5_representor_id_encode(const struct mlx5_switch_info *info, 1553 enum rte_eth_representor_type hpf_type); 1554 int mlx5_fw_version_get(struct rte_eth_dev *dev, char *fw_ver, 1555 size_t fw_size); 1556 int mlx5_dev_infos_get(struct rte_eth_dev *dev, 1557 struct rte_eth_dev_info *info); 1558 const uint32_t *mlx5_dev_supported_ptypes_get(struct rte_eth_dev *dev); 1559 int mlx5_dev_set_mtu(struct rte_eth_dev *dev, uint16_t mtu); 1560 int mlx5_hairpin_cap_get(struct rte_eth_dev *dev, 1561 struct rte_eth_hairpin_cap *cap); 1562 eth_rx_burst_t mlx5_select_rx_function(struct rte_eth_dev *dev); 1563 struct mlx5_priv *mlx5_port_to_eswitch_info(uint16_t port, bool valid); 1564 struct mlx5_priv *mlx5_dev_to_eswitch_info(struct rte_eth_dev *dev); 1565 int mlx5_dev_configure_rss_reta(struct rte_eth_dev *dev); 1566 1567 /* mlx5_ethdev_os.c */ 1568 1569 int mlx5_get_ifname(const struct rte_eth_dev *dev, 1570 char (*ifname)[MLX5_NAMESIZE]); 1571 unsigned int mlx5_ifindex(const struct rte_eth_dev *dev); 1572 int mlx5_get_mac(struct rte_eth_dev *dev, uint8_t (*mac)[RTE_ETHER_ADDR_LEN]); 1573 int mlx5_get_mtu(struct rte_eth_dev *dev, uint16_t *mtu); 1574 int mlx5_set_mtu(struct rte_eth_dev *dev, uint16_t mtu); 1575 int mlx5_read_clock(struct rte_eth_dev *dev, uint64_t *clock); 1576 int mlx5_link_update(struct rte_eth_dev *dev, int wait_to_complete); 1577 int mlx5_dev_get_flow_ctrl(struct rte_eth_dev *dev, 1578 struct rte_eth_fc_conf *fc_conf); 1579 int mlx5_dev_set_flow_ctrl(struct rte_eth_dev *dev, 1580 struct rte_eth_fc_conf *fc_conf); 1581 void mlx5_dev_interrupt_handler(void *arg); 1582 void mlx5_dev_interrupt_handler_devx(void *arg); 1583 int mlx5_set_link_down(struct rte_eth_dev *dev); 1584 int mlx5_set_link_up(struct rte_eth_dev *dev); 1585 int mlx5_is_removed(struct rte_eth_dev *dev); 1586 int mlx5_sysfs_switch_info(unsigned int ifindex, 1587 struct mlx5_switch_info *info); 1588 void mlx5_translate_port_name(const char *port_name_in, 1589 struct mlx5_switch_info *port_info_out); 1590 void mlx5_intr_callback_unregister(const struct rte_intr_handle *handle, 1591 rte_intr_callback_fn cb_fn, void *cb_arg); 1592 int mlx5_sysfs_bond_info(unsigned int pf_ifindex, unsigned int *ifindex, 1593 char *ifname); 1594 int mlx5_get_module_info(struct rte_eth_dev *dev, 1595 struct rte_eth_dev_module_info *modinfo); 1596 int mlx5_get_module_eeprom(struct rte_eth_dev *dev, 1597 struct rte_dev_eeprom_info *info); 1598 int mlx5_os_read_dev_stat(struct mlx5_priv *priv, 1599 const char *ctr_name, uint64_t *stat); 1600 int mlx5_os_read_dev_counters(struct rte_eth_dev *dev, uint64_t *stats); 1601 int mlx5_os_get_stats_n(struct rte_eth_dev *dev); 1602 void mlx5_os_stats_init(struct rte_eth_dev *dev); 1603 int mlx5_get_flag_dropless_rq(struct rte_eth_dev *dev); 1604 1605 /* mlx5_mac.c */ 1606 1607 void mlx5_mac_addr_remove(struct rte_eth_dev *dev, uint32_t index); 1608 int mlx5_mac_addr_add(struct rte_eth_dev *dev, struct rte_ether_addr *mac, 1609 uint32_t index, uint32_t vmdq); 1610 int mlx5_mac_addr_set(struct rte_eth_dev *dev, struct rte_ether_addr *mac_addr); 1611 int mlx5_set_mc_addr_list(struct rte_eth_dev *dev, 1612 struct rte_ether_addr *mc_addr_set, 1613 uint32_t nb_mc_addr); 1614 1615 /* mlx5_rss.c */ 1616 1617 int mlx5_rss_hash_update(struct rte_eth_dev *dev, 1618 struct rte_eth_rss_conf *rss_conf); 1619 int mlx5_rss_hash_conf_get(struct rte_eth_dev *dev, 1620 struct rte_eth_rss_conf *rss_conf); 1621 int mlx5_rss_reta_index_resize(struct rte_eth_dev *dev, unsigned int reta_size); 1622 int mlx5_dev_rss_reta_query(struct rte_eth_dev *dev, 1623 struct rte_eth_rss_reta_entry64 *reta_conf, 1624 uint16_t reta_size); 1625 int mlx5_dev_rss_reta_update(struct rte_eth_dev *dev, 1626 struct rte_eth_rss_reta_entry64 *reta_conf, 1627 uint16_t reta_size); 1628 1629 /* mlx5_rxmode.c */ 1630 1631 int mlx5_promiscuous_enable(struct rte_eth_dev *dev); 1632 int mlx5_promiscuous_disable(struct rte_eth_dev *dev); 1633 int mlx5_allmulticast_enable(struct rte_eth_dev *dev); 1634 int mlx5_allmulticast_disable(struct rte_eth_dev *dev); 1635 1636 /* mlx5_stats.c */ 1637 1638 int mlx5_stats_get(struct rte_eth_dev *dev, struct rte_eth_stats *stats); 1639 int mlx5_stats_reset(struct rte_eth_dev *dev); 1640 int mlx5_xstats_get(struct rte_eth_dev *dev, struct rte_eth_xstat *stats, 1641 unsigned int n); 1642 int mlx5_xstats_reset(struct rte_eth_dev *dev); 1643 int mlx5_xstats_get_names(struct rte_eth_dev *dev __rte_unused, 1644 struct rte_eth_xstat_name *xstats_names, 1645 unsigned int n); 1646 1647 /* mlx5_vlan.c */ 1648 1649 int mlx5_vlan_filter_set(struct rte_eth_dev *dev, uint16_t vlan_id, int on); 1650 void mlx5_vlan_strip_queue_set(struct rte_eth_dev *dev, uint16_t queue, int on); 1651 int mlx5_vlan_offload_set(struct rte_eth_dev *dev, int mask); 1652 1653 /* mlx5_vlan_os.c */ 1654 1655 void mlx5_vlan_vmwa_exit(void *ctx); 1656 void mlx5_vlan_vmwa_release(struct rte_eth_dev *dev, 1657 struct mlx5_vf_vlan *vf_vlan); 1658 void mlx5_vlan_vmwa_acquire(struct rte_eth_dev *dev, 1659 struct mlx5_vf_vlan *vf_vlan); 1660 void *mlx5_vlan_vmwa_init(struct rte_eth_dev *dev, uint32_t ifindex); 1661 1662 /* mlx5_trigger.c */ 1663 1664 int mlx5_dev_start(struct rte_eth_dev *dev); 1665 int mlx5_dev_stop(struct rte_eth_dev *dev); 1666 int mlx5_traffic_enable(struct rte_eth_dev *dev); 1667 void mlx5_traffic_disable(struct rte_eth_dev *dev); 1668 int mlx5_traffic_restart(struct rte_eth_dev *dev); 1669 int mlx5_hairpin_queue_peer_update(struct rte_eth_dev *dev, uint16_t peer_queue, 1670 struct rte_hairpin_peer_info *current_info, 1671 struct rte_hairpin_peer_info *peer_info, 1672 uint32_t direction); 1673 int mlx5_hairpin_queue_peer_bind(struct rte_eth_dev *dev, uint16_t cur_queue, 1674 struct rte_hairpin_peer_info *peer_info, 1675 uint32_t direction); 1676 int mlx5_hairpin_queue_peer_unbind(struct rte_eth_dev *dev, uint16_t cur_queue, 1677 uint32_t direction); 1678 int mlx5_hairpin_bind(struct rte_eth_dev *dev, uint16_t rx_port); 1679 int mlx5_hairpin_unbind(struct rte_eth_dev *dev, uint16_t rx_port); 1680 int mlx5_hairpin_get_peer_ports(struct rte_eth_dev *dev, uint16_t *peer_ports, 1681 size_t len, uint32_t direction); 1682 1683 /* mlx5_flow.c */ 1684 1685 int mlx5_flow_discover_mreg_c(struct rte_eth_dev *eth_dev); 1686 bool mlx5_flow_ext_mreg_supported(struct rte_eth_dev *dev); 1687 void mlx5_flow_print(struct rte_flow *flow); 1688 int mlx5_flow_validate(struct rte_eth_dev *dev, 1689 const struct rte_flow_attr *attr, 1690 const struct rte_flow_item items[], 1691 const struct rte_flow_action actions[], 1692 struct rte_flow_error *error); 1693 struct rte_flow *mlx5_flow_create(struct rte_eth_dev *dev, 1694 const struct rte_flow_attr *attr, 1695 const struct rte_flow_item items[], 1696 const struct rte_flow_action actions[], 1697 struct rte_flow_error *error); 1698 int mlx5_flow_destroy(struct rte_eth_dev *dev, struct rte_flow *flow, 1699 struct rte_flow_error *error); 1700 void mlx5_flow_list_flush(struct rte_eth_dev *dev, enum mlx5_flow_type type, 1701 bool active); 1702 int mlx5_flow_flush(struct rte_eth_dev *dev, struct rte_flow_error *error); 1703 int mlx5_flow_query(struct rte_eth_dev *dev, struct rte_flow *flow, 1704 const struct rte_flow_action *action, void *data, 1705 struct rte_flow_error *error); 1706 int mlx5_flow_isolate(struct rte_eth_dev *dev, int enable, 1707 struct rte_flow_error *error); 1708 int mlx5_flow_ops_get(struct rte_eth_dev *dev, const struct rte_flow_ops **ops); 1709 int mlx5_flow_start_default(struct rte_eth_dev *dev); 1710 void mlx5_flow_stop_default(struct rte_eth_dev *dev); 1711 int mlx5_flow_verify(struct rte_eth_dev *dev); 1712 int mlx5_ctrl_flow_source_queue(struct rte_eth_dev *dev, uint32_t queue); 1713 int mlx5_ctrl_flow_vlan(struct rte_eth_dev *dev, 1714 struct rte_flow_item_eth *eth_spec, 1715 struct rte_flow_item_eth *eth_mask, 1716 struct rte_flow_item_vlan *vlan_spec, 1717 struct rte_flow_item_vlan *vlan_mask); 1718 int mlx5_ctrl_flow(struct rte_eth_dev *dev, 1719 struct rte_flow_item_eth *eth_spec, 1720 struct rte_flow_item_eth *eth_mask); 1721 int mlx5_flow_lacp_miss(struct rte_eth_dev *dev); 1722 struct rte_flow *mlx5_flow_create_esw_table_zero_flow(struct rte_eth_dev *dev); 1723 uint32_t mlx5_flow_create_devx_sq_miss_flow(struct rte_eth_dev *dev, 1724 uint32_t txq); 1725 void mlx5_flow_async_pool_query_handle(struct mlx5_dev_ctx_shared *sh, 1726 uint64_t async_id, int status); 1727 void mlx5_set_query_alarm(struct mlx5_dev_ctx_shared *sh); 1728 void mlx5_flow_query_alarm(void *arg); 1729 uint32_t mlx5_counter_alloc(struct rte_eth_dev *dev); 1730 void mlx5_counter_free(struct rte_eth_dev *dev, uint32_t cnt); 1731 int mlx5_counter_query(struct rte_eth_dev *dev, uint32_t cnt, 1732 bool clear, uint64_t *pkts, uint64_t *bytes); 1733 int mlx5_flow_dev_dump(struct rte_eth_dev *dev, struct rte_flow *flow, 1734 FILE *file, struct rte_flow_error *error); 1735 int save_dump_file(const unsigned char *data, uint32_t size, 1736 uint32_t type, uint64_t id, void *arg, FILE *file); 1737 int mlx5_flow_query_counter(struct rte_eth_dev *dev, struct rte_flow *flow, 1738 struct rte_flow_query_count *count, struct rte_flow_error *error); 1739 #ifdef HAVE_IBV_FLOW_DV_SUPPORT 1740 int mlx5_flow_dev_dump_ipool(struct rte_eth_dev *dev, struct rte_flow *flow, 1741 FILE *file, struct rte_flow_error *error); 1742 #endif 1743 void mlx5_flow_rxq_dynf_metadata_set(struct rte_eth_dev *dev); 1744 int mlx5_flow_get_aged_flows(struct rte_eth_dev *dev, void **contexts, 1745 uint32_t nb_contexts, struct rte_flow_error *error); 1746 int mlx5_validate_action_ct(struct rte_eth_dev *dev, 1747 const struct rte_flow_action_conntrack *conntrack, 1748 struct rte_flow_error *error); 1749 1750 1751 /* mlx5_mp_os.c */ 1752 1753 int mlx5_mp_os_primary_handle(const struct rte_mp_msg *mp_msg, 1754 const void *peer); 1755 int mlx5_mp_os_secondary_handle(const struct rte_mp_msg *mp_msg, 1756 const void *peer); 1757 void mlx5_mp_os_req_start_rxtx(struct rte_eth_dev *dev); 1758 void mlx5_mp_os_req_stop_rxtx(struct rte_eth_dev *dev); 1759 int mlx5_mp_os_req_queue_control(struct rte_eth_dev *dev, uint16_t queue_id, 1760 enum mlx5_mp_req_type req_type); 1761 1762 /* mlx5_socket.c */ 1763 1764 int mlx5_pmd_socket_init(void); 1765 void mlx5_pmd_socket_uninit(void); 1766 1767 /* mlx5_flow_meter.c */ 1768 1769 int mlx5_flow_meter_ops_get(struct rte_eth_dev *dev, void *arg); 1770 struct mlx5_flow_meter_info *mlx5_flow_meter_find(struct mlx5_priv *priv, 1771 uint32_t meter_id, uint32_t *mtr_idx); 1772 struct mlx5_flow_meter_info * 1773 flow_dv_meter_find_by_idx(struct mlx5_priv *priv, uint32_t idx); 1774 int mlx5_flow_meter_attach(struct mlx5_priv *priv, 1775 struct mlx5_flow_meter_info *fm, 1776 const struct rte_flow_attr *attr, 1777 struct rte_flow_error *error); 1778 void mlx5_flow_meter_detach(struct mlx5_priv *priv, 1779 struct mlx5_flow_meter_info *fm); 1780 struct mlx5_flow_meter_policy *mlx5_flow_meter_policy_find 1781 (struct rte_eth_dev *dev, 1782 uint32_t policy_id, 1783 uint32_t *policy_idx); 1784 struct mlx5_flow_meter_policy * 1785 mlx5_flow_meter_hierarchy_get_final_policy(struct rte_eth_dev *dev, 1786 struct mlx5_flow_meter_policy *policy); 1787 int mlx5_flow_meter_flush(struct rte_eth_dev *dev, 1788 struct rte_mtr_error *error); 1789 void mlx5_flow_meter_rxq_flush(struct rte_eth_dev *dev); 1790 1791 /* mlx5_os.c */ 1792 1793 struct rte_pci_driver; 1794 int mlx5_os_get_dev_attr(struct mlx5_common_device *dev, 1795 struct mlx5_dev_attr *dev_attr); 1796 void mlx5_os_free_shared_dr(struct mlx5_priv *priv); 1797 int mlx5_os_net_probe(struct mlx5_common_device *cdev); 1798 void mlx5_os_dev_shared_handler_install(struct mlx5_dev_ctx_shared *sh); 1799 void mlx5_os_dev_shared_handler_uninstall(struct mlx5_dev_ctx_shared *sh); 1800 void mlx5_os_mac_addr_remove(struct rte_eth_dev *dev, uint32_t index); 1801 int mlx5_os_mac_addr_add(struct rte_eth_dev *dev, struct rte_ether_addr *mac, 1802 uint32_t index); 1803 int mlx5_os_vf_mac_addr_modify(struct mlx5_priv *priv, unsigned int iface_idx, 1804 struct rte_ether_addr *mac_addr, 1805 int vf_index); 1806 int mlx5_os_set_promisc(struct rte_eth_dev *dev, int enable); 1807 int mlx5_os_set_allmulti(struct rte_eth_dev *dev, int enable); 1808 int mlx5_os_set_nonblock_channel_fd(int fd); 1809 void mlx5_os_mac_addr_flush(struct rte_eth_dev *dev); 1810 void mlx5_os_net_cleanup(void); 1811 1812 /* mlx5_txpp.c */ 1813 1814 int mlx5_txpp_start(struct rte_eth_dev *dev); 1815 void mlx5_txpp_stop(struct rte_eth_dev *dev); 1816 int mlx5_txpp_read_clock(struct rte_eth_dev *dev, uint64_t *timestamp); 1817 int mlx5_txpp_xstats_get(struct rte_eth_dev *dev, 1818 struct rte_eth_xstat *stats, 1819 unsigned int n, unsigned int n_used); 1820 int mlx5_txpp_xstats_reset(struct rte_eth_dev *dev); 1821 int mlx5_txpp_xstats_get_names(struct rte_eth_dev *dev, 1822 struct rte_eth_xstat_name *xstats_names, 1823 unsigned int n, unsigned int n_used); 1824 void mlx5_txpp_interrupt_handler(void *cb_arg); 1825 1826 /* mlx5_rxtx.c */ 1827 1828 eth_tx_burst_t mlx5_select_tx_function(struct rte_eth_dev *dev); 1829 1830 /* mlx5_flow_aso.c */ 1831 1832 int mlx5_aso_queue_init(struct mlx5_dev_ctx_shared *sh, 1833 enum mlx5_access_aso_opc_mod aso_opc_mod); 1834 int mlx5_aso_flow_hit_queue_poll_start(struct mlx5_dev_ctx_shared *sh); 1835 int mlx5_aso_flow_hit_queue_poll_stop(struct mlx5_dev_ctx_shared *sh); 1836 void mlx5_aso_queue_uninit(struct mlx5_dev_ctx_shared *sh, 1837 enum mlx5_access_aso_opc_mod aso_opc_mod); 1838 int mlx5_aso_meter_update_by_wqe(struct mlx5_dev_ctx_shared *sh, 1839 struct mlx5_aso_mtr *mtr); 1840 int mlx5_aso_mtr_wait(struct mlx5_dev_ctx_shared *sh, 1841 struct mlx5_aso_mtr *mtr); 1842 int mlx5_aso_ct_update_by_wqe(struct mlx5_dev_ctx_shared *sh, 1843 struct mlx5_aso_ct_action *ct, 1844 const struct rte_flow_action_conntrack *profile); 1845 int mlx5_aso_ct_wait_ready(struct mlx5_dev_ctx_shared *sh, 1846 struct mlx5_aso_ct_action *ct); 1847 int mlx5_aso_ct_query_by_wqe(struct mlx5_dev_ctx_shared *sh, 1848 struct mlx5_aso_ct_action *ct, 1849 struct rte_flow_action_conntrack *profile); 1850 int mlx5_aso_ct_available(struct mlx5_dev_ctx_shared *sh, 1851 struct mlx5_aso_ct_action *ct); 1852 uint32_t 1853 mlx5_get_supported_sw_parsing_offloads(const struct mlx5_hca_attr *attr); 1854 uint32_t 1855 mlx5_get_supported_tunneling_offloads(const struct mlx5_hca_attr *attr); 1856 1857 /* mlx5_flow_flex.c */ 1858 1859 struct rte_flow_item_flex_handle * 1860 flow_dv_item_create(struct rte_eth_dev *dev, 1861 const struct rte_flow_item_flex_conf *conf, 1862 struct rte_flow_error *error); 1863 int flow_dv_item_release(struct rte_eth_dev *dev, 1864 const struct rte_flow_item_flex_handle *flex_handle, 1865 struct rte_flow_error *error); 1866 int mlx5_flex_item_port_init(struct rte_eth_dev *dev); 1867 void mlx5_flex_item_port_cleanup(struct rte_eth_dev *dev); 1868 void mlx5_flex_flow_translate_item(struct rte_eth_dev *dev, void *matcher, 1869 void *key, const struct rte_flow_item *item, 1870 bool is_inner); 1871 int mlx5_flex_acquire_index(struct rte_eth_dev *dev, 1872 struct rte_flow_item_flex_handle *handle, 1873 bool acquire); 1874 int mlx5_flex_release_index(struct rte_eth_dev *dev, int index); 1875 1876 /* Flex parser list callbacks. */ 1877 struct mlx5_list_entry *mlx5_flex_parser_create_cb(void *list_ctx, void *ctx); 1878 int mlx5_flex_parser_match_cb(void *list_ctx, 1879 struct mlx5_list_entry *iter, void *ctx); 1880 void mlx5_flex_parser_remove_cb(void *list_ctx, struct mlx5_list_entry *entry); 1881 struct mlx5_list_entry *mlx5_flex_parser_clone_cb(void *list_ctx, 1882 struct mlx5_list_entry *entry, 1883 void *ctx); 1884 void mlx5_flex_parser_clone_free_cb(void *tool_ctx, 1885 struct mlx5_list_entry *entry); 1886 #endif /* RTE_PMD_MLX5_H_ */ 1887