1 /*- 2 * BSD LICENSE 3 * 4 * Copyright 2015 6WIND S.A. 5 * Copyright 2015 Mellanox. 6 * 7 * Redistribution and use in source and binary forms, with or without 8 * modification, are permitted provided that the following conditions 9 * are met: 10 * 11 * * Redistributions of source code must retain the above copyright 12 * notice, this list of conditions and the following disclaimer. 13 * * Redistributions in binary form must reproduce the above copyright 14 * notice, this list of conditions and the following disclaimer in 15 * the documentation and/or other materials provided with the 16 * distribution. 17 * * Neither the name of 6WIND S.A. nor the names of its 18 * contributors may be used to endorse or promote products derived 19 * from this software without specific prior written permission. 20 * 21 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 22 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 23 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 24 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 25 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 26 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 27 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 28 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 29 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 30 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 31 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 32 */ 33 34 #ifndef RTE_PMD_MLX5_H_ 35 #define RTE_PMD_MLX5_H_ 36 37 #include <stddef.h> 38 #include <stdint.h> 39 #include <limits.h> 40 #include <net/if.h> 41 #include <netinet/in.h> 42 #include <sys/queue.h> 43 44 /* Verbs header. */ 45 /* ISO C doesn't support unnamed structs/unions, disabling -pedantic. */ 46 #ifdef PEDANTIC 47 #pragma GCC diagnostic ignored "-Wpedantic" 48 #endif 49 #include <infiniband/verbs.h> 50 #ifdef PEDANTIC 51 #pragma GCC diagnostic error "-Wpedantic" 52 #endif 53 54 #include <rte_pci.h> 55 #include <rte_ether.h> 56 #include <rte_ethdev_driver.h> 57 #include <rte_spinlock.h> 58 #include <rte_interrupts.h> 59 #include <rte_errno.h> 60 #include <rte_flow.h> 61 62 #include "mlx5_utils.h" 63 #include "mlx5_rxtx.h" 64 #include "mlx5_autoconf.h" 65 #include "mlx5_defs.h" 66 67 enum { 68 PCI_VENDOR_ID_MELLANOX = 0x15b3, 69 }; 70 71 enum { 72 PCI_DEVICE_ID_MELLANOX_CONNECTX4 = 0x1013, 73 PCI_DEVICE_ID_MELLANOX_CONNECTX4VF = 0x1014, 74 PCI_DEVICE_ID_MELLANOX_CONNECTX4LX = 0x1015, 75 PCI_DEVICE_ID_MELLANOX_CONNECTX4LXVF = 0x1016, 76 PCI_DEVICE_ID_MELLANOX_CONNECTX5 = 0x1017, 77 PCI_DEVICE_ID_MELLANOX_CONNECTX5VF = 0x1018, 78 PCI_DEVICE_ID_MELLANOX_CONNECTX5EX = 0x1019, 79 PCI_DEVICE_ID_MELLANOX_CONNECTX5EXVF = 0x101a, 80 }; 81 82 struct mlx5_xstats_ctrl { 83 /* Number of device stats. */ 84 uint16_t stats_n; 85 /* Index in the device counters table. */ 86 uint16_t dev_table_idx[MLX5_MAX_XSTATS]; 87 uint64_t base[MLX5_MAX_XSTATS]; 88 }; 89 90 /* Flow list . */ 91 TAILQ_HEAD(mlx5_flows, rte_flow); 92 93 /* Default PMD specific parameter value. */ 94 #define MLX5_ARG_UNSET (-1) 95 96 /* 97 * Device configuration structure. 98 * 99 * Merged configuration from: 100 * 101 * - Device capabilities, 102 * - User device parameters disabled features. 103 */ 104 struct mlx5_dev_config { 105 unsigned int hw_csum:1; /* Checksum offload is supported. */ 106 unsigned int hw_csum_l2tun:1; /* Same for L2 tunnels. */ 107 unsigned int hw_vlan_strip:1; /* VLAN stripping is supported. */ 108 unsigned int hw_fcs_strip:1; /* FCS stripping is supported. */ 109 unsigned int hw_padding:1; /* End alignment padding is supported. */ 110 unsigned int sriov:1; /* This is a VF or PF with VF devices. */ 111 unsigned int mps:2; /* Multi-packet send supported mode. */ 112 unsigned int tunnel_en:1; /* Whether tunnel is supported. */ 113 unsigned int flow_counter_en:1; /* Whether flow counter is supported. */ 114 unsigned int cqe_comp:1; /* CQE compression is enabled. */ 115 unsigned int tso:1; /* Whether TSO is supported. */ 116 unsigned int tx_vec_en:1; /* Tx vector is enabled. */ 117 unsigned int rx_vec_en:1; /* Rx vector is enabled. */ 118 unsigned int mpw_hdr_dseg:1; /* Enable DSEGs in the title WQEBB. */ 119 unsigned int tso_max_payload_sz; /* Maximum TCP payload for TSO. */ 120 unsigned int ind_table_max_size; /* Maximum indirection table size. */ 121 int txq_inline; /* Maximum packet size for inlining. */ 122 int txqs_inline; /* Queue number threshold for inlining. */ 123 int inline_max_packet_sz; /* Max packet size for inlining. */ 124 }; 125 126 /** 127 * Type of objet being allocated. 128 */ 129 enum mlx5_verbs_alloc_type { 130 MLX5_VERBS_ALLOC_TYPE_NONE, 131 MLX5_VERBS_ALLOC_TYPE_TX_QUEUE, 132 MLX5_VERBS_ALLOC_TYPE_RX_QUEUE, 133 }; 134 135 /** 136 * Verbs allocator needs a context to know in the callback which kind of 137 * resources it is allocating. 138 */ 139 struct mlx5_verbs_alloc_ctx { 140 enum mlx5_verbs_alloc_type type; /* Kind of object being allocated. */ 141 const void *obj; /* Pointer to the DPDK object. */ 142 }; 143 144 struct priv { 145 struct rte_eth_dev *dev; /* Ethernet device of master process. */ 146 struct ibv_context *ctx; /* Verbs context. */ 147 struct ibv_device_attr_ex device_attr; /* Device properties. */ 148 struct ibv_pd *pd; /* Protection Domain. */ 149 char ibdev_path[IBV_SYSFS_PATH_MAX]; /* IB device path for secondary */ 150 struct ether_addr mac[MLX5_MAX_MAC_ADDRESSES]; /* MAC addresses. */ 151 uint16_t vlan_filter[MLX5_MAX_VLAN_IDS]; /* VLAN filters table. */ 152 unsigned int vlan_filter_n; /* Number of configured VLAN filters. */ 153 /* Device properties. */ 154 uint16_t mtu; /* Configured MTU. */ 155 uint8_t port; /* Physical port number. */ 156 unsigned int pending_alarm:1; /* An alarm is pending. */ 157 unsigned int isolated:1; /* Whether isolated mode is enabled. */ 158 /* RX/TX queues. */ 159 unsigned int rxqs_n; /* RX queues array size. */ 160 unsigned int txqs_n; /* TX queues array size. */ 161 struct mlx5_rxq_data *(*rxqs)[]; /* RX queues. */ 162 struct mlx5_txq_data *(*txqs)[]; /* TX queues. */ 163 struct rte_eth_rss_conf rss_conf; /* RSS configuration. */ 164 struct rte_intr_handle intr_handle; /* Interrupt handler. */ 165 unsigned int (*reta_idx)[]; /* RETA index table. */ 166 unsigned int reta_idx_n; /* RETA index size. */ 167 struct mlx5_hrxq_drop *flow_drop_queue; /* Flow drop queue. */ 168 struct mlx5_flows flows; /* RTE Flow rules. */ 169 struct mlx5_flows ctrl_flows; /* Control flow rules. */ 170 LIST_HEAD(mr, mlx5_mr) mr; /* Memory region. */ 171 LIST_HEAD(rxq, mlx5_rxq_ctrl) rxqsctrl; /* DPDK Rx queues. */ 172 LIST_HEAD(rxqibv, mlx5_rxq_ibv) rxqsibv; /* Verbs Rx queues. */ 173 LIST_HEAD(hrxq, mlx5_hrxq) hrxqs; /* Verbs Hash Rx queues. */ 174 LIST_HEAD(txq, mlx5_txq_ctrl) txqsctrl; /* DPDK Tx queues. */ 175 LIST_HEAD(txqibv, mlx5_txq_ibv) txqsibv; /* Verbs Tx queues. */ 176 /* Verbs Indirection tables. */ 177 LIST_HEAD(ind_tables, mlx5_ind_table_ibv) ind_tbls; 178 uint32_t link_speed_capa; /* Link speed capabilities. */ 179 struct mlx5_xstats_ctrl xstats_ctrl; /* Extended stats control. */ 180 rte_spinlock_t lock; /* Lock for control functions. */ 181 int primary_socket; /* Unix socket for primary process. */ 182 void *uar_base; /* Reserved address space for UAR mapping */ 183 struct rte_intr_handle intr_handle_socket; /* Interrupt handler. */ 184 struct mlx5_dev_config config; /* Device configuration. */ 185 struct mlx5_verbs_alloc_ctx verbs_alloc_ctx; 186 /* Context for Verbs allocator. */ 187 }; 188 189 /** 190 * Lock private structure to protect it from concurrent access in the 191 * control path. 192 * 193 * @param priv 194 * Pointer to private structure. 195 */ 196 static inline void 197 priv_lock(struct priv *priv) 198 { 199 rte_spinlock_lock(&priv->lock); 200 } 201 202 /** 203 * Try to lock private structure to protect it from concurrent access in the 204 * control path. 205 * 206 * @param priv 207 * Pointer to private structure. 208 * 209 * @return 210 * 1 if the lock is successfully taken; 0 otherwise. 211 */ 212 static inline int 213 priv_trylock(struct priv *priv) 214 { 215 return rte_spinlock_trylock(&priv->lock); 216 } 217 218 /** 219 * Unlock private structure. 220 * 221 * @param priv 222 * Pointer to private structure. 223 */ 224 static inline void 225 priv_unlock(struct priv *priv) 226 { 227 rte_spinlock_unlock(&priv->lock); 228 } 229 230 /* mlx5.c */ 231 232 int mlx5_getenv_int(const char *); 233 234 /* mlx5_ethdev.c */ 235 236 struct priv *mlx5_get_priv(struct rte_eth_dev *dev); 237 int mlx5_is_secondary(void); 238 int priv_get_ifname(const struct priv *, char (*)[IF_NAMESIZE]); 239 int priv_ifreq(const struct priv *, int req, struct ifreq *); 240 int priv_is_ib_cntr(const char *); 241 int priv_get_cntr_sysfs(struct priv *, const char *, uint64_t *); 242 int priv_get_num_vfs(struct priv *, uint16_t *); 243 int priv_get_mtu(struct priv *, uint16_t *); 244 int priv_set_flags(struct priv *, unsigned int, unsigned int); 245 int mlx5_dev_configure(struct rte_eth_dev *); 246 void mlx5_dev_infos_get(struct rte_eth_dev *, struct rte_eth_dev_info *); 247 const uint32_t *mlx5_dev_supported_ptypes_get(struct rte_eth_dev *dev); 248 int priv_link_update(struct priv *, int); 249 int priv_force_link_status_change(struct priv *, int); 250 int mlx5_link_update(struct rte_eth_dev *, int); 251 int mlx5_dev_set_mtu(struct rte_eth_dev *, uint16_t); 252 int mlx5_dev_get_flow_ctrl(struct rte_eth_dev *, struct rte_eth_fc_conf *); 253 int mlx5_dev_set_flow_ctrl(struct rte_eth_dev *, struct rte_eth_fc_conf *); 254 int mlx5_ibv_device_to_pci_addr(const struct ibv_device *, 255 struct rte_pci_addr *); 256 void mlx5_dev_link_status_handler(void *); 257 void mlx5_dev_interrupt_handler(void *); 258 void priv_dev_interrupt_handler_uninstall(struct priv *, struct rte_eth_dev *); 259 void priv_dev_interrupt_handler_install(struct priv *, struct rte_eth_dev *); 260 int mlx5_set_link_down(struct rte_eth_dev *dev); 261 int mlx5_set_link_up(struct rte_eth_dev *dev); 262 int mlx5_is_removed(struct rte_eth_dev *dev); 263 eth_tx_burst_t priv_select_tx_function(struct priv *, struct rte_eth_dev *); 264 eth_rx_burst_t priv_select_rx_function(struct priv *, struct rte_eth_dev *); 265 266 /* mlx5_mac.c */ 267 268 int priv_get_mac(struct priv *, uint8_t (*)[ETHER_ADDR_LEN]); 269 void mlx5_mac_addr_remove(struct rte_eth_dev *, uint32_t); 270 int mlx5_mac_addr_add(struct rte_eth_dev *, struct ether_addr *, uint32_t, 271 uint32_t); 272 void mlx5_mac_addr_set(struct rte_eth_dev *, struct ether_addr *); 273 274 /* mlx5_rss.c */ 275 276 int mlx5_rss_hash_update(struct rte_eth_dev *, struct rte_eth_rss_conf *); 277 int mlx5_rss_hash_conf_get(struct rte_eth_dev *, struct rte_eth_rss_conf *); 278 int priv_rss_reta_index_resize(struct priv *, unsigned int); 279 int mlx5_dev_rss_reta_query(struct rte_eth_dev *, 280 struct rte_eth_rss_reta_entry64 *, uint16_t); 281 int mlx5_dev_rss_reta_update(struct rte_eth_dev *, 282 struct rte_eth_rss_reta_entry64 *, uint16_t); 283 284 /* mlx5_rxmode.c */ 285 286 void mlx5_promiscuous_enable(struct rte_eth_dev *); 287 void mlx5_promiscuous_disable(struct rte_eth_dev *); 288 void mlx5_allmulticast_enable(struct rte_eth_dev *); 289 void mlx5_allmulticast_disable(struct rte_eth_dev *); 290 291 /* mlx5_stats.c */ 292 293 void priv_xstats_init(struct priv *); 294 int mlx5_stats_get(struct rte_eth_dev *, struct rte_eth_stats *); 295 void mlx5_stats_reset(struct rte_eth_dev *); 296 int mlx5_xstats_get(struct rte_eth_dev *, 297 struct rte_eth_xstat *, unsigned int); 298 void mlx5_xstats_reset(struct rte_eth_dev *); 299 int mlx5_xstats_get_names(struct rte_eth_dev *, 300 struct rte_eth_xstat_name *, unsigned int); 301 302 /* mlx5_vlan.c */ 303 304 int mlx5_vlan_filter_set(struct rte_eth_dev *, uint16_t, int); 305 int mlx5_vlan_offload_set(struct rte_eth_dev *, int); 306 void mlx5_vlan_strip_queue_set(struct rte_eth_dev *, uint16_t, int); 307 308 /* mlx5_trigger.c */ 309 310 int mlx5_dev_start(struct rte_eth_dev *); 311 void mlx5_dev_stop(struct rte_eth_dev *); 312 int priv_dev_traffic_enable(struct priv *, struct rte_eth_dev *); 313 int priv_dev_traffic_disable(struct priv *, struct rte_eth_dev *); 314 int priv_dev_traffic_restart(struct priv *, struct rte_eth_dev *); 315 int mlx5_traffic_restart(struct rte_eth_dev *); 316 317 /* mlx5_flow.c */ 318 319 int mlx5_dev_filter_ctrl(struct rte_eth_dev *, enum rte_filter_type, 320 enum rte_filter_op, void *); 321 int mlx5_flow_validate(struct rte_eth_dev *, const struct rte_flow_attr *, 322 const struct rte_flow_item [], 323 const struct rte_flow_action [], 324 struct rte_flow_error *); 325 struct rte_flow *mlx5_flow_create(struct rte_eth_dev *, 326 const struct rte_flow_attr *, 327 const struct rte_flow_item [], 328 const struct rte_flow_action [], 329 struct rte_flow_error *); 330 int mlx5_flow_destroy(struct rte_eth_dev *, struct rte_flow *, 331 struct rte_flow_error *); 332 void priv_flow_flush(struct priv *, struct mlx5_flows *); 333 int mlx5_flow_flush(struct rte_eth_dev *, struct rte_flow_error *); 334 int mlx5_flow_query(struct rte_eth_dev *, struct rte_flow *, 335 enum rte_flow_action_type, void *, 336 struct rte_flow_error *); 337 int mlx5_flow_isolate(struct rte_eth_dev *, int, struct rte_flow_error *); 338 int priv_flow_start(struct priv *, struct mlx5_flows *); 339 void priv_flow_stop(struct priv *, struct mlx5_flows *); 340 int priv_flow_verify(struct priv *); 341 int mlx5_ctrl_flow_vlan(struct rte_eth_dev *, struct rte_flow_item_eth *, 342 struct rte_flow_item_eth *, struct rte_flow_item_vlan *, 343 struct rte_flow_item_vlan *); 344 int mlx5_ctrl_flow(struct rte_eth_dev *, struct rte_flow_item_eth *, 345 struct rte_flow_item_eth *); 346 int priv_flow_create_drop_queue(struct priv *); 347 void priv_flow_delete_drop_queue(struct priv *); 348 349 /* mlx5_socket.c */ 350 351 int priv_socket_init(struct priv *priv); 352 int priv_socket_uninit(struct priv *priv); 353 void priv_socket_handle(struct priv *priv); 354 int priv_socket_connect(struct priv *priv); 355 356 /* mlx5_mr.c */ 357 358 struct mlx5_mr *priv_mr_new(struct priv *, struct rte_mempool *); 359 struct mlx5_mr *priv_mr_get(struct priv *, struct rte_mempool *); 360 int priv_mr_release(struct priv *, struct mlx5_mr *); 361 int priv_mr_verify(struct priv *); 362 363 #endif /* RTE_PMD_MLX5_H_ */ 364