1 /* SPDX-License-Identifier: BSD-3-Clause 2 * Copyright 2015 6WIND S.A. 3 * Copyright 2015 Mellanox Technologies, Ltd 4 */ 5 6 #ifndef RTE_PMD_MLX5_H_ 7 #define RTE_PMD_MLX5_H_ 8 9 #include <stddef.h> 10 #include <stdbool.h> 11 #include <stdint.h> 12 #include <limits.h> 13 #include <netinet/in.h> 14 #include <sys/queue.h> 15 16 #include <rte_pci.h> 17 #include <rte_ether.h> 18 #include <rte_ethdev_driver.h> 19 #include <rte_rwlock.h> 20 #include <rte_interrupts.h> 21 #include <rte_errno.h> 22 #include <rte_flow.h> 23 24 #include <mlx5_glue.h> 25 #include <mlx5_devx_cmds.h> 26 #include <mlx5_prm.h> 27 #include <mlx5_common_mp.h> 28 #include <mlx5_common_mr.h> 29 30 #include "mlx5_defs.h" 31 #include "mlx5_utils.h" 32 #include "mlx5_os.h" 33 #include "mlx5_autoconf.h" 34 35 enum mlx5_ipool_index { 36 #ifdef HAVE_IBV_FLOW_DV_SUPPORT 37 MLX5_IPOOL_DECAP_ENCAP = 0, /* Pool for encap/decap resource. */ 38 MLX5_IPOOL_PUSH_VLAN, /* Pool for push vlan resource. */ 39 MLX5_IPOOL_TAG, /* Pool for tag resource. */ 40 MLX5_IPOOL_PORT_ID, /* Pool for port id resource. */ 41 MLX5_IPOOL_JUMP, /* Pool for jump resource. */ 42 MLX5_IPOOL_SAMPLE, /* Pool for sample resource. */ 43 MLX5_IPOOL_DEST_ARRAY, /* Pool for destination array resource. */ 44 #endif 45 MLX5_IPOOL_MTR, /* Pool for meter resource. */ 46 MLX5_IPOOL_MCP, /* Pool for metadata resource. */ 47 MLX5_IPOOL_HRXQ, /* Pool for hrxq resource. */ 48 MLX5_IPOOL_MLX5_FLOW, /* Pool for mlx5 flow handle. */ 49 MLX5_IPOOL_RTE_FLOW, /* Pool for rte_flow. */ 50 MLX5_IPOOL_MAX, 51 }; 52 53 /* 54 * There are three reclaim memory mode supported. 55 * 0(none) means no memory reclaim. 56 * 1(light) means only PMD level reclaim. 57 * 2(aggressive) means both PMD and rdma-core level reclaim. 58 */ 59 enum mlx5_reclaim_mem_mode { 60 MLX5_RCM_NONE, /* Don't reclaim memory. */ 61 MLX5_RCM_LIGHT, /* Reclaim PMD level. */ 62 MLX5_RCM_AGGR, /* Reclaim PMD and rdma-core level. */ 63 }; 64 65 /* Device attributes used in mlx5 PMD */ 66 struct mlx5_dev_attr { 67 uint64_t device_cap_flags_ex; 68 int max_qp_wr; 69 int max_sge; 70 int max_cq; 71 int max_qp; 72 uint32_t raw_packet_caps; 73 uint32_t max_rwq_indirection_table_size; 74 uint32_t max_tso; 75 uint32_t tso_supported_qpts; 76 uint64_t flags; 77 uint64_t comp_mask; 78 uint32_t sw_parsing_offloads; 79 uint32_t min_single_stride_log_num_of_bytes; 80 uint32_t max_single_stride_log_num_of_bytes; 81 uint32_t min_single_wqe_log_num_of_strides; 82 uint32_t max_single_wqe_log_num_of_strides; 83 uint32_t stride_supported_qpts; 84 uint32_t tunnel_offloads_caps; 85 char fw_ver[64]; 86 }; 87 88 /** Data associated with devices to spawn. */ 89 struct mlx5_dev_spawn_data { 90 uint32_t ifindex; /**< Network interface index. */ 91 uint32_t max_port; /**< Device maximal port index. */ 92 uint32_t phys_port; /**< Device physical port index. */ 93 int pf_bond; /**< bonding device PF index. < 0 - no bonding */ 94 struct mlx5_switch_info info; /**< Switch information. */ 95 void *phys_dev; /**< Associated physical device. */ 96 struct rte_eth_dev *eth_dev; /**< Associated Ethernet device. */ 97 struct rte_pci_device *pci_dev; /**< Backend PCI device. */ 98 }; 99 100 /** Key string for IPC. */ 101 #define MLX5_MP_NAME "net_mlx5_mp" 102 103 104 LIST_HEAD(mlx5_dev_list, mlx5_dev_ctx_shared); 105 106 /* Shared data between primary and secondary processes. */ 107 struct mlx5_shared_data { 108 rte_spinlock_t lock; 109 /* Global spinlock for primary and secondary processes. */ 110 int init_done; /* Whether primary has done initialization. */ 111 unsigned int secondary_cnt; /* Number of secondary processes init'd. */ 112 struct mlx5_dev_list mem_event_cb_list; 113 rte_rwlock_t mem_event_rwlock; 114 }; 115 116 /* Per-process data structure, not visible to other processes. */ 117 struct mlx5_local_data { 118 int init_done; /* Whether a secondary has done initialization. */ 119 }; 120 121 extern struct mlx5_shared_data *mlx5_shared_data; 122 123 /* Dev ops structs */ 124 extern const struct eth_dev_ops mlx5_os_dev_ops; 125 extern const struct eth_dev_ops mlx5_os_dev_sec_ops; 126 extern const struct eth_dev_ops mlx5_os_dev_ops_isolate; 127 128 struct mlx5_counter_ctrl { 129 /* Name of the counter. */ 130 char dpdk_name[RTE_ETH_XSTATS_NAME_SIZE]; 131 /* Name of the counter on the device table. */ 132 char ctr_name[RTE_ETH_XSTATS_NAME_SIZE]; 133 uint32_t dev:1; /**< Nonzero for dev counters. */ 134 }; 135 136 struct mlx5_xstats_ctrl { 137 /* Number of device stats. */ 138 uint16_t stats_n; 139 /* Number of device stats identified by PMD. */ 140 uint16_t mlx5_stats_n; 141 /* Index in the device counters table. */ 142 uint16_t dev_table_idx[MLX5_MAX_XSTATS]; 143 uint64_t base[MLX5_MAX_XSTATS]; 144 uint64_t xstats[MLX5_MAX_XSTATS]; 145 uint64_t hw_stats[MLX5_MAX_XSTATS]; 146 struct mlx5_counter_ctrl info[MLX5_MAX_XSTATS]; 147 }; 148 149 struct mlx5_stats_ctrl { 150 /* Base for imissed counter. */ 151 uint64_t imissed_base; 152 uint64_t imissed; 153 }; 154 155 /* Default PMD specific parameter value. */ 156 #define MLX5_ARG_UNSET (-1) 157 158 #define MLX5_LRO_SUPPORTED(dev) \ 159 (((struct mlx5_priv *)((dev)->data->dev_private))->config.lro.supported) 160 161 /* Maximal size of coalesced segment for LRO is set in chunks of 256 Bytes. */ 162 #define MLX5_LRO_SEG_CHUNK_SIZE 256u 163 164 /* Maximal size of aggregated LRO packet. */ 165 #define MLX5_MAX_LRO_SIZE (UINT8_MAX * MLX5_LRO_SEG_CHUNK_SIZE) 166 167 /* LRO configurations structure. */ 168 struct mlx5_lro_config { 169 uint32_t supported:1; /* Whether LRO is supported. */ 170 uint32_t timeout; /* User configuration. */ 171 }; 172 173 /* 174 * Device configuration structure. 175 * 176 * Merged configuration from: 177 * 178 * - Device capabilities, 179 * - User device parameters disabled features. 180 */ 181 struct mlx5_dev_config { 182 unsigned int hw_csum:1; /* Checksum offload is supported. */ 183 unsigned int hw_vlan_strip:1; /* VLAN stripping is supported. */ 184 unsigned int hw_vlan_insert:1; /* VLAN insertion in WQE is supported. */ 185 unsigned int hw_fcs_strip:1; /* FCS stripping is supported. */ 186 unsigned int hw_padding:1; /* End alignment padding is supported. */ 187 unsigned int vf:1; /* This is a VF. */ 188 unsigned int tunnel_en:1; 189 /* Whether tunnel stateless offloads are supported. */ 190 unsigned int mpls_en:1; /* MPLS over GRE/UDP is enabled. */ 191 unsigned int cqe_comp:1; /* CQE compression is enabled. */ 192 unsigned int cqe_pad:1; /* CQE padding is enabled. */ 193 unsigned int tso:1; /* Whether TSO is supported. */ 194 unsigned int rx_vec_en:1; /* Rx vector is enabled. */ 195 unsigned int mr_ext_memseg_en:1; 196 /* Whether memseg should be extended for MR creation. */ 197 unsigned int l3_vxlan_en:1; /* Enable L3 VXLAN flow creation. */ 198 unsigned int vf_nl_en:1; /* Enable Netlink requests in VF mode. */ 199 unsigned int dv_esw_en:1; /* Enable E-Switch DV flow. */ 200 unsigned int dv_flow_en:1; /* Enable DV flow. */ 201 unsigned int dv_xmeta_en:2; /* Enable extensive flow metadata. */ 202 unsigned int lacp_by_user:1; 203 /* Enable user to manage LACP traffic. */ 204 unsigned int swp:1; /* Tx generic tunnel checksum and TSO offload. */ 205 unsigned int devx:1; /* Whether devx interface is available or not. */ 206 unsigned int dest_tir:1; /* Whether advanced DR API is available. */ 207 unsigned int reclaim_mode:2; /* Memory reclaim mode. */ 208 unsigned int rt_timestamp:1; /* realtime timestamp format. */ 209 unsigned int sys_mem_en:1; /* The default memory allocator. */ 210 unsigned int decap_en:1; /* Whether decap will be used or not. */ 211 struct { 212 unsigned int enabled:1; /* Whether MPRQ is enabled. */ 213 unsigned int stride_num_n; /* Number of strides. */ 214 unsigned int stride_size_n; /* Size of a stride. */ 215 unsigned int min_stride_size_n; /* Min size of a stride. */ 216 unsigned int max_stride_size_n; /* Max size of a stride. */ 217 unsigned int max_memcpy_len; 218 /* Maximum packet size to memcpy Rx packets. */ 219 unsigned int min_rxqs_num; 220 /* Rx queue count threshold to enable MPRQ. */ 221 } mprq; /* Configurations for Multi-Packet RQ. */ 222 int mps; /* Multi-packet send supported mode. */ 223 int dbnc; /* Skip doorbell register write barrier. */ 224 unsigned int flow_prio; /* Number of flow priorities. */ 225 enum modify_reg flow_mreg_c[MLX5_MREG_C_NUM]; 226 /* Availibility of mreg_c's. */ 227 unsigned int tso_max_payload_sz; /* Maximum TCP payload for TSO. */ 228 unsigned int ind_table_max_size; /* Maximum indirection table size. */ 229 unsigned int max_dump_files_num; /* Maximum dump files per queue. */ 230 unsigned int log_hp_size; /* Single hairpin queue data size in total. */ 231 int txqs_inline; /* Queue number threshold for inlining. */ 232 int txq_inline_min; /* Minimal amount of data bytes to inline. */ 233 int txq_inline_max; /* Max packet size for inlining with SEND. */ 234 int txq_inline_mpw; /* Max packet size for inlining with eMPW. */ 235 int tx_pp; /* Timestamp scheduling granularity in nanoseconds. */ 236 int tx_skew; /* Tx scheduling skew between WQE and data on wire. */ 237 struct mlx5_hca_attr hca_attr; /* HCA attributes. */ 238 struct mlx5_lro_config lro; /* LRO configuration. */ 239 }; 240 241 242 /** 243 * Type of object being allocated. 244 */ 245 enum mlx5_verbs_alloc_type { 246 MLX5_VERBS_ALLOC_TYPE_NONE, 247 MLX5_VERBS_ALLOC_TYPE_TX_QUEUE, 248 MLX5_VERBS_ALLOC_TYPE_RX_QUEUE, 249 }; 250 251 /* Structure for VF VLAN workaround. */ 252 struct mlx5_vf_vlan { 253 uint32_t tag:12; 254 uint32_t created:1; 255 }; 256 257 /** 258 * Verbs allocator needs a context to know in the callback which kind of 259 * resources it is allocating. 260 */ 261 struct mlx5_verbs_alloc_ctx { 262 enum mlx5_verbs_alloc_type type; /* Kind of object being allocated. */ 263 const void *obj; /* Pointer to the DPDK object. */ 264 }; 265 266 /* Flow drop context necessary due to Verbs API. */ 267 struct mlx5_drop { 268 struct mlx5_hrxq *hrxq; /* Hash Rx queue queue. */ 269 struct mlx5_rxq_obj *rxq; /* Rx queue object. */ 270 }; 271 272 #define MLX5_COUNTERS_PER_POOL 512 273 #define MLX5_MAX_PENDING_QUERIES 4 274 #define MLX5_CNT_CONTAINER_RESIZE 64 275 #define MLX5_CNT_AGE_OFFSET 0x80000000 276 #define CNT_SIZE (sizeof(struct mlx5_flow_counter)) 277 #define CNTEXT_SIZE (sizeof(struct mlx5_flow_counter_ext)) 278 #define AGE_SIZE (sizeof(struct mlx5_age_param)) 279 #define MLX5_AGING_TIME_DELAY 7 280 #define CNT_POOL_TYPE_EXT (1 << 0) 281 #define CNT_POOL_TYPE_AGE (1 << 1) 282 #define IS_EXT_POOL(pool) (((pool)->type) & CNT_POOL_TYPE_EXT) 283 #define IS_AGE_POOL(pool) (((pool)->type) & CNT_POOL_TYPE_AGE) 284 #define MLX_CNT_IS_AGE(counter) ((counter) & MLX5_CNT_AGE_OFFSET ? 1 : 0) 285 #define MLX5_CNT_LEN(pool) \ 286 (CNT_SIZE + \ 287 (IS_AGE_POOL(pool) ? AGE_SIZE : 0) + \ 288 (IS_EXT_POOL(pool) ? CNTEXT_SIZE : 0)) 289 #define MLX5_POOL_GET_CNT(pool, index) \ 290 ((struct mlx5_flow_counter *) \ 291 ((uint8_t *)((pool) + 1) + (index) * (MLX5_CNT_LEN(pool)))) 292 #define MLX5_CNT_ARRAY_IDX(pool, cnt) \ 293 ((int)(((uint8_t *)(cnt) - (uint8_t *)((pool) + 1)) / \ 294 MLX5_CNT_LEN(pool))) 295 /* 296 * The pool index and offset of counter in the pool array makes up the 297 * counter index. In case the counter is from pool 0 and offset 0, it 298 * should plus 1 to avoid index 0, since 0 means invalid counter index 299 * currently. 300 */ 301 #define MLX5_MAKE_CNT_IDX(pi, offset) \ 302 ((pi) * MLX5_COUNTERS_PER_POOL + (offset) + 1) 303 #define MLX5_CNT_TO_CNT_EXT(pool, cnt) \ 304 ((struct mlx5_flow_counter_ext *)\ 305 ((uint8_t *)((cnt) + 1) + \ 306 (IS_AGE_POOL(pool) ? AGE_SIZE : 0))) 307 #define MLX5_GET_POOL_CNT_EXT(pool, offset) \ 308 MLX5_CNT_TO_CNT_EXT(pool, MLX5_POOL_GET_CNT((pool), (offset))) 309 #define MLX5_CNT_TO_AGE(cnt) \ 310 ((struct mlx5_age_param *)((cnt) + 1)) 311 /* 312 * The maximum single counter is 0x800000 as MLX5_CNT_BATCH_OFFSET 313 * defines. The pool size is 512, pool index should never reach 314 * INT16_MAX. 315 */ 316 #define POOL_IDX_INVALID UINT16_MAX 317 318 struct mlx5_flow_counter_pool; 319 320 /*age status*/ 321 enum { 322 AGE_FREE, /* Initialized state. */ 323 AGE_CANDIDATE, /* Counter assigned to flows. */ 324 AGE_TMOUT, /* Timeout, wait for rte_flow_get_aged_flows and destroy. */ 325 }; 326 327 #define MLX5_CNT_CONTAINER(sh, batch, age) (&(sh)->cmng.ccont \ 328 [(batch) * 2 + (age)]) 329 330 enum { 331 MLX5_CCONT_TYPE_SINGLE, 332 MLX5_CCONT_TYPE_SINGLE_FOR_AGE, 333 MLX5_CCONT_TYPE_BATCH, 334 MLX5_CCONT_TYPE_BATCH_FOR_AGE, 335 MLX5_CCONT_TYPE_MAX, 336 }; 337 338 /* Counter age parameter. */ 339 struct mlx5_age_param { 340 rte_atomic16_t state; /**< Age state. */ 341 uint16_t port_id; /**< Port id of the counter. */ 342 uint32_t timeout:15; /**< Age timeout in unit of 0.1sec. */ 343 uint32_t expire:16; /**< Expire time(0.1sec) in the future. */ 344 void *context; /**< Flow counter age context. */ 345 }; 346 347 struct flow_counter_stats { 348 uint64_t hits; 349 uint64_t bytes; 350 }; 351 352 struct mlx5_flow_counter_pool; 353 /* Generic counters information. */ 354 struct mlx5_flow_counter { 355 TAILQ_ENTRY(mlx5_flow_counter) next; 356 /**< Pointer to the next flow counter structure. */ 357 union { 358 uint64_t hits; /**< Reset value of hits packets. */ 359 struct mlx5_flow_counter_pool *pool; /**< Counter pool. */ 360 }; 361 uint64_t bytes; /**< Reset value of bytes. */ 362 void *action; /**< Pointer to the dv action. */ 363 }; 364 365 /* Extend counters information for none batch counters. */ 366 struct mlx5_flow_counter_ext { 367 uint32_t shared:1; /**< Share counter ID with other flow rules. */ 368 uint32_t batch: 1; 369 uint32_t skipped:1; /* This counter is skipped or not. */ 370 /**< Whether the counter was allocated by batch command. */ 371 uint32_t ref_cnt:29; /**< Reference counter. */ 372 uint32_t id; /**< User counter ID. */ 373 union { /**< Holds the counters for the rule. */ 374 #if defined(HAVE_IBV_DEVICE_COUNTERS_SET_V42) 375 struct ibv_counter_set *cs; 376 #elif defined(HAVE_IBV_DEVICE_COUNTERS_SET_V45) 377 struct ibv_counters *cs; 378 #endif 379 struct mlx5_devx_obj *dcs; /**< Counter Devx object. */ 380 }; 381 }; 382 383 TAILQ_HEAD(mlx5_counters, mlx5_flow_counter); 384 385 /* Generic counter pool structure - query is in pool resolution. */ 386 struct mlx5_flow_counter_pool { 387 TAILQ_ENTRY(mlx5_flow_counter_pool) next; 388 struct mlx5_counters counters[2]; /* Free counter list. */ 389 union { 390 struct mlx5_devx_obj *min_dcs; 391 rte_atomic64_t a64_dcs; 392 }; 393 /* The devx object of the minimum counter ID. */ 394 uint32_t index:28; /* Pool index in container. */ 395 uint32_t type:2; /* Memory type behind the counter array. */ 396 uint32_t skip_cnt:1; /* Pool contains skipped counter. */ 397 volatile uint32_t query_gen:1; /* Query round. */ 398 rte_spinlock_t sl; /* The pool lock. */ 399 struct mlx5_counter_stats_raw *raw; 400 struct mlx5_counter_stats_raw *raw_hw; /* The raw on HW working. */ 401 }; 402 403 struct mlx5_counter_stats_raw; 404 405 /* Memory management structure for group of counter statistics raws. */ 406 struct mlx5_counter_stats_mem_mng { 407 LIST_ENTRY(mlx5_counter_stats_mem_mng) next; 408 struct mlx5_counter_stats_raw *raws; 409 struct mlx5_devx_obj *dm; 410 void *umem; 411 }; 412 413 /* Raw memory structure for the counter statistics values of a pool. */ 414 struct mlx5_counter_stats_raw { 415 LIST_ENTRY(mlx5_counter_stats_raw) next; 416 int min_dcs_id; 417 struct mlx5_counter_stats_mem_mng *mem_mng; 418 volatile struct flow_counter_stats *data; 419 }; 420 421 TAILQ_HEAD(mlx5_counter_pools, mlx5_flow_counter_pool); 422 423 /* Container structure for counter pools. */ 424 struct mlx5_pools_container { 425 rte_atomic16_t n_valid; /* Number of valid pools. */ 426 uint16_t n; /* Number of pools. */ 427 uint16_t last_pool_idx; /* Last used pool index */ 428 int min_id; /* The minimum counter ID in the pools. */ 429 int max_id; /* The maximum counter ID in the pools. */ 430 rte_spinlock_t resize_sl; /* The resize lock. */ 431 rte_spinlock_t csl; /* The counter free list lock. */ 432 struct mlx5_counters counters; /* Free counter list. */ 433 struct mlx5_counter_pools pool_list; /* Counter pool list. */ 434 struct mlx5_flow_counter_pool **pools; /* Counter pool array. */ 435 struct mlx5_counter_stats_mem_mng *mem_mng; 436 /* Hold the memory management for the next allocated pools raws. */ 437 }; 438 439 /* Counter global management structure. */ 440 struct mlx5_flow_counter_mng { 441 struct mlx5_pools_container ccont[MLX5_CCONT_TYPE_MAX]; 442 struct mlx5_counters flow_counters; /* Legacy flow counter list. */ 443 uint8_t pending_queries; 444 uint8_t batch; 445 uint16_t pool_index; 446 uint8_t age; 447 uint8_t query_thread_on; 448 LIST_HEAD(mem_mngs, mlx5_counter_stats_mem_mng) mem_mngs; 449 LIST_HEAD(stat_raws, mlx5_counter_stats_raw) free_stat_raws; 450 }; 451 452 /* Default miss action resource structure. */ 453 struct mlx5_flow_default_miss_resource { 454 void *action; /* Pointer to the rdma-core action. */ 455 rte_atomic32_t refcnt; /* Default miss action reference counter. */ 456 }; 457 458 #define MLX5_AGE_EVENT_NEW 1 459 #define MLX5_AGE_TRIGGER 2 460 #define MLX5_AGE_SET(age_info, BIT) \ 461 ((age_info)->flags |= (1 << (BIT))) 462 #define MLX5_AGE_GET(age_info, BIT) \ 463 ((age_info)->flags & (1 << (BIT))) 464 #define GET_PORT_AGE_INFO(priv) \ 465 (&((priv)->sh->port[(priv)->dev_port - 1].age_info)) 466 467 /* Aging information for per port. */ 468 struct mlx5_age_info { 469 uint8_t flags; /*Indicate if is new event or need be trigered*/ 470 struct mlx5_counters aged_counters; /* Aged flow counter list. */ 471 rte_spinlock_t aged_sl; /* Aged flow counter list lock. */ 472 }; 473 474 /* Per port data of shared IB device. */ 475 struct mlx5_dev_shared_port { 476 uint32_t ih_port_id; 477 uint32_t devx_ih_port_id; 478 /* 479 * Interrupt handler port_id. Used by shared interrupt 480 * handler to find the corresponding rte_eth device 481 * by IB port index. If value is equal or greater 482 * RTE_MAX_ETHPORTS it means there is no subhandler 483 * installed for specified IB port index. 484 */ 485 struct mlx5_age_info age_info; 486 /* Aging information for per port. */ 487 }; 488 489 /* Table key of the hash organization. */ 490 union mlx5_flow_tbl_key { 491 struct { 492 /* Table ID should be at the lowest address. */ 493 uint32_t table_id; /**< ID of the table. */ 494 uint16_t reserved; /**< must be zero for comparison. */ 495 uint8_t domain; /**< 1 - FDB, 0 - NIC TX/RX. */ 496 uint8_t direction; /**< 1 - egress, 0 - ingress. */ 497 }; 498 uint64_t v64; /**< full 64bits value of key */ 499 }; 500 501 /* Table structure. */ 502 struct mlx5_flow_tbl_resource { 503 void *obj; /**< Pointer to DR table object. */ 504 rte_atomic32_t refcnt; /**< Reference counter. */ 505 }; 506 507 #define MLX5_MAX_TABLES UINT16_MAX 508 #define MLX5_HAIRPIN_TX_TABLE (UINT16_MAX - 1) 509 /* Reserve the last two tables for metadata register copy. */ 510 #define MLX5_FLOW_MREG_ACT_TABLE_GROUP (MLX5_MAX_TABLES - 1) 511 #define MLX5_FLOW_MREG_CP_TABLE_GROUP (MLX5_MAX_TABLES - 2) 512 /* Tables for metering splits should be added here. */ 513 #define MLX5_MAX_TABLES_EXTERNAL (MLX5_MAX_TABLES - 3) 514 #define MLX5_FLOW_TABLE_LEVEL_METER (MLX5_MAX_TABLES - 4) 515 #define MLX5_FLOW_TABLE_LEVEL_SUFFIX (MLX5_MAX_TABLES - 3) 516 #define MLX5_MAX_TABLES_FDB UINT16_MAX 517 #define MLX5_FLOW_TABLE_FACTOR 10 518 519 /* ID generation structure. */ 520 struct mlx5_flow_id_pool { 521 uint32_t *free_arr; /**< Pointer to the a array of free values. */ 522 uint32_t base_index; 523 /**< The next index that can be used without any free elements. */ 524 uint32_t *curr; /**< Pointer to the index to pop. */ 525 uint32_t *last; /**< Pointer to the last element in the empty arrray. */ 526 uint32_t max_id; /**< Maximum id can be allocated from the pool. */ 527 }; 528 529 /* Tx pacing queue structure - for Clock and Rearm queues. */ 530 struct mlx5_txpp_wq { 531 /* Completion Queue related data.*/ 532 struct mlx5_devx_obj *cq; 533 void *cq_umem; 534 union { 535 volatile void *cq_buf; 536 volatile struct mlx5_cqe *cqes; 537 }; 538 volatile uint32_t *cq_dbrec; 539 uint32_t cq_ci:24; 540 uint32_t arm_sn:2; 541 /* Send Queue related data.*/ 542 struct mlx5_devx_obj *sq; 543 void *sq_umem; 544 union { 545 volatile void *sq_buf; 546 volatile struct mlx5_wqe *wqes; 547 }; 548 uint16_t sq_size; /* Number of WQEs in the queue. */ 549 uint16_t sq_ci; /* Next WQE to execute. */ 550 volatile uint32_t *sq_dbrec; 551 }; 552 553 /* Tx packet pacing internal timestamp. */ 554 struct mlx5_txpp_ts { 555 rte_atomic64_t ci_ts; 556 rte_atomic64_t ts; 557 }; 558 559 /* Tx packet pacing structure. */ 560 struct mlx5_dev_txpp { 561 pthread_mutex_t mutex; /* Pacing create/destroy mutex. */ 562 uint32_t refcnt; /* Pacing reference counter. */ 563 uint32_t freq; /* Timestamp frequency, Hz. */ 564 uint32_t tick; /* Completion tick duration in nanoseconds. */ 565 uint32_t test; /* Packet pacing test mode. */ 566 int32_t skew; /* Scheduling skew. */ 567 struct rte_intr_handle intr_handle; /* Periodic interrupt. */ 568 void *echan; /* Event Channel. */ 569 struct mlx5_txpp_wq clock_queue; /* Clock Queue. */ 570 struct mlx5_txpp_wq rearm_queue; /* Clock Queue. */ 571 void *pp; /* Packet pacing context. */ 572 uint16_t pp_id; /* Packet pacing context index. */ 573 uint16_t ts_n; /* Number of captured timestamps. */ 574 uint16_t ts_p; /* Pointer to statisticks timestamp. */ 575 struct mlx5_txpp_ts *tsa; /* Timestamps sliding window stats. */ 576 struct mlx5_txpp_ts ts; /* Cached completion id/timestamp. */ 577 uint32_t sync_lost:1; /* ci/timestamp synchronization lost. */ 578 /* Statistics counters. */ 579 rte_atomic32_t err_miss_int; /* Missed service interrupt. */ 580 rte_atomic32_t err_rearm_queue; /* Rearm Queue errors. */ 581 rte_atomic32_t err_clock_queue; /* Clock Queue errors. */ 582 rte_atomic32_t err_ts_past; /* Timestamp in the past. */ 583 rte_atomic32_t err_ts_future; /* Timestamp in the distant future. */ 584 }; 585 586 /* Supported flex parser profile ID. */ 587 enum mlx5_flex_parser_profile_id { 588 MLX5_FLEX_PARSER_ECPRI_0 = 0, 589 MLX5_FLEX_PARSER_MAX = 8, 590 }; 591 592 /* Sample ID information of flex parser structure. */ 593 struct mlx5_flex_parser_profiles { 594 uint32_t num; /* Actual number of samples. */ 595 uint32_t ids[8]; /* Sample IDs for this profile. */ 596 uint8_t offset[8]; /* Bytes offset of each parser. */ 597 void *obj; /* Flex parser node object. */ 598 }; 599 600 /* 601 * Shared Infiniband device context for Master/Representors 602 * which belong to same IB device with multiple IB ports. 603 **/ 604 struct mlx5_dev_ctx_shared { 605 LIST_ENTRY(mlx5_dev_ctx_shared) next; 606 uint32_t refcnt; 607 uint32_t devx:1; /* Opened with DV. */ 608 uint32_t eqn; /* Event Queue number. */ 609 uint32_t max_port; /* Maximal IB device port index. */ 610 void *ctx; /* Verbs/DV/DevX context. */ 611 void *pd; /* Protection Domain. */ 612 uint32_t pdn; /* Protection Domain number. */ 613 uint32_t tdn; /* Transport Domain number. */ 614 char ibdev_name[DEV_SYSFS_NAME_MAX]; /* SYSFS dev name. */ 615 char ibdev_path[DEV_SYSFS_PATH_MAX]; /* SYSFS dev path for secondary */ 616 struct mlx5_dev_attr device_attr; /* Device properties. */ 617 int numa_node; /* Numa node of backing physical device. */ 618 LIST_ENTRY(mlx5_dev_ctx_shared) mem_event_cb; 619 /**< Called by memory event callback. */ 620 struct mlx5_mr_share_cache share_cache; 621 /* Packet pacing related structure. */ 622 struct mlx5_dev_txpp txpp; 623 /* Shared DV/DR flow data section. */ 624 pthread_mutex_t dv_mutex; /* DV context mutex. */ 625 uint32_t dv_meta_mask; /* flow META metadata supported mask. */ 626 uint32_t dv_mark_mask; /* flow MARK metadata supported mask. */ 627 uint32_t dv_regc0_mask; /* available bits of metatada reg_c[0]. */ 628 uint32_t dv_refcnt; /* DV/DR data reference counter. */ 629 void *fdb_domain; /* FDB Direct Rules name space handle. */ 630 void *rx_domain; /* RX Direct Rules name space handle. */ 631 void *tx_domain; /* TX Direct Rules name space handle. */ 632 #ifndef RTE_ARCH_64 633 rte_spinlock_t uar_lock_cq; /* CQs share a common distinct UAR */ 634 rte_spinlock_t uar_lock[MLX5_UAR_PAGE_NUM_MAX]; 635 /* UAR same-page access control required in 32bit implementations. */ 636 #endif 637 struct mlx5_hlist *flow_tbls; 638 /* Direct Rules tables for FDB, NIC TX+RX */ 639 void *esw_drop_action; /* Pointer to DR E-Switch drop action. */ 640 void *pop_vlan_action; /* Pointer to DR pop VLAN action. */ 641 struct mlx5_hlist *encaps_decaps; /* Encap/decap action hash list. */ 642 struct mlx5_hlist *modify_cmds; 643 struct mlx5_hlist *tag_table; 644 uint32_t port_id_action_list; /* List of port ID actions. */ 645 uint32_t push_vlan_action_list; /* List of push VLAN actions. */ 646 uint32_t sample_action_list; /* List of sample actions. */ 647 uint32_t dest_array_list; /* List of destination array actions. */ 648 struct mlx5_flow_counter_mng cmng; /* Counters management structure. */ 649 struct mlx5_flow_default_miss_resource default_miss; 650 /* Default miss action resource structure. */ 651 struct mlx5_indexed_pool *ipool[MLX5_IPOOL_MAX]; 652 /* Memory Pool for mlx5 flow resources. */ 653 struct mlx5_l3t_tbl *cnt_id_tbl; /* Shared counter lookup table. */ 654 /* Shared interrupt handler section. */ 655 struct rte_intr_handle intr_handle; /* Interrupt handler for device. */ 656 struct rte_intr_handle intr_handle_devx; /* DEVX interrupt handler. */ 657 void *devx_comp; /* DEVX async comp obj. */ 658 struct mlx5_devx_obj *tis; /* TIS object. */ 659 struct mlx5_devx_obj *td; /* Transport domain. */ 660 struct mlx5_flow_id_pool *flow_id_pool; /* Flow ID pool. */ 661 void *tx_uar; /* Tx/packet pacing shared UAR. */ 662 struct mlx5_flex_parser_profiles fp[MLX5_FLEX_PARSER_MAX]; 663 /* Flex parser profiles information. */ 664 void *devx_rx_uar; /* DevX UAR for Rx. */ 665 struct mlx5_dev_shared_port port[]; /* per device port data array. */ 666 }; 667 668 /* Per-process private structure. */ 669 struct mlx5_proc_priv { 670 size_t uar_table_sz; 671 /* Size of UAR register table. */ 672 void *uar_table[]; 673 /* Table of UAR registers for each process. */ 674 }; 675 676 /* MTR profile list. */ 677 TAILQ_HEAD(mlx5_mtr_profiles, mlx5_flow_meter_profile); 678 /* MTR list. */ 679 TAILQ_HEAD(mlx5_flow_meters, mlx5_flow_meter); 680 681 #define MLX5_PROC_PRIV(port_id) \ 682 ((struct mlx5_proc_priv *)rte_eth_devices[port_id].process_private) 683 684 /* Verbs/DevX Rx queue elements. */ 685 struct mlx5_rxq_obj { 686 LIST_ENTRY(mlx5_rxq_obj) next; /* Pointer to the next element. */ 687 struct mlx5_rxq_ctrl *rxq_ctrl; /* Back pointer to parent. */ 688 int fd; /* File descriptor for event channel */ 689 RTE_STD_C11 690 union { 691 struct { 692 void *wq; /* Work Queue. */ 693 void *ibv_cq; /* Completion Queue. */ 694 void *ibv_channel; 695 }; 696 struct { 697 struct mlx5_devx_obj *rq; /* DevX Rx Queue object. */ 698 struct mlx5_devx_obj *devx_cq; /* DevX CQ object. */ 699 void *devx_channel; 700 }; 701 }; 702 }; 703 704 /* Indirection table. */ 705 struct mlx5_ind_table_obj { 706 LIST_ENTRY(mlx5_ind_table_obj) next; /* Pointer to the next element. */ 707 rte_atomic32_t refcnt; /* Reference counter. */ 708 RTE_STD_C11 709 union { 710 void *ind_table; /**< Indirection table. */ 711 struct mlx5_devx_obj *rqt; /* DevX RQT object. */ 712 }; 713 uint32_t queues_n; /**< Number of queues in the list. */ 714 uint16_t queues[]; /**< Queue list. */ 715 }; 716 717 /* Hash Rx queue. */ 718 struct mlx5_hrxq { 719 ILIST_ENTRY(uint32_t)next; /* Index to the next element. */ 720 rte_atomic32_t refcnt; /* Reference counter. */ 721 struct mlx5_ind_table_obj *ind_table; /* Indirection table. */ 722 RTE_STD_C11 723 union { 724 void *qp; /* Verbs queue pair. */ 725 struct mlx5_devx_obj *tir; /* DevX TIR object. */ 726 }; 727 #ifdef HAVE_IBV_FLOW_DV_SUPPORT 728 void *action; /* DV QP action pointer. */ 729 #endif 730 uint64_t hash_fields; /* Verbs Hash fields. */ 731 uint32_t rss_key_len; /* Hash key length in bytes. */ 732 uint8_t rss_key[]; /* Hash key. */ 733 }; 734 735 /* Verbs/DevX Tx queue elements. */ 736 struct mlx5_txq_obj { 737 LIST_ENTRY(mlx5_txq_obj) next; /* Pointer to the next element. */ 738 struct mlx5_txq_ctrl *txq_ctrl; /* Pointer to the control queue. */ 739 RTE_STD_C11 740 union { 741 struct { 742 void *cq; /* Completion Queue. */ 743 void *qp; /* Queue Pair. */ 744 }; 745 struct { 746 struct mlx5_devx_obj *sq; 747 /* DevX object for Sx queue. */ 748 struct mlx5_devx_obj *tis; /* The TIS object. */ 749 }; 750 struct { 751 struct rte_eth_dev *dev; 752 struct mlx5_devx_obj *cq_devx; 753 void *cq_umem; 754 void *cq_buf; 755 int64_t cq_dbrec_offset; 756 struct mlx5_devx_dbr_page *cq_dbrec_page; 757 struct mlx5_devx_obj *sq_devx; 758 void *sq_umem; 759 void *sq_buf; 760 int64_t sq_dbrec_offset; 761 struct mlx5_devx_dbr_page *sq_dbrec_page; 762 }; 763 }; 764 }; 765 766 enum mlx5_rxq_modify_type { 767 MLX5_RXQ_MOD_ERR2RST, /* modify state from error to reset. */ 768 MLX5_RXQ_MOD_RST2RDY, /* modify state from reset to ready. */ 769 MLX5_RXQ_MOD_RDY2ERR, /* modify state from ready to error. */ 770 MLX5_RXQ_MOD_RDY2RST, /* modify state from ready to reset. */ 771 }; 772 773 enum mlx5_txq_modify_type { 774 MLX5_TXQ_MOD_RDY2RDY, /* modify state from ready to ready. */ 775 MLX5_TXQ_MOD_RST2RDY, /* modify state from reset to ready. */ 776 MLX5_TXQ_MOD_RDY2RST, /* modify state from ready to reset. */ 777 MLX5_TXQ_MOD_ERR2RDY, /* modify state from error to ready. */ 778 }; 779 780 /* HW objects operations structure. */ 781 struct mlx5_obj_ops { 782 int (*rxq_obj_modify_vlan_strip)(struct mlx5_rxq_obj *rxq_obj, int on); 783 int (*rxq_obj_new)(struct rte_eth_dev *dev, uint16_t idx); 784 int (*rxq_event_get)(struct mlx5_rxq_obj *rxq_obj); 785 int (*rxq_obj_modify)(struct mlx5_rxq_obj *rxq_obj, uint8_t type); 786 void (*rxq_obj_release)(struct mlx5_rxq_obj *rxq_obj); 787 int (*ind_table_new)(struct rte_eth_dev *dev, const unsigned int log_n, 788 struct mlx5_ind_table_obj *ind_tbl); 789 void (*ind_table_destroy)(struct mlx5_ind_table_obj *ind_tbl); 790 int (*hrxq_new)(struct rte_eth_dev *dev, struct mlx5_hrxq *hrxq, 791 int tunnel __rte_unused); 792 void (*hrxq_destroy)(struct mlx5_hrxq *hrxq); 793 int (*drop_action_create)(struct rte_eth_dev *dev); 794 void (*drop_action_destroy)(struct rte_eth_dev *dev); 795 int (*txq_obj_new)(struct rte_eth_dev *dev, uint16_t idx); 796 int (*txq_obj_modify)(struct mlx5_txq_obj *obj, 797 enum mlx5_txq_modify_type type, uint8_t dev_port); 798 void (*txq_obj_release)(struct mlx5_txq_obj *txq_obj); 799 }; 800 801 struct mlx5_priv { 802 struct rte_eth_dev_data *dev_data; /* Pointer to device data. */ 803 struct mlx5_dev_ctx_shared *sh; /* Shared device context. */ 804 uint32_t dev_port; /* Device port number. */ 805 struct rte_pci_device *pci_dev; /* Backend PCI device. */ 806 struct rte_ether_addr mac[MLX5_MAX_MAC_ADDRESSES]; /* MAC addresses. */ 807 BITFIELD_DECLARE(mac_own, uint64_t, MLX5_MAX_MAC_ADDRESSES); 808 /* Bit-field of MAC addresses owned by the PMD. */ 809 uint16_t vlan_filter[MLX5_MAX_VLAN_IDS]; /* VLAN filters table. */ 810 unsigned int vlan_filter_n; /* Number of configured VLAN filters. */ 811 /* Device properties. */ 812 uint16_t mtu; /* Configured MTU. */ 813 unsigned int isolated:1; /* Whether isolated mode is enabled. */ 814 unsigned int representor:1; /* Device is a port representor. */ 815 unsigned int master:1; /* Device is a E-Switch master. */ 816 unsigned int dr_shared:1; /* DV/DR data is shared. */ 817 unsigned int txpp_en:1; /* Tx packet pacing enabled. */ 818 unsigned int counter_fallback:1; /* Use counter fallback management. */ 819 unsigned int mtr_en:1; /* Whether support meter. */ 820 unsigned int mtr_reg_share:1; /* Whether support meter REG_C share. */ 821 unsigned int sampler_en:1; /* Whether support sampler. */ 822 uint16_t domain_id; /* Switch domain identifier. */ 823 uint16_t vport_id; /* Associated VF vport index (if any). */ 824 uint32_t vport_meta_tag; /* Used for vport index match ove VF LAG. */ 825 uint32_t vport_meta_mask; /* Used for vport index field match mask. */ 826 int32_t representor_id; /* Port representor identifier. */ 827 int32_t pf_bond; /* >=0 means PF index in bonding configuration. */ 828 unsigned int if_index; /* Associated kernel network device index. */ 829 uint32_t bond_ifindex; /**< Bond interface index. */ 830 char bond_name[IF_NAMESIZE]; /**< Bond interface name. */ 831 /* RX/TX queues. */ 832 unsigned int rxqs_n; /* RX queues array size. */ 833 unsigned int txqs_n; /* TX queues array size. */ 834 struct mlx5_rxq_data *(*rxqs)[]; /* RX queues. */ 835 struct mlx5_txq_data *(*txqs)[]; /* TX queues. */ 836 struct rte_mempool *mprq_mp; /* Mempool for Multi-Packet RQ. */ 837 struct rte_eth_rss_conf rss_conf; /* RSS configuration. */ 838 unsigned int (*reta_idx)[]; /* RETA index table. */ 839 unsigned int reta_idx_n; /* RETA index size. */ 840 struct mlx5_drop drop_queue; /* Flow drop queues. */ 841 uint32_t flows; /* RTE Flow rules. */ 842 uint32_t ctrl_flows; /* Control flow rules. */ 843 void *inter_flows; /* Intermediate resources for flow creation. */ 844 void *rss_desc; /* Intermediate rss description resources. */ 845 int flow_idx; /* Intermediate device flow index. */ 846 int flow_nested_idx; /* Intermediate device flow index, nested. */ 847 struct mlx5_obj_ops obj_ops; /* HW objects operations. */ 848 LIST_HEAD(rxq, mlx5_rxq_ctrl) rxqsctrl; /* DPDK Rx queues. */ 849 LIST_HEAD(rxqobj, mlx5_rxq_obj) rxqsobj; /* Verbs/DevX Rx queues. */ 850 uint32_t hrxqs; /* Verbs Hash Rx queues. */ 851 LIST_HEAD(txq, mlx5_txq_ctrl) txqsctrl; /* DPDK Tx queues. */ 852 LIST_HEAD(txqobj, mlx5_txq_obj) txqsobj; /* Verbs/DevX Tx queues. */ 853 /* Indirection tables. */ 854 LIST_HEAD(ind_tables, mlx5_ind_table_obj) ind_tbls; 855 /* Pointer to next element. */ 856 rte_atomic32_t refcnt; /**< Reference counter. */ 857 /**< Verbs modify header action object. */ 858 uint8_t ft_type; /**< Flow table type, Rx or Tx. */ 859 uint8_t max_lro_msg_size; 860 /* Tags resources cache. */ 861 uint32_t link_speed_capa; /* Link speed capabilities. */ 862 struct mlx5_xstats_ctrl xstats_ctrl; /* Extended stats control. */ 863 struct mlx5_stats_ctrl stats_ctrl; /* Stats control. */ 864 struct mlx5_dev_config config; /* Device configuration. */ 865 struct mlx5_verbs_alloc_ctx verbs_alloc_ctx; 866 /* Context for Verbs allocator. */ 867 int nl_socket_rdma; /* Netlink socket (NETLINK_RDMA). */ 868 int nl_socket_route; /* Netlink socket (NETLINK_ROUTE). */ 869 struct mlx5_dbr_page_list dbrpgs; /* Door-bell pages. */ 870 struct mlx5_nl_vlan_vmwa_context *vmwa_context; /* VLAN WA context. */ 871 struct mlx5_flow_id_pool *qrss_id_pool; 872 struct mlx5_hlist *mreg_cp_tbl; 873 /* Hash table of Rx metadata register copy table. */ 874 uint8_t mtr_sfx_reg; /* Meter prefix-suffix flow match REG_C. */ 875 uint8_t mtr_color_reg; /* Meter color match REG_C. */ 876 struct mlx5_mtr_profiles flow_meter_profiles; /* MTR profile list. */ 877 struct mlx5_flow_meters flow_meters; /* MTR list. */ 878 uint8_t skip_default_rss_reta; /* Skip configuration of default reta. */ 879 uint8_t fdb_def_rule; /* Whether fdb jump to table 1 is configured. */ 880 struct mlx5_mp_id mp_id; /* ID of a multi-process process */ 881 LIST_HEAD(fdir, mlx5_fdir_flow) fdir_flows; /* fdir flows. */ 882 }; 883 884 #define PORT_ID(priv) ((priv)->dev_data->port_id) 885 #define ETH_DEV(priv) (&rte_eth_devices[PORT_ID(priv)]) 886 887 /* mlx5.c */ 888 889 int mlx5_getenv_int(const char *); 890 int mlx5_proc_priv_init(struct rte_eth_dev *dev); 891 int mlx5_udp_tunnel_port_add(struct rte_eth_dev *dev, 892 struct rte_eth_udp_tunnel *udp_tunnel); 893 uint16_t mlx5_eth_find_next(uint16_t port_id, struct rte_pci_device *pci_dev); 894 int mlx5_dev_close(struct rte_eth_dev *dev); 895 896 /* Macro to iterate over all valid ports for mlx5 driver. */ 897 #define MLX5_ETH_FOREACH_DEV(port_id, pci_dev) \ 898 for (port_id = mlx5_eth_find_next(0, pci_dev); \ 899 port_id < RTE_MAX_ETHPORTS; \ 900 port_id = mlx5_eth_find_next(port_id + 1, pci_dev)) 901 int mlx5_args(struct mlx5_dev_config *config, struct rte_devargs *devargs); 902 struct mlx5_dev_ctx_shared * 903 mlx5_alloc_shared_dev_ctx(const struct mlx5_dev_spawn_data *spawn, 904 const struct mlx5_dev_config *config); 905 void mlx5_free_shared_dev_ctx(struct mlx5_dev_ctx_shared *sh); 906 void mlx5_free_table_hash_list(struct mlx5_priv *priv); 907 int mlx5_alloc_table_hash_list(struct mlx5_priv *priv); 908 void mlx5_set_min_inline(struct mlx5_dev_spawn_data *spawn, 909 struct mlx5_dev_config *config); 910 void mlx5_set_metadata_mask(struct rte_eth_dev *dev); 911 int mlx5_dev_check_sibling_config(struct mlx5_priv *priv, 912 struct mlx5_dev_config *config); 913 int mlx5_dev_configure(struct rte_eth_dev *dev); 914 int mlx5_dev_infos_get(struct rte_eth_dev *dev, struct rte_eth_dev_info *info); 915 int mlx5_fw_version_get(struct rte_eth_dev *dev, char *fw_ver, size_t fw_size); 916 int mlx5_dev_set_mtu(struct rte_eth_dev *dev, uint16_t mtu); 917 int mlx5_hairpin_cap_get(struct rte_eth_dev *dev, 918 struct rte_eth_hairpin_cap *cap); 919 bool mlx5_flex_parser_ecpri_exist(struct rte_eth_dev *dev); 920 int mlx5_flex_parser_ecpri_alloc(struct rte_eth_dev *dev); 921 922 /* mlx5_ethdev.c */ 923 924 int mlx5_dev_configure(struct rte_eth_dev *dev); 925 int mlx5_fw_version_get(struct rte_eth_dev *dev, char *fw_ver, 926 size_t fw_size); 927 int mlx5_dev_infos_get(struct rte_eth_dev *dev, 928 struct rte_eth_dev_info *info); 929 const uint32_t *mlx5_dev_supported_ptypes_get(struct rte_eth_dev *dev); 930 int mlx5_dev_set_mtu(struct rte_eth_dev *dev, uint16_t mtu); 931 int mlx5_hairpin_cap_get(struct rte_eth_dev *dev, 932 struct rte_eth_hairpin_cap *cap); 933 eth_rx_burst_t mlx5_select_rx_function(struct rte_eth_dev *dev); 934 struct mlx5_priv *mlx5_port_to_eswitch_info(uint16_t port, bool valid); 935 struct mlx5_priv *mlx5_dev_to_eswitch_info(struct rte_eth_dev *dev); 936 int mlx5_dev_configure_rss_reta(struct rte_eth_dev *dev); 937 938 /* mlx5_ethdev_os.c */ 939 940 unsigned int mlx5_ifindex(const struct rte_eth_dev *dev); 941 int mlx5_get_mac(struct rte_eth_dev *dev, uint8_t (*mac)[RTE_ETHER_ADDR_LEN]); 942 int mlx5_get_mtu(struct rte_eth_dev *dev, uint16_t *mtu); 943 int mlx5_set_mtu(struct rte_eth_dev *dev, uint16_t mtu); 944 int mlx5_read_clock(struct rte_eth_dev *dev, uint64_t *clock); 945 int mlx5_link_update(struct rte_eth_dev *dev, int wait_to_complete); 946 int mlx5_dev_get_flow_ctrl(struct rte_eth_dev *dev, 947 struct rte_eth_fc_conf *fc_conf); 948 int mlx5_dev_set_flow_ctrl(struct rte_eth_dev *dev, 949 struct rte_eth_fc_conf *fc_conf); 950 void mlx5_dev_interrupt_handler(void *arg); 951 void mlx5_dev_interrupt_handler_devx(void *arg); 952 int mlx5_set_link_down(struct rte_eth_dev *dev); 953 int mlx5_set_link_up(struct rte_eth_dev *dev); 954 int mlx5_is_removed(struct rte_eth_dev *dev); 955 int mlx5_sysfs_switch_info(unsigned int ifindex, 956 struct mlx5_switch_info *info); 957 void mlx5_translate_port_name(const char *port_name_in, 958 struct mlx5_switch_info *port_info_out); 959 void mlx5_intr_callback_unregister(const struct rte_intr_handle *handle, 960 rte_intr_callback_fn cb_fn, void *cb_arg); 961 int mlx5_sysfs_bond_info(unsigned int pf_ifindex, unsigned int *ifindex, 962 char *ifname); 963 int mlx5_get_module_info(struct rte_eth_dev *dev, 964 struct rte_eth_dev_module_info *modinfo); 965 int mlx5_get_module_eeprom(struct rte_eth_dev *dev, 966 struct rte_dev_eeprom_info *info); 967 int mlx5_os_read_dev_stat(struct mlx5_priv *priv, 968 const char *ctr_name, uint64_t *stat); 969 int mlx5_os_read_dev_counters(struct rte_eth_dev *dev, uint64_t *stats); 970 int mlx5_os_get_stats_n(struct rte_eth_dev *dev); 971 void mlx5_os_stats_init(struct rte_eth_dev *dev); 972 973 /* mlx5_mac.c */ 974 975 void mlx5_mac_addr_remove(struct rte_eth_dev *dev, uint32_t index); 976 int mlx5_mac_addr_add(struct rte_eth_dev *dev, struct rte_ether_addr *mac, 977 uint32_t index, uint32_t vmdq); 978 int mlx5_mac_addr_set(struct rte_eth_dev *dev, struct rte_ether_addr *mac_addr); 979 int mlx5_set_mc_addr_list(struct rte_eth_dev *dev, 980 struct rte_ether_addr *mc_addr_set, 981 uint32_t nb_mc_addr); 982 983 /* mlx5_rss.c */ 984 985 int mlx5_rss_hash_update(struct rte_eth_dev *dev, 986 struct rte_eth_rss_conf *rss_conf); 987 int mlx5_rss_hash_conf_get(struct rte_eth_dev *dev, 988 struct rte_eth_rss_conf *rss_conf); 989 int mlx5_rss_reta_index_resize(struct rte_eth_dev *dev, unsigned int reta_size); 990 int mlx5_dev_rss_reta_query(struct rte_eth_dev *dev, 991 struct rte_eth_rss_reta_entry64 *reta_conf, 992 uint16_t reta_size); 993 int mlx5_dev_rss_reta_update(struct rte_eth_dev *dev, 994 struct rte_eth_rss_reta_entry64 *reta_conf, 995 uint16_t reta_size); 996 997 /* mlx5_rxmode.c */ 998 999 int mlx5_promiscuous_enable(struct rte_eth_dev *dev); 1000 int mlx5_promiscuous_disable(struct rte_eth_dev *dev); 1001 int mlx5_allmulticast_enable(struct rte_eth_dev *dev); 1002 int mlx5_allmulticast_disable(struct rte_eth_dev *dev); 1003 1004 /* mlx5_stats.c */ 1005 1006 int mlx5_stats_get(struct rte_eth_dev *dev, struct rte_eth_stats *stats); 1007 int mlx5_stats_reset(struct rte_eth_dev *dev); 1008 int mlx5_xstats_get(struct rte_eth_dev *dev, struct rte_eth_xstat *stats, 1009 unsigned int n); 1010 int mlx5_xstats_reset(struct rte_eth_dev *dev); 1011 int mlx5_xstats_get_names(struct rte_eth_dev *dev __rte_unused, 1012 struct rte_eth_xstat_name *xstats_names, 1013 unsigned int n); 1014 1015 /* mlx5_vlan.c */ 1016 1017 int mlx5_vlan_filter_set(struct rte_eth_dev *dev, uint16_t vlan_id, int on); 1018 void mlx5_vlan_strip_queue_set(struct rte_eth_dev *dev, uint16_t queue, int on); 1019 int mlx5_vlan_offload_set(struct rte_eth_dev *dev, int mask); 1020 1021 /* mlx5_vlan_os.c */ 1022 1023 void mlx5_vlan_vmwa_exit(void *ctx); 1024 void mlx5_vlan_vmwa_release(struct rte_eth_dev *dev, 1025 struct mlx5_vf_vlan *vf_vlan); 1026 void mlx5_vlan_vmwa_acquire(struct rte_eth_dev *dev, 1027 struct mlx5_vf_vlan *vf_vlan); 1028 void *mlx5_vlan_vmwa_init(struct rte_eth_dev *dev, uint32_t ifindex); 1029 1030 /* mlx5_trigger.c */ 1031 1032 int mlx5_dev_start(struct rte_eth_dev *dev); 1033 int mlx5_dev_stop(struct rte_eth_dev *dev); 1034 int mlx5_traffic_enable(struct rte_eth_dev *dev); 1035 void mlx5_traffic_disable(struct rte_eth_dev *dev); 1036 int mlx5_traffic_restart(struct rte_eth_dev *dev); 1037 1038 /* mlx5_flow.c */ 1039 1040 int mlx5_flow_discover_mreg_c(struct rte_eth_dev *eth_dev); 1041 bool mlx5_flow_ext_mreg_supported(struct rte_eth_dev *dev); 1042 void mlx5_flow_print(struct rte_flow *flow); 1043 int mlx5_flow_validate(struct rte_eth_dev *dev, 1044 const struct rte_flow_attr *attr, 1045 const struct rte_flow_item items[], 1046 const struct rte_flow_action actions[], 1047 struct rte_flow_error *error); 1048 struct rte_flow *mlx5_flow_create(struct rte_eth_dev *dev, 1049 const struct rte_flow_attr *attr, 1050 const struct rte_flow_item items[], 1051 const struct rte_flow_action actions[], 1052 struct rte_flow_error *error); 1053 int mlx5_flow_destroy(struct rte_eth_dev *dev, struct rte_flow *flow, 1054 struct rte_flow_error *error); 1055 void mlx5_flow_list_flush(struct rte_eth_dev *dev, uint32_t *list, bool active); 1056 int mlx5_flow_flush(struct rte_eth_dev *dev, struct rte_flow_error *error); 1057 int mlx5_flow_query(struct rte_eth_dev *dev, struct rte_flow *flow, 1058 const struct rte_flow_action *action, void *data, 1059 struct rte_flow_error *error); 1060 int mlx5_flow_isolate(struct rte_eth_dev *dev, int enable, 1061 struct rte_flow_error *error); 1062 int mlx5_dev_filter_ctrl(struct rte_eth_dev *dev, 1063 enum rte_filter_type filter_type, 1064 enum rte_filter_op filter_op, 1065 void *arg); 1066 int mlx5_flow_start(struct rte_eth_dev *dev, uint32_t *list); 1067 void mlx5_flow_stop(struct rte_eth_dev *dev, uint32_t *list); 1068 int mlx5_flow_start_default(struct rte_eth_dev *dev); 1069 void mlx5_flow_stop_default(struct rte_eth_dev *dev); 1070 void mlx5_flow_alloc_intermediate(struct rte_eth_dev *dev); 1071 void mlx5_flow_free_intermediate(struct rte_eth_dev *dev); 1072 int mlx5_flow_verify(struct rte_eth_dev *dev); 1073 int mlx5_ctrl_flow_source_queue(struct rte_eth_dev *dev, uint32_t queue); 1074 int mlx5_ctrl_flow_vlan(struct rte_eth_dev *dev, 1075 struct rte_flow_item_eth *eth_spec, 1076 struct rte_flow_item_eth *eth_mask, 1077 struct rte_flow_item_vlan *vlan_spec, 1078 struct rte_flow_item_vlan *vlan_mask); 1079 int mlx5_ctrl_flow(struct rte_eth_dev *dev, 1080 struct rte_flow_item_eth *eth_spec, 1081 struct rte_flow_item_eth *eth_mask); 1082 int mlx5_flow_lacp_miss(struct rte_eth_dev *dev); 1083 struct rte_flow *mlx5_flow_create_esw_table_zero_flow(struct rte_eth_dev *dev); 1084 int mlx5_flow_create_drop_queue(struct rte_eth_dev *dev); 1085 void mlx5_flow_delete_drop_queue(struct rte_eth_dev *dev); 1086 void mlx5_flow_async_pool_query_handle(struct mlx5_dev_ctx_shared *sh, 1087 uint64_t async_id, int status); 1088 void mlx5_set_query_alarm(struct mlx5_dev_ctx_shared *sh); 1089 void mlx5_flow_query_alarm(void *arg); 1090 uint32_t mlx5_counter_alloc(struct rte_eth_dev *dev); 1091 void mlx5_counter_free(struct rte_eth_dev *dev, uint32_t cnt); 1092 int mlx5_counter_query(struct rte_eth_dev *dev, uint32_t cnt, 1093 bool clear, uint64_t *pkts, uint64_t *bytes); 1094 int mlx5_flow_dev_dump(struct rte_eth_dev *dev, FILE *file, 1095 struct rte_flow_error *error); 1096 void mlx5_flow_rxq_dynf_metadata_set(struct rte_eth_dev *dev); 1097 int mlx5_flow_get_aged_flows(struct rte_eth_dev *dev, void **contexts, 1098 uint32_t nb_contexts, struct rte_flow_error *error); 1099 1100 /* mlx5_mp_os.c */ 1101 1102 int mlx5_mp_os_primary_handle(const struct rte_mp_msg *mp_msg, 1103 const void *peer); 1104 int mlx5_mp_os_secondary_handle(const struct rte_mp_msg *mp_msg, 1105 const void *peer); 1106 void mlx5_mp_os_req_start_rxtx(struct rte_eth_dev *dev); 1107 void mlx5_mp_os_req_stop_rxtx(struct rte_eth_dev *dev); 1108 int mlx5_mp_os_req_queue_control(struct rte_eth_dev *dev, uint16_t queue_id, 1109 enum mlx5_mp_req_type req_type); 1110 1111 /* mlx5_socket.c */ 1112 1113 int mlx5_pmd_socket_init(void); 1114 1115 /* mlx5_flow_meter.c */ 1116 1117 int mlx5_flow_meter_ops_get(struct rte_eth_dev *dev, void *arg); 1118 struct mlx5_flow_meter *mlx5_flow_meter_find(struct mlx5_priv *priv, 1119 uint32_t meter_id); 1120 struct mlx5_flow_meter *mlx5_flow_meter_attach 1121 (struct mlx5_priv *priv, 1122 uint32_t meter_id, 1123 const struct rte_flow_attr *attr, 1124 struct rte_flow_error *error); 1125 void mlx5_flow_meter_detach(struct mlx5_flow_meter *fm); 1126 1127 /* mlx5_os.c */ 1128 struct rte_pci_driver; 1129 int mlx5_os_get_dev_attr(void *ctx, struct mlx5_dev_attr *dev_attr); 1130 void mlx5_os_free_shared_dr(struct mlx5_priv *priv); 1131 int mlx5_os_open_device(const struct mlx5_dev_spawn_data *spawn, 1132 const struct mlx5_dev_config *config, 1133 struct mlx5_dev_ctx_shared *sh); 1134 int mlx5_os_get_pdn(void *pd, uint32_t *pdn); 1135 int mlx5_os_pci_probe(struct rte_pci_driver *pci_drv __rte_unused, 1136 struct rte_pci_device *pci_dev); 1137 void mlx5_os_dev_shared_handler_install(struct mlx5_dev_ctx_shared *sh); 1138 void mlx5_os_dev_shared_handler_uninstall(struct mlx5_dev_ctx_shared *sh); 1139 void mlx5_os_set_reg_mr_cb(mlx5_reg_mr_t *reg_mr_cb, 1140 mlx5_dereg_mr_t *dereg_mr_cb); 1141 void mlx5_os_mac_addr_remove(struct rte_eth_dev *dev, uint32_t index); 1142 int mlx5_os_mac_addr_add(struct rte_eth_dev *dev, struct rte_ether_addr *mac, 1143 uint32_t index); 1144 int mlx5_os_vf_mac_addr_modify(struct mlx5_priv *priv, unsigned int iface_idx, 1145 struct rte_ether_addr *mac_addr, 1146 int vf_index); 1147 int mlx5_os_set_promisc(struct rte_eth_dev *dev, int enable); 1148 int mlx5_os_set_allmulti(struct rte_eth_dev *dev, int enable); 1149 int mlx5_os_set_nonblock_channel_fd(int fd); 1150 void mlx5_os_mac_addr_flush(struct rte_eth_dev *dev); 1151 1152 /* mlx5_txpp.c */ 1153 1154 int mlx5_txpp_start(struct rte_eth_dev *dev); 1155 void mlx5_txpp_stop(struct rte_eth_dev *dev); 1156 int mlx5_txpp_read_clock(struct rte_eth_dev *dev, uint64_t *timestamp); 1157 int mlx5_txpp_xstats_get(struct rte_eth_dev *dev, 1158 struct rte_eth_xstat *stats, 1159 unsigned int n, unsigned int n_used); 1160 int mlx5_txpp_xstats_reset(struct rte_eth_dev *dev); 1161 int mlx5_txpp_xstats_get_names(struct rte_eth_dev *dev, 1162 struct rte_eth_xstat_name *xstats_names, 1163 unsigned int n, unsigned int n_used); 1164 void mlx5_txpp_interrupt_handler(void *cb_arg); 1165 1166 /* mlx5_rxtx.c */ 1167 1168 eth_tx_burst_t mlx5_select_tx_function(struct rte_eth_dev *dev); 1169 1170 #endif /* RTE_PMD_MLX5_H_ */ 1171