1 /* SPDX-License-Identifier: BSD-3-Clause 2 * Copyright 2015 6WIND S.A. 3 * Copyright 2015 Mellanox Technologies, Ltd 4 */ 5 6 #ifndef RTE_PMD_MLX5_H_ 7 #define RTE_PMD_MLX5_H_ 8 9 #include <stddef.h> 10 #include <stdbool.h> 11 #include <stdint.h> 12 #include <limits.h> 13 #include <net/if.h> 14 #include <netinet/in.h> 15 #include <sys/queue.h> 16 17 /* Verbs header. */ 18 /* ISO C doesn't support unnamed structs/unions, disabling -pedantic. */ 19 #ifdef PEDANTIC 20 #pragma GCC diagnostic ignored "-Wpedantic" 21 #endif 22 #include <infiniband/verbs.h> 23 #ifdef PEDANTIC 24 #pragma GCC diagnostic error "-Wpedantic" 25 #endif 26 27 #include <rte_pci.h> 28 #include <rte_ether.h> 29 #include <rte_ethdev_driver.h> 30 #include <rte_rwlock.h> 31 #include <rte_interrupts.h> 32 #include <rte_errno.h> 33 #include <rte_flow.h> 34 35 #include <mlx5_glue.h> 36 #include <mlx5_devx_cmds.h> 37 #include <mlx5_prm.h> 38 #include <mlx5_nl.h> 39 40 #include "mlx5_defs.h" 41 #include "mlx5_utils.h" 42 #include "mlx5_mr.h" 43 #include "mlx5_autoconf.h" 44 45 /* Request types for IPC. */ 46 enum mlx5_mp_req_type { 47 MLX5_MP_REQ_VERBS_CMD_FD = 1, 48 MLX5_MP_REQ_CREATE_MR, 49 MLX5_MP_REQ_START_RXTX, 50 MLX5_MP_REQ_STOP_RXTX, 51 MLX5_MP_REQ_QUEUE_STATE_MODIFY, 52 }; 53 54 struct mlx5_mp_arg_queue_state_modify { 55 uint8_t is_wq; /* Set if WQ. */ 56 uint16_t queue_id; /* DPDK queue ID. */ 57 enum ibv_wq_state state; /* WQ requested state. */ 58 }; 59 60 /* Pameters for IPC. */ 61 struct mlx5_mp_param { 62 enum mlx5_mp_req_type type; 63 int port_id; 64 int result; 65 RTE_STD_C11 66 union { 67 uintptr_t addr; /* MLX5_MP_REQ_CREATE_MR */ 68 struct mlx5_mp_arg_queue_state_modify state_modify; 69 /* MLX5_MP_REQ_QUEUE_STATE_MODIFY */ 70 } args; 71 }; 72 73 /** Request timeout for IPC. */ 74 #define MLX5_MP_REQ_TIMEOUT_SEC 5 75 76 /** Key string for IPC. */ 77 #define MLX5_MP_NAME "net_mlx5_mp" 78 79 80 LIST_HEAD(mlx5_dev_list, mlx5_ibv_shared); 81 82 /* Shared data between primary and secondary processes. */ 83 struct mlx5_shared_data { 84 rte_spinlock_t lock; 85 /* Global spinlock for primary and secondary processes. */ 86 int init_done; /* Whether primary has done initialization. */ 87 unsigned int secondary_cnt; /* Number of secondary processes init'd. */ 88 struct mlx5_dev_list mem_event_cb_list; 89 rte_rwlock_t mem_event_rwlock; 90 }; 91 92 /* Per-process data structure, not visible to other processes. */ 93 struct mlx5_local_data { 94 int init_done; /* Whether a secondary has done initialization. */ 95 }; 96 97 extern struct mlx5_shared_data *mlx5_shared_data; 98 99 struct mlx5_counter_ctrl { 100 /* Name of the counter. */ 101 char dpdk_name[RTE_ETH_XSTATS_NAME_SIZE]; 102 /* Name of the counter on the device table. */ 103 char ctr_name[RTE_ETH_XSTATS_NAME_SIZE]; 104 uint32_t ib:1; /**< Nonzero for IB counters. */ 105 }; 106 107 struct mlx5_xstats_ctrl { 108 /* Number of device stats. */ 109 uint16_t stats_n; 110 /* Number of device stats identified by PMD. */ 111 uint16_t mlx5_stats_n; 112 /* Index in the device counters table. */ 113 uint16_t dev_table_idx[MLX5_MAX_XSTATS]; 114 uint64_t base[MLX5_MAX_XSTATS]; 115 struct mlx5_counter_ctrl info[MLX5_MAX_XSTATS]; 116 }; 117 118 struct mlx5_stats_ctrl { 119 /* Base for imissed counter. */ 120 uint64_t imissed_base; 121 }; 122 123 /* Flow list . */ 124 TAILQ_HEAD(mlx5_flows, rte_flow); 125 126 /* Default PMD specific parameter value. */ 127 #define MLX5_ARG_UNSET (-1) 128 129 #define MLX5_LRO_SUPPORTED(dev) \ 130 (((struct mlx5_priv *)((dev)->data->dev_private))->config.lro.supported) 131 132 /* Maximal size of coalesced segment for LRO is set in chunks of 256 Bytes. */ 133 #define MLX5_LRO_SEG_CHUNK_SIZE 256u 134 135 /* Maximal size of aggregated LRO packet. */ 136 #define MLX5_MAX_LRO_SIZE (UINT8_MAX * MLX5_LRO_SEG_CHUNK_SIZE) 137 138 /* LRO configurations structure. */ 139 struct mlx5_lro_config { 140 uint32_t supported:1; /* Whether LRO is supported. */ 141 uint32_t timeout; /* User configuration. */ 142 }; 143 144 /* 145 * Device configuration structure. 146 * 147 * Merged configuration from: 148 * 149 * - Device capabilities, 150 * - User device parameters disabled features. 151 */ 152 struct mlx5_dev_config { 153 unsigned int hw_csum:1; /* Checksum offload is supported. */ 154 unsigned int hw_vlan_strip:1; /* VLAN stripping is supported. */ 155 unsigned int hw_vlan_insert:1; /* VLAN insertion in WQE is supported. */ 156 unsigned int hw_fcs_strip:1; /* FCS stripping is supported. */ 157 unsigned int hw_padding:1; /* End alignment padding is supported. */ 158 unsigned int vf:1; /* This is a VF. */ 159 unsigned int tunnel_en:1; 160 /* Whether tunnel stateless offloads are supported. */ 161 unsigned int mpls_en:1; /* MPLS over GRE/UDP is enabled. */ 162 unsigned int cqe_comp:1; /* CQE compression is enabled. */ 163 unsigned int cqe_pad:1; /* CQE padding is enabled. */ 164 unsigned int tso:1; /* Whether TSO is supported. */ 165 unsigned int rx_vec_en:1; /* Rx vector is enabled. */ 166 unsigned int mr_ext_memseg_en:1; 167 /* Whether memseg should be extended for MR creation. */ 168 unsigned int l3_vxlan_en:1; /* Enable L3 VXLAN flow creation. */ 169 unsigned int vf_nl_en:1; /* Enable Netlink requests in VF mode. */ 170 unsigned int dv_esw_en:1; /* Enable E-Switch DV flow. */ 171 unsigned int dv_flow_en:1; /* Enable DV flow. */ 172 unsigned int dv_xmeta_en:2; /* Enable extensive flow metadata. */ 173 unsigned int swp:1; /* Tx generic tunnel checksum and TSO offload. */ 174 unsigned int devx:1; /* Whether devx interface is available or not. */ 175 unsigned int dest_tir:1; /* Whether advanced DR API is available. */ 176 struct { 177 unsigned int enabled:1; /* Whether MPRQ is enabled. */ 178 unsigned int stride_num_n; /* Number of strides. */ 179 unsigned int min_stride_size_n; /* Min size of a stride. */ 180 unsigned int max_stride_size_n; /* Max size of a stride. */ 181 unsigned int max_memcpy_len; 182 /* Maximum packet size to memcpy Rx packets. */ 183 unsigned int min_rxqs_num; 184 /* Rx queue count threshold to enable MPRQ. */ 185 } mprq; /* Configurations for Multi-Packet RQ. */ 186 int mps; /* Multi-packet send supported mode. */ 187 int dbnc; /* Skip doorbell register write barrier. */ 188 unsigned int flow_prio; /* Number of flow priorities. */ 189 enum modify_reg flow_mreg_c[MLX5_MREG_C_NUM]; 190 /* Availibility of mreg_c's. */ 191 unsigned int tso_max_payload_sz; /* Maximum TCP payload for TSO. */ 192 unsigned int ind_table_max_size; /* Maximum indirection table size. */ 193 unsigned int max_dump_files_num; /* Maximum dump files per queue. */ 194 int txqs_inline; /* Queue number threshold for inlining. */ 195 int txq_inline_min; /* Minimal amount of data bytes to inline. */ 196 int txq_inline_max; /* Max packet size for inlining with SEND. */ 197 int txq_inline_mpw; /* Max packet size for inlining with eMPW. */ 198 struct mlx5_hca_attr hca_attr; /* HCA attributes. */ 199 struct mlx5_lro_config lro; /* LRO configuration. */ 200 }; 201 202 203 /** 204 * Type of object being allocated. 205 */ 206 enum mlx5_verbs_alloc_type { 207 MLX5_VERBS_ALLOC_TYPE_NONE, 208 MLX5_VERBS_ALLOC_TYPE_TX_QUEUE, 209 MLX5_VERBS_ALLOC_TYPE_RX_QUEUE, 210 }; 211 212 /* Structure for VF VLAN workaround. */ 213 struct mlx5_vf_vlan { 214 uint32_t tag:12; 215 uint32_t created:1; 216 }; 217 218 /** 219 * Verbs allocator needs a context to know in the callback which kind of 220 * resources it is allocating. 221 */ 222 struct mlx5_verbs_alloc_ctx { 223 enum mlx5_verbs_alloc_type type; /* Kind of object being allocated. */ 224 const void *obj; /* Pointer to the DPDK object. */ 225 }; 226 227 LIST_HEAD(mlx5_mr_list, mlx5_mr); 228 229 /* Flow drop context necessary due to Verbs API. */ 230 struct mlx5_drop { 231 struct mlx5_hrxq *hrxq; /* Hash Rx queue queue. */ 232 struct mlx5_rxq_obj *rxq; /* Rx queue object. */ 233 }; 234 235 #define MLX5_COUNTERS_PER_POOL 512 236 #define MLX5_MAX_PENDING_QUERIES 4 237 238 struct mlx5_flow_counter_pool; 239 240 struct flow_counter_stats { 241 uint64_t hits; 242 uint64_t bytes; 243 }; 244 245 /* Counters information. */ 246 struct mlx5_flow_counter { 247 TAILQ_ENTRY(mlx5_flow_counter) next; 248 /**< Pointer to the next flow counter structure. */ 249 uint32_t shared:1; /**< Share counter ID with other flow rules. */ 250 uint32_t batch: 1; 251 /**< Whether the counter was allocated by batch command. */ 252 uint32_t ref_cnt:30; /**< Reference counter. */ 253 uint32_t id; /**< Counter ID. */ 254 union { /**< Holds the counters for the rule. */ 255 #if defined(HAVE_IBV_DEVICE_COUNTERS_SET_V42) 256 struct ibv_counter_set *cs; 257 #elif defined(HAVE_IBV_DEVICE_COUNTERS_SET_V45) 258 struct ibv_counters *cs; 259 #endif 260 struct mlx5_devx_obj *dcs; /**< Counter Devx object. */ 261 struct mlx5_flow_counter_pool *pool; /**< The counter pool. */ 262 }; 263 union { 264 uint64_t hits; /**< Reset value of hits packets. */ 265 int64_t query_gen; /**< Generation of the last release. */ 266 }; 267 uint64_t bytes; /**< Reset value of bytes. */ 268 void *action; /**< Pointer to the dv action. */ 269 }; 270 271 TAILQ_HEAD(mlx5_counters, mlx5_flow_counter); 272 273 /* Counter pool structure - query is in pool resolution. */ 274 struct mlx5_flow_counter_pool { 275 TAILQ_ENTRY(mlx5_flow_counter_pool) next; 276 struct mlx5_counters counters; /* Free counter list. */ 277 union { 278 struct mlx5_devx_obj *min_dcs; 279 rte_atomic64_t a64_dcs; 280 }; 281 /* The devx object of the minimum counter ID. */ 282 rte_atomic64_t query_gen; 283 uint32_t n_counters: 16; /* Number of devx allocated counters. */ 284 rte_spinlock_t sl; /* The pool lock. */ 285 struct mlx5_counter_stats_raw *raw; 286 struct mlx5_counter_stats_raw *raw_hw; /* The raw on HW working. */ 287 struct mlx5_flow_counter counters_raw[]; /* The pool counters memory. */ 288 }; 289 290 struct mlx5_counter_stats_raw; 291 292 /* Memory management structure for group of counter statistics raws. */ 293 struct mlx5_counter_stats_mem_mng { 294 LIST_ENTRY(mlx5_counter_stats_mem_mng) next; 295 struct mlx5_counter_stats_raw *raws; 296 struct mlx5_devx_obj *dm; 297 struct mlx5dv_devx_umem *umem; 298 }; 299 300 /* Raw memory structure for the counter statistics values of a pool. */ 301 struct mlx5_counter_stats_raw { 302 LIST_ENTRY(mlx5_counter_stats_raw) next; 303 int min_dcs_id; 304 struct mlx5_counter_stats_mem_mng *mem_mng; 305 volatile struct flow_counter_stats *data; 306 }; 307 308 TAILQ_HEAD(mlx5_counter_pools, mlx5_flow_counter_pool); 309 310 /* Container structure for counter pools. */ 311 struct mlx5_pools_container { 312 rte_atomic16_t n_valid; /* Number of valid pools. */ 313 uint16_t n; /* Number of pools. */ 314 struct mlx5_counter_pools pool_list; /* Counter pool list. */ 315 struct mlx5_flow_counter_pool **pools; /* Counter pool array. */ 316 struct mlx5_counter_stats_mem_mng *init_mem_mng; 317 /* Hold the memory management for the next allocated pools raws. */ 318 }; 319 320 /* Counter global management structure. */ 321 struct mlx5_flow_counter_mng { 322 uint8_t mhi[2]; /* master \ host container index. */ 323 struct mlx5_pools_container ccont[2 * 2]; 324 /* 2 containers for single and for batch for double-buffer. */ 325 struct mlx5_counters flow_counters; /* Legacy flow counter list. */ 326 uint8_t pending_queries; 327 uint8_t batch; 328 uint16_t pool_index; 329 uint8_t query_thread_on; 330 LIST_HEAD(mem_mngs, mlx5_counter_stats_mem_mng) mem_mngs; 331 LIST_HEAD(stat_raws, mlx5_counter_stats_raw) free_stat_raws; 332 }; 333 334 /* Per port data of shared IB device. */ 335 struct mlx5_ibv_shared_port { 336 uint32_t ih_port_id; 337 uint32_t devx_ih_port_id; 338 /* 339 * Interrupt handler port_id. Used by shared interrupt 340 * handler to find the corresponding rte_eth device 341 * by IB port index. If value is equal or greater 342 * RTE_MAX_ETHPORTS it means there is no subhandler 343 * installed for specified IB port index. 344 */ 345 }; 346 347 /* Table key of the hash organization. */ 348 union mlx5_flow_tbl_key { 349 struct { 350 /* Table ID should be at the lowest address. */ 351 uint32_t table_id; /**< ID of the table. */ 352 uint16_t reserved; /**< must be zero for comparison. */ 353 uint8_t domain; /**< 1 - FDB, 0 - NIC TX/RX. */ 354 uint8_t direction; /**< 1 - egress, 0 - ingress. */ 355 }; 356 uint64_t v64; /**< full 64bits value of key */ 357 }; 358 359 /* Table structure. */ 360 struct mlx5_flow_tbl_resource { 361 void *obj; /**< Pointer to DR table object. */ 362 rte_atomic32_t refcnt; /**< Reference counter. */ 363 }; 364 365 #define MLX5_MAX_TABLES UINT16_MAX 366 #define MLX5_FLOW_TABLE_LEVEL_METER (UINT16_MAX - 3) 367 #define MLX5_FLOW_TABLE_LEVEL_SUFFIX (UINT16_MAX - 2) 368 #define MLX5_HAIRPIN_TX_TABLE (UINT16_MAX - 1) 369 /* Reserve the last two tables for metadata register copy. */ 370 #define MLX5_FLOW_MREG_ACT_TABLE_GROUP (MLX5_MAX_TABLES - 1) 371 #define MLX5_FLOW_MREG_CP_TABLE_GROUP (MLX5_MAX_TABLES - 2) 372 /* Tables for metering splits should be added here. */ 373 #define MLX5_MAX_TABLES_EXTERNAL (MLX5_MAX_TABLES - 3) 374 #define MLX5_MAX_TABLES_FDB UINT16_MAX 375 376 #define MLX5_DBR_PAGE_SIZE 4096 /* Must be >= 512. */ 377 #define MLX5_DBR_SIZE 8 378 #define MLX5_DBR_PER_PAGE (MLX5_DBR_PAGE_SIZE / MLX5_DBR_SIZE) 379 #define MLX5_DBR_BITMAP_SIZE (MLX5_DBR_PER_PAGE / 64) 380 381 struct mlx5_devx_dbr_page { 382 /* Door-bell records, must be first member in structure. */ 383 uint8_t dbrs[MLX5_DBR_PAGE_SIZE]; 384 LIST_ENTRY(mlx5_devx_dbr_page) next; /* Pointer to the next element. */ 385 struct mlx5dv_devx_umem *umem; 386 uint32_t dbr_count; /* Number of door-bell records in use. */ 387 /* 1 bit marks matching door-bell is in use. */ 388 uint64_t dbr_bitmap[MLX5_DBR_BITMAP_SIZE]; 389 }; 390 391 /* ID generation structure. */ 392 struct mlx5_flow_id_pool { 393 uint32_t *free_arr; /**< Pointer to the a array of free values. */ 394 uint32_t base_index; 395 /**< The next index that can be used without any free elements. */ 396 uint32_t *curr; /**< Pointer to the index to pop. */ 397 uint32_t *last; /**< Pointer to the last element in the empty arrray. */ 398 uint32_t max_id; /**< Maximum id can be allocated from the pool. */ 399 }; 400 401 /* 402 * Shared Infiniband device context for Master/Representors 403 * which belong to same IB device with multiple IB ports. 404 **/ 405 struct mlx5_ibv_shared { 406 LIST_ENTRY(mlx5_ibv_shared) next; 407 uint32_t refcnt; 408 uint32_t devx:1; /* Opened with DV. */ 409 uint32_t max_port; /* Maximal IB device port index. */ 410 struct ibv_context *ctx; /* Verbs/DV context. */ 411 struct ibv_pd *pd; /* Protection Domain. */ 412 uint32_t pdn; /* Protection Domain number. */ 413 uint32_t tdn; /* Transport Domain number. */ 414 char ibdev_name[IBV_SYSFS_NAME_MAX]; /* IB device name. */ 415 char ibdev_path[IBV_SYSFS_PATH_MAX]; /* IB device path for secondary */ 416 struct ibv_device_attr_ex device_attr; /* Device properties. */ 417 LIST_ENTRY(mlx5_ibv_shared) mem_event_cb; 418 /**< Called by memory event callback. */ 419 struct { 420 uint32_t dev_gen; /* Generation number to flush local caches. */ 421 rte_rwlock_t rwlock; /* MR Lock. */ 422 struct mlx5_mr_btree cache; /* Global MR cache table. */ 423 struct mlx5_mr_list mr_list; /* Registered MR list. */ 424 struct mlx5_mr_list mr_free_list; /* Freed MR list. */ 425 } mr; 426 /* Shared DV/DR flow data section. */ 427 pthread_mutex_t dv_mutex; /* DV context mutex. */ 428 uint32_t dv_meta_mask; /* flow META metadata supported mask. */ 429 uint32_t dv_mark_mask; /* flow MARK metadata supported mask. */ 430 uint32_t dv_regc0_mask; /* available bits of metatada reg_c[0]. */ 431 uint32_t dv_refcnt; /* DV/DR data reference counter. */ 432 void *fdb_domain; /* FDB Direct Rules name space handle. */ 433 struct mlx5_flow_tbl_resource *fdb_mtr_sfx_tbl; 434 /* FDB meter suffix rules table. */ 435 void *rx_domain; /* RX Direct Rules name space handle. */ 436 struct mlx5_flow_tbl_resource *rx_mtr_sfx_tbl; 437 /* RX meter suffix rules table. */ 438 void *tx_domain; /* TX Direct Rules name space handle. */ 439 struct mlx5_flow_tbl_resource *tx_mtr_sfx_tbl; 440 /* TX meter suffix rules table. */ 441 struct mlx5_hlist *flow_tbls; 442 /* Direct Rules tables for FDB, NIC TX+RX */ 443 void *esw_drop_action; /* Pointer to DR E-Switch drop action. */ 444 void *pop_vlan_action; /* Pointer to DR pop VLAN action. */ 445 LIST_HEAD(encap_decap, mlx5_flow_dv_encap_decap_resource) encaps_decaps; 446 LIST_HEAD(modify_cmd, mlx5_flow_dv_modify_hdr_resource) modify_cmds; 447 struct mlx5_hlist *tag_table; 448 LIST_HEAD(port_id_action_list, mlx5_flow_dv_port_id_action_resource) 449 port_id_action_list; /* List of port ID actions. */ 450 LIST_HEAD(push_vlan_action_list, mlx5_flow_dv_push_vlan_action_resource) 451 push_vlan_action_list; /* List of push VLAN actions. */ 452 struct mlx5_flow_counter_mng cmng; /* Counters management structure. */ 453 /* Shared interrupt handler section. */ 454 pthread_mutex_t intr_mutex; /* Interrupt config mutex. */ 455 uint32_t intr_cnt; /* Interrupt handler reference counter. */ 456 struct rte_intr_handle intr_handle; /* Interrupt handler for device. */ 457 uint32_t devx_intr_cnt; /* Devx interrupt handler reference counter. */ 458 struct rte_intr_handle intr_handle_devx; /* DEVX interrupt handler. */ 459 struct mlx5dv_devx_cmd_comp *devx_comp; /* DEVX async comp obj. */ 460 struct mlx5_devx_obj *tis; /* TIS object. */ 461 struct mlx5_devx_obj *td; /* Transport domain. */ 462 struct mlx5_flow_id_pool *flow_id_pool; /* Flow ID pool. */ 463 struct mlx5_ibv_shared_port port[]; /* per device port data array. */ 464 }; 465 466 /* Per-process private structure. */ 467 struct mlx5_proc_priv { 468 size_t uar_table_sz; 469 /* Size of UAR register table. */ 470 void *uar_table[]; 471 /* Table of UAR registers for each process. */ 472 }; 473 474 /* MTR profile list. */ 475 TAILQ_HEAD(mlx5_mtr_profiles, mlx5_flow_meter_profile); 476 /* MTR list. */ 477 TAILQ_HEAD(mlx5_flow_meters, mlx5_flow_meter); 478 479 #define MLX5_PROC_PRIV(port_id) \ 480 ((struct mlx5_proc_priv *)rte_eth_devices[port_id].process_private) 481 482 struct mlx5_priv { 483 struct rte_eth_dev_data *dev_data; /* Pointer to device data. */ 484 struct mlx5_ibv_shared *sh; /* Shared IB device context. */ 485 uint32_t ibv_port; /* IB device port number. */ 486 struct rte_pci_device *pci_dev; /* Backend PCI device. */ 487 struct rte_ether_addr mac[MLX5_MAX_MAC_ADDRESSES]; /* MAC addresses. */ 488 BITFIELD_DECLARE(mac_own, uint64_t, MLX5_MAX_MAC_ADDRESSES); 489 /* Bit-field of MAC addresses owned by the PMD. */ 490 uint16_t vlan_filter[MLX5_MAX_VLAN_IDS]; /* VLAN filters table. */ 491 unsigned int vlan_filter_n; /* Number of configured VLAN filters. */ 492 /* Device properties. */ 493 uint16_t mtu; /* Configured MTU. */ 494 unsigned int isolated:1; /* Whether isolated mode is enabled. */ 495 unsigned int representor:1; /* Device is a port representor. */ 496 unsigned int master:1; /* Device is a E-Switch master. */ 497 unsigned int dr_shared:1; /* DV/DR data is shared. */ 498 unsigned int counter_fallback:1; /* Use counter fallback management. */ 499 unsigned int mtr_en:1; /* Whether support meter. */ 500 unsigned int mtr_reg_share:1; /* Whether support meter REG_C share. */ 501 uint16_t domain_id; /* Switch domain identifier. */ 502 uint16_t vport_id; /* Associated VF vport index (if any). */ 503 uint32_t vport_meta_tag; /* Used for vport index match ove VF LAG. */ 504 uint32_t vport_meta_mask; /* Used for vport index field match mask. */ 505 int32_t representor_id; /* Port representor identifier. */ 506 int32_t pf_bond; /* >=0 means PF index in bonding configuration. */ 507 unsigned int if_index; /* Associated kernel network device index. */ 508 /* RX/TX queues. */ 509 unsigned int rxqs_n; /* RX queues array size. */ 510 unsigned int txqs_n; /* TX queues array size. */ 511 struct mlx5_rxq_data *(*rxqs)[]; /* RX queues. */ 512 struct mlx5_txq_data *(*txqs)[]; /* TX queues. */ 513 struct rte_mempool *mprq_mp; /* Mempool for Multi-Packet RQ. */ 514 struct rte_eth_rss_conf rss_conf; /* RSS configuration. */ 515 unsigned int (*reta_idx)[]; /* RETA index table. */ 516 unsigned int reta_idx_n; /* RETA index size. */ 517 struct mlx5_drop drop_queue; /* Flow drop queues. */ 518 struct mlx5_flows flows; /* RTE Flow rules. */ 519 struct mlx5_flows ctrl_flows; /* Control flow rules. */ 520 LIST_HEAD(rxq, mlx5_rxq_ctrl) rxqsctrl; /* DPDK Rx queues. */ 521 LIST_HEAD(rxqobj, mlx5_rxq_obj) rxqsobj; /* Verbs/DevX Rx queues. */ 522 LIST_HEAD(hrxq, mlx5_hrxq) hrxqs; /* Verbs Hash Rx queues. */ 523 LIST_HEAD(txq, mlx5_txq_ctrl) txqsctrl; /* DPDK Tx queues. */ 524 LIST_HEAD(txqobj, mlx5_txq_obj) txqsobj; /* Verbs/DevX Tx queues. */ 525 /* Indirection tables. */ 526 LIST_HEAD(ind_tables, mlx5_ind_table_obj) ind_tbls; 527 /* Pointer to next element. */ 528 rte_atomic32_t refcnt; /**< Reference counter. */ 529 struct ibv_flow_action *verbs_action; 530 /**< Verbs modify header action object. */ 531 uint8_t ft_type; /**< Flow table type, Rx or Tx. */ 532 uint8_t max_lro_msg_size; 533 /* Tags resources cache. */ 534 uint32_t link_speed_capa; /* Link speed capabilities. */ 535 struct mlx5_xstats_ctrl xstats_ctrl; /* Extended stats control. */ 536 struct mlx5_stats_ctrl stats_ctrl; /* Stats control. */ 537 struct mlx5_dev_config config; /* Device configuration. */ 538 struct mlx5_verbs_alloc_ctx verbs_alloc_ctx; 539 /* Context for Verbs allocator. */ 540 int nl_socket_rdma; /* Netlink socket (NETLINK_RDMA). */ 541 int nl_socket_route; /* Netlink socket (NETLINK_ROUTE). */ 542 LIST_HEAD(dbrpage, mlx5_devx_dbr_page) dbrpgs; /* Door-bell pages. */ 543 struct mlx5_nl_vlan_vmwa_context *vmwa_context; /* VLAN WA context. */ 544 struct mlx5_flow_id_pool *qrss_id_pool; 545 struct mlx5_hlist *mreg_cp_tbl; 546 /* Hash table of Rx metadata register copy table. */ 547 uint8_t mtr_sfx_reg; /* Meter prefix-suffix flow match REG_C. */ 548 uint8_t mtr_color_reg; /* Meter color match REG_C. */ 549 struct mlx5_mtr_profiles flow_meter_profiles; /* MTR profile list. */ 550 struct mlx5_flow_meters flow_meters; /* MTR list. */ 551 #ifndef RTE_ARCH_64 552 rte_spinlock_t uar_lock_cq; /* CQs share a common distinct UAR */ 553 rte_spinlock_t uar_lock[MLX5_UAR_PAGE_NUM_MAX]; 554 /* UAR same-page access control required in 32bit implementations. */ 555 #endif 556 uint8_t skip_default_rss_reta; /* Skip configuration of default reta. */ 557 uint8_t fdb_def_rule; /* Whether fdb jump to table 1 is configured. */ 558 }; 559 560 #define PORT_ID(priv) ((priv)->dev_data->port_id) 561 #define ETH_DEV(priv) (&rte_eth_devices[PORT_ID(priv)]) 562 563 /* mlx5.c */ 564 565 int mlx5_getenv_int(const char *); 566 int mlx5_proc_priv_init(struct rte_eth_dev *dev); 567 int64_t mlx5_get_dbr(struct rte_eth_dev *dev, 568 struct mlx5_devx_dbr_page **dbr_page); 569 int32_t mlx5_release_dbr(struct rte_eth_dev *dev, uint32_t umem_id, 570 uint64_t offset); 571 int mlx5_udp_tunnel_port_add(struct rte_eth_dev *dev, 572 struct rte_eth_udp_tunnel *udp_tunnel); 573 uint16_t mlx5_eth_find_next(uint16_t port_id, struct rte_pci_device *pci_dev); 574 575 /* Macro to iterate over all valid ports for mlx5 driver. */ 576 #define MLX5_ETH_FOREACH_DEV(port_id, pci_dev) \ 577 for (port_id = mlx5_eth_find_next(0, pci_dev); \ 578 port_id < RTE_MAX_ETHPORTS; \ 579 port_id = mlx5_eth_find_next(port_id + 1, pci_dev)) 580 581 /* mlx5_ethdev.c */ 582 583 int mlx5_get_ifname(const struct rte_eth_dev *dev, char (*ifname)[IF_NAMESIZE]); 584 int mlx5_get_master_ifname(const char *ibdev_path, char (*ifname)[IF_NAMESIZE]); 585 unsigned int mlx5_ifindex(const struct rte_eth_dev *dev); 586 int mlx5_ifreq(const struct rte_eth_dev *dev, int req, struct ifreq *ifr); 587 int mlx5_get_mtu(struct rte_eth_dev *dev, uint16_t *mtu); 588 int mlx5_set_flags(struct rte_eth_dev *dev, unsigned int keep, 589 unsigned int flags); 590 int mlx5_dev_configure(struct rte_eth_dev *dev); 591 int mlx5_dev_infos_get(struct rte_eth_dev *dev, struct rte_eth_dev_info *info); 592 int mlx5_read_clock(struct rte_eth_dev *dev, uint64_t *clock); 593 int mlx5_fw_version_get(struct rte_eth_dev *dev, char *fw_ver, size_t fw_size); 594 const uint32_t *mlx5_dev_supported_ptypes_get(struct rte_eth_dev *dev); 595 int mlx5_link_update(struct rte_eth_dev *dev, int wait_to_complete); 596 int mlx5_force_link_status_change(struct rte_eth_dev *dev, int status); 597 int mlx5_dev_set_mtu(struct rte_eth_dev *dev, uint16_t mtu); 598 int mlx5_dev_get_flow_ctrl(struct rte_eth_dev *dev, 599 struct rte_eth_fc_conf *fc_conf); 600 int mlx5_dev_set_flow_ctrl(struct rte_eth_dev *dev, 601 struct rte_eth_fc_conf *fc_conf); 602 void mlx5_dev_link_status_handler(void *arg); 603 void mlx5_dev_interrupt_handler(void *arg); 604 void mlx5_dev_interrupt_handler_devx(void *arg); 605 void mlx5_dev_interrupt_handler_uninstall(struct rte_eth_dev *dev); 606 void mlx5_dev_interrupt_handler_install(struct rte_eth_dev *dev); 607 void mlx5_dev_interrupt_handler_devx_uninstall(struct rte_eth_dev *dev); 608 void mlx5_dev_interrupt_handler_devx_install(struct rte_eth_dev *dev); 609 int mlx5_set_link_down(struct rte_eth_dev *dev); 610 int mlx5_set_link_up(struct rte_eth_dev *dev); 611 int mlx5_is_removed(struct rte_eth_dev *dev); 612 eth_tx_burst_t mlx5_select_tx_function(struct rte_eth_dev *dev); 613 eth_rx_burst_t mlx5_select_rx_function(struct rte_eth_dev *dev); 614 struct mlx5_priv *mlx5_port_to_eswitch_info(uint16_t port, bool valid); 615 struct mlx5_priv *mlx5_dev_to_eswitch_info(struct rte_eth_dev *dev); 616 int mlx5_sysfs_switch_info(unsigned int ifindex, 617 struct mlx5_switch_info *info); 618 void mlx5_sysfs_check_switch_info(bool device_dir, 619 struct mlx5_switch_info *switch_info); 620 void mlx5_translate_port_name(const char *port_name_in, 621 struct mlx5_switch_info *port_info_out); 622 void mlx5_intr_callback_unregister(const struct rte_intr_handle *handle, 623 rte_intr_callback_fn cb_fn, void *cb_arg); 624 int mlx5_get_module_info(struct rte_eth_dev *dev, 625 struct rte_eth_dev_module_info *modinfo); 626 int mlx5_get_module_eeprom(struct rte_eth_dev *dev, 627 struct rte_dev_eeprom_info *info); 628 int mlx5_hairpin_cap_get(struct rte_eth_dev *dev, 629 struct rte_eth_hairpin_cap *cap); 630 int mlx5_dev_configure_rss_reta(struct rte_eth_dev *dev); 631 632 /* mlx5_mac.c */ 633 634 int mlx5_get_mac(struct rte_eth_dev *dev, uint8_t (*mac)[RTE_ETHER_ADDR_LEN]); 635 void mlx5_mac_addr_remove(struct rte_eth_dev *dev, uint32_t index); 636 int mlx5_mac_addr_add(struct rte_eth_dev *dev, struct rte_ether_addr *mac, 637 uint32_t index, uint32_t vmdq); 638 struct mlx5_nl_vlan_vmwa_context *mlx5_vlan_vmwa_init 639 (struct rte_eth_dev *dev, uint32_t ifindex); 640 int mlx5_mac_addr_set(struct rte_eth_dev *dev, struct rte_ether_addr *mac_addr); 641 int mlx5_set_mc_addr_list(struct rte_eth_dev *dev, 642 struct rte_ether_addr *mc_addr_set, 643 uint32_t nb_mc_addr); 644 645 /* mlx5_rss.c */ 646 647 int mlx5_rss_hash_update(struct rte_eth_dev *dev, 648 struct rte_eth_rss_conf *rss_conf); 649 int mlx5_rss_hash_conf_get(struct rte_eth_dev *dev, 650 struct rte_eth_rss_conf *rss_conf); 651 int mlx5_rss_reta_index_resize(struct rte_eth_dev *dev, unsigned int reta_size); 652 int mlx5_dev_rss_reta_query(struct rte_eth_dev *dev, 653 struct rte_eth_rss_reta_entry64 *reta_conf, 654 uint16_t reta_size); 655 int mlx5_dev_rss_reta_update(struct rte_eth_dev *dev, 656 struct rte_eth_rss_reta_entry64 *reta_conf, 657 uint16_t reta_size); 658 659 /* mlx5_rxmode.c */ 660 661 int mlx5_promiscuous_enable(struct rte_eth_dev *dev); 662 int mlx5_promiscuous_disable(struct rte_eth_dev *dev); 663 int mlx5_allmulticast_enable(struct rte_eth_dev *dev); 664 int mlx5_allmulticast_disable(struct rte_eth_dev *dev); 665 666 /* mlx5_stats.c */ 667 668 void mlx5_stats_init(struct rte_eth_dev *dev); 669 int mlx5_stats_get(struct rte_eth_dev *dev, struct rte_eth_stats *stats); 670 int mlx5_stats_reset(struct rte_eth_dev *dev); 671 int mlx5_xstats_get(struct rte_eth_dev *dev, struct rte_eth_xstat *stats, 672 unsigned int n); 673 int mlx5_xstats_reset(struct rte_eth_dev *dev); 674 int mlx5_xstats_get_names(struct rte_eth_dev *dev __rte_unused, 675 struct rte_eth_xstat_name *xstats_names, 676 unsigned int n); 677 678 /* mlx5_vlan.c */ 679 680 int mlx5_vlan_filter_set(struct rte_eth_dev *dev, uint16_t vlan_id, int on); 681 void mlx5_vlan_strip_queue_set(struct rte_eth_dev *dev, uint16_t queue, int on); 682 int mlx5_vlan_offload_set(struct rte_eth_dev *dev, int mask); 683 void mlx5_vlan_vmwa_exit(struct mlx5_nl_vlan_vmwa_context *ctx); 684 void mlx5_vlan_vmwa_release(struct rte_eth_dev *dev, 685 struct mlx5_vf_vlan *vf_vlan); 686 void mlx5_vlan_vmwa_acquire(struct rte_eth_dev *dev, 687 struct mlx5_vf_vlan *vf_vlan); 688 689 /* mlx5_trigger.c */ 690 691 int mlx5_dev_start(struct rte_eth_dev *dev); 692 void mlx5_dev_stop(struct rte_eth_dev *dev); 693 int mlx5_traffic_enable(struct rte_eth_dev *dev); 694 void mlx5_traffic_disable(struct rte_eth_dev *dev); 695 int mlx5_traffic_restart(struct rte_eth_dev *dev); 696 697 /* mlx5_flow.c */ 698 699 int mlx5_flow_discover_mreg_c(struct rte_eth_dev *eth_dev); 700 bool mlx5_flow_ext_mreg_supported(struct rte_eth_dev *dev); 701 int mlx5_flow_discover_priorities(struct rte_eth_dev *dev); 702 void mlx5_flow_print(struct rte_flow *flow); 703 int mlx5_flow_validate(struct rte_eth_dev *dev, 704 const struct rte_flow_attr *attr, 705 const struct rte_flow_item items[], 706 const struct rte_flow_action actions[], 707 struct rte_flow_error *error); 708 struct rte_flow *mlx5_flow_create(struct rte_eth_dev *dev, 709 const struct rte_flow_attr *attr, 710 const struct rte_flow_item items[], 711 const struct rte_flow_action actions[], 712 struct rte_flow_error *error); 713 int mlx5_flow_destroy(struct rte_eth_dev *dev, struct rte_flow *flow, 714 struct rte_flow_error *error); 715 void mlx5_flow_list_flush(struct rte_eth_dev *dev, struct mlx5_flows *list); 716 int mlx5_flow_flush(struct rte_eth_dev *dev, struct rte_flow_error *error); 717 int mlx5_flow_query(struct rte_eth_dev *dev, struct rte_flow *flow, 718 const struct rte_flow_action *action, void *data, 719 struct rte_flow_error *error); 720 int mlx5_flow_isolate(struct rte_eth_dev *dev, int enable, 721 struct rte_flow_error *error); 722 int mlx5_dev_filter_ctrl(struct rte_eth_dev *dev, 723 enum rte_filter_type filter_type, 724 enum rte_filter_op filter_op, 725 void *arg); 726 int mlx5_flow_start(struct rte_eth_dev *dev, struct mlx5_flows *list); 727 void mlx5_flow_stop(struct rte_eth_dev *dev, struct mlx5_flows *list); 728 int mlx5_flow_verify(struct rte_eth_dev *dev); 729 int mlx5_ctrl_flow_source_queue(struct rte_eth_dev *dev, uint32_t queue); 730 int mlx5_ctrl_flow_vlan(struct rte_eth_dev *dev, 731 struct rte_flow_item_eth *eth_spec, 732 struct rte_flow_item_eth *eth_mask, 733 struct rte_flow_item_vlan *vlan_spec, 734 struct rte_flow_item_vlan *vlan_mask); 735 int mlx5_ctrl_flow(struct rte_eth_dev *dev, 736 struct rte_flow_item_eth *eth_spec, 737 struct rte_flow_item_eth *eth_mask); 738 struct rte_flow *mlx5_flow_create_esw_table_zero_flow(struct rte_eth_dev *dev); 739 int mlx5_flow_create_drop_queue(struct rte_eth_dev *dev); 740 void mlx5_flow_delete_drop_queue(struct rte_eth_dev *dev); 741 void mlx5_flow_async_pool_query_handle(struct mlx5_ibv_shared *sh, 742 uint64_t async_id, int status); 743 void mlx5_set_query_alarm(struct mlx5_ibv_shared *sh); 744 void mlx5_flow_query_alarm(void *arg); 745 struct mlx5_flow_counter *mlx5_counter_alloc(struct rte_eth_dev *dev); 746 void mlx5_counter_free(struct rte_eth_dev *dev, struct mlx5_flow_counter *cnt); 747 int mlx5_counter_query(struct rte_eth_dev *dev, struct mlx5_flow_counter *cnt, 748 bool clear, uint64_t *pkts, uint64_t *bytes); 749 int mlx5_flow_dev_dump(struct rte_eth_dev *dev, FILE *file, 750 struct rte_flow_error *error); 751 752 /* mlx5_mp.c */ 753 void mlx5_mp_req_start_rxtx(struct rte_eth_dev *dev); 754 void mlx5_mp_req_stop_rxtx(struct rte_eth_dev *dev); 755 int mlx5_mp_req_mr_create(struct rte_eth_dev *dev, uintptr_t addr); 756 int mlx5_mp_req_verbs_cmd_fd(struct rte_eth_dev *dev); 757 int mlx5_mp_req_queue_state_modify(struct rte_eth_dev *dev, 758 struct mlx5_mp_arg_queue_state_modify *sm); 759 int mlx5_mp_init_primary(void); 760 void mlx5_mp_uninit_primary(void); 761 int mlx5_mp_init_secondary(void); 762 void mlx5_mp_uninit_secondary(void); 763 764 /* mlx5_socket.c */ 765 766 int mlx5_pmd_socket_init(void); 767 void mlx5_pmd_socket_uninit(void); 768 769 /* mlx5_flow_meter.c */ 770 771 int mlx5_flow_meter_ops_get(struct rte_eth_dev *dev, void *arg); 772 struct mlx5_flow_meter *mlx5_flow_meter_find(struct mlx5_priv *priv, 773 uint32_t meter_id); 774 struct mlx5_flow_meter *mlx5_flow_meter_attach 775 (struct mlx5_priv *priv, 776 uint32_t meter_id, 777 const struct rte_flow_attr *attr, 778 struct rte_flow_error *error); 779 void mlx5_flow_meter_detach(struct mlx5_flow_meter *fm); 780 781 #endif /* RTE_PMD_MLX5_H_ */ 782