1 /* SPDX-License-Identifier: BSD-3-Clause 2 * Copyright 2015 6WIND S.A. 3 * Copyright 2015 Mellanox Technologies, Ltd 4 */ 5 6 #ifndef RTE_PMD_MLX5_H_ 7 #define RTE_PMD_MLX5_H_ 8 9 #include <stddef.h> 10 #include <stdbool.h> 11 #include <stdint.h> 12 #include <limits.h> 13 #include <netinet/in.h> 14 #include <sys/queue.h> 15 16 #include <rte_pci.h> 17 #include <rte_ether.h> 18 #include <ethdev_driver.h> 19 #include <rte_rwlock.h> 20 #include <rte_interrupts.h> 21 #include <rte_errno.h> 22 #include <rte_flow.h> 23 24 #include <mlx5_glue.h> 25 #include <mlx5_devx_cmds.h> 26 #include <mlx5_prm.h> 27 #include <mlx5_common_mp.h> 28 #include <mlx5_common_mr.h> 29 #include <mlx5_common_devx.h> 30 31 #include "mlx5_defs.h" 32 #include "mlx5_utils.h" 33 #include "mlx5_os.h" 34 #include "mlx5_autoconf.h" 35 36 37 #define MLX5_SH(dev) (((struct mlx5_priv *)(dev)->data->dev_private)->sh) 38 39 enum mlx5_ipool_index { 40 #if defined(HAVE_IBV_FLOW_DV_SUPPORT) || !defined(HAVE_INFINIBAND_VERBS_H) 41 MLX5_IPOOL_DECAP_ENCAP = 0, /* Pool for encap/decap resource. */ 42 MLX5_IPOOL_PUSH_VLAN, /* Pool for push vlan resource. */ 43 MLX5_IPOOL_TAG, /* Pool for tag resource. */ 44 MLX5_IPOOL_PORT_ID, /* Pool for port id resource. */ 45 MLX5_IPOOL_JUMP, /* Pool for jump resource. */ 46 MLX5_IPOOL_SAMPLE, /* Pool for sample resource. */ 47 MLX5_IPOOL_DEST_ARRAY, /* Pool for destination array resource. */ 48 MLX5_IPOOL_TUNNEL_ID, /* Pool for tunnel offload context */ 49 MLX5_IPOOL_TNL_TBL_ID, /* Pool for tunnel table ID. */ 50 #endif 51 MLX5_IPOOL_MTR, /* Pool for meter resource. */ 52 MLX5_IPOOL_MCP, /* Pool for metadata resource. */ 53 MLX5_IPOOL_HRXQ, /* Pool for hrxq resource. */ 54 MLX5_IPOOL_MLX5_FLOW, /* Pool for mlx5 flow handle. */ 55 MLX5_IPOOL_RTE_FLOW, /* Pool for rte_flow. */ 56 MLX5_IPOOL_RSS_EXPANTION_FLOW_ID, /* Pool for Queue/RSS flow ID. */ 57 MLX5_IPOOL_RSS_SHARED_ACTIONS, /* Pool for RSS shared actions. */ 58 MLX5_IPOOL_MAX, 59 }; 60 61 /* 62 * There are three reclaim memory mode supported. 63 * 0(none) means no memory reclaim. 64 * 1(light) means only PMD level reclaim. 65 * 2(aggressive) means both PMD and rdma-core level reclaim. 66 */ 67 enum mlx5_reclaim_mem_mode { 68 MLX5_RCM_NONE, /* Don't reclaim memory. */ 69 MLX5_RCM_LIGHT, /* Reclaim PMD level. */ 70 MLX5_RCM_AGGR, /* Reclaim PMD and rdma-core level. */ 71 }; 72 73 /* Hash and cache list callback context. */ 74 struct mlx5_flow_cb_ctx { 75 struct rte_eth_dev *dev; 76 struct rte_flow_error *error; 77 void *data; 78 }; 79 80 /* Device attributes used in mlx5 PMD */ 81 struct mlx5_dev_attr { 82 uint64_t device_cap_flags_ex; 83 int max_qp_wr; 84 int max_sge; 85 int max_cq; 86 int max_qp; 87 int max_cqe; 88 uint32_t max_pd; 89 uint32_t max_mr; 90 uint32_t max_srq; 91 uint32_t max_srq_wr; 92 uint32_t raw_packet_caps; 93 uint32_t max_rwq_indirection_table_size; 94 uint32_t max_tso; 95 uint32_t tso_supported_qpts; 96 uint64_t flags; 97 uint64_t comp_mask; 98 uint32_t sw_parsing_offloads; 99 uint32_t min_single_stride_log_num_of_bytes; 100 uint32_t max_single_stride_log_num_of_bytes; 101 uint32_t min_single_wqe_log_num_of_strides; 102 uint32_t max_single_wqe_log_num_of_strides; 103 uint32_t stride_supported_qpts; 104 uint32_t tunnel_offloads_caps; 105 char fw_ver[64]; 106 }; 107 108 /** Data associated with devices to spawn. */ 109 struct mlx5_dev_spawn_data { 110 uint32_t ifindex; /**< Network interface index. */ 111 uint32_t max_port; /**< Device maximal port index. */ 112 uint32_t phys_port; /**< Device physical port index. */ 113 int pf_bond; /**< bonding device PF index. < 0 - no bonding */ 114 struct mlx5_switch_info info; /**< Switch information. */ 115 void *phys_dev; /**< Associated physical device. */ 116 struct rte_eth_dev *eth_dev; /**< Associated Ethernet device. */ 117 struct rte_pci_device *pci_dev; /**< Backend PCI device. */ 118 struct mlx5_bond_info *bond_info; 119 }; 120 121 /** Key string for IPC. */ 122 #define MLX5_MP_NAME "net_mlx5_mp" 123 124 125 LIST_HEAD(mlx5_dev_list, mlx5_dev_ctx_shared); 126 127 /* Shared data between primary and secondary processes. */ 128 struct mlx5_shared_data { 129 rte_spinlock_t lock; 130 /* Global spinlock for primary and secondary processes. */ 131 int init_done; /* Whether primary has done initialization. */ 132 unsigned int secondary_cnt; /* Number of secondary processes init'd. */ 133 struct mlx5_dev_list mem_event_cb_list; 134 rte_rwlock_t mem_event_rwlock; 135 }; 136 137 /* Per-process data structure, not visible to other processes. */ 138 struct mlx5_local_data { 139 int init_done; /* Whether a secondary has done initialization. */ 140 }; 141 142 extern struct mlx5_shared_data *mlx5_shared_data; 143 144 /* Dev ops structs */ 145 extern const struct eth_dev_ops mlx5_dev_ops; 146 extern const struct eth_dev_ops mlx5_dev_sec_ops; 147 extern const struct eth_dev_ops mlx5_dev_ops_isolate; 148 149 struct mlx5_counter_ctrl { 150 /* Name of the counter. */ 151 char dpdk_name[RTE_ETH_XSTATS_NAME_SIZE]; 152 /* Name of the counter on the device table. */ 153 char ctr_name[RTE_ETH_XSTATS_NAME_SIZE]; 154 uint32_t dev:1; /**< Nonzero for dev counters. */ 155 }; 156 157 struct mlx5_xstats_ctrl { 158 /* Number of device stats. */ 159 uint16_t stats_n; 160 /* Number of device stats identified by PMD. */ 161 uint16_t mlx5_stats_n; 162 /* Index in the device counters table. */ 163 uint16_t dev_table_idx[MLX5_MAX_XSTATS]; 164 uint64_t base[MLX5_MAX_XSTATS]; 165 uint64_t xstats[MLX5_MAX_XSTATS]; 166 uint64_t hw_stats[MLX5_MAX_XSTATS]; 167 struct mlx5_counter_ctrl info[MLX5_MAX_XSTATS]; 168 }; 169 170 struct mlx5_stats_ctrl { 171 /* Base for imissed counter. */ 172 uint64_t imissed_base; 173 uint64_t imissed; 174 }; 175 176 /* Default PMD specific parameter value. */ 177 #define MLX5_ARG_UNSET (-1) 178 179 #define MLX5_LRO_SUPPORTED(dev) \ 180 (((struct mlx5_priv *)((dev)->data->dev_private))->config.lro.supported) 181 182 /* Maximal size of coalesced segment for LRO is set in chunks of 256 Bytes. */ 183 #define MLX5_LRO_SEG_CHUNK_SIZE 256u 184 185 /* Maximal size of aggregated LRO packet. */ 186 #define MLX5_MAX_LRO_SIZE (UINT8_MAX * MLX5_LRO_SEG_CHUNK_SIZE) 187 188 /* Maximal number of segments to split. */ 189 #define MLX5_MAX_RXQ_NSEG (1u << MLX5_MAX_LOG_RQ_SEGS) 190 191 /* LRO configurations structure. */ 192 struct mlx5_lro_config { 193 uint32_t supported:1; /* Whether LRO is supported. */ 194 uint32_t timeout; /* User configuration. */ 195 }; 196 197 /* 198 * Device configuration structure. 199 * 200 * Merged configuration from: 201 * 202 * - Device capabilities, 203 * - User device parameters disabled features. 204 */ 205 struct mlx5_dev_config { 206 unsigned int hw_csum:1; /* Checksum offload is supported. */ 207 unsigned int hw_vlan_strip:1; /* VLAN stripping is supported. */ 208 unsigned int hw_vlan_insert:1; /* VLAN insertion in WQE is supported. */ 209 unsigned int hw_fcs_strip:1; /* FCS stripping is supported. */ 210 unsigned int hw_padding:1; /* End alignment padding is supported. */ 211 unsigned int vf:1; /* This is a VF. */ 212 unsigned int tunnel_en:1; 213 /* Whether tunnel stateless offloads are supported. */ 214 unsigned int mpls_en:1; /* MPLS over GRE/UDP is enabled. */ 215 unsigned int cqe_comp:1; /* CQE compression is enabled. */ 216 unsigned int cqe_comp_fmt:3; /* CQE compression format. */ 217 unsigned int tso:1; /* Whether TSO is supported. */ 218 unsigned int rx_vec_en:1; /* Rx vector is enabled. */ 219 unsigned int mr_ext_memseg_en:1; 220 /* Whether memseg should be extended for MR creation. */ 221 unsigned int l3_vxlan_en:1; /* Enable L3 VXLAN flow creation. */ 222 unsigned int vf_nl_en:1; /* Enable Netlink requests in VF mode. */ 223 unsigned int dv_esw_en:1; /* Enable E-Switch DV flow. */ 224 unsigned int dv_flow_en:1; /* Enable DV flow. */ 225 unsigned int dv_xmeta_en:2; /* Enable extensive flow metadata. */ 226 unsigned int lacp_by_user:1; 227 /* Enable user to manage LACP traffic. */ 228 unsigned int swp:1; /* Tx generic tunnel checksum and TSO offload. */ 229 unsigned int devx:1; /* Whether devx interface is available or not. */ 230 unsigned int dest_tir:1; /* Whether advanced DR API is available. */ 231 unsigned int reclaim_mode:2; /* Memory reclaim mode. */ 232 unsigned int rt_timestamp:1; /* realtime timestamp format. */ 233 unsigned int sys_mem_en:1; /* The default memory allocator. */ 234 unsigned int decap_en:1; /* Whether decap will be used or not. */ 235 unsigned int dv_miss_info:1; /* restore packet after partial hw miss */ 236 struct { 237 unsigned int enabled:1; /* Whether MPRQ is enabled. */ 238 unsigned int stride_num_n; /* Number of strides. */ 239 unsigned int stride_size_n; /* Size of a stride. */ 240 unsigned int min_stride_size_n; /* Min size of a stride. */ 241 unsigned int max_stride_size_n; /* Max size of a stride. */ 242 unsigned int max_memcpy_len; 243 /* Maximum packet size to memcpy Rx packets. */ 244 unsigned int min_rxqs_num; 245 /* Rx queue count threshold to enable MPRQ. */ 246 } mprq; /* Configurations for Multi-Packet RQ. */ 247 int mps; /* Multi-packet send supported mode. */ 248 int dbnc; /* Skip doorbell register write barrier. */ 249 unsigned int flow_prio; /* Number of flow priorities. */ 250 enum modify_reg flow_mreg_c[MLX5_MREG_C_NUM]; 251 /* Availibility of mreg_c's. */ 252 unsigned int tso_max_payload_sz; /* Maximum TCP payload for TSO. */ 253 unsigned int ind_table_max_size; /* Maximum indirection table size. */ 254 unsigned int max_dump_files_num; /* Maximum dump files per queue. */ 255 unsigned int log_hp_size; /* Single hairpin queue data size in total. */ 256 int txqs_inline; /* Queue number threshold for inlining. */ 257 int txq_inline_min; /* Minimal amount of data bytes to inline. */ 258 int txq_inline_max; /* Max packet size for inlining with SEND. */ 259 int txq_inline_mpw; /* Max packet size for inlining with eMPW. */ 260 int tx_pp; /* Timestamp scheduling granularity in nanoseconds. */ 261 int tx_skew; /* Tx scheduling skew between WQE and data on wire. */ 262 struct mlx5_hca_attr hca_attr; /* HCA attributes. */ 263 struct mlx5_lro_config lro; /* LRO configuration. */ 264 }; 265 266 267 /* Structure for VF VLAN workaround. */ 268 struct mlx5_vf_vlan { 269 uint32_t tag:12; 270 uint32_t created:1; 271 }; 272 273 /* Flow drop context necessary due to Verbs API. */ 274 struct mlx5_drop { 275 struct mlx5_hrxq *hrxq; /* Hash Rx queue queue. */ 276 struct mlx5_rxq_obj *rxq; /* Rx queue object. */ 277 }; 278 279 #define MLX5_COUNTERS_PER_POOL 512 280 #define MLX5_MAX_PENDING_QUERIES 4 281 #define MLX5_CNT_CONTAINER_RESIZE 64 282 #define MLX5_CNT_SHARED_OFFSET 0x80000000 283 #define IS_SHARED_CNT(cnt) (!!((cnt) & MLX5_CNT_SHARED_OFFSET)) 284 #define IS_BATCH_CNT(cnt) (((cnt) & (MLX5_CNT_SHARED_OFFSET - 1)) >= \ 285 MLX5_CNT_BATCH_OFFSET) 286 #define MLX5_CNT_SIZE (sizeof(struct mlx5_flow_counter)) 287 #define MLX5_AGE_SIZE (sizeof(struct mlx5_age_param)) 288 289 #define MLX5_CNT_LEN(pool) \ 290 (MLX5_CNT_SIZE + \ 291 ((pool)->is_aged ? MLX5_AGE_SIZE : 0)) 292 #define MLX5_POOL_GET_CNT(pool, index) \ 293 ((struct mlx5_flow_counter *) \ 294 ((uint8_t *)((pool) + 1) + (index) * (MLX5_CNT_LEN(pool)))) 295 #define MLX5_CNT_ARRAY_IDX(pool, cnt) \ 296 ((int)(((uint8_t *)(cnt) - (uint8_t *)((pool) + 1)) / \ 297 MLX5_CNT_LEN(pool))) 298 /* 299 * The pool index and offset of counter in the pool array makes up the 300 * counter index. In case the counter is from pool 0 and offset 0, it 301 * should plus 1 to avoid index 0, since 0 means invalid counter index 302 * currently. 303 */ 304 #define MLX5_MAKE_CNT_IDX(pi, offset) \ 305 ((pi) * MLX5_COUNTERS_PER_POOL + (offset) + 1) 306 #define MLX5_CNT_TO_AGE(cnt) \ 307 ((struct mlx5_age_param *)((cnt) + 1)) 308 /* 309 * The maximum single counter is 0x800000 as MLX5_CNT_BATCH_OFFSET 310 * defines. The pool size is 512, pool index should never reach 311 * INT16_MAX. 312 */ 313 #define POOL_IDX_INVALID UINT16_MAX 314 315 /* Age status. */ 316 enum { 317 AGE_FREE, /* Initialized state. */ 318 AGE_CANDIDATE, /* Counter assigned to flows. */ 319 AGE_TMOUT, /* Timeout, wait for rte_flow_get_aged_flows and destroy. */ 320 }; 321 322 enum mlx5_counter_type { 323 MLX5_COUNTER_TYPE_ORIGIN, 324 MLX5_COUNTER_TYPE_AGE, 325 MLX5_COUNTER_TYPE_MAX, 326 }; 327 328 /* Counter age parameter. */ 329 struct mlx5_age_param { 330 uint16_t state; /**< Age state (atomically accessed). */ 331 uint16_t port_id; /**< Port id of the counter. */ 332 uint32_t timeout:24; /**< Aging timeout in seconds. */ 333 uint32_t sec_since_last_hit; 334 /**< Time in seconds since last hit (atomically accessed). */ 335 void *context; /**< Flow counter age context. */ 336 }; 337 338 struct flow_counter_stats { 339 uint64_t hits; 340 uint64_t bytes; 341 }; 342 343 /* Shared counters information for counters. */ 344 struct mlx5_flow_counter_shared { 345 uint32_t id; /**< User counter ID. */ 346 }; 347 348 /* Shared counter configuration. */ 349 struct mlx5_shared_counter_conf { 350 struct rte_eth_dev *dev; /* The device shared counter belongs to. */ 351 uint32_t id; /* The shared counter ID. */ 352 }; 353 354 struct mlx5_flow_counter_pool; 355 /* Generic counters information. */ 356 struct mlx5_flow_counter { 357 union { 358 /* 359 * User-defined counter shared info is only used during 360 * counter active time. And aging counter sharing is not 361 * supported, so active shared counter will not be chained 362 * to the aging list. For shared counter, only when it is 363 * released, the TAILQ entry memory will be used, at that 364 * time, shared memory is not used anymore. 365 * 366 * Similarly to none-batch counter dcs, since it doesn't 367 * support aging, while counter is allocated, the entry 368 * memory is not used anymore. In this case, as bytes 369 * memory is used only when counter is allocated, and 370 * entry memory is used only when counter is free. The 371 * dcs pointer can be saved to these two different place 372 * at different stage. It will eliminate the individual 373 * counter extend struct. 374 */ 375 TAILQ_ENTRY(mlx5_flow_counter) next; 376 /**< Pointer to the next flow counter structure. */ 377 struct { 378 struct mlx5_flow_counter_shared shared_info; 379 /**< Shared counter information. */ 380 void *dcs_when_active; 381 /* 382 * For non-batch mode, the dcs will be saved 383 * here when the counter is free. 384 */ 385 }; 386 }; 387 union { 388 uint64_t hits; /**< Reset value of hits packets. */ 389 struct mlx5_flow_counter_pool *pool; /**< Counter pool. */ 390 }; 391 union { 392 uint64_t bytes; /**< Reset value of bytes. */ 393 void *dcs_when_free; 394 /* 395 * For non-batch mode, the dcs will be saved here 396 * when the counter is free. 397 */ 398 }; 399 void *action; /**< Pointer to the dv action. */ 400 }; 401 402 TAILQ_HEAD(mlx5_counters, mlx5_flow_counter); 403 404 /* Generic counter pool structure - query is in pool resolution. */ 405 struct mlx5_flow_counter_pool { 406 TAILQ_ENTRY(mlx5_flow_counter_pool) next; 407 struct mlx5_counters counters[2]; /* Free counter list. */ 408 struct mlx5_devx_obj *min_dcs; 409 /* The devx object of the minimum counter ID. */ 410 uint64_t time_of_last_age_check; 411 /* System time (from rte_rdtsc()) read in the last aging check. */ 412 uint32_t index:30; /* Pool index in container. */ 413 uint32_t is_aged:1; /* Pool with aging counter. */ 414 volatile uint32_t query_gen:1; /* Query round. */ 415 rte_spinlock_t sl; /* The pool lock. */ 416 rte_spinlock_t csl; /* The pool counter free list lock. */ 417 struct mlx5_counter_stats_raw *raw; 418 struct mlx5_counter_stats_raw *raw_hw; 419 /* The raw on HW working. */ 420 }; 421 422 /* Memory management structure for group of counter statistics raws. */ 423 struct mlx5_counter_stats_mem_mng { 424 LIST_ENTRY(mlx5_counter_stats_mem_mng) next; 425 struct mlx5_counter_stats_raw *raws; 426 struct mlx5_devx_obj *dm; 427 void *umem; 428 }; 429 430 /* Raw memory structure for the counter statistics values of a pool. */ 431 struct mlx5_counter_stats_raw { 432 LIST_ENTRY(mlx5_counter_stats_raw) next; 433 struct mlx5_counter_stats_mem_mng *mem_mng; 434 volatile struct flow_counter_stats *data; 435 }; 436 437 TAILQ_HEAD(mlx5_counter_pools, mlx5_flow_counter_pool); 438 439 /* Counter global management structure. */ 440 struct mlx5_flow_counter_mng { 441 volatile uint16_t n_valid; /* Number of valid pools. */ 442 uint16_t n; /* Number of pools. */ 443 uint16_t last_pool_idx; /* Last used pool index */ 444 int min_id; /* The minimum counter ID in the pools. */ 445 int max_id; /* The maximum counter ID in the pools. */ 446 rte_spinlock_t pool_update_sl; /* The pool update lock. */ 447 rte_spinlock_t csl[MLX5_COUNTER_TYPE_MAX]; 448 /* The counter free list lock. */ 449 struct mlx5_counters counters[MLX5_COUNTER_TYPE_MAX]; 450 /* Free counter list. */ 451 struct mlx5_flow_counter_pool **pools; /* Counter pool array. */ 452 struct mlx5_counter_stats_mem_mng *mem_mng; 453 /* Hold the memory management for the next allocated pools raws. */ 454 struct mlx5_counters flow_counters; /* Legacy flow counter list. */ 455 uint8_t pending_queries; 456 uint16_t pool_index; 457 uint8_t query_thread_on; 458 bool relaxed_ordering_read; 459 bool relaxed_ordering_write; 460 bool counter_fallback; /* Use counter fallback management. */ 461 LIST_HEAD(mem_mngs, mlx5_counter_stats_mem_mng) mem_mngs; 462 LIST_HEAD(stat_raws, mlx5_counter_stats_raw) free_stat_raws; 463 }; 464 465 /* ASO structures. */ 466 #define MLX5_ASO_QUEUE_LOG_DESC 10 467 468 struct mlx5_aso_cq { 469 uint16_t log_desc_n; 470 uint32_t cq_ci:24; 471 struct mlx5_devx_cq cq_obj; 472 uint64_t errors; 473 }; 474 475 struct mlx5_aso_devx_mr { 476 void *buf; 477 uint64_t length; 478 struct mlx5dv_devx_umem *umem; 479 struct mlx5_devx_obj *mkey; 480 bool is_indirect; 481 }; 482 483 struct mlx5_aso_sq_elem { 484 struct mlx5_aso_age_pool *pool; 485 uint16_t burst_size; 486 }; 487 488 struct mlx5_aso_sq { 489 uint16_t log_desc_n; 490 struct mlx5_aso_cq cq; 491 struct mlx5_devx_sq sq_obj; 492 volatile uint64_t *uar_addr; 493 struct mlx5_aso_devx_mr mr; 494 uint16_t pi; 495 uint32_t head; 496 uint32_t tail; 497 uint32_t sqn; 498 struct mlx5_aso_sq_elem elts[1 << MLX5_ASO_QUEUE_LOG_DESC]; 499 uint16_t next; /* Pool index of the next pool to query. */ 500 }; 501 502 struct mlx5_aso_age_action { 503 LIST_ENTRY(mlx5_aso_age_action) next; 504 void *dr_action; 505 uint32_t refcnt; 506 /* Following fields relevant only when action is active. */ 507 uint16_t offset; /* Offset of ASO Flow Hit flag in DevX object. */ 508 struct mlx5_age_param age_params; 509 }; 510 511 #define MLX5_ASO_AGE_ACTIONS_PER_POOL 512 512 513 struct mlx5_aso_age_pool { 514 struct mlx5_devx_obj *flow_hit_aso_obj; 515 uint16_t index; /* Pool index in pools array. */ 516 uint64_t time_of_last_age_check; /* In seconds. */ 517 struct mlx5_aso_age_action actions[MLX5_ASO_AGE_ACTIONS_PER_POOL]; 518 }; 519 520 LIST_HEAD(aso_age_list, mlx5_aso_age_action); 521 522 struct mlx5_aso_age_mng { 523 struct mlx5_aso_age_pool **pools; 524 uint16_t n; /* Total number of pools. */ 525 uint16_t next; /* Number of pools in use, index of next free pool. */ 526 rte_spinlock_t resize_sl; /* Lock for resize objects. */ 527 rte_spinlock_t free_sl; /* Lock for free list access. */ 528 struct aso_age_list free; /* Free age actions list - ready to use. */ 529 struct mlx5_aso_sq aso_sq; /* ASO queue objects. */ 530 }; 531 532 /* Management structure for geneve tlv option */ 533 struct mlx5_geneve_tlv_option_resource { 534 struct mlx5_devx_obj *obj; /* Pointer to the geneve tlv opt object. */ 535 rte_be16_t option_class; /* geneve tlv opt class.*/ 536 uint8_t option_type; /* geneve tlv opt type.*/ 537 uint8_t length; /* geneve tlv opt length. */ 538 uint32_t refcnt; /* geneve tlv object reference counter */ 539 }; 540 541 542 #define MLX5_AGE_EVENT_NEW 1 543 #define MLX5_AGE_TRIGGER 2 544 #define MLX5_AGE_SET(age_info, BIT) \ 545 ((age_info)->flags |= (1 << (BIT))) 546 #define MLX5_AGE_GET(age_info, BIT) \ 547 ((age_info)->flags & (1 << (BIT))) 548 #define GET_PORT_AGE_INFO(priv) \ 549 (&((priv)->sh->port[(priv)->dev_port - 1].age_info)) 550 /* Current time in seconds. */ 551 #define MLX5_CURR_TIME_SEC (rte_rdtsc() / rte_get_tsc_hz()) 552 553 /* Aging information for per port. */ 554 struct mlx5_age_info { 555 uint8_t flags; /* Indicate if is new event or need to be triggered. */ 556 struct mlx5_counters aged_counters; /* Aged counter list. */ 557 struct aso_age_list aged_aso; /* Aged ASO actions list. */ 558 rte_spinlock_t aged_sl; /* Aged flow list lock. */ 559 }; 560 561 /* Per port data of shared IB device. */ 562 struct mlx5_dev_shared_port { 563 uint32_t ih_port_id; 564 uint32_t devx_ih_port_id; 565 /* 566 * Interrupt handler port_id. Used by shared interrupt 567 * handler to find the corresponding rte_eth device 568 * by IB port index. If value is equal or greater 569 * RTE_MAX_ETHPORTS it means there is no subhandler 570 * installed for specified IB port index. 571 */ 572 struct mlx5_age_info age_info; 573 /* Aging information for per port. */ 574 }; 575 576 /* Table key of the hash organization. */ 577 union mlx5_flow_tbl_key { 578 struct { 579 /* Table ID should be at the lowest address. */ 580 uint32_t table_id; /**< ID of the table. */ 581 uint16_t dummy; /**< Dummy table for DV API. */ 582 uint8_t domain; /**< 1 - FDB, 0 - NIC TX/RX. */ 583 uint8_t direction; /**< 1 - egress, 0 - ingress. */ 584 }; 585 uint64_t v64; /**< full 64bits value of key */ 586 }; 587 588 /* Table structure. */ 589 struct mlx5_flow_tbl_resource { 590 void *obj; /**< Pointer to DR table object. */ 591 uint32_t refcnt; /**< Reference counter. */ 592 }; 593 594 #define MLX5_MAX_TABLES UINT16_MAX 595 #define MLX5_HAIRPIN_TX_TABLE (UINT16_MAX - 1) 596 /* Reserve the last two tables for metadata register copy. */ 597 #define MLX5_FLOW_MREG_ACT_TABLE_GROUP (MLX5_MAX_TABLES - 1) 598 #define MLX5_FLOW_MREG_CP_TABLE_GROUP (MLX5_MAX_TABLES - 2) 599 /* Tables for metering splits should be added here. */ 600 #define MLX5_FLOW_TABLE_LEVEL_SUFFIX (MLX5_MAX_TABLES - 3) 601 #define MLX5_FLOW_TABLE_LEVEL_METER (MLX5_MAX_TABLES - 4) 602 #define MLX5_MAX_TABLES_EXTERNAL MLX5_FLOW_TABLE_LEVEL_METER 603 #define MLX5_MAX_TABLES_FDB UINT16_MAX 604 #define MLX5_FLOW_TABLE_FACTOR 10 605 606 /* ID generation structure. */ 607 struct mlx5_flow_id_pool { 608 uint32_t *free_arr; /**< Pointer to the a array of free values. */ 609 uint32_t base_index; 610 /**< The next index that can be used without any free elements. */ 611 uint32_t *curr; /**< Pointer to the index to pop. */ 612 uint32_t *last; /**< Pointer to the last element in the empty arrray. */ 613 uint32_t max_id; /**< Maximum id can be allocated from the pool. */ 614 }; 615 616 /* Tx pacing queue structure - for Clock and Rearm queues. */ 617 struct mlx5_txpp_wq { 618 /* Completion Queue related data.*/ 619 struct mlx5_devx_cq cq_obj; 620 uint32_t cq_ci:24; 621 uint32_t arm_sn:2; 622 /* Send Queue related data.*/ 623 struct mlx5_devx_sq sq_obj; 624 uint16_t sq_size; /* Number of WQEs in the queue. */ 625 uint16_t sq_ci; /* Next WQE to execute. */ 626 }; 627 628 /* Tx packet pacing internal timestamp. */ 629 struct mlx5_txpp_ts { 630 uint64_t ci_ts; 631 uint64_t ts; 632 }; 633 634 /* Tx packet pacing structure. */ 635 struct mlx5_dev_txpp { 636 pthread_mutex_t mutex; /* Pacing create/destroy mutex. */ 637 uint32_t refcnt; /* Pacing reference counter. */ 638 uint32_t freq; /* Timestamp frequency, Hz. */ 639 uint32_t tick; /* Completion tick duration in nanoseconds. */ 640 uint32_t test; /* Packet pacing test mode. */ 641 int32_t skew; /* Scheduling skew. */ 642 struct rte_intr_handle intr_handle; /* Periodic interrupt. */ 643 void *echan; /* Event Channel. */ 644 struct mlx5_txpp_wq clock_queue; /* Clock Queue. */ 645 struct mlx5_txpp_wq rearm_queue; /* Clock Queue. */ 646 void *pp; /* Packet pacing context. */ 647 uint16_t pp_id; /* Packet pacing context index. */ 648 uint16_t ts_n; /* Number of captured timestamps. */ 649 uint16_t ts_p; /* Pointer to statisticks timestamp. */ 650 struct mlx5_txpp_ts *tsa; /* Timestamps sliding window stats. */ 651 struct mlx5_txpp_ts ts; /* Cached completion id/timestamp. */ 652 uint32_t sync_lost:1; /* ci/timestamp synchronization lost. */ 653 /* Statistics counters. */ 654 uint64_t err_miss_int; /* Missed service interrupt. */ 655 uint64_t err_rearm_queue; /* Rearm Queue errors. */ 656 uint64_t err_clock_queue; /* Clock Queue errors. */ 657 uint64_t err_ts_past; /* Timestamp in the past. */ 658 uint64_t err_ts_future; /* Timestamp in the distant future. */ 659 }; 660 661 /* Supported flex parser profile ID. */ 662 enum mlx5_flex_parser_profile_id { 663 MLX5_FLEX_PARSER_ECPRI_0 = 0, 664 MLX5_FLEX_PARSER_MAX = 8, 665 }; 666 667 /* Sample ID information of flex parser structure. */ 668 struct mlx5_flex_parser_profiles { 669 uint32_t num; /* Actual number of samples. */ 670 uint32_t ids[8]; /* Sample IDs for this profile. */ 671 uint8_t offset[8]; /* Bytes offset of each parser. */ 672 void *obj; /* Flex parser node object. */ 673 }; 674 675 /* Max member ports per bonding device. */ 676 #define MLX5_BOND_MAX_PORTS 2 677 678 /* Bonding device information. */ 679 struct mlx5_bond_info { 680 int n_port; /* Number of bond member ports. */ 681 uint32_t ifindex; 682 char ifname[MLX5_NAMESIZE + 1]; 683 struct { 684 char ifname[MLX5_NAMESIZE + 1]; 685 uint32_t ifindex; 686 struct rte_pci_addr pci_addr; 687 } ports[MLX5_BOND_MAX_PORTS]; 688 }; 689 690 /* 691 * Shared Infiniband device context for Master/Representors 692 * which belong to same IB device with multiple IB ports. 693 **/ 694 struct mlx5_dev_ctx_shared { 695 LIST_ENTRY(mlx5_dev_ctx_shared) next; 696 uint32_t refcnt; 697 uint32_t devx:1; /* Opened with DV. */ 698 uint32_t flow_hit_aso_en:1; /* Flow Hit ASO is supported. */ 699 uint32_t rq_ts_format:2; /* RQ timestamp formats supported. */ 700 uint32_t sq_ts_format:2; /* SQ timestamp formats supported. */ 701 uint32_t qp_ts_format:2; /* QP timestamp formats supported. */ 702 uint32_t max_port; /* Maximal IB device port index. */ 703 struct mlx5_bond_info bond; /* Bonding information. */ 704 void *ctx; /* Verbs/DV/DevX context. */ 705 void *pd; /* Protection Domain. */ 706 uint32_t pdn; /* Protection Domain number. */ 707 uint32_t tdn; /* Transport Domain number. */ 708 char ibdev_name[MLX5_FS_NAME_MAX]; /* SYSFS dev name. */ 709 char ibdev_path[MLX5_FS_PATH_MAX]; /* SYSFS dev path for secondary */ 710 struct mlx5_dev_attr device_attr; /* Device properties. */ 711 int numa_node; /* Numa node of backing physical device. */ 712 LIST_ENTRY(mlx5_dev_ctx_shared) mem_event_cb; 713 /**< Called by memory event callback. */ 714 struct mlx5_mr_share_cache share_cache; 715 /* Packet pacing related structure. */ 716 struct mlx5_dev_txpp txpp; 717 /* Shared DV/DR flow data section. */ 718 uint32_t dv_meta_mask; /* flow META metadata supported mask. */ 719 uint32_t dv_mark_mask; /* flow MARK metadata supported mask. */ 720 uint32_t dv_regc0_mask; /* available bits of metatada reg_c[0]. */ 721 void *fdb_domain; /* FDB Direct Rules name space handle. */ 722 void *rx_domain; /* RX Direct Rules name space handle. */ 723 void *tx_domain; /* TX Direct Rules name space handle. */ 724 #ifndef RTE_ARCH_64 725 rte_spinlock_t uar_lock_cq; /* CQs share a common distinct UAR */ 726 rte_spinlock_t uar_lock[MLX5_UAR_PAGE_NUM_MAX]; 727 /* UAR same-page access control required in 32bit implementations. */ 728 #endif 729 struct mlx5_hlist *flow_tbls; 730 struct mlx5_flow_tunnel_hub *tunnel_hub; 731 /* Direct Rules tables for FDB, NIC TX+RX */ 732 void *esw_drop_action; /* Pointer to DR E-Switch drop action. */ 733 void *pop_vlan_action; /* Pointer to DR pop VLAN action. */ 734 struct mlx5_hlist *encaps_decaps; /* Encap/decap action hash list. */ 735 struct mlx5_hlist *modify_cmds; 736 struct mlx5_hlist *tag_table; 737 struct mlx5_cache_list port_id_action_list; /* Port ID action cache. */ 738 struct mlx5_cache_list push_vlan_action_list; /* Push VLAN actions. */ 739 struct mlx5_cache_list sample_action_list; /* List of sample actions. */ 740 struct mlx5_cache_list dest_array_list; 741 /* List of destination array actions. */ 742 struct mlx5_flow_counter_mng cmng; /* Counters management structure. */ 743 void *default_miss_action; /* Default miss action. */ 744 struct mlx5_indexed_pool *ipool[MLX5_IPOOL_MAX]; 745 /* Memory Pool for mlx5 flow resources. */ 746 struct mlx5_l3t_tbl *cnt_id_tbl; /* Shared counter lookup table. */ 747 /* Shared interrupt handler section. */ 748 struct rte_intr_handle intr_handle; /* Interrupt handler for device. */ 749 struct rte_intr_handle intr_handle_devx; /* DEVX interrupt handler. */ 750 void *devx_comp; /* DEVX async comp obj. */ 751 struct mlx5_devx_obj *tis; /* TIS object. */ 752 struct mlx5_devx_obj *td; /* Transport domain. */ 753 void *tx_uar; /* Tx/packet pacing shared UAR. */ 754 struct mlx5_flex_parser_profiles fp[MLX5_FLEX_PARSER_MAX]; 755 /* Flex parser profiles information. */ 756 void *devx_rx_uar; /* DevX UAR for Rx. */ 757 struct mlx5_aso_age_mng *aso_age_mng; 758 /* Management data for aging mechanism using ASO Flow Hit. */ 759 struct mlx5_geneve_tlv_option_resource *geneve_tlv_option_resource; 760 /* Management structure for geneve tlv option */ 761 rte_spinlock_t geneve_tlv_opt_sl; /* Lock for geneve tlv resource */ 762 struct mlx5_dev_shared_port port[]; /* per device port data array. */ 763 }; 764 765 /* 766 * Per-process private structure. 767 * Caution, secondary process may rebuild the struct during port start. 768 */ 769 struct mlx5_proc_priv { 770 size_t uar_table_sz; 771 /* Size of UAR register table. */ 772 void *uar_table[]; 773 /* Table of UAR registers for each process. */ 774 }; 775 776 /* MTR profile list. */ 777 TAILQ_HEAD(mlx5_mtr_profiles, mlx5_flow_meter_profile); 778 /* MTR list. */ 779 TAILQ_HEAD(mlx5_flow_meters, mlx5_flow_meter); 780 781 /* RSS description. */ 782 struct mlx5_flow_rss_desc { 783 uint32_t level; 784 uint32_t queue_num; /**< Number of entries in @p queue. */ 785 uint64_t types; /**< Specific RSS hash types (see ETH_RSS_*). */ 786 uint64_t hash_fields; /* Verbs Hash fields. */ 787 uint8_t key[MLX5_RSS_HASH_KEY_LEN]; /**< RSS hash key. */ 788 uint32_t key_len; /**< RSS hash key len. */ 789 uint32_t tunnel; /**< Queue in tunnel. */ 790 uint32_t shared_rss; /**< Shared RSS index. */ 791 struct mlx5_ind_table_obj *ind_tbl; 792 /**< Indirection table for shared RSS hash RX queues. */ 793 union { 794 uint16_t *queue; /**< Destination queues. */ 795 const uint16_t *const_q; /**< Const pointer convert. */ 796 }; 797 }; 798 799 #define MLX5_PROC_PRIV(port_id) \ 800 ((struct mlx5_proc_priv *)rte_eth_devices[port_id].process_private) 801 802 /* Verbs/DevX Rx queue elements. */ 803 struct mlx5_rxq_obj { 804 LIST_ENTRY(mlx5_rxq_obj) next; /* Pointer to the next element. */ 805 struct mlx5_rxq_ctrl *rxq_ctrl; /* Back pointer to parent. */ 806 int fd; /* File descriptor for event channel */ 807 RTE_STD_C11 808 union { 809 struct { 810 void *wq; /* Work Queue. */ 811 void *ibv_cq; /* Completion Queue. */ 812 void *ibv_channel; 813 }; 814 struct mlx5_devx_obj *rq; /* DevX RQ object for hairpin. */ 815 struct { 816 struct mlx5_devx_rq rq_obj; /* DevX RQ object. */ 817 struct mlx5_devx_cq cq_obj; /* DevX CQ object. */ 818 void *devx_channel; 819 }; 820 }; 821 }; 822 823 /* Indirection table. */ 824 struct mlx5_ind_table_obj { 825 LIST_ENTRY(mlx5_ind_table_obj) next; /* Pointer to the next element. */ 826 uint32_t refcnt; /* Reference counter. */ 827 RTE_STD_C11 828 union { 829 void *ind_table; /**< Indirection table. */ 830 struct mlx5_devx_obj *rqt; /* DevX RQT object. */ 831 }; 832 uint32_t queues_n; /**< Number of queues in the list. */ 833 uint16_t *queues; /**< Queue list. */ 834 }; 835 836 /* Hash Rx queue. */ 837 __extension__ 838 struct mlx5_hrxq { 839 struct mlx5_cache_entry entry; /* Cache entry. */ 840 uint32_t standalone:1; /* This object used in shared action. */ 841 struct mlx5_ind_table_obj *ind_table; /* Indirection table. */ 842 RTE_STD_C11 843 union { 844 void *qp; /* Verbs queue pair. */ 845 struct mlx5_devx_obj *tir; /* DevX TIR object. */ 846 }; 847 #if defined(HAVE_IBV_FLOW_DV_SUPPORT) || !defined(HAVE_INFINIBAND_VERBS_H) 848 void *action; /* DV QP action pointer. */ 849 #endif 850 uint64_t hash_fields; /* Verbs Hash fields. */ 851 uint32_t rss_key_len; /* Hash key length in bytes. */ 852 uint32_t idx; /* Hash Rx queue index. */ 853 uint8_t rss_key[]; /* Hash key. */ 854 }; 855 856 /* Verbs/DevX Tx queue elements. */ 857 struct mlx5_txq_obj { 858 LIST_ENTRY(mlx5_txq_obj) next; /* Pointer to the next element. */ 859 struct mlx5_txq_ctrl *txq_ctrl; /* Pointer to the control queue. */ 860 RTE_STD_C11 861 union { 862 struct { 863 void *cq; /* Completion Queue. */ 864 void *qp; /* Queue Pair. */ 865 }; 866 struct { 867 struct mlx5_devx_obj *sq; 868 /* DevX object for Sx queue. */ 869 struct mlx5_devx_obj *tis; /* The TIS object. */ 870 }; 871 struct { 872 struct rte_eth_dev *dev; 873 struct mlx5_devx_cq cq_obj; 874 /* DevX CQ object and its resources. */ 875 struct mlx5_devx_sq sq_obj; 876 /* DevX SQ object and its resources. */ 877 }; 878 }; 879 }; 880 881 enum mlx5_rxq_modify_type { 882 MLX5_RXQ_MOD_ERR2RST, /* modify state from error to reset. */ 883 MLX5_RXQ_MOD_RST2RDY, /* modify state from reset to ready. */ 884 MLX5_RXQ_MOD_RDY2ERR, /* modify state from ready to error. */ 885 MLX5_RXQ_MOD_RDY2RST, /* modify state from ready to reset. */ 886 }; 887 888 enum mlx5_txq_modify_type { 889 MLX5_TXQ_MOD_RST2RDY, /* modify state from reset to ready. */ 890 MLX5_TXQ_MOD_RDY2RST, /* modify state from ready to reset. */ 891 MLX5_TXQ_MOD_ERR2RDY, /* modify state from error to ready. */ 892 }; 893 894 /* HW objects operations structure. */ 895 struct mlx5_obj_ops { 896 int (*rxq_obj_modify_vlan_strip)(struct mlx5_rxq_obj *rxq_obj, int on); 897 int (*rxq_obj_new)(struct rte_eth_dev *dev, uint16_t idx); 898 int (*rxq_event_get)(struct mlx5_rxq_obj *rxq_obj); 899 int (*rxq_obj_modify)(struct mlx5_rxq_obj *rxq_obj, uint8_t type); 900 void (*rxq_obj_release)(struct mlx5_rxq_obj *rxq_obj); 901 int (*ind_table_new)(struct rte_eth_dev *dev, const unsigned int log_n, 902 struct mlx5_ind_table_obj *ind_tbl); 903 int (*ind_table_modify)(struct rte_eth_dev *dev, 904 const unsigned int log_n, 905 const uint16_t *queues, const uint32_t queues_n, 906 struct mlx5_ind_table_obj *ind_tbl); 907 void (*ind_table_destroy)(struct mlx5_ind_table_obj *ind_tbl); 908 int (*hrxq_new)(struct rte_eth_dev *dev, struct mlx5_hrxq *hrxq, 909 int tunnel __rte_unused); 910 int (*hrxq_modify)(struct rte_eth_dev *dev, struct mlx5_hrxq *hrxq, 911 const uint8_t *rss_key, 912 uint64_t hash_fields, 913 const struct mlx5_ind_table_obj *ind_tbl); 914 void (*hrxq_destroy)(struct mlx5_hrxq *hrxq); 915 int (*drop_action_create)(struct rte_eth_dev *dev); 916 void (*drop_action_destroy)(struct rte_eth_dev *dev); 917 int (*txq_obj_new)(struct rte_eth_dev *dev, uint16_t idx); 918 int (*txq_obj_modify)(struct mlx5_txq_obj *obj, 919 enum mlx5_txq_modify_type type, uint8_t dev_port); 920 void (*txq_obj_release)(struct mlx5_txq_obj *txq_obj); 921 }; 922 923 #define MLX5_RSS_HASH_FIELDS_LEN RTE_DIM(mlx5_rss_hash_fields) 924 925 /* MR operations structure. */ 926 struct mlx5_mr_ops { 927 mlx5_reg_mr_t reg_mr; 928 mlx5_dereg_mr_t dereg_mr; 929 }; 930 931 struct mlx5_priv { 932 struct rte_eth_dev_data *dev_data; /* Pointer to device data. */ 933 struct mlx5_dev_ctx_shared *sh; /* Shared device context. */ 934 uint32_t dev_port; /* Device port number. */ 935 struct rte_pci_device *pci_dev; /* Backend PCI device. */ 936 struct rte_ether_addr mac[MLX5_MAX_MAC_ADDRESSES]; /* MAC addresses. */ 937 BITFIELD_DECLARE(mac_own, uint64_t, MLX5_MAX_MAC_ADDRESSES); 938 /* Bit-field of MAC addresses owned by the PMD. */ 939 uint16_t vlan_filter[MLX5_MAX_VLAN_IDS]; /* VLAN filters table. */ 940 unsigned int vlan_filter_n; /* Number of configured VLAN filters. */ 941 /* Device properties. */ 942 uint16_t mtu; /* Configured MTU. */ 943 unsigned int isolated:1; /* Whether isolated mode is enabled. */ 944 unsigned int representor:1; /* Device is a port representor. */ 945 unsigned int master:1; /* Device is a E-Switch master. */ 946 unsigned int txpp_en:1; /* Tx packet pacing enabled. */ 947 unsigned int mtr_en:1; /* Whether support meter. */ 948 unsigned int mtr_reg_share:1; /* Whether support meter REG_C share. */ 949 unsigned int sampler_en:1; /* Whether support sampler. */ 950 uint16_t domain_id; /* Switch domain identifier. */ 951 uint16_t vport_id; /* Associated VF vport index (if any). */ 952 uint32_t vport_meta_tag; /* Used for vport index match ove VF LAG. */ 953 uint32_t vport_meta_mask; /* Used for vport index field match mask. */ 954 int32_t representor_id; /* -1 if not a representor. */ 955 int32_t pf_bond; /* >=0, representor owner PF index in bonding. */ 956 unsigned int if_index; /* Associated kernel network device index. */ 957 /* RX/TX queues. */ 958 unsigned int rxqs_n; /* RX queues array size. */ 959 unsigned int txqs_n; /* TX queues array size. */ 960 struct mlx5_rxq_data *(*rxqs)[]; /* RX queues. */ 961 struct mlx5_txq_data *(*txqs)[]; /* TX queues. */ 962 struct rte_mempool *mprq_mp; /* Mempool for Multi-Packet RQ. */ 963 struct rte_eth_rss_conf rss_conf; /* RSS configuration. */ 964 unsigned int (*reta_idx)[]; /* RETA index table. */ 965 unsigned int reta_idx_n; /* RETA index size. */ 966 struct mlx5_drop drop_queue; /* Flow drop queues. */ 967 uint32_t flows; /* RTE Flow rules. */ 968 uint32_t ctrl_flows; /* Control flow rules. */ 969 rte_spinlock_t flow_list_lock; 970 struct mlx5_obj_ops obj_ops; /* HW objects operations. */ 971 LIST_HEAD(rxq, mlx5_rxq_ctrl) rxqsctrl; /* DPDK Rx queues. */ 972 LIST_HEAD(rxqobj, mlx5_rxq_obj) rxqsobj; /* Verbs/DevX Rx queues. */ 973 struct mlx5_cache_list hrxqs; /* Hash Rx queues. */ 974 LIST_HEAD(txq, mlx5_txq_ctrl) txqsctrl; /* DPDK Tx queues. */ 975 LIST_HEAD(txqobj, mlx5_txq_obj) txqsobj; /* Verbs/DevX Tx queues. */ 976 /* Indirection tables. */ 977 LIST_HEAD(ind_tables, mlx5_ind_table_obj) ind_tbls; 978 /* Pointer to next element. */ 979 uint32_t refcnt; /**< Reference counter. */ 980 /**< Verbs modify header action object. */ 981 uint8_t ft_type; /**< Flow table type, Rx or Tx. */ 982 uint8_t max_lro_msg_size; 983 /* Tags resources cache. */ 984 uint32_t link_speed_capa; /* Link speed capabilities. */ 985 struct mlx5_xstats_ctrl xstats_ctrl; /* Extended stats control. */ 986 struct mlx5_stats_ctrl stats_ctrl; /* Stats control. */ 987 struct mlx5_dev_config config; /* Device configuration. */ 988 /* Context for Verbs allocator. */ 989 int nl_socket_rdma; /* Netlink socket (NETLINK_RDMA). */ 990 int nl_socket_route; /* Netlink socket (NETLINK_ROUTE). */ 991 struct mlx5_nl_vlan_vmwa_context *vmwa_context; /* VLAN WA context. */ 992 struct mlx5_hlist *mreg_cp_tbl; 993 /* Hash table of Rx metadata register copy table. */ 994 uint8_t mtr_sfx_reg; /* Meter prefix-suffix flow match REG_C. */ 995 uint8_t mtr_color_reg; /* Meter color match REG_C. */ 996 struct mlx5_mtr_profiles flow_meter_profiles; /* MTR profile list. */ 997 struct mlx5_flow_meters flow_meters; /* MTR list. */ 998 uint8_t skip_default_rss_reta; /* Skip configuration of default reta. */ 999 uint8_t fdb_def_rule; /* Whether fdb jump to table 1 is configured. */ 1000 struct mlx5_mp_id mp_id; /* ID of a multi-process process */ 1001 LIST_HEAD(fdir, mlx5_fdir_flow) fdir_flows; /* fdir flows. */ 1002 rte_spinlock_t shared_act_sl; /* Shared actions spinlock. */ 1003 uint32_t rss_shared_actions; /* RSS shared actions. */ 1004 struct mlx5_devx_obj *q_counters; /* DevX queue counter object. */ 1005 uint32_t counter_set_id; /* Queue counter ID to set in DevX objects. */ 1006 }; 1007 1008 #define PORT_ID(priv) ((priv)->dev_data->port_id) 1009 #define ETH_DEV(priv) (&rte_eth_devices[PORT_ID(priv)]) 1010 1011 struct rte_hairpin_peer_info { 1012 uint32_t qp_id; 1013 uint32_t vhca_id; 1014 uint16_t peer_q; 1015 uint16_t tx_explicit; 1016 uint16_t manual_bind; 1017 }; 1018 1019 /* mlx5.c */ 1020 1021 int mlx5_getenv_int(const char *); 1022 int mlx5_proc_priv_init(struct rte_eth_dev *dev); 1023 void mlx5_proc_priv_uninit(struct rte_eth_dev *dev); 1024 int mlx5_udp_tunnel_port_add(struct rte_eth_dev *dev, 1025 struct rte_eth_udp_tunnel *udp_tunnel); 1026 uint16_t mlx5_eth_find_next(uint16_t port_id, struct rte_pci_device *pci_dev); 1027 int mlx5_dev_close(struct rte_eth_dev *dev); 1028 bool mlx5_is_hpf(struct rte_eth_dev *dev); 1029 void mlx5_age_event_prepare(struct mlx5_dev_ctx_shared *sh); 1030 1031 /* Macro to iterate over all valid ports for mlx5 driver. */ 1032 #define MLX5_ETH_FOREACH_DEV(port_id, pci_dev) \ 1033 for (port_id = mlx5_eth_find_next(0, pci_dev); \ 1034 port_id < RTE_MAX_ETHPORTS; \ 1035 port_id = mlx5_eth_find_next(port_id + 1, pci_dev)) 1036 int mlx5_args(struct mlx5_dev_config *config, struct rte_devargs *devargs); 1037 struct mlx5_dev_ctx_shared * 1038 mlx5_alloc_shared_dev_ctx(const struct mlx5_dev_spawn_data *spawn, 1039 const struct mlx5_dev_config *config); 1040 void mlx5_free_shared_dev_ctx(struct mlx5_dev_ctx_shared *sh); 1041 void mlx5_free_table_hash_list(struct mlx5_priv *priv); 1042 int mlx5_alloc_table_hash_list(struct mlx5_priv *priv); 1043 void mlx5_set_min_inline(struct mlx5_dev_spawn_data *spawn, 1044 struct mlx5_dev_config *config); 1045 void mlx5_set_metadata_mask(struct rte_eth_dev *dev); 1046 int mlx5_dev_check_sibling_config(struct mlx5_priv *priv, 1047 struct mlx5_dev_config *config); 1048 int mlx5_dev_configure(struct rte_eth_dev *dev); 1049 int mlx5_dev_infos_get(struct rte_eth_dev *dev, struct rte_eth_dev_info *info); 1050 int mlx5_fw_version_get(struct rte_eth_dev *dev, char *fw_ver, size_t fw_size); 1051 int mlx5_dev_set_mtu(struct rte_eth_dev *dev, uint16_t mtu); 1052 int mlx5_hairpin_cap_get(struct rte_eth_dev *dev, 1053 struct rte_eth_hairpin_cap *cap); 1054 bool mlx5_flex_parser_ecpri_exist(struct rte_eth_dev *dev); 1055 int mlx5_flex_parser_ecpri_alloc(struct rte_eth_dev *dev); 1056 int mlx5_flow_aso_age_mng_init(struct mlx5_dev_ctx_shared *sh); 1057 1058 /* mlx5_ethdev.c */ 1059 1060 int mlx5_dev_configure(struct rte_eth_dev *dev); 1061 int mlx5_representor_info_get(struct rte_eth_dev *dev, 1062 struct rte_eth_representor_info *info); 1063 #define MLX5_REPRESENTOR_ID(pf, type, repr) \ 1064 (((pf) << 14) + ((type) << 12) + ((repr) & 0xfff)) 1065 #define MLX5_REPRESENTOR_REPR(repr_id) \ 1066 ((repr_id) & 0xfff) 1067 #define MLX5_REPRESENTOR_TYPE(repr_id) \ 1068 (((repr_id) >> 12) & 3) 1069 uint16_t mlx5_representor_id_encode(const struct mlx5_switch_info *info, 1070 enum rte_eth_representor_type hpf_type); 1071 int mlx5_fw_version_get(struct rte_eth_dev *dev, char *fw_ver, 1072 size_t fw_size); 1073 int mlx5_dev_infos_get(struct rte_eth_dev *dev, 1074 struct rte_eth_dev_info *info); 1075 const uint32_t *mlx5_dev_supported_ptypes_get(struct rte_eth_dev *dev); 1076 int mlx5_dev_set_mtu(struct rte_eth_dev *dev, uint16_t mtu); 1077 int mlx5_hairpin_cap_get(struct rte_eth_dev *dev, 1078 struct rte_eth_hairpin_cap *cap); 1079 eth_rx_burst_t mlx5_select_rx_function(struct rte_eth_dev *dev); 1080 struct mlx5_priv *mlx5_port_to_eswitch_info(uint16_t port, bool valid); 1081 struct mlx5_priv *mlx5_dev_to_eswitch_info(struct rte_eth_dev *dev); 1082 int mlx5_dev_configure_rss_reta(struct rte_eth_dev *dev); 1083 1084 /* mlx5_ethdev_os.c */ 1085 1086 int mlx5_get_ifname(const struct rte_eth_dev *dev, 1087 char (*ifname)[MLX5_NAMESIZE]); 1088 unsigned int mlx5_ifindex(const struct rte_eth_dev *dev); 1089 int mlx5_get_mac(struct rte_eth_dev *dev, uint8_t (*mac)[RTE_ETHER_ADDR_LEN]); 1090 int mlx5_get_mtu(struct rte_eth_dev *dev, uint16_t *mtu); 1091 int mlx5_set_mtu(struct rte_eth_dev *dev, uint16_t mtu); 1092 int mlx5_read_clock(struct rte_eth_dev *dev, uint64_t *clock); 1093 int mlx5_link_update(struct rte_eth_dev *dev, int wait_to_complete); 1094 int mlx5_dev_get_flow_ctrl(struct rte_eth_dev *dev, 1095 struct rte_eth_fc_conf *fc_conf); 1096 int mlx5_dev_set_flow_ctrl(struct rte_eth_dev *dev, 1097 struct rte_eth_fc_conf *fc_conf); 1098 void mlx5_dev_interrupt_handler(void *arg); 1099 void mlx5_dev_interrupt_handler_devx(void *arg); 1100 int mlx5_set_link_down(struct rte_eth_dev *dev); 1101 int mlx5_set_link_up(struct rte_eth_dev *dev); 1102 int mlx5_is_removed(struct rte_eth_dev *dev); 1103 int mlx5_sysfs_switch_info(unsigned int ifindex, 1104 struct mlx5_switch_info *info); 1105 void mlx5_translate_port_name(const char *port_name_in, 1106 struct mlx5_switch_info *port_info_out); 1107 void mlx5_intr_callback_unregister(const struct rte_intr_handle *handle, 1108 rte_intr_callback_fn cb_fn, void *cb_arg); 1109 int mlx5_sysfs_bond_info(unsigned int pf_ifindex, unsigned int *ifindex, 1110 char *ifname); 1111 int mlx5_get_module_info(struct rte_eth_dev *dev, 1112 struct rte_eth_dev_module_info *modinfo); 1113 int mlx5_get_module_eeprom(struct rte_eth_dev *dev, 1114 struct rte_dev_eeprom_info *info); 1115 int mlx5_os_read_dev_stat(struct mlx5_priv *priv, 1116 const char *ctr_name, uint64_t *stat); 1117 int mlx5_os_read_dev_counters(struct rte_eth_dev *dev, uint64_t *stats); 1118 int mlx5_os_get_stats_n(struct rte_eth_dev *dev); 1119 void mlx5_os_stats_init(struct rte_eth_dev *dev); 1120 1121 /* mlx5_mac.c */ 1122 1123 void mlx5_mac_addr_remove(struct rte_eth_dev *dev, uint32_t index); 1124 int mlx5_mac_addr_add(struct rte_eth_dev *dev, struct rte_ether_addr *mac, 1125 uint32_t index, uint32_t vmdq); 1126 int mlx5_mac_addr_set(struct rte_eth_dev *dev, struct rte_ether_addr *mac_addr); 1127 int mlx5_set_mc_addr_list(struct rte_eth_dev *dev, 1128 struct rte_ether_addr *mc_addr_set, 1129 uint32_t nb_mc_addr); 1130 1131 /* mlx5_rss.c */ 1132 1133 int mlx5_rss_hash_update(struct rte_eth_dev *dev, 1134 struct rte_eth_rss_conf *rss_conf); 1135 int mlx5_rss_hash_conf_get(struct rte_eth_dev *dev, 1136 struct rte_eth_rss_conf *rss_conf); 1137 int mlx5_rss_reta_index_resize(struct rte_eth_dev *dev, unsigned int reta_size); 1138 int mlx5_dev_rss_reta_query(struct rte_eth_dev *dev, 1139 struct rte_eth_rss_reta_entry64 *reta_conf, 1140 uint16_t reta_size); 1141 int mlx5_dev_rss_reta_update(struct rte_eth_dev *dev, 1142 struct rte_eth_rss_reta_entry64 *reta_conf, 1143 uint16_t reta_size); 1144 1145 /* mlx5_rxmode.c */ 1146 1147 int mlx5_promiscuous_enable(struct rte_eth_dev *dev); 1148 int mlx5_promiscuous_disable(struct rte_eth_dev *dev); 1149 int mlx5_allmulticast_enable(struct rte_eth_dev *dev); 1150 int mlx5_allmulticast_disable(struct rte_eth_dev *dev); 1151 1152 /* mlx5_stats.c */ 1153 1154 int mlx5_stats_get(struct rte_eth_dev *dev, struct rte_eth_stats *stats); 1155 int mlx5_stats_reset(struct rte_eth_dev *dev); 1156 int mlx5_xstats_get(struct rte_eth_dev *dev, struct rte_eth_xstat *stats, 1157 unsigned int n); 1158 int mlx5_xstats_reset(struct rte_eth_dev *dev); 1159 int mlx5_xstats_get_names(struct rte_eth_dev *dev __rte_unused, 1160 struct rte_eth_xstat_name *xstats_names, 1161 unsigned int n); 1162 1163 /* mlx5_vlan.c */ 1164 1165 int mlx5_vlan_filter_set(struct rte_eth_dev *dev, uint16_t vlan_id, int on); 1166 void mlx5_vlan_strip_queue_set(struct rte_eth_dev *dev, uint16_t queue, int on); 1167 int mlx5_vlan_offload_set(struct rte_eth_dev *dev, int mask); 1168 1169 /* mlx5_vlan_os.c */ 1170 1171 void mlx5_vlan_vmwa_exit(void *ctx); 1172 void mlx5_vlan_vmwa_release(struct rte_eth_dev *dev, 1173 struct mlx5_vf_vlan *vf_vlan); 1174 void mlx5_vlan_vmwa_acquire(struct rte_eth_dev *dev, 1175 struct mlx5_vf_vlan *vf_vlan); 1176 void *mlx5_vlan_vmwa_init(struct rte_eth_dev *dev, uint32_t ifindex); 1177 1178 /* mlx5_trigger.c */ 1179 1180 int mlx5_dev_start(struct rte_eth_dev *dev); 1181 int mlx5_dev_stop(struct rte_eth_dev *dev); 1182 int mlx5_traffic_enable(struct rte_eth_dev *dev); 1183 void mlx5_traffic_disable(struct rte_eth_dev *dev); 1184 int mlx5_traffic_restart(struct rte_eth_dev *dev); 1185 int mlx5_hairpin_queue_peer_update(struct rte_eth_dev *dev, uint16_t peer_queue, 1186 struct rte_hairpin_peer_info *current_info, 1187 struct rte_hairpin_peer_info *peer_info, 1188 uint32_t direction); 1189 int mlx5_hairpin_queue_peer_bind(struct rte_eth_dev *dev, uint16_t cur_queue, 1190 struct rte_hairpin_peer_info *peer_info, 1191 uint32_t direction); 1192 int mlx5_hairpin_queue_peer_unbind(struct rte_eth_dev *dev, uint16_t cur_queue, 1193 uint32_t direction); 1194 int mlx5_hairpin_bind(struct rte_eth_dev *dev, uint16_t rx_port); 1195 int mlx5_hairpin_unbind(struct rte_eth_dev *dev, uint16_t rx_port); 1196 int mlx5_hairpin_get_peer_ports(struct rte_eth_dev *dev, uint16_t *peer_ports, 1197 size_t len, uint32_t direction); 1198 1199 /* mlx5_flow.c */ 1200 1201 int mlx5_flow_discover_mreg_c(struct rte_eth_dev *eth_dev); 1202 bool mlx5_flow_ext_mreg_supported(struct rte_eth_dev *dev); 1203 void mlx5_flow_print(struct rte_flow *flow); 1204 int mlx5_flow_validate(struct rte_eth_dev *dev, 1205 const struct rte_flow_attr *attr, 1206 const struct rte_flow_item items[], 1207 const struct rte_flow_action actions[], 1208 struct rte_flow_error *error); 1209 struct rte_flow *mlx5_flow_create(struct rte_eth_dev *dev, 1210 const struct rte_flow_attr *attr, 1211 const struct rte_flow_item items[], 1212 const struct rte_flow_action actions[], 1213 struct rte_flow_error *error); 1214 int mlx5_flow_destroy(struct rte_eth_dev *dev, struct rte_flow *flow, 1215 struct rte_flow_error *error); 1216 void mlx5_flow_list_flush(struct rte_eth_dev *dev, uint32_t *list, bool active); 1217 int mlx5_flow_flush(struct rte_eth_dev *dev, struct rte_flow_error *error); 1218 int mlx5_flow_query(struct rte_eth_dev *dev, struct rte_flow *flow, 1219 const struct rte_flow_action *action, void *data, 1220 struct rte_flow_error *error); 1221 int mlx5_flow_isolate(struct rte_eth_dev *dev, int enable, 1222 struct rte_flow_error *error); 1223 int mlx5_flow_ops_get(struct rte_eth_dev *dev, const struct rte_flow_ops **ops); 1224 int mlx5_flow_start_default(struct rte_eth_dev *dev); 1225 void mlx5_flow_stop_default(struct rte_eth_dev *dev); 1226 int mlx5_flow_verify(struct rte_eth_dev *dev); 1227 int mlx5_ctrl_flow_source_queue(struct rte_eth_dev *dev, uint32_t queue); 1228 int mlx5_ctrl_flow_vlan(struct rte_eth_dev *dev, 1229 struct rte_flow_item_eth *eth_spec, 1230 struct rte_flow_item_eth *eth_mask, 1231 struct rte_flow_item_vlan *vlan_spec, 1232 struct rte_flow_item_vlan *vlan_mask); 1233 int mlx5_ctrl_flow(struct rte_eth_dev *dev, 1234 struct rte_flow_item_eth *eth_spec, 1235 struct rte_flow_item_eth *eth_mask); 1236 int mlx5_flow_lacp_miss(struct rte_eth_dev *dev); 1237 struct rte_flow *mlx5_flow_create_esw_table_zero_flow(struct rte_eth_dev *dev); 1238 int mlx5_flow_create_drop_queue(struct rte_eth_dev *dev); 1239 void mlx5_flow_delete_drop_queue(struct rte_eth_dev *dev); 1240 void mlx5_flow_async_pool_query_handle(struct mlx5_dev_ctx_shared *sh, 1241 uint64_t async_id, int status); 1242 void mlx5_set_query_alarm(struct mlx5_dev_ctx_shared *sh); 1243 void mlx5_flow_query_alarm(void *arg); 1244 uint32_t mlx5_counter_alloc(struct rte_eth_dev *dev); 1245 void mlx5_counter_free(struct rte_eth_dev *dev, uint32_t cnt); 1246 int mlx5_counter_query(struct rte_eth_dev *dev, uint32_t cnt, 1247 bool clear, uint64_t *pkts, uint64_t *bytes); 1248 int mlx5_flow_dev_dump(struct rte_eth_dev *dev, FILE *file, 1249 struct rte_flow_error *error); 1250 void mlx5_flow_rxq_dynf_metadata_set(struct rte_eth_dev *dev); 1251 int mlx5_flow_get_aged_flows(struct rte_eth_dev *dev, void **contexts, 1252 uint32_t nb_contexts, struct rte_flow_error *error); 1253 1254 /* mlx5_mp_os.c */ 1255 1256 int mlx5_mp_os_primary_handle(const struct rte_mp_msg *mp_msg, 1257 const void *peer); 1258 int mlx5_mp_os_secondary_handle(const struct rte_mp_msg *mp_msg, 1259 const void *peer); 1260 void mlx5_mp_os_req_start_rxtx(struct rte_eth_dev *dev); 1261 void mlx5_mp_os_req_stop_rxtx(struct rte_eth_dev *dev); 1262 int mlx5_mp_os_req_queue_control(struct rte_eth_dev *dev, uint16_t queue_id, 1263 enum mlx5_mp_req_type req_type); 1264 1265 /* mlx5_socket.c */ 1266 1267 int mlx5_pmd_socket_init(void); 1268 1269 /* mlx5_flow_meter.c */ 1270 1271 int mlx5_flow_meter_ops_get(struct rte_eth_dev *dev, void *arg); 1272 struct mlx5_flow_meter *mlx5_flow_meter_find(struct mlx5_priv *priv, 1273 uint32_t meter_id); 1274 struct mlx5_flow_meter *mlx5_flow_meter_attach 1275 (struct mlx5_priv *priv, 1276 uint32_t meter_id, 1277 const struct rte_flow_attr *attr, 1278 struct rte_flow_error *error); 1279 void mlx5_flow_meter_detach(struct mlx5_flow_meter *fm); 1280 1281 /* mlx5_os.c */ 1282 struct rte_pci_driver; 1283 int mlx5_os_get_dev_attr(void *ctx, struct mlx5_dev_attr *dev_attr); 1284 void mlx5_os_free_shared_dr(struct mlx5_priv *priv); 1285 int mlx5_os_open_device(const struct mlx5_dev_spawn_data *spawn, 1286 const struct mlx5_dev_config *config, 1287 struct mlx5_dev_ctx_shared *sh); 1288 int mlx5_os_get_pdn(void *pd, uint32_t *pdn); 1289 int mlx5_os_pci_probe(struct rte_pci_driver *pci_drv __rte_unused, 1290 struct rte_pci_device *pci_dev); 1291 void mlx5_os_dev_shared_handler_install(struct mlx5_dev_ctx_shared *sh); 1292 void mlx5_os_dev_shared_handler_uninstall(struct mlx5_dev_ctx_shared *sh); 1293 void mlx5_os_set_reg_mr_cb(mlx5_reg_mr_t *reg_mr_cb, 1294 mlx5_dereg_mr_t *dereg_mr_cb); 1295 void mlx5_os_mac_addr_remove(struct rte_eth_dev *dev, uint32_t index); 1296 int mlx5_os_mac_addr_add(struct rte_eth_dev *dev, struct rte_ether_addr *mac, 1297 uint32_t index); 1298 int mlx5_os_vf_mac_addr_modify(struct mlx5_priv *priv, unsigned int iface_idx, 1299 struct rte_ether_addr *mac_addr, 1300 int vf_index); 1301 int mlx5_os_set_promisc(struct rte_eth_dev *dev, int enable); 1302 int mlx5_os_set_allmulti(struct rte_eth_dev *dev, int enable); 1303 int mlx5_os_set_nonblock_channel_fd(int fd); 1304 void mlx5_os_mac_addr_flush(struct rte_eth_dev *dev); 1305 1306 /* mlx5_txpp.c */ 1307 1308 int mlx5_txpp_start(struct rte_eth_dev *dev); 1309 void mlx5_txpp_stop(struct rte_eth_dev *dev); 1310 int mlx5_txpp_read_clock(struct rte_eth_dev *dev, uint64_t *timestamp); 1311 int mlx5_txpp_xstats_get(struct rte_eth_dev *dev, 1312 struct rte_eth_xstat *stats, 1313 unsigned int n, unsigned int n_used); 1314 int mlx5_txpp_xstats_reset(struct rte_eth_dev *dev); 1315 int mlx5_txpp_xstats_get_names(struct rte_eth_dev *dev, 1316 struct rte_eth_xstat_name *xstats_names, 1317 unsigned int n, unsigned int n_used); 1318 void mlx5_txpp_interrupt_handler(void *cb_arg); 1319 1320 /* mlx5_rxtx.c */ 1321 1322 eth_tx_burst_t mlx5_select_tx_function(struct rte_eth_dev *dev); 1323 1324 /* mlx5_flow_age.c */ 1325 1326 int mlx5_aso_queue_init(struct mlx5_dev_ctx_shared *sh); 1327 int mlx5_aso_queue_start(struct mlx5_dev_ctx_shared *sh); 1328 int mlx5_aso_queue_stop(struct mlx5_dev_ctx_shared *sh); 1329 void mlx5_aso_queue_uninit(struct mlx5_dev_ctx_shared *sh); 1330 1331 #endif /* RTE_PMD_MLX5_H_ */ 1332