1 /* SPDX-License-Identifier: BSD-3-Clause 2 * Copyright 2015 6WIND S.A. 3 * Copyright 2015 Mellanox Technologies, Ltd 4 */ 5 6 #ifndef RTE_PMD_MLX5_H_ 7 #define RTE_PMD_MLX5_H_ 8 9 #include <stddef.h> 10 #include <stdint.h> 11 #include <limits.h> 12 #include <net/if.h> 13 #include <netinet/in.h> 14 #include <sys/queue.h> 15 16 /* Verbs header. */ 17 /* ISO C doesn't support unnamed structs/unions, disabling -pedantic. */ 18 #ifdef PEDANTIC 19 #pragma GCC diagnostic ignored "-Wpedantic" 20 #endif 21 #include <infiniband/verbs.h> 22 #ifdef PEDANTIC 23 #pragma GCC diagnostic error "-Wpedantic" 24 #endif 25 26 #include <rte_pci.h> 27 #include <rte_ether.h> 28 #include <rte_ethdev_driver.h> 29 #include <rte_rwlock.h> 30 #include <rte_interrupts.h> 31 #include <rte_errno.h> 32 #include <rte_flow.h> 33 34 #include "mlx5_utils.h" 35 #include "mlx5_mr.h" 36 #include "mlx5_autoconf.h" 37 #include "mlx5_defs.h" 38 39 enum { 40 PCI_VENDOR_ID_MELLANOX = 0x15b3, 41 }; 42 43 enum { 44 PCI_DEVICE_ID_MELLANOX_CONNECTX4 = 0x1013, 45 PCI_DEVICE_ID_MELLANOX_CONNECTX4VF = 0x1014, 46 PCI_DEVICE_ID_MELLANOX_CONNECTX4LX = 0x1015, 47 PCI_DEVICE_ID_MELLANOX_CONNECTX4LXVF = 0x1016, 48 PCI_DEVICE_ID_MELLANOX_CONNECTX5 = 0x1017, 49 PCI_DEVICE_ID_MELLANOX_CONNECTX5VF = 0x1018, 50 PCI_DEVICE_ID_MELLANOX_CONNECTX5EX = 0x1019, 51 PCI_DEVICE_ID_MELLANOX_CONNECTX5EXVF = 0x101a, 52 PCI_DEVICE_ID_MELLANOX_CONNECTX5BF = 0xa2d2, 53 PCI_DEVICE_ID_MELLANOX_CONNECTX5BFVF = 0xa2d3, 54 PCI_DEVICE_ID_MELLANOX_CONNECTX6 = 0x101b, 55 PCI_DEVICE_ID_MELLANOX_CONNECTX6VF = 0x101c, 56 }; 57 58 /* Request types for IPC. */ 59 enum mlx5_mp_req_type { 60 MLX5_MP_REQ_VERBS_CMD_FD = 1, 61 MLX5_MP_REQ_CREATE_MR, 62 MLX5_MP_REQ_START_RXTX, 63 MLX5_MP_REQ_STOP_RXTX, 64 }; 65 66 /* Pameters for IPC. */ 67 struct mlx5_mp_param { 68 enum mlx5_mp_req_type type; 69 int port_id; 70 int result; 71 RTE_STD_C11 72 union { 73 uintptr_t addr; /* MLX5_MP_REQ_CREATE_MR */ 74 } args; 75 }; 76 77 /** Request timeout for IPC. */ 78 #define MLX5_MP_REQ_TIMEOUT_SEC 5 79 80 /** Key string for IPC. */ 81 #define MLX5_MP_NAME "net_mlx5_mp" 82 83 /** Switch information returned by mlx5_nl_switch_info(). */ 84 struct mlx5_switch_info { 85 uint32_t master:1; /**< Master device. */ 86 uint32_t representor:1; /**< Representor device. */ 87 uint32_t port_name_new:1; /**< Rep. port name is in new format. */ 88 int32_t port_name; /**< Representor port name. */ 89 uint64_t switch_id; /**< Switch identifier. */ 90 }; 91 92 LIST_HEAD(mlx5_dev_list, mlx5_priv); 93 94 /* Shared data between primary and secondary processes. */ 95 struct mlx5_shared_data { 96 rte_spinlock_t lock; 97 /* Global spinlock for primary and secondary processes. */ 98 int init_done; /* Whether primary has done initialization. */ 99 unsigned int secondary_cnt; /* Number of secondary processes init'd. */ 100 struct mlx5_dev_list mem_event_cb_list; 101 rte_rwlock_t mem_event_rwlock; 102 }; 103 104 /* Per-process data structure, not visible to other processes. */ 105 struct mlx5_local_data { 106 int init_done; /* Whether a secondary has done initialization. */ 107 }; 108 109 extern struct mlx5_shared_data *mlx5_shared_data; 110 111 struct mlx5_counter_ctrl { 112 /* Name of the counter. */ 113 char dpdk_name[RTE_ETH_XSTATS_NAME_SIZE]; 114 /* Name of the counter on the device table. */ 115 char ctr_name[RTE_ETH_XSTATS_NAME_SIZE]; 116 uint32_t ib:1; /**< Nonzero for IB counters. */ 117 }; 118 119 struct mlx5_xstats_ctrl { 120 /* Number of device stats. */ 121 uint16_t stats_n; 122 /* Number of device stats identified by PMD. */ 123 uint16_t mlx5_stats_n; 124 /* Index in the device counters table. */ 125 uint16_t dev_table_idx[MLX5_MAX_XSTATS]; 126 uint64_t base[MLX5_MAX_XSTATS]; 127 struct mlx5_counter_ctrl info[MLX5_MAX_XSTATS]; 128 }; 129 130 struct mlx5_stats_ctrl { 131 /* Base for imissed counter. */ 132 uint64_t imissed_base; 133 }; 134 135 /* devx counter object */ 136 struct mlx5_devx_counter_set { 137 struct mlx5dv_devx_obj *obj; 138 int id; /* Flow counter ID */ 139 }; 140 141 /* Flow list . */ 142 TAILQ_HEAD(mlx5_flows, rte_flow); 143 144 /* Default PMD specific parameter value. */ 145 #define MLX5_ARG_UNSET (-1) 146 147 /* 148 * Device configuration structure. 149 * 150 * Merged configuration from: 151 * 152 * - Device capabilities, 153 * - User device parameters disabled features. 154 */ 155 struct mlx5_dev_config { 156 unsigned int hw_csum:1; /* Checksum offload is supported. */ 157 unsigned int hw_vlan_strip:1; /* VLAN stripping is supported. */ 158 unsigned int hw_fcs_strip:1; /* FCS stripping is supported. */ 159 unsigned int hw_padding:1; /* End alignment padding is supported. */ 160 unsigned int vf:1; /* This is a VF. */ 161 unsigned int tunnel_en:1; 162 /* Whether tunnel stateless offloads are supported. */ 163 unsigned int mpls_en:1; /* MPLS over GRE/UDP is enabled. */ 164 unsigned int cqe_comp:1; /* CQE compression is enabled. */ 165 unsigned int cqe_pad:1; /* CQE padding is enabled. */ 166 unsigned int tso:1; /* Whether TSO is supported. */ 167 unsigned int tx_vec_en:1; /* Tx vector is enabled. */ 168 unsigned int rx_vec_en:1; /* Rx vector is enabled. */ 169 unsigned int mpw_hdr_dseg:1; /* Enable DSEGs in the title WQEBB. */ 170 unsigned int mr_ext_memseg_en:1; 171 /* Whether memseg should be extended for MR creation. */ 172 unsigned int l3_vxlan_en:1; /* Enable L3 VXLAN flow creation. */ 173 unsigned int vf_nl_en:1; /* Enable Netlink requests in VF mode. */ 174 unsigned int dv_flow_en:1; /* Enable DV flow. */ 175 unsigned int swp:1; /* Tx generic tunnel checksum and TSO offload. */ 176 unsigned int devx:1; /* Whether devx interface is available or not. */ 177 struct { 178 unsigned int enabled:1; /* Whether MPRQ is enabled. */ 179 unsigned int stride_num_n; /* Number of strides. */ 180 unsigned int min_stride_size_n; /* Min size of a stride. */ 181 unsigned int max_stride_size_n; /* Max size of a stride. */ 182 unsigned int max_memcpy_len; 183 /* Maximum packet size to memcpy Rx packets. */ 184 unsigned int min_rxqs_num; 185 /* Rx queue count threshold to enable MPRQ. */ 186 } mprq; /* Configurations for Multi-Packet RQ. */ 187 int mps; /* Multi-packet send supported mode. */ 188 unsigned int flow_prio; /* Number of flow priorities. */ 189 unsigned int tso_max_payload_sz; /* Maximum TCP payload for TSO. */ 190 unsigned int ind_table_max_size; /* Maximum indirection table size. */ 191 int txq_inline; /* Maximum packet size for inlining. */ 192 int txqs_inline; /* Queue number threshold for inlining. */ 193 int txqs_vec; /* Queue number threshold for vectorized Tx. */ 194 int inline_max_packet_sz; /* Max packet size for inlining. */ 195 }; 196 197 /** 198 * Type of objet being allocated. 199 */ 200 enum mlx5_verbs_alloc_type { 201 MLX5_VERBS_ALLOC_TYPE_NONE, 202 MLX5_VERBS_ALLOC_TYPE_TX_QUEUE, 203 MLX5_VERBS_ALLOC_TYPE_RX_QUEUE, 204 }; 205 206 /** 207 * Verbs allocator needs a context to know in the callback which kind of 208 * resources it is allocating. 209 */ 210 struct mlx5_verbs_alloc_ctx { 211 enum mlx5_verbs_alloc_type type; /* Kind of object being allocated. */ 212 const void *obj; /* Pointer to the DPDK object. */ 213 }; 214 215 LIST_HEAD(mlx5_mr_list, mlx5_mr); 216 217 /* Flow drop context necessary due to Verbs API. */ 218 struct mlx5_drop { 219 struct mlx5_hrxq *hrxq; /* Hash Rx queue queue. */ 220 struct mlx5_rxq_ibv *rxq; /* Verbs Rx queue. */ 221 }; 222 223 struct mlx5_flow_tcf_context; 224 225 /* Per port data of shared IB device. */ 226 struct mlx5_ibv_shared_port { 227 uint32_t ih_port_id; 228 /* 229 * Interrupt handler port_id. Used by shared interrupt 230 * handler to find the corresponding rte_eth device 231 * by IB port index. If value is equal or greater 232 * RTE_MAX_ETHPORTS it means there is no subhandler 233 * installed for specified IB port index. 234 */ 235 }; 236 237 /* Table structure. */ 238 struct mlx5_flow_tbl_resource { 239 void *obj; /**< Pointer to DR table object. */ 240 rte_atomic32_t refcnt; /**< Reference counter. */ 241 }; 242 243 #define MLX5_MAX_TABLES 1024 244 #define MLX5_GROUP_FACTOR 1 245 246 /* 247 * Shared Infiniband device context for Master/Representors 248 * which belong to same IB device with multiple IB ports. 249 **/ 250 struct mlx5_ibv_shared { 251 LIST_ENTRY(mlx5_ibv_shared) next; 252 uint32_t refcnt; 253 uint32_t devx:1; /* Opened with DV. */ 254 uint32_t max_port; /* Maximal IB device port index. */ 255 struct ibv_context *ctx; /* Verbs/DV context. */ 256 struct ibv_pd *pd; /* Protection Domain. */ 257 char ibdev_name[IBV_SYSFS_NAME_MAX]; /* IB device name. */ 258 char ibdev_path[IBV_SYSFS_PATH_MAX]; /* IB device path for secondary */ 259 struct ibv_device_attr_ex device_attr; /* Device properties. */ 260 /* Shared DV/DR flow data section. */ 261 pthread_mutex_t dv_mutex; /* DV context mutex. */ 262 uint32_t dv_refcnt; /* DV/DR data reference counter. */ 263 void *rx_ns; /* RX Direct Rules name space handle. */ 264 struct mlx5_flow_tbl_resource rx_tbl[MLX5_MAX_TABLES]; 265 /* RX Direct Rules tables. */ 266 void *tx_ns; /* TX Direct Rules name space handle. */ 267 struct mlx5_flow_tbl_resource tx_tbl[MLX5_MAX_TABLES]; 268 /* TX Direct Rules tables/ */ 269 LIST_HEAD(matchers, mlx5_flow_dv_matcher) matchers; 270 LIST_HEAD(encap_decap, mlx5_flow_dv_encap_decap_resource) encaps_decaps; 271 LIST_HEAD(modify_cmd, mlx5_flow_dv_modify_hdr_resource) modify_cmds; 272 LIST_HEAD(tag, mlx5_flow_dv_tag_resource) tags; 273 LIST_HEAD(jump, mlx5_flow_dv_jump_tbl_resource) jump_tbl; 274 /* Shared interrupt handler section. */ 275 pthread_mutex_t intr_mutex; /* Interrupt config mutex. */ 276 uint32_t intr_cnt; /* Interrupt handler reference counter. */ 277 struct rte_intr_handle intr_handle; /* Interrupt handler for device. */ 278 struct mlx5_ibv_shared_port port[]; /* per device port data array. */ 279 }; 280 281 /* Per-process private structure. */ 282 struct mlx5_proc_priv { 283 size_t uar_table_sz; 284 /* Size of UAR register table. */ 285 void *uar_table[]; 286 /* Table of UAR registers for each process. */ 287 }; 288 289 #define MLX5_PROC_PRIV(port_id) \ 290 ((struct mlx5_proc_priv *)rte_eth_devices[port_id].process_private) 291 292 struct mlx5_priv { 293 LIST_ENTRY(mlx5_priv) mem_event_cb; 294 /**< Called by memory event callback. */ 295 struct rte_eth_dev_data *dev_data; /* Pointer to device data. */ 296 struct mlx5_ibv_shared *sh; /* Shared IB device context. */ 297 uint32_t ibv_port; /* IB device port number. */ 298 struct ether_addr mac[MLX5_MAX_MAC_ADDRESSES]; /* MAC addresses. */ 299 BITFIELD_DECLARE(mac_own, uint64_t, MLX5_MAX_MAC_ADDRESSES); 300 /* Bit-field of MAC addresses owned by the PMD. */ 301 uint16_t vlan_filter[MLX5_MAX_VLAN_IDS]; /* VLAN filters table. */ 302 unsigned int vlan_filter_n; /* Number of configured VLAN filters. */ 303 /* Device properties. */ 304 uint16_t mtu; /* Configured MTU. */ 305 unsigned int isolated:1; /* Whether isolated mode is enabled. */ 306 unsigned int representor:1; /* Device is a port representor. */ 307 unsigned int master:1; /* Device is a E-Switch master. */ 308 unsigned int dr_shared:1; /* DV/DR data is shared. */ 309 uint16_t domain_id; /* Switch domain identifier. */ 310 uint16_t vport_id; /* Associated VF vport index (if any). */ 311 int32_t representor_id; /* Port representor identifier. */ 312 /* RX/TX queues. */ 313 unsigned int rxqs_n; /* RX queues array size. */ 314 unsigned int txqs_n; /* TX queues array size. */ 315 struct mlx5_rxq_data *(*rxqs)[]; /* RX queues. */ 316 struct mlx5_txq_data *(*txqs)[]; /* TX queues. */ 317 struct rte_mempool *mprq_mp; /* Mempool for Multi-Packet RQ. */ 318 struct rte_eth_rss_conf rss_conf; /* RSS configuration. */ 319 unsigned int (*reta_idx)[]; /* RETA index table. */ 320 unsigned int reta_idx_n; /* RETA index size. */ 321 struct mlx5_drop drop_queue; /* Flow drop queues. */ 322 struct mlx5_flows flows; /* RTE Flow rules. */ 323 struct mlx5_flows ctrl_flows; /* Control flow rules. */ 324 LIST_HEAD(counters, mlx5_flow_counter) flow_counters; 325 /* Flow counters. */ 326 struct { 327 uint32_t dev_gen; /* Generation number to flush local caches. */ 328 rte_rwlock_t rwlock; /* MR Lock. */ 329 struct mlx5_mr_btree cache; /* Global MR cache table. */ 330 struct mlx5_mr_list mr_list; /* Registered MR list. */ 331 struct mlx5_mr_list mr_free_list; /* Freed MR list. */ 332 } mr; 333 LIST_HEAD(rxq, mlx5_rxq_ctrl) rxqsctrl; /* DPDK Rx queues. */ 334 LIST_HEAD(rxqibv, mlx5_rxq_ibv) rxqsibv; /* Verbs Rx queues. */ 335 LIST_HEAD(hrxq, mlx5_hrxq) hrxqs; /* Verbs Hash Rx queues. */ 336 LIST_HEAD(txq, mlx5_txq_ctrl) txqsctrl; /* DPDK Tx queues. */ 337 LIST_HEAD(txqibv, mlx5_txq_ibv) txqsibv; /* Verbs Tx queues. */ 338 /* Verbs Indirection tables. */ 339 LIST_HEAD(ind_tables, mlx5_ind_table_ibv) ind_tbls; 340 /* Pointer to next element. */ 341 rte_atomic32_t refcnt; /**< Reference counter. */ 342 struct ibv_flow_action *verbs_action; 343 /**< Verbs modify header action object. */ 344 uint8_t ft_type; /**< Flow table type, Rx or Tx. */ 345 /* Tags resources cache. */ 346 uint32_t link_speed_capa; /* Link speed capabilities. */ 347 struct mlx5_xstats_ctrl xstats_ctrl; /* Extended stats control. */ 348 struct mlx5_stats_ctrl stats_ctrl; /* Stats control. */ 349 struct mlx5_dev_config config; /* Device configuration. */ 350 struct mlx5_verbs_alloc_ctx verbs_alloc_ctx; 351 /* Context for Verbs allocator. */ 352 int nl_socket_rdma; /* Netlink socket (NETLINK_RDMA). */ 353 int nl_socket_route; /* Netlink socket (NETLINK_ROUTE). */ 354 uint32_t nl_sn; /* Netlink message sequence number. */ 355 #ifndef RTE_ARCH_64 356 rte_spinlock_t uar_lock_cq; /* CQs share a common distinct UAR */ 357 rte_spinlock_t uar_lock[MLX5_UAR_PAGE_NUM_MAX]; 358 /* UAR same-page access control required in 32bit implementations. */ 359 #endif 360 struct mlx5_flow_tcf_context *tcf_context; /* TC flower context. */ 361 }; 362 363 #define PORT_ID(priv) ((priv)->dev_data->port_id) 364 #define ETH_DEV(priv) (&rte_eth_devices[PORT_ID(priv)]) 365 366 /* mlx5.c */ 367 368 int mlx5_getenv_int(const char *); 369 int mlx5_proc_priv_init(struct rte_eth_dev *dev); 370 371 /* mlx5_ethdev.c */ 372 373 int mlx5_get_ifname(const struct rte_eth_dev *dev, char (*ifname)[IF_NAMESIZE]); 374 int mlx5_get_master_ifname(const char *ibdev_path, char (*ifname)[IF_NAMESIZE]); 375 unsigned int mlx5_ifindex(const struct rte_eth_dev *dev); 376 int mlx5_ifreq(const struct rte_eth_dev *dev, int req, struct ifreq *ifr); 377 int mlx5_get_mtu(struct rte_eth_dev *dev, uint16_t *mtu); 378 int mlx5_set_flags(struct rte_eth_dev *dev, unsigned int keep, 379 unsigned int flags); 380 int mlx5_dev_configure(struct rte_eth_dev *dev); 381 void mlx5_dev_infos_get(struct rte_eth_dev *dev, struct rte_eth_dev_info *info); 382 int mlx5_fw_version_get(struct rte_eth_dev *dev, char *fw_ver, size_t fw_size); 383 const uint32_t *mlx5_dev_supported_ptypes_get(struct rte_eth_dev *dev); 384 int mlx5_link_update(struct rte_eth_dev *dev, int wait_to_complete); 385 int mlx5_force_link_status_change(struct rte_eth_dev *dev, int status); 386 int mlx5_dev_set_mtu(struct rte_eth_dev *dev, uint16_t mtu); 387 int mlx5_dev_get_flow_ctrl(struct rte_eth_dev *dev, 388 struct rte_eth_fc_conf *fc_conf); 389 int mlx5_dev_set_flow_ctrl(struct rte_eth_dev *dev, 390 struct rte_eth_fc_conf *fc_conf); 391 int mlx5_ibv_device_to_pci_addr(const struct ibv_device *device, 392 struct rte_pci_addr *pci_addr); 393 void mlx5_dev_link_status_handler(void *arg); 394 void mlx5_dev_interrupt_handler(void *arg); 395 void mlx5_dev_interrupt_handler_uninstall(struct rte_eth_dev *dev); 396 void mlx5_dev_interrupt_handler_install(struct rte_eth_dev *dev); 397 int mlx5_set_link_down(struct rte_eth_dev *dev); 398 int mlx5_set_link_up(struct rte_eth_dev *dev); 399 int mlx5_is_removed(struct rte_eth_dev *dev); 400 eth_tx_burst_t mlx5_select_tx_function(struct rte_eth_dev *dev); 401 eth_rx_burst_t mlx5_select_rx_function(struct rte_eth_dev *dev); 402 unsigned int mlx5_dev_to_port_id(const struct rte_device *dev, 403 uint16_t *port_list, 404 unsigned int port_list_n); 405 int mlx5_sysfs_switch_info(unsigned int ifindex, 406 struct mlx5_switch_info *info); 407 bool mlx5_translate_port_name(const char *port_name_in, 408 struct mlx5_switch_info *port_info_out); 409 410 /* mlx5_mac.c */ 411 412 int mlx5_get_mac(struct rte_eth_dev *dev, uint8_t (*mac)[ETHER_ADDR_LEN]); 413 void mlx5_mac_addr_remove(struct rte_eth_dev *dev, uint32_t index); 414 int mlx5_mac_addr_add(struct rte_eth_dev *dev, struct ether_addr *mac, 415 uint32_t index, uint32_t vmdq); 416 int mlx5_mac_addr_set(struct rte_eth_dev *dev, struct ether_addr *mac_addr); 417 int mlx5_set_mc_addr_list(struct rte_eth_dev *dev, 418 struct ether_addr *mc_addr_set, uint32_t nb_mc_addr); 419 420 /* mlx5_rss.c */ 421 422 int mlx5_rss_hash_update(struct rte_eth_dev *dev, 423 struct rte_eth_rss_conf *rss_conf); 424 int mlx5_rss_hash_conf_get(struct rte_eth_dev *dev, 425 struct rte_eth_rss_conf *rss_conf); 426 int mlx5_rss_reta_index_resize(struct rte_eth_dev *dev, unsigned int reta_size); 427 int mlx5_dev_rss_reta_query(struct rte_eth_dev *dev, 428 struct rte_eth_rss_reta_entry64 *reta_conf, 429 uint16_t reta_size); 430 int mlx5_dev_rss_reta_update(struct rte_eth_dev *dev, 431 struct rte_eth_rss_reta_entry64 *reta_conf, 432 uint16_t reta_size); 433 434 /* mlx5_rxmode.c */ 435 436 void mlx5_promiscuous_enable(struct rte_eth_dev *dev); 437 void mlx5_promiscuous_disable(struct rte_eth_dev *dev); 438 void mlx5_allmulticast_enable(struct rte_eth_dev *dev); 439 void mlx5_allmulticast_disable(struct rte_eth_dev *dev); 440 441 /* mlx5_stats.c */ 442 443 void mlx5_stats_init(struct rte_eth_dev *dev); 444 int mlx5_stats_get(struct rte_eth_dev *dev, struct rte_eth_stats *stats); 445 void mlx5_stats_reset(struct rte_eth_dev *dev); 446 int mlx5_xstats_get(struct rte_eth_dev *dev, struct rte_eth_xstat *stats, 447 unsigned int n); 448 void mlx5_xstats_reset(struct rte_eth_dev *dev); 449 int mlx5_xstats_get_names(struct rte_eth_dev *dev __rte_unused, 450 struct rte_eth_xstat_name *xstats_names, 451 unsigned int n); 452 453 /* mlx5_vlan.c */ 454 455 int mlx5_vlan_filter_set(struct rte_eth_dev *dev, uint16_t vlan_id, int on); 456 void mlx5_vlan_strip_queue_set(struct rte_eth_dev *dev, uint16_t queue, int on); 457 int mlx5_vlan_offload_set(struct rte_eth_dev *dev, int mask); 458 459 /* mlx5_trigger.c */ 460 461 int mlx5_dev_start(struct rte_eth_dev *dev); 462 void mlx5_dev_stop(struct rte_eth_dev *dev); 463 int mlx5_traffic_enable(struct rte_eth_dev *dev); 464 void mlx5_traffic_disable(struct rte_eth_dev *dev); 465 int mlx5_traffic_restart(struct rte_eth_dev *dev); 466 467 /* mlx5_flow.c */ 468 469 int mlx5_flow_discover_priorities(struct rte_eth_dev *dev); 470 void mlx5_flow_print(struct rte_flow *flow); 471 int mlx5_flow_validate(struct rte_eth_dev *dev, 472 const struct rte_flow_attr *attr, 473 const struct rte_flow_item items[], 474 const struct rte_flow_action actions[], 475 struct rte_flow_error *error); 476 struct rte_flow *mlx5_flow_create(struct rte_eth_dev *dev, 477 const struct rte_flow_attr *attr, 478 const struct rte_flow_item items[], 479 const struct rte_flow_action actions[], 480 struct rte_flow_error *error); 481 int mlx5_flow_destroy(struct rte_eth_dev *dev, struct rte_flow *flow, 482 struct rte_flow_error *error); 483 void mlx5_flow_list_flush(struct rte_eth_dev *dev, struct mlx5_flows *list); 484 int mlx5_flow_flush(struct rte_eth_dev *dev, struct rte_flow_error *error); 485 int mlx5_flow_query(struct rte_eth_dev *dev, struct rte_flow *flow, 486 const struct rte_flow_action *action, void *data, 487 struct rte_flow_error *error); 488 int mlx5_flow_isolate(struct rte_eth_dev *dev, int enable, 489 struct rte_flow_error *error); 490 int mlx5_dev_filter_ctrl(struct rte_eth_dev *dev, 491 enum rte_filter_type filter_type, 492 enum rte_filter_op filter_op, 493 void *arg); 494 int mlx5_flow_start(struct rte_eth_dev *dev, struct mlx5_flows *list); 495 void mlx5_flow_stop(struct rte_eth_dev *dev, struct mlx5_flows *list); 496 int mlx5_flow_verify(struct rte_eth_dev *dev); 497 int mlx5_ctrl_flow_vlan(struct rte_eth_dev *dev, 498 struct rte_flow_item_eth *eth_spec, 499 struct rte_flow_item_eth *eth_mask, 500 struct rte_flow_item_vlan *vlan_spec, 501 struct rte_flow_item_vlan *vlan_mask); 502 int mlx5_ctrl_flow(struct rte_eth_dev *dev, 503 struct rte_flow_item_eth *eth_spec, 504 struct rte_flow_item_eth *eth_mask); 505 int mlx5_flow_create_drop_queue(struct rte_eth_dev *dev); 506 void mlx5_flow_delete_drop_queue(struct rte_eth_dev *dev); 507 508 /* mlx5_mp.c */ 509 void mlx5_mp_req_start_rxtx(struct rte_eth_dev *dev); 510 void mlx5_mp_req_stop_rxtx(struct rte_eth_dev *dev); 511 int mlx5_mp_req_mr_create(struct rte_eth_dev *dev, uintptr_t addr); 512 int mlx5_mp_req_verbs_cmd_fd(struct rte_eth_dev *dev); 513 void mlx5_mp_init_primary(void); 514 void mlx5_mp_uninit_primary(void); 515 void mlx5_mp_init_secondary(void); 516 void mlx5_mp_uninit_secondary(void); 517 518 /* mlx5_nl.c */ 519 520 int mlx5_nl_init(int protocol); 521 int mlx5_nl_mac_addr_add(struct rte_eth_dev *dev, struct ether_addr *mac, 522 uint32_t index); 523 int mlx5_nl_mac_addr_remove(struct rte_eth_dev *dev, struct ether_addr *mac, 524 uint32_t index); 525 void mlx5_nl_mac_addr_sync(struct rte_eth_dev *dev); 526 void mlx5_nl_mac_addr_flush(struct rte_eth_dev *dev); 527 int mlx5_nl_promisc(struct rte_eth_dev *dev, int enable); 528 int mlx5_nl_allmulti(struct rte_eth_dev *dev, int enable); 529 unsigned int mlx5_nl_portnum(int nl, const char *name); 530 unsigned int mlx5_nl_ifindex(int nl, const char *name, uint32_t pindex); 531 int mlx5_nl_switch_info(int nl, unsigned int ifindex, 532 struct mlx5_switch_info *info); 533 534 /* mlx5_devx_cmds.c */ 535 536 int mlx5_devx_cmd_flow_counter_alloc(struct ibv_context *ctx, 537 struct mlx5_devx_counter_set *dcx); 538 int mlx5_devx_cmd_flow_counter_free(struct mlx5dv_devx_obj *obj); 539 int mlx5_devx_cmd_flow_counter_query(struct mlx5_devx_counter_set *dcx, 540 int clear, 541 uint64_t *pkts, uint64_t *bytes); 542 #endif /* RTE_PMD_MLX5_H_ */ 543