1 /* SPDX-License-Identifier: BSD-3-Clause 2 * Copyright 2015 6WIND S.A. 3 * Copyright 2015 Mellanox Technologies, Ltd 4 */ 5 6 #ifndef RTE_PMD_MLX5_H_ 7 #define RTE_PMD_MLX5_H_ 8 9 #include <stddef.h> 10 #include <stdbool.h> 11 #include <stdint.h> 12 #include <limits.h> 13 #include <sys/queue.h> 14 15 #include <rte_pci.h> 16 #include <rte_ether.h> 17 #include <ethdev_driver.h> 18 #include <rte_rwlock.h> 19 #include <rte_interrupts.h> 20 #include <rte_errno.h> 21 #include <rte_flow.h> 22 #include <rte_mtr.h> 23 24 #include <mlx5_glue.h> 25 #include <mlx5_devx_cmds.h> 26 #include <mlx5_prm.h> 27 #include <mlx5_common_mp.h> 28 #include <mlx5_common_mr.h> 29 #include <mlx5_common_devx.h> 30 #include <mlx5_common_defs.h> 31 32 #include "mlx5_defs.h" 33 #include "mlx5_utils.h" 34 #include "mlx5_os.h" 35 #include "mlx5_autoconf.h" 36 #if defined(HAVE_IBV_FLOW_DV_SUPPORT) || !defined(HAVE_INFINIBAND_VERBS_H) 37 #include "mlx5_dr.h" 38 #endif 39 40 #define MLX5_SH(dev) (((struct mlx5_priv *)(dev)->data->dev_private)->sh) 41 42 /* 43 * Number of modification commands. 44 * The maximal actions amount in FW is some constant, and it is 16 in the 45 * latest releases. In some old releases, it will be limited to 8. 46 * Since there is no interface to query the capacity, the maximal value should 47 * be used to allow PMD to create the flow. The validation will be done in the 48 * lower driver layer or FW. A failure will be returned if exceeds the maximal 49 * supported actions number on the root table. 50 * On non-root tables, there is no limitation, but 32 is enough right now. 51 */ 52 #define MLX5_MAX_MODIFY_NUM 32 53 #define MLX5_ROOT_TBL_MODIFY_NUM 16 54 55 /* Maximal number of flex items created on the port.*/ 56 #define MLX5_PORT_FLEX_ITEM_NUM 4 57 58 /* Maximal number of field/field parts to map into sample registers .*/ 59 #define MLX5_FLEX_ITEM_MAPPING_NUM 32 60 61 enum mlx5_ipool_index { 62 #if defined(HAVE_IBV_FLOW_DV_SUPPORT) || !defined(HAVE_INFINIBAND_VERBS_H) 63 MLX5_IPOOL_DECAP_ENCAP = 0, /* Pool for encap/decap resource. */ 64 MLX5_IPOOL_PUSH_VLAN, /* Pool for push vlan resource. */ 65 MLX5_IPOOL_TAG, /* Pool for tag resource. */ 66 MLX5_IPOOL_PORT_ID, /* Pool for port id resource. */ 67 MLX5_IPOOL_JUMP, /* Pool for SWS jump resource. */ 68 /* Pool for HWS group. Jump action will be created internally. */ 69 MLX5_IPOOL_HW_GRP = MLX5_IPOOL_JUMP, 70 MLX5_IPOOL_SAMPLE, /* Pool for sample resource. */ 71 MLX5_IPOOL_DEST_ARRAY, /* Pool for destination array resource. */ 72 MLX5_IPOOL_TUNNEL_ID, /* Pool for tunnel offload context */ 73 MLX5_IPOOL_TNL_TBL_ID, /* Pool for tunnel table ID. */ 74 #endif 75 MLX5_IPOOL_MTR, /* Pool for meter resource. */ 76 MLX5_IPOOL_MCP, /* Pool for metadata resource. */ 77 MLX5_IPOOL_HRXQ, /* Pool for hrxq resource. */ 78 MLX5_IPOOL_MLX5_FLOW, /* Pool for mlx5 flow handle. */ 79 MLX5_IPOOL_RTE_FLOW, /* Pool for rte_flow. */ 80 MLX5_IPOOL_RSS_EXPANTION_FLOW_ID, /* Pool for Queue/RSS flow ID. */ 81 MLX5_IPOOL_RSS_SHARED_ACTIONS, /* Pool for RSS shared actions. */ 82 MLX5_IPOOL_MTR_POLICY, /* Pool for meter policy resource. */ 83 MLX5_IPOOL_MAX, 84 }; 85 86 /* 87 * There are three reclaim memory mode supported. 88 * 0(none) means no memory reclaim. 89 * 1(light) means only PMD level reclaim. 90 * 2(aggressive) means both PMD and rdma-core level reclaim. 91 */ 92 enum mlx5_reclaim_mem_mode { 93 MLX5_RCM_NONE, /* Don't reclaim memory. */ 94 MLX5_RCM_LIGHT, /* Reclaim PMD level. */ 95 MLX5_RCM_AGGR, /* Reclaim PMD and rdma-core level. */ 96 }; 97 98 /* The type of flow. */ 99 enum mlx5_flow_type { 100 MLX5_FLOW_TYPE_CTL, /* Control flow. */ 101 MLX5_FLOW_TYPE_GEN, /* General flow. */ 102 MLX5_FLOW_TYPE_MCP, /* MCP flow. */ 103 MLX5_FLOW_TYPE_MAXI, 104 }; 105 106 /* The mode of delay drop for Rx queues. */ 107 enum mlx5_delay_drop_mode { 108 MLX5_DELAY_DROP_NONE = 0, /* All disabled. */ 109 MLX5_DELAY_DROP_STANDARD = RTE_BIT32(0), /* Standard queues enable. */ 110 MLX5_DELAY_DROP_HAIRPIN = RTE_BIT32(1), /* Hairpin queues enable. */ 111 }; 112 113 /* The HWS action type root/non-root. */ 114 enum mlx5_hw_action_flag_type { 115 MLX5_HW_ACTION_FLAG_ROOT, /* Root action. */ 116 MLX5_HW_ACTION_FLAG_NONE_ROOT, /* Non-root ation. */ 117 MLX5_HW_ACTION_FLAG_MAX, /* Maximum action flag. */ 118 }; 119 120 /* Hlist and list callback context. */ 121 struct mlx5_flow_cb_ctx { 122 struct rte_eth_dev *dev; 123 struct rte_flow_error *error; 124 void *data; 125 void *data2; 126 }; 127 128 /* Device capabilities structure which isn't changed in any stage. */ 129 struct mlx5_dev_cap { 130 int max_cq; /* Maximum number of supported CQs */ 131 int max_qp; /* Maximum number of supported QPs. */ 132 int max_qp_wr; /* Maximum number of outstanding WR on any WQ. */ 133 int max_sge; 134 /* Maximum number of s/g per WR for SQ & RQ of QP for non RDMA Read 135 * operations. 136 */ 137 int mps; /* Multi-packet send supported mode. */ 138 uint32_t vf:1; /* This is a VF. */ 139 uint32_t sf:1; /* This is a SF. */ 140 uint32_t txpp_en:1; /* Tx packet pacing is supported. */ 141 uint32_t mpls_en:1; /* MPLS over GRE/UDP is supported. */ 142 uint32_t cqe_comp:1; /* CQE compression is supported. */ 143 uint32_t hw_csum:1; /* Checksum offload is supported. */ 144 uint32_t hw_padding:1; /* End alignment padding is supported. */ 145 uint32_t dest_tir:1; /* Whether advanced DR API is available. */ 146 uint32_t dv_esw_en:1; /* E-Switch DV flow is supported. */ 147 uint32_t dv_flow_en:1; /* DV flow is supported. */ 148 uint32_t swp:3; /* Tx generic tunnel checksum and TSO offload. */ 149 uint32_t hw_vlan_strip:1; /* VLAN stripping is supported. */ 150 uint32_t scatter_fcs_w_decap_disable:1; 151 /* HW has bug working with tunnel packet decap and scatter FCS. */ 152 uint32_t hw_fcs_strip:1; /* FCS stripping is supported. */ 153 uint32_t rt_timestamp:1; /* Realtime timestamp format. */ 154 uint32_t rq_delay_drop_en:1; /* Enable RxQ delay drop. */ 155 uint32_t tunnel_en:3; 156 /* Whether tunnel stateless offloads are supported. */ 157 uint32_t ind_table_max_size; 158 /* Maximum receive WQ indirection table size. */ 159 uint32_t tso:1; /* Whether TSO is supported. */ 160 uint32_t tso_max_payload_sz; /* Maximum TCP payload for TSO. */ 161 struct { 162 uint32_t enabled:1; /* Whether MPRQ is enabled. */ 163 uint32_t log_min_stride_size; /* Log min size of a stride. */ 164 uint32_t log_max_stride_size; /* Log max size of a stride. */ 165 uint32_t log_min_stride_num; /* Log min num of strides. */ 166 uint32_t log_max_stride_num; /* Log max num of strides. */ 167 uint32_t log_min_stride_wqe_size; 168 /* Log min WQE size, (size of single stride)*(num of strides).*/ 169 } mprq; /* Capability for Multi-Packet RQ. */ 170 char fw_ver[64]; /* Firmware version of this device. */ 171 }; 172 173 /** Data associated with devices to spawn. */ 174 struct mlx5_dev_spawn_data { 175 uint32_t ifindex; /**< Network interface index. */ 176 uint32_t max_port; /**< Device maximal port index. */ 177 uint32_t phys_port; /**< Device physical port index. */ 178 int pf_bond; /**< bonding device PF index. < 0 - no bonding */ 179 struct mlx5_switch_info info; /**< Switch information. */ 180 const char *phys_dev_name; /**< Name of physical device. */ 181 struct rte_eth_dev *eth_dev; /**< Associated Ethernet device. */ 182 struct rte_pci_device *pci_dev; /**< Backend PCI device. */ 183 struct mlx5_common_device *cdev; /**< Backend common device. */ 184 struct mlx5_bond_info *bond_info; 185 }; 186 187 /** Data associated with socket messages. */ 188 struct mlx5_flow_dump_req { 189 uint32_t port_id; /**< There are plans in DPDK to extend port_id. */ 190 uint64_t flow_id; 191 } __rte_packed; 192 193 struct mlx5_flow_dump_ack { 194 int rc; /**< Return code. */ 195 }; 196 197 LIST_HEAD(mlx5_dev_list, mlx5_dev_ctx_shared); 198 199 /* Shared data between primary and secondary processes. */ 200 struct mlx5_shared_data { 201 rte_spinlock_t lock; 202 /* Global spinlock for primary and secondary processes. */ 203 int init_done; /* Whether primary has done initialization. */ 204 unsigned int secondary_cnt; /* Number of secondary processes init'd. */ 205 }; 206 207 /* Per-process data structure, not visible to other processes. */ 208 struct mlx5_local_data { 209 int init_done; /* Whether a secondary has done initialization. */ 210 }; 211 212 extern struct mlx5_shared_data *mlx5_shared_data; 213 214 /* Dev ops structs */ 215 extern const struct eth_dev_ops mlx5_dev_ops; 216 extern const struct eth_dev_ops mlx5_dev_sec_ops; 217 extern const struct eth_dev_ops mlx5_dev_ops_isolate; 218 219 struct mlx5_counter_ctrl { 220 /* Name of the counter. */ 221 char dpdk_name[RTE_ETH_XSTATS_NAME_SIZE]; 222 /* Name of the counter on the device table. */ 223 char ctr_name[RTE_ETH_XSTATS_NAME_SIZE]; 224 uint32_t dev:1; /**< Nonzero for dev counters. */ 225 }; 226 227 struct mlx5_xstats_ctrl { 228 /* Number of device stats. */ 229 uint16_t stats_n; 230 /* Number of device stats identified by PMD. */ 231 uint16_t mlx5_stats_n; 232 /* Index in the device counters table. */ 233 uint16_t dev_table_idx[MLX5_MAX_XSTATS]; 234 uint64_t base[MLX5_MAX_XSTATS]; 235 uint64_t xstats[MLX5_MAX_XSTATS]; 236 uint64_t hw_stats[MLX5_MAX_XSTATS]; 237 struct mlx5_counter_ctrl info[MLX5_MAX_XSTATS]; 238 }; 239 240 struct mlx5_stats_ctrl { 241 /* Base for imissed counter. */ 242 uint64_t imissed_base; 243 uint64_t imissed; 244 }; 245 246 /* Maximal size of coalesced segment for LRO is set in chunks of 256 Bytes. */ 247 #define MLX5_LRO_SEG_CHUNK_SIZE 256u 248 249 /* Maximal size of aggregated LRO packet. */ 250 #define MLX5_MAX_LRO_SIZE (UINT8_MAX * MLX5_LRO_SEG_CHUNK_SIZE) 251 252 /* Maximal number of segments to split. */ 253 #define MLX5_MAX_RXQ_NSEG (1u << MLX5_MAX_LOG_RQ_SEGS) 254 255 /* 256 * Port configuration structure. 257 * User device parameters disabled features. 258 * This structure contains all configurations coming from devargs which 259 * oriented to port. When probing again, devargs doesn't have to be compatible 260 * with primary devargs. It is updated for each port in spawn function. 261 */ 262 struct mlx5_port_config { 263 unsigned int hw_vlan_insert:1; /* VLAN insertion in WQE is supported. */ 264 unsigned int hw_padding:1; /* End alignment padding is supported. */ 265 unsigned int cqe_comp:1; /* CQE compression is enabled. */ 266 unsigned int cqe_comp_fmt:3; /* CQE compression format. */ 267 unsigned int rx_vec_en:1; /* Rx vector is enabled. */ 268 unsigned int std_delay_drop:1; /* Enable standard Rxq delay drop. */ 269 unsigned int hp_delay_drop:1; /* Enable hairpin Rxq delay drop. */ 270 struct { 271 unsigned int enabled:1; /* Whether MPRQ is enabled. */ 272 unsigned int log_stride_num; /* Log number of strides. */ 273 unsigned int log_stride_size; /* Log size of a stride. */ 274 unsigned int max_memcpy_len; 275 /* Maximum packet size to memcpy Rx packets. */ 276 unsigned int min_rxqs_num; 277 /* Rx queue count threshold to enable MPRQ. */ 278 } mprq; /* Configurations for Multi-Packet RQ. */ 279 int mps; /* Multi-packet send supported mode. */ 280 unsigned int max_dump_files_num; /* Maximum dump files per queue. */ 281 unsigned int log_hp_size; /* Single hairpin queue data size in total. */ 282 unsigned int lro_timeout; /* LRO user configuration. */ 283 int txqs_inline; /* Queue number threshold for inlining. */ 284 int txq_inline_min; /* Minimal amount of data bytes to inline. */ 285 int txq_inline_max; /* Max packet size for inlining with SEND. */ 286 int txq_inline_mpw; /* Max packet size for inlining with eMPW. */ 287 }; 288 289 /* 290 * Share context device configuration structure. 291 * User device parameters disabled features. 292 * This structure updated once for device in mlx5_alloc_shared_dev_ctx() 293 * function and cannot change even when probing again. 294 */ 295 struct mlx5_sh_config { 296 int tx_pp; /* Timestamp scheduling granularity in nanoseconds. */ 297 int tx_skew; /* Tx scheduling skew between WQE and data on wire. */ 298 uint32_t reclaim_mode:2; /* Memory reclaim mode. */ 299 uint32_t dv_esw_en:1; /* Enable E-Switch DV flow. */ 300 /* Enable DV flow. 1 means SW steering, 2 means HW steering. */ 301 unsigned int dv_flow_en:2; 302 uint32_t dv_xmeta_en:2; /* Enable extensive flow metadata. */ 303 uint32_t dv_miss_info:1; /* Restore packet after partial hw miss. */ 304 uint32_t l3_vxlan_en:1; /* Enable L3 VXLAN flow creation. */ 305 uint32_t vf_nl_en:1; /* Enable Netlink requests in VF mode. */ 306 uint32_t lacp_by_user:1; /* Enable user to manage LACP traffic. */ 307 uint32_t decap_en:1; /* Whether decap will be used or not. */ 308 uint32_t hw_fcs_strip:1; /* FCS stripping is supported. */ 309 uint32_t allow_duplicate_pattern:1; 310 uint32_t lro_allowed:1; /* Whether LRO is allowed. */ 311 /* Allow/Prevent the duplicate rules pattern. */ 312 }; 313 314 315 /* Structure for VF VLAN workaround. */ 316 struct mlx5_vf_vlan { 317 uint32_t tag:12; 318 uint32_t created:1; 319 }; 320 321 /* Flow drop context necessary due to Verbs API. */ 322 struct mlx5_drop { 323 struct mlx5_hrxq *hrxq; /* Hash Rx queue queue. */ 324 struct mlx5_rxq_priv *rxq; /* Rx queue. */ 325 }; 326 327 /* Loopback dummy queue resources required due to Verbs API. */ 328 struct mlx5_lb_ctx { 329 struct ibv_qp *qp; /* QP object. */ 330 void *ibv_cq; /* Completion queue. */ 331 uint16_t refcnt; /* Reference count for representors. */ 332 }; 333 334 /* HW steering queue job descriptor type. */ 335 enum { 336 MLX5_HW_Q_JOB_TYPE_CREATE, /* Flow create job type. */ 337 MLX5_HW_Q_JOB_TYPE_DESTROY, /* Flow destroy job type. */ 338 }; 339 340 /* HW steering flow management job descriptor. */ 341 struct mlx5_hw_q_job { 342 uint32_t type; /* Job type. */ 343 struct rte_flow_hw *flow; /* Flow attached to the job. */ 344 void *user_data; /* Job user data. */ 345 uint8_t *encap_data; /* Encap data. */ 346 }; 347 348 /* HW steering job descriptor LIFO pool. */ 349 struct mlx5_hw_q { 350 uint32_t job_idx; /* Free job index. */ 351 uint32_t size; /* LIFO size. */ 352 struct mlx5_hw_q_job **job; /* LIFO header. */ 353 } __rte_cache_aligned; 354 355 #define MLX5_COUNTERS_PER_POOL 512 356 #define MLX5_MAX_PENDING_QUERIES 4 357 #define MLX5_CNT_CONTAINER_RESIZE 64 358 #define MLX5_CNT_SHARED_OFFSET 0x80000000 359 #define IS_BATCH_CNT(cnt) (((cnt) & (MLX5_CNT_SHARED_OFFSET - 1)) >= \ 360 MLX5_CNT_BATCH_OFFSET) 361 #define MLX5_CNT_SIZE (sizeof(struct mlx5_flow_counter)) 362 #define MLX5_AGE_SIZE (sizeof(struct mlx5_age_param)) 363 364 #define MLX5_CNT_LEN(pool) \ 365 (MLX5_CNT_SIZE + \ 366 ((pool)->is_aged ? MLX5_AGE_SIZE : 0)) 367 #define MLX5_POOL_GET_CNT(pool, index) \ 368 ((struct mlx5_flow_counter *) \ 369 ((uint8_t *)((pool) + 1) + (index) * (MLX5_CNT_LEN(pool)))) 370 #define MLX5_CNT_ARRAY_IDX(pool, cnt) \ 371 ((int)(((uint8_t *)(cnt) - (uint8_t *)((pool) + 1)) / \ 372 MLX5_CNT_LEN(pool))) 373 #define MLX5_TS_MASK_SECS 8ull 374 /* timestamp wrapping in seconds, must be power of 2. */ 375 376 /* 377 * The pool index and offset of counter in the pool array makes up the 378 * counter index. In case the counter is from pool 0 and offset 0, it 379 * should plus 1 to avoid index 0, since 0 means invalid counter index 380 * currently. 381 */ 382 #define MLX5_MAKE_CNT_IDX(pi, offset) \ 383 ((pi) * MLX5_COUNTERS_PER_POOL + (offset) + 1) 384 #define MLX5_CNT_TO_AGE(cnt) \ 385 ((struct mlx5_age_param *)((cnt) + 1)) 386 /* 387 * The maximum single counter is 0x800000 as MLX5_CNT_BATCH_OFFSET 388 * defines. The pool size is 512, pool index should never reach 389 * INT16_MAX. 390 */ 391 #define POOL_IDX_INVALID UINT16_MAX 392 393 /* Age status. */ 394 enum { 395 AGE_FREE, /* Initialized state. */ 396 AGE_CANDIDATE, /* Counter assigned to flows. */ 397 AGE_TMOUT, /* Timeout, wait for rte_flow_get_aged_flows and destroy. */ 398 }; 399 400 enum mlx5_counter_type { 401 MLX5_COUNTER_TYPE_ORIGIN, 402 MLX5_COUNTER_TYPE_AGE, 403 MLX5_COUNTER_TYPE_MAX, 404 }; 405 406 /* Counter age parameter. */ 407 struct mlx5_age_param { 408 uint16_t state; /**< Age state (atomically accessed). */ 409 uint16_t port_id; /**< Port id of the counter. */ 410 uint32_t timeout:24; /**< Aging timeout in seconds. */ 411 uint32_t sec_since_last_hit; 412 /**< Time in seconds since last hit (atomically accessed). */ 413 void *context; /**< Flow counter age context. */ 414 }; 415 416 struct flow_counter_stats { 417 uint64_t hits; 418 uint64_t bytes; 419 }; 420 421 /* Shared counters information for counters. */ 422 struct mlx5_flow_counter_shared { 423 union { 424 uint32_t refcnt; /* Only for shared action management. */ 425 uint32_t id; /* User counter ID for legacy sharing. */ 426 }; 427 }; 428 429 struct mlx5_flow_counter_pool; 430 /* Generic counters information. */ 431 struct mlx5_flow_counter { 432 union { 433 /* 434 * User-defined counter shared info is only used during 435 * counter active time. And aging counter sharing is not 436 * supported, so active shared counter will not be chained 437 * to the aging list. For shared counter, only when it is 438 * released, the TAILQ entry memory will be used, at that 439 * time, shared memory is not used anymore. 440 * 441 * Similarly to none-batch counter dcs, since it doesn't 442 * support aging, while counter is allocated, the entry 443 * memory is not used anymore. In this case, as bytes 444 * memory is used only when counter is allocated, and 445 * entry memory is used only when counter is free. The 446 * dcs pointer can be saved to these two different place 447 * at different stage. It will eliminate the individual 448 * counter extend struct. 449 */ 450 TAILQ_ENTRY(mlx5_flow_counter) next; 451 /**< Pointer to the next flow counter structure. */ 452 struct { 453 struct mlx5_flow_counter_shared shared_info; 454 /**< Shared counter information. */ 455 void *dcs_when_active; 456 /* 457 * For non-batch mode, the dcs will be saved 458 * here when the counter is free. 459 */ 460 }; 461 }; 462 union { 463 uint64_t hits; /**< Reset value of hits packets. */ 464 struct mlx5_flow_counter_pool *pool; /**< Counter pool. */ 465 }; 466 union { 467 uint64_t bytes; /**< Reset value of bytes. */ 468 void *dcs_when_free; 469 /* 470 * For non-batch mode, the dcs will be saved here 471 * when the counter is free. 472 */ 473 }; 474 void *action; /**< Pointer to the dv action. */ 475 }; 476 477 TAILQ_HEAD(mlx5_counters, mlx5_flow_counter); 478 479 /* Generic counter pool structure - query is in pool resolution. */ 480 struct mlx5_flow_counter_pool { 481 TAILQ_ENTRY(mlx5_flow_counter_pool) next; 482 struct mlx5_counters counters[2]; /* Free counter list. */ 483 struct mlx5_devx_obj *min_dcs; 484 /* The devx object of the minimum counter ID. */ 485 uint64_t time_of_last_age_check; 486 /* System time (from rte_rdtsc()) read in the last aging check. */ 487 uint32_t index:30; /* Pool index in container. */ 488 uint32_t is_aged:1; /* Pool with aging counter. */ 489 volatile uint32_t query_gen:1; /* Query round. */ 490 rte_spinlock_t sl; /* The pool lock. */ 491 rte_spinlock_t csl; /* The pool counter free list lock. */ 492 struct mlx5_counter_stats_raw *raw; 493 struct mlx5_counter_stats_raw *raw_hw; 494 /* The raw on HW working. */ 495 }; 496 497 /* Memory management structure for group of counter statistics raws. */ 498 struct mlx5_counter_stats_mem_mng { 499 LIST_ENTRY(mlx5_counter_stats_mem_mng) next; 500 struct mlx5_counter_stats_raw *raws; 501 struct mlx5_pmd_wrapped_mr wm; 502 }; 503 504 /* Raw memory structure for the counter statistics values of a pool. */ 505 struct mlx5_counter_stats_raw { 506 LIST_ENTRY(mlx5_counter_stats_raw) next; 507 struct mlx5_counter_stats_mem_mng *mem_mng; 508 volatile struct flow_counter_stats *data; 509 }; 510 511 TAILQ_HEAD(mlx5_counter_pools, mlx5_flow_counter_pool); 512 513 /* Counter global management structure. */ 514 struct mlx5_flow_counter_mng { 515 volatile uint16_t n_valid; /* Number of valid pools. */ 516 uint16_t n; /* Number of pools. */ 517 uint16_t last_pool_idx; /* Last used pool index */ 518 int min_id; /* The minimum counter ID in the pools. */ 519 int max_id; /* The maximum counter ID in the pools. */ 520 rte_spinlock_t pool_update_sl; /* The pool update lock. */ 521 rte_spinlock_t csl[MLX5_COUNTER_TYPE_MAX]; 522 /* The counter free list lock. */ 523 struct mlx5_counters counters[MLX5_COUNTER_TYPE_MAX]; 524 /* Free counter list. */ 525 struct mlx5_flow_counter_pool **pools; /* Counter pool array. */ 526 struct mlx5_counter_stats_mem_mng *mem_mng; 527 /* Hold the memory management for the next allocated pools raws. */ 528 struct mlx5_counters flow_counters; /* Legacy flow counter list. */ 529 uint8_t pending_queries; 530 uint16_t pool_index; 531 uint8_t query_thread_on; 532 bool counter_fallback; /* Use counter fallback management. */ 533 LIST_HEAD(mem_mngs, mlx5_counter_stats_mem_mng) mem_mngs; 534 LIST_HEAD(stat_raws, mlx5_counter_stats_raw) free_stat_raws; 535 }; 536 537 /* ASO structures. */ 538 #define MLX5_ASO_QUEUE_LOG_DESC 10 539 540 struct mlx5_aso_cq { 541 uint16_t log_desc_n; 542 uint32_t cq_ci:24; 543 struct mlx5_devx_cq cq_obj; 544 uint64_t errors; 545 }; 546 547 struct mlx5_aso_sq_elem { 548 union { 549 struct { 550 struct mlx5_aso_age_pool *pool; 551 uint16_t burst_size; 552 }; 553 struct mlx5_aso_mtr *mtr; 554 struct { 555 struct mlx5_aso_ct_action *ct; 556 char *query_data; 557 }; 558 }; 559 }; 560 561 struct mlx5_aso_sq { 562 uint16_t log_desc_n; 563 rte_spinlock_t sqsl; 564 struct mlx5_aso_cq cq; 565 struct mlx5_devx_sq sq_obj; 566 struct mlx5_pmd_mr mr; 567 uint16_t pi; 568 uint32_t head; 569 uint32_t tail; 570 uint32_t sqn; 571 struct mlx5_aso_sq_elem elts[1 << MLX5_ASO_QUEUE_LOG_DESC]; 572 uint16_t next; /* Pool index of the next pool to query. */ 573 }; 574 575 struct mlx5_aso_age_action { 576 LIST_ENTRY(mlx5_aso_age_action) next; 577 void *dr_action; 578 uint32_t refcnt; 579 /* Following fields relevant only when action is active. */ 580 uint16_t offset; /* Offset of ASO Flow Hit flag in DevX object. */ 581 struct mlx5_age_param age_params; 582 }; 583 584 #define MLX5_ASO_AGE_ACTIONS_PER_POOL 512 585 586 struct mlx5_aso_age_pool { 587 struct mlx5_devx_obj *flow_hit_aso_obj; 588 uint16_t index; /* Pool index in pools array. */ 589 uint64_t time_of_last_age_check; /* In seconds. */ 590 struct mlx5_aso_age_action actions[MLX5_ASO_AGE_ACTIONS_PER_POOL]; 591 }; 592 593 LIST_HEAD(aso_age_list, mlx5_aso_age_action); 594 595 struct mlx5_aso_age_mng { 596 struct mlx5_aso_age_pool **pools; 597 uint16_t n; /* Total number of pools. */ 598 uint16_t next; /* Number of pools in use, index of next free pool. */ 599 rte_rwlock_t resize_rwl; /* Lock for resize objects. */ 600 rte_spinlock_t free_sl; /* Lock for free list access. */ 601 struct aso_age_list free; /* Free age actions list - ready to use. */ 602 struct mlx5_aso_sq aso_sq; /* ASO queue objects. */ 603 }; 604 605 /* Management structure for geneve tlv option */ 606 struct mlx5_geneve_tlv_option_resource { 607 struct mlx5_devx_obj *obj; /* Pointer to the geneve tlv opt object. */ 608 rte_be16_t option_class; /* geneve tlv opt class.*/ 609 uint8_t option_type; /* geneve tlv opt type.*/ 610 uint8_t length; /* geneve tlv opt length. */ 611 uint32_t refcnt; /* geneve tlv object reference counter */ 612 }; 613 614 615 #define MLX5_AGE_EVENT_NEW 1 616 #define MLX5_AGE_TRIGGER 2 617 #define MLX5_AGE_SET(age_info, BIT) \ 618 ((age_info)->flags |= (1 << (BIT))) 619 #define MLX5_AGE_UNSET(age_info, BIT) \ 620 ((age_info)->flags &= ~(1 << (BIT))) 621 #define MLX5_AGE_GET(age_info, BIT) \ 622 ((age_info)->flags & (1 << (BIT))) 623 #define GET_PORT_AGE_INFO(priv) \ 624 (&((priv)->sh->port[(priv)->dev_port - 1].age_info)) 625 /* Current time in seconds. */ 626 #define MLX5_CURR_TIME_SEC (rte_rdtsc() / rte_get_tsc_hz()) 627 628 /* Aging information for per port. */ 629 struct mlx5_age_info { 630 uint8_t flags; /* Indicate if is new event or need to be triggered. */ 631 struct mlx5_counters aged_counters; /* Aged counter list. */ 632 struct aso_age_list aged_aso; /* Aged ASO actions list. */ 633 rte_spinlock_t aged_sl; /* Aged flow list lock. */ 634 }; 635 636 /* Per port data of shared IB device. */ 637 struct mlx5_dev_shared_port { 638 uint32_t ih_port_id; 639 uint32_t devx_ih_port_id; 640 uint32_t nl_ih_port_id; 641 /* 642 * Interrupt handler port_id. Used by shared interrupt 643 * handler to find the corresponding rte_eth device 644 * by IB port index. If value is equal or greater 645 * RTE_MAX_ETHPORTS it means there is no subhandler 646 * installed for specified IB port index. 647 */ 648 struct mlx5_age_info age_info; 649 /* Aging information for per port. */ 650 }; 651 652 /* 653 * Max number of actions per DV flow. 654 * See CREATE_FLOW_MAX_FLOW_ACTIONS_SUPPORTED 655 * in rdma-core file providers/mlx5/verbs.c. 656 */ 657 #define MLX5_DV_MAX_NUMBER_OF_ACTIONS 8 658 659 /* ASO flow meter structures */ 660 /* Modify this value if enum rte_mtr_color changes. */ 661 #define RTE_MTR_DROPPED RTE_COLORS 662 /* Yellow is now supported. */ 663 #define MLX5_MTR_RTE_COLORS (RTE_COLOR_YELLOW + 1) 664 /* table_id 22 bits in mlx5_flow_tbl_key so limit policy number. */ 665 #define MLX5_MAX_SUB_POLICY_TBL_NUM 0x3FFFFF 666 #define MLX5_INVALID_POLICY_ID UINT32_MAX 667 /* Suffix table_id on MLX5_FLOW_TABLE_LEVEL_METER. */ 668 #define MLX5_MTR_TABLE_ID_SUFFIX 1 669 /* Drop table_id on MLX5_FLOW_TABLE_LEVEL_METER. */ 670 #define MLX5_MTR_TABLE_ID_DROP 2 671 /* Priority of the meter policy matcher. */ 672 #define MLX5_MTR_POLICY_MATCHER_PRIO 0 673 /* Green & yellow color valid for now. */ 674 #define MLX5_MTR_POLICY_MODE_ALL 0 675 /* Default policy. */ 676 #define MLX5_MTR_POLICY_MODE_DEF 1 677 /* Only green color valid. */ 678 #define MLX5_MTR_POLICY_MODE_OG 2 679 /* Only yellow color valid. */ 680 #define MLX5_MTR_POLICY_MODE_OY 3 681 682 enum mlx5_meter_domain { 683 MLX5_MTR_DOMAIN_INGRESS, 684 MLX5_MTR_DOMAIN_EGRESS, 685 MLX5_MTR_DOMAIN_TRANSFER, 686 MLX5_MTR_DOMAIN_MAX, 687 }; 688 #define MLX5_MTR_DOMAIN_INGRESS_BIT (1 << MLX5_MTR_DOMAIN_INGRESS) 689 #define MLX5_MTR_DOMAIN_EGRESS_BIT (1 << MLX5_MTR_DOMAIN_EGRESS) 690 #define MLX5_MTR_DOMAIN_TRANSFER_BIT (1 << MLX5_MTR_DOMAIN_TRANSFER) 691 #define MLX5_MTR_ALL_DOMAIN_BIT (MLX5_MTR_DOMAIN_INGRESS_BIT | \ 692 MLX5_MTR_DOMAIN_EGRESS_BIT | \ 693 MLX5_MTR_DOMAIN_TRANSFER_BIT) 694 695 /* The color tag rule structure. */ 696 struct mlx5_sub_policy_color_rule { 697 void *rule; 698 /* The color rule. */ 699 struct mlx5_flow_dv_matcher *matcher; 700 /* The color matcher. */ 701 TAILQ_ENTRY(mlx5_sub_policy_color_rule) next_port; 702 /**< Pointer to the next color rule structure. */ 703 int32_t src_port; 704 /* On which src port this rule applied. */ 705 }; 706 707 TAILQ_HEAD(mlx5_sub_policy_color_rules, mlx5_sub_policy_color_rule); 708 709 /* 710 * Meter sub-policy structure. 711 * Each RSS TIR in meter policy need its own sub-policy resource. 712 */ 713 struct mlx5_flow_meter_sub_policy { 714 uint32_t main_policy_id:1; 715 /* Main policy id is same as this sub_policy id. */ 716 uint32_t idx:31; 717 /* Index to sub_policy ipool entity. */ 718 void *main_policy; 719 /* Point to struct mlx5_flow_meter_policy. */ 720 struct mlx5_flow_tbl_resource *tbl_rsc; 721 /* The sub-policy table resource. */ 722 uint32_t rix_hrxq[MLX5_MTR_RTE_COLORS]; 723 /* Index to TIR resource. */ 724 struct mlx5_flow_tbl_resource *jump_tbl[MLX5_MTR_RTE_COLORS]; 725 /* Meter jump/drop table. */ 726 struct mlx5_sub_policy_color_rules color_rules[RTE_COLORS]; 727 /* List for the color rules. */ 728 }; 729 730 struct mlx5_meter_policy_acts { 731 uint8_t actions_n; 732 /* Number of actions. */ 733 void *dv_actions[MLX5_DV_MAX_NUMBER_OF_ACTIONS]; 734 /* Action list. */ 735 }; 736 737 struct mlx5_meter_policy_action_container { 738 uint32_t rix_mark; 739 /* Index to the mark action. */ 740 struct mlx5_flow_dv_modify_hdr_resource *modify_hdr; 741 /* Pointer to modify header resource in cache. */ 742 uint8_t fate_action; 743 /* Fate action type. */ 744 union { 745 struct rte_flow_action *rss; 746 /* Rss action configuration. */ 747 uint32_t rix_port_id_action; 748 /* Index to port ID action resource. */ 749 void *dr_jump_action[MLX5_MTR_DOMAIN_MAX]; 750 /* Jump/drop action per color. */ 751 uint16_t queue; 752 /* Queue action configuration. */ 753 struct { 754 uint32_t next_mtr_id; 755 /* The next meter id. */ 756 void *next_sub_policy; 757 /* Next meter's sub-policy. */ 758 }; 759 }; 760 }; 761 762 /* Flow meter policy parameter structure. */ 763 struct mlx5_flow_meter_policy { 764 struct rte_eth_dev *dev; 765 /* The port dev on which policy is created. */ 766 uint32_t is_rss:1; 767 /* Is RSS policy table. */ 768 uint32_t ingress:1; 769 /* Rule applies to ingress domain. */ 770 uint32_t egress:1; 771 /* Rule applies to egress domain. */ 772 uint32_t transfer:1; 773 /* Rule applies to transfer domain. */ 774 uint32_t is_queue:1; 775 /* Is queue action in policy table. */ 776 uint32_t is_hierarchy:1; 777 /* Is meter action in policy table. */ 778 uint32_t hierarchy_drop_cnt:1; 779 /* Is any meter in hierarchy contains drop_cnt. */ 780 uint32_t skip_y:1; 781 /* If yellow color policy is skipped. */ 782 uint32_t skip_g:1; 783 /* If green color policy is skipped. */ 784 uint32_t mark:1; 785 /* If policy contains mark action. */ 786 rte_spinlock_t sl; 787 uint32_t ref_cnt; 788 /* Use count. */ 789 struct mlx5_meter_policy_action_container act_cnt[MLX5_MTR_RTE_COLORS]; 790 /* Policy actions container. */ 791 void *dr_drop_action[MLX5_MTR_DOMAIN_MAX]; 792 /* drop action for red color. */ 793 uint16_t sub_policy_num; 794 /* Count sub policy tables, 3 bits per domain. */ 795 struct mlx5_flow_meter_sub_policy **sub_policys[MLX5_MTR_DOMAIN_MAX]; 796 /* Sub policy table array must be the end of struct. */ 797 }; 798 799 /* The maximum sub policy is relate to struct mlx5_rss_hash_fields[]. */ 800 #define MLX5_MTR_RSS_MAX_SUB_POLICY 7 801 #define MLX5_MTR_SUB_POLICY_NUM_SHIFT 3 802 #define MLX5_MTR_SUB_POLICY_NUM_MASK 0x7 803 #define MLX5_MTRS_DEFAULT_RULE_PRIORITY 0xFFFF 804 #define MLX5_MTR_CHAIN_MAX_NUM 8 805 806 /* Flow meter default policy parameter structure. 807 * Policy index 0 is reserved by default policy table. 808 * Action per color as below: 809 * green - do nothing, yellow - do nothing, red - drop 810 */ 811 struct mlx5_flow_meter_def_policy { 812 struct mlx5_flow_meter_sub_policy sub_policy; 813 /* Policy rules jump to other tables. */ 814 void *dr_jump_action[RTE_COLORS]; 815 /* Jump action per color. */ 816 }; 817 818 /* Meter parameter structure. */ 819 struct mlx5_flow_meter_info { 820 uint32_t meter_id; 821 /**< Meter id. */ 822 uint32_t policy_id; 823 /* Policy id, the first sub_policy idx. */ 824 struct mlx5_flow_meter_profile *profile; 825 /**< Meter profile parameters. */ 826 rte_spinlock_t sl; /**< Meter action spinlock. */ 827 /** Set of stats counters to be enabled. 828 * @see enum rte_mtr_stats_type 829 */ 830 uint32_t bytes_dropped:1; 831 /** Set bytes dropped stats to be enabled. */ 832 uint32_t pkts_dropped:1; 833 /** Set packets dropped stats to be enabled. */ 834 uint32_t active_state:1; 835 /**< Meter hw active state. */ 836 uint32_t shared:1; 837 /**< Meter shared or not. */ 838 uint32_t is_enable:1; 839 /**< Meter disable/enable state. */ 840 uint32_t ingress:1; 841 /**< Rule applies to egress traffic. */ 842 uint32_t egress:1; 843 /** 844 * Instead of simply matching the properties of traffic as it would 845 * appear on a given DPDK port ID, enabling this attribute transfers 846 * a flow rule to the lowest possible level of any device endpoints 847 * found in the pattern. 848 * 849 * When supported, this effectively enables an application to 850 * re-route traffic not necessarily intended for it (e.g. coming 851 * from or addressed to different physical ports, VFs or 852 * applications) at the device level. 853 * 854 * It complements the behavior of some pattern items such as 855 * RTE_FLOW_ITEM_TYPE_REPRESENTED_PORT and is meaningless without them. 856 * 857 * When transferring flow rules, ingress and egress attributes keep 858 * their original meaning, as if processing traffic emitted or 859 * received by the application. 860 */ 861 uint32_t transfer:1; 862 uint32_t def_policy:1; 863 /* Meter points to default policy. */ 864 uint32_t color_aware:1; 865 /* Meter is color aware mode. */ 866 void *drop_rule[MLX5_MTR_DOMAIN_MAX]; 867 /* Meter drop rule in drop table. */ 868 uint32_t drop_cnt; 869 /**< Color counter for drop. */ 870 uint32_t ref_cnt; 871 /**< Use count. */ 872 struct mlx5_indexed_pool *flow_ipool; 873 /**< Index pool for flow id. */ 874 void *meter_action_g; 875 /**< Flow meter action. */ 876 void *meter_action_y; 877 /**< Flow meter action for yellow init_color. */ 878 }; 879 880 /* PPS(packets per second) map to BPS(Bytes per second). 881 * HW treat packet as 128bytes in PPS mode 882 */ 883 #define MLX5_MTRS_PPS_MAP_BPS_SHIFT 7 884 885 /* RFC2697 parameter structure. */ 886 struct mlx5_flow_meter_srtcm_rfc2697_prm { 887 rte_be32_t cbs_cir; 888 /* 889 * bit 24-28: cbs_exponent, bit 16-23 cbs_mantissa, 890 * bit 8-12: cir_exponent, bit 0-7 cir_mantissa. 891 */ 892 rte_be32_t ebs_eir; 893 /* 894 * bit 24-28: ebs_exponent, bit 16-23 ebs_mantissa, 895 * bit 8-12: eir_exponent, bit 0-7 eir_mantissa. 896 */ 897 }; 898 899 /* Flow meter profile structure. */ 900 struct mlx5_flow_meter_profile { 901 TAILQ_ENTRY(mlx5_flow_meter_profile) next; 902 /**< Pointer to the next flow meter structure. */ 903 uint32_t id; /**< Profile id. */ 904 struct rte_mtr_meter_profile profile; /**< Profile detail. */ 905 union { 906 struct mlx5_flow_meter_srtcm_rfc2697_prm srtcm_prm; 907 /**< srtcm_rfc2697 struct. */ 908 }; 909 uint32_t ref_cnt; /**< Use count. */ 910 uint32_t g_support:1; /**< If G color will be generated. */ 911 uint32_t y_support:1; /**< If Y color will be generated. */ 912 }; 913 914 /* 2 meters in each ASO cache line */ 915 #define MLX5_MTRS_CONTAINER_RESIZE 64 916 /* 917 * The pool index and offset of meter in the pool array makes up the 918 * meter index. In case the meter is from pool 0 and offset 0, it 919 * should plus 1 to avoid index 0, since 0 means invalid meter index 920 * currently. 921 */ 922 #define MLX5_MAKE_MTR_IDX(pi, offset) \ 923 ((pi) * MLX5_ASO_MTRS_PER_POOL + (offset) + 1) 924 925 /*aso flow meter state*/ 926 enum mlx5_aso_mtr_state { 927 ASO_METER_FREE, /* In free list. */ 928 ASO_METER_WAIT, /* ACCESS_ASO WQE in progress. */ 929 ASO_METER_READY, /* CQE received. */ 930 }; 931 932 /* Generic aso_flow_meter information. */ 933 struct mlx5_aso_mtr { 934 LIST_ENTRY(mlx5_aso_mtr) next; 935 struct mlx5_flow_meter_info fm; 936 /**< Pointer to the next aso flow meter structure. */ 937 uint8_t state; /**< ASO flow meter state. */ 938 uint8_t offset; 939 }; 940 941 /* Generic aso_flow_meter pool structure. */ 942 struct mlx5_aso_mtr_pool { 943 struct mlx5_aso_mtr mtrs[MLX5_ASO_MTRS_PER_POOL]; 944 /*Must be the first in pool*/ 945 struct mlx5_devx_obj *devx_obj; 946 /* The devx object of the minimum aso flow meter ID. */ 947 uint32_t index; /* Pool index in management structure. */ 948 }; 949 950 LIST_HEAD(aso_meter_list, mlx5_aso_mtr); 951 /* Pools management structure for ASO flow meter pools. */ 952 struct mlx5_aso_mtr_pools_mng { 953 volatile uint16_t n_valid; /* Number of valid pools. */ 954 uint16_t n; /* Number of pools. */ 955 rte_spinlock_t mtrsl; /* The ASO flow meter free list lock. */ 956 rte_rwlock_t resize_mtrwl; /* Lock for resize objects. */ 957 struct aso_meter_list meters; /* Free ASO flow meter list. */ 958 struct mlx5_aso_sq sq; /*SQ using by ASO flow meter. */ 959 struct mlx5_aso_mtr_pool **pools; /* ASO flow meter pool array. */ 960 }; 961 962 /* Meter management structure for global flow meter resource. */ 963 struct mlx5_flow_mtr_mng { 964 struct mlx5_aso_mtr_pools_mng pools_mng; 965 /* Pools management structure for ASO flow meter pools. */ 966 struct mlx5_flow_meter_def_policy *def_policy[MLX5_MTR_DOMAIN_MAX]; 967 /* Default policy table. */ 968 uint32_t def_policy_id; 969 /* Default policy id. */ 970 uint32_t def_policy_ref_cnt; 971 /** def_policy meter use count. */ 972 struct mlx5_flow_tbl_resource *drop_tbl[MLX5_MTR_DOMAIN_MAX]; 973 /* Meter drop table. */ 974 struct mlx5_flow_dv_matcher * 975 drop_matcher[MLX5_MTR_DOMAIN_MAX][MLX5_REG_BITS]; 976 /* Matcher meter in drop table. */ 977 struct mlx5_flow_dv_matcher *def_matcher[MLX5_MTR_DOMAIN_MAX]; 978 /* Default matcher in drop table. */ 979 void *def_rule[MLX5_MTR_DOMAIN_MAX]; 980 /* Default rule in drop table. */ 981 uint8_t max_mtr_bits; 982 /* Indicate how many bits are used by meter id at the most. */ 983 uint8_t max_mtr_flow_bits; 984 /* Indicate how many bits are used by meter flow id at the most. */ 985 }; 986 987 /* Table key of the hash organization. */ 988 union mlx5_flow_tbl_key { 989 struct { 990 /* Table ID should be at the lowest address. */ 991 uint32_t level; /**< Level of the table. */ 992 uint32_t id:22; /**< ID of the table. */ 993 uint32_t dummy:1; /**< Dummy table for DV API. */ 994 uint32_t is_fdb:1; /**< 1 - FDB, 0 - NIC TX/RX. */ 995 uint32_t is_egress:1; /**< 1 - egress, 0 - ingress. */ 996 uint32_t reserved:7; /**< must be zero for comparison. */ 997 }; 998 uint64_t v64; /**< full 64bits value of key */ 999 }; 1000 1001 /* Table structure. */ 1002 struct mlx5_flow_tbl_resource { 1003 void *obj; /**< Pointer to DR table object. */ 1004 }; 1005 1006 #define MLX5_MAX_TABLES UINT16_MAX 1007 #define MLX5_HAIRPIN_TX_TABLE (UINT16_MAX - 1) 1008 /* Reserve the last two tables for metadata register copy. */ 1009 #define MLX5_FLOW_MREG_ACT_TABLE_GROUP (MLX5_MAX_TABLES - 1) 1010 #define MLX5_FLOW_MREG_CP_TABLE_GROUP (MLX5_MAX_TABLES - 2) 1011 /* Tables for metering splits should be added here. */ 1012 #define MLX5_FLOW_TABLE_LEVEL_METER (MLX5_MAX_TABLES - 3) 1013 #define MLX5_FLOW_TABLE_LEVEL_POLICY (MLX5_MAX_TABLES - 4) 1014 #define MLX5_MAX_TABLES_EXTERNAL MLX5_FLOW_TABLE_LEVEL_POLICY 1015 #define MLX5_MAX_TABLES_FDB UINT16_MAX 1016 #define MLX5_FLOW_TABLE_FACTOR 10 1017 1018 /* ID generation structure. */ 1019 struct mlx5_flow_id_pool { 1020 uint32_t *free_arr; /**< Pointer to the a array of free values. */ 1021 uint32_t base_index; 1022 /**< The next index that can be used without any free elements. */ 1023 uint32_t *curr; /**< Pointer to the index to pop. */ 1024 uint32_t *last; /**< Pointer to the last element in the empty array. */ 1025 uint32_t max_id; /**< Maximum id can be allocated from the pool. */ 1026 }; 1027 1028 /* Tx pacing queue structure - for Clock and Rearm queues. */ 1029 struct mlx5_txpp_wq { 1030 /* Completion Queue related data.*/ 1031 struct mlx5_devx_cq cq_obj; 1032 uint32_t cq_ci:24; 1033 uint32_t arm_sn:2; 1034 /* Send Queue related data.*/ 1035 struct mlx5_devx_sq sq_obj; 1036 uint16_t sq_size; /* Number of WQEs in the queue. */ 1037 uint16_t sq_ci; /* Next WQE to execute. */ 1038 }; 1039 1040 /* Tx packet pacing internal timestamp. */ 1041 struct mlx5_txpp_ts { 1042 uint64_t ci_ts; 1043 uint64_t ts; 1044 }; 1045 1046 /* Tx packet pacing structure. */ 1047 struct mlx5_dev_txpp { 1048 pthread_mutex_t mutex; /* Pacing create/destroy mutex. */ 1049 uint32_t refcnt; /* Pacing reference counter. */ 1050 uint32_t freq; /* Timestamp frequency, Hz. */ 1051 uint32_t tick; /* Completion tick duration in nanoseconds. */ 1052 uint32_t test; /* Packet pacing test mode. */ 1053 int32_t skew; /* Scheduling skew. */ 1054 struct rte_intr_handle *intr_handle; /* Periodic interrupt. */ 1055 void *echan; /* Event Channel. */ 1056 struct mlx5_txpp_wq clock_queue; /* Clock Queue. */ 1057 struct mlx5_txpp_wq rearm_queue; /* Clock Queue. */ 1058 void *pp; /* Packet pacing context. */ 1059 uint16_t pp_id; /* Packet pacing context index. */ 1060 uint16_t ts_n; /* Number of captured timestamps. */ 1061 uint16_t ts_p; /* Pointer to statistics timestamp. */ 1062 struct mlx5_txpp_ts *tsa; /* Timestamps sliding window stats. */ 1063 struct mlx5_txpp_ts ts; /* Cached completion id/timestamp. */ 1064 uint32_t sync_lost:1; /* ci/timestamp synchronization lost. */ 1065 /* Statistics counters. */ 1066 uint64_t err_miss_int; /* Missed service interrupt. */ 1067 uint64_t err_rearm_queue; /* Rearm Queue errors. */ 1068 uint64_t err_clock_queue; /* Clock Queue errors. */ 1069 uint64_t err_ts_past; /* Timestamp in the past. */ 1070 uint64_t err_ts_future; /* Timestamp in the distant future. */ 1071 }; 1072 1073 /* Sample ID information of eCPRI flex parser structure. */ 1074 struct mlx5_ecpri_parser_profile { 1075 uint32_t num; /* Actual number of samples. */ 1076 uint32_t ids[8]; /* Sample IDs for this profile. */ 1077 uint8_t offset[8]; /* Bytes offset of each parser. */ 1078 void *obj; /* Flex parser node object. */ 1079 }; 1080 1081 /* Max member ports per bonding device. */ 1082 #define MLX5_BOND_MAX_PORTS 2 1083 1084 /* Bonding device information. */ 1085 struct mlx5_bond_info { 1086 int n_port; /* Number of bond member ports. */ 1087 uint32_t ifindex; 1088 char ifname[MLX5_NAMESIZE + 1]; 1089 struct { 1090 char ifname[MLX5_NAMESIZE + 1]; 1091 uint32_t ifindex; 1092 struct rte_pci_addr pci_addr; 1093 } ports[MLX5_BOND_MAX_PORTS]; 1094 }; 1095 1096 /* Number of connection tracking objects per pool: must be a power of 2. */ 1097 #define MLX5_ASO_CT_ACTIONS_PER_POOL 64 1098 1099 /* Generate incremental and unique CT index from pool and offset. */ 1100 #define MLX5_MAKE_CT_IDX(pool, offset) \ 1101 ((pool) * MLX5_ASO_CT_ACTIONS_PER_POOL + (offset) + 1) 1102 1103 /* ASO Conntrack state. */ 1104 enum mlx5_aso_ct_state { 1105 ASO_CONNTRACK_FREE, /* Inactive, in the free list. */ 1106 ASO_CONNTRACK_WAIT, /* WQE sent in the SQ. */ 1107 ASO_CONNTRACK_READY, /* CQE received w/o error. */ 1108 ASO_CONNTRACK_QUERY, /* WQE for query sent. */ 1109 ASO_CONNTRACK_MAX, /* Guard. */ 1110 }; 1111 1112 /* Generic ASO connection tracking structure. */ 1113 struct mlx5_aso_ct_action { 1114 LIST_ENTRY(mlx5_aso_ct_action) next; /* Pointer to the next ASO CT. */ 1115 void *dr_action_orig; /* General action object for original dir. */ 1116 void *dr_action_rply; /* General action object for reply dir. */ 1117 uint32_t refcnt; /* Action used count in device flows. */ 1118 uint16_t offset; /* Offset of ASO CT in DevX objects bulk. */ 1119 uint16_t peer; /* The only peer port index could also use this CT. */ 1120 enum mlx5_aso_ct_state state; /* ASO CT state. */ 1121 bool is_original; /* The direction of the DR action to be used. */ 1122 }; 1123 1124 /* CT action object state update. */ 1125 #define MLX5_ASO_CT_UPDATE_STATE(c, s) \ 1126 __atomic_store_n(&((c)->state), (s), __ATOMIC_RELAXED) 1127 1128 /* ASO connection tracking software pool definition. */ 1129 struct mlx5_aso_ct_pool { 1130 uint16_t index; /* Pool index in pools array. */ 1131 struct mlx5_devx_obj *devx_obj; 1132 /* The first devx object in the bulk, used for freeing (not yet). */ 1133 struct mlx5_aso_ct_action actions[MLX5_ASO_CT_ACTIONS_PER_POOL]; 1134 /* CT action structures bulk. */ 1135 }; 1136 1137 LIST_HEAD(aso_ct_list, mlx5_aso_ct_action); 1138 1139 /* Pools management structure for ASO connection tracking pools. */ 1140 struct mlx5_aso_ct_pools_mng { 1141 struct mlx5_aso_ct_pool **pools; 1142 uint16_t n; /* Total number of pools. */ 1143 uint16_t next; /* Number of pools in use, index of next free pool. */ 1144 rte_spinlock_t ct_sl; /* The ASO CT free list lock. */ 1145 rte_rwlock_t resize_rwl; /* The ASO CT pool resize lock. */ 1146 struct aso_ct_list free_cts; /* Free ASO CT objects list. */ 1147 struct mlx5_aso_sq aso_sq; /* ASO queue objects. */ 1148 }; 1149 1150 /* LAG attr. */ 1151 struct mlx5_lag { 1152 uint8_t tx_remap_affinity[16]; /* The PF port number of affinity */ 1153 uint8_t affinity_mode; /* TIS or hash based affinity */ 1154 }; 1155 1156 /* DevX flex parser context. */ 1157 struct mlx5_flex_parser_devx { 1158 struct mlx5_list_entry entry; /* List element at the beginning. */ 1159 uint32_t num_samples; 1160 void *devx_obj; 1161 struct mlx5_devx_graph_node_attr devx_conf; 1162 uint32_t sample_ids[MLX5_GRAPH_NODE_SAMPLE_NUM]; 1163 }; 1164 1165 /* Pattern field descriptor - how to translate flex pattern into samples. */ 1166 __extension__ 1167 struct mlx5_flex_pattern_field { 1168 uint16_t width:6; 1169 uint16_t shift:5; 1170 uint16_t reg_id:5; 1171 }; 1172 #define MLX5_INVALID_SAMPLE_REG_ID 0x1F 1173 1174 /* Port flex item context. */ 1175 struct mlx5_flex_item { 1176 struct mlx5_flex_parser_devx *devx_fp; /* DevX flex parser object. */ 1177 uint32_t refcnt; /* Atomically accessed refcnt by flows. */ 1178 enum rte_flow_item_flex_tunnel_mode tunnel_mode; /* Tunnel mode. */ 1179 uint32_t mapnum; /* Number of pattern translation entries. */ 1180 struct mlx5_flex_pattern_field map[MLX5_FLEX_ITEM_MAPPING_NUM]; 1181 }; 1182 1183 /* 1184 * Shared Infiniband device context for Master/Representors 1185 * which belong to same IB device with multiple IB ports. 1186 **/ 1187 struct mlx5_dev_ctx_shared { 1188 LIST_ENTRY(mlx5_dev_ctx_shared) next; 1189 uint32_t refcnt; 1190 uint32_t esw_mode:1; /* Whether is E-Switch mode. */ 1191 uint32_t flow_hit_aso_en:1; /* Flow Hit ASO is supported. */ 1192 uint32_t steering_format_version:4; 1193 /* Indicates the device steering logic format. */ 1194 uint32_t meter_aso_en:1; /* Flow Meter ASO is supported. */ 1195 uint32_t ct_aso_en:1; /* Connection Tracking ASO is supported. */ 1196 uint32_t tunnel_header_0_1:1; /* tunnel_header_0_1 is supported. */ 1197 uint32_t tunnel_header_2_3:1; /* tunnel_header_2_3 is supported. */ 1198 uint32_t misc5_cap:1; /* misc5 matcher parameter is supported. */ 1199 uint32_t dr_drop_action_en:1; /* Use DR drop action. */ 1200 uint32_t drop_action_check_flag:1; /* Check Flag for drop action. */ 1201 uint32_t flow_priority_check_flag:1; /* Check Flag for flow priority. */ 1202 uint32_t metadata_regc_check_flag:1; /* Check Flag for metadata REGC. */ 1203 uint32_t max_port; /* Maximal IB device port index. */ 1204 struct mlx5_bond_info bond; /* Bonding information. */ 1205 struct mlx5_common_device *cdev; /* Backend mlx5 device. */ 1206 uint32_t tdn; /* Transport Domain number. */ 1207 char ibdev_name[MLX5_FS_NAME_MAX]; /* SYSFS dev name. */ 1208 char ibdev_path[MLX5_FS_PATH_MAX]; /* SYSFS dev path for secondary */ 1209 struct mlx5_dev_cap dev_cap; /* Device capabilities. */ 1210 struct mlx5_sh_config config; /* Device configuration. */ 1211 int numa_node; /* Numa node of backing physical device. */ 1212 /* Packet pacing related structure. */ 1213 struct mlx5_dev_txpp txpp; 1214 /* Shared DV/DR flow data section. */ 1215 uint32_t dv_meta_mask; /* flow META metadata supported mask. */ 1216 uint32_t dv_mark_mask; /* flow MARK metadata supported mask. */ 1217 uint32_t dv_regc0_mask; /* available bits of metadata reg_c[0]. */ 1218 void *fdb_domain; /* FDB Direct Rules name space handle. */ 1219 void *rx_domain; /* RX Direct Rules name space handle. */ 1220 void *tx_domain; /* TX Direct Rules name space handle. */ 1221 #ifndef RTE_ARCH_64 1222 rte_spinlock_t uar_lock_cq; /* CQs share a common distinct UAR. */ 1223 rte_spinlock_t uar_lock[MLX5_UAR_PAGE_NUM_MAX]; 1224 /* UAR same-page access control required in 32bit implementations. */ 1225 #endif 1226 union { 1227 struct mlx5_hlist *flow_tbls; /* SWS flow table. */ 1228 struct mlx5_hlist *groups; /* HWS flow group. */ 1229 }; 1230 struct mlx5_flow_tunnel_hub *tunnel_hub; 1231 /* Direct Rules tables for FDB, NIC TX+RX */ 1232 void *dr_drop_action; /* Pointer to DR drop action, any domain. */ 1233 void *pop_vlan_action; /* Pointer to DR pop VLAN action. */ 1234 struct mlx5_hlist *encaps_decaps; /* Encap/decap action hash list. */ 1235 struct mlx5_hlist *modify_cmds; 1236 struct mlx5_hlist *tag_table; 1237 struct mlx5_list *port_id_action_list; /* Port ID action list. */ 1238 struct mlx5_list *push_vlan_action_list; /* Push VLAN actions. */ 1239 struct mlx5_list *sample_action_list; /* List of sample actions. */ 1240 struct mlx5_list *dest_array_list; 1241 struct mlx5_list *flex_parsers_dv; /* Flex Item parsers. */ 1242 /* List of destination array actions. */ 1243 struct mlx5_flow_counter_mng cmng; /* Counters management structure. */ 1244 void *default_miss_action; /* Default miss action. */ 1245 struct mlx5_indexed_pool *ipool[MLX5_IPOOL_MAX]; 1246 struct mlx5_indexed_pool *mdh_ipools[MLX5_MAX_MODIFY_NUM]; 1247 /* Shared interrupt handler section. */ 1248 struct rte_intr_handle *intr_handle; /* Interrupt handler for device. */ 1249 struct rte_intr_handle *intr_handle_devx; /* DEVX interrupt handler. */ 1250 struct rte_intr_handle *intr_handle_nl; /* Netlink interrupt handler. */ 1251 void *devx_comp; /* DEVX async comp obj. */ 1252 struct mlx5_devx_obj *tis[16]; /* TIS object. */ 1253 struct mlx5_devx_obj *td; /* Transport domain. */ 1254 struct mlx5_lag lag; /* LAG attributes */ 1255 struct mlx5_uar tx_uar; /* DevX UAR for Tx and Txpp and ASO SQs. */ 1256 struct mlx5_uar rx_uar; /* DevX UAR for Rx. */ 1257 struct mlx5_proc_priv *pppriv; /* Pointer to primary private process. */ 1258 struct mlx5_ecpri_parser_profile ecpri_parser; 1259 /* Flex parser profiles information. */ 1260 LIST_HEAD(shared_rxqs, mlx5_rxq_ctrl) shared_rxqs; /* Shared RXQs. */ 1261 struct mlx5_aso_age_mng *aso_age_mng; 1262 /* Management data for aging mechanism using ASO Flow Hit. */ 1263 struct mlx5_geneve_tlv_option_resource *geneve_tlv_option_resource; 1264 /* Management structure for geneve tlv option */ 1265 rte_spinlock_t geneve_tlv_opt_sl; /* Lock for geneve tlv resource */ 1266 struct mlx5_flow_mtr_mng *mtrmng; 1267 /* Meter management structure. */ 1268 struct mlx5_aso_ct_pools_mng *ct_mng; 1269 /* Management data for ASO connection tracking. */ 1270 struct mlx5_lb_ctx self_lb; /* QP to enable self loopback for Devx. */ 1271 unsigned int flow_max_priority; 1272 enum modify_reg flow_mreg_c[MLX5_MREG_C_NUM]; 1273 void *devx_channel_lwm; 1274 struct rte_intr_handle *intr_handle_lwm; 1275 pthread_mutex_t lwm_config_lock; 1276 uint32_t host_shaper_rate:8; 1277 uint32_t lwm_triggered:1; 1278 /* Availability of mreg_c's. */ 1279 struct mlx5_dev_shared_port port[]; /* per device port data array. */ 1280 }; 1281 1282 /* 1283 * Per-process private structure. 1284 * Caution, secondary process may rebuild the struct during port start. 1285 */ 1286 struct mlx5_proc_priv { 1287 size_t uar_table_sz; 1288 /* Size of UAR register table. */ 1289 struct mlx5_uar_data uar_table[]; 1290 /* Table of UAR registers for each process. */ 1291 }; 1292 1293 /* MTR profile list. */ 1294 TAILQ_HEAD(mlx5_mtr_profiles, mlx5_flow_meter_profile); 1295 /* MTR list. */ 1296 TAILQ_HEAD(mlx5_legacy_flow_meters, mlx5_legacy_flow_meter); 1297 1298 /* RSS description. */ 1299 struct mlx5_flow_rss_desc { 1300 uint32_t level; 1301 uint32_t queue_num; /**< Number of entries in @p queue. */ 1302 uint64_t types; /**< Specific RSS hash types (see RTE_ETH_RSS_*). */ 1303 uint64_t hash_fields; /* Verbs Hash fields. */ 1304 uint8_t key[MLX5_RSS_HASH_KEY_LEN]; /**< RSS hash key. */ 1305 uint32_t key_len; /**< RSS hash key len. */ 1306 uint32_t hws_flags; /**< HW steering action. */ 1307 uint32_t tunnel; /**< Queue in tunnel. */ 1308 uint32_t shared_rss; /**< Shared RSS index. */ 1309 struct mlx5_ind_table_obj *ind_tbl; 1310 /**< Indirection table for shared RSS hash RX queues. */ 1311 union { 1312 uint16_t *queue; /**< Destination queues. */ 1313 const uint16_t *const_q; /**< Const pointer convert. */ 1314 }; 1315 }; 1316 1317 #define MLX5_PROC_PRIV(port_id) \ 1318 ((struct mlx5_proc_priv *)rte_eth_devices[port_id].process_private) 1319 1320 /* Verbs/DevX Rx queue elements. */ 1321 struct mlx5_rxq_obj { 1322 LIST_ENTRY(mlx5_rxq_obj) next; /* Pointer to the next element. */ 1323 struct mlx5_rxq_ctrl *rxq_ctrl; /* Back pointer to parent. */ 1324 int fd; /* File descriptor for event channel */ 1325 RTE_STD_C11 1326 union { 1327 struct { 1328 void *wq; /* Work Queue. */ 1329 void *ibv_cq; /* Completion Queue. */ 1330 void *ibv_channel; 1331 }; 1332 struct mlx5_devx_obj *rq; /* DevX RQ object for hairpin. */ 1333 struct { 1334 struct mlx5_devx_rmp devx_rmp; /* RMP for shared RQ. */ 1335 struct mlx5_devx_cq cq_obj; /* DevX CQ object. */ 1336 void *devx_channel; 1337 }; 1338 }; 1339 }; 1340 1341 /* Indirection table. */ 1342 struct mlx5_ind_table_obj { 1343 LIST_ENTRY(mlx5_ind_table_obj) next; /* Pointer to the next element. */ 1344 uint32_t refcnt; /* Reference counter. */ 1345 RTE_STD_C11 1346 union { 1347 void *ind_table; /**< Indirection table. */ 1348 struct mlx5_devx_obj *rqt; /* DevX RQT object. */ 1349 }; 1350 uint32_t queues_n; /**< Number of queues in the list. */ 1351 uint16_t *queues; /**< Queue list. */ 1352 }; 1353 1354 /* Hash Rx queue. */ 1355 __extension__ 1356 struct mlx5_hrxq { 1357 struct mlx5_list_entry entry; /* List entry. */ 1358 uint32_t standalone:1; /* This object used in shared action. */ 1359 struct mlx5_ind_table_obj *ind_table; /* Indirection table. */ 1360 RTE_STD_C11 1361 union { 1362 void *qp; /* Verbs queue pair. */ 1363 struct mlx5_devx_obj *tir; /* DevX TIR object. */ 1364 }; 1365 #if defined(HAVE_IBV_FLOW_DV_SUPPORT) || !defined(HAVE_INFINIBAND_VERBS_H) 1366 void *action; /* DV QP action pointer. */ 1367 #endif 1368 uint32_t hws_flags; /* Hw steering flags. */ 1369 uint64_t hash_fields; /* Verbs Hash fields. */ 1370 uint32_t rss_key_len; /* Hash key length in bytes. */ 1371 uint32_t idx; /* Hash Rx queue index. */ 1372 uint8_t rss_key[]; /* Hash key. */ 1373 }; 1374 1375 /* Verbs/DevX Tx queue elements. */ 1376 struct mlx5_txq_obj { 1377 LIST_ENTRY(mlx5_txq_obj) next; /* Pointer to the next element. */ 1378 struct mlx5_txq_ctrl *txq_ctrl; /* Pointer to the control queue. */ 1379 RTE_STD_C11 1380 union { 1381 struct { 1382 void *cq; /* Completion Queue. */ 1383 void *qp; /* Queue Pair. */ 1384 }; 1385 struct { 1386 struct mlx5_devx_obj *sq; 1387 /* DevX object for Sx queue. */ 1388 struct mlx5_devx_obj *tis; /* The TIS object. */ 1389 }; 1390 struct { 1391 struct rte_eth_dev *dev; 1392 struct mlx5_devx_cq cq_obj; 1393 /* DevX CQ object and its resources. */ 1394 struct mlx5_devx_sq sq_obj; 1395 /* DevX SQ object and its resources. */ 1396 }; 1397 }; 1398 }; 1399 1400 enum mlx5_rxq_modify_type { 1401 MLX5_RXQ_MOD_ERR2RST, /* modify state from error to reset. */ 1402 MLX5_RXQ_MOD_RST2RDY, /* modify state from reset to ready. */ 1403 MLX5_RXQ_MOD_RDY2ERR, /* modify state from ready to error. */ 1404 MLX5_RXQ_MOD_RDY2RST, /* modify state from ready to reset. */ 1405 MLX5_RXQ_MOD_RDY2RDY, /* modify state from ready to ready. */ 1406 }; 1407 1408 enum mlx5_txq_modify_type { 1409 MLX5_TXQ_MOD_RST2RDY, /* modify state from reset to ready. */ 1410 MLX5_TXQ_MOD_RDY2RST, /* modify state from ready to reset. */ 1411 MLX5_TXQ_MOD_ERR2RDY, /* modify state from error to ready. */ 1412 }; 1413 1414 struct mlx5_rxq_priv; 1415 struct mlx5_priv; 1416 1417 /* HW objects operations structure. */ 1418 struct mlx5_obj_ops { 1419 int (*rxq_obj_modify_vlan_strip)(struct mlx5_rxq_priv *rxq, int on); 1420 int (*rxq_obj_new)(struct mlx5_rxq_priv *rxq); 1421 int (*rxq_event_get)(struct mlx5_rxq_obj *rxq_obj); 1422 int (*rxq_obj_modify)(struct mlx5_rxq_priv *rxq, uint8_t type); 1423 void (*rxq_obj_release)(struct mlx5_rxq_priv *rxq); 1424 int (*rxq_event_get_lwm)(struct mlx5_priv *priv, int *rxq_idx, int *port_id); 1425 int (*ind_table_new)(struct rte_eth_dev *dev, const unsigned int log_n, 1426 struct mlx5_ind_table_obj *ind_tbl); 1427 int (*ind_table_modify)(struct rte_eth_dev *dev, 1428 const unsigned int log_n, 1429 const uint16_t *queues, const uint32_t queues_n, 1430 struct mlx5_ind_table_obj *ind_tbl); 1431 void (*ind_table_destroy)(struct mlx5_ind_table_obj *ind_tbl); 1432 int (*hrxq_new)(struct rte_eth_dev *dev, struct mlx5_hrxq *hrxq, 1433 int tunnel __rte_unused); 1434 int (*hrxq_modify)(struct rte_eth_dev *dev, struct mlx5_hrxq *hrxq, 1435 const uint8_t *rss_key, 1436 uint64_t hash_fields, 1437 const struct mlx5_ind_table_obj *ind_tbl); 1438 void (*hrxq_destroy)(struct mlx5_hrxq *hrxq); 1439 int (*drop_action_create)(struct rte_eth_dev *dev); 1440 void (*drop_action_destroy)(struct rte_eth_dev *dev); 1441 int (*txq_obj_new)(struct rte_eth_dev *dev, uint16_t idx); 1442 int (*txq_obj_modify)(struct mlx5_txq_obj *obj, 1443 enum mlx5_txq_modify_type type, uint8_t dev_port); 1444 void (*txq_obj_release)(struct mlx5_txq_obj *txq_obj); 1445 int (*lb_dummy_queue_create)(struct rte_eth_dev *dev); 1446 void (*lb_dummy_queue_release)(struct rte_eth_dev *dev); 1447 }; 1448 1449 #define MLX5_RSS_HASH_FIELDS_LEN RTE_DIM(mlx5_rss_hash_fields) 1450 1451 struct mlx5_priv { 1452 struct rte_eth_dev_data *dev_data; /* Pointer to device data. */ 1453 struct mlx5_dev_ctx_shared *sh; /* Shared device context. */ 1454 uint32_t dev_port; /* Device port number. */ 1455 struct rte_pci_device *pci_dev; /* Backend PCI device. */ 1456 struct rte_ether_addr mac[MLX5_MAX_MAC_ADDRESSES]; /* MAC addresses. */ 1457 BITFIELD_DECLARE(mac_own, uint64_t, MLX5_MAX_MAC_ADDRESSES); 1458 /* Bit-field of MAC addresses owned by the PMD. */ 1459 uint16_t vlan_filter[MLX5_MAX_VLAN_IDS]; /* VLAN filters table. */ 1460 unsigned int vlan_filter_n; /* Number of configured VLAN filters. */ 1461 /* Device properties. */ 1462 uint16_t mtu; /* Configured MTU. */ 1463 unsigned int isolated:1; /* Whether isolated mode is enabled. */ 1464 unsigned int representor:1; /* Device is a port representor. */ 1465 unsigned int master:1; /* Device is a E-Switch master. */ 1466 unsigned int txpp_en:1; /* Tx packet pacing enabled. */ 1467 unsigned int sampler_en:1; /* Whether support sampler. */ 1468 unsigned int mtr_en:1; /* Whether support meter. */ 1469 unsigned int mtr_reg_share:1; /* Whether support meter REG_C share. */ 1470 unsigned int lb_used:1; /* Loopback queue is referred to. */ 1471 uint32_t mark_enabled:1; /* If mark action is enabled on rxqs. */ 1472 uint16_t domain_id; /* Switch domain identifier. */ 1473 uint16_t vport_id; /* Associated VF vport index (if any). */ 1474 uint32_t vport_meta_tag; /* Used for vport index match ove VF LAG. */ 1475 uint32_t vport_meta_mask; /* Used for vport index field match mask. */ 1476 uint16_t representor_id; /* UINT16_MAX if not a representor. */ 1477 int32_t pf_bond; /* >=0, representor owner PF index in bonding. */ 1478 unsigned int if_index; /* Associated kernel network device index. */ 1479 /* RX/TX queues. */ 1480 unsigned int rxqs_n; /* RX queues array size. */ 1481 unsigned int txqs_n; /* TX queues array size. */ 1482 struct mlx5_external_rxq *ext_rxqs; /* External RX queues array. */ 1483 struct mlx5_rxq_priv *(*rxq_privs)[]; /* RX queue non-shared data. */ 1484 struct mlx5_txq_data *(*txqs)[]; /* TX queues. */ 1485 struct rte_mempool *mprq_mp; /* Mempool for Multi-Packet RQ. */ 1486 struct rte_eth_rss_conf rss_conf; /* RSS configuration. */ 1487 unsigned int (*reta_idx)[]; /* RETA index table. */ 1488 unsigned int reta_idx_n; /* RETA index size. */ 1489 struct mlx5_drop drop_queue; /* Flow drop queues. */ 1490 void *root_drop_action; /* Pointer to root drop action. */ 1491 struct mlx5_indexed_pool *flows[MLX5_FLOW_TYPE_MAXI]; 1492 /* RTE Flow rules. */ 1493 uint32_t ctrl_flows; /* Control flow rules. */ 1494 rte_spinlock_t flow_list_lock; 1495 struct mlx5_obj_ops obj_ops; /* HW objects operations. */ 1496 LIST_HEAD(rxq, mlx5_rxq_ctrl) rxqsctrl; /* DPDK Rx queues. */ 1497 LIST_HEAD(rxqobj, mlx5_rxq_obj) rxqsobj; /* Verbs/DevX Rx queues. */ 1498 struct mlx5_list *hrxqs; /* Hash Rx queues. */ 1499 LIST_HEAD(txq, mlx5_txq_ctrl) txqsctrl; /* DPDK Tx queues. */ 1500 LIST_HEAD(txqobj, mlx5_txq_obj) txqsobj; /* Verbs/DevX Tx queues. */ 1501 /* Indirection tables. */ 1502 LIST_HEAD(ind_tables, mlx5_ind_table_obj) ind_tbls; 1503 /* Standalone indirect tables. */ 1504 LIST_HEAD(stdl_ind_tables, mlx5_ind_table_obj) standalone_ind_tbls; 1505 /* Pointer to next element. */ 1506 rte_rwlock_t ind_tbls_lock; 1507 uint32_t refcnt; /**< Reference counter. */ 1508 /**< Verbs modify header action object. */ 1509 uint8_t ft_type; /**< Flow table type, Rx or Tx. */ 1510 uint8_t max_lro_msg_size; 1511 uint32_t link_speed_capa; /* Link speed capabilities. */ 1512 struct mlx5_xstats_ctrl xstats_ctrl; /* Extended stats control. */ 1513 struct mlx5_stats_ctrl stats_ctrl; /* Stats control. */ 1514 struct mlx5_port_config config; /* Port configuration. */ 1515 /* Context for Verbs allocator. */ 1516 int nl_socket_rdma; /* Netlink socket (NETLINK_RDMA). */ 1517 int nl_socket_route; /* Netlink socket (NETLINK_ROUTE). */ 1518 struct mlx5_nl_vlan_vmwa_context *vmwa_context; /* VLAN WA context. */ 1519 struct mlx5_hlist *mreg_cp_tbl; 1520 /* Hash table of Rx metadata register copy table. */ 1521 uint8_t mtr_sfx_reg; /* Meter prefix-suffix flow match REG_C. */ 1522 uint8_t mtr_color_reg; /* Meter color match REG_C. */ 1523 struct mlx5_legacy_flow_meters flow_meters; /* MTR list. */ 1524 struct mlx5_l3t_tbl *mtr_profile_tbl; /* Meter index lookup table. */ 1525 struct mlx5_l3t_tbl *policy_idx_tbl; /* Policy index lookup table. */ 1526 struct mlx5_l3t_tbl *mtr_idx_tbl; /* Meter index lookup table. */ 1527 uint8_t skip_default_rss_reta; /* Skip configuration of default reta. */ 1528 uint8_t fdb_def_rule; /* Whether fdb jump to table 1 is configured. */ 1529 struct mlx5_mp_id mp_id; /* ID of a multi-process process */ 1530 LIST_HEAD(fdir, mlx5_fdir_flow) fdir_flows; /* fdir flows. */ 1531 rte_spinlock_t shared_act_sl; /* Shared actions spinlock. */ 1532 uint32_t rss_shared_actions; /* RSS shared actions. */ 1533 struct mlx5_devx_obj *q_counters; /* DevX queue counter object. */ 1534 uint32_t counter_set_id; /* Queue counter ID to set in DevX objects. */ 1535 uint32_t lag_affinity_idx; /* LAG mode queue 0 affinity starting. */ 1536 rte_spinlock_t flex_item_sl; /* Flex item list spinlock. */ 1537 struct mlx5_flex_item flex_item[MLX5_PORT_FLEX_ITEM_NUM]; 1538 /* Flex items have been created on the port. */ 1539 uint32_t flex_item_map; /* Map of allocated flex item elements. */ 1540 #if defined(HAVE_IBV_FLOW_DV_SUPPORT) || !defined(HAVE_INFINIBAND_VERBS_H) 1541 /* Item template list. */ 1542 LIST_HEAD(flow_hw_itt, rte_flow_pattern_template) flow_hw_itt; 1543 /* Action template list. */ 1544 LIST_HEAD(flow_hw_at, rte_flow_actions_template) flow_hw_at; 1545 struct mlx5dr_context *dr_ctx; /**< HW steering DR context. */ 1546 uint32_t nb_queue; /* HW steering queue number. */ 1547 /* HW steering queue polling mechanism job descriptor LIFO. */ 1548 struct mlx5_hw_q *hw_q; 1549 /* HW steering rte flow table list header. */ 1550 LIST_HEAD(flow_hw_tbl, rte_flow_template_table) flow_hw_tbl; 1551 /* HW steering global drop action. */ 1552 struct mlx5dr_action *hw_drop[MLX5_HW_ACTION_FLAG_MAX] 1553 [MLX5DR_TABLE_TYPE_MAX]; 1554 /* HW steering global drop action. */ 1555 struct mlx5dr_action *hw_tag[MLX5_HW_ACTION_FLAG_MAX]; 1556 struct mlx5_indexed_pool *acts_ipool; /* Action data indexed pool. */ 1557 #endif 1558 }; 1559 1560 #define PORT_ID(priv) ((priv)->dev_data->port_id) 1561 #define ETH_DEV(priv) (&rte_eth_devices[PORT_ID(priv)]) 1562 1563 struct rte_hairpin_peer_info { 1564 uint32_t qp_id; 1565 uint32_t vhca_id; 1566 uint16_t peer_q; 1567 uint16_t tx_explicit; 1568 uint16_t manual_bind; 1569 }; 1570 1571 #define BUF_SIZE 1024 1572 enum dr_dump_rec_type { 1573 DR_DUMP_REC_TYPE_PMD_PKT_REFORMAT = 4410, 1574 DR_DUMP_REC_TYPE_PMD_MODIFY_HDR = 4420, 1575 DR_DUMP_REC_TYPE_PMD_COUNTER = 4430, 1576 }; 1577 1578 /** 1579 * Indicates whether HW objects operations can be created by DevX. 1580 * 1581 * This function is used for both: 1582 * Before creation - deciding whether to create HW objects operations by DevX. 1583 * After creation - indicator if HW objects operations were created by DevX. 1584 * 1585 * @param sh 1586 * Pointer to shared device context. 1587 * 1588 * @return 1589 * True if HW objects were created by DevX, False otherwise. 1590 */ 1591 static inline bool 1592 mlx5_devx_obj_ops_en(struct mlx5_dev_ctx_shared *sh) 1593 { 1594 /* 1595 * When advanced DR API is available and DV flow is supported and 1596 * DevX is supported, HW objects operations are created by DevX. 1597 */ 1598 return (sh->cdev->config.devx && sh->config.dv_flow_en && 1599 sh->dev_cap.dest_tir); 1600 } 1601 1602 /* mlx5.c */ 1603 1604 int mlx5_getenv_int(const char *); 1605 int mlx5_proc_priv_init(struct rte_eth_dev *dev); 1606 void mlx5_proc_priv_uninit(struct rte_eth_dev *dev); 1607 int mlx5_udp_tunnel_port_add(struct rte_eth_dev *dev, 1608 struct rte_eth_udp_tunnel *udp_tunnel); 1609 uint16_t mlx5_eth_find_next(uint16_t port_id, struct rte_device *odev); 1610 int mlx5_dev_close(struct rte_eth_dev *dev); 1611 int mlx5_net_remove(struct mlx5_common_device *cdev); 1612 bool mlx5_is_hpf(struct rte_eth_dev *dev); 1613 bool mlx5_is_sf_repr(struct rte_eth_dev *dev); 1614 void mlx5_age_event_prepare(struct mlx5_dev_ctx_shared *sh); 1615 int mlx5_lwm_setup(struct mlx5_priv *priv); 1616 void mlx5_lwm_unset(struct mlx5_dev_ctx_shared *sh); 1617 1618 /* Macro to iterate over all valid ports for mlx5 driver. */ 1619 #define MLX5_ETH_FOREACH_DEV(port_id, dev) \ 1620 for (port_id = mlx5_eth_find_next(0, dev); \ 1621 port_id < RTE_MAX_ETHPORTS; \ 1622 port_id = mlx5_eth_find_next(port_id + 1, dev)) 1623 void mlx5_rt_timestamp_config(struct mlx5_dev_ctx_shared *sh, 1624 struct mlx5_hca_attr *hca_attr); 1625 struct mlx5_dev_ctx_shared * 1626 mlx5_alloc_shared_dev_ctx(const struct mlx5_dev_spawn_data *spawn, 1627 struct mlx5_kvargs_ctrl *mkvlist); 1628 void mlx5_free_shared_dev_ctx(struct mlx5_dev_ctx_shared *sh); 1629 int mlx5_dev_ctx_shared_mempool_subscribe(struct rte_eth_dev *dev); 1630 void mlx5_free_table_hash_list(struct mlx5_priv *priv); 1631 int mlx5_alloc_table_hash_list(struct mlx5_priv *priv); 1632 void mlx5_set_min_inline(struct mlx5_priv *priv); 1633 void mlx5_set_metadata_mask(struct rte_eth_dev *dev); 1634 int mlx5_probe_again_args_validate(struct mlx5_common_device *cdev, 1635 struct mlx5_kvargs_ctrl *mkvlist); 1636 int mlx5_port_args_config(struct mlx5_priv *priv, 1637 struct mlx5_kvargs_ctrl *mkvlist, 1638 struct mlx5_port_config *config); 1639 void mlx5_port_args_set_used(const char *name, uint16_t port_id, 1640 struct mlx5_kvargs_ctrl *mkvlist); 1641 bool mlx5_flex_parser_ecpri_exist(struct rte_eth_dev *dev); 1642 int mlx5_flex_parser_ecpri_alloc(struct rte_eth_dev *dev); 1643 void mlx5_flow_counter_mode_config(struct rte_eth_dev *dev); 1644 int mlx5_flow_aso_age_mng_init(struct mlx5_dev_ctx_shared *sh); 1645 int mlx5_aso_flow_mtrs_mng_init(struct mlx5_dev_ctx_shared *sh); 1646 int mlx5_flow_aso_ct_mng_init(struct mlx5_dev_ctx_shared *sh); 1647 1648 /* mlx5_ethdev.c */ 1649 1650 int mlx5_dev_configure(struct rte_eth_dev *dev); 1651 int mlx5_representor_info_get(struct rte_eth_dev *dev, 1652 struct rte_eth_representor_info *info); 1653 #define MLX5_REPRESENTOR_ID(pf, type, repr) \ 1654 (((pf) << 14) + ((type) << 12) + ((repr) & 0xfff)) 1655 #define MLX5_REPRESENTOR_REPR(repr_id) \ 1656 ((repr_id) & 0xfff) 1657 #define MLX5_REPRESENTOR_TYPE(repr_id) \ 1658 (((repr_id) >> 12) & 3) 1659 uint16_t mlx5_representor_id_encode(const struct mlx5_switch_info *info, 1660 enum rte_eth_representor_type hpf_type); 1661 int mlx5_dev_infos_get(struct rte_eth_dev *dev, struct rte_eth_dev_info *info); 1662 int mlx5_fw_version_get(struct rte_eth_dev *dev, char *fw_ver, size_t fw_size); 1663 const uint32_t *mlx5_dev_supported_ptypes_get(struct rte_eth_dev *dev); 1664 int mlx5_dev_set_mtu(struct rte_eth_dev *dev, uint16_t mtu); 1665 int mlx5_hairpin_cap_get(struct rte_eth_dev *dev, 1666 struct rte_eth_hairpin_cap *cap); 1667 eth_rx_burst_t mlx5_select_rx_function(struct rte_eth_dev *dev); 1668 struct mlx5_priv *mlx5_port_to_eswitch_info(uint16_t port, bool valid); 1669 struct mlx5_priv *mlx5_dev_to_eswitch_info(struct rte_eth_dev *dev); 1670 int mlx5_dev_configure_rss_reta(struct rte_eth_dev *dev); 1671 1672 /* mlx5_ethdev_os.c */ 1673 1674 int mlx5_get_ifname(const struct rte_eth_dev *dev, 1675 char (*ifname)[MLX5_NAMESIZE]); 1676 unsigned int mlx5_ifindex(const struct rte_eth_dev *dev); 1677 int mlx5_get_mac(struct rte_eth_dev *dev, uint8_t (*mac)[RTE_ETHER_ADDR_LEN]); 1678 int mlx5_get_mtu(struct rte_eth_dev *dev, uint16_t *mtu); 1679 int mlx5_set_mtu(struct rte_eth_dev *dev, uint16_t mtu); 1680 int mlx5_read_clock(struct rte_eth_dev *dev, uint64_t *clock); 1681 int mlx5_link_update(struct rte_eth_dev *dev, int wait_to_complete); 1682 int mlx5_dev_get_flow_ctrl(struct rte_eth_dev *dev, 1683 struct rte_eth_fc_conf *fc_conf); 1684 int mlx5_dev_set_flow_ctrl(struct rte_eth_dev *dev, 1685 struct rte_eth_fc_conf *fc_conf); 1686 void mlx5_dev_interrupt_handler(void *arg); 1687 void mlx5_dev_interrupt_handler_devx(void *arg); 1688 void mlx5_dev_interrupt_handler_nl(void *arg); 1689 int mlx5_set_link_down(struct rte_eth_dev *dev); 1690 int mlx5_set_link_up(struct rte_eth_dev *dev); 1691 int mlx5_is_removed(struct rte_eth_dev *dev); 1692 int mlx5_sysfs_switch_info(unsigned int ifindex, 1693 struct mlx5_switch_info *info); 1694 void mlx5_translate_port_name(const char *port_name_in, 1695 struct mlx5_switch_info *port_info_out); 1696 int mlx5_sysfs_bond_info(unsigned int pf_ifindex, unsigned int *ifindex, 1697 char *ifname); 1698 int mlx5_get_module_info(struct rte_eth_dev *dev, 1699 struct rte_eth_dev_module_info *modinfo); 1700 int mlx5_get_module_eeprom(struct rte_eth_dev *dev, 1701 struct rte_dev_eeprom_info *info); 1702 int mlx5_os_read_dev_stat(struct mlx5_priv *priv, 1703 const char *ctr_name, uint64_t *stat); 1704 int mlx5_os_read_dev_counters(struct rte_eth_dev *dev, uint64_t *stats); 1705 int mlx5_os_get_stats_n(struct rte_eth_dev *dev); 1706 void mlx5_os_stats_init(struct rte_eth_dev *dev); 1707 int mlx5_get_flag_dropless_rq(struct rte_eth_dev *dev); 1708 1709 /* mlx5_mac.c */ 1710 1711 void mlx5_mac_addr_remove(struct rte_eth_dev *dev, uint32_t index); 1712 int mlx5_mac_addr_add(struct rte_eth_dev *dev, struct rte_ether_addr *mac, 1713 uint32_t index, uint32_t vmdq); 1714 int mlx5_mac_addr_set(struct rte_eth_dev *dev, struct rte_ether_addr *mac_addr); 1715 int mlx5_set_mc_addr_list(struct rte_eth_dev *dev, 1716 struct rte_ether_addr *mc_addr_set, 1717 uint32_t nb_mc_addr); 1718 1719 /* mlx5_rss.c */ 1720 1721 int mlx5_rss_hash_update(struct rte_eth_dev *dev, 1722 struct rte_eth_rss_conf *rss_conf); 1723 int mlx5_rss_hash_conf_get(struct rte_eth_dev *dev, 1724 struct rte_eth_rss_conf *rss_conf); 1725 int mlx5_rss_reta_index_resize(struct rte_eth_dev *dev, unsigned int reta_size); 1726 int mlx5_dev_rss_reta_query(struct rte_eth_dev *dev, 1727 struct rte_eth_rss_reta_entry64 *reta_conf, 1728 uint16_t reta_size); 1729 int mlx5_dev_rss_reta_update(struct rte_eth_dev *dev, 1730 struct rte_eth_rss_reta_entry64 *reta_conf, 1731 uint16_t reta_size); 1732 1733 /* mlx5_rxmode.c */ 1734 1735 int mlx5_promiscuous_enable(struct rte_eth_dev *dev); 1736 int mlx5_promiscuous_disable(struct rte_eth_dev *dev); 1737 int mlx5_allmulticast_enable(struct rte_eth_dev *dev); 1738 int mlx5_allmulticast_disable(struct rte_eth_dev *dev); 1739 1740 /* mlx5_stats.c */ 1741 1742 int mlx5_stats_get(struct rte_eth_dev *dev, struct rte_eth_stats *stats); 1743 int mlx5_stats_reset(struct rte_eth_dev *dev); 1744 int mlx5_xstats_get(struct rte_eth_dev *dev, struct rte_eth_xstat *stats, 1745 unsigned int n); 1746 int mlx5_xstats_reset(struct rte_eth_dev *dev); 1747 int mlx5_xstats_get_names(struct rte_eth_dev *dev __rte_unused, 1748 struct rte_eth_xstat_name *xstats_names, 1749 unsigned int n); 1750 1751 /* mlx5_vlan.c */ 1752 1753 int mlx5_vlan_filter_set(struct rte_eth_dev *dev, uint16_t vlan_id, int on); 1754 void mlx5_vlan_strip_queue_set(struct rte_eth_dev *dev, uint16_t queue, int on); 1755 int mlx5_vlan_offload_set(struct rte_eth_dev *dev, int mask); 1756 1757 /* mlx5_vlan_os.c */ 1758 1759 void mlx5_vlan_vmwa_exit(void *ctx); 1760 void mlx5_vlan_vmwa_release(struct rte_eth_dev *dev, 1761 struct mlx5_vf_vlan *vf_vlan); 1762 void mlx5_vlan_vmwa_acquire(struct rte_eth_dev *dev, 1763 struct mlx5_vf_vlan *vf_vlan); 1764 void *mlx5_vlan_vmwa_init(struct rte_eth_dev *dev, uint32_t ifindex); 1765 1766 /* mlx5_trigger.c */ 1767 1768 int mlx5_dev_start(struct rte_eth_dev *dev); 1769 int mlx5_dev_stop(struct rte_eth_dev *dev); 1770 int mlx5_traffic_enable(struct rte_eth_dev *dev); 1771 void mlx5_traffic_disable(struct rte_eth_dev *dev); 1772 int mlx5_traffic_restart(struct rte_eth_dev *dev); 1773 int mlx5_hairpin_queue_peer_update(struct rte_eth_dev *dev, uint16_t peer_queue, 1774 struct rte_hairpin_peer_info *current_info, 1775 struct rte_hairpin_peer_info *peer_info, 1776 uint32_t direction); 1777 int mlx5_hairpin_queue_peer_bind(struct rte_eth_dev *dev, uint16_t cur_queue, 1778 struct rte_hairpin_peer_info *peer_info, 1779 uint32_t direction); 1780 int mlx5_hairpin_queue_peer_unbind(struct rte_eth_dev *dev, uint16_t cur_queue, 1781 uint32_t direction); 1782 int mlx5_hairpin_bind(struct rte_eth_dev *dev, uint16_t rx_port); 1783 int mlx5_hairpin_unbind(struct rte_eth_dev *dev, uint16_t rx_port); 1784 int mlx5_hairpin_get_peer_ports(struct rte_eth_dev *dev, uint16_t *peer_ports, 1785 size_t len, uint32_t direction); 1786 1787 /* mlx5_flow.c */ 1788 1789 int mlx5_flow_discover_mreg_c(struct rte_eth_dev *eth_dev); 1790 bool mlx5_flow_ext_mreg_supported(struct rte_eth_dev *dev); 1791 void mlx5_flow_print(struct rte_flow *flow); 1792 int mlx5_flow_validate(struct rte_eth_dev *dev, 1793 const struct rte_flow_attr *attr, 1794 const struct rte_flow_item items[], 1795 const struct rte_flow_action actions[], 1796 struct rte_flow_error *error); 1797 struct rte_flow *mlx5_flow_create(struct rte_eth_dev *dev, 1798 const struct rte_flow_attr *attr, 1799 const struct rte_flow_item items[], 1800 const struct rte_flow_action actions[], 1801 struct rte_flow_error *error); 1802 int mlx5_flow_destroy(struct rte_eth_dev *dev, struct rte_flow *flow, 1803 struct rte_flow_error *error); 1804 void mlx5_flow_list_flush(struct rte_eth_dev *dev, enum mlx5_flow_type type, 1805 bool active); 1806 int mlx5_flow_flush(struct rte_eth_dev *dev, struct rte_flow_error *error); 1807 int mlx5_flow_query(struct rte_eth_dev *dev, struct rte_flow *flow, 1808 const struct rte_flow_action *action, void *data, 1809 struct rte_flow_error *error); 1810 int mlx5_flow_isolate(struct rte_eth_dev *dev, int enable, 1811 struct rte_flow_error *error); 1812 int mlx5_flow_ops_get(struct rte_eth_dev *dev, const struct rte_flow_ops **ops); 1813 int mlx5_flow_start_default(struct rte_eth_dev *dev); 1814 void mlx5_flow_stop_default(struct rte_eth_dev *dev); 1815 int mlx5_flow_verify(struct rte_eth_dev *dev); 1816 int mlx5_ctrl_flow_source_queue(struct rte_eth_dev *dev, uint32_t queue); 1817 int mlx5_ctrl_flow_vlan(struct rte_eth_dev *dev, 1818 struct rte_flow_item_eth *eth_spec, 1819 struct rte_flow_item_eth *eth_mask, 1820 struct rte_flow_item_vlan *vlan_spec, 1821 struct rte_flow_item_vlan *vlan_mask); 1822 int mlx5_ctrl_flow(struct rte_eth_dev *dev, 1823 struct rte_flow_item_eth *eth_spec, 1824 struct rte_flow_item_eth *eth_mask); 1825 int mlx5_flow_lacp_miss(struct rte_eth_dev *dev); 1826 struct rte_flow *mlx5_flow_create_esw_table_zero_flow(struct rte_eth_dev *dev); 1827 uint32_t mlx5_flow_create_devx_sq_miss_flow(struct rte_eth_dev *dev, 1828 uint32_t txq); 1829 void mlx5_flow_async_pool_query_handle(struct mlx5_dev_ctx_shared *sh, 1830 uint64_t async_id, int status); 1831 void mlx5_set_query_alarm(struct mlx5_dev_ctx_shared *sh); 1832 void mlx5_flow_query_alarm(void *arg); 1833 uint32_t mlx5_counter_alloc(struct rte_eth_dev *dev); 1834 void mlx5_counter_free(struct rte_eth_dev *dev, uint32_t cnt); 1835 int mlx5_counter_query(struct rte_eth_dev *dev, uint32_t cnt, 1836 bool clear, uint64_t *pkts, uint64_t *bytes, void **action); 1837 int mlx5_flow_dev_dump(struct rte_eth_dev *dev, struct rte_flow *flow, 1838 FILE *file, struct rte_flow_error *error); 1839 int save_dump_file(const unsigned char *data, uint32_t size, 1840 uint32_t type, uint64_t id, void *arg, FILE *file); 1841 int mlx5_flow_query_counter(struct rte_eth_dev *dev, struct rte_flow *flow, 1842 struct rte_flow_query_count *count, struct rte_flow_error *error); 1843 #ifdef HAVE_IBV_FLOW_DV_SUPPORT 1844 int mlx5_flow_dev_dump_ipool(struct rte_eth_dev *dev, struct rte_flow *flow, 1845 FILE *file, struct rte_flow_error *error); 1846 #endif 1847 void mlx5_flow_rxq_dynf_metadata_set(struct rte_eth_dev *dev); 1848 int mlx5_flow_get_aged_flows(struct rte_eth_dev *dev, void **contexts, 1849 uint32_t nb_contexts, struct rte_flow_error *error); 1850 int mlx5_validate_action_ct(struct rte_eth_dev *dev, 1851 const struct rte_flow_action_conntrack *conntrack, 1852 struct rte_flow_error *error); 1853 1854 1855 /* mlx5_mp_os.c */ 1856 1857 int mlx5_mp_os_primary_handle(const struct rte_mp_msg *mp_msg, 1858 const void *peer); 1859 int mlx5_mp_os_secondary_handle(const struct rte_mp_msg *mp_msg, 1860 const void *peer); 1861 void mlx5_mp_os_req_start_rxtx(struct rte_eth_dev *dev); 1862 void mlx5_mp_os_req_stop_rxtx(struct rte_eth_dev *dev); 1863 int mlx5_mp_os_req_queue_control(struct rte_eth_dev *dev, uint16_t queue_id, 1864 enum mlx5_mp_req_type req_type); 1865 1866 /* mlx5_socket.c */ 1867 1868 int mlx5_pmd_socket_init(void); 1869 void mlx5_pmd_socket_uninit(void); 1870 1871 /* mlx5_flow_meter.c */ 1872 1873 int mlx5_flow_meter_ops_get(struct rte_eth_dev *dev, void *arg); 1874 struct mlx5_flow_meter_info *mlx5_flow_meter_find(struct mlx5_priv *priv, 1875 uint32_t meter_id, uint32_t *mtr_idx); 1876 struct mlx5_flow_meter_info * 1877 flow_dv_meter_find_by_idx(struct mlx5_priv *priv, uint32_t idx); 1878 int mlx5_flow_meter_attach(struct mlx5_priv *priv, 1879 struct mlx5_flow_meter_info *fm, 1880 const struct rte_flow_attr *attr, 1881 struct rte_flow_error *error); 1882 void mlx5_flow_meter_detach(struct mlx5_priv *priv, 1883 struct mlx5_flow_meter_info *fm); 1884 struct mlx5_flow_meter_policy *mlx5_flow_meter_policy_find 1885 (struct rte_eth_dev *dev, 1886 uint32_t policy_id, 1887 uint32_t *policy_idx); 1888 struct mlx5_flow_meter_info * 1889 mlx5_flow_meter_hierarchy_next_meter(struct mlx5_priv *priv, 1890 struct mlx5_flow_meter_policy *policy, 1891 uint32_t *mtr_idx); 1892 struct mlx5_flow_meter_policy * 1893 mlx5_flow_meter_hierarchy_get_final_policy(struct rte_eth_dev *dev, 1894 struct mlx5_flow_meter_policy *policy); 1895 int mlx5_flow_meter_flush(struct rte_eth_dev *dev, 1896 struct rte_mtr_error *error); 1897 void mlx5_flow_meter_rxq_flush(struct rte_eth_dev *dev); 1898 1899 /* mlx5_os.c */ 1900 1901 struct rte_pci_driver; 1902 int mlx5_os_capabilities_prepare(struct mlx5_dev_ctx_shared *sh); 1903 void mlx5_os_free_shared_dr(struct mlx5_priv *priv); 1904 int mlx5_os_net_probe(struct mlx5_common_device *cdev, 1905 struct mlx5_kvargs_ctrl *mkvlist); 1906 void mlx5_os_dev_shared_handler_install(struct mlx5_dev_ctx_shared *sh); 1907 void mlx5_os_dev_shared_handler_uninstall(struct mlx5_dev_ctx_shared *sh); 1908 void mlx5_os_mac_addr_remove(struct rte_eth_dev *dev, uint32_t index); 1909 int mlx5_os_mac_addr_add(struct rte_eth_dev *dev, struct rte_ether_addr *mac, 1910 uint32_t index); 1911 int mlx5_os_vf_mac_addr_modify(struct mlx5_priv *priv, unsigned int iface_idx, 1912 struct rte_ether_addr *mac_addr, 1913 int vf_index); 1914 int mlx5_os_set_promisc(struct rte_eth_dev *dev, int enable); 1915 int mlx5_os_set_allmulti(struct rte_eth_dev *dev, int enable); 1916 int mlx5_os_set_nonblock_channel_fd(int fd); 1917 void mlx5_os_mac_addr_flush(struct rte_eth_dev *dev); 1918 void mlx5_os_net_cleanup(void); 1919 1920 /* mlx5_txpp.c */ 1921 1922 int mlx5_txpp_start(struct rte_eth_dev *dev); 1923 void mlx5_txpp_stop(struct rte_eth_dev *dev); 1924 int mlx5_txpp_read_clock(struct rte_eth_dev *dev, uint64_t *timestamp); 1925 int mlx5_txpp_xstats_get(struct rte_eth_dev *dev, 1926 struct rte_eth_xstat *stats, 1927 unsigned int n, unsigned int n_used); 1928 int mlx5_txpp_xstats_reset(struct rte_eth_dev *dev); 1929 int mlx5_txpp_xstats_get_names(struct rte_eth_dev *dev, 1930 struct rte_eth_xstat_name *xstats_names, 1931 unsigned int n, unsigned int n_used); 1932 void mlx5_txpp_interrupt_handler(void *cb_arg); 1933 1934 /* mlx5_rxtx.c */ 1935 1936 eth_tx_burst_t mlx5_select_tx_function(struct rte_eth_dev *dev); 1937 1938 /* mlx5_flow_aso.c */ 1939 1940 int mlx5_aso_queue_init(struct mlx5_dev_ctx_shared *sh, 1941 enum mlx5_access_aso_opc_mod aso_opc_mod); 1942 int mlx5_aso_flow_hit_queue_poll_start(struct mlx5_dev_ctx_shared *sh); 1943 int mlx5_aso_flow_hit_queue_poll_stop(struct mlx5_dev_ctx_shared *sh); 1944 void mlx5_aso_queue_uninit(struct mlx5_dev_ctx_shared *sh, 1945 enum mlx5_access_aso_opc_mod aso_opc_mod); 1946 int mlx5_aso_meter_update_by_wqe(struct mlx5_dev_ctx_shared *sh, 1947 struct mlx5_aso_mtr *mtr); 1948 int mlx5_aso_mtr_wait(struct mlx5_dev_ctx_shared *sh, 1949 struct mlx5_aso_mtr *mtr); 1950 int mlx5_aso_ct_update_by_wqe(struct mlx5_dev_ctx_shared *sh, 1951 struct mlx5_aso_ct_action *ct, 1952 const struct rte_flow_action_conntrack *profile); 1953 int mlx5_aso_ct_wait_ready(struct mlx5_dev_ctx_shared *sh, 1954 struct mlx5_aso_ct_action *ct); 1955 int mlx5_aso_ct_query_by_wqe(struct mlx5_dev_ctx_shared *sh, 1956 struct mlx5_aso_ct_action *ct, 1957 struct rte_flow_action_conntrack *profile); 1958 int mlx5_aso_ct_available(struct mlx5_dev_ctx_shared *sh, 1959 struct mlx5_aso_ct_action *ct); 1960 uint32_t 1961 mlx5_get_supported_sw_parsing_offloads(const struct mlx5_hca_attr *attr); 1962 uint32_t 1963 mlx5_get_supported_tunneling_offloads(const struct mlx5_hca_attr *attr); 1964 1965 /* mlx5_flow_flex.c */ 1966 1967 struct rte_flow_item_flex_handle * 1968 flow_dv_item_create(struct rte_eth_dev *dev, 1969 const struct rte_flow_item_flex_conf *conf, 1970 struct rte_flow_error *error); 1971 int flow_dv_item_release(struct rte_eth_dev *dev, 1972 const struct rte_flow_item_flex_handle *flex_handle, 1973 struct rte_flow_error *error); 1974 int mlx5_flex_item_port_init(struct rte_eth_dev *dev); 1975 void mlx5_flex_item_port_cleanup(struct rte_eth_dev *dev); 1976 void mlx5_flex_flow_translate_item(struct rte_eth_dev *dev, void *matcher, 1977 void *key, const struct rte_flow_item *item, 1978 bool is_inner); 1979 int mlx5_flex_acquire_index(struct rte_eth_dev *dev, 1980 struct rte_flow_item_flex_handle *handle, 1981 bool acquire); 1982 int mlx5_flex_release_index(struct rte_eth_dev *dev, int index); 1983 1984 /* Flex parser list callbacks. */ 1985 struct mlx5_list_entry *mlx5_flex_parser_create_cb(void *list_ctx, void *ctx); 1986 int mlx5_flex_parser_match_cb(void *list_ctx, 1987 struct mlx5_list_entry *iter, void *ctx); 1988 void mlx5_flex_parser_remove_cb(void *list_ctx, struct mlx5_list_entry *entry); 1989 struct mlx5_list_entry *mlx5_flex_parser_clone_cb(void *list_ctx, 1990 struct mlx5_list_entry *entry, 1991 void *ctx); 1992 void mlx5_flex_parser_clone_free_cb(void *tool_ctx, 1993 struct mlx5_list_entry *entry); 1994 #endif /* RTE_PMD_MLX5_H_ */ 1995