1 /* SPDX-License-Identifier: BSD-3-Clause 2 * Copyright 2015 6WIND S.A. 3 * Copyright 2015 Mellanox Technologies, Ltd 4 */ 5 6 #ifndef RTE_PMD_MLX5_H_ 7 #define RTE_PMD_MLX5_H_ 8 9 #include <stddef.h> 10 #include <stdbool.h> 11 #include <stdint.h> 12 #include <limits.h> 13 #include <sys/queue.h> 14 15 #include <rte_pci.h> 16 #include <rte_ether.h> 17 #include <ethdev_driver.h> 18 #include <rte_rwlock.h> 19 #include <rte_interrupts.h> 20 #include <rte_errno.h> 21 #include <rte_flow.h> 22 #include <rte_mtr.h> 23 24 #include <mlx5_glue.h> 25 #include <mlx5_devx_cmds.h> 26 #include <mlx5_prm.h> 27 #include <mlx5_common_mp.h> 28 #include <mlx5_common_mr.h> 29 #include <mlx5_common_devx.h> 30 #include <mlx5_common_defs.h> 31 32 #include "mlx5_defs.h" 33 #include "mlx5_utils.h" 34 #include "mlx5_os.h" 35 #include "mlx5_autoconf.h" 36 #if defined(HAVE_IBV_FLOW_DV_SUPPORT) || !defined(HAVE_INFINIBAND_VERBS_H) 37 #ifndef RTE_EXEC_ENV_WINDOWS 38 #define HAVE_MLX5_HWS_SUPPORT 1 39 #else 40 #define __be64 uint64_t 41 #endif 42 #include "hws/mlx5dr.h" 43 #endif 44 45 #define MLX5_SH(dev) (((struct mlx5_priv *)(dev)->data->dev_private)->sh) 46 47 #define MLX5_HW_INV_QUEUE UINT32_MAX 48 49 /* 50 * Number of modification commands. 51 * The maximal actions amount in FW is some constant, and it is 16 in the 52 * latest releases. In some old releases, it will be limited to 8. 53 * Since there is no interface to query the capacity, the maximal value should 54 * be used to allow PMD to create the flow. The validation will be done in the 55 * lower driver layer or FW. A failure will be returned if exceeds the maximal 56 * supported actions number on the root table. 57 * On non-root tables, there is no limitation, but 32 is enough right now. 58 */ 59 #define MLX5_MAX_MODIFY_NUM 32 60 #define MLX5_ROOT_TBL_MODIFY_NUM 16 61 62 /* Maximal number of flex items created on the port.*/ 63 #define MLX5_PORT_FLEX_ITEM_NUM 4 64 65 /* Maximal number of field/field parts to map into sample registers .*/ 66 #define MLX5_FLEX_ITEM_MAPPING_NUM 32 67 68 enum mlx5_ipool_index { 69 #if defined(HAVE_IBV_FLOW_DV_SUPPORT) || !defined(HAVE_INFINIBAND_VERBS_H) 70 MLX5_IPOOL_DECAP_ENCAP = 0, /* Pool for encap/decap resource. */ 71 MLX5_IPOOL_PUSH_VLAN, /* Pool for push vlan resource. */ 72 MLX5_IPOOL_TAG, /* Pool for tag resource. */ 73 MLX5_IPOOL_PORT_ID, /* Pool for port id resource. */ 74 MLX5_IPOOL_JUMP, /* Pool for SWS jump resource. */ 75 /* Pool for HWS group. Jump action will be created internally. */ 76 MLX5_IPOOL_HW_GRP = MLX5_IPOOL_JUMP, 77 MLX5_IPOOL_SAMPLE, /* Pool for sample resource. */ 78 MLX5_IPOOL_DEST_ARRAY, /* Pool for destination array resource. */ 79 MLX5_IPOOL_TUNNEL_ID, /* Pool for tunnel offload context */ 80 MLX5_IPOOL_TNL_TBL_ID, /* Pool for tunnel table ID. */ 81 #endif 82 MLX5_IPOOL_MTR, /* Pool for meter resource. */ 83 MLX5_IPOOL_MCP, /* Pool for metadata resource. */ 84 MLX5_IPOOL_HRXQ, /* Pool for hrxq resource. */ 85 MLX5_IPOOL_MLX5_FLOW, /* Pool for mlx5 flow handle. */ 86 MLX5_IPOOL_RTE_FLOW, /* Pool for rte_flow. */ 87 MLX5_IPOOL_RSS_EXPANTION_FLOW_ID, /* Pool for Queue/RSS flow ID. */ 88 MLX5_IPOOL_RSS_SHARED_ACTIONS, /* Pool for RSS shared actions. */ 89 MLX5_IPOOL_MTR_POLICY, /* Pool for meter policy resource. */ 90 MLX5_IPOOL_MAX, 91 }; 92 93 /* 94 * There are three reclaim memory mode supported. 95 * 0(none) means no memory reclaim. 96 * 1(light) means only PMD level reclaim. 97 * 2(aggressive) means both PMD and rdma-core level reclaim. 98 */ 99 enum mlx5_reclaim_mem_mode { 100 MLX5_RCM_NONE, /* Don't reclaim memory. */ 101 MLX5_RCM_LIGHT, /* Reclaim PMD level. */ 102 MLX5_RCM_AGGR, /* Reclaim PMD and rdma-core level. */ 103 }; 104 105 /* The type of flow. */ 106 enum mlx5_flow_type { 107 MLX5_FLOW_TYPE_CTL, /* Control flow. */ 108 MLX5_FLOW_TYPE_GEN, /* General flow. */ 109 MLX5_FLOW_TYPE_MCP, /* MCP flow. */ 110 MLX5_FLOW_TYPE_MAXI, 111 }; 112 113 /* The mode of delay drop for Rx queues. */ 114 enum mlx5_delay_drop_mode { 115 MLX5_DELAY_DROP_NONE = 0, /* All disabled. */ 116 MLX5_DELAY_DROP_STANDARD = RTE_BIT32(0), /* Standard queues enable. */ 117 MLX5_DELAY_DROP_HAIRPIN = RTE_BIT32(1), /* Hairpin queues enable. */ 118 }; 119 120 /* The HWS action type root/non-root. */ 121 enum mlx5_hw_action_flag_type { 122 MLX5_HW_ACTION_FLAG_ROOT, /* Root action. */ 123 MLX5_HW_ACTION_FLAG_NONE_ROOT, /* Non-root ation. */ 124 MLX5_HW_ACTION_FLAG_MAX, /* Maximum action flag. */ 125 }; 126 127 /* Hlist and list callback context. */ 128 struct mlx5_flow_cb_ctx { 129 struct rte_eth_dev *dev; 130 struct rte_flow_error *error; 131 void *data; 132 void *data2; 133 }; 134 135 /* Device capabilities structure which isn't changed in any stage. */ 136 struct mlx5_dev_cap { 137 int max_cq; /* Maximum number of supported CQs */ 138 int max_qp; /* Maximum number of supported QPs. */ 139 int max_qp_wr; /* Maximum number of outstanding WR on any WQ. */ 140 int max_sge; 141 /* Maximum number of s/g per WR for SQ & RQ of QP for non RDMA Read 142 * operations. 143 */ 144 int mps; /* Multi-packet send supported mode. */ 145 uint32_t vf:1; /* This is a VF. */ 146 uint32_t sf:1; /* This is a SF. */ 147 uint32_t txpp_en:1; /* Tx packet pacing is supported. */ 148 uint32_t mpls_en:1; /* MPLS over GRE/UDP is supported. */ 149 uint32_t cqe_comp:1; /* CQE compression is supported. */ 150 uint32_t hw_csum:1; /* Checksum offload is supported. */ 151 uint32_t hw_padding:1; /* End alignment padding is supported. */ 152 uint32_t dest_tir:1; /* Whether advanced DR API is available. */ 153 uint32_t dv_esw_en:1; /* E-Switch DV flow is supported. */ 154 uint32_t dv_flow_en:1; /* DV flow is supported. */ 155 uint32_t swp:3; /* Tx generic tunnel checksum and TSO offload. */ 156 uint32_t hw_vlan_strip:1; /* VLAN stripping is supported. */ 157 uint32_t scatter_fcs_w_decap_disable:1; 158 /* HW has bug working with tunnel packet decap and scatter FCS. */ 159 uint32_t hw_fcs_strip:1; /* FCS stripping is supported. */ 160 uint32_t rt_timestamp:1; /* Realtime timestamp format. */ 161 uint32_t rq_delay_drop_en:1; /* Enable RxQ delay drop. */ 162 uint32_t tunnel_en:3; 163 /* Whether tunnel stateless offloads are supported. */ 164 uint32_t ind_table_max_size; 165 /* Maximum receive WQ indirection table size. */ 166 uint32_t tso:1; /* Whether TSO is supported. */ 167 uint32_t tso_max_payload_sz; /* Maximum TCP payload for TSO. */ 168 struct { 169 uint32_t enabled:1; /* Whether MPRQ is enabled. */ 170 uint32_t log_min_stride_size; /* Log min size of a stride. */ 171 uint32_t log_max_stride_size; /* Log max size of a stride. */ 172 uint32_t log_min_stride_num; /* Log min num of strides. */ 173 uint32_t log_max_stride_num; /* Log max num of strides. */ 174 uint32_t log_min_stride_wqe_size; 175 /* Log min WQE size, (size of single stride)*(num of strides).*/ 176 } mprq; /* Capability for Multi-Packet RQ. */ 177 char fw_ver[64]; /* Firmware version of this device. */ 178 }; 179 180 /** Data associated with devices to spawn. */ 181 struct mlx5_dev_spawn_data { 182 uint32_t ifindex; /**< Network interface index. */ 183 uint32_t max_port; /**< Device maximal port index. */ 184 uint32_t phys_port; /**< Device physical port index. */ 185 int pf_bond; /**< bonding device PF index. < 0 - no bonding */ 186 struct mlx5_switch_info info; /**< Switch information. */ 187 const char *phys_dev_name; /**< Name of physical device. */ 188 struct rte_eth_dev *eth_dev; /**< Associated Ethernet device. */ 189 struct rte_pci_device *pci_dev; /**< Backend PCI device. */ 190 struct mlx5_common_device *cdev; /**< Backend common device. */ 191 struct mlx5_bond_info *bond_info; 192 }; 193 194 /** Data associated with socket messages. */ 195 struct mlx5_flow_dump_req { 196 uint32_t port_id; /**< There are plans in DPDK to extend port_id. */ 197 uint64_t flow_id; 198 } __rte_packed; 199 200 struct mlx5_flow_dump_ack { 201 int rc; /**< Return code. */ 202 }; 203 204 LIST_HEAD(mlx5_dev_list, mlx5_dev_ctx_shared); 205 206 /* Shared data between primary and secondary processes. */ 207 struct mlx5_shared_data { 208 rte_spinlock_t lock; 209 /* Global spinlock for primary and secondary processes. */ 210 int init_done; /* Whether primary has done initialization. */ 211 unsigned int secondary_cnt; /* Number of secondary processes init'd. */ 212 }; 213 214 /* Per-process data structure, not visible to other processes. */ 215 struct mlx5_local_data { 216 int init_done; /* Whether a secondary has done initialization. */ 217 }; 218 219 extern struct mlx5_shared_data *mlx5_shared_data; 220 221 /* Dev ops structs */ 222 extern const struct eth_dev_ops mlx5_dev_ops; 223 extern const struct eth_dev_ops mlx5_dev_sec_ops; 224 extern const struct eth_dev_ops mlx5_dev_ops_isolate; 225 226 struct mlx5_counter_ctrl { 227 /* Name of the counter. */ 228 char dpdk_name[RTE_ETH_XSTATS_NAME_SIZE]; 229 /* Name of the counter on the device table. */ 230 char ctr_name[RTE_ETH_XSTATS_NAME_SIZE]; 231 uint32_t dev:1; /**< Nonzero for dev counters. */ 232 }; 233 234 struct mlx5_xstats_ctrl { 235 /* Number of device stats. */ 236 uint16_t stats_n; 237 /* Number of device stats identified by PMD. */ 238 uint16_t mlx5_stats_n; 239 /* Index in the device counters table. */ 240 uint16_t dev_table_idx[MLX5_MAX_XSTATS]; 241 uint64_t base[MLX5_MAX_XSTATS]; 242 uint64_t xstats[MLX5_MAX_XSTATS]; 243 uint64_t hw_stats[MLX5_MAX_XSTATS]; 244 struct mlx5_counter_ctrl info[MLX5_MAX_XSTATS]; 245 }; 246 247 struct mlx5_stats_ctrl { 248 /* Base for imissed counter. */ 249 uint64_t imissed_base; 250 uint64_t imissed; 251 }; 252 253 /* Maximal size of coalesced segment for LRO is set in chunks of 256 Bytes. */ 254 #define MLX5_LRO_SEG_CHUNK_SIZE 256u 255 256 /* Maximal size of aggregated LRO packet. */ 257 #define MLX5_MAX_LRO_SIZE (UINT8_MAX * MLX5_LRO_SEG_CHUNK_SIZE) 258 259 /* Maximal number of segments to split. */ 260 #define MLX5_MAX_RXQ_NSEG (1u << MLX5_MAX_LOG_RQ_SEGS) 261 262 /* 263 * Port configuration structure. 264 * User device parameters disabled features. 265 * This structure contains all configurations coming from devargs which 266 * oriented to port. When probing again, devargs doesn't have to be compatible 267 * with primary devargs. It is updated for each port in spawn function. 268 */ 269 struct mlx5_port_config { 270 unsigned int hw_vlan_insert:1; /* VLAN insertion in WQE is supported. */ 271 unsigned int hw_padding:1; /* End alignment padding is supported. */ 272 unsigned int cqe_comp:1; /* CQE compression is enabled. */ 273 unsigned int cqe_comp_fmt:3; /* CQE compression format. */ 274 unsigned int rx_vec_en:1; /* Rx vector is enabled. */ 275 unsigned int std_delay_drop:1; /* Enable standard Rxq delay drop. */ 276 unsigned int hp_delay_drop:1; /* Enable hairpin Rxq delay drop. */ 277 struct { 278 unsigned int enabled:1; /* Whether MPRQ is enabled. */ 279 unsigned int log_stride_num; /* Log number of strides. */ 280 unsigned int log_stride_size; /* Log size of a stride. */ 281 unsigned int max_memcpy_len; 282 /* Maximum packet size to memcpy Rx packets. */ 283 unsigned int min_rxqs_num; 284 /* Rx queue count threshold to enable MPRQ. */ 285 } mprq; /* Configurations for Multi-Packet RQ. */ 286 int mps; /* Multi-packet send supported mode. */ 287 unsigned int max_dump_files_num; /* Maximum dump files per queue. */ 288 unsigned int log_hp_size; /* Single hairpin queue data size in total. */ 289 unsigned int lro_timeout; /* LRO user configuration. */ 290 int txqs_inline; /* Queue number threshold for inlining. */ 291 int txq_inline_min; /* Minimal amount of data bytes to inline. */ 292 int txq_inline_max; /* Max packet size for inlining with SEND. */ 293 int txq_inline_mpw; /* Max packet size for inlining with eMPW. */ 294 }; 295 296 /* 297 * Share context device configuration structure. 298 * User device parameters disabled features. 299 * This structure updated once for device in mlx5_alloc_shared_dev_ctx() 300 * function and cannot change even when probing again. 301 */ 302 struct mlx5_sh_config { 303 int tx_pp; /* Timestamp scheduling granularity in nanoseconds. */ 304 int tx_skew; /* Tx scheduling skew between WQE and data on wire. */ 305 uint32_t reclaim_mode:2; /* Memory reclaim mode. */ 306 uint32_t dv_esw_en:1; /* Enable E-Switch DV flow. */ 307 /* Enable DV flow. 1 means SW steering, 2 means HW steering. */ 308 uint32_t dv_flow_en:2; /* Enable DV flow. */ 309 uint32_t dv_xmeta_en:3; /* Enable extensive flow metadata. */ 310 uint32_t dv_miss_info:1; /* Restore packet after partial hw miss. */ 311 uint32_t l3_vxlan_en:1; /* Enable L3 VXLAN flow creation. */ 312 uint32_t vf_nl_en:1; /* Enable Netlink requests in VF mode. */ 313 uint32_t lacp_by_user:1; /* Enable user to manage LACP traffic. */ 314 uint32_t decap_en:1; /* Whether decap will be used or not. */ 315 uint32_t hw_fcs_strip:1; /* FCS stripping is supported. */ 316 uint32_t allow_duplicate_pattern:1; 317 uint32_t lro_allowed:1; /* Whether LRO is allowed. */ 318 struct { 319 uint16_t service_core; 320 uint32_t cycle_time; /* query cycle time in milli-second. */ 321 } cnt_svc; /* configure for HW steering's counter's service. */ 322 /* Allow/Prevent the duplicate rules pattern. */ 323 uint32_t fdb_def_rule:1; /* Create FDB default jump rule */ 324 uint32_t repr_matching:1; /* Enable implicit vport matching in HWS FDB. */ 325 }; 326 327 /* Structure for VF VLAN workaround. */ 328 struct mlx5_vf_vlan { 329 uint32_t tag:12; 330 uint32_t created:1; 331 }; 332 333 /* Flow drop context necessary due to Verbs API. */ 334 struct mlx5_drop { 335 struct mlx5_hrxq *hrxq; /* Hash Rx queue queue. */ 336 struct mlx5_rxq_priv *rxq; /* Rx queue. */ 337 }; 338 339 /* Loopback dummy queue resources required due to Verbs API. */ 340 struct mlx5_lb_ctx { 341 struct ibv_qp *qp; /* QP object. */ 342 void *ibv_cq; /* Completion queue. */ 343 uint16_t refcnt; /* Reference count for representors. */ 344 }; 345 346 /* HW steering queue job descriptor type. */ 347 enum { 348 MLX5_HW_Q_JOB_TYPE_CREATE, /* Flow create job type. */ 349 MLX5_HW_Q_JOB_TYPE_DESTROY, /* Flow destroy job type. */ 350 MLX5_HW_Q_JOB_TYPE_UPDATE, 351 MLX5_HW_Q_JOB_TYPE_QUERY, 352 }; 353 354 #define MLX5_HW_MAX_ITEMS (16) 355 356 /* HW steering flow management job descriptor. */ 357 struct mlx5_hw_q_job { 358 uint32_t type; /* Job type. */ 359 union { 360 struct rte_flow_hw *flow; /* Flow attached to the job. */ 361 const void *action; /* Indirect action attached to the job. */ 362 }; 363 void *user_data; /* Job user data. */ 364 uint8_t *encap_data; /* Encap data. */ 365 struct mlx5_modification_cmd *mhdr_cmd; 366 struct rte_flow_item *items; 367 union { 368 struct { 369 /* Pointer to ct query user memory. */ 370 struct rte_flow_action_conntrack *profile; 371 /* Pointer to ct ASO query out memory. */ 372 void *out_data; 373 } __rte_packed; 374 struct rte_flow_item_ethdev port_spec; 375 struct rte_flow_item_tag tag_spec; 376 } __rte_packed; 377 }; 378 379 /* HW steering job descriptor LIFO pool. */ 380 struct mlx5_hw_q { 381 uint32_t job_idx; /* Free job index. */ 382 uint32_t size; /* LIFO size. */ 383 struct mlx5_hw_q_job **job; /* LIFO header. */ 384 struct rte_ring *indir_cq; /* Indirect action SW completion queue. */ 385 struct rte_ring *indir_iq; /* Indirect action SW in progress queue. */ 386 } __rte_cache_aligned; 387 388 389 390 391 #define MLX5_COUNTERS_PER_POOL 512 392 #define MLX5_MAX_PENDING_QUERIES 4 393 #define MLX5_CNT_CONTAINER_RESIZE 64 394 #define MLX5_CNT_SHARED_OFFSET 0x80000000 395 #define IS_BATCH_CNT(cnt) (((cnt) & (MLX5_CNT_SHARED_OFFSET - 1)) >= \ 396 MLX5_CNT_BATCH_OFFSET) 397 #define MLX5_CNT_SIZE (sizeof(struct mlx5_flow_counter)) 398 #define MLX5_AGE_SIZE (sizeof(struct mlx5_age_param)) 399 400 #define MLX5_CNT_LEN(pool) \ 401 (MLX5_CNT_SIZE + \ 402 ((pool)->is_aged ? MLX5_AGE_SIZE : 0)) 403 #define MLX5_POOL_GET_CNT(pool, index) \ 404 ((struct mlx5_flow_counter *) \ 405 ((uint8_t *)((pool) + 1) + (index) * (MLX5_CNT_LEN(pool)))) 406 #define MLX5_CNT_ARRAY_IDX(pool, cnt) \ 407 ((int)(((uint8_t *)(cnt) - (uint8_t *)((pool) + 1)) / \ 408 MLX5_CNT_LEN(pool))) 409 #define MLX5_TS_MASK_SECS 8ull 410 /* timestamp wrapping in seconds, must be power of 2. */ 411 412 /* 413 * The pool index and offset of counter in the pool array makes up the 414 * counter index. In case the counter is from pool 0 and offset 0, it 415 * should plus 1 to avoid index 0, since 0 means invalid counter index 416 * currently. 417 */ 418 #define MLX5_MAKE_CNT_IDX(pi, offset) \ 419 ((pi) * MLX5_COUNTERS_PER_POOL + (offset) + 1) 420 #define MLX5_CNT_TO_AGE(cnt) \ 421 ((struct mlx5_age_param *)((cnt) + 1)) 422 /* 423 * The maximum single counter is 0x800000 as MLX5_CNT_BATCH_OFFSET 424 * defines. The pool size is 512, pool index should never reach 425 * INT16_MAX. 426 */ 427 #define POOL_IDX_INVALID UINT16_MAX 428 429 /* Age status. */ 430 enum { 431 AGE_FREE, /* Initialized state. */ 432 AGE_CANDIDATE, /* Counter assigned to flows. */ 433 AGE_TMOUT, /* Timeout, wait for rte_flow_get_aged_flows and destroy. */ 434 }; 435 436 enum mlx5_counter_type { 437 MLX5_COUNTER_TYPE_ORIGIN, 438 MLX5_COUNTER_TYPE_AGE, 439 MLX5_COUNTER_TYPE_MAX, 440 }; 441 442 /* Counter age parameter. */ 443 struct mlx5_age_param { 444 uint16_t state; /**< Age state (atomically accessed). */ 445 uint16_t port_id; /**< Port id of the counter. */ 446 uint32_t timeout:24; /**< Aging timeout in seconds. */ 447 uint32_t sec_since_last_hit; 448 /**< Time in seconds since last hit (atomically accessed). */ 449 void *context; /**< Flow counter age context. */ 450 }; 451 452 struct flow_counter_stats { 453 uint64_t hits; 454 uint64_t bytes; 455 }; 456 457 /* Shared counters information for counters. */ 458 struct mlx5_flow_counter_shared { 459 union { 460 uint32_t refcnt; /* Only for shared action management. */ 461 uint32_t id; /* User counter ID for legacy sharing. */ 462 }; 463 }; 464 465 struct mlx5_flow_counter_pool; 466 /* Generic counters information. */ 467 struct mlx5_flow_counter { 468 union { 469 /* 470 * User-defined counter shared info is only used during 471 * counter active time. And aging counter sharing is not 472 * supported, so active shared counter will not be chained 473 * to the aging list. For shared counter, only when it is 474 * released, the TAILQ entry memory will be used, at that 475 * time, shared memory is not used anymore. 476 * 477 * Similarly to none-batch counter dcs, since it doesn't 478 * support aging, while counter is allocated, the entry 479 * memory is not used anymore. In this case, as bytes 480 * memory is used only when counter is allocated, and 481 * entry memory is used only when counter is free. The 482 * dcs pointer can be saved to these two different place 483 * at different stage. It will eliminate the individual 484 * counter extend struct. 485 */ 486 TAILQ_ENTRY(mlx5_flow_counter) next; 487 /**< Pointer to the next flow counter structure. */ 488 struct { 489 struct mlx5_flow_counter_shared shared_info; 490 /**< Shared counter information. */ 491 void *dcs_when_active; 492 /* 493 * For non-batch mode, the dcs will be saved 494 * here when the counter is free. 495 */ 496 }; 497 }; 498 union { 499 uint64_t hits; /**< Reset value of hits packets. */ 500 struct mlx5_flow_counter_pool *pool; /**< Counter pool. */ 501 }; 502 union { 503 uint64_t bytes; /**< Reset value of bytes. */ 504 void *dcs_when_free; 505 /* 506 * For non-batch mode, the dcs will be saved here 507 * when the counter is free. 508 */ 509 }; 510 void *action; /**< Pointer to the dv action. */ 511 }; 512 513 TAILQ_HEAD(mlx5_counters, mlx5_flow_counter); 514 515 /* Generic counter pool structure - query is in pool resolution. */ 516 struct mlx5_flow_counter_pool { 517 TAILQ_ENTRY(mlx5_flow_counter_pool) next; 518 struct mlx5_counters counters[2]; /* Free counter list. */ 519 struct mlx5_devx_obj *min_dcs; 520 /* The devx object of the minimum counter ID. */ 521 uint64_t time_of_last_age_check; 522 /* System time (from rte_rdtsc()) read in the last aging check. */ 523 uint32_t index:30; /* Pool index in container. */ 524 uint32_t is_aged:1; /* Pool with aging counter. */ 525 volatile uint32_t query_gen:1; /* Query round. */ 526 rte_spinlock_t sl; /* The pool lock. */ 527 rte_spinlock_t csl; /* The pool counter free list lock. */ 528 struct mlx5_counter_stats_raw *raw; 529 struct mlx5_counter_stats_raw *raw_hw; 530 /* The raw on HW working. */ 531 }; 532 533 /* Memory management structure for group of counter statistics raws. */ 534 struct mlx5_counter_stats_mem_mng { 535 LIST_ENTRY(mlx5_counter_stats_mem_mng) next; 536 struct mlx5_counter_stats_raw *raws; 537 struct mlx5_pmd_wrapped_mr wm; 538 }; 539 540 /* Raw memory structure for the counter statistics values of a pool. */ 541 struct mlx5_counter_stats_raw { 542 LIST_ENTRY(mlx5_counter_stats_raw) next; 543 struct mlx5_counter_stats_mem_mng *mem_mng; 544 volatile struct flow_counter_stats *data; 545 }; 546 547 TAILQ_HEAD(mlx5_counter_pools, mlx5_flow_counter_pool); 548 549 /* Counter global management structure. */ 550 struct mlx5_flow_counter_mng { 551 volatile uint16_t n_valid; /* Number of valid pools. */ 552 uint16_t n; /* Number of pools. */ 553 uint16_t last_pool_idx; /* Last used pool index */ 554 int min_id; /* The minimum counter ID in the pools. */ 555 int max_id; /* The maximum counter ID in the pools. */ 556 rte_spinlock_t pool_update_sl; /* The pool update lock. */ 557 rte_spinlock_t csl[MLX5_COUNTER_TYPE_MAX]; 558 /* The counter free list lock. */ 559 struct mlx5_counters counters[MLX5_COUNTER_TYPE_MAX]; 560 /* Free counter list. */ 561 struct mlx5_flow_counter_pool **pools; /* Counter pool array. */ 562 struct mlx5_counter_stats_mem_mng *mem_mng; 563 /* Hold the memory management for the next allocated pools raws. */ 564 struct mlx5_counters flow_counters; /* Legacy flow counter list. */ 565 uint8_t pending_queries; 566 uint16_t pool_index; 567 uint8_t query_thread_on; 568 bool counter_fallback; /* Use counter fallback management. */ 569 LIST_HEAD(mem_mngs, mlx5_counter_stats_mem_mng) mem_mngs; 570 LIST_HEAD(stat_raws, mlx5_counter_stats_raw) free_stat_raws; 571 }; 572 573 /* ASO structures. */ 574 #define MLX5_ASO_QUEUE_LOG_DESC 10 575 576 struct mlx5_aso_cq { 577 uint16_t log_desc_n; 578 uint32_t cq_ci:24; 579 struct mlx5_devx_cq cq_obj; 580 uint64_t errors; 581 }; 582 583 struct mlx5_aso_sq_elem { 584 union { 585 struct { 586 struct mlx5_aso_age_pool *pool; 587 uint16_t burst_size; 588 }; 589 struct mlx5_aso_mtr *mtr; 590 struct { 591 struct mlx5_aso_ct_action *ct; 592 char *query_data; 593 }; 594 void *user_data; 595 }; 596 }; 597 598 struct mlx5_aso_sq { 599 uint16_t log_desc_n; 600 rte_spinlock_t sqsl; 601 struct mlx5_aso_cq cq; 602 struct mlx5_devx_sq sq_obj; 603 struct mlx5_pmd_mr mr; 604 volatile struct mlx5_aso_wqe *db; 605 uint16_t pi; 606 uint16_t db_pi; 607 uint32_t head; 608 uint32_t tail; 609 uint32_t sqn; 610 struct mlx5_aso_sq_elem elts[1 << MLX5_ASO_QUEUE_LOG_DESC]; 611 uint16_t next; /* Pool index of the next pool to query. */ 612 }; 613 614 struct mlx5_aso_age_action { 615 LIST_ENTRY(mlx5_aso_age_action) next; 616 void *dr_action; 617 uint32_t refcnt; 618 /* Following fields relevant only when action is active. */ 619 uint16_t offset; /* Offset of ASO Flow Hit flag in DevX object. */ 620 struct mlx5_age_param age_params; 621 }; 622 623 #define MLX5_ASO_AGE_ACTIONS_PER_POOL 512 624 625 struct mlx5_aso_age_pool { 626 struct mlx5_devx_obj *flow_hit_aso_obj; 627 uint16_t index; /* Pool index in pools array. */ 628 uint64_t time_of_last_age_check; /* In seconds. */ 629 struct mlx5_aso_age_action actions[MLX5_ASO_AGE_ACTIONS_PER_POOL]; 630 }; 631 632 LIST_HEAD(aso_age_list, mlx5_aso_age_action); 633 634 struct mlx5_aso_age_mng { 635 struct mlx5_aso_age_pool **pools; 636 uint16_t n; /* Total number of pools. */ 637 uint16_t next; /* Number of pools in use, index of next free pool. */ 638 rte_rwlock_t resize_rwl; /* Lock for resize objects. */ 639 rte_spinlock_t free_sl; /* Lock for free list access. */ 640 struct aso_age_list free; /* Free age actions list - ready to use. */ 641 struct mlx5_aso_sq aso_sq; /* ASO queue objects. */ 642 }; 643 644 /* Management structure for geneve tlv option */ 645 struct mlx5_geneve_tlv_option_resource { 646 struct mlx5_devx_obj *obj; /* Pointer to the geneve tlv opt object. */ 647 rte_be16_t option_class; /* geneve tlv opt class.*/ 648 uint8_t option_type; /* geneve tlv opt type.*/ 649 uint8_t length; /* geneve tlv opt length. */ 650 uint32_t refcnt; /* geneve tlv object reference counter */ 651 }; 652 653 654 #define MLX5_AGE_EVENT_NEW 1 655 #define MLX5_AGE_TRIGGER 2 656 #define MLX5_AGE_SET(age_info, BIT) \ 657 ((age_info)->flags |= (1 << (BIT))) 658 #define MLX5_AGE_UNSET(age_info, BIT) \ 659 ((age_info)->flags &= ~(1 << (BIT))) 660 #define MLX5_AGE_GET(age_info, BIT) \ 661 ((age_info)->flags & (1 << (BIT))) 662 #define GET_PORT_AGE_INFO(priv) \ 663 (&((priv)->sh->port[(priv)->dev_port - 1].age_info)) 664 /* Current time in seconds. */ 665 #define MLX5_CURR_TIME_SEC (rte_rdtsc() / rte_get_tsc_hz()) 666 667 /* 668 * HW steering queue oriented AGE info. 669 * It contains an array of rings, one for each HWS queue. 670 */ 671 struct mlx5_hws_q_age_info { 672 uint16_t nb_rings; /* Number of aged-out ring lists. */ 673 struct rte_ring *aged_lists[]; /* Aged-out lists. */ 674 }; 675 676 /* 677 * HW steering AGE info. 678 * It has a ring list containing all aged out flow rules. 679 */ 680 struct mlx5_hws_age_info { 681 struct rte_ring *aged_list; /* Aged out lists. */ 682 }; 683 684 /* Aging information for per port. */ 685 struct mlx5_age_info { 686 uint8_t flags; /* Indicate if is new event or need to be triggered. */ 687 union { 688 /* SW/FW steering AGE info. */ 689 struct { 690 struct mlx5_counters aged_counters; 691 /* Aged counter list. */ 692 struct aso_age_list aged_aso; 693 /* Aged ASO actions list. */ 694 rte_spinlock_t aged_sl; /* Aged flow list lock. */ 695 }; 696 struct { 697 struct mlx5_indexed_pool *ages_ipool; 698 union { 699 struct mlx5_hws_age_info hw_age; 700 /* HW steering AGE info. */ 701 struct mlx5_hws_q_age_info *hw_q_age; 702 /* HW steering queue oriented AGE info. */ 703 }; 704 }; 705 }; 706 }; 707 708 /* Per port data of shared IB device. */ 709 struct mlx5_dev_shared_port { 710 uint32_t ih_port_id; 711 uint32_t devx_ih_port_id; 712 uint32_t nl_ih_port_id; 713 /* 714 * Interrupt handler port_id. Used by shared interrupt 715 * handler to find the corresponding rte_eth device 716 * by IB port index. If value is equal or greater 717 * RTE_MAX_ETHPORTS it means there is no subhandler 718 * installed for specified IB port index. 719 */ 720 struct mlx5_age_info age_info; 721 /* Aging information for per port. */ 722 }; 723 724 /* 725 * Max number of actions per DV flow. 726 * See CREATE_FLOW_MAX_FLOW_ACTIONS_SUPPORTED 727 * in rdma-core file providers/mlx5/verbs.c. 728 */ 729 #define MLX5_DV_MAX_NUMBER_OF_ACTIONS 8 730 731 /* ASO flow meter structures */ 732 /* Modify this value if enum rte_mtr_color changes. */ 733 #define RTE_MTR_DROPPED RTE_COLORS 734 /* Yellow is now supported. */ 735 #define MLX5_MTR_RTE_COLORS (RTE_COLOR_YELLOW + 1) 736 /* table_id 22 bits in mlx5_flow_tbl_key so limit policy number. */ 737 #define MLX5_MAX_SUB_POLICY_TBL_NUM 0x3FFFFF 738 #define MLX5_INVALID_POLICY_ID UINT32_MAX 739 /* Suffix table_id on MLX5_FLOW_TABLE_LEVEL_METER. */ 740 #define MLX5_MTR_TABLE_ID_SUFFIX 1 741 /* Drop table_id on MLX5_FLOW_TABLE_LEVEL_METER. */ 742 #define MLX5_MTR_TABLE_ID_DROP 2 743 /* Priority of the meter policy matcher. */ 744 #define MLX5_MTR_POLICY_MATCHER_PRIO 0 745 /* Green & yellow color valid for now. */ 746 #define MLX5_MTR_POLICY_MODE_ALL 0 747 /* Default policy. */ 748 #define MLX5_MTR_POLICY_MODE_DEF 1 749 /* Only green color valid. */ 750 #define MLX5_MTR_POLICY_MODE_OG 2 751 /* Only yellow color valid. */ 752 #define MLX5_MTR_POLICY_MODE_OY 3 753 754 enum mlx5_meter_domain { 755 MLX5_MTR_DOMAIN_INGRESS, 756 MLX5_MTR_DOMAIN_EGRESS, 757 MLX5_MTR_DOMAIN_TRANSFER, 758 MLX5_MTR_DOMAIN_MAX, 759 }; 760 #define MLX5_MTR_DOMAIN_INGRESS_BIT (1 << MLX5_MTR_DOMAIN_INGRESS) 761 #define MLX5_MTR_DOMAIN_EGRESS_BIT (1 << MLX5_MTR_DOMAIN_EGRESS) 762 #define MLX5_MTR_DOMAIN_TRANSFER_BIT (1 << MLX5_MTR_DOMAIN_TRANSFER) 763 #define MLX5_MTR_ALL_DOMAIN_BIT (MLX5_MTR_DOMAIN_INGRESS_BIT | \ 764 MLX5_MTR_DOMAIN_EGRESS_BIT | \ 765 MLX5_MTR_DOMAIN_TRANSFER_BIT) 766 767 /* The color tag rule structure. */ 768 struct mlx5_sub_policy_color_rule { 769 void *rule; 770 /* The color rule. */ 771 struct mlx5_flow_dv_matcher *matcher; 772 /* The color matcher. */ 773 TAILQ_ENTRY(mlx5_sub_policy_color_rule) next_port; 774 /**< Pointer to the next color rule structure. */ 775 int32_t src_port; 776 /* On which src port this rule applied. */ 777 }; 778 779 TAILQ_HEAD(mlx5_sub_policy_color_rules, mlx5_sub_policy_color_rule); 780 781 /* 782 * Meter sub-policy structure. 783 * Each RSS TIR in meter policy need its own sub-policy resource. 784 */ 785 struct mlx5_flow_meter_sub_policy { 786 uint32_t main_policy_id:1; 787 /* Main policy id is same as this sub_policy id. */ 788 uint32_t idx:31; 789 /* Index to sub_policy ipool entity. */ 790 void *main_policy; 791 /* Point to struct mlx5_flow_meter_policy. */ 792 struct mlx5_flow_tbl_resource *tbl_rsc; 793 /* The sub-policy table resource. */ 794 uint32_t rix_hrxq[MLX5_MTR_RTE_COLORS]; 795 /* Index to TIR resource. */ 796 struct mlx5_flow_tbl_resource *jump_tbl[MLX5_MTR_RTE_COLORS]; 797 /* Meter jump/drop table. */ 798 struct mlx5_sub_policy_color_rules color_rules[RTE_COLORS]; 799 /* List for the color rules. */ 800 }; 801 802 struct mlx5_meter_policy_acts { 803 uint8_t actions_n; 804 /* Number of actions. */ 805 void *dv_actions[MLX5_DV_MAX_NUMBER_OF_ACTIONS]; 806 /* Action list. */ 807 }; 808 809 struct mlx5_meter_policy_action_container { 810 uint32_t rix_mark; 811 /* Index to the mark action. */ 812 struct mlx5_flow_dv_modify_hdr_resource *modify_hdr; 813 /* Pointer to modify header resource in cache. */ 814 uint8_t fate_action; 815 /* Fate action type. */ 816 union { 817 struct rte_flow_action *rss; 818 /* Rss action configuration. */ 819 uint32_t rix_port_id_action; 820 /* Index to port ID action resource. */ 821 void *dr_jump_action[MLX5_MTR_DOMAIN_MAX]; 822 /* Jump/drop action per color. */ 823 uint16_t queue; 824 /* Queue action configuration. */ 825 struct { 826 uint32_t next_mtr_id; 827 /* The next meter id. */ 828 void *next_sub_policy; 829 /* Next meter's sub-policy. */ 830 }; 831 }; 832 }; 833 834 /* Flow meter policy parameter structure. */ 835 struct mlx5_flow_meter_policy { 836 struct rte_eth_dev *dev; 837 /* The port dev on which policy is created. */ 838 uint32_t is_rss:1; 839 /* Is RSS policy table. */ 840 uint32_t ingress:1; 841 /* Rule applies to ingress domain. */ 842 uint32_t egress:1; 843 /* Rule applies to egress domain. */ 844 uint32_t transfer:1; 845 /* Rule applies to transfer domain. */ 846 uint32_t is_queue:1; 847 /* Is queue action in policy table. */ 848 uint32_t is_hierarchy:1; 849 /* Is meter action in policy table. */ 850 uint32_t hierarchy_drop_cnt:1; 851 /* Is any meter in hierarchy contains drop_cnt. */ 852 uint32_t skip_r:1; 853 /* If red color policy is skipped. */ 854 uint32_t skip_y:1; 855 /* If yellow color policy is skipped. */ 856 uint32_t skip_g:1; 857 /* If green color policy is skipped. */ 858 uint32_t mark:1; 859 /* If policy contains mark action. */ 860 uint32_t initialized:1; 861 /* Initialized. */ 862 uint16_t group; 863 /* The group. */ 864 rte_spinlock_t sl; 865 uint32_t ref_cnt; 866 /* Use count. */ 867 struct rte_flow_pattern_template *hws_item_templ; 868 /* Hardware steering item templates. */ 869 struct rte_flow_actions_template *hws_act_templ[MLX5_MTR_DOMAIN_MAX]; 870 /* Hardware steering action templates. */ 871 struct rte_flow_template_table *hws_flow_table[MLX5_MTR_DOMAIN_MAX]; 872 /* Hardware steering tables. */ 873 struct rte_flow *hws_flow_rule[MLX5_MTR_DOMAIN_MAX][RTE_COLORS]; 874 /* Hardware steering rules. */ 875 struct mlx5_meter_policy_action_container act_cnt[MLX5_MTR_RTE_COLORS]; 876 /* Policy actions container. */ 877 void *dr_drop_action[MLX5_MTR_DOMAIN_MAX]; 878 /* drop action for red color. */ 879 uint16_t sub_policy_num; 880 /* Count sub policy tables, 3 bits per domain. */ 881 struct mlx5_flow_meter_sub_policy **sub_policys[MLX5_MTR_DOMAIN_MAX]; 882 /* Sub policy table array must be the end of struct. */ 883 }; 884 885 /* The maximum sub policy is relate to struct mlx5_rss_hash_fields[]. */ 886 #define MLX5_MTR_RSS_MAX_SUB_POLICY 7 887 #define MLX5_MTR_SUB_POLICY_NUM_SHIFT 3 888 #define MLX5_MTR_SUB_POLICY_NUM_MASK 0x7 889 #define MLX5_MTRS_DEFAULT_RULE_PRIORITY 0xFFFF 890 #define MLX5_MTR_CHAIN_MAX_NUM 8 891 892 /* Flow meter default policy parameter structure. 893 * Policy index 0 is reserved by default policy table. 894 * Action per color as below: 895 * green - do nothing, yellow - do nothing, red - drop 896 */ 897 struct mlx5_flow_meter_def_policy { 898 struct mlx5_flow_meter_sub_policy sub_policy; 899 /* Policy rules jump to other tables. */ 900 void *dr_jump_action[RTE_COLORS]; 901 /* Jump action per color. */ 902 }; 903 904 /* Meter parameter structure. */ 905 struct mlx5_flow_meter_info { 906 uint32_t meter_id; 907 /**< Meter id. */ 908 uint32_t policy_id; 909 /* Policy id, the first sub_policy idx. */ 910 struct mlx5_flow_meter_profile *profile; 911 /**< Meter profile parameters. */ 912 rte_spinlock_t sl; /**< Meter action spinlock. */ 913 /** Set of stats counters to be enabled. 914 * @see enum rte_mtr_stats_type 915 */ 916 uint32_t bytes_dropped:1; 917 /** Set bytes dropped stats to be enabled. */ 918 uint32_t pkts_dropped:1; 919 /** Set packets dropped stats to be enabled. */ 920 uint32_t active_state:1; 921 /**< Meter hw active state. */ 922 uint32_t shared:1; 923 /**< Meter shared or not. */ 924 uint32_t is_enable:1; 925 /**< Meter disable/enable state. */ 926 uint32_t ingress:1; 927 /**< Rule applies to egress traffic. */ 928 uint32_t egress:1; 929 /** 930 * Instead of simply matching the properties of traffic as it would 931 * appear on a given DPDK port ID, enabling this attribute transfers 932 * a flow rule to the lowest possible level of any device endpoints 933 * found in the pattern. 934 * 935 * When supported, this effectively enables an application to 936 * re-route traffic not necessarily intended for it (e.g. coming 937 * from or addressed to different physical ports, VFs or 938 * applications) at the device level. 939 * 940 * It complements the behavior of some pattern items such as 941 * RTE_FLOW_ITEM_TYPE_REPRESENTED_PORT and is meaningless without them. 942 * 943 * When transferring flow rules, ingress and egress attributes keep 944 * their original meaning, as if processing traffic emitted or 945 * received by the application. 946 */ 947 uint32_t transfer:1; 948 uint32_t def_policy:1; 949 uint32_t initialized:1; 950 /* Meter points to default policy. */ 951 uint32_t color_aware:1; 952 /* Meter is color aware mode. */ 953 void *drop_rule[MLX5_MTR_DOMAIN_MAX]; 954 /* Meter drop rule in drop table. */ 955 uint32_t drop_cnt; 956 /**< Color counter for drop. */ 957 uint32_t ref_cnt; 958 /**< Use count. */ 959 struct mlx5_indexed_pool *flow_ipool; 960 /**< Index pool for flow id. */ 961 void *meter_action_g; 962 /**< Flow meter action. */ 963 void *meter_action_y; 964 /**< Flow meter action for yellow init_color. */ 965 uint32_t meter_offset; 966 /**< Flow meter offset. */ 967 uint16_t group; 968 /**< Flow meter group. */ 969 }; 970 971 /* PPS(packets per second) map to BPS(Bytes per second). 972 * HW treat packet as 128bytes in PPS mode 973 */ 974 #define MLX5_MTRS_PPS_MAP_BPS_SHIFT 7 975 976 /* RFC2697 parameter structure. */ 977 struct mlx5_flow_meter_srtcm_rfc2697_prm { 978 rte_be32_t cbs_cir; 979 /* 980 * bit 24-28: cbs_exponent, bit 16-23 cbs_mantissa, 981 * bit 8-12: cir_exponent, bit 0-7 cir_mantissa. 982 */ 983 rte_be32_t ebs_eir; 984 /* 985 * bit 24-28: ebs_exponent, bit 16-23 ebs_mantissa, 986 * bit 8-12: eir_exponent, bit 0-7 eir_mantissa. 987 */ 988 }; 989 990 /* Flow meter profile structure. */ 991 struct mlx5_flow_meter_profile { 992 TAILQ_ENTRY(mlx5_flow_meter_profile) next; 993 /**< Pointer to the next flow meter structure. */ 994 uint32_t id; /**< Profile id. */ 995 struct rte_mtr_meter_profile profile; /**< Profile detail. */ 996 union { 997 struct mlx5_flow_meter_srtcm_rfc2697_prm srtcm_prm; 998 /**< srtcm_rfc2697 struct. */ 999 }; 1000 uint32_t ref_cnt; /**< Use count. */ 1001 uint32_t g_support:1; /**< If G color will be generated. */ 1002 uint32_t y_support:1; /**< If Y color will be generated. */ 1003 uint32_t initialized:1; /**< Initialized. */ 1004 }; 1005 1006 /* 2 meters in each ASO cache line */ 1007 #define MLX5_MTRS_CONTAINER_RESIZE 64 1008 /* 1009 * The pool index and offset of meter in the pool array makes up the 1010 * meter index. In case the meter is from pool 0 and offset 0, it 1011 * should plus 1 to avoid index 0, since 0 means invalid meter index 1012 * currently. 1013 */ 1014 #define MLX5_MAKE_MTR_IDX(pi, offset) \ 1015 ((pi) * MLX5_ASO_MTRS_PER_POOL + (offset) + 1) 1016 1017 /*aso flow meter state*/ 1018 enum mlx5_aso_mtr_state { 1019 ASO_METER_FREE, /* In free list. */ 1020 ASO_METER_WAIT, /* ACCESS_ASO WQE in progress. */ 1021 ASO_METER_WAIT_ASYNC, /* CQE will be handled by async pull. */ 1022 ASO_METER_READY, /* CQE received. */ 1023 }; 1024 1025 /*aso flow meter type*/ 1026 enum mlx5_aso_mtr_type { 1027 ASO_METER_INDIRECT, 1028 ASO_METER_DIRECT, 1029 }; 1030 1031 /* Generic aso_flow_meter information. */ 1032 struct mlx5_aso_mtr { 1033 union { 1034 LIST_ENTRY(mlx5_aso_mtr) next; 1035 struct mlx5_aso_mtr_pool *pool; 1036 }; 1037 enum mlx5_aso_mtr_type type; 1038 struct mlx5_flow_meter_info fm; 1039 /**< Pointer to the next aso flow meter structure. */ 1040 uint8_t state; /**< ASO flow meter state. */ 1041 uint32_t offset; 1042 enum rte_color init_color; 1043 }; 1044 1045 /* Generic aso_flow_meter pool structure. */ 1046 struct mlx5_aso_mtr_pool { 1047 struct mlx5_aso_mtr mtrs[MLX5_ASO_MTRS_PER_POOL]; 1048 /*Must be the first in pool*/ 1049 struct mlx5_devx_obj *devx_obj; 1050 /* The devx object of the minimum aso flow meter ID. */ 1051 struct mlx5dr_action *action; /* HWS action. */ 1052 struct mlx5_indexed_pool *idx_pool; /* HWS index pool. */ 1053 uint32_t index; /* Pool index in management structure. */ 1054 uint32_t nb_sq; /* Number of ASO SQ. */ 1055 struct mlx5_aso_sq *sq; /* ASO SQs. */ 1056 }; 1057 1058 LIST_HEAD(aso_meter_list, mlx5_aso_mtr); 1059 /* Pools management structure for ASO flow meter pools. */ 1060 struct mlx5_aso_mtr_pools_mng { 1061 volatile uint16_t n_valid; /* Number of valid pools. */ 1062 uint16_t n; /* Number of pools. */ 1063 rte_spinlock_t mtrsl; /* The ASO flow meter free list lock. */ 1064 rte_rwlock_t resize_mtrwl; /* Lock for resize objects. */ 1065 struct aso_meter_list meters; /* Free ASO flow meter list. */ 1066 struct mlx5_aso_sq sq; /*SQ using by ASO flow meter. */ 1067 struct mlx5_aso_mtr_pool **pools; /* ASO flow meter pool array. */ 1068 }; 1069 1070 /* Bulk management structure for ASO flow meter. */ 1071 struct mlx5_mtr_bulk { 1072 uint32_t size; /* Number of ASO objects. */ 1073 struct mlx5dr_action *action; /* HWS action */ 1074 struct mlx5_devx_obj *devx_obj; /* DEVX object. */ 1075 struct mlx5_aso_mtr *aso; /* Array of ASO objects. */ 1076 }; 1077 1078 /* Meter management structure for global flow meter resource. */ 1079 struct mlx5_flow_mtr_mng { 1080 struct mlx5_aso_mtr_pools_mng pools_mng; 1081 /* Pools management structure for ASO flow meter pools. */ 1082 struct mlx5_flow_meter_def_policy *def_policy[MLX5_MTR_DOMAIN_MAX]; 1083 /* Default policy table. */ 1084 uint32_t def_policy_id; 1085 /* Default policy id. */ 1086 uint32_t def_policy_ref_cnt; 1087 /** def_policy meter use count. */ 1088 struct mlx5_flow_tbl_resource *drop_tbl[MLX5_MTR_DOMAIN_MAX]; 1089 /* Meter drop table. */ 1090 struct mlx5_flow_dv_matcher * 1091 drop_matcher[MLX5_MTR_DOMAIN_MAX][MLX5_REG_BITS]; 1092 /* Matcher meter in drop table. */ 1093 struct mlx5_flow_dv_matcher *def_matcher[MLX5_MTR_DOMAIN_MAX]; 1094 /* Default matcher in drop table. */ 1095 void *def_rule[MLX5_MTR_DOMAIN_MAX]; 1096 /* Default rule in drop table. */ 1097 uint8_t max_mtr_bits; 1098 /* Indicate how many bits are used by meter id at the most. */ 1099 uint8_t max_mtr_flow_bits; 1100 /* Indicate how many bits are used by meter flow id at the most. */ 1101 }; 1102 1103 /* Table key of the hash organization. */ 1104 union mlx5_flow_tbl_key { 1105 struct { 1106 /* Table ID should be at the lowest address. */ 1107 uint32_t level; /**< Level of the table. */ 1108 uint32_t id:22; /**< ID of the table. */ 1109 uint32_t dummy:1; /**< Dummy table for DV API. */ 1110 uint32_t is_fdb:1; /**< 1 - FDB, 0 - NIC TX/RX. */ 1111 uint32_t is_egress:1; /**< 1 - egress, 0 - ingress. */ 1112 uint32_t reserved:7; /**< must be zero for comparison. */ 1113 }; 1114 uint64_t v64; /**< full 64bits value of key */ 1115 }; 1116 1117 /* Table structure. */ 1118 struct mlx5_flow_tbl_resource { 1119 void *obj; /**< Pointer to DR table object. */ 1120 }; 1121 1122 #define MLX5_MAX_TABLES UINT16_MAX 1123 #define MLX5_HAIRPIN_TX_TABLE (UINT16_MAX - 1) 1124 /* Reserve the last two tables for metadata register copy. */ 1125 #define MLX5_FLOW_MREG_ACT_TABLE_GROUP (MLX5_MAX_TABLES - 1) 1126 #define MLX5_FLOW_MREG_CP_TABLE_GROUP (MLX5_MAX_TABLES - 2) 1127 /* Tables for metering splits should be added here. */ 1128 #define MLX5_FLOW_TABLE_LEVEL_METER (MLX5_MAX_TABLES - 3) 1129 #define MLX5_FLOW_TABLE_LEVEL_POLICY (MLX5_MAX_TABLES - 4) 1130 #define MLX5_MAX_TABLES_EXTERNAL MLX5_FLOW_TABLE_LEVEL_POLICY 1131 #define MLX5_FLOW_TABLE_HWS_POLICY (MLX5_MAX_TABLES - 10) 1132 #define MLX5_MAX_TABLES_FDB UINT16_MAX 1133 #define MLX5_FLOW_TABLE_FACTOR 10 1134 1135 /* ID generation structure. */ 1136 struct mlx5_flow_id_pool { 1137 uint32_t *free_arr; /**< Pointer to the a array of free values. */ 1138 uint32_t base_index; 1139 /**< The next index that can be used without any free elements. */ 1140 uint32_t *curr; /**< Pointer to the index to pop. */ 1141 uint32_t *last; /**< Pointer to the last element in the empty array. */ 1142 uint32_t max_id; /**< Maximum id can be allocated from the pool. */ 1143 }; 1144 1145 /* Tx pacing queue structure - for Clock and Rearm queues. */ 1146 struct mlx5_txpp_wq { 1147 /* Completion Queue related data.*/ 1148 struct mlx5_devx_cq cq_obj; 1149 uint32_t cq_ci:24; 1150 uint32_t arm_sn:2; 1151 /* Send Queue related data.*/ 1152 struct mlx5_devx_sq sq_obj; 1153 uint16_t sq_size; /* Number of WQEs in the queue. */ 1154 uint16_t sq_ci; /* Next WQE to execute. */ 1155 }; 1156 1157 /* Tx packet pacing internal timestamp. */ 1158 struct mlx5_txpp_ts { 1159 uint64_t ci_ts; 1160 uint64_t ts; 1161 }; 1162 1163 /* Tx packet pacing structure. */ 1164 struct mlx5_dev_txpp { 1165 pthread_mutex_t mutex; /* Pacing create/destroy mutex. */ 1166 uint32_t refcnt; /* Pacing reference counter. */ 1167 uint32_t freq; /* Timestamp frequency, Hz. */ 1168 uint32_t tick; /* Completion tick duration in nanoseconds. */ 1169 uint32_t test; /* Packet pacing test mode. */ 1170 int32_t skew; /* Scheduling skew. */ 1171 struct rte_intr_handle *intr_handle; /* Periodic interrupt. */ 1172 void *echan; /* Event Channel. */ 1173 struct mlx5_txpp_wq clock_queue; /* Clock Queue. */ 1174 struct mlx5_txpp_wq rearm_queue; /* Clock Queue. */ 1175 void *pp; /* Packet pacing context. */ 1176 uint16_t pp_id; /* Packet pacing context index. */ 1177 uint16_t ts_n; /* Number of captured timestamps. */ 1178 uint16_t ts_p; /* Pointer to statistics timestamp. */ 1179 struct mlx5_txpp_ts *tsa; /* Timestamps sliding window stats. */ 1180 struct mlx5_txpp_ts ts; /* Cached completion id/timestamp. */ 1181 uint32_t sync_lost:1; /* ci/timestamp synchronization lost. */ 1182 /* Statistics counters. */ 1183 uint64_t err_miss_int; /* Missed service interrupt. */ 1184 uint64_t err_rearm_queue; /* Rearm Queue errors. */ 1185 uint64_t err_clock_queue; /* Clock Queue errors. */ 1186 uint64_t err_ts_past; /* Timestamp in the past. */ 1187 uint64_t err_ts_future; /* Timestamp in the distant future. */ 1188 }; 1189 1190 /* Sample ID information of eCPRI flex parser structure. */ 1191 struct mlx5_ecpri_parser_profile { 1192 uint32_t num; /* Actual number of samples. */ 1193 uint32_t ids[8]; /* Sample IDs for this profile. */ 1194 uint8_t offset[8]; /* Bytes offset of each parser. */ 1195 void *obj; /* Flex parser node object. */ 1196 }; 1197 1198 /* Max member ports per bonding device. */ 1199 #define MLX5_BOND_MAX_PORTS 2 1200 1201 /* Bonding device information. */ 1202 struct mlx5_bond_info { 1203 int n_port; /* Number of bond member ports. */ 1204 uint32_t ifindex; 1205 char ifname[MLX5_NAMESIZE + 1]; 1206 struct { 1207 char ifname[MLX5_NAMESIZE + 1]; 1208 uint32_t ifindex; 1209 struct rte_pci_addr pci_addr; 1210 } ports[MLX5_BOND_MAX_PORTS]; 1211 }; 1212 1213 /* Number of connection tracking objects per pool: must be a power of 2. */ 1214 #define MLX5_ASO_CT_ACTIONS_PER_POOL 64 1215 1216 /* Generate incremental and unique CT index from pool and offset. */ 1217 #define MLX5_MAKE_CT_IDX(pool, offset) \ 1218 ((pool) * MLX5_ASO_CT_ACTIONS_PER_POOL + (offset) + 1) 1219 1220 /* ASO Conntrack state. */ 1221 enum mlx5_aso_ct_state { 1222 ASO_CONNTRACK_FREE, /* Inactive, in the free list. */ 1223 ASO_CONNTRACK_WAIT, /* WQE sent in the SQ. */ 1224 ASO_CONNTRACK_WAIT_ASYNC, /* CQE will be handled by async pull. */ 1225 ASO_CONNTRACK_READY, /* CQE received w/o error. */ 1226 ASO_CONNTRACK_QUERY, /* WQE for query sent. */ 1227 ASO_CONNTRACK_MAX, /* Guard. */ 1228 }; 1229 1230 /* Generic ASO connection tracking structure. */ 1231 struct mlx5_aso_ct_action { 1232 union { 1233 /* SWS mode struct. */ 1234 struct { 1235 /* Pointer to the next ASO CT. Used only in SWS. */ 1236 LIST_ENTRY(mlx5_aso_ct_action) next; 1237 }; 1238 /* HWS mode struct. */ 1239 struct { 1240 /* Pointer to action pool. Used only in HWS. */ 1241 struct mlx5_aso_ct_pool *pool; 1242 }; 1243 }; 1244 /* General action object for original dir. */ 1245 void *dr_action_orig; 1246 /* General action object for reply dir. */ 1247 void *dr_action_rply; 1248 uint32_t refcnt; /* Action used count in device flows. */ 1249 uint16_t offset; /* Offset of ASO CT in DevX objects bulk. */ 1250 uint16_t peer; /* The only peer port index could also use this CT. */ 1251 enum mlx5_aso_ct_state state; /* ASO CT state. */ 1252 bool is_original; /* The direction of the DR action to be used. */ 1253 }; 1254 1255 /* CT action object state update. */ 1256 #define MLX5_ASO_CT_UPDATE_STATE(c, s) \ 1257 __atomic_store_n(&((c)->state), (s), __ATOMIC_RELAXED) 1258 1259 #ifdef PEDANTIC 1260 #pragma GCC diagnostic ignored "-Wpedantic" 1261 #endif 1262 1263 /* ASO connection tracking software pool definition. */ 1264 struct mlx5_aso_ct_pool { 1265 uint16_t index; /* Pool index in pools array. */ 1266 /* Free ASO CT index in the pool. Used by HWS. */ 1267 struct mlx5_indexed_pool *cts; 1268 struct mlx5_devx_obj *devx_obj; 1269 union { 1270 void *dummy_action; 1271 /* Dummy action to increase the reference count in the driver. */ 1272 struct mlx5dr_action *dr_action; 1273 /* HWS action. */ 1274 }; 1275 struct mlx5_aso_sq *sq; /* Async ASO SQ. */ 1276 struct mlx5_aso_sq *shared_sq; /* Shared ASO SQ. */ 1277 struct mlx5_aso_ct_action actions[0]; 1278 /* CT action structures bulk. */ 1279 }; 1280 1281 LIST_HEAD(aso_ct_list, mlx5_aso_ct_action); 1282 1283 #define MLX5_ASO_CT_SQ_NUM 16 1284 1285 /* Pools management structure for ASO connection tracking pools. */ 1286 struct mlx5_aso_ct_pools_mng { 1287 struct mlx5_aso_ct_pool **pools; 1288 uint16_t n; /* Total number of pools. */ 1289 uint16_t next; /* Number of pools in use, index of next free pool. */ 1290 uint32_t nb_sq; /* Number of ASO SQ. */ 1291 rte_spinlock_t ct_sl; /* The ASO CT free list lock. */ 1292 rte_rwlock_t resize_rwl; /* The ASO CT pool resize lock. */ 1293 struct aso_ct_list free_cts; /* Free ASO CT objects list. */ 1294 struct mlx5_aso_sq aso_sqs[0]; /* ASO queue objects. */ 1295 }; 1296 1297 #ifdef PEDANTIC 1298 #pragma GCC diagnostic error "-Wpedantic" 1299 #endif 1300 1301 /* LAG attr. */ 1302 struct mlx5_lag { 1303 uint8_t tx_remap_affinity[16]; /* The PF port number of affinity */ 1304 uint8_t affinity_mode; /* TIS or hash based affinity */ 1305 }; 1306 1307 /* DevX flex parser context. */ 1308 struct mlx5_flex_parser_devx { 1309 struct mlx5_list_entry entry; /* List element at the beginning. */ 1310 uint32_t num_samples; 1311 void *devx_obj; 1312 struct mlx5_devx_graph_node_attr devx_conf; 1313 uint32_t sample_ids[MLX5_GRAPH_NODE_SAMPLE_NUM]; 1314 }; 1315 1316 /* Pattern field descriptor - how to translate flex pattern into samples. */ 1317 __extension__ 1318 struct mlx5_flex_pattern_field { 1319 uint16_t width:6; 1320 uint16_t shift:5; 1321 uint16_t reg_id:5; 1322 }; 1323 #define MLX5_INVALID_SAMPLE_REG_ID 0x1F 1324 1325 /* Port flex item context. */ 1326 struct mlx5_flex_item { 1327 struct mlx5_flex_parser_devx *devx_fp; /* DevX flex parser object. */ 1328 uint32_t refcnt; /* Atomically accessed refcnt by flows. */ 1329 enum rte_flow_item_flex_tunnel_mode tunnel_mode; /* Tunnel mode. */ 1330 uint32_t mapnum; /* Number of pattern translation entries. */ 1331 struct mlx5_flex_pattern_field map[MLX5_FLEX_ITEM_MAPPING_NUM]; 1332 }; 1333 1334 struct mlx5_send_to_kernel_action { 1335 void *action; 1336 void *tbl; 1337 }; 1338 1339 #define HWS_CNT_ASO_SQ_NUM 4 1340 1341 struct mlx5_hws_aso_mng { 1342 uint16_t sq_num; 1343 struct mlx5_aso_sq sqs[HWS_CNT_ASO_SQ_NUM]; 1344 }; 1345 1346 struct mlx5_hws_cnt_svc_mng { 1347 uint32_t refcnt; 1348 uint32_t service_core; 1349 uint32_t query_interval; 1350 pthread_t service_thread; 1351 uint8_t svc_running; 1352 struct mlx5_hws_aso_mng aso_mng __rte_cache_aligned; 1353 }; 1354 1355 /* 1356 * Shared Infiniband device context for Master/Representors 1357 * which belong to same IB device with multiple IB ports. 1358 **/ 1359 struct mlx5_dev_ctx_shared { 1360 LIST_ENTRY(mlx5_dev_ctx_shared) next; 1361 uint32_t refcnt; 1362 uint32_t esw_mode:1; /* Whether is E-Switch mode. */ 1363 uint32_t flow_hit_aso_en:1; /* Flow Hit ASO is supported. */ 1364 uint32_t steering_format_version:4; 1365 /* Indicates the device steering logic format. */ 1366 uint32_t meter_aso_en:1; /* Flow Meter ASO is supported. */ 1367 uint32_t ct_aso_en:1; /* Connection Tracking ASO is supported. */ 1368 uint32_t tunnel_header_0_1:1; /* tunnel_header_0_1 is supported. */ 1369 uint32_t tunnel_header_2_3:1; /* tunnel_header_2_3 is supported. */ 1370 uint32_t misc5_cap:1; /* misc5 matcher parameter is supported. */ 1371 uint32_t dr_drop_action_en:1; /* Use DR drop action. */ 1372 uint32_t drop_action_check_flag:1; /* Check Flag for drop action. */ 1373 uint32_t flow_priority_check_flag:1; /* Check Flag for flow priority. */ 1374 uint32_t metadata_regc_check_flag:1; /* Check Flag for metadata REGC. */ 1375 uint32_t hws_tags:1; /* Check if tags info for HWS initialized. */ 1376 uint32_t shared_mark_enabled:1; 1377 /* If mark action is enabled on Rxqs (shared E-Switch domain). */ 1378 uint32_t hws_max_log_bulk_sz:5; 1379 /* Log of minimal HWS counters created hard coded. */ 1380 uint32_t hws_max_nb_counters; /* Maximal number for HWS counters. */ 1381 uint32_t max_port; /* Maximal IB device port index. */ 1382 struct mlx5_bond_info bond; /* Bonding information. */ 1383 struct mlx5_common_device *cdev; /* Backend mlx5 device. */ 1384 uint32_t tdn; /* Transport Domain number. */ 1385 char ibdev_name[MLX5_FS_NAME_MAX]; /* SYSFS dev name. */ 1386 char ibdev_path[MLX5_FS_PATH_MAX]; /* SYSFS dev path for secondary */ 1387 struct mlx5_dev_cap dev_cap; /* Device capabilities. */ 1388 struct mlx5_sh_config config; /* Device configuration. */ 1389 int numa_node; /* Numa node of backing physical device. */ 1390 /* Packet pacing related structure. */ 1391 struct mlx5_dev_txpp txpp; 1392 /* Shared DV/DR flow data section. */ 1393 uint32_t dv_meta_mask; /* flow META metadata supported mask. */ 1394 uint32_t dv_mark_mask; /* flow MARK metadata supported mask. */ 1395 uint32_t dv_regc0_mask; /* available bits of metadata reg_c[0]. */ 1396 void *fdb_domain; /* FDB Direct Rules name space handle. */ 1397 void *rx_domain; /* RX Direct Rules name space handle. */ 1398 void *tx_domain; /* TX Direct Rules name space handle. */ 1399 #ifndef RTE_ARCH_64 1400 rte_spinlock_t uar_lock_cq; /* CQs share a common distinct UAR. */ 1401 rte_spinlock_t uar_lock[MLX5_UAR_PAGE_NUM_MAX]; 1402 /* UAR same-page access control required in 32bit implementations. */ 1403 #endif 1404 union { 1405 struct mlx5_hlist *flow_tbls; /* SWS flow table. */ 1406 struct mlx5_hlist *groups; /* HWS flow group. */ 1407 }; 1408 struct mlx5_flow_tunnel_hub *tunnel_hub; 1409 /* Direct Rules tables for FDB, NIC TX+RX */ 1410 void *dr_drop_action; /* Pointer to DR drop action, any domain. */ 1411 void *pop_vlan_action; /* Pointer to DR pop VLAN action. */ 1412 struct mlx5_send_to_kernel_action send_to_kernel_action; 1413 struct mlx5_hlist *encaps_decaps; /* Encap/decap action hash list. */ 1414 struct mlx5_hlist *modify_cmds; 1415 struct mlx5_hlist *tag_table; 1416 struct mlx5_list *port_id_action_list; /* Port ID action list. */ 1417 struct mlx5_list *push_vlan_action_list; /* Push VLAN actions. */ 1418 struct mlx5_list *sample_action_list; /* List of sample actions. */ 1419 struct mlx5_list *dest_array_list; 1420 struct mlx5_list *flex_parsers_dv; /* Flex Item parsers. */ 1421 /* List of destination array actions. */ 1422 struct mlx5_flow_counter_mng sws_cmng; 1423 /* SW steering counters management structure. */ 1424 void *default_miss_action; /* Default miss action. */ 1425 struct mlx5_indexed_pool *ipool[MLX5_IPOOL_MAX]; 1426 struct mlx5_indexed_pool *mdh_ipools[MLX5_MAX_MODIFY_NUM]; 1427 /* Shared interrupt handler section. */ 1428 struct rte_intr_handle *intr_handle; /* Interrupt handler for device. */ 1429 struct rte_intr_handle *intr_handle_devx; /* DEVX interrupt handler. */ 1430 struct rte_intr_handle *intr_handle_nl; /* Netlink interrupt handler. */ 1431 void *devx_comp; /* DEVX async comp obj. */ 1432 struct mlx5_devx_obj *tis[16]; /* TIS object. */ 1433 struct mlx5_devx_obj *td; /* Transport domain. */ 1434 struct mlx5_lag lag; /* LAG attributes */ 1435 struct mlx5_uar tx_uar; /* DevX UAR for Tx and Txpp and ASO SQs. */ 1436 struct mlx5_uar rx_uar; /* DevX UAR for Rx. */ 1437 struct mlx5_proc_priv *pppriv; /* Pointer to primary private process. */ 1438 struct mlx5_ecpri_parser_profile ecpri_parser; 1439 /* Flex parser profiles information. */ 1440 LIST_HEAD(shared_rxqs, mlx5_rxq_ctrl) shared_rxqs; /* Shared RXQs. */ 1441 struct mlx5_aso_age_mng *aso_age_mng; 1442 /* Management data for aging mechanism using ASO Flow Hit. */ 1443 struct mlx5_geneve_tlv_option_resource *geneve_tlv_option_resource; 1444 /* Management structure for geneve tlv option */ 1445 rte_spinlock_t geneve_tlv_opt_sl; /* Lock for geneve tlv resource */ 1446 struct mlx5_flow_mtr_mng *mtrmng; 1447 /* Meter management structure. */ 1448 struct mlx5_aso_ct_pools_mng *ct_mng; /* Management data for ASO CT in HWS only. */ 1449 struct mlx5_lb_ctx self_lb; /* QP to enable self loopback for Devx. */ 1450 unsigned int flow_max_priority; 1451 enum modify_reg flow_mreg_c[MLX5_MREG_C_NUM]; 1452 /* Availability of mreg_c's. */ 1453 void *devx_channel_lwm; 1454 struct rte_intr_handle *intr_handle_lwm; 1455 pthread_mutex_t lwm_config_lock; 1456 uint32_t host_shaper_rate:8; 1457 uint32_t lwm_triggered:1; 1458 struct mlx5_hws_cnt_svc_mng *cnt_svc; 1459 struct mlx5_dev_shared_port port[]; /* per device port data array. */ 1460 }; 1461 1462 /* 1463 * Per-process private structure. 1464 * Caution, secondary process may rebuild the struct during port start. 1465 */ 1466 struct mlx5_proc_priv { 1467 size_t uar_table_sz; 1468 /* Size of UAR register table. */ 1469 struct mlx5_uar_data uar_table[]; 1470 /* Table of UAR registers for each process. */ 1471 }; 1472 1473 /* MTR profile list. */ 1474 TAILQ_HEAD(mlx5_mtr_profiles, mlx5_flow_meter_profile); 1475 /* MTR list. */ 1476 TAILQ_HEAD(mlx5_legacy_flow_meters, mlx5_legacy_flow_meter); 1477 1478 struct mlx5_mtr_config { 1479 uint32_t nb_meters; /**< Number of configured meters */ 1480 uint32_t nb_meter_profiles; /**< Number of configured meter profiles */ 1481 uint32_t nb_meter_policies; /**< Number of configured meter policies */ 1482 }; 1483 1484 /* RSS description. */ 1485 struct mlx5_flow_rss_desc { 1486 uint32_t level; 1487 uint32_t queue_num; /**< Number of entries in @p queue. */ 1488 uint64_t types; /**< Specific RSS hash types (see RTE_ETH_RSS_*). */ 1489 uint64_t hash_fields; /* Verbs Hash fields. */ 1490 uint8_t key[MLX5_RSS_HASH_KEY_LEN]; /**< RSS hash key. */ 1491 uint32_t key_len; /**< RSS hash key len. */ 1492 uint32_t hws_flags; /**< HW steering action. */ 1493 uint32_t tunnel; /**< Queue in tunnel. */ 1494 uint32_t shared_rss; /**< Shared RSS index. */ 1495 struct mlx5_ind_table_obj *ind_tbl; 1496 /**< Indirection table for shared RSS hash RX queues. */ 1497 union { 1498 uint16_t *queue; /**< Destination queues. */ 1499 const uint16_t *const_q; /**< Const pointer convert. */ 1500 }; 1501 }; 1502 1503 #define MLX5_PROC_PRIV(port_id) \ 1504 ((struct mlx5_proc_priv *)rte_eth_devices[port_id].process_private) 1505 1506 /* Verbs/DevX Rx queue elements. */ 1507 struct mlx5_rxq_obj { 1508 LIST_ENTRY(mlx5_rxq_obj) next; /* Pointer to the next element. */ 1509 struct mlx5_rxq_ctrl *rxq_ctrl; /* Back pointer to parent. */ 1510 int fd; /* File descriptor for event channel */ 1511 RTE_STD_C11 1512 union { 1513 struct { 1514 void *wq; /* Work Queue. */ 1515 void *ibv_cq; /* Completion Queue. */ 1516 void *ibv_channel; 1517 }; 1518 struct mlx5_devx_obj *rq; /* DevX RQ object for hairpin. */ 1519 struct { 1520 struct mlx5_devx_rmp devx_rmp; /* RMP for shared RQ. */ 1521 struct mlx5_devx_cq cq_obj; /* DevX CQ object. */ 1522 void *devx_channel; 1523 }; 1524 }; 1525 }; 1526 1527 /* Indirection table. */ 1528 struct mlx5_ind_table_obj { 1529 LIST_ENTRY(mlx5_ind_table_obj) next; /* Pointer to the next element. */ 1530 uint32_t refcnt; /* Reference counter. */ 1531 RTE_STD_C11 1532 union { 1533 void *ind_table; /**< Indirection table. */ 1534 struct mlx5_devx_obj *rqt; /* DevX RQT object. */ 1535 }; 1536 uint32_t queues_n; /**< Number of queues in the list. */ 1537 uint16_t *queues; /**< Queue list. */ 1538 }; 1539 1540 /* Hash Rx queue. */ 1541 __extension__ 1542 struct mlx5_hrxq { 1543 struct mlx5_list_entry entry; /* List entry. */ 1544 uint32_t standalone:1; /* This object used in shared action. */ 1545 struct mlx5_ind_table_obj *ind_table; /* Indirection table. */ 1546 RTE_STD_C11 1547 union { 1548 void *qp; /* Verbs queue pair. */ 1549 struct mlx5_devx_obj *tir; /* DevX TIR object. */ 1550 }; 1551 #if defined(HAVE_IBV_FLOW_DV_SUPPORT) || !defined(HAVE_INFINIBAND_VERBS_H) 1552 void *action; /* DV QP action pointer. */ 1553 #endif 1554 uint32_t hws_flags; /* Hw steering flags. */ 1555 uint64_t hash_fields; /* Verbs Hash fields. */ 1556 uint32_t rss_key_len; /* Hash key length in bytes. */ 1557 uint32_t idx; /* Hash Rx queue index. */ 1558 uint8_t rss_key[]; /* Hash key. */ 1559 }; 1560 1561 /* Verbs/DevX Tx queue elements. */ 1562 struct mlx5_txq_obj { 1563 LIST_ENTRY(mlx5_txq_obj) next; /* Pointer to the next element. */ 1564 struct mlx5_txq_ctrl *txq_ctrl; /* Pointer to the control queue. */ 1565 RTE_STD_C11 1566 union { 1567 struct { 1568 void *cq; /* Completion Queue. */ 1569 void *qp; /* Queue Pair. */ 1570 }; 1571 struct { 1572 struct mlx5_devx_obj *sq; 1573 /* DevX object for Sx queue. */ 1574 struct mlx5_devx_obj *tis; /* The TIS object. */ 1575 void *umem_buf_wq_buffer; 1576 void *umem_obj_wq_buffer; 1577 }; 1578 struct { 1579 struct rte_eth_dev *dev; 1580 struct mlx5_devx_cq cq_obj; 1581 /* DevX CQ object and its resources. */ 1582 struct mlx5_devx_sq sq_obj; 1583 /* DevX SQ object and its resources. */ 1584 }; 1585 }; 1586 }; 1587 1588 enum mlx5_rxq_modify_type { 1589 MLX5_RXQ_MOD_ERR2RST, /* modify state from error to reset. */ 1590 MLX5_RXQ_MOD_RST2RDY, /* modify state from reset to ready. */ 1591 MLX5_RXQ_MOD_RDY2ERR, /* modify state from ready to error. */ 1592 MLX5_RXQ_MOD_RDY2RST, /* modify state from ready to reset. */ 1593 MLX5_RXQ_MOD_RDY2RDY, /* modify state from ready to ready. */ 1594 }; 1595 1596 enum mlx5_txq_modify_type { 1597 MLX5_TXQ_MOD_RST2RDY, /* modify state from reset to ready. */ 1598 MLX5_TXQ_MOD_RDY2RST, /* modify state from ready to reset. */ 1599 MLX5_TXQ_MOD_ERR2RDY, /* modify state from error to ready. */ 1600 }; 1601 1602 struct mlx5_rxq_priv; 1603 struct mlx5_priv; 1604 1605 /* HW objects operations structure. */ 1606 struct mlx5_obj_ops { 1607 int (*rxq_obj_modify_vlan_strip)(struct mlx5_rxq_priv *rxq, int on); 1608 int (*rxq_obj_new)(struct mlx5_rxq_priv *rxq); 1609 int (*rxq_event_get)(struct mlx5_rxq_obj *rxq_obj); 1610 int (*rxq_obj_modify)(struct mlx5_rxq_priv *rxq, uint8_t type); 1611 void (*rxq_obj_release)(struct mlx5_rxq_priv *rxq); 1612 int (*rxq_event_get_lwm)(struct mlx5_priv *priv, int *rxq_idx, int *port_id); 1613 int (*ind_table_new)(struct rte_eth_dev *dev, const unsigned int log_n, 1614 struct mlx5_ind_table_obj *ind_tbl); 1615 int (*ind_table_modify)(struct rte_eth_dev *dev, 1616 const unsigned int log_n, 1617 const uint16_t *queues, const uint32_t queues_n, 1618 struct mlx5_ind_table_obj *ind_tbl); 1619 void (*ind_table_destroy)(struct mlx5_ind_table_obj *ind_tbl); 1620 int (*hrxq_new)(struct rte_eth_dev *dev, struct mlx5_hrxq *hrxq, 1621 int tunnel __rte_unused); 1622 int (*hrxq_modify)(struct rte_eth_dev *dev, struct mlx5_hrxq *hrxq, 1623 const uint8_t *rss_key, 1624 uint64_t hash_fields, 1625 const struct mlx5_ind_table_obj *ind_tbl); 1626 void (*hrxq_destroy)(struct mlx5_hrxq *hrxq); 1627 int (*drop_action_create)(struct rte_eth_dev *dev); 1628 void (*drop_action_destroy)(struct rte_eth_dev *dev); 1629 int (*txq_obj_new)(struct rte_eth_dev *dev, uint16_t idx); 1630 int (*txq_obj_modify)(struct mlx5_txq_obj *obj, 1631 enum mlx5_txq_modify_type type, uint8_t dev_port); 1632 void (*txq_obj_release)(struct mlx5_txq_obj *txq_obj); 1633 int (*lb_dummy_queue_create)(struct rte_eth_dev *dev); 1634 void (*lb_dummy_queue_release)(struct rte_eth_dev *dev); 1635 }; 1636 1637 #define MLX5_RSS_HASH_FIELDS_LEN RTE_DIM(mlx5_rss_hash_fields) 1638 1639 struct mlx5_hw_ctrl_flow { 1640 LIST_ENTRY(mlx5_hw_ctrl_flow) next; 1641 struct rte_eth_dev *owner_dev; 1642 struct rte_flow *flow; 1643 }; 1644 1645 struct mlx5_flow_hw_ctrl_rx; 1646 1647 struct mlx5_priv { 1648 struct rte_eth_dev_data *dev_data; /* Pointer to device data. */ 1649 struct mlx5_dev_ctx_shared *sh; /* Shared device context. */ 1650 uint32_t dev_port; /* Device port number. */ 1651 struct rte_pci_device *pci_dev; /* Backend PCI device. */ 1652 struct rte_ether_addr mac[MLX5_MAX_MAC_ADDRESSES]; /* MAC addresses. */ 1653 BITFIELD_DECLARE(mac_own, uint64_t, MLX5_MAX_MAC_ADDRESSES); 1654 /* Bit-field of MAC addresses owned by the PMD. */ 1655 uint16_t vlan_filter[MLX5_MAX_VLAN_IDS]; /* VLAN filters table. */ 1656 unsigned int vlan_filter_n; /* Number of configured VLAN filters. */ 1657 /* Device properties. */ 1658 uint16_t mtu; /* Configured MTU. */ 1659 unsigned int isolated:1; /* Whether isolated mode is enabled. */ 1660 unsigned int representor:1; /* Device is a port representor. */ 1661 unsigned int master:1; /* Device is a E-Switch master. */ 1662 unsigned int txpp_en:1; /* Tx packet pacing enabled. */ 1663 unsigned int sampler_en:1; /* Whether support sampler. */ 1664 unsigned int mtr_en:1; /* Whether support meter. */ 1665 unsigned int mtr_reg_share:1; /* Whether support meter REG_C share. */ 1666 unsigned int lb_used:1; /* Loopback queue is referred to. */ 1667 uint32_t mark_enabled:1; /* If mark action is enabled on rxqs. */ 1668 uint16_t domain_id; /* Switch domain identifier. */ 1669 uint16_t vport_id; /* Associated VF vport index (if any). */ 1670 uint32_t vport_meta_tag; /* Used for vport index match ove VF LAG. */ 1671 uint32_t vport_meta_mask; /* Used for vport index field match mask. */ 1672 uint16_t representor_id; /* UINT16_MAX if not a representor. */ 1673 int32_t pf_bond; /* >=0, representor owner PF index in bonding. */ 1674 unsigned int if_index; /* Associated kernel network device index. */ 1675 /* RX/TX queues. */ 1676 unsigned int rxqs_n; /* RX queues array size. */ 1677 unsigned int txqs_n; /* TX queues array size. */ 1678 struct mlx5_external_rxq *ext_rxqs; /* External RX queues array. */ 1679 struct mlx5_rxq_priv *(*rxq_privs)[]; /* RX queue non-shared data. */ 1680 struct mlx5_txq_data *(*txqs)[]; /* TX queues. */ 1681 struct rte_mempool *mprq_mp; /* Mempool for Multi-Packet RQ. */ 1682 struct rte_eth_rss_conf rss_conf; /* RSS configuration. */ 1683 unsigned int (*reta_idx)[]; /* RETA index table. */ 1684 unsigned int reta_idx_n; /* RETA index size. */ 1685 struct mlx5_drop drop_queue; /* Flow drop queues. */ 1686 void *root_drop_action; /* Pointer to root drop action. */ 1687 rte_spinlock_t hw_ctrl_lock; 1688 LIST_HEAD(hw_ctrl_flow, mlx5_hw_ctrl_flow) hw_ctrl_flows; 1689 struct rte_flow_template_table *hw_esw_sq_miss_root_tbl; 1690 struct rte_flow_template_table *hw_esw_sq_miss_tbl; 1691 struct rte_flow_template_table *hw_esw_zero_tbl; 1692 struct rte_flow_template_table *hw_tx_meta_cpy_tbl; 1693 struct rte_flow_pattern_template *hw_tx_repr_tagging_pt; 1694 struct rte_flow_actions_template *hw_tx_repr_tagging_at; 1695 struct rte_flow_template_table *hw_tx_repr_tagging_tbl; 1696 struct mlx5_indexed_pool *flows[MLX5_FLOW_TYPE_MAXI]; 1697 /* RTE Flow rules. */ 1698 uint32_t ctrl_flows; /* Control flow rules. */ 1699 rte_spinlock_t flow_list_lock; 1700 struct mlx5_obj_ops obj_ops; /* HW objects operations. */ 1701 LIST_HEAD(rxq, mlx5_rxq_ctrl) rxqsctrl; /* DPDK Rx queues. */ 1702 LIST_HEAD(rxqobj, mlx5_rxq_obj) rxqsobj; /* Verbs/DevX Rx queues. */ 1703 struct mlx5_list *hrxqs; /* Hash Rx queues. */ 1704 LIST_HEAD(txq, mlx5_txq_ctrl) txqsctrl; /* DPDK Tx queues. */ 1705 LIST_HEAD(txqobj, mlx5_txq_obj) txqsobj; /* Verbs/DevX Tx queues. */ 1706 /* Indirection tables. */ 1707 LIST_HEAD(ind_tables, mlx5_ind_table_obj) ind_tbls; 1708 /* Standalone indirect tables. */ 1709 LIST_HEAD(stdl_ind_tables, mlx5_ind_table_obj) standalone_ind_tbls; 1710 /* Pointer to next element. */ 1711 rte_rwlock_t ind_tbls_lock; 1712 uint32_t refcnt; /**< Reference counter. */ 1713 /**< Verbs modify header action object. */ 1714 uint8_t ft_type; /**< Flow table type, Rx or Tx. */ 1715 uint8_t max_lro_msg_size; 1716 uint32_t link_speed_capa; /* Link speed capabilities. */ 1717 struct mlx5_xstats_ctrl xstats_ctrl; /* Extended stats control. */ 1718 struct mlx5_stats_ctrl stats_ctrl; /* Stats control. */ 1719 struct mlx5_port_config config; /* Port configuration. */ 1720 /* Context for Verbs allocator. */ 1721 int nl_socket_rdma; /* Netlink socket (NETLINK_RDMA). */ 1722 int nl_socket_route; /* Netlink socket (NETLINK_ROUTE). */ 1723 struct mlx5_nl_vlan_vmwa_context *vmwa_context; /* VLAN WA context. */ 1724 struct mlx5_hlist *mreg_cp_tbl; 1725 /* Hash table of Rx metadata register copy table. */ 1726 struct mlx5_mtr_config mtr_config; /* Meter configuration */ 1727 uint8_t mtr_sfx_reg; /* Meter prefix-suffix flow match REG_C. */ 1728 uint8_t mtr_color_reg; /* Meter color match REG_C. */ 1729 struct mlx5_legacy_flow_meters flow_meters; /* MTR list. */ 1730 struct mlx5_l3t_tbl *mtr_profile_tbl; /* Meter index lookup table. */ 1731 struct mlx5_flow_meter_profile *mtr_profile_arr; /* Profile array. */ 1732 struct mlx5_l3t_tbl *policy_idx_tbl; /* Policy index lookup table. */ 1733 struct mlx5_flow_meter_policy *mtr_policy_arr; /* Policy array. */ 1734 struct mlx5_l3t_tbl *mtr_idx_tbl; /* Meter index lookup table. */ 1735 struct mlx5_mtr_bulk mtr_bulk; /* Meter index mapping for HWS */ 1736 uint8_t skip_default_rss_reta; /* Skip configuration of default reta. */ 1737 uint8_t fdb_def_rule; /* Whether fdb jump to table 1 is configured. */ 1738 struct mlx5_mp_id mp_id; /* ID of a multi-process process */ 1739 LIST_HEAD(fdir, mlx5_fdir_flow) fdir_flows; /* fdir flows. */ 1740 rte_spinlock_t shared_act_sl; /* Shared actions spinlock. */ 1741 uint32_t rss_shared_actions; /* RSS shared actions. */ 1742 struct mlx5_devx_obj *q_counters; /* DevX queue counter object. */ 1743 uint32_t counter_set_id; /* Queue counter ID to set in DevX objects. */ 1744 uint32_t lag_affinity_idx; /* LAG mode queue 0 affinity starting. */ 1745 rte_spinlock_t flex_item_sl; /* Flex item list spinlock. */ 1746 struct mlx5_flex_item flex_item[MLX5_PORT_FLEX_ITEM_NUM]; 1747 /* Flex items have been created on the port. */ 1748 uint32_t flex_item_map; /* Map of allocated flex item elements. */ 1749 uint32_t nb_queue; /* HW steering queue number. */ 1750 struct mlx5_hws_cnt_pool *hws_cpool; /* HW steering's counter pool. */ 1751 #if defined(HAVE_IBV_FLOW_DV_SUPPORT) || !defined(HAVE_INFINIBAND_VERBS_H) 1752 /* Item template list. */ 1753 LIST_HEAD(flow_hw_itt, rte_flow_pattern_template) flow_hw_itt; 1754 /* Action template list. */ 1755 LIST_HEAD(flow_hw_at, rte_flow_actions_template) flow_hw_at; 1756 struct mlx5dr_context *dr_ctx; /**< HW steering DR context. */ 1757 /* HW steering queue polling mechanism job descriptor LIFO. */ 1758 uint32_t hws_strict_queue:1; 1759 /**< Whether all operations strictly happen on the same HWS queue. */ 1760 uint32_t hws_age_req:1; /**< Whether this port has AGE indexed pool. */ 1761 struct mlx5_hw_q *hw_q; 1762 /* HW steering rte flow table list header. */ 1763 LIST_HEAD(flow_hw_tbl, rte_flow_template_table) flow_hw_tbl; 1764 struct mlx5dr_action *hw_push_vlan[MLX5DR_TABLE_TYPE_MAX]; 1765 struct mlx5dr_action *hw_pop_vlan[MLX5DR_TABLE_TYPE_MAX]; 1766 struct mlx5dr_action **hw_vport; 1767 /* HW steering global drop action. */ 1768 struct mlx5dr_action *hw_drop[2]; 1769 /* HW steering global tag action. */ 1770 struct mlx5dr_action *hw_tag[2]; 1771 /* HW steering create ongoing rte flow table list header. */ 1772 LIST_HEAD(flow_hw_tbl_ongo, rte_flow_template_table) flow_hw_tbl_ongo; 1773 struct mlx5_indexed_pool *acts_ipool; /* Action data indexed pool. */ 1774 struct mlx5_aso_ct_pools_mng *ct_mng; 1775 /* Management data for ASO connection tracking. */ 1776 struct mlx5_aso_ct_pool *hws_ctpool; /* HW steering's CT pool. */ 1777 struct mlx5_aso_mtr_pool *hws_mpool; /* HW steering's Meter pool. */ 1778 struct mlx5_flow_hw_ctrl_rx *hw_ctrl_rx; 1779 /**< HW steering templates used to create control flow rules. */ 1780 #endif 1781 }; 1782 1783 #define PORT_ID(priv) ((priv)->dev_data->port_id) 1784 #define ETH_DEV(priv) (&rte_eth_devices[PORT_ID(priv)]) 1785 #define CTRL_QUEUE_ID(priv) ((priv)->nb_queue - 1) 1786 1787 struct rte_hairpin_peer_info { 1788 uint32_t qp_id; 1789 uint32_t vhca_id; 1790 uint16_t peer_q; 1791 uint16_t tx_explicit; 1792 uint16_t manual_bind; 1793 }; 1794 1795 #define BUF_SIZE 1024 1796 enum dr_dump_rec_type { 1797 DR_DUMP_REC_TYPE_PMD_PKT_REFORMAT = 4410, 1798 DR_DUMP_REC_TYPE_PMD_MODIFY_HDR = 4420, 1799 DR_DUMP_REC_TYPE_PMD_COUNTER = 4430, 1800 }; 1801 1802 /** 1803 * Indicates whether HW objects operations can be created by DevX. 1804 * 1805 * This function is used for both: 1806 * Before creation - deciding whether to create HW objects operations by DevX. 1807 * After creation - indicator if HW objects operations were created by DevX. 1808 * 1809 * @param sh 1810 * Pointer to shared device context. 1811 * 1812 * @return 1813 * True if HW objects were created by DevX, False otherwise. 1814 */ 1815 static inline bool 1816 mlx5_devx_obj_ops_en(struct mlx5_dev_ctx_shared *sh) 1817 { 1818 /* 1819 * When advanced DR API is available and DV flow is supported and 1820 * DevX is supported, HW objects operations are created by DevX. 1821 */ 1822 return (sh->cdev->config.devx && sh->config.dv_flow_en && 1823 sh->dev_cap.dest_tir); 1824 } 1825 1826 /* mlx5.c */ 1827 1828 int mlx5_getenv_int(const char *); 1829 int mlx5_proc_priv_init(struct rte_eth_dev *dev); 1830 void mlx5_proc_priv_uninit(struct rte_eth_dev *dev); 1831 int mlx5_udp_tunnel_port_add(struct rte_eth_dev *dev, 1832 struct rte_eth_udp_tunnel *udp_tunnel); 1833 uint16_t mlx5_eth_find_next(uint16_t port_id, struct rte_device *odev); 1834 int mlx5_dev_close(struct rte_eth_dev *dev); 1835 int mlx5_net_remove(struct mlx5_common_device *cdev); 1836 bool mlx5_is_hpf(struct rte_eth_dev *dev); 1837 bool mlx5_is_sf_repr(struct rte_eth_dev *dev); 1838 void mlx5_age_event_prepare(struct mlx5_dev_ctx_shared *sh); 1839 int mlx5_lwm_setup(struct mlx5_priv *priv); 1840 void mlx5_lwm_unset(struct mlx5_dev_ctx_shared *sh); 1841 1842 /* Macro to iterate over all valid ports for mlx5 driver. */ 1843 #define MLX5_ETH_FOREACH_DEV(port_id, dev) \ 1844 for (port_id = mlx5_eth_find_next(0, dev); \ 1845 port_id < RTE_MAX_ETHPORTS; \ 1846 port_id = mlx5_eth_find_next(port_id + 1, dev)) 1847 void mlx5_rt_timestamp_config(struct mlx5_dev_ctx_shared *sh, 1848 struct mlx5_hca_attr *hca_attr); 1849 struct mlx5_dev_ctx_shared * 1850 mlx5_alloc_shared_dev_ctx(const struct mlx5_dev_spawn_data *spawn, 1851 struct mlx5_kvargs_ctrl *mkvlist); 1852 void mlx5_free_shared_dev_ctx(struct mlx5_dev_ctx_shared *sh); 1853 int mlx5_dev_ctx_shared_mempool_subscribe(struct rte_eth_dev *dev); 1854 void mlx5_free_table_hash_list(struct mlx5_priv *priv); 1855 int mlx5_alloc_table_hash_list(struct mlx5_priv *priv); 1856 void mlx5_set_min_inline(struct mlx5_priv *priv); 1857 void mlx5_set_metadata_mask(struct rte_eth_dev *dev); 1858 int mlx5_probe_again_args_validate(struct mlx5_common_device *cdev, 1859 struct mlx5_kvargs_ctrl *mkvlist); 1860 int mlx5_port_args_config(struct mlx5_priv *priv, 1861 struct mlx5_kvargs_ctrl *mkvlist, 1862 struct mlx5_port_config *config); 1863 void mlx5_port_args_set_used(const char *name, uint16_t port_id, 1864 struct mlx5_kvargs_ctrl *mkvlist); 1865 bool mlx5_flex_parser_ecpri_exist(struct rte_eth_dev *dev); 1866 int mlx5_flex_parser_ecpri_alloc(struct rte_eth_dev *dev); 1867 void mlx5_flow_counter_mode_config(struct rte_eth_dev *dev); 1868 int mlx5_flow_aso_age_mng_init(struct mlx5_dev_ctx_shared *sh); 1869 int mlx5_aso_flow_mtrs_mng_init(struct mlx5_dev_ctx_shared *sh); 1870 int mlx5_flow_aso_ct_mng_init(struct mlx5_dev_ctx_shared *sh); 1871 1872 /* mlx5_ethdev.c */ 1873 1874 int mlx5_dev_configure(struct rte_eth_dev *dev); 1875 int mlx5_representor_info_get(struct rte_eth_dev *dev, 1876 struct rte_eth_representor_info *info); 1877 #define MLX5_REPRESENTOR_ID(pf, type, repr) \ 1878 (((pf) << 14) + ((type) << 12) + ((repr) & 0xfff)) 1879 #define MLX5_REPRESENTOR_REPR(repr_id) \ 1880 ((repr_id) & 0xfff) 1881 #define MLX5_REPRESENTOR_TYPE(repr_id) \ 1882 (((repr_id) >> 12) & 3) 1883 uint16_t mlx5_representor_id_encode(const struct mlx5_switch_info *info, 1884 enum rte_eth_representor_type hpf_type); 1885 int mlx5_dev_infos_get(struct rte_eth_dev *dev, struct rte_eth_dev_info *info); 1886 int mlx5_fw_version_get(struct rte_eth_dev *dev, char *fw_ver, size_t fw_size); 1887 const uint32_t *mlx5_dev_supported_ptypes_get(struct rte_eth_dev *dev); 1888 int mlx5_dev_set_mtu(struct rte_eth_dev *dev, uint16_t mtu); 1889 int mlx5_hairpin_cap_get(struct rte_eth_dev *dev, 1890 struct rte_eth_hairpin_cap *cap); 1891 eth_rx_burst_t mlx5_select_rx_function(struct rte_eth_dev *dev); 1892 struct mlx5_priv *mlx5_port_to_eswitch_info(uint16_t port, bool valid); 1893 struct mlx5_priv *mlx5_dev_to_eswitch_info(struct rte_eth_dev *dev); 1894 int mlx5_dev_configure_rss_reta(struct rte_eth_dev *dev); 1895 1896 /* mlx5_ethdev_os.c */ 1897 1898 int mlx5_get_ifname(const struct rte_eth_dev *dev, 1899 char (*ifname)[MLX5_NAMESIZE]); 1900 unsigned int mlx5_ifindex(const struct rte_eth_dev *dev); 1901 int mlx5_get_mac(struct rte_eth_dev *dev, uint8_t (*mac)[RTE_ETHER_ADDR_LEN]); 1902 int mlx5_get_mtu(struct rte_eth_dev *dev, uint16_t *mtu); 1903 int mlx5_set_mtu(struct rte_eth_dev *dev, uint16_t mtu); 1904 int mlx5_read_clock(struct rte_eth_dev *dev, uint64_t *clock); 1905 int mlx5_link_update(struct rte_eth_dev *dev, int wait_to_complete); 1906 int mlx5_dev_get_flow_ctrl(struct rte_eth_dev *dev, 1907 struct rte_eth_fc_conf *fc_conf); 1908 int mlx5_dev_set_flow_ctrl(struct rte_eth_dev *dev, 1909 struct rte_eth_fc_conf *fc_conf); 1910 void mlx5_dev_interrupt_handler(void *arg); 1911 void mlx5_dev_interrupt_handler_devx(void *arg); 1912 void mlx5_dev_interrupt_handler_nl(void *arg); 1913 int mlx5_set_link_down(struct rte_eth_dev *dev); 1914 int mlx5_set_link_up(struct rte_eth_dev *dev); 1915 int mlx5_is_removed(struct rte_eth_dev *dev); 1916 int mlx5_sysfs_switch_info(unsigned int ifindex, 1917 struct mlx5_switch_info *info); 1918 void mlx5_translate_port_name(const char *port_name_in, 1919 struct mlx5_switch_info *port_info_out); 1920 int mlx5_sysfs_bond_info(unsigned int pf_ifindex, unsigned int *ifindex, 1921 char *ifname); 1922 int mlx5_get_module_info(struct rte_eth_dev *dev, 1923 struct rte_eth_dev_module_info *modinfo); 1924 int mlx5_get_module_eeprom(struct rte_eth_dev *dev, 1925 struct rte_dev_eeprom_info *info); 1926 int mlx5_os_read_dev_stat(struct mlx5_priv *priv, 1927 const char *ctr_name, uint64_t *stat); 1928 int mlx5_os_read_dev_counters(struct rte_eth_dev *dev, uint64_t *stats); 1929 int mlx5_os_get_stats_n(struct rte_eth_dev *dev); 1930 void mlx5_os_stats_init(struct rte_eth_dev *dev); 1931 int mlx5_get_flag_dropless_rq(struct rte_eth_dev *dev); 1932 1933 /* mlx5_mac.c */ 1934 1935 void mlx5_mac_addr_remove(struct rte_eth_dev *dev, uint32_t index); 1936 int mlx5_mac_addr_add(struct rte_eth_dev *dev, struct rte_ether_addr *mac, 1937 uint32_t index, uint32_t vmdq); 1938 int mlx5_mac_addr_set(struct rte_eth_dev *dev, struct rte_ether_addr *mac_addr); 1939 int mlx5_set_mc_addr_list(struct rte_eth_dev *dev, 1940 struct rte_ether_addr *mc_addr_set, 1941 uint32_t nb_mc_addr); 1942 1943 /* mlx5_rss.c */ 1944 1945 int mlx5_rss_hash_update(struct rte_eth_dev *dev, 1946 struct rte_eth_rss_conf *rss_conf); 1947 int mlx5_rss_hash_conf_get(struct rte_eth_dev *dev, 1948 struct rte_eth_rss_conf *rss_conf); 1949 int mlx5_rss_reta_index_resize(struct rte_eth_dev *dev, unsigned int reta_size); 1950 int mlx5_dev_rss_reta_query(struct rte_eth_dev *dev, 1951 struct rte_eth_rss_reta_entry64 *reta_conf, 1952 uint16_t reta_size); 1953 int mlx5_dev_rss_reta_update(struct rte_eth_dev *dev, 1954 struct rte_eth_rss_reta_entry64 *reta_conf, 1955 uint16_t reta_size); 1956 1957 /* mlx5_rxmode.c */ 1958 1959 int mlx5_promiscuous_enable(struct rte_eth_dev *dev); 1960 int mlx5_promiscuous_disable(struct rte_eth_dev *dev); 1961 int mlx5_allmulticast_enable(struct rte_eth_dev *dev); 1962 int mlx5_allmulticast_disable(struct rte_eth_dev *dev); 1963 1964 /* mlx5_stats.c */ 1965 1966 int mlx5_stats_get(struct rte_eth_dev *dev, struct rte_eth_stats *stats); 1967 int mlx5_stats_reset(struct rte_eth_dev *dev); 1968 int mlx5_xstats_get(struct rte_eth_dev *dev, struct rte_eth_xstat *stats, 1969 unsigned int n); 1970 int mlx5_xstats_reset(struct rte_eth_dev *dev); 1971 int mlx5_xstats_get_names(struct rte_eth_dev *dev __rte_unused, 1972 struct rte_eth_xstat_name *xstats_names, 1973 unsigned int n); 1974 1975 /* mlx5_vlan.c */ 1976 1977 int mlx5_vlan_filter_set(struct rte_eth_dev *dev, uint16_t vlan_id, int on); 1978 void mlx5_vlan_strip_queue_set(struct rte_eth_dev *dev, uint16_t queue, int on); 1979 int mlx5_vlan_offload_set(struct rte_eth_dev *dev, int mask); 1980 1981 /* mlx5_vlan_os.c */ 1982 1983 void mlx5_vlan_vmwa_exit(void *ctx); 1984 void mlx5_vlan_vmwa_release(struct rte_eth_dev *dev, 1985 struct mlx5_vf_vlan *vf_vlan); 1986 void mlx5_vlan_vmwa_acquire(struct rte_eth_dev *dev, 1987 struct mlx5_vf_vlan *vf_vlan); 1988 void *mlx5_vlan_vmwa_init(struct rte_eth_dev *dev, uint32_t ifindex); 1989 1990 /* mlx5_trigger.c */ 1991 1992 int mlx5_dev_start(struct rte_eth_dev *dev); 1993 int mlx5_dev_stop(struct rte_eth_dev *dev); 1994 int mlx5_traffic_enable(struct rte_eth_dev *dev); 1995 void mlx5_traffic_disable(struct rte_eth_dev *dev); 1996 int mlx5_traffic_restart(struct rte_eth_dev *dev); 1997 int mlx5_hairpin_queue_peer_update(struct rte_eth_dev *dev, uint16_t peer_queue, 1998 struct rte_hairpin_peer_info *current_info, 1999 struct rte_hairpin_peer_info *peer_info, 2000 uint32_t direction); 2001 int mlx5_hairpin_queue_peer_bind(struct rte_eth_dev *dev, uint16_t cur_queue, 2002 struct rte_hairpin_peer_info *peer_info, 2003 uint32_t direction); 2004 int mlx5_hairpin_queue_peer_unbind(struct rte_eth_dev *dev, uint16_t cur_queue, 2005 uint32_t direction); 2006 int mlx5_hairpin_bind(struct rte_eth_dev *dev, uint16_t rx_port); 2007 int mlx5_hairpin_unbind(struct rte_eth_dev *dev, uint16_t rx_port); 2008 int mlx5_hairpin_get_peer_ports(struct rte_eth_dev *dev, uint16_t *peer_ports, 2009 size_t len, uint32_t direction); 2010 2011 /* mlx5_flow.c */ 2012 2013 int mlx5_flow_discover_mreg_c(struct rte_eth_dev *eth_dev); 2014 bool mlx5_flow_ext_mreg_supported(struct rte_eth_dev *dev); 2015 void mlx5_flow_print(struct rte_flow *flow); 2016 int mlx5_flow_validate(struct rte_eth_dev *dev, 2017 const struct rte_flow_attr *attr, 2018 const struct rte_flow_item items[], 2019 const struct rte_flow_action actions[], 2020 struct rte_flow_error *error); 2021 struct rte_flow *mlx5_flow_create(struct rte_eth_dev *dev, 2022 const struct rte_flow_attr *attr, 2023 const struct rte_flow_item items[], 2024 const struct rte_flow_action actions[], 2025 struct rte_flow_error *error); 2026 int mlx5_flow_destroy(struct rte_eth_dev *dev, struct rte_flow *flow, 2027 struct rte_flow_error *error); 2028 void mlx5_flow_list_flush(struct rte_eth_dev *dev, enum mlx5_flow_type type, 2029 bool active); 2030 int mlx5_flow_flush(struct rte_eth_dev *dev, struct rte_flow_error *error); 2031 int mlx5_flow_query(struct rte_eth_dev *dev, struct rte_flow *flow, 2032 const struct rte_flow_action *action, void *data, 2033 struct rte_flow_error *error); 2034 int mlx5_flow_isolate(struct rte_eth_dev *dev, int enable, 2035 struct rte_flow_error *error); 2036 int mlx5_flow_ops_get(struct rte_eth_dev *dev, const struct rte_flow_ops **ops); 2037 int mlx5_flow_start_default(struct rte_eth_dev *dev); 2038 void mlx5_flow_stop_default(struct rte_eth_dev *dev); 2039 int mlx5_flow_verify(struct rte_eth_dev *dev); 2040 int mlx5_ctrl_flow_source_queue(struct rte_eth_dev *dev, uint32_t sq_num); 2041 int mlx5_ctrl_flow_vlan(struct rte_eth_dev *dev, 2042 struct rte_flow_item_eth *eth_spec, 2043 struct rte_flow_item_eth *eth_mask, 2044 struct rte_flow_item_vlan *vlan_spec, 2045 struct rte_flow_item_vlan *vlan_mask); 2046 int mlx5_ctrl_flow(struct rte_eth_dev *dev, 2047 struct rte_flow_item_eth *eth_spec, 2048 struct rte_flow_item_eth *eth_mask); 2049 int mlx5_flow_lacp_miss(struct rte_eth_dev *dev); 2050 struct rte_flow *mlx5_flow_create_esw_table_zero_flow(struct rte_eth_dev *dev); 2051 uint32_t mlx5_flow_create_devx_sq_miss_flow(struct rte_eth_dev *dev, 2052 uint32_t sq_num); 2053 void mlx5_flow_async_pool_query_handle(struct mlx5_dev_ctx_shared *sh, 2054 uint64_t async_id, int status); 2055 void mlx5_set_query_alarm(struct mlx5_dev_ctx_shared *sh); 2056 void mlx5_flow_query_alarm(void *arg); 2057 uint32_t mlx5_counter_alloc(struct rte_eth_dev *dev); 2058 void mlx5_counter_free(struct rte_eth_dev *dev, uint32_t cnt); 2059 int mlx5_counter_query(struct rte_eth_dev *dev, uint32_t cnt, 2060 bool clear, uint64_t *pkts, uint64_t *bytes, void **action); 2061 int mlx5_flow_dev_dump(struct rte_eth_dev *dev, struct rte_flow *flow, 2062 FILE *file, struct rte_flow_error *error); 2063 int save_dump_file(const unsigned char *data, uint32_t size, 2064 uint32_t type, uint64_t id, void *arg, FILE *file); 2065 int mlx5_flow_query_counter(struct rte_eth_dev *dev, struct rte_flow *flow, 2066 struct rte_flow_query_count *count, struct rte_flow_error *error); 2067 #ifdef HAVE_IBV_FLOW_DV_SUPPORT 2068 int mlx5_flow_dev_dump_ipool(struct rte_eth_dev *dev, struct rte_flow *flow, 2069 FILE *file, struct rte_flow_error *error); 2070 #endif 2071 void mlx5_flow_rxq_dynf_metadata_set(struct rte_eth_dev *dev); 2072 int mlx5_flow_get_aged_flows(struct rte_eth_dev *dev, void **contexts, 2073 uint32_t nb_contexts, struct rte_flow_error *error); 2074 int mlx5_validate_action_ct(struct rte_eth_dev *dev, 2075 const struct rte_flow_action_conntrack *conntrack, 2076 struct rte_flow_error *error); 2077 2078 int mlx5_flow_get_q_aged_flows(struct rte_eth_dev *dev, uint32_t queue_id, 2079 void **contexts, uint32_t nb_contexts, 2080 struct rte_flow_error *error); 2081 2082 /* mlx5_mp_os.c */ 2083 2084 int mlx5_mp_os_primary_handle(const struct rte_mp_msg *mp_msg, 2085 const void *peer); 2086 int mlx5_mp_os_secondary_handle(const struct rte_mp_msg *mp_msg, 2087 const void *peer); 2088 void mlx5_mp_os_req_start_rxtx(struct rte_eth_dev *dev); 2089 void mlx5_mp_os_req_stop_rxtx(struct rte_eth_dev *dev); 2090 int mlx5_mp_os_req_queue_control(struct rte_eth_dev *dev, uint16_t queue_id, 2091 enum mlx5_mp_req_type req_type); 2092 2093 /* mlx5_socket.c */ 2094 2095 int mlx5_pmd_socket_init(void); 2096 void mlx5_pmd_socket_uninit(void); 2097 2098 /* mlx5_flow_meter.c */ 2099 2100 int mlx5_flow_meter_init(struct rte_eth_dev *dev, 2101 uint32_t nb_meters, 2102 uint32_t nb_meter_profiles, 2103 uint32_t nb_meter_policies, 2104 uint32_t nb_queues); 2105 void mlx5_flow_meter_uninit(struct rte_eth_dev *dev); 2106 int mlx5_flow_meter_ops_get(struct rte_eth_dev *dev, void *arg); 2107 struct mlx5_flow_meter_info *mlx5_flow_meter_find(struct mlx5_priv *priv, 2108 uint32_t meter_id, uint32_t *mtr_idx); 2109 struct mlx5_flow_meter_info * 2110 flow_dv_meter_find_by_idx(struct mlx5_priv *priv, uint32_t idx); 2111 int mlx5_flow_meter_attach(struct mlx5_priv *priv, 2112 struct mlx5_flow_meter_info *fm, 2113 const struct rte_flow_attr *attr, 2114 struct rte_flow_error *error); 2115 void mlx5_flow_meter_detach(struct mlx5_priv *priv, 2116 struct mlx5_flow_meter_info *fm); 2117 struct mlx5_flow_meter_policy *mlx5_flow_meter_policy_find 2118 (struct rte_eth_dev *dev, 2119 uint32_t policy_id, 2120 uint32_t *policy_idx); 2121 struct mlx5_flow_meter_info * 2122 mlx5_flow_meter_hierarchy_next_meter(struct mlx5_priv *priv, 2123 struct mlx5_flow_meter_policy *policy, 2124 uint32_t *mtr_idx); 2125 struct mlx5_flow_meter_policy * 2126 mlx5_flow_meter_hierarchy_get_final_policy(struct rte_eth_dev *dev, 2127 struct mlx5_flow_meter_policy *policy); 2128 int mlx5_flow_meter_flush(struct rte_eth_dev *dev, 2129 struct rte_mtr_error *error); 2130 void mlx5_flow_meter_rxq_flush(struct rte_eth_dev *dev); 2131 2132 /* mlx5_os.c */ 2133 2134 struct rte_pci_driver; 2135 int mlx5_os_capabilities_prepare(struct mlx5_dev_ctx_shared *sh); 2136 void mlx5_os_free_shared_dr(struct mlx5_priv *priv); 2137 int mlx5_os_net_probe(struct mlx5_common_device *cdev, 2138 struct mlx5_kvargs_ctrl *mkvlist); 2139 void mlx5_os_dev_shared_handler_install(struct mlx5_dev_ctx_shared *sh); 2140 void mlx5_os_dev_shared_handler_uninstall(struct mlx5_dev_ctx_shared *sh); 2141 void mlx5_os_mac_addr_remove(struct rte_eth_dev *dev, uint32_t index); 2142 int mlx5_os_mac_addr_add(struct rte_eth_dev *dev, struct rte_ether_addr *mac, 2143 uint32_t index); 2144 int mlx5_os_vf_mac_addr_modify(struct mlx5_priv *priv, unsigned int iface_idx, 2145 struct rte_ether_addr *mac_addr, 2146 int vf_index); 2147 int mlx5_os_set_promisc(struct rte_eth_dev *dev, int enable); 2148 int mlx5_os_set_allmulti(struct rte_eth_dev *dev, int enable); 2149 int mlx5_os_set_nonblock_channel_fd(int fd); 2150 void mlx5_os_mac_addr_flush(struct rte_eth_dev *dev); 2151 void mlx5_os_net_cleanup(void); 2152 2153 /* mlx5_txpp.c */ 2154 2155 int mlx5_txpp_start(struct rte_eth_dev *dev); 2156 void mlx5_txpp_stop(struct rte_eth_dev *dev); 2157 int mlx5_txpp_read_clock(struct rte_eth_dev *dev, uint64_t *timestamp); 2158 int mlx5_txpp_xstats_get(struct rte_eth_dev *dev, 2159 struct rte_eth_xstat *stats, 2160 unsigned int n, unsigned int n_used); 2161 int mlx5_txpp_xstats_reset(struct rte_eth_dev *dev); 2162 int mlx5_txpp_xstats_get_names(struct rte_eth_dev *dev, 2163 struct rte_eth_xstat_name *xstats_names, 2164 unsigned int n, unsigned int n_used); 2165 void mlx5_txpp_interrupt_handler(void *cb_arg); 2166 2167 /* mlx5_rxtx.c */ 2168 2169 eth_tx_burst_t mlx5_select_tx_function(struct rte_eth_dev *dev); 2170 2171 /* mlx5_flow_aso.c */ 2172 2173 int mlx5_aso_mtr_queue_init(struct mlx5_dev_ctx_shared *sh, 2174 struct mlx5_aso_mtr_pool *hws_pool, 2175 struct mlx5_aso_mtr_pools_mng *pool_mng, 2176 uint32_t nb_queues); 2177 void mlx5_aso_mtr_queue_uninit(struct mlx5_dev_ctx_shared *sh, 2178 struct mlx5_aso_mtr_pool *hws_pool, 2179 struct mlx5_aso_mtr_pools_mng *pool_mng); 2180 int mlx5_aso_queue_init(struct mlx5_dev_ctx_shared *sh, 2181 enum mlx5_access_aso_opc_mod aso_opc_mode, 2182 uint32_t nb_queues); 2183 int mlx5_aso_flow_hit_queue_poll_start(struct mlx5_dev_ctx_shared *sh); 2184 int mlx5_aso_flow_hit_queue_poll_stop(struct mlx5_dev_ctx_shared *sh); 2185 void mlx5_aso_queue_uninit(struct mlx5_dev_ctx_shared *sh, 2186 enum mlx5_access_aso_opc_mod aso_opc_mod); 2187 int mlx5_aso_meter_update_by_wqe(struct mlx5_dev_ctx_shared *sh, uint32_t queue, 2188 struct mlx5_aso_mtr *mtr, struct mlx5_mtr_bulk *bulk, 2189 void *user_data, bool push); 2190 int mlx5_aso_mtr_wait(struct mlx5_dev_ctx_shared *sh, uint32_t queue, 2191 struct mlx5_aso_mtr *mtr); 2192 int mlx5_aso_ct_update_by_wqe(struct mlx5_dev_ctx_shared *sh, uint32_t queue, 2193 struct mlx5_aso_ct_action *ct, 2194 const struct rte_flow_action_conntrack *profile, 2195 void *user_data, 2196 bool push); 2197 int mlx5_aso_ct_wait_ready(struct mlx5_dev_ctx_shared *sh, uint32_t queue, 2198 struct mlx5_aso_ct_action *ct); 2199 int mlx5_aso_ct_query_by_wqe(struct mlx5_dev_ctx_shared *sh, uint32_t queue, 2200 struct mlx5_aso_ct_action *ct, 2201 struct rte_flow_action_conntrack *profile, 2202 void *user_data, bool push); 2203 int mlx5_aso_ct_available(struct mlx5_dev_ctx_shared *sh, uint32_t queue, 2204 struct mlx5_aso_ct_action *ct); 2205 uint32_t 2206 mlx5_get_supported_sw_parsing_offloads(const struct mlx5_hca_attr *attr); 2207 uint32_t 2208 mlx5_get_supported_tunneling_offloads(const struct mlx5_hca_attr *attr); 2209 2210 void mlx5_aso_ct_obj_analyze(struct rte_flow_action_conntrack *profile, 2211 char *wdata); 2212 void mlx5_aso_push_wqe(struct mlx5_dev_ctx_shared *sh, 2213 struct mlx5_aso_sq *sq); 2214 int mlx5_aso_pull_completion(struct mlx5_aso_sq *sq, 2215 struct rte_flow_op_result res[], 2216 uint16_t n_res); 2217 int mlx5_aso_cnt_queue_init(struct mlx5_dev_ctx_shared *sh); 2218 void mlx5_aso_cnt_queue_uninit(struct mlx5_dev_ctx_shared *sh); 2219 int mlx5_aso_cnt_query(struct mlx5_dev_ctx_shared *sh, 2220 struct mlx5_hws_cnt_pool *cpool); 2221 int mlx5_aso_ct_queue_init(struct mlx5_dev_ctx_shared *sh, 2222 struct mlx5_aso_ct_pools_mng *ct_mng, 2223 uint32_t nb_queues); 2224 int mlx5_aso_ct_queue_uninit(struct mlx5_dev_ctx_shared *sh, 2225 struct mlx5_aso_ct_pools_mng *ct_mng); 2226 2227 /* mlx5_flow_flex.c */ 2228 2229 struct rte_flow_item_flex_handle * 2230 flow_dv_item_create(struct rte_eth_dev *dev, 2231 const struct rte_flow_item_flex_conf *conf, 2232 struct rte_flow_error *error); 2233 int flow_dv_item_release(struct rte_eth_dev *dev, 2234 const struct rte_flow_item_flex_handle *flex_handle, 2235 struct rte_flow_error *error); 2236 int mlx5_flex_item_port_init(struct rte_eth_dev *dev); 2237 void mlx5_flex_item_port_cleanup(struct rte_eth_dev *dev); 2238 void mlx5_flex_flow_translate_item(struct rte_eth_dev *dev, void *matcher, 2239 void *key, const struct rte_flow_item *item, 2240 bool is_inner); 2241 int mlx5_flex_acquire_index(struct rte_eth_dev *dev, 2242 struct rte_flow_item_flex_handle *handle, 2243 bool acquire); 2244 int mlx5_flex_release_index(struct rte_eth_dev *dev, int index); 2245 2246 /* Flex parser list callbacks. */ 2247 struct mlx5_list_entry *mlx5_flex_parser_create_cb(void *list_ctx, void *ctx); 2248 int mlx5_flex_parser_match_cb(void *list_ctx, 2249 struct mlx5_list_entry *iter, void *ctx); 2250 void mlx5_flex_parser_remove_cb(void *list_ctx, struct mlx5_list_entry *entry); 2251 struct mlx5_list_entry *mlx5_flex_parser_clone_cb(void *list_ctx, 2252 struct mlx5_list_entry *entry, 2253 void *ctx); 2254 void mlx5_flex_parser_clone_free_cb(void *tool_ctx, 2255 struct mlx5_list_entry *entry); 2256 #endif /* RTE_PMD_MLX5_H_ */ 2257