1 /* SPDX-License-Identifier: BSD-3-Clause 2 * Copyright 2015 6WIND S.A. 3 * Copyright 2015 Mellanox Technologies, Ltd 4 */ 5 6 #ifndef RTE_PMD_MLX5_H_ 7 #define RTE_PMD_MLX5_H_ 8 9 #include <stddef.h> 10 #include <stdint.h> 11 #include <limits.h> 12 #include <net/if.h> 13 #include <netinet/in.h> 14 #include <sys/queue.h> 15 16 /* Verbs header. */ 17 /* ISO C doesn't support unnamed structs/unions, disabling -pedantic. */ 18 #ifdef PEDANTIC 19 #pragma GCC diagnostic ignored "-Wpedantic" 20 #endif 21 #include <infiniband/verbs.h> 22 #ifdef PEDANTIC 23 #pragma GCC diagnostic error "-Wpedantic" 24 #endif 25 26 #include <rte_pci.h> 27 #include <rte_ether.h> 28 #include <rte_ethdev_driver.h> 29 #include <rte_rwlock.h> 30 #include <rte_interrupts.h> 31 #include <rte_errno.h> 32 #include <rte_flow.h> 33 34 #include "mlx5_utils.h" 35 #include "mlx5_mr.h" 36 #include "mlx5_rxtx.h" 37 #include "mlx5_autoconf.h" 38 #include "mlx5_defs.h" 39 40 enum { 41 PCI_VENDOR_ID_MELLANOX = 0x15b3, 42 }; 43 44 enum { 45 PCI_DEVICE_ID_MELLANOX_CONNECTX4 = 0x1013, 46 PCI_DEVICE_ID_MELLANOX_CONNECTX4VF = 0x1014, 47 PCI_DEVICE_ID_MELLANOX_CONNECTX4LX = 0x1015, 48 PCI_DEVICE_ID_MELLANOX_CONNECTX4LXVF = 0x1016, 49 PCI_DEVICE_ID_MELLANOX_CONNECTX5 = 0x1017, 50 PCI_DEVICE_ID_MELLANOX_CONNECTX5VF = 0x1018, 51 PCI_DEVICE_ID_MELLANOX_CONNECTX5EX = 0x1019, 52 PCI_DEVICE_ID_MELLANOX_CONNECTX5EXVF = 0x101a, 53 PCI_DEVICE_ID_MELLANOX_CONNECTX5BF = 0xa2d2, 54 PCI_DEVICE_ID_MELLANOX_CONNECTX5BFVF = 0xa2d3, 55 PCI_DEVICE_ID_MELLANOX_CONNECTX6 = 0x101b, 56 PCI_DEVICE_ID_MELLANOX_CONNECTX6VF = 0x101c, 57 }; 58 59 /** Switch information returned by mlx5_nl_switch_info(). */ 60 struct mlx5_switch_info { 61 uint32_t master:1; /**< Master device. */ 62 uint32_t representor:1; /**< Representor device. */ 63 uint32_t port_name_new:1; /**< Rep. port name is in new format. */ 64 int32_t port_name; /**< Representor port name. */ 65 uint64_t switch_id; /**< Switch identifier. */ 66 }; 67 68 LIST_HEAD(mlx5_dev_list, mlx5_priv); 69 70 /* Shared memory between primary and secondary processes. */ 71 struct mlx5_shared_data { 72 struct mlx5_dev_list mem_event_cb_list; 73 rte_rwlock_t mem_event_rwlock; 74 }; 75 76 extern struct mlx5_shared_data *mlx5_shared_data; 77 78 struct mlx5_counter_ctrl { 79 /* Name of the counter. */ 80 char dpdk_name[RTE_ETH_XSTATS_NAME_SIZE]; 81 /* Name of the counter on the device table. */ 82 char ctr_name[RTE_ETH_XSTATS_NAME_SIZE]; 83 uint32_t ib:1; /**< Nonzero for IB counters. */ 84 }; 85 86 struct mlx5_xstats_ctrl { 87 /* Number of device stats. */ 88 uint16_t stats_n; 89 /* Number of device stats identified by PMD. */ 90 uint16_t mlx5_stats_n; 91 /* Index in the device counters table. */ 92 uint16_t dev_table_idx[MLX5_MAX_XSTATS]; 93 uint64_t base[MLX5_MAX_XSTATS]; 94 struct mlx5_counter_ctrl info[MLX5_MAX_XSTATS]; 95 }; 96 97 struct mlx5_stats_ctrl { 98 /* Base for imissed counter. */ 99 uint64_t imissed_base; 100 }; 101 102 /* devx counter object */ 103 struct mlx5_devx_counter_set { 104 struct mlx5dv_devx_obj *obj; 105 int id; /* Flow counter ID */ 106 }; 107 108 /* Flow list . */ 109 TAILQ_HEAD(mlx5_flows, rte_flow); 110 111 /* Default PMD specific parameter value. */ 112 #define MLX5_ARG_UNSET (-1) 113 114 /* 115 * Device configuration structure. 116 * 117 * Merged configuration from: 118 * 119 * - Device capabilities, 120 * - User device parameters disabled features. 121 */ 122 struct mlx5_dev_config { 123 unsigned int hw_csum:1; /* Checksum offload is supported. */ 124 unsigned int hw_vlan_strip:1; /* VLAN stripping is supported. */ 125 unsigned int hw_fcs_strip:1; /* FCS stripping is supported. */ 126 unsigned int hw_padding:1; /* End alignment padding is supported. */ 127 unsigned int vf:1; /* This is a VF. */ 128 unsigned int tunnel_en:1; 129 /* Whether tunnel stateless offloads are supported. */ 130 unsigned int mpls_en:1; /* MPLS over GRE/UDP is enabled. */ 131 unsigned int cqe_comp:1; /* CQE compression is enabled. */ 132 unsigned int cqe_pad:1; /* CQE padding is enabled. */ 133 unsigned int tso:1; /* Whether TSO is supported. */ 134 unsigned int tx_vec_en:1; /* Tx vector is enabled. */ 135 unsigned int rx_vec_en:1; /* Rx vector is enabled. */ 136 unsigned int mpw_hdr_dseg:1; /* Enable DSEGs in the title WQEBB. */ 137 unsigned int l3_vxlan_en:1; /* Enable L3 VXLAN flow creation. */ 138 unsigned int vf_nl_en:1; /* Enable Netlink requests in VF mode. */ 139 unsigned int dv_flow_en:1; /* Enable DV flow. */ 140 unsigned int swp:1; /* Tx generic tunnel checksum and TSO offload. */ 141 unsigned int devx:1; /* Whether devx interface is available or not. */ 142 struct { 143 unsigned int enabled:1; /* Whether MPRQ is enabled. */ 144 unsigned int stride_num_n; /* Number of strides. */ 145 unsigned int min_stride_size_n; /* Min size of a stride. */ 146 unsigned int max_stride_size_n; /* Max size of a stride. */ 147 unsigned int max_memcpy_len; 148 /* Maximum packet size to memcpy Rx packets. */ 149 unsigned int min_rxqs_num; 150 /* Rx queue count threshold to enable MPRQ. */ 151 } mprq; /* Configurations for Multi-Packet RQ. */ 152 int mps; /* Multi-packet send supported mode. */ 153 unsigned int flow_prio; /* Number of flow priorities. */ 154 unsigned int tso_max_payload_sz; /* Maximum TCP payload for TSO. */ 155 unsigned int ind_table_max_size; /* Maximum indirection table size. */ 156 int txq_inline; /* Maximum packet size for inlining. */ 157 int txqs_inline; /* Queue number threshold for inlining. */ 158 int txqs_vec; /* Queue number threshold for vectorized Tx. */ 159 int inline_max_packet_sz; /* Max packet size for inlining. */ 160 }; 161 162 /** 163 * Type of objet being allocated. 164 */ 165 enum mlx5_verbs_alloc_type { 166 MLX5_VERBS_ALLOC_TYPE_NONE, 167 MLX5_VERBS_ALLOC_TYPE_TX_QUEUE, 168 MLX5_VERBS_ALLOC_TYPE_RX_QUEUE, 169 }; 170 171 /** 172 * Verbs allocator needs a context to know in the callback which kind of 173 * resources it is allocating. 174 */ 175 struct mlx5_verbs_alloc_ctx { 176 enum mlx5_verbs_alloc_type type; /* Kind of object being allocated. */ 177 const void *obj; /* Pointer to the DPDK object. */ 178 }; 179 180 LIST_HEAD(mlx5_mr_list, mlx5_mr); 181 182 /* Flow drop context necessary due to Verbs API. */ 183 struct mlx5_drop { 184 struct mlx5_hrxq *hrxq; /* Hash Rx queue queue. */ 185 struct mlx5_rxq_ibv *rxq; /* Verbs Rx queue. */ 186 }; 187 188 struct mlx5_flow_tcf_context; 189 190 /* Per port data of shared IB device. */ 191 struct mlx5_ibv_shared_port { 192 uint32_t ih_port_id; 193 /* 194 * Interrupt handler port_id. Used by shared interrupt 195 * handler to find the corresponding rte_eth device 196 * by IB port index. If value is equal or greater 197 * RTE_MAX_ETHPORTS it means there is no subhandler 198 * installed for specified IB port index. 199 */ 200 }; 201 202 /* 203 * Shared Infiniband device context for Master/Representors 204 * which belong to same IB device with multiple IB ports. 205 **/ 206 struct mlx5_ibv_shared { 207 LIST_ENTRY(mlx5_ibv_shared) next; 208 uint32_t refcnt; 209 uint32_t devx:1; /* Opened with DV. */ 210 uint32_t max_port; /* Maximal IB device port index. */ 211 struct ibv_context *ctx; /* Verbs/DV context. */ 212 struct ibv_pd *pd; /* Protection Domain. */ 213 char ibdev_name[IBV_SYSFS_NAME_MAX]; /* IB device name. */ 214 char ibdev_path[IBV_SYSFS_PATH_MAX]; /* IB device path for secondary */ 215 struct ibv_device_attr_ex device_attr; /* Device properties. */ 216 pthread_mutex_t intr_mutex; /* Interrupt config mutex. */ 217 uint32_t intr_cnt; /* Interrupt handler reference counter. */ 218 struct rte_intr_handle intr_handle; /* Interrupt handler for device. */ 219 struct mlx5_ibv_shared_port port[]; /* per device port data array. */ 220 }; 221 222 struct mlx5_priv { 223 LIST_ENTRY(mlx5_priv) mem_event_cb; 224 /**< Called by memory event callback. */ 225 struct rte_eth_dev_data *dev_data; /* Pointer to device data. */ 226 struct mlx5_ibv_shared *sh; /* Shared IB device context. */ 227 uint32_t ibv_port; /* IB device port number. */ 228 struct ether_addr mac[MLX5_MAX_MAC_ADDRESSES]; /* MAC addresses. */ 229 BITFIELD_DECLARE(mac_own, uint64_t, MLX5_MAX_MAC_ADDRESSES); 230 /* Bit-field of MAC addresses owned by the PMD. */ 231 uint16_t vlan_filter[MLX5_MAX_VLAN_IDS]; /* VLAN filters table. */ 232 unsigned int vlan_filter_n; /* Number of configured VLAN filters. */ 233 /* Device properties. */ 234 uint16_t mtu; /* Configured MTU. */ 235 unsigned int isolated:1; /* Whether isolated mode is enabled. */ 236 unsigned int representor:1; /* Device is a port representor. */ 237 unsigned int master:1; /* Device is a E-Switch master. */ 238 uint16_t domain_id; /* Switch domain identifier. */ 239 uint16_t vport_id; /* Associated VF vport index (if any). */ 240 int32_t representor_id; /* Port representor identifier. */ 241 /* RX/TX queues. */ 242 unsigned int rxqs_n; /* RX queues array size. */ 243 unsigned int txqs_n; /* TX queues array size. */ 244 struct mlx5_rxq_data *(*rxqs)[]; /* RX queues. */ 245 struct mlx5_txq_data *(*txqs)[]; /* TX queues. */ 246 struct rte_mempool *mprq_mp; /* Mempool for Multi-Packet RQ. */ 247 struct rte_eth_rss_conf rss_conf; /* RSS configuration. */ 248 unsigned int (*reta_idx)[]; /* RETA index table. */ 249 unsigned int reta_idx_n; /* RETA index size. */ 250 struct mlx5_drop drop_queue; /* Flow drop queues. */ 251 struct mlx5_flows flows; /* RTE Flow rules. */ 252 struct mlx5_flows ctrl_flows; /* Control flow rules. */ 253 LIST_HEAD(counters, mlx5_flow_counter) flow_counters; 254 /* Flow counters. */ 255 struct { 256 uint32_t dev_gen; /* Generation number to flush local caches. */ 257 rte_rwlock_t rwlock; /* MR Lock. */ 258 struct mlx5_mr_btree cache; /* Global MR cache table. */ 259 struct mlx5_mr_list mr_list; /* Registered MR list. */ 260 struct mlx5_mr_list mr_free_list; /* Freed MR list. */ 261 } mr; 262 LIST_HEAD(rxq, mlx5_rxq_ctrl) rxqsctrl; /* DPDK Rx queues. */ 263 LIST_HEAD(rxqibv, mlx5_rxq_ibv) rxqsibv; /* Verbs Rx queues. */ 264 LIST_HEAD(hrxq, mlx5_hrxq) hrxqs; /* Verbs Hash Rx queues. */ 265 LIST_HEAD(txq, mlx5_txq_ctrl) txqsctrl; /* DPDK Tx queues. */ 266 LIST_HEAD(txqibv, mlx5_txq_ibv) txqsibv; /* Verbs Tx queues. */ 267 /* Verbs Indirection tables. */ 268 LIST_HEAD(ind_tables, mlx5_ind_table_ibv) ind_tbls; 269 LIST_HEAD(matchers, mlx5_flow_dv_matcher) matchers; 270 LIST_HEAD(encap_decap, mlx5_flow_dv_encap_decap_resource) encaps_decaps; 271 LIST_HEAD(modify_cmd, mlx5_flow_dv_modify_hdr_resource) modify_cmds; 272 uint32_t link_speed_capa; /* Link speed capabilities. */ 273 struct mlx5_xstats_ctrl xstats_ctrl; /* Extended stats control. */ 274 struct mlx5_stats_ctrl stats_ctrl; /* Stats control. */ 275 int primary_socket; /* Unix socket for primary process. */ 276 void *uar_base; /* Reserved address space for UAR mapping */ 277 struct rte_intr_handle intr_handle_socket; /* Interrupt handler. */ 278 struct mlx5_dev_config config; /* Device configuration. */ 279 struct mlx5_verbs_alloc_ctx verbs_alloc_ctx; 280 /* Context for Verbs allocator. */ 281 int nl_socket_rdma; /* Netlink socket (NETLINK_RDMA). */ 282 int nl_socket_route; /* Netlink socket (NETLINK_ROUTE). */ 283 uint32_t nl_sn; /* Netlink message sequence number. */ 284 #ifndef RTE_ARCH_64 285 rte_spinlock_t uar_lock_cq; /* CQs share a common distinct UAR */ 286 rte_spinlock_t uar_lock[MLX5_UAR_PAGE_NUM_MAX]; 287 /* UAR same-page access control required in 32bit implementations. */ 288 #endif 289 struct mlx5_flow_tcf_context *tcf_context; /* TC flower context. */ 290 }; 291 292 #define PORT_ID(priv) ((priv)->dev_data->port_id) 293 #define ETH_DEV(priv) (&rte_eth_devices[PORT_ID(priv)]) 294 295 /* mlx5.c */ 296 297 int mlx5_getenv_int(const char *); 298 299 /* mlx5_ethdev.c */ 300 301 int mlx5_get_ifname(const struct rte_eth_dev *dev, char (*ifname)[IF_NAMESIZE]); 302 unsigned int mlx5_ifindex(const struct rte_eth_dev *dev); 303 int mlx5_ifreq(const struct rte_eth_dev *dev, int req, struct ifreq *ifr); 304 int mlx5_get_mtu(struct rte_eth_dev *dev, uint16_t *mtu); 305 int mlx5_set_flags(struct rte_eth_dev *dev, unsigned int keep, 306 unsigned int flags); 307 int mlx5_dev_configure(struct rte_eth_dev *dev); 308 void mlx5_dev_infos_get(struct rte_eth_dev *dev, struct rte_eth_dev_info *info); 309 int mlx5_fw_version_get(struct rte_eth_dev *dev, char *fw_ver, size_t fw_size); 310 const uint32_t *mlx5_dev_supported_ptypes_get(struct rte_eth_dev *dev); 311 int mlx5_link_update(struct rte_eth_dev *dev, int wait_to_complete); 312 int mlx5_force_link_status_change(struct rte_eth_dev *dev, int status); 313 int mlx5_dev_set_mtu(struct rte_eth_dev *dev, uint16_t mtu); 314 int mlx5_dev_get_flow_ctrl(struct rte_eth_dev *dev, 315 struct rte_eth_fc_conf *fc_conf); 316 int mlx5_dev_set_flow_ctrl(struct rte_eth_dev *dev, 317 struct rte_eth_fc_conf *fc_conf); 318 int mlx5_ibv_device_to_pci_addr(const struct ibv_device *device, 319 struct rte_pci_addr *pci_addr); 320 void mlx5_dev_link_status_handler(void *arg); 321 void mlx5_dev_interrupt_handler(void *arg); 322 void mlx5_dev_interrupt_handler_uninstall(struct rte_eth_dev *dev); 323 void mlx5_dev_interrupt_handler_install(struct rte_eth_dev *dev); 324 int mlx5_set_link_down(struct rte_eth_dev *dev); 325 int mlx5_set_link_up(struct rte_eth_dev *dev); 326 int mlx5_is_removed(struct rte_eth_dev *dev); 327 eth_tx_burst_t mlx5_select_tx_function(struct rte_eth_dev *dev); 328 eth_rx_burst_t mlx5_select_rx_function(struct rte_eth_dev *dev); 329 unsigned int mlx5_dev_to_port_id(const struct rte_device *dev, 330 uint16_t *port_list, 331 unsigned int port_list_n); 332 int mlx5_sysfs_switch_info(unsigned int ifindex, 333 struct mlx5_switch_info *info); 334 bool mlx5_translate_port_name(const char *port_name_in, 335 struct mlx5_switch_info *port_info_out); 336 337 /* mlx5_mac.c */ 338 339 int mlx5_get_mac(struct rte_eth_dev *dev, uint8_t (*mac)[ETHER_ADDR_LEN]); 340 void mlx5_mac_addr_remove(struct rte_eth_dev *dev, uint32_t index); 341 int mlx5_mac_addr_add(struct rte_eth_dev *dev, struct ether_addr *mac, 342 uint32_t index, uint32_t vmdq); 343 int mlx5_mac_addr_set(struct rte_eth_dev *dev, struct ether_addr *mac_addr); 344 int mlx5_set_mc_addr_list(struct rte_eth_dev *dev, 345 struct ether_addr *mc_addr_set, uint32_t nb_mc_addr); 346 347 /* mlx5_rss.c */ 348 349 int mlx5_rss_hash_update(struct rte_eth_dev *dev, 350 struct rte_eth_rss_conf *rss_conf); 351 int mlx5_rss_hash_conf_get(struct rte_eth_dev *dev, 352 struct rte_eth_rss_conf *rss_conf); 353 int mlx5_rss_reta_index_resize(struct rte_eth_dev *dev, unsigned int reta_size); 354 int mlx5_dev_rss_reta_query(struct rte_eth_dev *dev, 355 struct rte_eth_rss_reta_entry64 *reta_conf, 356 uint16_t reta_size); 357 int mlx5_dev_rss_reta_update(struct rte_eth_dev *dev, 358 struct rte_eth_rss_reta_entry64 *reta_conf, 359 uint16_t reta_size); 360 361 /* mlx5_rxmode.c */ 362 363 void mlx5_promiscuous_enable(struct rte_eth_dev *dev); 364 void mlx5_promiscuous_disable(struct rte_eth_dev *dev); 365 void mlx5_allmulticast_enable(struct rte_eth_dev *dev); 366 void mlx5_allmulticast_disable(struct rte_eth_dev *dev); 367 368 /* mlx5_stats.c */ 369 370 void mlx5_stats_init(struct rte_eth_dev *dev); 371 int mlx5_stats_get(struct rte_eth_dev *dev, struct rte_eth_stats *stats); 372 void mlx5_stats_reset(struct rte_eth_dev *dev); 373 int mlx5_xstats_get(struct rte_eth_dev *dev, struct rte_eth_xstat *stats, 374 unsigned int n); 375 void mlx5_xstats_reset(struct rte_eth_dev *dev); 376 int mlx5_xstats_get_names(struct rte_eth_dev *dev __rte_unused, 377 struct rte_eth_xstat_name *xstats_names, 378 unsigned int n); 379 380 /* mlx5_vlan.c */ 381 382 int mlx5_vlan_filter_set(struct rte_eth_dev *dev, uint16_t vlan_id, int on); 383 void mlx5_vlan_strip_queue_set(struct rte_eth_dev *dev, uint16_t queue, int on); 384 int mlx5_vlan_offload_set(struct rte_eth_dev *dev, int mask); 385 386 /* mlx5_trigger.c */ 387 388 int mlx5_dev_start(struct rte_eth_dev *dev); 389 void mlx5_dev_stop(struct rte_eth_dev *dev); 390 int mlx5_traffic_enable(struct rte_eth_dev *dev); 391 void mlx5_traffic_disable(struct rte_eth_dev *dev); 392 int mlx5_traffic_restart(struct rte_eth_dev *dev); 393 394 /* mlx5_flow.c */ 395 396 int mlx5_flow_discover_priorities(struct rte_eth_dev *dev); 397 void mlx5_flow_print(struct rte_flow *flow); 398 int mlx5_flow_validate(struct rte_eth_dev *dev, 399 const struct rte_flow_attr *attr, 400 const struct rte_flow_item items[], 401 const struct rte_flow_action actions[], 402 struct rte_flow_error *error); 403 struct rte_flow *mlx5_flow_create(struct rte_eth_dev *dev, 404 const struct rte_flow_attr *attr, 405 const struct rte_flow_item items[], 406 const struct rte_flow_action actions[], 407 struct rte_flow_error *error); 408 int mlx5_flow_destroy(struct rte_eth_dev *dev, struct rte_flow *flow, 409 struct rte_flow_error *error); 410 void mlx5_flow_list_flush(struct rte_eth_dev *dev, struct mlx5_flows *list); 411 int mlx5_flow_flush(struct rte_eth_dev *dev, struct rte_flow_error *error); 412 int mlx5_flow_query(struct rte_eth_dev *dev, struct rte_flow *flow, 413 const struct rte_flow_action *action, void *data, 414 struct rte_flow_error *error); 415 int mlx5_flow_isolate(struct rte_eth_dev *dev, int enable, 416 struct rte_flow_error *error); 417 int mlx5_dev_filter_ctrl(struct rte_eth_dev *dev, 418 enum rte_filter_type filter_type, 419 enum rte_filter_op filter_op, 420 void *arg); 421 int mlx5_flow_start(struct rte_eth_dev *dev, struct mlx5_flows *list); 422 void mlx5_flow_stop(struct rte_eth_dev *dev, struct mlx5_flows *list); 423 int mlx5_flow_verify(struct rte_eth_dev *dev); 424 int mlx5_ctrl_flow_vlan(struct rte_eth_dev *dev, 425 struct rte_flow_item_eth *eth_spec, 426 struct rte_flow_item_eth *eth_mask, 427 struct rte_flow_item_vlan *vlan_spec, 428 struct rte_flow_item_vlan *vlan_mask); 429 int mlx5_ctrl_flow(struct rte_eth_dev *dev, 430 struct rte_flow_item_eth *eth_spec, 431 struct rte_flow_item_eth *eth_mask); 432 int mlx5_flow_create_drop_queue(struct rte_eth_dev *dev); 433 void mlx5_flow_delete_drop_queue(struct rte_eth_dev *dev); 434 435 /* mlx5_socket.c */ 436 437 int mlx5_socket_init(struct rte_eth_dev *priv); 438 void mlx5_socket_uninit(struct rte_eth_dev *priv); 439 void mlx5_socket_handle(struct rte_eth_dev *priv); 440 int mlx5_socket_connect(struct rte_eth_dev *priv); 441 442 /* mlx5_nl.c */ 443 444 int mlx5_nl_init(int protocol); 445 int mlx5_nl_mac_addr_add(struct rte_eth_dev *dev, struct ether_addr *mac, 446 uint32_t index); 447 int mlx5_nl_mac_addr_remove(struct rte_eth_dev *dev, struct ether_addr *mac, 448 uint32_t index); 449 void mlx5_nl_mac_addr_sync(struct rte_eth_dev *dev); 450 void mlx5_nl_mac_addr_flush(struct rte_eth_dev *dev); 451 int mlx5_nl_promisc(struct rte_eth_dev *dev, int enable); 452 int mlx5_nl_allmulti(struct rte_eth_dev *dev, int enable); 453 unsigned int mlx5_nl_portnum(int nl, const char *name); 454 unsigned int mlx5_nl_ifindex(int nl, const char *name, uint32_t pindex); 455 int mlx5_nl_switch_info(int nl, unsigned int ifindex, 456 struct mlx5_switch_info *info); 457 458 /* mlx5_devx_cmds.c */ 459 460 int mlx5_devx_cmd_flow_counter_alloc(struct ibv_context *ctx, 461 struct mlx5_devx_counter_set *dcx); 462 int mlx5_devx_cmd_flow_counter_free(struct mlx5dv_devx_obj *obj); 463 int mlx5_devx_cmd_flow_counter_query(struct mlx5_devx_counter_set *dcx, 464 int clear, 465 uint64_t *pkts, uint64_t *bytes); 466 #endif /* RTE_PMD_MLX5_H_ */ 467