1 /* SPDX-License-Identifier: BSD-3-Clause 2 * Copyright 2015 6WIND S.A. 3 * Copyright 2015 Mellanox Technologies, Ltd 4 */ 5 6 #ifndef RTE_PMD_MLX5_H_ 7 #define RTE_PMD_MLX5_H_ 8 9 #include <stddef.h> 10 #include <stdbool.h> 11 #include <stdint.h> 12 #include <limits.h> 13 #include <sys/queue.h> 14 15 #include <rte_pci.h> 16 #include <rte_ether.h> 17 #include <ethdev_driver.h> 18 #include <rte_rwlock.h> 19 #include <rte_interrupts.h> 20 #include <rte_errno.h> 21 #include <rte_flow.h> 22 #include <rte_mtr.h> 23 24 #include <mlx5_glue.h> 25 #include <mlx5_devx_cmds.h> 26 #include <mlx5_prm.h> 27 #include <mlx5_common_mp.h> 28 #include <mlx5_common_mr.h> 29 #include <mlx5_common_devx.h> 30 31 #include "mlx5_defs.h" 32 #include "mlx5_utils.h" 33 #include "mlx5_os.h" 34 #include "mlx5_autoconf.h" 35 36 37 #define MLX5_SH(dev) (((struct mlx5_priv *)(dev)->data->dev_private)->sh) 38 39 /* 40 * Number of modification commands. 41 * The maximal actions amount in FW is some constant, and it is 16 in the 42 * latest releases. In some old releases, it will be limited to 8. 43 * Since there is no interface to query the capacity, the maximal value should 44 * be used to allow PMD to create the flow. The validation will be done in the 45 * lower driver layer or FW. A failure will be returned if exceeds the maximal 46 * supported actions number on the root table. 47 * On non-root tables, there is no limitation, but 32 is enough right now. 48 */ 49 #define MLX5_MAX_MODIFY_NUM 32 50 #define MLX5_ROOT_TBL_MODIFY_NUM 16 51 52 enum mlx5_ipool_index { 53 #if defined(HAVE_IBV_FLOW_DV_SUPPORT) || !defined(HAVE_INFINIBAND_VERBS_H) 54 MLX5_IPOOL_DECAP_ENCAP = 0, /* Pool for encap/decap resource. */ 55 MLX5_IPOOL_PUSH_VLAN, /* Pool for push vlan resource. */ 56 MLX5_IPOOL_TAG, /* Pool for tag resource. */ 57 MLX5_IPOOL_PORT_ID, /* Pool for port id resource. */ 58 MLX5_IPOOL_JUMP, /* Pool for jump resource. */ 59 MLX5_IPOOL_SAMPLE, /* Pool for sample resource. */ 60 MLX5_IPOOL_DEST_ARRAY, /* Pool for destination array resource. */ 61 MLX5_IPOOL_TUNNEL_ID, /* Pool for tunnel offload context */ 62 MLX5_IPOOL_TNL_TBL_ID, /* Pool for tunnel table ID. */ 63 #endif 64 MLX5_IPOOL_MTR, /* Pool for meter resource. */ 65 MLX5_IPOOL_MCP, /* Pool for metadata resource. */ 66 MLX5_IPOOL_HRXQ, /* Pool for hrxq resource. */ 67 MLX5_IPOOL_MLX5_FLOW, /* Pool for mlx5 flow handle. */ 68 MLX5_IPOOL_RTE_FLOW, /* Pool for rte_flow. */ 69 MLX5_IPOOL_RSS_EXPANTION_FLOW_ID, /* Pool for Queue/RSS flow ID. */ 70 MLX5_IPOOL_RSS_SHARED_ACTIONS, /* Pool for RSS shared actions. */ 71 MLX5_IPOOL_MTR_POLICY, /* Pool for meter policy resource. */ 72 MLX5_IPOOL_MAX, 73 }; 74 75 /* 76 * There are three reclaim memory mode supported. 77 * 0(none) means no memory reclaim. 78 * 1(light) means only PMD level reclaim. 79 * 2(aggressive) means both PMD and rdma-core level reclaim. 80 */ 81 enum mlx5_reclaim_mem_mode { 82 MLX5_RCM_NONE, /* Don't reclaim memory. */ 83 MLX5_RCM_LIGHT, /* Reclaim PMD level. */ 84 MLX5_RCM_AGGR, /* Reclaim PMD and rdma-core level. */ 85 }; 86 87 /* The type of flow. */ 88 enum mlx5_flow_type { 89 MLX5_FLOW_TYPE_CTL, /* Control flow. */ 90 MLX5_FLOW_TYPE_GEN, /* General flow. */ 91 MLX5_FLOW_TYPE_MCP, /* MCP flow. */ 92 MLX5_FLOW_TYPE_MAXI, 93 }; 94 95 /* Hlist and list callback context. */ 96 struct mlx5_flow_cb_ctx { 97 struct rte_eth_dev *dev; 98 struct rte_flow_error *error; 99 void *data; 100 void *data2; 101 }; 102 103 /* Device attributes used in mlx5 PMD */ 104 struct mlx5_dev_attr { 105 uint64_t device_cap_flags_ex; 106 int max_qp_wr; 107 int max_sge; 108 int max_cq; 109 int max_qp; 110 int max_cqe; 111 uint32_t max_pd; 112 uint32_t max_mr; 113 uint32_t max_srq; 114 uint32_t max_srq_wr; 115 uint32_t raw_packet_caps; 116 uint32_t max_rwq_indirection_table_size; 117 uint32_t max_tso; 118 uint32_t tso_supported_qpts; 119 uint64_t flags; 120 uint64_t comp_mask; 121 uint32_t sw_parsing_offloads; 122 uint32_t min_single_stride_log_num_of_bytes; 123 uint32_t max_single_stride_log_num_of_bytes; 124 uint32_t min_single_wqe_log_num_of_strides; 125 uint32_t max_single_wqe_log_num_of_strides; 126 uint32_t stride_supported_qpts; 127 uint32_t tunnel_offloads_caps; 128 char fw_ver[64]; 129 }; 130 131 /** Data associated with devices to spawn. */ 132 struct mlx5_dev_spawn_data { 133 uint32_t ifindex; /**< Network interface index. */ 134 uint32_t max_port; /**< Device maximal port index. */ 135 uint32_t phys_port; /**< Device physical port index. */ 136 int pf_bond; /**< bonding device PF index. < 0 - no bonding */ 137 int numa_node; /**< Device numa node. */ 138 struct mlx5_switch_info info; /**< Switch information. */ 139 void *phys_dev; /**< Associated physical device. */ 140 struct rte_eth_dev *eth_dev; /**< Associated Ethernet device. */ 141 struct rte_pci_device *pci_dev; /**< Backend PCI device. */ 142 struct mlx5_bond_info *bond_info; 143 }; 144 145 /** Data associated with socket messages. */ 146 struct mlx5_flow_dump_req { 147 uint32_t port_id; /**< There are plans in DPDK to extend port_id. */ 148 uint64_t flow_id; 149 } __rte_packed; 150 151 struct mlx5_flow_dump_ack { 152 int rc; /**< Return code. */ 153 }; 154 155 /** Key string for IPC. */ 156 #define MLX5_MP_NAME "net_mlx5_mp" 157 158 159 LIST_HEAD(mlx5_dev_list, mlx5_dev_ctx_shared); 160 161 /* Shared data between primary and secondary processes. */ 162 struct mlx5_shared_data { 163 rte_spinlock_t lock; 164 /* Global spinlock for primary and secondary processes. */ 165 int init_done; /* Whether primary has done initialization. */ 166 unsigned int secondary_cnt; /* Number of secondary processes init'd. */ 167 struct mlx5_dev_list mem_event_cb_list; 168 rte_rwlock_t mem_event_rwlock; 169 }; 170 171 /* Per-process data structure, not visible to other processes. */ 172 struct mlx5_local_data { 173 int init_done; /* Whether a secondary has done initialization. */ 174 }; 175 176 extern struct mlx5_shared_data *mlx5_shared_data; 177 178 /* Dev ops structs */ 179 extern const struct eth_dev_ops mlx5_dev_ops; 180 extern const struct eth_dev_ops mlx5_dev_sec_ops; 181 extern const struct eth_dev_ops mlx5_dev_ops_isolate; 182 183 struct mlx5_counter_ctrl { 184 /* Name of the counter. */ 185 char dpdk_name[RTE_ETH_XSTATS_NAME_SIZE]; 186 /* Name of the counter on the device table. */ 187 char ctr_name[RTE_ETH_XSTATS_NAME_SIZE]; 188 uint32_t dev:1; /**< Nonzero for dev counters. */ 189 }; 190 191 struct mlx5_xstats_ctrl { 192 /* Number of device stats. */ 193 uint16_t stats_n; 194 /* Number of device stats identified by PMD. */ 195 uint16_t mlx5_stats_n; 196 /* Index in the device counters table. */ 197 uint16_t dev_table_idx[MLX5_MAX_XSTATS]; 198 uint64_t base[MLX5_MAX_XSTATS]; 199 uint64_t xstats[MLX5_MAX_XSTATS]; 200 uint64_t hw_stats[MLX5_MAX_XSTATS]; 201 struct mlx5_counter_ctrl info[MLX5_MAX_XSTATS]; 202 }; 203 204 struct mlx5_stats_ctrl { 205 /* Base for imissed counter. */ 206 uint64_t imissed_base; 207 uint64_t imissed; 208 }; 209 210 /* Default PMD specific parameter value. */ 211 #define MLX5_ARG_UNSET (-1) 212 213 #define MLX5_LRO_SUPPORTED(dev) \ 214 (((struct mlx5_priv *)((dev)->data->dev_private))->config.lro.supported) 215 216 /* Maximal size of coalesced segment for LRO is set in chunks of 256 Bytes. */ 217 #define MLX5_LRO_SEG_CHUNK_SIZE 256u 218 219 /* Maximal size of aggregated LRO packet. */ 220 #define MLX5_MAX_LRO_SIZE (UINT8_MAX * MLX5_LRO_SEG_CHUNK_SIZE) 221 222 /* Maximal number of segments to split. */ 223 #define MLX5_MAX_RXQ_NSEG (1u << MLX5_MAX_LOG_RQ_SEGS) 224 225 /* LRO configurations structure. */ 226 struct mlx5_lro_config { 227 uint32_t supported:1; /* Whether LRO is supported. */ 228 uint32_t timeout; /* User configuration. */ 229 }; 230 231 /* 232 * Device configuration structure. 233 * 234 * Merged configuration from: 235 * 236 * - Device capabilities, 237 * - User device parameters disabled features. 238 */ 239 struct mlx5_dev_config { 240 unsigned int hw_csum:1; /* Checksum offload is supported. */ 241 unsigned int hw_vlan_strip:1; /* VLAN stripping is supported. */ 242 unsigned int hw_vlan_insert:1; /* VLAN insertion in WQE is supported. */ 243 unsigned int hw_fcs_strip:1; /* FCS stripping is supported. */ 244 unsigned int hw_padding:1; /* End alignment padding is supported. */ 245 unsigned int vf:1; /* This is a VF. */ 246 unsigned int sf:1; /* This is a SF. */ 247 unsigned int tunnel_en:1; 248 /* Whether tunnel stateless offloads are supported. */ 249 unsigned int mpls_en:1; /* MPLS over GRE/UDP is enabled. */ 250 unsigned int cqe_comp:1; /* CQE compression is enabled. */ 251 unsigned int cqe_comp_fmt:3; /* CQE compression format. */ 252 unsigned int tso:1; /* Whether TSO is supported. */ 253 unsigned int rx_vec_en:1; /* Rx vector is enabled. */ 254 unsigned int mr_ext_memseg_en:1; 255 /* Whether memseg should be extended for MR creation. */ 256 unsigned int l3_vxlan_en:1; /* Enable L3 VXLAN flow creation. */ 257 unsigned int vf_nl_en:1; /* Enable Netlink requests in VF mode. */ 258 unsigned int dv_esw_en:1; /* Enable E-Switch DV flow. */ 259 unsigned int dv_flow_en:1; /* Enable DV flow. */ 260 unsigned int dv_xmeta_en:2; /* Enable extensive flow metadata. */ 261 unsigned int lacp_by_user:1; 262 /* Enable user to manage LACP traffic. */ 263 unsigned int swp:1; /* Tx generic tunnel checksum and TSO offload. */ 264 unsigned int devx:1; /* Whether devx interface is available or not. */ 265 unsigned int dest_tir:1; /* Whether advanced DR API is available. */ 266 unsigned int reclaim_mode:2; /* Memory reclaim mode. */ 267 unsigned int rt_timestamp:1; /* realtime timestamp format. */ 268 unsigned int sys_mem_en:1; /* The default memory allocator. */ 269 unsigned int decap_en:1; /* Whether decap will be used or not. */ 270 unsigned int dv_miss_info:1; /* restore packet after partial hw miss */ 271 unsigned int allow_duplicate_pattern:1; 272 /* Allow/Prevent the duplicate rules pattern. */ 273 struct { 274 unsigned int enabled:1; /* Whether MPRQ is enabled. */ 275 unsigned int stride_num_n; /* Number of strides. */ 276 unsigned int stride_size_n; /* Size of a stride. */ 277 unsigned int min_stride_size_n; /* Min size of a stride. */ 278 unsigned int max_stride_size_n; /* Max size of a stride. */ 279 unsigned int max_memcpy_len; 280 /* Maximum packet size to memcpy Rx packets. */ 281 unsigned int min_rxqs_num; 282 /* Rx queue count threshold to enable MPRQ. */ 283 } mprq; /* Configurations for Multi-Packet RQ. */ 284 int mps; /* Multi-packet send supported mode. */ 285 int dbnc; /* Skip doorbell register write barrier. */ 286 unsigned int flow_prio; /* Number of flow priorities. */ 287 enum modify_reg flow_mreg_c[MLX5_MREG_C_NUM]; 288 /* Availibility of mreg_c's. */ 289 unsigned int tso_max_payload_sz; /* Maximum TCP payload for TSO. */ 290 unsigned int ind_table_max_size; /* Maximum indirection table size. */ 291 unsigned int max_dump_files_num; /* Maximum dump files per queue. */ 292 unsigned int log_hp_size; /* Single hairpin queue data size in total. */ 293 int txqs_inline; /* Queue number threshold for inlining. */ 294 int txq_inline_min; /* Minimal amount of data bytes to inline. */ 295 int txq_inline_max; /* Max packet size for inlining with SEND. */ 296 int txq_inline_mpw; /* Max packet size for inlining with eMPW. */ 297 int tx_pp; /* Timestamp scheduling granularity in nanoseconds. */ 298 int tx_skew; /* Tx scheduling skew between WQE and data on wire. */ 299 struct mlx5_hca_attr hca_attr; /* HCA attributes. */ 300 struct mlx5_lro_config lro; /* LRO configuration. */ 301 }; 302 303 304 /* Structure for VF VLAN workaround. */ 305 struct mlx5_vf_vlan { 306 uint32_t tag:12; 307 uint32_t created:1; 308 }; 309 310 /* Flow drop context necessary due to Verbs API. */ 311 struct mlx5_drop { 312 struct mlx5_hrxq *hrxq; /* Hash Rx queue queue. */ 313 struct mlx5_rxq_obj *rxq; /* Rx queue object. */ 314 }; 315 316 /* Loopback dummy queue resources required due to Verbs API. */ 317 struct mlx5_lb_ctx { 318 struct ibv_qp *qp; /* QP object. */ 319 void *ibv_cq; /* Completion queue. */ 320 uint16_t refcnt; /* Reference count for representors. */ 321 }; 322 323 #define MLX5_COUNTERS_PER_POOL 512 324 #define MLX5_MAX_PENDING_QUERIES 4 325 #define MLX5_CNT_CONTAINER_RESIZE 64 326 #define MLX5_CNT_SHARED_OFFSET 0x80000000 327 #define IS_LEGACY_SHARED_CNT(cnt) (!!((cnt) & MLX5_CNT_SHARED_OFFSET)) 328 #define IS_BATCH_CNT(cnt) (((cnt) & (MLX5_CNT_SHARED_OFFSET - 1)) >= \ 329 MLX5_CNT_BATCH_OFFSET) 330 #define MLX5_CNT_SIZE (sizeof(struct mlx5_flow_counter)) 331 #define MLX5_AGE_SIZE (sizeof(struct mlx5_age_param)) 332 333 #define MLX5_CNT_LEN(pool) \ 334 (MLX5_CNT_SIZE + \ 335 ((pool)->is_aged ? MLX5_AGE_SIZE : 0)) 336 #define MLX5_POOL_GET_CNT(pool, index) \ 337 ((struct mlx5_flow_counter *) \ 338 ((uint8_t *)((pool) + 1) + (index) * (MLX5_CNT_LEN(pool)))) 339 #define MLX5_CNT_ARRAY_IDX(pool, cnt) \ 340 ((int)(((uint8_t *)(cnt) - (uint8_t *)((pool) + 1)) / \ 341 MLX5_CNT_LEN(pool))) 342 /* 343 * The pool index and offset of counter in the pool array makes up the 344 * counter index. In case the counter is from pool 0 and offset 0, it 345 * should plus 1 to avoid index 0, since 0 means invalid counter index 346 * currently. 347 */ 348 #define MLX5_MAKE_CNT_IDX(pi, offset) \ 349 ((pi) * MLX5_COUNTERS_PER_POOL + (offset) + 1) 350 #define MLX5_CNT_TO_AGE(cnt) \ 351 ((struct mlx5_age_param *)((cnt) + 1)) 352 /* 353 * The maximum single counter is 0x800000 as MLX5_CNT_BATCH_OFFSET 354 * defines. The pool size is 512, pool index should never reach 355 * INT16_MAX. 356 */ 357 #define POOL_IDX_INVALID UINT16_MAX 358 359 /* Age status. */ 360 enum { 361 AGE_FREE, /* Initialized state. */ 362 AGE_CANDIDATE, /* Counter assigned to flows. */ 363 AGE_TMOUT, /* Timeout, wait for rte_flow_get_aged_flows and destroy. */ 364 }; 365 366 enum mlx5_counter_type { 367 MLX5_COUNTER_TYPE_ORIGIN, 368 MLX5_COUNTER_TYPE_AGE, 369 MLX5_COUNTER_TYPE_MAX, 370 }; 371 372 /* Counter age parameter. */ 373 struct mlx5_age_param { 374 uint16_t state; /**< Age state (atomically accessed). */ 375 uint16_t port_id; /**< Port id of the counter. */ 376 uint32_t timeout:24; /**< Aging timeout in seconds. */ 377 uint32_t sec_since_last_hit; 378 /**< Time in seconds since last hit (atomically accessed). */ 379 void *context; /**< Flow counter age context. */ 380 }; 381 382 struct flow_counter_stats { 383 uint64_t hits; 384 uint64_t bytes; 385 }; 386 387 /* Shared counters information for counters. */ 388 struct mlx5_flow_counter_shared { 389 union { 390 uint32_t refcnt; /* Only for shared action management. */ 391 uint32_t id; /* User counter ID for legacy sharing. */ 392 }; 393 }; 394 395 /* Shared counter configuration. */ 396 struct mlx5_shared_counter_conf { 397 struct rte_eth_dev *dev; /* The device shared counter belongs to. */ 398 uint32_t id; /* The shared counter ID. */ 399 }; 400 401 struct mlx5_flow_counter_pool; 402 /* Generic counters information. */ 403 struct mlx5_flow_counter { 404 union { 405 /* 406 * User-defined counter shared info is only used during 407 * counter active time. And aging counter sharing is not 408 * supported, so active shared counter will not be chained 409 * to the aging list. For shared counter, only when it is 410 * released, the TAILQ entry memory will be used, at that 411 * time, shared memory is not used anymore. 412 * 413 * Similarly to none-batch counter dcs, since it doesn't 414 * support aging, while counter is allocated, the entry 415 * memory is not used anymore. In this case, as bytes 416 * memory is used only when counter is allocated, and 417 * entry memory is used only when counter is free. The 418 * dcs pointer can be saved to these two different place 419 * at different stage. It will eliminate the individual 420 * counter extend struct. 421 */ 422 TAILQ_ENTRY(mlx5_flow_counter) next; 423 /**< Pointer to the next flow counter structure. */ 424 struct { 425 struct mlx5_flow_counter_shared shared_info; 426 /**< Shared counter information. */ 427 void *dcs_when_active; 428 /* 429 * For non-batch mode, the dcs will be saved 430 * here when the counter is free. 431 */ 432 }; 433 }; 434 union { 435 uint64_t hits; /**< Reset value of hits packets. */ 436 struct mlx5_flow_counter_pool *pool; /**< Counter pool. */ 437 }; 438 union { 439 uint64_t bytes; /**< Reset value of bytes. */ 440 void *dcs_when_free; 441 /* 442 * For non-batch mode, the dcs will be saved here 443 * when the counter is free. 444 */ 445 }; 446 void *action; /**< Pointer to the dv action. */ 447 }; 448 449 TAILQ_HEAD(mlx5_counters, mlx5_flow_counter); 450 451 /* Generic counter pool structure - query is in pool resolution. */ 452 struct mlx5_flow_counter_pool { 453 TAILQ_ENTRY(mlx5_flow_counter_pool) next; 454 struct mlx5_counters counters[2]; /* Free counter list. */ 455 struct mlx5_devx_obj *min_dcs; 456 /* The devx object of the minimum counter ID. */ 457 uint64_t time_of_last_age_check; 458 /* System time (from rte_rdtsc()) read in the last aging check. */ 459 uint32_t index:30; /* Pool index in container. */ 460 uint32_t is_aged:1; /* Pool with aging counter. */ 461 volatile uint32_t query_gen:1; /* Query round. */ 462 rte_spinlock_t sl; /* The pool lock. */ 463 rte_spinlock_t csl; /* The pool counter free list lock. */ 464 struct mlx5_counter_stats_raw *raw; 465 struct mlx5_counter_stats_raw *raw_hw; 466 /* The raw on HW working. */ 467 }; 468 469 /* Memory management structure for group of counter statistics raws. */ 470 struct mlx5_counter_stats_mem_mng { 471 LIST_ENTRY(mlx5_counter_stats_mem_mng) next; 472 struct mlx5_counter_stats_raw *raws; 473 struct mlx5_devx_obj *dm; 474 void *umem; 475 }; 476 477 /* Raw memory structure for the counter statistics values of a pool. */ 478 struct mlx5_counter_stats_raw { 479 LIST_ENTRY(mlx5_counter_stats_raw) next; 480 struct mlx5_counter_stats_mem_mng *mem_mng; 481 volatile struct flow_counter_stats *data; 482 }; 483 484 TAILQ_HEAD(mlx5_counter_pools, mlx5_flow_counter_pool); 485 486 /* Counter global management structure. */ 487 struct mlx5_flow_counter_mng { 488 volatile uint16_t n_valid; /* Number of valid pools. */ 489 uint16_t n; /* Number of pools. */ 490 uint16_t last_pool_idx; /* Last used pool index */ 491 int min_id; /* The minimum counter ID in the pools. */ 492 int max_id; /* The maximum counter ID in the pools. */ 493 rte_spinlock_t pool_update_sl; /* The pool update lock. */ 494 rte_spinlock_t csl[MLX5_COUNTER_TYPE_MAX]; 495 /* The counter free list lock. */ 496 struct mlx5_counters counters[MLX5_COUNTER_TYPE_MAX]; 497 /* Free counter list. */ 498 struct mlx5_flow_counter_pool **pools; /* Counter pool array. */ 499 struct mlx5_counter_stats_mem_mng *mem_mng; 500 /* Hold the memory management for the next allocated pools raws. */ 501 struct mlx5_counters flow_counters; /* Legacy flow counter list. */ 502 uint8_t pending_queries; 503 uint16_t pool_index; 504 uint8_t query_thread_on; 505 bool relaxed_ordering_read; 506 bool relaxed_ordering_write; 507 bool counter_fallback; /* Use counter fallback management. */ 508 LIST_HEAD(mem_mngs, mlx5_counter_stats_mem_mng) mem_mngs; 509 LIST_HEAD(stat_raws, mlx5_counter_stats_raw) free_stat_raws; 510 }; 511 512 /* ASO structures. */ 513 #define MLX5_ASO_QUEUE_LOG_DESC 10 514 515 struct mlx5_aso_cq { 516 uint16_t log_desc_n; 517 uint32_t cq_ci:24; 518 struct mlx5_devx_cq cq_obj; 519 uint64_t errors; 520 }; 521 522 struct mlx5_aso_sq_elem { 523 union { 524 struct { 525 struct mlx5_aso_age_pool *pool; 526 uint16_t burst_size; 527 }; 528 struct mlx5_aso_mtr *mtr; 529 struct { 530 struct mlx5_aso_ct_action *ct; 531 char *query_data; 532 }; 533 }; 534 }; 535 536 struct mlx5_aso_sq { 537 uint16_t log_desc_n; 538 rte_spinlock_t sqsl; 539 struct mlx5_aso_cq cq; 540 struct mlx5_devx_sq sq_obj; 541 volatile uint64_t *uar_addr; 542 struct mlx5_pmd_mr mr; 543 uint16_t pi; 544 uint32_t head; 545 uint32_t tail; 546 uint32_t sqn; 547 struct mlx5_aso_sq_elem elts[1 << MLX5_ASO_QUEUE_LOG_DESC]; 548 uint16_t next; /* Pool index of the next pool to query. */ 549 }; 550 551 struct mlx5_aso_age_action { 552 LIST_ENTRY(mlx5_aso_age_action) next; 553 void *dr_action; 554 uint32_t refcnt; 555 /* Following fields relevant only when action is active. */ 556 uint16_t offset; /* Offset of ASO Flow Hit flag in DevX object. */ 557 struct mlx5_age_param age_params; 558 }; 559 560 #define MLX5_ASO_AGE_ACTIONS_PER_POOL 512 561 562 struct mlx5_aso_age_pool { 563 struct mlx5_devx_obj *flow_hit_aso_obj; 564 uint16_t index; /* Pool index in pools array. */ 565 uint64_t time_of_last_age_check; /* In seconds. */ 566 struct mlx5_aso_age_action actions[MLX5_ASO_AGE_ACTIONS_PER_POOL]; 567 }; 568 569 LIST_HEAD(aso_age_list, mlx5_aso_age_action); 570 571 struct mlx5_aso_age_mng { 572 struct mlx5_aso_age_pool **pools; 573 uint16_t n; /* Total number of pools. */ 574 uint16_t next; /* Number of pools in use, index of next free pool. */ 575 rte_spinlock_t resize_sl; /* Lock for resize objects. */ 576 rte_spinlock_t free_sl; /* Lock for free list access. */ 577 struct aso_age_list free; /* Free age actions list - ready to use. */ 578 struct mlx5_aso_sq aso_sq; /* ASO queue objects. */ 579 }; 580 581 /* Management structure for geneve tlv option */ 582 struct mlx5_geneve_tlv_option_resource { 583 struct mlx5_devx_obj *obj; /* Pointer to the geneve tlv opt object. */ 584 rte_be16_t option_class; /* geneve tlv opt class.*/ 585 uint8_t option_type; /* geneve tlv opt type.*/ 586 uint8_t length; /* geneve tlv opt length. */ 587 uint32_t refcnt; /* geneve tlv object reference counter */ 588 }; 589 590 591 #define MLX5_AGE_EVENT_NEW 1 592 #define MLX5_AGE_TRIGGER 2 593 #define MLX5_AGE_SET(age_info, BIT) \ 594 ((age_info)->flags |= (1 << (BIT))) 595 #define MLX5_AGE_UNSET(age_info, BIT) \ 596 ((age_info)->flags &= ~(1 << (BIT))) 597 #define MLX5_AGE_GET(age_info, BIT) \ 598 ((age_info)->flags & (1 << (BIT))) 599 #define GET_PORT_AGE_INFO(priv) \ 600 (&((priv)->sh->port[(priv)->dev_port - 1].age_info)) 601 /* Current time in seconds. */ 602 #define MLX5_CURR_TIME_SEC (rte_rdtsc() / rte_get_tsc_hz()) 603 604 /* Aging information for per port. */ 605 struct mlx5_age_info { 606 uint8_t flags; /* Indicate if is new event or need to be triggered. */ 607 struct mlx5_counters aged_counters; /* Aged counter list. */ 608 struct aso_age_list aged_aso; /* Aged ASO actions list. */ 609 rte_spinlock_t aged_sl; /* Aged flow list lock. */ 610 }; 611 612 /* Per port data of shared IB device. */ 613 struct mlx5_dev_shared_port { 614 uint32_t ih_port_id; 615 uint32_t devx_ih_port_id; 616 /* 617 * Interrupt handler port_id. Used by shared interrupt 618 * handler to find the corresponding rte_eth device 619 * by IB port index. If value is equal or greater 620 * RTE_MAX_ETHPORTS it means there is no subhandler 621 * installed for specified IB port index. 622 */ 623 struct mlx5_age_info age_info; 624 /* Aging information for per port. */ 625 }; 626 627 /* 628 * Max number of actions per DV flow. 629 * See CREATE_FLOW_MAX_FLOW_ACTIONS_SUPPORTED 630 * in rdma-core file providers/mlx5/verbs.c. 631 */ 632 #define MLX5_DV_MAX_NUMBER_OF_ACTIONS 8 633 634 /* ASO flow meter structures */ 635 /* Modify this value if enum rte_mtr_color changes. */ 636 #define RTE_MTR_DROPPED RTE_COLORS 637 /* Yellow is now supported. */ 638 #define MLX5_MTR_RTE_COLORS (RTE_COLOR_YELLOW + 1) 639 /* table_id 22 bits in mlx5_flow_tbl_key so limit policy number. */ 640 #define MLX5_MAX_SUB_POLICY_TBL_NUM 0x3FFFFF 641 #define MLX5_INVALID_POLICY_ID UINT32_MAX 642 /* Suffix table_id on MLX5_FLOW_TABLE_LEVEL_METER. */ 643 #define MLX5_MTR_TABLE_ID_SUFFIX 1 644 /* Drop table_id on MLX5_FLOW_TABLE_LEVEL_METER. */ 645 #define MLX5_MTR_TABLE_ID_DROP 2 646 /* Priority of the meter policy matcher. */ 647 #define MLX5_MTR_POLICY_MATCHER_PRIO 0 648 /* Default policy. */ 649 #define MLX5_MTR_POLICY_MODE_DEF 1 650 /* Only green color valid. */ 651 #define MLX5_MTR_POLICY_MODE_OG 2 652 /* Only yellow color valid. */ 653 #define MLX5_MTR_POLICY_MODE_OY 3 654 655 enum mlx5_meter_domain { 656 MLX5_MTR_DOMAIN_INGRESS, 657 MLX5_MTR_DOMAIN_EGRESS, 658 MLX5_MTR_DOMAIN_TRANSFER, 659 MLX5_MTR_DOMAIN_MAX, 660 }; 661 #define MLX5_MTR_DOMAIN_INGRESS_BIT (1 << MLX5_MTR_DOMAIN_INGRESS) 662 #define MLX5_MTR_DOMAIN_EGRESS_BIT (1 << MLX5_MTR_DOMAIN_EGRESS) 663 #define MLX5_MTR_DOMAIN_TRANSFER_BIT (1 << MLX5_MTR_DOMAIN_TRANSFER) 664 #define MLX5_MTR_ALL_DOMAIN_BIT (MLX5_MTR_DOMAIN_INGRESS_BIT | \ 665 MLX5_MTR_DOMAIN_EGRESS_BIT | \ 666 MLX5_MTR_DOMAIN_TRANSFER_BIT) 667 668 /* The color tag rule structure. */ 669 struct mlx5_sub_policy_color_rule { 670 void *rule; 671 /* The color rule. */ 672 struct mlx5_flow_dv_matcher *matcher; 673 /* The color matcher. */ 674 TAILQ_ENTRY(mlx5_sub_policy_color_rule) next_port; 675 /**< Pointer to the next color rule structure. */ 676 int32_t src_port; 677 /* On which src port this rule applied. */ 678 }; 679 680 TAILQ_HEAD(mlx5_sub_policy_color_rules, mlx5_sub_policy_color_rule); 681 682 /* 683 * Meter sub-policy structure. 684 * Each RSS TIR in meter policy need its own sub-policy resource. 685 */ 686 struct mlx5_flow_meter_sub_policy { 687 uint32_t main_policy_id:1; 688 /* Main policy id is same as this sub_policy id. */ 689 uint32_t idx:31; 690 /* Index to sub_policy ipool entity. */ 691 void *main_policy; 692 /* Point to struct mlx5_flow_meter_policy. */ 693 struct mlx5_flow_tbl_resource *tbl_rsc; 694 /* The sub-policy table resource. */ 695 uint32_t rix_hrxq[MLX5_MTR_RTE_COLORS]; 696 /* Index to TIR resource. */ 697 struct mlx5_flow_tbl_resource *jump_tbl[MLX5_MTR_RTE_COLORS]; 698 /* Meter jump/drop table. */ 699 struct mlx5_sub_policy_color_rules color_rules[RTE_COLORS]; 700 /* List for the color rules. */ 701 }; 702 703 struct mlx5_meter_policy_acts { 704 uint8_t actions_n; 705 /* Number of actions. */ 706 void *dv_actions[MLX5_DV_MAX_NUMBER_OF_ACTIONS]; 707 /* Action list. */ 708 }; 709 710 struct mlx5_meter_policy_action_container { 711 uint32_t rix_mark; 712 /* Index to the mark action. */ 713 struct mlx5_flow_dv_modify_hdr_resource *modify_hdr; 714 /* Pointer to modify header resource in cache. */ 715 uint8_t fate_action; 716 /* Fate action type. */ 717 union { 718 struct rte_flow_action *rss; 719 /* Rss action configuration. */ 720 uint32_t rix_port_id_action; 721 /* Index to port ID action resource. */ 722 void *dr_jump_action[MLX5_MTR_DOMAIN_MAX]; 723 /* Jump/drop action per color. */ 724 uint16_t queue; 725 /* Queue action configuration. */ 726 struct { 727 uint32_t next_mtr_id; 728 /* The next meter id. */ 729 void *next_sub_policy; 730 /* Next meter's sub-policy. */ 731 }; 732 }; 733 }; 734 735 /* Flow meter policy parameter structure. */ 736 struct mlx5_flow_meter_policy { 737 struct rte_eth_dev *dev; 738 /* The port dev on which policy is created. */ 739 uint32_t is_rss:1; 740 /* Is RSS policy table. */ 741 uint32_t ingress:1; 742 /* Rule applies to ingress domain. */ 743 uint32_t egress:1; 744 /* Rule applies to egress domain. */ 745 uint32_t transfer:1; 746 /* Rule applies to transfer domain. */ 747 uint32_t is_queue:1; 748 /* Is queue action in policy table. */ 749 uint32_t is_hierarchy:1; 750 /* Is meter action in policy table. */ 751 uint32_t skip_y:1; 752 /* If yellow color policy is skipped. */ 753 uint32_t skip_g:1; 754 /* If green color policy is skipped. */ 755 rte_spinlock_t sl; 756 uint32_t ref_cnt; 757 /* Use count. */ 758 struct mlx5_meter_policy_action_container act_cnt[MLX5_MTR_RTE_COLORS]; 759 /* Policy actions container. */ 760 void *dr_drop_action[MLX5_MTR_DOMAIN_MAX]; 761 /* drop action for red color. */ 762 uint16_t sub_policy_num; 763 /* Count sub policy tables, 3 bits per domain. */ 764 struct mlx5_flow_meter_sub_policy **sub_policys[MLX5_MTR_DOMAIN_MAX]; 765 /* Sub policy table array must be the end of struct. */ 766 }; 767 768 /* The maximum sub policy is relate to struct mlx5_rss_hash_fields[]. */ 769 #define MLX5_MTR_RSS_MAX_SUB_POLICY 7 770 #define MLX5_MTR_SUB_POLICY_NUM_SHIFT 3 771 #define MLX5_MTR_SUB_POLICY_NUM_MASK 0x7 772 #define MLX5_MTRS_DEFAULT_RULE_PRIORITY 0xFFFF 773 #define MLX5_MTR_CHAIN_MAX_NUM 8 774 775 /* Flow meter default policy parameter structure. 776 * Policy index 0 is reserved by default policy table. 777 * Action per color as below: 778 * green - do nothing, yellow - do nothing, red - drop 779 */ 780 struct mlx5_flow_meter_def_policy { 781 struct mlx5_flow_meter_sub_policy sub_policy; 782 /* Policy rules jump to other tables. */ 783 void *dr_jump_action[RTE_COLORS]; 784 /* Jump action per color. */ 785 }; 786 787 /* Meter parameter structure. */ 788 struct mlx5_flow_meter_info { 789 uint32_t meter_id; 790 /**< Meter id. */ 791 uint32_t policy_id; 792 /* Policy id, the first sub_policy idx. */ 793 struct mlx5_flow_meter_profile *profile; 794 /**< Meter profile parameters. */ 795 rte_spinlock_t sl; /**< Meter action spinlock. */ 796 /** Set of stats counters to be enabled. 797 * @see enum rte_mtr_stats_type 798 */ 799 uint32_t bytes_dropped:1; 800 /** Set bytes dropped stats to be enabled. */ 801 uint32_t pkts_dropped:1; 802 /** Set packets dropped stats to be enabled. */ 803 uint32_t active_state:1; 804 /**< Meter hw active state. */ 805 uint32_t shared:1; 806 /**< Meter shared or not. */ 807 uint32_t is_enable:1; 808 /**< Meter disable/enable state. */ 809 uint32_t ingress:1; 810 /**< Rule applies to egress traffic. */ 811 uint32_t egress:1; 812 /** 813 * Instead of simply matching the properties of traffic as it would 814 * appear on a given DPDK port ID, enabling this attribute transfers 815 * a flow rule to the lowest possible level of any device endpoints 816 * found in the pattern. 817 * 818 * When supported, this effectively enables an application to 819 * re-route traffic not necessarily intended for it (e.g. coming 820 * from or addressed to different physical ports, VFs or 821 * applications) at the device level. 822 * 823 * It complements the behavior of some pattern items such as 824 * RTE_FLOW_ITEM_TYPE_PHY_PORT and is meaningless without them. 825 * 826 * When transferring flow rules, ingress and egress attributes keep 827 * their original meaning, as if processing traffic emitted or 828 * received by the application. 829 */ 830 uint32_t transfer:1; 831 uint32_t def_policy:1; 832 /* Meter points to default policy. */ 833 void *drop_rule[MLX5_MTR_DOMAIN_MAX]; 834 /* Meter drop rule in drop table. */ 835 uint32_t drop_cnt; 836 /**< Color counter for drop. */ 837 uint32_t ref_cnt; 838 /**< Use count. */ 839 struct mlx5_indexed_pool *flow_ipool; 840 /**< Index pool for flow id. */ 841 void *meter_action; 842 /**< Flow meter action. */ 843 }; 844 845 /* PPS(packets per second) map to BPS(Bytes per second). 846 * HW treat packet as 128bytes in PPS mode 847 */ 848 #define MLX5_MTRS_PPS_MAP_BPS_SHIFT 7 849 850 /* RFC2697 parameter structure. */ 851 struct mlx5_flow_meter_srtcm_rfc2697_prm { 852 rte_be32_t cbs_cir; 853 /* 854 * bit 24-28: cbs_exponent, bit 16-23 cbs_mantissa, 855 * bit 8-12: cir_exponent, bit 0-7 cir_mantissa. 856 */ 857 rte_be32_t ebs_eir; 858 /* 859 * bit 24-28: ebs_exponent, bit 16-23 ebs_mantissa, 860 * bit 8-12: eir_exponent, bit 0-7 eir_mantissa. 861 */ 862 }; 863 864 /* Flow meter profile structure. */ 865 struct mlx5_flow_meter_profile { 866 TAILQ_ENTRY(mlx5_flow_meter_profile) next; 867 /**< Pointer to the next flow meter structure. */ 868 uint32_t id; /**< Profile id. */ 869 struct rte_mtr_meter_profile profile; /**< Profile detail. */ 870 union { 871 struct mlx5_flow_meter_srtcm_rfc2697_prm srtcm_prm; 872 /**< srtcm_rfc2697 struct. */ 873 }; 874 uint32_t ref_cnt; /**< Use count. */ 875 uint32_t g_support:1; /**< If G color will be generated. */ 876 uint32_t y_support:1; /**< If Y color will be generated. */ 877 }; 878 879 /* 2 meters in each ASO cache line */ 880 #define MLX5_MTRS_CONTAINER_RESIZE 64 881 /* 882 * The pool index and offset of meter in the pool array makes up the 883 * meter index. In case the meter is from pool 0 and offset 0, it 884 * should plus 1 to avoid index 0, since 0 means invalid meter index 885 * currently. 886 */ 887 #define MLX5_MAKE_MTR_IDX(pi, offset) \ 888 ((pi) * MLX5_ASO_MTRS_PER_POOL + (offset) + 1) 889 890 /*aso flow meter state*/ 891 enum mlx5_aso_mtr_state { 892 ASO_METER_FREE, /* In free list. */ 893 ASO_METER_WAIT, /* ACCESS_ASO WQE in progress. */ 894 ASO_METER_READY, /* CQE received. */ 895 }; 896 897 /* Generic aso_flow_meter information. */ 898 struct mlx5_aso_mtr { 899 LIST_ENTRY(mlx5_aso_mtr) next; 900 struct mlx5_flow_meter_info fm; 901 /**< Pointer to the next aso flow meter structure. */ 902 uint8_t state; /**< ASO flow meter state. */ 903 uint8_t offset; 904 }; 905 906 /* Generic aso_flow_meter pool structure. */ 907 struct mlx5_aso_mtr_pool { 908 struct mlx5_aso_mtr mtrs[MLX5_ASO_MTRS_PER_POOL]; 909 /*Must be the first in pool*/ 910 struct mlx5_devx_obj *devx_obj; 911 /* The devx object of the minimum aso flow meter ID. */ 912 uint32_t index; /* Pool index in management structure. */ 913 }; 914 915 LIST_HEAD(aso_meter_list, mlx5_aso_mtr); 916 /* Pools management structure for ASO flow meter pools. */ 917 struct mlx5_aso_mtr_pools_mng { 918 volatile uint16_t n_valid; /* Number of valid pools. */ 919 uint16_t n; /* Number of pools. */ 920 rte_spinlock_t mtrsl; /* The ASO flow meter free list lock. */ 921 struct aso_meter_list meters; /* Free ASO flow meter list. */ 922 struct mlx5_aso_sq sq; /*SQ using by ASO flow meter. */ 923 struct mlx5_aso_mtr_pool **pools; /* ASO flow meter pool array. */ 924 }; 925 926 /* Meter management structure for global flow meter resource. */ 927 struct mlx5_flow_mtr_mng { 928 struct mlx5_aso_mtr_pools_mng pools_mng; 929 /* Pools management structure for ASO flow meter pools. */ 930 struct mlx5_flow_meter_def_policy *def_policy[MLX5_MTR_DOMAIN_MAX]; 931 /* Default policy table. */ 932 uint32_t def_policy_id; 933 /* Default policy id. */ 934 uint32_t def_policy_ref_cnt; 935 /** def_policy meter use count. */ 936 struct mlx5_flow_tbl_resource *drop_tbl[MLX5_MTR_DOMAIN_MAX]; 937 /* Meter drop table. */ 938 struct mlx5_flow_dv_matcher * 939 drop_matcher[MLX5_MTR_DOMAIN_MAX][MLX5_REG_BITS]; 940 /* Matcher meter in drop table. */ 941 struct mlx5_flow_dv_matcher *def_matcher[MLX5_MTR_DOMAIN_MAX]; 942 /* Default matcher in drop table. */ 943 void *def_rule[MLX5_MTR_DOMAIN_MAX]; 944 /* Default rule in drop table. */ 945 uint8_t max_mtr_bits; 946 /* Indicate how many bits are used by meter id at the most. */ 947 uint8_t max_mtr_flow_bits; 948 /* Indicate how many bits are used by meter flow id at the most. */ 949 }; 950 951 /* Table key of the hash organization. */ 952 union mlx5_flow_tbl_key { 953 struct { 954 /* Table ID should be at the lowest address. */ 955 uint32_t level; /**< Level of the table. */ 956 uint32_t id:22; /**< ID of the table. */ 957 uint32_t dummy:1; /**< Dummy table for DV API. */ 958 uint32_t is_fdb:1; /**< 1 - FDB, 0 - NIC TX/RX. */ 959 uint32_t is_egress:1; /**< 1 - egress, 0 - ingress. */ 960 uint32_t reserved:7; /**< must be zero for comparison. */ 961 }; 962 uint64_t v64; /**< full 64bits value of key */ 963 }; 964 965 /* Table structure. */ 966 struct mlx5_flow_tbl_resource { 967 void *obj; /**< Pointer to DR table object. */ 968 uint32_t refcnt; /**< Reference counter. */ 969 }; 970 971 #define MLX5_MAX_TABLES UINT16_MAX 972 #define MLX5_HAIRPIN_TX_TABLE (UINT16_MAX - 1) 973 /* Reserve the last two tables for metadata register copy. */ 974 #define MLX5_FLOW_MREG_ACT_TABLE_GROUP (MLX5_MAX_TABLES - 1) 975 #define MLX5_FLOW_MREG_CP_TABLE_GROUP (MLX5_MAX_TABLES - 2) 976 /* Tables for metering splits should be added here. */ 977 #define MLX5_FLOW_TABLE_LEVEL_METER (MLX5_MAX_TABLES - 3) 978 #define MLX5_FLOW_TABLE_LEVEL_POLICY (MLX5_MAX_TABLES - 4) 979 #define MLX5_MAX_TABLES_EXTERNAL MLX5_FLOW_TABLE_LEVEL_POLICY 980 #define MLX5_MAX_TABLES_FDB UINT16_MAX 981 #define MLX5_FLOW_TABLE_FACTOR 10 982 983 /* ID generation structure. */ 984 struct mlx5_flow_id_pool { 985 uint32_t *free_arr; /**< Pointer to the a array of free values. */ 986 uint32_t base_index; 987 /**< The next index that can be used without any free elements. */ 988 uint32_t *curr; /**< Pointer to the index to pop. */ 989 uint32_t *last; /**< Pointer to the last element in the empty arrray. */ 990 uint32_t max_id; /**< Maximum id can be allocated from the pool. */ 991 }; 992 993 /* Tx pacing queue structure - for Clock and Rearm queues. */ 994 struct mlx5_txpp_wq { 995 /* Completion Queue related data.*/ 996 struct mlx5_devx_cq cq_obj; 997 uint32_t cq_ci:24; 998 uint32_t arm_sn:2; 999 /* Send Queue related data.*/ 1000 struct mlx5_devx_sq sq_obj; 1001 uint16_t sq_size; /* Number of WQEs in the queue. */ 1002 uint16_t sq_ci; /* Next WQE to execute. */ 1003 }; 1004 1005 /* Tx packet pacing internal timestamp. */ 1006 struct mlx5_txpp_ts { 1007 uint64_t ci_ts; 1008 uint64_t ts; 1009 }; 1010 1011 /* Tx packet pacing structure. */ 1012 struct mlx5_dev_txpp { 1013 pthread_mutex_t mutex; /* Pacing create/destroy mutex. */ 1014 uint32_t refcnt; /* Pacing reference counter. */ 1015 uint32_t freq; /* Timestamp frequency, Hz. */ 1016 uint32_t tick; /* Completion tick duration in nanoseconds. */ 1017 uint32_t test; /* Packet pacing test mode. */ 1018 int32_t skew; /* Scheduling skew. */ 1019 struct rte_intr_handle intr_handle; /* Periodic interrupt. */ 1020 void *echan; /* Event Channel. */ 1021 struct mlx5_txpp_wq clock_queue; /* Clock Queue. */ 1022 struct mlx5_txpp_wq rearm_queue; /* Clock Queue. */ 1023 void *pp; /* Packet pacing context. */ 1024 uint16_t pp_id; /* Packet pacing context index. */ 1025 uint16_t ts_n; /* Number of captured timestamps. */ 1026 uint16_t ts_p; /* Pointer to statisticks timestamp. */ 1027 struct mlx5_txpp_ts *tsa; /* Timestamps sliding window stats. */ 1028 struct mlx5_txpp_ts ts; /* Cached completion id/timestamp. */ 1029 uint32_t sync_lost:1; /* ci/timestamp synchronization lost. */ 1030 /* Statistics counters. */ 1031 uint64_t err_miss_int; /* Missed service interrupt. */ 1032 uint64_t err_rearm_queue; /* Rearm Queue errors. */ 1033 uint64_t err_clock_queue; /* Clock Queue errors. */ 1034 uint64_t err_ts_past; /* Timestamp in the past. */ 1035 uint64_t err_ts_future; /* Timestamp in the distant future. */ 1036 }; 1037 1038 /* Supported flex parser profile ID. */ 1039 enum mlx5_flex_parser_profile_id { 1040 MLX5_FLEX_PARSER_ECPRI_0 = 0, 1041 MLX5_FLEX_PARSER_MAX = 8, 1042 }; 1043 1044 /* Sample ID information of flex parser structure. */ 1045 struct mlx5_flex_parser_profiles { 1046 uint32_t num; /* Actual number of samples. */ 1047 uint32_t ids[8]; /* Sample IDs for this profile. */ 1048 uint8_t offset[8]; /* Bytes offset of each parser. */ 1049 void *obj; /* Flex parser node object. */ 1050 }; 1051 1052 /* Max member ports per bonding device. */ 1053 #define MLX5_BOND_MAX_PORTS 2 1054 1055 /* Bonding device information. */ 1056 struct mlx5_bond_info { 1057 int n_port; /* Number of bond member ports. */ 1058 uint32_t ifindex; 1059 char ifname[MLX5_NAMESIZE + 1]; 1060 struct { 1061 char ifname[MLX5_NAMESIZE + 1]; 1062 uint32_t ifindex; 1063 struct rte_pci_addr pci_addr; 1064 } ports[MLX5_BOND_MAX_PORTS]; 1065 }; 1066 1067 /* Number of connection tracking objects per pool: must be a power of 2. */ 1068 #define MLX5_ASO_CT_ACTIONS_PER_POOL 64 1069 1070 /* Generate incremental and unique CT index from pool and offset. */ 1071 #define MLX5_MAKE_CT_IDX(pool, offset) \ 1072 ((pool) * MLX5_ASO_CT_ACTIONS_PER_POOL + (offset) + 1) 1073 1074 /* ASO Conntrack state. */ 1075 enum mlx5_aso_ct_state { 1076 ASO_CONNTRACK_FREE, /* Inactive, in the free list. */ 1077 ASO_CONNTRACK_WAIT, /* WQE sent in the SQ. */ 1078 ASO_CONNTRACK_READY, /* CQE received w/o error. */ 1079 ASO_CONNTRACK_QUERY, /* WQE for query sent. */ 1080 ASO_CONNTRACK_MAX, /* Guard. */ 1081 }; 1082 1083 /* Generic ASO connection tracking structure. */ 1084 struct mlx5_aso_ct_action { 1085 LIST_ENTRY(mlx5_aso_ct_action) next; /* Pointer to the next ASO CT. */ 1086 void *dr_action_orig; /* General action object for original dir. */ 1087 void *dr_action_rply; /* General action object for reply dir. */ 1088 uint32_t refcnt; /* Action used count in device flows. */ 1089 uint16_t offset; /* Offset of ASO CT in DevX objects bulk. */ 1090 uint16_t peer; /* The only peer port index could also use this CT. */ 1091 enum mlx5_aso_ct_state state; /* ASO CT state. */ 1092 bool is_original; /* The direction of the DR action to be used. */ 1093 }; 1094 1095 /* CT action object state update. */ 1096 #define MLX5_ASO_CT_UPDATE_STATE(c, s) \ 1097 __atomic_store_n(&((c)->state), (s), __ATOMIC_RELAXED) 1098 1099 /* ASO connection tracking software pool definition. */ 1100 struct mlx5_aso_ct_pool { 1101 uint16_t index; /* Pool index in pools array. */ 1102 struct mlx5_devx_obj *devx_obj; 1103 /* The first devx object in the bulk, used for freeing (not yet). */ 1104 struct mlx5_aso_ct_action actions[MLX5_ASO_CT_ACTIONS_PER_POOL]; 1105 /* CT action structures bulk. */ 1106 }; 1107 1108 LIST_HEAD(aso_ct_list, mlx5_aso_ct_action); 1109 1110 /* Pools management structure for ASO connection tracking pools. */ 1111 struct mlx5_aso_ct_pools_mng { 1112 struct mlx5_aso_ct_pool **pools; 1113 uint16_t n; /* Total number of pools. */ 1114 uint16_t next; /* Number of pools in use, index of next free pool. */ 1115 rte_spinlock_t ct_sl; /* The ASO CT free list lock. */ 1116 rte_rwlock_t resize_rwl; /* The ASO CT pool resize lock. */ 1117 struct aso_ct_list free_cts; /* Free ASO CT objects list. */ 1118 struct mlx5_aso_sq aso_sq; /* ASO queue objects. */ 1119 }; 1120 1121 /* 1122 * Shared Infiniband device context for Master/Representors 1123 * which belong to same IB device with multiple IB ports. 1124 **/ 1125 struct mlx5_dev_ctx_shared { 1126 LIST_ENTRY(mlx5_dev_ctx_shared) next; 1127 uint32_t refcnt; 1128 uint32_t devx:1; /* Opened with DV. */ 1129 uint32_t flow_hit_aso_en:1; /* Flow Hit ASO is supported. */ 1130 uint32_t rq_ts_format:2; /* RQ timestamp formats supported. */ 1131 uint32_t sq_ts_format:2; /* SQ timestamp formats supported. */ 1132 uint32_t steering_format_version:4; 1133 /* Indicates the device steering logic format. */ 1134 uint32_t qp_ts_format:2; /* QP timestamp formats supported. */ 1135 uint32_t meter_aso_en:1; /* Flow Meter ASO is supported. */ 1136 uint32_t ct_aso_en:1; /* Connection Tracking ASO is supported. */ 1137 uint32_t tunnel_header_0_1:1; /* tunnel_header_0_1 is supported. */ 1138 uint32_t misc5_cap:1; /* misc5 matcher parameter is supported. */ 1139 uint32_t reclaim_mode:1; /* Reclaim memory. */ 1140 uint32_t max_port; /* Maximal IB device port index. */ 1141 struct mlx5_bond_info bond; /* Bonding information. */ 1142 void *ctx; /* Verbs/DV/DevX context. */ 1143 void *pd; /* Protection Domain. */ 1144 uint32_t pdn; /* Protection Domain number. */ 1145 uint32_t tdn; /* Transport Domain number. */ 1146 char ibdev_name[MLX5_FS_NAME_MAX]; /* SYSFS dev name. */ 1147 char ibdev_path[MLX5_FS_PATH_MAX]; /* SYSFS dev path for secondary */ 1148 struct mlx5_dev_attr device_attr; /* Device properties. */ 1149 int numa_node; /* Numa node of backing physical device. */ 1150 LIST_ENTRY(mlx5_dev_ctx_shared) mem_event_cb; 1151 /**< Called by memory event callback. */ 1152 struct mlx5_mr_share_cache share_cache; 1153 /* Packet pacing related structure. */ 1154 struct mlx5_dev_txpp txpp; 1155 /* Shared DV/DR flow data section. */ 1156 uint32_t dv_meta_mask; /* flow META metadata supported mask. */ 1157 uint32_t dv_mark_mask; /* flow MARK metadata supported mask. */ 1158 uint32_t dv_regc0_mask; /* available bits of metatada reg_c[0]. */ 1159 void *fdb_domain; /* FDB Direct Rules name space handle. */ 1160 void *rx_domain; /* RX Direct Rules name space handle. */ 1161 void *tx_domain; /* TX Direct Rules name space handle. */ 1162 #ifndef RTE_ARCH_64 1163 rte_spinlock_t uar_lock_cq; /* CQs share a common distinct UAR */ 1164 rte_spinlock_t uar_lock[MLX5_UAR_PAGE_NUM_MAX]; 1165 /* UAR same-page access control required in 32bit implementations. */ 1166 #endif 1167 struct mlx5_hlist *flow_tbls; 1168 struct mlx5_flow_tunnel_hub *tunnel_hub; 1169 /* Direct Rules tables for FDB, NIC TX+RX */ 1170 void *dr_drop_action; /* Pointer to DR drop action, any domain. */ 1171 void *pop_vlan_action; /* Pointer to DR pop VLAN action. */ 1172 struct mlx5_hlist *encaps_decaps; /* Encap/decap action hash list. */ 1173 struct mlx5_hlist *modify_cmds; 1174 struct mlx5_hlist *tag_table; 1175 struct mlx5_list *port_id_action_list; /* Port ID action list. */ 1176 struct mlx5_list *push_vlan_action_list; /* Push VLAN actions. */ 1177 struct mlx5_list *sample_action_list; /* List of sample actions. */ 1178 struct mlx5_list *dest_array_list; 1179 /* List of destination array actions. */ 1180 struct mlx5_flow_counter_mng cmng; /* Counters management structure. */ 1181 void *default_miss_action; /* Default miss action. */ 1182 struct mlx5_indexed_pool *ipool[MLX5_IPOOL_MAX]; 1183 struct mlx5_indexed_pool *mdh_ipools[MLX5_MAX_MODIFY_NUM]; 1184 /* Memory Pool for mlx5 flow resources. */ 1185 struct mlx5_l3t_tbl *cnt_id_tbl; /* Shared counter lookup table. */ 1186 /* Shared interrupt handler section. */ 1187 struct rte_intr_handle intr_handle; /* Interrupt handler for device. */ 1188 struct rte_intr_handle intr_handle_devx; /* DEVX interrupt handler. */ 1189 void *devx_comp; /* DEVX async comp obj. */ 1190 struct mlx5_devx_obj *tis; /* TIS object. */ 1191 struct mlx5_devx_obj *td; /* Transport domain. */ 1192 void *tx_uar; /* Tx/packet pacing shared UAR. */ 1193 struct mlx5_flex_parser_profiles fp[MLX5_FLEX_PARSER_MAX]; 1194 /* Flex parser profiles information. */ 1195 void *devx_rx_uar; /* DevX UAR for Rx. */ 1196 struct mlx5_aso_age_mng *aso_age_mng; 1197 /* Management data for aging mechanism using ASO Flow Hit. */ 1198 struct mlx5_geneve_tlv_option_resource *geneve_tlv_option_resource; 1199 /* Management structure for geneve tlv option */ 1200 rte_spinlock_t geneve_tlv_opt_sl; /* Lock for geneve tlv resource */ 1201 struct mlx5_flow_mtr_mng *mtrmng; 1202 /* Meter management structure. */ 1203 struct mlx5_aso_ct_pools_mng *ct_mng; 1204 /* Management data for ASO connection tracking. */ 1205 struct mlx5_lb_ctx self_lb; /* QP to enable self loopback for Devx. */ 1206 struct mlx5_dev_shared_port port[]; /* per device port data array. */ 1207 }; 1208 1209 /* 1210 * Per-process private structure. 1211 * Caution, secondary process may rebuild the struct during port start. 1212 */ 1213 struct mlx5_proc_priv { 1214 size_t uar_table_sz; 1215 /* Size of UAR register table. */ 1216 void *uar_table[]; 1217 /* Table of UAR registers for each process. */ 1218 }; 1219 1220 /* MTR profile list. */ 1221 TAILQ_HEAD(mlx5_mtr_profiles, mlx5_flow_meter_profile); 1222 /* MTR list. */ 1223 TAILQ_HEAD(mlx5_legacy_flow_meters, mlx5_legacy_flow_meter); 1224 1225 /* RSS description. */ 1226 struct mlx5_flow_rss_desc { 1227 uint32_t level; 1228 uint32_t queue_num; /**< Number of entries in @p queue. */ 1229 uint64_t types; /**< Specific RSS hash types (see ETH_RSS_*). */ 1230 uint64_t hash_fields; /* Verbs Hash fields. */ 1231 uint8_t key[MLX5_RSS_HASH_KEY_LEN]; /**< RSS hash key. */ 1232 uint32_t key_len; /**< RSS hash key len. */ 1233 uint32_t tunnel; /**< Queue in tunnel. */ 1234 uint32_t shared_rss; /**< Shared RSS index. */ 1235 struct mlx5_ind_table_obj *ind_tbl; 1236 /**< Indirection table for shared RSS hash RX queues. */ 1237 union { 1238 uint16_t *queue; /**< Destination queues. */ 1239 const uint16_t *const_q; /**< Const pointer convert. */ 1240 }; 1241 }; 1242 1243 #define MLX5_PROC_PRIV(port_id) \ 1244 ((struct mlx5_proc_priv *)rte_eth_devices[port_id].process_private) 1245 1246 /* Verbs/DevX Rx queue elements. */ 1247 struct mlx5_rxq_obj { 1248 LIST_ENTRY(mlx5_rxq_obj) next; /* Pointer to the next element. */ 1249 struct mlx5_rxq_ctrl *rxq_ctrl; /* Back pointer to parent. */ 1250 int fd; /* File descriptor for event channel */ 1251 RTE_STD_C11 1252 union { 1253 struct { 1254 void *wq; /* Work Queue. */ 1255 void *ibv_cq; /* Completion Queue. */ 1256 void *ibv_channel; 1257 }; 1258 struct mlx5_devx_obj *rq; /* DevX RQ object for hairpin. */ 1259 struct { 1260 struct mlx5_devx_rq rq_obj; /* DevX RQ object. */ 1261 struct mlx5_devx_cq cq_obj; /* DevX CQ object. */ 1262 void *devx_channel; 1263 }; 1264 }; 1265 }; 1266 1267 /* Indirection table. */ 1268 struct mlx5_ind_table_obj { 1269 LIST_ENTRY(mlx5_ind_table_obj) next; /* Pointer to the next element. */ 1270 uint32_t refcnt; /* Reference counter. */ 1271 RTE_STD_C11 1272 union { 1273 void *ind_table; /**< Indirection table. */ 1274 struct mlx5_devx_obj *rqt; /* DevX RQT object. */ 1275 }; 1276 uint32_t queues_n; /**< Number of queues in the list. */ 1277 uint16_t *queues; /**< Queue list. */ 1278 }; 1279 1280 /* Hash Rx queue. */ 1281 __extension__ 1282 struct mlx5_hrxq { 1283 struct mlx5_list_entry entry; /* List entry. */ 1284 uint32_t standalone:1; /* This object used in shared action. */ 1285 struct mlx5_ind_table_obj *ind_table; /* Indirection table. */ 1286 RTE_STD_C11 1287 union { 1288 void *qp; /* Verbs queue pair. */ 1289 struct mlx5_devx_obj *tir; /* DevX TIR object. */ 1290 }; 1291 #if defined(HAVE_IBV_FLOW_DV_SUPPORT) || !defined(HAVE_INFINIBAND_VERBS_H) 1292 void *action; /* DV QP action pointer. */ 1293 #endif 1294 uint64_t hash_fields; /* Verbs Hash fields. */ 1295 uint32_t rss_key_len; /* Hash key length in bytes. */ 1296 uint32_t idx; /* Hash Rx queue index. */ 1297 uint8_t rss_key[]; /* Hash key. */ 1298 }; 1299 1300 /* Verbs/DevX Tx queue elements. */ 1301 struct mlx5_txq_obj { 1302 LIST_ENTRY(mlx5_txq_obj) next; /* Pointer to the next element. */ 1303 struct mlx5_txq_ctrl *txq_ctrl; /* Pointer to the control queue. */ 1304 RTE_STD_C11 1305 union { 1306 struct { 1307 void *cq; /* Completion Queue. */ 1308 void *qp; /* Queue Pair. */ 1309 }; 1310 struct { 1311 struct mlx5_devx_obj *sq; 1312 /* DevX object for Sx queue. */ 1313 struct mlx5_devx_obj *tis; /* The TIS object. */ 1314 }; 1315 struct { 1316 struct rte_eth_dev *dev; 1317 struct mlx5_devx_cq cq_obj; 1318 /* DevX CQ object and its resources. */ 1319 struct mlx5_devx_sq sq_obj; 1320 /* DevX SQ object and its resources. */ 1321 }; 1322 }; 1323 }; 1324 1325 enum mlx5_rxq_modify_type { 1326 MLX5_RXQ_MOD_ERR2RST, /* modify state from error to reset. */ 1327 MLX5_RXQ_MOD_RST2RDY, /* modify state from reset to ready. */ 1328 MLX5_RXQ_MOD_RDY2ERR, /* modify state from ready to error. */ 1329 MLX5_RXQ_MOD_RDY2RST, /* modify state from ready to reset. */ 1330 }; 1331 1332 enum mlx5_txq_modify_type { 1333 MLX5_TXQ_MOD_RST2RDY, /* modify state from reset to ready. */ 1334 MLX5_TXQ_MOD_RDY2RST, /* modify state from ready to reset. */ 1335 MLX5_TXQ_MOD_ERR2RDY, /* modify state from error to ready. */ 1336 }; 1337 1338 /* HW objects operations structure. */ 1339 struct mlx5_obj_ops { 1340 int (*rxq_obj_modify_vlan_strip)(struct mlx5_rxq_obj *rxq_obj, int on); 1341 int (*rxq_obj_new)(struct rte_eth_dev *dev, uint16_t idx); 1342 int (*rxq_event_get)(struct mlx5_rxq_obj *rxq_obj); 1343 int (*rxq_obj_modify)(struct mlx5_rxq_obj *rxq_obj, uint8_t type); 1344 void (*rxq_obj_release)(struct mlx5_rxq_obj *rxq_obj); 1345 int (*ind_table_new)(struct rte_eth_dev *dev, const unsigned int log_n, 1346 struct mlx5_ind_table_obj *ind_tbl); 1347 int (*ind_table_modify)(struct rte_eth_dev *dev, 1348 const unsigned int log_n, 1349 const uint16_t *queues, const uint32_t queues_n, 1350 struct mlx5_ind_table_obj *ind_tbl); 1351 void (*ind_table_destroy)(struct mlx5_ind_table_obj *ind_tbl); 1352 int (*hrxq_new)(struct rte_eth_dev *dev, struct mlx5_hrxq *hrxq, 1353 int tunnel __rte_unused); 1354 int (*hrxq_modify)(struct rte_eth_dev *dev, struct mlx5_hrxq *hrxq, 1355 const uint8_t *rss_key, 1356 uint64_t hash_fields, 1357 const struct mlx5_ind_table_obj *ind_tbl); 1358 void (*hrxq_destroy)(struct mlx5_hrxq *hrxq); 1359 int (*drop_action_create)(struct rte_eth_dev *dev); 1360 void (*drop_action_destroy)(struct rte_eth_dev *dev); 1361 int (*txq_obj_new)(struct rte_eth_dev *dev, uint16_t idx); 1362 int (*txq_obj_modify)(struct mlx5_txq_obj *obj, 1363 enum mlx5_txq_modify_type type, uint8_t dev_port); 1364 void (*txq_obj_release)(struct mlx5_txq_obj *txq_obj); 1365 int (*lb_dummy_queue_create)(struct rte_eth_dev *dev); 1366 void (*lb_dummy_queue_release)(struct rte_eth_dev *dev); 1367 }; 1368 1369 #define MLX5_RSS_HASH_FIELDS_LEN RTE_DIM(mlx5_rss_hash_fields) 1370 1371 /* MR operations structure. */ 1372 struct mlx5_mr_ops { 1373 mlx5_reg_mr_t reg_mr; 1374 mlx5_dereg_mr_t dereg_mr; 1375 }; 1376 1377 struct mlx5_priv { 1378 struct rte_eth_dev_data *dev_data; /* Pointer to device data. */ 1379 struct mlx5_dev_ctx_shared *sh; /* Shared device context. */ 1380 uint32_t dev_port; /* Device port number. */ 1381 struct rte_pci_device *pci_dev; /* Backend PCI device. */ 1382 struct rte_ether_addr mac[MLX5_MAX_MAC_ADDRESSES]; /* MAC addresses. */ 1383 BITFIELD_DECLARE(mac_own, uint64_t, MLX5_MAX_MAC_ADDRESSES); 1384 /* Bit-field of MAC addresses owned by the PMD. */ 1385 uint16_t vlan_filter[MLX5_MAX_VLAN_IDS]; /* VLAN filters table. */ 1386 unsigned int vlan_filter_n; /* Number of configured VLAN filters. */ 1387 /* Device properties. */ 1388 uint16_t mtu; /* Configured MTU. */ 1389 unsigned int isolated:1; /* Whether isolated mode is enabled. */ 1390 unsigned int representor:1; /* Device is a port representor. */ 1391 unsigned int master:1; /* Device is a E-Switch master. */ 1392 unsigned int txpp_en:1; /* Tx packet pacing enabled. */ 1393 unsigned int sampler_en:1; /* Whether support sampler. */ 1394 unsigned int mtr_en:1; /* Whether support meter. */ 1395 unsigned int mtr_reg_share:1; /* Whether support meter REG_C share. */ 1396 unsigned int lb_used:1; /* Loopback queue is referred to. */ 1397 uint16_t domain_id; /* Switch domain identifier. */ 1398 uint16_t vport_id; /* Associated VF vport index (if any). */ 1399 uint32_t vport_meta_tag; /* Used for vport index match ove VF LAG. */ 1400 uint32_t vport_meta_mask; /* Used for vport index field match mask. */ 1401 uint16_t representor_id; /* UINT16_MAX if not a representor. */ 1402 int32_t pf_bond; /* >=0, representor owner PF index in bonding. */ 1403 unsigned int if_index; /* Associated kernel network device index. */ 1404 /* RX/TX queues. */ 1405 unsigned int rxqs_n; /* RX queues array size. */ 1406 unsigned int txqs_n; /* TX queues array size. */ 1407 struct mlx5_rxq_data *(*rxqs)[]; /* RX queues. */ 1408 struct mlx5_txq_data *(*txqs)[]; /* TX queues. */ 1409 struct rte_mempool *mprq_mp; /* Mempool for Multi-Packet RQ. */ 1410 struct rte_eth_rss_conf rss_conf; /* RSS configuration. */ 1411 unsigned int (*reta_idx)[]; /* RETA index table. */ 1412 unsigned int reta_idx_n; /* RETA index size. */ 1413 struct mlx5_drop drop_queue; /* Flow drop queues. */ 1414 void *root_drop_action; /* Pointer to root drop action. */ 1415 struct mlx5_indexed_pool *flows[MLX5_FLOW_TYPE_MAXI]; 1416 /* RTE Flow rules. */ 1417 uint32_t ctrl_flows; /* Control flow rules. */ 1418 rte_spinlock_t flow_list_lock; 1419 struct mlx5_obj_ops obj_ops; /* HW objects operations. */ 1420 LIST_HEAD(rxq, mlx5_rxq_ctrl) rxqsctrl; /* DPDK Rx queues. */ 1421 LIST_HEAD(rxqobj, mlx5_rxq_obj) rxqsobj; /* Verbs/DevX Rx queues. */ 1422 struct mlx5_list *hrxqs; /* Hash Rx queues. */ 1423 LIST_HEAD(txq, mlx5_txq_ctrl) txqsctrl; /* DPDK Tx queues. */ 1424 LIST_HEAD(txqobj, mlx5_txq_obj) txqsobj; /* Verbs/DevX Tx queues. */ 1425 /* Indirection tables. */ 1426 LIST_HEAD(ind_tables, mlx5_ind_table_obj) ind_tbls; 1427 /* Pointer to next element. */ 1428 rte_rwlock_t ind_tbls_lock; 1429 uint32_t refcnt; /**< Reference counter. */ 1430 /**< Verbs modify header action object. */ 1431 uint8_t ft_type; /**< Flow table type, Rx or Tx. */ 1432 uint8_t max_lro_msg_size; 1433 uint32_t link_speed_capa; /* Link speed capabilities. */ 1434 struct mlx5_xstats_ctrl xstats_ctrl; /* Extended stats control. */ 1435 struct mlx5_stats_ctrl stats_ctrl; /* Stats control. */ 1436 struct mlx5_dev_config config; /* Device configuration. */ 1437 /* Context for Verbs allocator. */ 1438 int nl_socket_rdma; /* Netlink socket (NETLINK_RDMA). */ 1439 int nl_socket_route; /* Netlink socket (NETLINK_ROUTE). */ 1440 struct mlx5_nl_vlan_vmwa_context *vmwa_context; /* VLAN WA context. */ 1441 struct mlx5_hlist *mreg_cp_tbl; 1442 /* Hash table of Rx metadata register copy table. */ 1443 uint8_t mtr_sfx_reg; /* Meter prefix-suffix flow match REG_C. */ 1444 uint8_t mtr_color_reg; /* Meter color match REG_C. */ 1445 struct mlx5_legacy_flow_meters flow_meters; /* MTR list. */ 1446 struct mlx5_l3t_tbl *mtr_profile_tbl; /* Meter index lookup table. */ 1447 struct mlx5_l3t_tbl *policy_idx_tbl; /* Policy index lookup table. */ 1448 struct mlx5_l3t_tbl *mtr_idx_tbl; /* Meter index lookup table. */ 1449 uint8_t skip_default_rss_reta; /* Skip configuration of default reta. */ 1450 uint8_t fdb_def_rule; /* Whether fdb jump to table 1 is configured. */ 1451 struct mlx5_mp_id mp_id; /* ID of a multi-process process */ 1452 LIST_HEAD(fdir, mlx5_fdir_flow) fdir_flows; /* fdir flows. */ 1453 rte_spinlock_t shared_act_sl; /* Shared actions spinlock. */ 1454 uint32_t rss_shared_actions; /* RSS shared actions. */ 1455 struct mlx5_devx_obj *q_counters; /* DevX queue counter object. */ 1456 uint32_t counter_set_id; /* Queue counter ID to set in DevX objects. */ 1457 }; 1458 1459 #define PORT_ID(priv) ((priv)->dev_data->port_id) 1460 #define ETH_DEV(priv) (&rte_eth_devices[PORT_ID(priv)]) 1461 1462 struct rte_hairpin_peer_info { 1463 uint32_t qp_id; 1464 uint32_t vhca_id; 1465 uint16_t peer_q; 1466 uint16_t tx_explicit; 1467 uint16_t manual_bind; 1468 }; 1469 1470 #define BUF_SIZE 1024 1471 enum dr_dump_rec_type { 1472 DR_DUMP_REC_TYPE_PMD_PKT_REFORMAT = 4410, 1473 DR_DUMP_REC_TYPE_PMD_MODIFY_HDR = 4420, 1474 DR_DUMP_REC_TYPE_PMD_COUNTER = 4430, 1475 }; 1476 1477 /* mlx5.c */ 1478 1479 int mlx5_getenv_int(const char *); 1480 int mlx5_proc_priv_init(struct rte_eth_dev *dev); 1481 void mlx5_proc_priv_uninit(struct rte_eth_dev *dev); 1482 int mlx5_udp_tunnel_port_add(struct rte_eth_dev *dev, 1483 struct rte_eth_udp_tunnel *udp_tunnel); 1484 uint16_t mlx5_eth_find_next(uint16_t port_id, struct rte_device *odev); 1485 int mlx5_dev_close(struct rte_eth_dev *dev); 1486 int mlx5_net_remove(struct rte_device *dev); 1487 bool mlx5_is_hpf(struct rte_eth_dev *dev); 1488 bool mlx5_is_sf_repr(struct rte_eth_dev *dev); 1489 void mlx5_age_event_prepare(struct mlx5_dev_ctx_shared *sh); 1490 1491 /* Macro to iterate over all valid ports for mlx5 driver. */ 1492 #define MLX5_ETH_FOREACH_DEV(port_id, dev) \ 1493 for (port_id = mlx5_eth_find_next(0, dev); \ 1494 port_id < RTE_MAX_ETHPORTS; \ 1495 port_id = mlx5_eth_find_next(port_id + 1, dev)) 1496 int mlx5_args(struct mlx5_dev_config *config, struct rte_devargs *devargs); 1497 struct mlx5_dev_ctx_shared * 1498 mlx5_alloc_shared_dev_ctx(const struct mlx5_dev_spawn_data *spawn, 1499 const struct mlx5_dev_config *config); 1500 void mlx5_free_shared_dev_ctx(struct mlx5_dev_ctx_shared *sh); 1501 void mlx5_free_table_hash_list(struct mlx5_priv *priv); 1502 int mlx5_alloc_table_hash_list(struct mlx5_priv *priv); 1503 void mlx5_set_min_inline(struct mlx5_dev_spawn_data *spawn, 1504 struct mlx5_dev_config *config); 1505 void mlx5_set_metadata_mask(struct rte_eth_dev *dev); 1506 int mlx5_dev_check_sibling_config(struct mlx5_priv *priv, 1507 struct mlx5_dev_config *config, 1508 struct rte_device *dpdk_dev); 1509 int mlx5_dev_configure(struct rte_eth_dev *dev); 1510 int mlx5_dev_infos_get(struct rte_eth_dev *dev, struct rte_eth_dev_info *info); 1511 int mlx5_fw_version_get(struct rte_eth_dev *dev, char *fw_ver, size_t fw_size); 1512 int mlx5_dev_set_mtu(struct rte_eth_dev *dev, uint16_t mtu); 1513 int mlx5_hairpin_cap_get(struct rte_eth_dev *dev, 1514 struct rte_eth_hairpin_cap *cap); 1515 bool mlx5_flex_parser_ecpri_exist(struct rte_eth_dev *dev); 1516 int mlx5_flex_parser_ecpri_alloc(struct rte_eth_dev *dev); 1517 int mlx5_flow_aso_age_mng_init(struct mlx5_dev_ctx_shared *sh); 1518 int mlx5_aso_flow_mtrs_mng_init(struct mlx5_dev_ctx_shared *sh); 1519 int mlx5_flow_aso_ct_mng_init(struct mlx5_dev_ctx_shared *sh); 1520 1521 /* mlx5_ethdev.c */ 1522 1523 int mlx5_dev_configure(struct rte_eth_dev *dev); 1524 int mlx5_representor_info_get(struct rte_eth_dev *dev, 1525 struct rte_eth_representor_info *info); 1526 #define MLX5_REPRESENTOR_ID(pf, type, repr) \ 1527 (((pf) << 14) + ((type) << 12) + ((repr) & 0xfff)) 1528 #define MLX5_REPRESENTOR_REPR(repr_id) \ 1529 ((repr_id) & 0xfff) 1530 #define MLX5_REPRESENTOR_TYPE(repr_id) \ 1531 (((repr_id) >> 12) & 3) 1532 uint16_t mlx5_representor_id_encode(const struct mlx5_switch_info *info, 1533 enum rte_eth_representor_type hpf_type); 1534 int mlx5_fw_version_get(struct rte_eth_dev *dev, char *fw_ver, 1535 size_t fw_size); 1536 int mlx5_dev_infos_get(struct rte_eth_dev *dev, 1537 struct rte_eth_dev_info *info); 1538 const uint32_t *mlx5_dev_supported_ptypes_get(struct rte_eth_dev *dev); 1539 int mlx5_dev_set_mtu(struct rte_eth_dev *dev, uint16_t mtu); 1540 int mlx5_hairpin_cap_get(struct rte_eth_dev *dev, 1541 struct rte_eth_hairpin_cap *cap); 1542 eth_rx_burst_t mlx5_select_rx_function(struct rte_eth_dev *dev); 1543 struct mlx5_priv *mlx5_port_to_eswitch_info(uint16_t port, bool valid); 1544 struct mlx5_priv *mlx5_dev_to_eswitch_info(struct rte_eth_dev *dev); 1545 int mlx5_dev_configure_rss_reta(struct rte_eth_dev *dev); 1546 1547 /* mlx5_ethdev_os.c */ 1548 1549 int mlx5_get_ifname(const struct rte_eth_dev *dev, 1550 char (*ifname)[MLX5_NAMESIZE]); 1551 unsigned int mlx5_ifindex(const struct rte_eth_dev *dev); 1552 int mlx5_get_mac(struct rte_eth_dev *dev, uint8_t (*mac)[RTE_ETHER_ADDR_LEN]); 1553 int mlx5_get_mtu(struct rte_eth_dev *dev, uint16_t *mtu); 1554 int mlx5_set_mtu(struct rte_eth_dev *dev, uint16_t mtu); 1555 int mlx5_read_clock(struct rte_eth_dev *dev, uint64_t *clock); 1556 int mlx5_link_update(struct rte_eth_dev *dev, int wait_to_complete); 1557 int mlx5_dev_get_flow_ctrl(struct rte_eth_dev *dev, 1558 struct rte_eth_fc_conf *fc_conf); 1559 int mlx5_dev_set_flow_ctrl(struct rte_eth_dev *dev, 1560 struct rte_eth_fc_conf *fc_conf); 1561 void mlx5_dev_interrupt_handler(void *arg); 1562 void mlx5_dev_interrupt_handler_devx(void *arg); 1563 int mlx5_set_link_down(struct rte_eth_dev *dev); 1564 int mlx5_set_link_up(struct rte_eth_dev *dev); 1565 int mlx5_is_removed(struct rte_eth_dev *dev); 1566 int mlx5_sysfs_switch_info(unsigned int ifindex, 1567 struct mlx5_switch_info *info); 1568 void mlx5_translate_port_name(const char *port_name_in, 1569 struct mlx5_switch_info *port_info_out); 1570 void mlx5_intr_callback_unregister(const struct rte_intr_handle *handle, 1571 rte_intr_callback_fn cb_fn, void *cb_arg); 1572 int mlx5_sysfs_bond_info(unsigned int pf_ifindex, unsigned int *ifindex, 1573 char *ifname); 1574 int mlx5_get_module_info(struct rte_eth_dev *dev, 1575 struct rte_eth_dev_module_info *modinfo); 1576 int mlx5_get_module_eeprom(struct rte_eth_dev *dev, 1577 struct rte_dev_eeprom_info *info); 1578 int mlx5_os_read_dev_stat(struct mlx5_priv *priv, 1579 const char *ctr_name, uint64_t *stat); 1580 int mlx5_os_read_dev_counters(struct rte_eth_dev *dev, uint64_t *stats); 1581 int mlx5_os_get_stats_n(struct rte_eth_dev *dev); 1582 void mlx5_os_stats_init(struct rte_eth_dev *dev); 1583 1584 /* mlx5_mac.c */ 1585 1586 void mlx5_mac_addr_remove(struct rte_eth_dev *dev, uint32_t index); 1587 int mlx5_mac_addr_add(struct rte_eth_dev *dev, struct rte_ether_addr *mac, 1588 uint32_t index, uint32_t vmdq); 1589 int mlx5_mac_addr_set(struct rte_eth_dev *dev, struct rte_ether_addr *mac_addr); 1590 int mlx5_set_mc_addr_list(struct rte_eth_dev *dev, 1591 struct rte_ether_addr *mc_addr_set, 1592 uint32_t nb_mc_addr); 1593 1594 /* mlx5_rss.c */ 1595 1596 int mlx5_rss_hash_update(struct rte_eth_dev *dev, 1597 struct rte_eth_rss_conf *rss_conf); 1598 int mlx5_rss_hash_conf_get(struct rte_eth_dev *dev, 1599 struct rte_eth_rss_conf *rss_conf); 1600 int mlx5_rss_reta_index_resize(struct rte_eth_dev *dev, unsigned int reta_size); 1601 int mlx5_dev_rss_reta_query(struct rte_eth_dev *dev, 1602 struct rte_eth_rss_reta_entry64 *reta_conf, 1603 uint16_t reta_size); 1604 int mlx5_dev_rss_reta_update(struct rte_eth_dev *dev, 1605 struct rte_eth_rss_reta_entry64 *reta_conf, 1606 uint16_t reta_size); 1607 1608 /* mlx5_rxmode.c */ 1609 1610 int mlx5_promiscuous_enable(struct rte_eth_dev *dev); 1611 int mlx5_promiscuous_disable(struct rte_eth_dev *dev); 1612 int mlx5_allmulticast_enable(struct rte_eth_dev *dev); 1613 int mlx5_allmulticast_disable(struct rte_eth_dev *dev); 1614 1615 /* mlx5_stats.c */ 1616 1617 int mlx5_stats_get(struct rte_eth_dev *dev, struct rte_eth_stats *stats); 1618 int mlx5_stats_reset(struct rte_eth_dev *dev); 1619 int mlx5_xstats_get(struct rte_eth_dev *dev, struct rte_eth_xstat *stats, 1620 unsigned int n); 1621 int mlx5_xstats_reset(struct rte_eth_dev *dev); 1622 int mlx5_xstats_get_names(struct rte_eth_dev *dev __rte_unused, 1623 struct rte_eth_xstat_name *xstats_names, 1624 unsigned int n); 1625 1626 /* mlx5_vlan.c */ 1627 1628 int mlx5_vlan_filter_set(struct rte_eth_dev *dev, uint16_t vlan_id, int on); 1629 void mlx5_vlan_strip_queue_set(struct rte_eth_dev *dev, uint16_t queue, int on); 1630 int mlx5_vlan_offload_set(struct rte_eth_dev *dev, int mask); 1631 1632 /* mlx5_vlan_os.c */ 1633 1634 void mlx5_vlan_vmwa_exit(void *ctx); 1635 void mlx5_vlan_vmwa_release(struct rte_eth_dev *dev, 1636 struct mlx5_vf_vlan *vf_vlan); 1637 void mlx5_vlan_vmwa_acquire(struct rte_eth_dev *dev, 1638 struct mlx5_vf_vlan *vf_vlan); 1639 void *mlx5_vlan_vmwa_init(struct rte_eth_dev *dev, uint32_t ifindex); 1640 1641 /* mlx5_trigger.c */ 1642 1643 int mlx5_dev_start(struct rte_eth_dev *dev); 1644 int mlx5_dev_stop(struct rte_eth_dev *dev); 1645 int mlx5_traffic_enable(struct rte_eth_dev *dev); 1646 void mlx5_traffic_disable(struct rte_eth_dev *dev); 1647 int mlx5_traffic_restart(struct rte_eth_dev *dev); 1648 int mlx5_hairpin_queue_peer_update(struct rte_eth_dev *dev, uint16_t peer_queue, 1649 struct rte_hairpin_peer_info *current_info, 1650 struct rte_hairpin_peer_info *peer_info, 1651 uint32_t direction); 1652 int mlx5_hairpin_queue_peer_bind(struct rte_eth_dev *dev, uint16_t cur_queue, 1653 struct rte_hairpin_peer_info *peer_info, 1654 uint32_t direction); 1655 int mlx5_hairpin_queue_peer_unbind(struct rte_eth_dev *dev, uint16_t cur_queue, 1656 uint32_t direction); 1657 int mlx5_hairpin_bind(struct rte_eth_dev *dev, uint16_t rx_port); 1658 int mlx5_hairpin_unbind(struct rte_eth_dev *dev, uint16_t rx_port); 1659 int mlx5_hairpin_get_peer_ports(struct rte_eth_dev *dev, uint16_t *peer_ports, 1660 size_t len, uint32_t direction); 1661 1662 /* mlx5_flow.c */ 1663 1664 int mlx5_flow_discover_mreg_c(struct rte_eth_dev *eth_dev); 1665 bool mlx5_flow_ext_mreg_supported(struct rte_eth_dev *dev); 1666 void mlx5_flow_print(struct rte_flow *flow); 1667 int mlx5_flow_validate(struct rte_eth_dev *dev, 1668 const struct rte_flow_attr *attr, 1669 const struct rte_flow_item items[], 1670 const struct rte_flow_action actions[], 1671 struct rte_flow_error *error); 1672 struct rte_flow *mlx5_flow_create(struct rte_eth_dev *dev, 1673 const struct rte_flow_attr *attr, 1674 const struct rte_flow_item items[], 1675 const struct rte_flow_action actions[], 1676 struct rte_flow_error *error); 1677 int mlx5_flow_destroy(struct rte_eth_dev *dev, struct rte_flow *flow, 1678 struct rte_flow_error *error); 1679 void mlx5_flow_list_flush(struct rte_eth_dev *dev, enum mlx5_flow_type type, 1680 bool active); 1681 int mlx5_flow_flush(struct rte_eth_dev *dev, struct rte_flow_error *error); 1682 int mlx5_flow_query(struct rte_eth_dev *dev, struct rte_flow *flow, 1683 const struct rte_flow_action *action, void *data, 1684 struct rte_flow_error *error); 1685 int mlx5_flow_isolate(struct rte_eth_dev *dev, int enable, 1686 struct rte_flow_error *error); 1687 int mlx5_flow_ops_get(struct rte_eth_dev *dev, const struct rte_flow_ops **ops); 1688 int mlx5_flow_start_default(struct rte_eth_dev *dev); 1689 void mlx5_flow_stop_default(struct rte_eth_dev *dev); 1690 int mlx5_flow_verify(struct rte_eth_dev *dev); 1691 int mlx5_ctrl_flow_source_queue(struct rte_eth_dev *dev, uint32_t queue); 1692 int mlx5_ctrl_flow_vlan(struct rte_eth_dev *dev, 1693 struct rte_flow_item_eth *eth_spec, 1694 struct rte_flow_item_eth *eth_mask, 1695 struct rte_flow_item_vlan *vlan_spec, 1696 struct rte_flow_item_vlan *vlan_mask); 1697 int mlx5_ctrl_flow(struct rte_eth_dev *dev, 1698 struct rte_flow_item_eth *eth_spec, 1699 struct rte_flow_item_eth *eth_mask); 1700 int mlx5_flow_lacp_miss(struct rte_eth_dev *dev); 1701 struct rte_flow *mlx5_flow_create_esw_table_zero_flow(struct rte_eth_dev *dev); 1702 void mlx5_flow_async_pool_query_handle(struct mlx5_dev_ctx_shared *sh, 1703 uint64_t async_id, int status); 1704 void mlx5_set_query_alarm(struct mlx5_dev_ctx_shared *sh); 1705 void mlx5_flow_query_alarm(void *arg); 1706 uint32_t mlx5_counter_alloc(struct rte_eth_dev *dev); 1707 void mlx5_counter_free(struct rte_eth_dev *dev, uint32_t cnt); 1708 int mlx5_counter_query(struct rte_eth_dev *dev, uint32_t cnt, 1709 bool clear, uint64_t *pkts, uint64_t *bytes); 1710 int mlx5_flow_dev_dump(struct rte_eth_dev *dev, struct rte_flow *flow, 1711 FILE *file, struct rte_flow_error *error); 1712 int save_dump_file(const unsigned char *data, uint32_t size, 1713 uint32_t type, uint32_t id, void *arg, FILE *file); 1714 int mlx5_flow_query_counter(struct rte_eth_dev *dev, struct rte_flow *flow, 1715 struct rte_flow_query_count *count, struct rte_flow_error *error); 1716 #ifdef HAVE_IBV_FLOW_DV_SUPPORT 1717 int mlx5_flow_dev_dump_ipool(struct rte_eth_dev *dev, struct rte_flow *flow, 1718 FILE *file, struct rte_flow_error *error); 1719 #endif 1720 void mlx5_flow_rxq_dynf_metadata_set(struct rte_eth_dev *dev); 1721 int mlx5_flow_get_aged_flows(struct rte_eth_dev *dev, void **contexts, 1722 uint32_t nb_contexts, struct rte_flow_error *error); 1723 int mlx5_validate_action_ct(struct rte_eth_dev *dev, 1724 const struct rte_flow_action_conntrack *conntrack, 1725 struct rte_flow_error *error); 1726 1727 1728 /* mlx5_mp_os.c */ 1729 1730 int mlx5_mp_os_primary_handle(const struct rte_mp_msg *mp_msg, 1731 const void *peer); 1732 int mlx5_mp_os_secondary_handle(const struct rte_mp_msg *mp_msg, 1733 const void *peer); 1734 void mlx5_mp_os_req_start_rxtx(struct rte_eth_dev *dev); 1735 void mlx5_mp_os_req_stop_rxtx(struct rte_eth_dev *dev); 1736 int mlx5_mp_os_req_queue_control(struct rte_eth_dev *dev, uint16_t queue_id, 1737 enum mlx5_mp_req_type req_type); 1738 1739 /* mlx5_socket.c */ 1740 1741 int mlx5_pmd_socket_init(void); 1742 1743 /* mlx5_flow_meter.c */ 1744 1745 int mlx5_flow_meter_ops_get(struct rte_eth_dev *dev, void *arg); 1746 struct mlx5_flow_meter_info *mlx5_flow_meter_find(struct mlx5_priv *priv, 1747 uint32_t meter_id, uint32_t *mtr_idx); 1748 struct mlx5_flow_meter_info * 1749 flow_dv_meter_find_by_idx(struct mlx5_priv *priv, uint32_t idx); 1750 int mlx5_flow_meter_attach(struct mlx5_priv *priv, 1751 struct mlx5_flow_meter_info *fm, 1752 const struct rte_flow_attr *attr, 1753 struct rte_flow_error *error); 1754 void mlx5_flow_meter_detach(struct mlx5_priv *priv, 1755 struct mlx5_flow_meter_info *fm); 1756 struct mlx5_flow_meter_policy *mlx5_flow_meter_policy_find 1757 (struct rte_eth_dev *dev, 1758 uint32_t policy_id, 1759 uint32_t *policy_idx); 1760 struct mlx5_flow_meter_policy * 1761 mlx5_flow_meter_hierarchy_get_final_policy(struct rte_eth_dev *dev, 1762 struct mlx5_flow_meter_policy *policy); 1763 int mlx5_flow_meter_flush(struct rte_eth_dev *dev, 1764 struct rte_mtr_error *error); 1765 void mlx5_flow_meter_rxq_flush(struct rte_eth_dev *dev); 1766 1767 /* mlx5_os.c */ 1768 struct rte_pci_driver; 1769 int mlx5_os_get_dev_attr(void *ctx, struct mlx5_dev_attr *dev_attr); 1770 void mlx5_os_free_shared_dr(struct mlx5_priv *priv); 1771 int mlx5_os_open_device(const struct mlx5_dev_spawn_data *spawn, 1772 const struct mlx5_dev_config *config, 1773 struct mlx5_dev_ctx_shared *sh); 1774 int mlx5_os_get_pdn(void *pd, uint32_t *pdn); 1775 int mlx5_os_net_probe(struct rte_device *dev); 1776 void mlx5_os_dev_shared_handler_install(struct mlx5_dev_ctx_shared *sh); 1777 void mlx5_os_dev_shared_handler_uninstall(struct mlx5_dev_ctx_shared *sh); 1778 void mlx5_os_set_reg_mr_cb(mlx5_reg_mr_t *reg_mr_cb, 1779 mlx5_dereg_mr_t *dereg_mr_cb); 1780 void mlx5_os_mac_addr_remove(struct rte_eth_dev *dev, uint32_t index); 1781 int mlx5_os_mac_addr_add(struct rte_eth_dev *dev, struct rte_ether_addr *mac, 1782 uint32_t index); 1783 int mlx5_os_vf_mac_addr_modify(struct mlx5_priv *priv, unsigned int iface_idx, 1784 struct rte_ether_addr *mac_addr, 1785 int vf_index); 1786 int mlx5_os_set_promisc(struct rte_eth_dev *dev, int enable); 1787 int mlx5_os_set_allmulti(struct rte_eth_dev *dev, int enable); 1788 int mlx5_os_set_nonblock_channel_fd(int fd); 1789 void mlx5_os_mac_addr_flush(struct rte_eth_dev *dev); 1790 1791 /* mlx5_txpp.c */ 1792 1793 int mlx5_txpp_start(struct rte_eth_dev *dev); 1794 void mlx5_txpp_stop(struct rte_eth_dev *dev); 1795 int mlx5_txpp_read_clock(struct rte_eth_dev *dev, uint64_t *timestamp); 1796 int mlx5_txpp_xstats_get(struct rte_eth_dev *dev, 1797 struct rte_eth_xstat *stats, 1798 unsigned int n, unsigned int n_used); 1799 int mlx5_txpp_xstats_reset(struct rte_eth_dev *dev); 1800 int mlx5_txpp_xstats_get_names(struct rte_eth_dev *dev, 1801 struct rte_eth_xstat_name *xstats_names, 1802 unsigned int n, unsigned int n_used); 1803 void mlx5_txpp_interrupt_handler(void *cb_arg); 1804 1805 /* mlx5_rxtx.c */ 1806 1807 eth_tx_burst_t mlx5_select_tx_function(struct rte_eth_dev *dev); 1808 1809 /* mlx5_flow_aso.c */ 1810 1811 int mlx5_aso_queue_init(struct mlx5_dev_ctx_shared *sh, 1812 enum mlx5_access_aso_opc_mod aso_opc_mod); 1813 int mlx5_aso_flow_hit_queue_poll_start(struct mlx5_dev_ctx_shared *sh); 1814 int mlx5_aso_flow_hit_queue_poll_stop(struct mlx5_dev_ctx_shared *sh); 1815 void mlx5_aso_queue_uninit(struct mlx5_dev_ctx_shared *sh, 1816 enum mlx5_access_aso_opc_mod aso_opc_mod); 1817 int mlx5_aso_meter_update_by_wqe(struct mlx5_dev_ctx_shared *sh, 1818 struct mlx5_aso_mtr *mtr); 1819 int mlx5_aso_mtr_wait(struct mlx5_dev_ctx_shared *sh, 1820 struct mlx5_aso_mtr *mtr); 1821 int mlx5_aso_ct_update_by_wqe(struct mlx5_dev_ctx_shared *sh, 1822 struct mlx5_aso_ct_action *ct, 1823 const struct rte_flow_action_conntrack *profile); 1824 int mlx5_aso_ct_wait_ready(struct mlx5_dev_ctx_shared *sh, 1825 struct mlx5_aso_ct_action *ct); 1826 int mlx5_aso_ct_query_by_wqe(struct mlx5_dev_ctx_shared *sh, 1827 struct mlx5_aso_ct_action *ct, 1828 struct rte_flow_action_conntrack *profile); 1829 int mlx5_aso_ct_available(struct mlx5_dev_ctx_shared *sh, 1830 struct mlx5_aso_ct_action *ct); 1831 1832 #endif /* RTE_PMD_MLX5_H_ */ 1833