1 /* SPDX-License-Identifier: BSD-3-Clause 2 * Copyright 2015 6WIND S.A. 3 * Copyright 2015 Mellanox Technologies, Ltd 4 */ 5 6 #include <stddef.h> 7 #include <unistd.h> 8 #include <string.h> 9 #include <stdint.h> 10 #include <stdlib.h> 11 #include <errno.h> 12 #include <fcntl.h> 13 14 #include <rte_malloc.h> 15 #include <ethdev_driver.h> 16 #include <rte_pci.h> 17 #include <bus_pci_driver.h> 18 #include <rte_common.h> 19 #include <rte_kvargs.h> 20 #include <rte_rwlock.h> 21 #include <rte_spinlock.h> 22 #include <rte_string_fns.h> 23 #include <rte_eal_paging.h> 24 #include <rte_alarm.h> 25 #include <rte_cycles.h> 26 #include <rte_interrupts.h> 27 28 #include <mlx5_glue.h> 29 #include <mlx5_devx_cmds.h> 30 #include <mlx5_common.h> 31 #include <mlx5_common_os.h> 32 #include <mlx5_common_mp.h> 33 #include <mlx5_malloc.h> 34 35 #include "mlx5_defs.h" 36 #include "mlx5.h" 37 #include "mlx5_utils.h" 38 #include "mlx5_rxtx.h" 39 #include "mlx5_rx.h" 40 #include "mlx5_tx.h" 41 #include "mlx5_autoconf.h" 42 #include "mlx5_flow.h" 43 #include "mlx5_flow_os.h" 44 #include "rte_pmd_mlx5.h" 45 46 #define MLX5_ETH_DRIVER_NAME mlx5_eth 47 48 /* Device parameter to enable RX completion queue compression. */ 49 #define MLX5_RXQ_CQE_COMP_EN "rxq_cqe_comp_en" 50 51 /* Device parameter to enable padding Rx packet to cacheline size. */ 52 #define MLX5_RXQ_PKT_PAD_EN "rxq_pkt_pad_en" 53 54 /* Device parameter to enable Multi-Packet Rx queue. */ 55 #define MLX5_RX_MPRQ_EN "mprq_en" 56 57 /* Device parameter to configure log 2 of the number of strides for MPRQ. */ 58 #define MLX5_RX_MPRQ_LOG_STRIDE_NUM "mprq_log_stride_num" 59 60 /* Device parameter to configure log 2 of the stride size for MPRQ. */ 61 #define MLX5_RX_MPRQ_LOG_STRIDE_SIZE "mprq_log_stride_size" 62 63 /* Device parameter to limit the size of memcpy'd packet for MPRQ. */ 64 #define MLX5_RX_MPRQ_MAX_MEMCPY_LEN "mprq_max_memcpy_len" 65 66 /* Device parameter to set the minimum number of Rx queues to enable MPRQ. */ 67 #define MLX5_RXQS_MIN_MPRQ "rxqs_min_mprq" 68 69 /* Device parameter to configure inline send. Deprecated, ignored.*/ 70 #define MLX5_TXQ_INLINE "txq_inline" 71 72 /* Device parameter to limit packet size to inline with ordinary SEND. */ 73 #define MLX5_TXQ_INLINE_MAX "txq_inline_max" 74 75 /* Device parameter to configure minimal data size to inline. */ 76 #define MLX5_TXQ_INLINE_MIN "txq_inline_min" 77 78 /* Device parameter to limit packet size to inline with Enhanced MPW. */ 79 #define MLX5_TXQ_INLINE_MPW "txq_inline_mpw" 80 81 /* 82 * Device parameter to configure the number of TX queues threshold for 83 * enabling inline send. 84 */ 85 #define MLX5_TXQS_MIN_INLINE "txqs_min_inline" 86 87 /* 88 * Device parameter to configure the number of TX queues threshold for 89 * enabling vectorized Tx, deprecated, ignored (no vectorized Tx routines). 90 */ 91 #define MLX5_TXQS_MAX_VEC "txqs_max_vec" 92 93 /* Device parameter to enable multi-packet send WQEs. */ 94 #define MLX5_TXQ_MPW_EN "txq_mpw_en" 95 96 /* 97 * Device parameter to include 2 dsegs in the title WQEBB. 98 * Deprecated, ignored. 99 */ 100 #define MLX5_TXQ_MPW_HDR_DSEG_EN "txq_mpw_hdr_dseg_en" 101 102 /* 103 * Device parameter to limit the size of inlining packet. 104 * Deprecated, ignored. 105 */ 106 #define MLX5_TXQ_MAX_INLINE_LEN "txq_max_inline_len" 107 108 /* 109 * Device parameter to enable Tx scheduling on timestamps 110 * and specify the packet pacing granularity in nanoseconds. 111 */ 112 #define MLX5_TX_PP "tx_pp" 113 114 /* 115 * Device parameter to specify skew in nanoseconds on Tx datapath, 116 * it represents the time between SQ start WQE processing and 117 * appearing actual packet data on the wire. 118 */ 119 #define MLX5_TX_SKEW "tx_skew" 120 121 /* 122 * Device parameter to enable hardware Tx vector. 123 * Deprecated, ignored (no vectorized Tx routines anymore). 124 */ 125 #define MLX5_TX_VEC_EN "tx_vec_en" 126 127 /* Device parameter to enable hardware Rx vector. */ 128 #define MLX5_RX_VEC_EN "rx_vec_en" 129 130 /* Allow L3 VXLAN flow creation. */ 131 #define MLX5_L3_VXLAN_EN "l3_vxlan_en" 132 133 /* Activate DV E-Switch flow steering. */ 134 #define MLX5_DV_ESW_EN "dv_esw_en" 135 136 /* Activate DV flow steering. */ 137 #define MLX5_DV_FLOW_EN "dv_flow_en" 138 139 /* Enable extensive flow metadata support. */ 140 #define MLX5_DV_XMETA_EN "dv_xmeta_en" 141 142 /* Device parameter to let the user manage the lacp traffic of bonding device */ 143 #define MLX5_LACP_BY_USER "lacp_by_user" 144 145 /* Activate Netlink support in VF mode. */ 146 #define MLX5_VF_NL_EN "vf_nl_en" 147 148 /* Select port representors to instantiate. */ 149 #define MLX5_REPRESENTOR "representor" 150 151 /* Device parameter to configure the maximum number of dump files per queue. */ 152 #define MLX5_MAX_DUMP_FILES_NUM "max_dump_files_num" 153 154 /* Configure timeout of LRO session (in microseconds). */ 155 #define MLX5_LRO_TIMEOUT_USEC "lro_timeout_usec" 156 157 /* 158 * Device parameter to configure the total data buffer size for a single 159 * hairpin queue (logarithm value). 160 */ 161 #define MLX5_HP_BUF_SIZE "hp_buf_log_sz" 162 163 /* Flow memory reclaim mode. */ 164 #define MLX5_RECLAIM_MEM "reclaim_mem_mode" 165 166 /* Decap will be used or not. */ 167 #define MLX5_DECAP_EN "decap_en" 168 169 /* Device parameter to configure allow or prevent duplicate rules pattern. */ 170 #define MLX5_ALLOW_DUPLICATE_PATTERN "allow_duplicate_pattern" 171 172 /* Device parameter to configure the delay drop when creating Rxqs. */ 173 #define MLX5_DELAY_DROP "delay_drop" 174 175 /* Device parameter to create the fdb default rule in PMD */ 176 #define MLX5_FDB_DEFAULT_RULE_EN "fdb_def_rule_en" 177 178 /* HW steering counter configuration. */ 179 #define MLX5_HWS_CNT_SERVICE_CORE "service_core" 180 181 /* HW steering counter's query interval. */ 182 #define MLX5_HWS_CNT_CYCLE_TIME "svc_cycle_time" 183 184 /* Device parameter to control representor matching in ingress/egress flows with HWS. */ 185 #define MLX5_REPR_MATCHING_EN "repr_matching_en" 186 187 /* Shared memory between primary and secondary processes. */ 188 struct mlx5_shared_data *mlx5_shared_data; 189 190 /** Driver-specific log messages type. */ 191 int mlx5_logtype; 192 193 static LIST_HEAD(, mlx5_dev_ctx_shared) mlx5_dev_ctx_list = 194 LIST_HEAD_INITIALIZER(); 195 static pthread_mutex_t mlx5_dev_ctx_list_mutex; 196 static const struct mlx5_indexed_pool_config mlx5_ipool_cfg[] = { 197 #if defined(HAVE_IBV_FLOW_DV_SUPPORT) || !defined(HAVE_INFINIBAND_VERBS_H) 198 [MLX5_IPOOL_DECAP_ENCAP] = { 199 .size = sizeof(struct mlx5_flow_dv_encap_decap_resource), 200 .trunk_size = 64, 201 .grow_trunk = 3, 202 .grow_shift = 2, 203 .need_lock = 1, 204 .release_mem_en = 1, 205 .malloc = mlx5_malloc, 206 .free = mlx5_free, 207 .type = "mlx5_encap_decap_ipool", 208 }, 209 [MLX5_IPOOL_PUSH_VLAN] = { 210 .size = sizeof(struct mlx5_flow_dv_push_vlan_action_resource), 211 .trunk_size = 64, 212 .grow_trunk = 3, 213 .grow_shift = 2, 214 .need_lock = 1, 215 .release_mem_en = 1, 216 .malloc = mlx5_malloc, 217 .free = mlx5_free, 218 .type = "mlx5_push_vlan_ipool", 219 }, 220 [MLX5_IPOOL_TAG] = { 221 .size = sizeof(struct mlx5_flow_dv_tag_resource), 222 .trunk_size = 64, 223 .grow_trunk = 3, 224 .grow_shift = 2, 225 .need_lock = 1, 226 .release_mem_en = 0, 227 .per_core_cache = (1 << 16), 228 .malloc = mlx5_malloc, 229 .free = mlx5_free, 230 .type = "mlx5_tag_ipool", 231 }, 232 [MLX5_IPOOL_PORT_ID] = { 233 .size = sizeof(struct mlx5_flow_dv_port_id_action_resource), 234 .trunk_size = 64, 235 .grow_trunk = 3, 236 .grow_shift = 2, 237 .need_lock = 1, 238 .release_mem_en = 1, 239 .malloc = mlx5_malloc, 240 .free = mlx5_free, 241 .type = "mlx5_port_id_ipool", 242 }, 243 [MLX5_IPOOL_JUMP] = { 244 /* 245 * MLX5_IPOOL_JUMP ipool entry size depends on selected flow engine. 246 * When HW steering is enabled mlx5_flow_group struct is used. 247 * Otherwise mlx5_flow_tbl_data_entry struct is used. 248 */ 249 .size = 0, 250 .trunk_size = 64, 251 .grow_trunk = 3, 252 .grow_shift = 2, 253 .need_lock = 1, 254 .release_mem_en = 1, 255 .malloc = mlx5_malloc, 256 .free = mlx5_free, 257 .type = "mlx5_jump_ipool", 258 }, 259 [MLX5_IPOOL_SAMPLE] = { 260 .size = sizeof(struct mlx5_flow_dv_sample_resource), 261 .trunk_size = 64, 262 .grow_trunk = 3, 263 .grow_shift = 2, 264 .need_lock = 1, 265 .release_mem_en = 1, 266 .malloc = mlx5_malloc, 267 .free = mlx5_free, 268 .type = "mlx5_sample_ipool", 269 }, 270 [MLX5_IPOOL_DEST_ARRAY] = { 271 .size = sizeof(struct mlx5_flow_dv_dest_array_resource), 272 .trunk_size = 64, 273 .grow_trunk = 3, 274 .grow_shift = 2, 275 .need_lock = 1, 276 .release_mem_en = 1, 277 .malloc = mlx5_malloc, 278 .free = mlx5_free, 279 .type = "mlx5_dest_array_ipool", 280 }, 281 [MLX5_IPOOL_TUNNEL_ID] = { 282 .size = sizeof(struct mlx5_flow_tunnel), 283 .trunk_size = MLX5_MAX_TUNNELS, 284 .need_lock = 1, 285 .release_mem_en = 1, 286 .type = "mlx5_tunnel_offload", 287 }, 288 [MLX5_IPOOL_TNL_TBL_ID] = { 289 .size = 0, 290 .need_lock = 1, 291 .type = "mlx5_flow_tnl_tbl_ipool", 292 }, 293 #endif 294 [MLX5_IPOOL_MTR] = { 295 /** 296 * The ipool index should grow continually from small to big, 297 * for meter idx, so not set grow_trunk to avoid meter index 298 * not jump continually. 299 */ 300 .size = sizeof(struct mlx5_legacy_flow_meter), 301 .trunk_size = 64, 302 .need_lock = 1, 303 .release_mem_en = 1, 304 .malloc = mlx5_malloc, 305 .free = mlx5_free, 306 .type = "mlx5_meter_ipool", 307 }, 308 [MLX5_IPOOL_MCP] = { 309 .size = sizeof(struct mlx5_flow_mreg_copy_resource), 310 .trunk_size = 64, 311 .grow_trunk = 3, 312 .grow_shift = 2, 313 .need_lock = 1, 314 .release_mem_en = 1, 315 .malloc = mlx5_malloc, 316 .free = mlx5_free, 317 .type = "mlx5_mcp_ipool", 318 }, 319 [MLX5_IPOOL_HRXQ] = { 320 .size = (sizeof(struct mlx5_hrxq) + MLX5_RSS_HASH_KEY_LEN), 321 .trunk_size = 64, 322 .grow_trunk = 3, 323 .grow_shift = 2, 324 .need_lock = 1, 325 .release_mem_en = 1, 326 .malloc = mlx5_malloc, 327 .free = mlx5_free, 328 .type = "mlx5_hrxq_ipool", 329 }, 330 [MLX5_IPOOL_MLX5_FLOW] = { 331 /* 332 * MLX5_IPOOL_MLX5_FLOW size varies for DV and VERBS flows. 333 * It set in run time according to PCI function configuration. 334 */ 335 .size = 0, 336 .trunk_size = 64, 337 .grow_trunk = 3, 338 .grow_shift = 2, 339 .need_lock = 1, 340 .release_mem_en = 0, 341 .per_core_cache = 1 << 19, 342 .malloc = mlx5_malloc, 343 .free = mlx5_free, 344 .type = "mlx5_flow_handle_ipool", 345 }, 346 [MLX5_IPOOL_RTE_FLOW] = { 347 .size = sizeof(struct rte_flow), 348 .trunk_size = 4096, 349 .need_lock = 1, 350 .release_mem_en = 1, 351 .malloc = mlx5_malloc, 352 .free = mlx5_free, 353 .type = "rte_flow_ipool", 354 }, 355 [MLX5_IPOOL_RSS_EXPANTION_FLOW_ID] = { 356 .size = 0, 357 .need_lock = 1, 358 .type = "mlx5_flow_rss_id_ipool", 359 }, 360 [MLX5_IPOOL_RSS_SHARED_ACTIONS] = { 361 .size = sizeof(struct mlx5_shared_action_rss), 362 .trunk_size = 64, 363 .grow_trunk = 3, 364 .grow_shift = 2, 365 .need_lock = 1, 366 .release_mem_en = 1, 367 .malloc = mlx5_malloc, 368 .free = mlx5_free, 369 .type = "mlx5_shared_action_rss", 370 }, 371 [MLX5_IPOOL_MTR_POLICY] = { 372 /** 373 * The ipool index should grow continually from small to big, 374 * for policy idx, so not set grow_trunk to avoid policy index 375 * not jump continually. 376 */ 377 .size = sizeof(struct mlx5_flow_meter_sub_policy), 378 .trunk_size = 64, 379 .need_lock = 1, 380 .release_mem_en = 1, 381 .malloc = mlx5_malloc, 382 .free = mlx5_free, 383 .type = "mlx5_meter_policy_ipool", 384 }, 385 }; 386 387 #define MLX5_FLOW_MIN_ID_POOL_SIZE 512 388 #define MLX5_ID_GENERATION_ARRAY_FACTOR 16 389 390 #define MLX5_FLOW_TABLE_HLIST_ARRAY_SIZE 1024 391 392 #define MLX5_RXQ_ENH_CQE_COMP_MASK 0x80 393 394 /** 395 * Decide whether representor ID is a HPF(host PF) port on BF2. 396 * 397 * @param dev 398 * Pointer to Ethernet device structure. 399 * 400 * @return 401 * Non-zero if HPF, otherwise 0. 402 */ 403 bool 404 mlx5_is_hpf(struct rte_eth_dev *dev) 405 { 406 struct mlx5_priv *priv = dev->data->dev_private; 407 uint16_t repr = MLX5_REPRESENTOR_REPR(priv->representor_id); 408 int type = MLX5_REPRESENTOR_TYPE(priv->representor_id); 409 410 return priv->representor != 0 && type == RTE_ETH_REPRESENTOR_VF && 411 MLX5_REPRESENTOR_REPR(-1) == repr; 412 } 413 414 /** 415 * Decide whether representor ID is a SF port representor. 416 * 417 * @param dev 418 * Pointer to Ethernet device structure. 419 * 420 * @return 421 * Non-zero if HPF, otherwise 0. 422 */ 423 bool 424 mlx5_is_sf_repr(struct rte_eth_dev *dev) 425 { 426 struct mlx5_priv *priv = dev->data->dev_private; 427 int type = MLX5_REPRESENTOR_TYPE(priv->representor_id); 428 429 return priv->representor != 0 && type == RTE_ETH_REPRESENTOR_SF; 430 } 431 432 /** 433 * Initialize the ASO aging management structure. 434 * 435 * @param[in] sh 436 * Pointer to mlx5_dev_ctx_shared object to free 437 * 438 * @return 439 * 0 on success, a negative errno value otherwise and rte_errno is set. 440 */ 441 int 442 mlx5_flow_aso_age_mng_init(struct mlx5_dev_ctx_shared *sh) 443 { 444 int err; 445 446 if (sh->aso_age_mng) 447 return 0; 448 sh->aso_age_mng = mlx5_malloc(MLX5_MEM_ZERO, sizeof(*sh->aso_age_mng), 449 RTE_CACHE_LINE_SIZE, SOCKET_ID_ANY); 450 if (!sh->aso_age_mng) { 451 DRV_LOG(ERR, "aso_age_mng allocation was failed."); 452 rte_errno = ENOMEM; 453 return -ENOMEM; 454 } 455 err = mlx5_aso_queue_init(sh, ASO_OPC_MOD_FLOW_HIT, 1); 456 if (err) { 457 mlx5_free(sh->aso_age_mng); 458 return -1; 459 } 460 rte_rwlock_init(&sh->aso_age_mng->resize_rwl); 461 rte_spinlock_init(&sh->aso_age_mng->free_sl); 462 LIST_INIT(&sh->aso_age_mng->free); 463 return 0; 464 } 465 466 /** 467 * Close and release all the resources of the ASO aging management structure. 468 * 469 * @param[in] sh 470 * Pointer to mlx5_dev_ctx_shared object to free. 471 */ 472 static void 473 mlx5_flow_aso_age_mng_close(struct mlx5_dev_ctx_shared *sh) 474 { 475 int i, j; 476 477 mlx5_aso_flow_hit_queue_poll_stop(sh); 478 mlx5_aso_queue_uninit(sh, ASO_OPC_MOD_FLOW_HIT); 479 if (sh->aso_age_mng->pools) { 480 struct mlx5_aso_age_pool *pool; 481 482 for (i = 0; i < sh->aso_age_mng->next; ++i) { 483 pool = sh->aso_age_mng->pools[i]; 484 claim_zero(mlx5_devx_cmd_destroy 485 (pool->flow_hit_aso_obj)); 486 for (j = 0; j < MLX5_COUNTERS_PER_POOL; ++j) 487 if (pool->actions[j].dr_action) 488 claim_zero 489 (mlx5_flow_os_destroy_flow_action 490 (pool->actions[j].dr_action)); 491 mlx5_free(pool); 492 } 493 mlx5_free(sh->aso_age_mng->pools); 494 } 495 mlx5_free(sh->aso_age_mng); 496 } 497 498 /** 499 * Initialize the shared aging list information per port. 500 * 501 * @param[in] sh 502 * Pointer to mlx5_dev_ctx_shared object. 503 */ 504 static void 505 mlx5_flow_aging_init(struct mlx5_dev_ctx_shared *sh) 506 { 507 uint32_t i; 508 struct mlx5_age_info *age_info; 509 510 /* 511 * In HW steering, aging information structure is initialized later 512 * during configure function. 513 */ 514 if (sh->config.dv_flow_en == 2) 515 return; 516 for (i = 0; i < sh->max_port; i++) { 517 age_info = &sh->port[i].age_info; 518 age_info->flags = 0; 519 TAILQ_INIT(&age_info->aged_counters); 520 LIST_INIT(&age_info->aged_aso); 521 rte_spinlock_init(&age_info->aged_sl); 522 MLX5_AGE_SET(age_info, MLX5_AGE_TRIGGER); 523 } 524 } 525 526 /** 527 * DV flow counter mode detect and config. 528 * 529 * @param dev 530 * Pointer to rte_eth_dev structure. 531 * 532 */ 533 void 534 mlx5_flow_counter_mode_config(struct rte_eth_dev *dev __rte_unused) 535 { 536 #ifdef HAVE_IBV_FLOW_DV_SUPPORT 537 struct mlx5_priv *priv = dev->data->dev_private; 538 struct mlx5_dev_ctx_shared *sh = priv->sh; 539 struct mlx5_hca_attr *hca_attr = &sh->cdev->config.hca_attr; 540 bool fallback; 541 542 #ifndef HAVE_IBV_DEVX_ASYNC 543 fallback = true; 544 #else 545 fallback = false; 546 if (!sh->cdev->config.devx || !sh->config.dv_flow_en || 547 !hca_attr->flow_counters_dump || 548 !(hca_attr->flow_counter_bulk_alloc_bitmap & 0x4) || 549 (mlx5_flow_dv_discover_counter_offset_support(dev) == -ENOTSUP)) 550 fallback = true; 551 #endif 552 if (fallback) 553 DRV_LOG(INFO, "Use fall-back DV counter management. Flow " 554 "counter dump:%d, bulk_alloc_bitmap:0x%hhx.", 555 hca_attr->flow_counters_dump, 556 hca_attr->flow_counter_bulk_alloc_bitmap); 557 /* Initialize fallback mode only on the port initializes sh. */ 558 if (sh->refcnt == 1) 559 sh->sws_cmng.counter_fallback = fallback; 560 else if (fallback != sh->sws_cmng.counter_fallback) 561 DRV_LOG(WARNING, "Port %d in sh has different fallback mode " 562 "with others:%d.", PORT_ID(priv), fallback); 563 #endif 564 } 565 566 /** 567 * Initialize the counters management structure. 568 * 569 * @param[in] sh 570 * Pointer to mlx5_dev_ctx_shared object to free 571 * 572 * @return 573 * 0 on success, otherwise negative errno value and rte_errno is set. 574 */ 575 static int 576 mlx5_flow_counters_mng_init(struct mlx5_dev_ctx_shared *sh) 577 { 578 int i, j; 579 580 if (sh->config.dv_flow_en < 2) { 581 void *pools; 582 583 pools = mlx5_malloc(MLX5_MEM_ZERO, 584 sizeof(struct mlx5_flow_counter_pool *) * 585 MLX5_COUNTER_POOLS_MAX_NUM, 586 0, SOCKET_ID_ANY); 587 if (!pools) { 588 DRV_LOG(ERR, 589 "Counter management allocation was failed."); 590 rte_errno = ENOMEM; 591 return -rte_errno; 592 } 593 memset(&sh->sws_cmng, 0, sizeof(sh->sws_cmng)); 594 TAILQ_INIT(&sh->sws_cmng.flow_counters); 595 sh->sws_cmng.min_id = MLX5_CNT_BATCH_OFFSET; 596 sh->sws_cmng.max_id = -1; 597 sh->sws_cmng.last_pool_idx = POOL_IDX_INVALID; 598 sh->sws_cmng.pools = pools; 599 rte_spinlock_init(&sh->sws_cmng.pool_update_sl); 600 for (i = 0; i < MLX5_COUNTER_TYPE_MAX; i++) { 601 TAILQ_INIT(&sh->sws_cmng.counters[i]); 602 rte_spinlock_init(&sh->sws_cmng.csl[i]); 603 } 604 } else { 605 struct mlx5_hca_attr *attr = &sh->cdev->config.hca_attr; 606 uint32_t fw_max_nb_cnts = attr->max_flow_counter; 607 uint8_t log_dcs = log2above(fw_max_nb_cnts) - 1; 608 uint32_t max_nb_cnts = 0; 609 610 for (i = 0, j = 0; j < MLX5_HWS_CNT_DCS_NUM; ++i) { 611 int log_dcs_i = log_dcs - i; 612 613 if (log_dcs_i < 0) 614 break; 615 if ((max_nb_cnts | RTE_BIT32(log_dcs_i)) > 616 fw_max_nb_cnts) 617 continue; 618 max_nb_cnts |= RTE_BIT32(log_dcs_i); 619 j++; 620 } 621 sh->hws_max_log_bulk_sz = log_dcs; 622 sh->hws_max_nb_counters = max_nb_cnts; 623 } 624 return 0; 625 } 626 627 /** 628 * Destroy all the resources allocated for a counter memory management. 629 * 630 * @param[in] mng 631 * Pointer to the memory management structure. 632 */ 633 static void 634 mlx5_flow_destroy_counter_stat_mem_mng(struct mlx5_counter_stats_mem_mng *mng) 635 { 636 uint8_t *mem = (uint8_t *)(uintptr_t)mng->raws[0].data; 637 638 LIST_REMOVE(mng, next); 639 mlx5_os_wrapped_mkey_destroy(&mng->wm); 640 mlx5_free(mem); 641 } 642 643 /** 644 * Close and release all the resources of the counters management. 645 * 646 * @param[in] sh 647 * Pointer to mlx5_dev_ctx_shared object to free. 648 */ 649 static void 650 mlx5_flow_counters_mng_close(struct mlx5_dev_ctx_shared *sh) 651 { 652 struct mlx5_counter_stats_mem_mng *mng; 653 int i, j; 654 int retries = 1024; 655 656 rte_errno = 0; 657 while (--retries) { 658 rte_eal_alarm_cancel(mlx5_flow_query_alarm, sh); 659 if (rte_errno != EINPROGRESS) 660 break; 661 rte_pause(); 662 } 663 664 if (sh->sws_cmng.pools) { 665 struct mlx5_flow_counter_pool *pool; 666 uint16_t n_valid = sh->sws_cmng.n_valid; 667 bool fallback = sh->sws_cmng.counter_fallback; 668 669 for (i = 0; i < n_valid; ++i) { 670 pool = sh->sws_cmng.pools[i]; 671 if (!fallback && pool->min_dcs) 672 claim_zero(mlx5_devx_cmd_destroy 673 (pool->min_dcs)); 674 for (j = 0; j < MLX5_COUNTERS_PER_POOL; ++j) { 675 struct mlx5_flow_counter *cnt = 676 MLX5_POOL_GET_CNT(pool, j); 677 678 if (cnt->action) 679 claim_zero 680 (mlx5_flow_os_destroy_flow_action 681 (cnt->action)); 682 if (fallback && cnt->dcs_when_free) 683 claim_zero(mlx5_devx_cmd_destroy 684 (cnt->dcs_when_free)); 685 } 686 mlx5_free(pool); 687 } 688 mlx5_free(sh->sws_cmng.pools); 689 } 690 mng = LIST_FIRST(&sh->sws_cmng.mem_mngs); 691 while (mng) { 692 mlx5_flow_destroy_counter_stat_mem_mng(mng); 693 mng = LIST_FIRST(&sh->sws_cmng.mem_mngs); 694 } 695 memset(&sh->sws_cmng, 0, sizeof(sh->sws_cmng)); 696 } 697 698 /** 699 * Initialize the aso flow meters management structure. 700 * 701 * @param[in] sh 702 * Pointer to mlx5_dev_ctx_shared object to free 703 */ 704 int 705 mlx5_aso_flow_mtrs_mng_init(struct mlx5_dev_ctx_shared *sh) 706 { 707 if (!sh->mtrmng) { 708 sh->mtrmng = mlx5_malloc(MLX5_MEM_ZERO, 709 sizeof(*sh->mtrmng), 710 RTE_CACHE_LINE_SIZE, SOCKET_ID_ANY); 711 if (!sh->mtrmng) { 712 DRV_LOG(ERR, 713 "meter management allocation was failed."); 714 rte_errno = ENOMEM; 715 return -ENOMEM; 716 } 717 if (sh->meter_aso_en) { 718 rte_spinlock_init(&sh->mtrmng->pools_mng.mtrsl); 719 rte_rwlock_init(&sh->mtrmng->pools_mng.resize_mtrwl); 720 LIST_INIT(&sh->mtrmng->pools_mng.meters); 721 } 722 sh->mtrmng->def_policy_id = MLX5_INVALID_POLICY_ID; 723 } 724 return 0; 725 } 726 727 /** 728 * Close and release all the resources of 729 * the ASO flow meter management structure. 730 * 731 * @param[in] sh 732 * Pointer to mlx5_dev_ctx_shared object to free. 733 */ 734 static void 735 mlx5_aso_flow_mtrs_mng_close(struct mlx5_dev_ctx_shared *sh) 736 { 737 struct mlx5_aso_mtr_pool *mtr_pool; 738 struct mlx5_flow_mtr_mng *mtrmng = sh->mtrmng; 739 uint32_t idx; 740 #ifdef HAVE_MLX5_DR_CREATE_ACTION_ASO 741 struct mlx5_aso_mtr *aso_mtr; 742 int i; 743 #endif /* HAVE_MLX5_DR_CREATE_ACTION_ASO */ 744 745 if (sh->meter_aso_en) { 746 mlx5_aso_queue_uninit(sh, ASO_OPC_MOD_POLICER); 747 idx = mtrmng->pools_mng.n_valid; 748 while (idx--) { 749 mtr_pool = mtrmng->pools_mng.pools[idx]; 750 #ifdef HAVE_MLX5_DR_CREATE_ACTION_ASO 751 for (i = 0; i < MLX5_ASO_MTRS_PER_POOL; i++) { 752 aso_mtr = &mtr_pool->mtrs[i]; 753 if (aso_mtr->fm.meter_action_g) 754 claim_zero 755 (mlx5_glue->destroy_flow_action 756 (aso_mtr->fm.meter_action_g)); 757 if (aso_mtr->fm.meter_action_y) 758 claim_zero 759 (mlx5_glue->destroy_flow_action 760 (aso_mtr->fm.meter_action_y)); 761 } 762 #endif /* HAVE_MLX5_DR_CREATE_ACTION_ASO */ 763 claim_zero(mlx5_devx_cmd_destroy 764 (mtr_pool->devx_obj)); 765 mtrmng->pools_mng.n_valid--; 766 mlx5_free(mtr_pool); 767 } 768 mlx5_free(sh->mtrmng->pools_mng.pools); 769 } 770 mlx5_free(sh->mtrmng); 771 sh->mtrmng = NULL; 772 } 773 774 /* Send FLOW_AGED event if needed. */ 775 void 776 mlx5_age_event_prepare(struct mlx5_dev_ctx_shared *sh) 777 { 778 struct mlx5_age_info *age_info; 779 uint32_t i; 780 781 for (i = 0; i < sh->max_port; i++) { 782 age_info = &sh->port[i].age_info; 783 if (!MLX5_AGE_GET(age_info, MLX5_AGE_EVENT_NEW)) 784 continue; 785 MLX5_AGE_UNSET(age_info, MLX5_AGE_EVENT_NEW); 786 if (MLX5_AGE_GET(age_info, MLX5_AGE_TRIGGER)) { 787 MLX5_AGE_UNSET(age_info, MLX5_AGE_TRIGGER); 788 rte_eth_dev_callback_process 789 (&rte_eth_devices[sh->port[i].devx_ih_port_id], 790 RTE_ETH_EVENT_FLOW_AGED, NULL); 791 } 792 } 793 } 794 795 /* 796 * Initialize the ASO connection tracking structure. 797 * 798 * @param[in] sh 799 * Pointer to mlx5_dev_ctx_shared object. 800 * 801 * @return 802 * 0 on success, a negative errno value otherwise and rte_errno is set. 803 */ 804 int 805 mlx5_flow_aso_ct_mng_init(struct mlx5_dev_ctx_shared *sh) 806 { 807 int err; 808 809 if (sh->ct_mng) 810 return 0; 811 sh->ct_mng = mlx5_malloc(MLX5_MEM_ZERO, sizeof(*sh->ct_mng) + 812 sizeof(struct mlx5_aso_sq) * MLX5_ASO_CT_SQ_NUM, 813 RTE_CACHE_LINE_SIZE, SOCKET_ID_ANY); 814 if (!sh->ct_mng) { 815 DRV_LOG(ERR, "ASO CT management allocation failed."); 816 rte_errno = ENOMEM; 817 return -rte_errno; 818 } 819 err = mlx5_aso_queue_init(sh, ASO_OPC_MOD_CONNECTION_TRACKING, MLX5_ASO_CT_SQ_NUM); 820 if (err) { 821 mlx5_free(sh->ct_mng); 822 /* rte_errno should be extracted from the failure. */ 823 rte_errno = EINVAL; 824 return -rte_errno; 825 } 826 rte_spinlock_init(&sh->ct_mng->ct_sl); 827 rte_rwlock_init(&sh->ct_mng->resize_rwl); 828 LIST_INIT(&sh->ct_mng->free_cts); 829 return 0; 830 } 831 832 /* 833 * Close and release all the resources of the 834 * ASO connection tracking management structure. 835 * 836 * @param[in] sh 837 * Pointer to mlx5_dev_ctx_shared object to free. 838 */ 839 static void 840 mlx5_flow_aso_ct_mng_close(struct mlx5_dev_ctx_shared *sh) 841 { 842 struct mlx5_aso_ct_pools_mng *mng = sh->ct_mng; 843 struct mlx5_aso_ct_pool *ct_pool; 844 struct mlx5_aso_ct_action *ct; 845 uint32_t idx; 846 uint32_t val; 847 uint32_t cnt; 848 int i; 849 850 mlx5_aso_queue_uninit(sh, ASO_OPC_MOD_CONNECTION_TRACKING); 851 idx = mng->next; 852 while (idx--) { 853 cnt = 0; 854 ct_pool = mng->pools[idx]; 855 for (i = 0; i < MLX5_ASO_CT_ACTIONS_PER_POOL; i++) { 856 ct = &ct_pool->actions[i]; 857 val = __atomic_fetch_sub(&ct->refcnt, 1, 858 __ATOMIC_RELAXED); 859 MLX5_ASSERT(val == 1); 860 if (val > 1) 861 cnt++; 862 #ifdef HAVE_MLX5_DR_ACTION_ASO_CT 863 if (ct->dr_action_orig) 864 claim_zero(mlx5_glue->destroy_flow_action 865 (ct->dr_action_orig)); 866 if (ct->dr_action_rply) 867 claim_zero(mlx5_glue->destroy_flow_action 868 (ct->dr_action_rply)); 869 #endif 870 } 871 claim_zero(mlx5_devx_cmd_destroy(ct_pool->devx_obj)); 872 if (cnt) { 873 DRV_LOG(DEBUG, "%u ASO CT objects are being used in the pool %u", 874 cnt, i); 875 } 876 mlx5_free(ct_pool); 877 /* in case of failure. */ 878 mng->next--; 879 } 880 mlx5_free(mng->pools); 881 mlx5_free(mng); 882 /* Management structure must be cleared to 0s during allocation. */ 883 sh->ct_mng = NULL; 884 } 885 886 /** 887 * Initialize the flow resources' indexed mempool. 888 * 889 * @param[in] sh 890 * Pointer to mlx5_dev_ctx_shared object. 891 */ 892 static void 893 mlx5_flow_ipool_create(struct mlx5_dev_ctx_shared *sh) 894 { 895 uint8_t i; 896 struct mlx5_indexed_pool_config cfg; 897 898 for (i = 0; i < MLX5_IPOOL_MAX; ++i) { 899 cfg = mlx5_ipool_cfg[i]; 900 switch (i) { 901 default: 902 break; 903 /* 904 * Set MLX5_IPOOL_MLX5_FLOW ipool size 905 * according to PCI function flow configuration. 906 */ 907 case MLX5_IPOOL_MLX5_FLOW: 908 cfg.size = sh->config.dv_flow_en ? 909 sizeof(struct mlx5_flow_handle) : 910 MLX5_FLOW_HANDLE_VERBS_SIZE; 911 break; 912 #if defined(HAVE_IBV_FLOW_DV_SUPPORT) || !defined(HAVE_INFINIBAND_VERBS_H) 913 /* Set MLX5_IPOOL_JUMP ipool entry size depending on selected flow engine. */ 914 case MLX5_IPOOL_JUMP: 915 cfg.size = sh->config.dv_flow_en == 2 ? 916 sizeof(struct mlx5_flow_group) : 917 sizeof(struct mlx5_flow_tbl_data_entry); 918 break; 919 #endif 920 } 921 if (sh->config.reclaim_mode) { 922 cfg.release_mem_en = 1; 923 cfg.per_core_cache = 0; 924 } else { 925 cfg.release_mem_en = 0; 926 } 927 sh->ipool[i] = mlx5_ipool_create(&cfg); 928 } 929 } 930 931 932 /** 933 * Release the flow resources' indexed mempool. 934 * 935 * @param[in] sh 936 * Pointer to mlx5_dev_ctx_shared object. 937 */ 938 static void 939 mlx5_flow_ipool_destroy(struct mlx5_dev_ctx_shared *sh) 940 { 941 uint8_t i; 942 943 for (i = 0; i < MLX5_IPOOL_MAX; ++i) 944 mlx5_ipool_destroy(sh->ipool[i]); 945 for (i = 0; i < MLX5_MAX_MODIFY_NUM; ++i) 946 if (sh->mdh_ipools[i]) 947 mlx5_ipool_destroy(sh->mdh_ipools[i]); 948 } 949 950 /* 951 * Check if dynamic flex parser for eCPRI already exists. 952 * 953 * @param dev 954 * Pointer to Ethernet device structure. 955 * 956 * @return 957 * true on exists, false on not. 958 */ 959 bool 960 mlx5_flex_parser_ecpri_exist(struct rte_eth_dev *dev) 961 { 962 struct mlx5_priv *priv = dev->data->dev_private; 963 struct mlx5_ecpri_parser_profile *prf = &priv->sh->ecpri_parser; 964 965 return !!prf->obj; 966 } 967 968 /* 969 * Allocation of a flex parser for eCPRI. Once created, this parser related 970 * resources will be held until the device is closed. 971 * 972 * @param dev 973 * Pointer to Ethernet device structure. 974 * 975 * @return 976 * 0 on success, a negative errno value otherwise and rte_errno is set. 977 */ 978 int 979 mlx5_flex_parser_ecpri_alloc(struct rte_eth_dev *dev) 980 { 981 struct mlx5_priv *priv = dev->data->dev_private; 982 struct mlx5_ecpri_parser_profile *prf = &priv->sh->ecpri_parser; 983 struct mlx5_devx_graph_node_attr node = { 984 .modify_field_select = 0, 985 }; 986 uint32_t ids[8]; 987 int ret; 988 989 if (!priv->sh->cdev->config.hca_attr.parse_graph_flex_node) { 990 DRV_LOG(ERR, "Dynamic flex parser is not supported " 991 "for device %s.", priv->dev_data->name); 992 return -ENOTSUP; 993 } 994 node.header_length_mode = MLX5_GRAPH_NODE_LEN_FIXED; 995 /* 8 bytes now: 4B common header + 4B message body header. */ 996 node.header_length_base_value = 0x8; 997 /* After MAC layer: Ether / VLAN. */ 998 node.in[0].arc_parse_graph_node = MLX5_GRAPH_ARC_NODE_MAC; 999 /* Type of compared condition should be 0xAEFE in the L2 layer. */ 1000 node.in[0].compare_condition_value = RTE_ETHER_TYPE_ECPRI; 1001 /* Sample #0: type in common header. */ 1002 node.sample[0].flow_match_sample_en = 1; 1003 /* Fixed offset. */ 1004 node.sample[0].flow_match_sample_offset_mode = 0x0; 1005 /* Only the 2nd byte will be used. */ 1006 node.sample[0].flow_match_sample_field_base_offset = 0x0; 1007 /* Sample #1: message payload. */ 1008 node.sample[1].flow_match_sample_en = 1; 1009 /* Fixed offset. */ 1010 node.sample[1].flow_match_sample_offset_mode = 0x0; 1011 /* 1012 * Only the first two bytes will be used right now, and its offset will 1013 * start after the common header that with the length of a DW(u32). 1014 */ 1015 node.sample[1].flow_match_sample_field_base_offset = sizeof(uint32_t); 1016 prf->obj = mlx5_devx_cmd_create_flex_parser(priv->sh->cdev->ctx, &node); 1017 if (!prf->obj) { 1018 DRV_LOG(ERR, "Failed to create flex parser node object."); 1019 return (rte_errno == 0) ? -ENODEV : -rte_errno; 1020 } 1021 prf->num = 2; 1022 ret = mlx5_devx_cmd_query_parse_samples(prf->obj, ids, prf->num, NULL); 1023 if (ret) { 1024 DRV_LOG(ERR, "Failed to query sample IDs."); 1025 goto error; 1026 } 1027 prf->offset[0] = 0x0; 1028 prf->offset[1] = sizeof(uint32_t); 1029 prf->ids[0] = ids[0]; 1030 prf->ids[1] = ids[1]; 1031 return 0; 1032 error: 1033 mlx5_devx_cmd_destroy(prf->obj); 1034 return (rte_errno == 0) ? -ENODEV : -rte_errno; 1035 } 1036 1037 /* 1038 * Destroy the flex parser node, including the parser itself, input / output 1039 * arcs and DW samples. Resources could be reused then. 1040 * 1041 * @param dev 1042 * Pointer to Ethernet device structure. 1043 */ 1044 static void 1045 mlx5_flex_parser_ecpri_release(struct rte_eth_dev *dev) 1046 { 1047 struct mlx5_priv *priv = dev->data->dev_private; 1048 struct mlx5_ecpri_parser_profile *prf = &priv->sh->ecpri_parser; 1049 1050 if (prf->obj) 1051 mlx5_devx_cmd_destroy(prf->obj); 1052 prf->obj = NULL; 1053 } 1054 1055 /* 1056 * Allocation of a flex parser for srh. Once refcnt is zero, the resources held 1057 * by this parser will be freed. 1058 * @param dev 1059 * Pointer to Ethernet device structure. 1060 * 1061 * @return 1062 * 0 on success, a negative errno value otherwise and rte_errno is set. 1063 */ 1064 int 1065 mlx5_alloc_srh_flex_parser(struct rte_eth_dev *dev) 1066 { 1067 struct mlx5_devx_graph_node_attr node = { 1068 .modify_field_select = 0, 1069 }; 1070 uint32_t ids[MLX5_GRAPH_NODE_SAMPLE_NUM]; 1071 struct mlx5_priv *priv = dev->data->dev_private; 1072 struct mlx5_common_dev_config *config = &priv->sh->cdev->config; 1073 struct mlx5_hca_flex_attr *attr = &priv->sh->cdev->config.hca_attr.flex; 1074 void *fp = NULL, *ibv_ctx = priv->sh->cdev->ctx; 1075 int ret; 1076 1077 memset(ids, 0xff, sizeof(ids)); 1078 if (!config->hca_attr.parse_graph_flex_node || 1079 !config->hca_attr.flex.query_match_sample_info) { 1080 DRV_LOG(ERR, "Dynamic flex parser is not supported on HWS"); 1081 return -ENOTSUP; 1082 } 1083 if (__atomic_fetch_add(&priv->sh->srh_flex_parser.refcnt, 1, __ATOMIC_RELAXED) + 1 > 1) 1084 return 0; 1085 priv->sh->srh_flex_parser.flex.devx_fp = mlx5_malloc(MLX5_MEM_ZERO, 1086 sizeof(struct mlx5_flex_parser_devx), 0, SOCKET_ID_ANY); 1087 if (!priv->sh->srh_flex_parser.flex.devx_fp) 1088 return -ENOMEM; 1089 node.header_length_mode = MLX5_GRAPH_NODE_LEN_FIELD; 1090 /* Srv6 first two DW are not counted in. */ 1091 node.header_length_base_value = 0x8; 1092 /* The unit is uint64_t. */ 1093 node.header_length_field_shift = 0x3; 1094 /* Header length is the 2nd byte. */ 1095 node.header_length_field_offset = 0x8; 1096 if (attr->header_length_mask_width < 8) 1097 node.header_length_field_offset += 8 - attr->header_length_mask_width; 1098 node.header_length_field_mask = 0xF; 1099 /* One byte next header protocol. */ 1100 node.next_header_field_size = 0x8; 1101 node.in[0].arc_parse_graph_node = MLX5_GRAPH_ARC_NODE_IP; 1102 node.in[0].compare_condition_value = IPPROTO_ROUTING; 1103 node.sample[0].flow_match_sample_en = 1; 1104 /* First come first serve no matter inner or outer. */ 1105 node.sample[0].flow_match_sample_tunnel_mode = MLX5_GRAPH_SAMPLE_TUNNEL_FIRST; 1106 node.sample[0].flow_match_sample_offset_mode = MLX5_GRAPH_SAMPLE_OFFSET_FIXED; 1107 node.out[0].arc_parse_graph_node = MLX5_GRAPH_ARC_NODE_TCP; 1108 node.out[0].compare_condition_value = IPPROTO_TCP; 1109 node.out[1].arc_parse_graph_node = MLX5_GRAPH_ARC_NODE_UDP; 1110 node.out[1].compare_condition_value = IPPROTO_UDP; 1111 node.out[2].arc_parse_graph_node = MLX5_GRAPH_ARC_NODE_IPV6; 1112 node.out[2].compare_condition_value = IPPROTO_IPV6; 1113 fp = mlx5_devx_cmd_create_flex_parser(ibv_ctx, &node); 1114 if (!fp) { 1115 DRV_LOG(ERR, "Failed to create flex parser node object."); 1116 goto error; 1117 } 1118 priv->sh->srh_flex_parser.flex.devx_fp->devx_obj = fp; 1119 priv->sh->srh_flex_parser.flex.mapnum = 1; 1120 priv->sh->srh_flex_parser.flex.devx_fp->num_samples = 1; 1121 1122 ret = mlx5_devx_cmd_query_parse_samples(fp, ids, priv->sh->srh_flex_parser.flex.mapnum, 1123 &priv->sh->srh_flex_parser.flex.devx_fp->anchor_id); 1124 if (ret) { 1125 DRV_LOG(ERR, "Failed to query sample IDs."); 1126 goto error; 1127 } 1128 ret = mlx5_devx_cmd_match_sample_info_query(ibv_ctx, ids[0], 1129 &priv->sh->srh_flex_parser.flex.devx_fp->sample_info[0]); 1130 if (ret) { 1131 DRV_LOG(ERR, "Failed to query sample id information."); 1132 goto error; 1133 } 1134 return 0; 1135 error: 1136 if (fp) 1137 mlx5_devx_cmd_destroy(fp); 1138 if (priv->sh->srh_flex_parser.flex.devx_fp) 1139 mlx5_free(priv->sh->srh_flex_parser.flex.devx_fp); 1140 return (rte_errno == 0) ? -ENODEV : -rte_errno; 1141 } 1142 1143 /* 1144 * Destroy the flex parser node, including the parser itself, input / output 1145 * arcs and DW samples. Resources could be reused then. 1146 * 1147 * @param dev 1148 * Pointer to Ethernet device structure 1149 */ 1150 void 1151 mlx5_free_srh_flex_parser(struct rte_eth_dev *dev) 1152 { 1153 struct mlx5_priv *priv = dev->data->dev_private; 1154 struct mlx5_internal_flex_parser_profile *fp = &priv->sh->srh_flex_parser; 1155 1156 if (__atomic_fetch_sub(&fp->refcnt, 1, __ATOMIC_RELAXED) - 1) 1157 return; 1158 mlx5_devx_cmd_destroy(fp->flex.devx_fp->devx_obj); 1159 mlx5_free(fp->flex.devx_fp); 1160 fp->flex.devx_fp = NULL; 1161 } 1162 1163 uint32_t 1164 mlx5_get_supported_sw_parsing_offloads(const struct mlx5_hca_attr *attr) 1165 { 1166 uint32_t sw_parsing_offloads = 0; 1167 1168 if (attr->swp) { 1169 sw_parsing_offloads |= MLX5_SW_PARSING_CAP; 1170 if (attr->swp_csum) 1171 sw_parsing_offloads |= MLX5_SW_PARSING_CSUM_CAP; 1172 1173 if (attr->swp_lso) 1174 sw_parsing_offloads |= MLX5_SW_PARSING_TSO_CAP; 1175 } 1176 return sw_parsing_offloads; 1177 } 1178 1179 uint32_t 1180 mlx5_get_supported_tunneling_offloads(const struct mlx5_hca_attr *attr) 1181 { 1182 uint32_t tn_offloads = 0; 1183 1184 if (attr->tunnel_stateless_vxlan) 1185 tn_offloads |= MLX5_TUNNELED_OFFLOADS_VXLAN_CAP; 1186 if (attr->tunnel_stateless_gre) 1187 tn_offloads |= MLX5_TUNNELED_OFFLOADS_GRE_CAP; 1188 if (attr->tunnel_stateless_geneve_rx) 1189 tn_offloads |= MLX5_TUNNELED_OFFLOADS_GENEVE_CAP; 1190 return tn_offloads; 1191 } 1192 1193 /* Fill all fields of UAR structure. */ 1194 static int 1195 mlx5_rxtx_uars_prepare(struct mlx5_dev_ctx_shared *sh) 1196 { 1197 int ret; 1198 1199 ret = mlx5_devx_uar_prepare(sh->cdev, &sh->tx_uar); 1200 if (ret) { 1201 DRV_LOG(ERR, "Failed to prepare Tx DevX UAR."); 1202 return -rte_errno; 1203 } 1204 MLX5_ASSERT(sh->tx_uar.obj); 1205 MLX5_ASSERT(mlx5_os_get_devx_uar_base_addr(sh->tx_uar.obj)); 1206 ret = mlx5_devx_uar_prepare(sh->cdev, &sh->rx_uar); 1207 if (ret) { 1208 DRV_LOG(ERR, "Failed to prepare Rx DevX UAR."); 1209 mlx5_devx_uar_release(&sh->tx_uar); 1210 return -rte_errno; 1211 } 1212 MLX5_ASSERT(sh->rx_uar.obj); 1213 MLX5_ASSERT(mlx5_os_get_devx_uar_base_addr(sh->rx_uar.obj)); 1214 return 0; 1215 } 1216 1217 static void 1218 mlx5_rxtx_uars_release(struct mlx5_dev_ctx_shared *sh) 1219 { 1220 mlx5_devx_uar_release(&sh->rx_uar); 1221 mlx5_devx_uar_release(&sh->tx_uar); 1222 } 1223 1224 /** 1225 * rte_mempool_walk() callback to unregister Rx mempools. 1226 * It used when implicit mempool registration is disabled. 1227 * 1228 * @param mp 1229 * The mempool being walked. 1230 * @param arg 1231 * Pointer to the device shared context. 1232 */ 1233 static void 1234 mlx5_dev_ctx_shared_rx_mempool_unregister_cb(struct rte_mempool *mp, void *arg) 1235 { 1236 struct mlx5_dev_ctx_shared *sh = arg; 1237 1238 mlx5_dev_mempool_unregister(sh->cdev, mp); 1239 } 1240 1241 /** 1242 * Callback used when implicit mempool registration is disabled 1243 * in order to track Rx mempool destruction. 1244 * 1245 * @param event 1246 * Mempool life cycle event. 1247 * @param mp 1248 * An Rx mempool registered explicitly when the port is started. 1249 * @param arg 1250 * Pointer to a device shared context. 1251 */ 1252 static void 1253 mlx5_dev_ctx_shared_rx_mempool_event_cb(enum rte_mempool_event event, 1254 struct rte_mempool *mp, void *arg) 1255 { 1256 struct mlx5_dev_ctx_shared *sh = arg; 1257 1258 if (event == RTE_MEMPOOL_EVENT_DESTROY) 1259 mlx5_dev_mempool_unregister(sh->cdev, mp); 1260 } 1261 1262 int 1263 mlx5_dev_ctx_shared_mempool_subscribe(struct rte_eth_dev *dev) 1264 { 1265 struct mlx5_priv *priv = dev->data->dev_private; 1266 struct mlx5_dev_ctx_shared *sh = priv->sh; 1267 int ret; 1268 1269 /* Check if we only need to track Rx mempool destruction. */ 1270 if (!sh->cdev->config.mr_mempool_reg_en) { 1271 ret = rte_mempool_event_callback_register 1272 (mlx5_dev_ctx_shared_rx_mempool_event_cb, sh); 1273 return ret == 0 || rte_errno == EEXIST ? 0 : ret; 1274 } 1275 return mlx5_dev_mempool_subscribe(sh->cdev); 1276 } 1277 1278 /** 1279 * Set up multiple TISs with different affinities according to 1280 * number of bonding ports 1281 * 1282 * @param priv 1283 * Pointer of shared context. 1284 * 1285 * @return 1286 * Zero on success, -1 otherwise. 1287 */ 1288 static int 1289 mlx5_setup_tis(struct mlx5_dev_ctx_shared *sh) 1290 { 1291 struct mlx5_devx_lag_context lag_ctx = { 0 }; 1292 struct mlx5_devx_tis_attr tis_attr = { 0 }; 1293 int i; 1294 1295 tis_attr.transport_domain = sh->td->id; 1296 if (sh->bond.n_port) { 1297 if (!mlx5_devx_cmd_query_lag(sh->cdev->ctx, &lag_ctx)) { 1298 sh->lag.tx_remap_affinity[0] = 1299 lag_ctx.tx_remap_affinity_1; 1300 sh->lag.tx_remap_affinity[1] = 1301 lag_ctx.tx_remap_affinity_2; 1302 sh->lag.affinity_mode = lag_ctx.port_select_mode; 1303 } else { 1304 DRV_LOG(ERR, "Failed to query lag affinity."); 1305 return -1; 1306 } 1307 if (sh->lag.affinity_mode == MLX5_LAG_MODE_TIS) 1308 DRV_LOG(DEBUG, "LAG number of ports : %d, affinity_1 & 2 : pf%d & %d.\n", 1309 sh->bond.n_port, lag_ctx.tx_remap_affinity_1, 1310 lag_ctx.tx_remap_affinity_2); 1311 else if (sh->lag.affinity_mode == MLX5_LAG_MODE_HASH) 1312 DRV_LOG(INFO, "Device %s enabled HW hash based LAG.", 1313 sh->ibdev_name); 1314 } 1315 for (i = 0; i <= sh->bond.n_port; i++) { 1316 /* 1317 * lag_tx_port_affinity: 0 auto-selection, 1 PF1, 2 PF2 vice versa. 1318 * Each TIS binds to one PF by setting lag_tx_port_affinity (> 0). 1319 * Once LAG enabled, we create multiple TISs and bind each one to 1320 * different PFs, then TIS[i+1] gets affinity i+1 and goes to PF i+1. 1321 * TIS[0] is reserved for HW Hash mode. 1322 */ 1323 tis_attr.lag_tx_port_affinity = i; 1324 sh->tis[i] = mlx5_devx_cmd_create_tis(sh->cdev->ctx, &tis_attr); 1325 if (!sh->tis[i]) { 1326 DRV_LOG(ERR, "Failed to create TIS %d/%d for [bonding] device" 1327 " %s.", i, sh->bond.n_port, 1328 sh->ibdev_name); 1329 return -1; 1330 } 1331 } 1332 return 0; 1333 } 1334 1335 /** 1336 * Verify and store value for share device argument. 1337 * 1338 * @param[in] key 1339 * Key argument to verify. 1340 * @param[in] val 1341 * Value associated with key. 1342 * @param opaque 1343 * User data. 1344 * 1345 * @return 1346 * 0 on success, a negative errno value otherwise and rte_errno is set. 1347 */ 1348 static int 1349 mlx5_dev_args_check_handler(const char *key, const char *val, void *opaque) 1350 { 1351 struct mlx5_sh_config *config = opaque; 1352 signed long tmp; 1353 1354 errno = 0; 1355 tmp = strtol(val, NULL, 0); 1356 if (errno) { 1357 rte_errno = errno; 1358 DRV_LOG(WARNING, "%s: \"%s\" is not a valid integer", key, val); 1359 return -rte_errno; 1360 } 1361 if (tmp < 0 && strcmp(MLX5_TX_PP, key) && strcmp(MLX5_TX_SKEW, key)) { 1362 /* Negative values are acceptable for some keys only. */ 1363 rte_errno = EINVAL; 1364 DRV_LOG(WARNING, "%s: invalid negative value \"%s\"", key, val); 1365 return -rte_errno; 1366 } 1367 if (strcmp(MLX5_TX_PP, key) == 0) { 1368 unsigned long mod = tmp >= 0 ? tmp : -tmp; 1369 1370 if (!mod) { 1371 DRV_LOG(ERR, "Zero Tx packet pacing parameter."); 1372 rte_errno = EINVAL; 1373 return -rte_errno; 1374 } 1375 config->tx_pp = tmp; 1376 } else if (strcmp(MLX5_TX_SKEW, key) == 0) { 1377 config->tx_skew = tmp; 1378 } else if (strcmp(MLX5_L3_VXLAN_EN, key) == 0) { 1379 config->l3_vxlan_en = !!tmp; 1380 } else if (strcmp(MLX5_VF_NL_EN, key) == 0) { 1381 config->vf_nl_en = !!tmp; 1382 } else if (strcmp(MLX5_DV_ESW_EN, key) == 0) { 1383 config->dv_esw_en = !!tmp; 1384 } else if (strcmp(MLX5_DV_FLOW_EN, key) == 0) { 1385 if (tmp > 2) { 1386 DRV_LOG(ERR, "Invalid %s parameter.", key); 1387 rte_errno = EINVAL; 1388 return -rte_errno; 1389 } 1390 config->dv_flow_en = tmp; 1391 } else if (strcmp(MLX5_DV_XMETA_EN, key) == 0) { 1392 if (tmp != MLX5_XMETA_MODE_LEGACY && 1393 tmp != MLX5_XMETA_MODE_META16 && 1394 tmp != MLX5_XMETA_MODE_META32 && 1395 tmp != MLX5_XMETA_MODE_MISS_INFO && 1396 tmp != MLX5_XMETA_MODE_META32_HWS) { 1397 DRV_LOG(ERR, "Invalid extensive metadata parameter."); 1398 rte_errno = EINVAL; 1399 return -rte_errno; 1400 } 1401 if (tmp != MLX5_XMETA_MODE_MISS_INFO) 1402 config->dv_xmeta_en = tmp; 1403 else 1404 config->dv_miss_info = 1; 1405 } else if (strcmp(MLX5_LACP_BY_USER, key) == 0) { 1406 config->lacp_by_user = !!tmp; 1407 } else if (strcmp(MLX5_RECLAIM_MEM, key) == 0) { 1408 if (tmp != MLX5_RCM_NONE && 1409 tmp != MLX5_RCM_LIGHT && 1410 tmp != MLX5_RCM_AGGR) { 1411 DRV_LOG(ERR, "Unrecognize %s: \"%s\"", key, val); 1412 rte_errno = EINVAL; 1413 return -rte_errno; 1414 } 1415 config->reclaim_mode = tmp; 1416 } else if (strcmp(MLX5_DECAP_EN, key) == 0) { 1417 config->decap_en = !!tmp; 1418 } else if (strcmp(MLX5_ALLOW_DUPLICATE_PATTERN, key) == 0) { 1419 config->allow_duplicate_pattern = !!tmp; 1420 } else if (strcmp(MLX5_FDB_DEFAULT_RULE_EN, key) == 0) { 1421 config->fdb_def_rule = !!tmp; 1422 } else if (strcmp(MLX5_HWS_CNT_SERVICE_CORE, key) == 0) { 1423 config->cnt_svc.service_core = tmp; 1424 } else if (strcmp(MLX5_HWS_CNT_CYCLE_TIME, key) == 0) { 1425 config->cnt_svc.cycle_time = tmp; 1426 } else if (strcmp(MLX5_REPR_MATCHING_EN, key) == 0) { 1427 config->repr_matching = !!tmp; 1428 } 1429 return 0; 1430 } 1431 1432 /** 1433 * Parse user device parameters and adjust them according to device 1434 * capabilities. 1435 * 1436 * @param sh 1437 * Pointer to shared device context. 1438 * @param mkvlist 1439 * Pointer to mlx5 kvargs control, can be NULL if there is no devargs. 1440 * @param config 1441 * Pointer to shared device configuration structure. 1442 * 1443 * @return 1444 * 0 on success, a negative errno value otherwise and rte_errno is set. 1445 */ 1446 static int 1447 mlx5_shared_dev_ctx_args_config(struct mlx5_dev_ctx_shared *sh, 1448 struct mlx5_kvargs_ctrl *mkvlist, 1449 struct mlx5_sh_config *config) 1450 { 1451 const char **params = (const char *[]){ 1452 MLX5_TX_PP, 1453 MLX5_TX_SKEW, 1454 MLX5_L3_VXLAN_EN, 1455 MLX5_VF_NL_EN, 1456 MLX5_DV_ESW_EN, 1457 MLX5_DV_FLOW_EN, 1458 MLX5_DV_XMETA_EN, 1459 MLX5_LACP_BY_USER, 1460 MLX5_RECLAIM_MEM, 1461 MLX5_DECAP_EN, 1462 MLX5_ALLOW_DUPLICATE_PATTERN, 1463 MLX5_FDB_DEFAULT_RULE_EN, 1464 MLX5_HWS_CNT_SERVICE_CORE, 1465 MLX5_HWS_CNT_CYCLE_TIME, 1466 MLX5_REPR_MATCHING_EN, 1467 NULL, 1468 }; 1469 int ret = 0; 1470 1471 /* Default configuration. */ 1472 memset(config, 0, sizeof(*config)); 1473 config->vf_nl_en = 1; 1474 config->dv_esw_en = 1; 1475 config->dv_flow_en = 1; 1476 config->decap_en = 1; 1477 config->allow_duplicate_pattern = 1; 1478 config->fdb_def_rule = 1; 1479 config->cnt_svc.cycle_time = MLX5_CNT_SVC_CYCLE_TIME_DEFAULT; 1480 config->cnt_svc.service_core = rte_get_main_lcore(); 1481 config->repr_matching = 1; 1482 if (mkvlist != NULL) { 1483 /* Process parameters. */ 1484 ret = mlx5_kvargs_process(mkvlist, params, 1485 mlx5_dev_args_check_handler, config); 1486 if (ret) { 1487 DRV_LOG(ERR, "Failed to process device arguments: %s", 1488 strerror(rte_errno)); 1489 return -rte_errno; 1490 } 1491 } 1492 /* Adjust parameters according to device capabilities. */ 1493 if (config->dv_flow_en && !sh->dev_cap.dv_flow_en) { 1494 DRV_LOG(WARNING, "DV flow is not supported."); 1495 config->dv_flow_en = 0; 1496 } 1497 if (config->dv_esw_en && !sh->dev_cap.dv_esw_en) { 1498 DRV_LOG(DEBUG, "E-Switch DV flow is not supported."); 1499 config->dv_esw_en = 0; 1500 } 1501 if (config->dv_esw_en && !config->dv_flow_en) { 1502 DRV_LOG(DEBUG, 1503 "E-Switch DV flow is supported only when DV flow is enabled."); 1504 config->dv_esw_en = 0; 1505 } 1506 if (config->dv_miss_info && config->dv_esw_en) 1507 config->dv_xmeta_en = MLX5_XMETA_MODE_META16; 1508 if (!config->dv_esw_en && 1509 config->dv_xmeta_en != MLX5_XMETA_MODE_LEGACY) { 1510 DRV_LOG(WARNING, 1511 "Metadata mode %u is not supported (no E-Switch).", 1512 config->dv_xmeta_en); 1513 config->dv_xmeta_en = MLX5_XMETA_MODE_LEGACY; 1514 } 1515 if (config->dv_flow_en != 2 && !config->repr_matching) { 1516 DRV_LOG(DEBUG, "Disabling representor matching is valid only " 1517 "when HW Steering is enabled."); 1518 config->repr_matching = 1; 1519 } 1520 if (config->tx_pp && !sh->dev_cap.txpp_en) { 1521 DRV_LOG(ERR, "Packet pacing is not supported."); 1522 rte_errno = ENODEV; 1523 return -rte_errno; 1524 } 1525 if (!config->tx_pp && config->tx_skew && 1526 !sh->cdev->config.hca_attr.wait_on_time) { 1527 DRV_LOG(WARNING, 1528 "\"tx_skew\" doesn't affect without \"tx_pp\"."); 1529 } 1530 /* Check for LRO support. */ 1531 if (mlx5_devx_obj_ops_en(sh) && sh->cdev->config.hca_attr.lro_cap) { 1532 /* TBD check tunnel lro caps. */ 1533 config->lro_allowed = 1; 1534 DRV_LOG(DEBUG, "LRO is allowed."); 1535 DRV_LOG(DEBUG, 1536 "LRO minimal size of TCP segment required for coalescing is %d bytes.", 1537 sh->cdev->config.hca_attr.lro_min_mss_size); 1538 } 1539 /* 1540 * If HW has bug working with tunnel packet decapsulation and scatter 1541 * FCS, and decapsulation is needed, clear the hw_fcs_strip bit. 1542 * Then RTE_ETH_RX_OFFLOAD_KEEP_CRC bit will not be set anymore. 1543 */ 1544 if (sh->dev_cap.scatter_fcs_w_decap_disable && sh->config.decap_en) 1545 config->hw_fcs_strip = 0; 1546 else 1547 config->hw_fcs_strip = sh->dev_cap.hw_fcs_strip; 1548 DRV_LOG(DEBUG, "FCS stripping configuration is %ssupported", 1549 (config->hw_fcs_strip ? "" : "not ")); 1550 DRV_LOG(DEBUG, "\"tx_pp\" is %d.", config->tx_pp); 1551 DRV_LOG(DEBUG, "\"tx_skew\" is %d.", config->tx_skew); 1552 DRV_LOG(DEBUG, "\"reclaim_mode\" is %u.", config->reclaim_mode); 1553 DRV_LOG(DEBUG, "\"dv_esw_en\" is %u.", config->dv_esw_en); 1554 DRV_LOG(DEBUG, "\"dv_flow_en\" is %u.", config->dv_flow_en); 1555 DRV_LOG(DEBUG, "\"dv_xmeta_en\" is %u.", config->dv_xmeta_en); 1556 DRV_LOG(DEBUG, "\"dv_miss_info\" is %u.", config->dv_miss_info); 1557 DRV_LOG(DEBUG, "\"l3_vxlan_en\" is %u.", config->l3_vxlan_en); 1558 DRV_LOG(DEBUG, "\"vf_nl_en\" is %u.", config->vf_nl_en); 1559 DRV_LOG(DEBUG, "\"lacp_by_user\" is %u.", config->lacp_by_user); 1560 DRV_LOG(DEBUG, "\"decap_en\" is %u.", config->decap_en); 1561 DRV_LOG(DEBUG, "\"allow_duplicate_pattern\" is %u.", 1562 config->allow_duplicate_pattern); 1563 DRV_LOG(DEBUG, "\"fdb_def_rule_en\" is %u.", config->fdb_def_rule); 1564 DRV_LOG(DEBUG, "\"repr_matching_en\" is %u.", config->repr_matching); 1565 return 0; 1566 } 1567 1568 /** 1569 * Configure realtime timestamp format. 1570 * 1571 * @param sh 1572 * Pointer to mlx5_dev_ctx_shared object. 1573 * @param hca_attr 1574 * Pointer to DevX HCA capabilities structure. 1575 */ 1576 void 1577 mlx5_rt_timestamp_config(struct mlx5_dev_ctx_shared *sh, 1578 struct mlx5_hca_attr *hca_attr) 1579 { 1580 uint32_t dw_cnt = MLX5_ST_SZ_DW(register_mtutc); 1581 uint32_t reg[dw_cnt]; 1582 int ret = ENOTSUP; 1583 1584 if (hca_attr->access_register_user) 1585 ret = mlx5_devx_cmd_register_read(sh->cdev->ctx, 1586 MLX5_REGISTER_ID_MTUTC, 0, 1587 reg, dw_cnt); 1588 if (!ret) { 1589 uint32_t ts_mode; 1590 1591 /* MTUTC register is read successfully. */ 1592 ts_mode = MLX5_GET(register_mtutc, reg, time_stamp_mode); 1593 if (ts_mode == MLX5_MTUTC_TIMESTAMP_MODE_REAL_TIME) 1594 sh->dev_cap.rt_timestamp = 1; 1595 } else { 1596 /* Kernel does not support register reading. */ 1597 if (hca_attr->dev_freq_khz == (NS_PER_S / MS_PER_S)) 1598 sh->dev_cap.rt_timestamp = 1; 1599 } 1600 } 1601 1602 /** 1603 * Allocate shared device context. If there is multiport device the 1604 * master and representors will share this context, if there is single 1605 * port dedicated device, the context will be used by only given 1606 * port due to unification. 1607 * 1608 * Routine first searches the context for the specified device name, 1609 * if found the shared context assumed and reference counter is incremented. 1610 * If no context found the new one is created and initialized with specified 1611 * device context and parameters. 1612 * 1613 * @param[in] spawn 1614 * Pointer to the device attributes (name, port, etc). 1615 * @param mkvlist 1616 * Pointer to mlx5 kvargs control, can be NULL if there is no devargs. 1617 * 1618 * @return 1619 * Pointer to mlx5_dev_ctx_shared object on success, 1620 * otherwise NULL and rte_errno is set. 1621 */ 1622 struct mlx5_dev_ctx_shared * 1623 mlx5_alloc_shared_dev_ctx(const struct mlx5_dev_spawn_data *spawn, 1624 struct mlx5_kvargs_ctrl *mkvlist) 1625 { 1626 struct mlx5_dev_ctx_shared *sh; 1627 int err = 0; 1628 uint32_t i; 1629 1630 MLX5_ASSERT(spawn); 1631 /* Secondary process should not create the shared context. */ 1632 MLX5_ASSERT(rte_eal_process_type() == RTE_PROC_PRIMARY); 1633 pthread_mutex_lock(&mlx5_dev_ctx_list_mutex); 1634 /* Search for IB context by device name. */ 1635 LIST_FOREACH(sh, &mlx5_dev_ctx_list, next) { 1636 if (!strcmp(sh->ibdev_name, spawn->phys_dev_name)) { 1637 sh->refcnt++; 1638 goto exit; 1639 } 1640 } 1641 /* No device found, we have to create new shared context. */ 1642 MLX5_ASSERT(spawn->max_port); 1643 sh = mlx5_malloc(MLX5_MEM_ZERO | MLX5_MEM_RTE, 1644 sizeof(struct mlx5_dev_ctx_shared) + 1645 spawn->max_port * sizeof(struct mlx5_dev_shared_port), 1646 RTE_CACHE_LINE_SIZE, SOCKET_ID_ANY); 1647 if (!sh) { 1648 DRV_LOG(ERR, "Shared context allocation failure."); 1649 rte_errno = ENOMEM; 1650 goto exit; 1651 } 1652 pthread_mutex_init(&sh->txpp.mutex, NULL); 1653 sh->numa_node = spawn->cdev->dev->numa_node; 1654 sh->cdev = spawn->cdev; 1655 sh->esw_mode = !!(spawn->info.master || spawn->info.representor); 1656 if (spawn->bond_info) 1657 sh->bond = *spawn->bond_info; 1658 err = mlx5_os_capabilities_prepare(sh); 1659 if (err) { 1660 DRV_LOG(ERR, "Fail to configure device capabilities."); 1661 goto error; 1662 } 1663 err = mlx5_shared_dev_ctx_args_config(sh, mkvlist, &sh->config); 1664 if (err) { 1665 DRV_LOG(ERR, "Failed to process device configure: %s", 1666 strerror(rte_errno)); 1667 goto error; 1668 } 1669 sh->refcnt = 1; 1670 sh->max_port = spawn->max_port; 1671 strncpy(sh->ibdev_name, mlx5_os_get_ctx_device_name(sh->cdev->ctx), 1672 sizeof(sh->ibdev_name) - 1); 1673 strncpy(sh->ibdev_path, mlx5_os_get_ctx_device_path(sh->cdev->ctx), 1674 sizeof(sh->ibdev_path) - 1); 1675 /* 1676 * Setting port_id to max unallowed value means there is no interrupt 1677 * subhandler installed for the given port index i. 1678 */ 1679 for (i = 0; i < sh->max_port; i++) { 1680 sh->port[i].ih_port_id = RTE_MAX_ETHPORTS; 1681 sh->port[i].devx_ih_port_id = RTE_MAX_ETHPORTS; 1682 sh->port[i].nl_ih_port_id = RTE_MAX_ETHPORTS; 1683 } 1684 if (sh->cdev->config.devx) { 1685 sh->td = mlx5_devx_cmd_create_td(sh->cdev->ctx); 1686 if (!sh->td) { 1687 DRV_LOG(ERR, "TD allocation failure"); 1688 rte_errno = ENOMEM; 1689 goto error; 1690 } 1691 if (mlx5_setup_tis(sh)) { 1692 DRV_LOG(ERR, "TIS allocation failure"); 1693 rte_errno = ENOMEM; 1694 goto error; 1695 } 1696 err = mlx5_rxtx_uars_prepare(sh); 1697 if (err) 1698 goto error; 1699 #ifndef RTE_ARCH_64 1700 } else { 1701 /* Initialize UAR access locks for 32bit implementations. */ 1702 rte_spinlock_init(&sh->uar_lock_cq); 1703 for (i = 0; i < MLX5_UAR_PAGE_NUM_MAX; i++) 1704 rte_spinlock_init(&sh->uar_lock[i]); 1705 #endif 1706 } 1707 mlx5_os_dev_shared_handler_install(sh); 1708 if (LIST_EMPTY(&mlx5_dev_ctx_list)) { 1709 err = mlx5_flow_os_init_workspace_once(); 1710 if (err) 1711 goto error; 1712 } 1713 err = mlx5_flow_counters_mng_init(sh); 1714 if (err) { 1715 DRV_LOG(ERR, "Fail to initialize counters manage."); 1716 goto error; 1717 } 1718 mlx5_flow_aging_init(sh); 1719 mlx5_flow_ipool_create(sh); 1720 /* Add context to the global device list. */ 1721 LIST_INSERT_HEAD(&mlx5_dev_ctx_list, sh, next); 1722 rte_spinlock_init(&sh->geneve_tlv_opt_sl); 1723 exit: 1724 pthread_mutex_unlock(&mlx5_dev_ctx_list_mutex); 1725 return sh; 1726 error: 1727 err = rte_errno; 1728 pthread_mutex_destroy(&sh->txpp.mutex); 1729 pthread_mutex_unlock(&mlx5_dev_ctx_list_mutex); 1730 MLX5_ASSERT(sh); 1731 mlx5_rxtx_uars_release(sh); 1732 i = 0; 1733 do { 1734 if (sh->tis[i]) 1735 claim_zero(mlx5_devx_cmd_destroy(sh->tis[i])); 1736 } while (++i <= (uint32_t)sh->bond.n_port); 1737 if (sh->td) 1738 claim_zero(mlx5_devx_cmd_destroy(sh->td)); 1739 mlx5_free(sh); 1740 rte_errno = err; 1741 return NULL; 1742 } 1743 1744 /** 1745 * Create LWM event_channel and interrupt handle for shared device 1746 * context. All rxqs sharing the device context share the event_channel. 1747 * A callback is registered in interrupt thread to receive the LWM event. 1748 * 1749 * @param[in] priv 1750 * Pointer to mlx5_priv instance. 1751 * 1752 * @return 1753 * 0 on success, negative with rte_errno set. 1754 */ 1755 int 1756 mlx5_lwm_setup(struct mlx5_priv *priv) 1757 { 1758 int fd_lwm; 1759 1760 pthread_mutex_init(&priv->sh->lwm_config_lock, NULL); 1761 priv->sh->devx_channel_lwm = mlx5_os_devx_create_event_channel 1762 (priv->sh->cdev->ctx, 1763 MLX5DV_DEVX_CREATE_EVENT_CHANNEL_FLAGS_OMIT_EV_DATA); 1764 if (!priv->sh->devx_channel_lwm) 1765 goto err; 1766 fd_lwm = mlx5_os_get_devx_channel_fd(priv->sh->devx_channel_lwm); 1767 priv->sh->intr_handle_lwm = mlx5_os_interrupt_handler_create 1768 (RTE_INTR_INSTANCE_F_SHARED, true, 1769 fd_lwm, mlx5_dev_interrupt_handler_lwm, priv); 1770 if (!priv->sh->intr_handle_lwm) 1771 goto err; 1772 return 0; 1773 err: 1774 if (priv->sh->devx_channel_lwm) { 1775 mlx5_os_devx_destroy_event_channel 1776 (priv->sh->devx_channel_lwm); 1777 priv->sh->devx_channel_lwm = NULL; 1778 } 1779 pthread_mutex_destroy(&priv->sh->lwm_config_lock); 1780 return -rte_errno; 1781 } 1782 1783 /** 1784 * Destroy LWM event_channel and interrupt handle for shared device 1785 * context before free this context. The interrupt handler is also 1786 * unregistered. 1787 * 1788 * @param[in] sh 1789 * Pointer to shared device context. 1790 */ 1791 void 1792 mlx5_lwm_unset(struct mlx5_dev_ctx_shared *sh) 1793 { 1794 if (sh->intr_handle_lwm) { 1795 mlx5_os_interrupt_handler_destroy(sh->intr_handle_lwm, 1796 mlx5_dev_interrupt_handler_lwm, (void *)-1); 1797 sh->intr_handle_lwm = NULL; 1798 } 1799 if (sh->devx_channel_lwm) { 1800 mlx5_os_devx_destroy_event_channel 1801 (sh->devx_channel_lwm); 1802 sh->devx_channel_lwm = NULL; 1803 } 1804 pthread_mutex_destroy(&sh->lwm_config_lock); 1805 } 1806 1807 /** 1808 * Free shared IB device context. Decrement counter and if zero free 1809 * all allocated resources and close handles. 1810 * 1811 * @param[in] sh 1812 * Pointer to mlx5_dev_ctx_shared object to free 1813 */ 1814 void 1815 mlx5_free_shared_dev_ctx(struct mlx5_dev_ctx_shared *sh) 1816 { 1817 int ret; 1818 int i = 0; 1819 1820 pthread_mutex_lock(&mlx5_dev_ctx_list_mutex); 1821 #ifdef RTE_LIBRTE_MLX5_DEBUG 1822 /* Check the object presence in the list. */ 1823 struct mlx5_dev_ctx_shared *lctx; 1824 1825 LIST_FOREACH(lctx, &mlx5_dev_ctx_list, next) 1826 if (lctx == sh) 1827 break; 1828 MLX5_ASSERT(lctx); 1829 if (lctx != sh) { 1830 DRV_LOG(ERR, "Freeing non-existing shared IB context"); 1831 goto exit; 1832 } 1833 #endif 1834 MLX5_ASSERT(sh); 1835 MLX5_ASSERT(sh->refcnt); 1836 /* Secondary process should not free the shared context. */ 1837 MLX5_ASSERT(rte_eal_process_type() == RTE_PROC_PRIMARY); 1838 if (--sh->refcnt) 1839 goto exit; 1840 /* Stop watching for mempool events and unregister all mempools. */ 1841 if (!sh->cdev->config.mr_mempool_reg_en) { 1842 ret = rte_mempool_event_callback_unregister 1843 (mlx5_dev_ctx_shared_rx_mempool_event_cb, sh); 1844 if (ret == 0) 1845 rte_mempool_walk 1846 (mlx5_dev_ctx_shared_rx_mempool_unregister_cb, sh); 1847 } 1848 /* Remove context from the global device list. */ 1849 LIST_REMOVE(sh, next); 1850 /* Release resources on the last device removal. */ 1851 if (LIST_EMPTY(&mlx5_dev_ctx_list)) { 1852 mlx5_os_net_cleanup(); 1853 mlx5_flow_os_release_workspace(); 1854 mlx5_flow_workspace_gc_release(); 1855 } 1856 pthread_mutex_unlock(&mlx5_dev_ctx_list_mutex); 1857 if (sh->flex_parsers_dv) { 1858 mlx5_list_destroy(sh->flex_parsers_dv); 1859 sh->flex_parsers_dv = NULL; 1860 } 1861 /* 1862 * Ensure there is no async event handler installed. 1863 * Only primary process handles async device events. 1864 **/ 1865 mlx5_flow_counters_mng_close(sh); 1866 if (sh->ct_mng) 1867 mlx5_flow_aso_ct_mng_close(sh); 1868 if (sh->aso_age_mng) { 1869 mlx5_flow_aso_age_mng_close(sh); 1870 sh->aso_age_mng = NULL; 1871 } 1872 if (sh->mtrmng) 1873 mlx5_aso_flow_mtrs_mng_close(sh); 1874 mlx5_flow_ipool_destroy(sh); 1875 mlx5_os_dev_shared_handler_uninstall(sh); 1876 mlx5_rxtx_uars_release(sh); 1877 do { 1878 if (sh->tis[i]) 1879 claim_zero(mlx5_devx_cmd_destroy(sh->tis[i])); 1880 } while (++i <= sh->bond.n_port); 1881 if (sh->td) 1882 claim_zero(mlx5_devx_cmd_destroy(sh->td)); 1883 #ifdef HAVE_MLX5_HWS_SUPPORT 1884 /* HWS manages geneve_tlv_option resource as global. */ 1885 if (sh->config.dv_flow_en == 2) 1886 flow_dev_geneve_tlv_option_resource_release(sh); 1887 else 1888 #endif 1889 MLX5_ASSERT(sh->geneve_tlv_option_resource == NULL); 1890 pthread_mutex_destroy(&sh->txpp.mutex); 1891 mlx5_lwm_unset(sh); 1892 mlx5_free(sh); 1893 return; 1894 exit: 1895 pthread_mutex_unlock(&mlx5_dev_ctx_list_mutex); 1896 } 1897 1898 /** 1899 * Destroy table hash list. 1900 * 1901 * @param[in] priv 1902 * Pointer to the private device data structure. 1903 */ 1904 void 1905 mlx5_free_table_hash_list(struct mlx5_priv *priv) 1906 { 1907 struct mlx5_dev_ctx_shared *sh = priv->sh; 1908 struct mlx5_hlist **tbls = (priv->sh->config.dv_flow_en == 2) ? 1909 &sh->groups : &sh->flow_tbls; 1910 if (*tbls == NULL) 1911 return; 1912 mlx5_hlist_destroy(*tbls); 1913 *tbls = NULL; 1914 } 1915 1916 #ifdef HAVE_MLX5_HWS_SUPPORT 1917 /** 1918 * Allocate HW steering group hash list. 1919 * 1920 * @param[in] priv 1921 * Pointer to the private device data structure. 1922 */ 1923 static int 1924 mlx5_alloc_hw_group_hash_list(struct mlx5_priv *priv) 1925 { 1926 int err = 0; 1927 struct mlx5_dev_ctx_shared *sh = priv->sh; 1928 char s[MLX5_NAME_SIZE]; 1929 1930 MLX5_ASSERT(sh); 1931 snprintf(s, sizeof(s), "%s_flow_groups", priv->sh->ibdev_name); 1932 sh->groups = mlx5_hlist_create 1933 (s, MLX5_FLOW_TABLE_HLIST_ARRAY_SIZE, 1934 false, true, sh, 1935 flow_hw_grp_create_cb, 1936 flow_hw_grp_match_cb, 1937 flow_hw_grp_remove_cb, 1938 flow_hw_grp_clone_cb, 1939 flow_hw_grp_clone_free_cb); 1940 if (!sh->groups) { 1941 DRV_LOG(ERR, "flow groups with hash creation failed."); 1942 err = ENOMEM; 1943 } 1944 return err; 1945 } 1946 #endif 1947 1948 1949 /** 1950 * Initialize flow table hash list and create the root tables entry 1951 * for each domain. 1952 * 1953 * @param[in] priv 1954 * Pointer to the private device data structure. 1955 * 1956 * @return 1957 * Zero on success, positive error code otherwise. 1958 */ 1959 int 1960 mlx5_alloc_table_hash_list(struct mlx5_priv *priv __rte_unused) 1961 { 1962 int err = 0; 1963 1964 /* Tables are only used in DV and DR modes. */ 1965 #if defined(HAVE_IBV_FLOW_DV_SUPPORT) || !defined(HAVE_INFINIBAND_VERBS_H) 1966 struct mlx5_dev_ctx_shared *sh = priv->sh; 1967 char s[MLX5_NAME_SIZE]; 1968 1969 #ifdef HAVE_MLX5_HWS_SUPPORT 1970 if (priv->sh->config.dv_flow_en == 2) 1971 return mlx5_alloc_hw_group_hash_list(priv); 1972 #endif 1973 MLX5_ASSERT(sh); 1974 snprintf(s, sizeof(s), "%s_flow_table", priv->sh->ibdev_name); 1975 sh->flow_tbls = mlx5_hlist_create(s, MLX5_FLOW_TABLE_HLIST_ARRAY_SIZE, 1976 false, true, sh, 1977 flow_dv_tbl_create_cb, 1978 flow_dv_tbl_match_cb, 1979 flow_dv_tbl_remove_cb, 1980 flow_dv_tbl_clone_cb, 1981 flow_dv_tbl_clone_free_cb); 1982 if (!sh->flow_tbls) { 1983 DRV_LOG(ERR, "flow tables with hash creation failed."); 1984 err = ENOMEM; 1985 return err; 1986 } 1987 #ifndef HAVE_MLX5DV_DR 1988 struct rte_flow_error error; 1989 struct rte_eth_dev *dev = &rte_eth_devices[priv->dev_data->port_id]; 1990 1991 /* 1992 * In case we have not DR support, the zero tables should be created 1993 * because DV expect to see them even if they cannot be created by 1994 * RDMA-CORE. 1995 */ 1996 if (!flow_dv_tbl_resource_get(dev, 0, 0, 0, 0, 1997 NULL, 0, 1, 0, &error) || 1998 !flow_dv_tbl_resource_get(dev, 0, 1, 0, 0, 1999 NULL, 0, 1, 0, &error) || 2000 !flow_dv_tbl_resource_get(dev, 0, 0, 1, 0, 2001 NULL, 0, 1, 0, &error)) { 2002 err = ENOMEM; 2003 goto error; 2004 } 2005 return err; 2006 error: 2007 mlx5_free_table_hash_list(priv); 2008 #endif /* HAVE_MLX5DV_DR */ 2009 #endif 2010 return err; 2011 } 2012 2013 /** 2014 * Retrieve integer value from environment variable. 2015 * 2016 * @param[in] name 2017 * Environment variable name. 2018 * 2019 * @return 2020 * Integer value, 0 if the variable is not set. 2021 */ 2022 int 2023 mlx5_getenv_int(const char *name) 2024 { 2025 const char *val = getenv(name); 2026 2027 if (val == NULL) 2028 return 0; 2029 return atoi(val); 2030 } 2031 2032 /** 2033 * DPDK callback to add udp tunnel port 2034 * 2035 * @param[in] dev 2036 * A pointer to eth_dev 2037 * @param[in] udp_tunnel 2038 * A pointer to udp tunnel 2039 * 2040 * @return 2041 * 0 on valid udp ports and tunnels, -ENOTSUP otherwise. 2042 */ 2043 int 2044 mlx5_udp_tunnel_port_add(struct rte_eth_dev *dev __rte_unused, 2045 struct rte_eth_udp_tunnel *udp_tunnel) 2046 { 2047 MLX5_ASSERT(udp_tunnel != NULL); 2048 if (udp_tunnel->prot_type == RTE_ETH_TUNNEL_TYPE_VXLAN && 2049 udp_tunnel->udp_port == 4789) 2050 return 0; 2051 if (udp_tunnel->prot_type == RTE_ETH_TUNNEL_TYPE_VXLAN_GPE && 2052 udp_tunnel->udp_port == 4790) 2053 return 0; 2054 return -ENOTSUP; 2055 } 2056 2057 /** 2058 * Initialize process private data structure. 2059 * 2060 * @param dev 2061 * Pointer to Ethernet device structure. 2062 * 2063 * @return 2064 * 0 on success, a negative errno value otherwise and rte_errno is set. 2065 */ 2066 int 2067 mlx5_proc_priv_init(struct rte_eth_dev *dev) 2068 { 2069 struct mlx5_priv *priv = dev->data->dev_private; 2070 struct mlx5_proc_priv *ppriv; 2071 size_t ppriv_size; 2072 2073 mlx5_proc_priv_uninit(dev); 2074 /* 2075 * UAR register table follows the process private structure. BlueFlame 2076 * registers for Tx queues are stored in the table. 2077 */ 2078 ppriv_size = sizeof(struct mlx5_proc_priv) + 2079 priv->txqs_n * sizeof(struct mlx5_uar_data); 2080 ppriv = mlx5_malloc(MLX5_MEM_RTE | MLX5_MEM_ZERO, ppriv_size, 2081 RTE_CACHE_LINE_SIZE, dev->device->numa_node); 2082 if (!ppriv) { 2083 rte_errno = ENOMEM; 2084 return -rte_errno; 2085 } 2086 ppriv->uar_table_sz = priv->txqs_n; 2087 dev->process_private = ppriv; 2088 if (rte_eal_process_type() == RTE_PROC_PRIMARY) 2089 priv->sh->pppriv = ppriv; 2090 return 0; 2091 } 2092 2093 /** 2094 * Un-initialize process private data structure. 2095 * 2096 * @param dev 2097 * Pointer to Ethernet device structure. 2098 */ 2099 void 2100 mlx5_proc_priv_uninit(struct rte_eth_dev *dev) 2101 { 2102 struct mlx5_proc_priv *ppriv = dev->process_private; 2103 2104 if (!ppriv) 2105 return; 2106 if (ppriv->hca_bar) 2107 mlx5_txpp_unmap_hca_bar(dev); 2108 mlx5_free(dev->process_private); 2109 dev->process_private = NULL; 2110 } 2111 2112 /** 2113 * DPDK callback to close the device. 2114 * 2115 * Destroy all queues and objects, free memory. 2116 * 2117 * @param dev 2118 * Pointer to Ethernet device structure. 2119 */ 2120 int 2121 mlx5_dev_close(struct rte_eth_dev *dev) 2122 { 2123 struct mlx5_priv *priv = dev->data->dev_private; 2124 unsigned int i; 2125 int ret; 2126 2127 if (rte_eal_process_type() == RTE_PROC_SECONDARY) { 2128 /* Check if process_private released. */ 2129 if (!dev->process_private) 2130 return 0; 2131 mlx5_tx_uar_uninit_secondary(dev); 2132 mlx5_proc_priv_uninit(dev); 2133 rte_eth_dev_release_port(dev); 2134 return 0; 2135 } 2136 if (!priv->sh) 2137 return 0; 2138 if (priv->shared_refcnt) { 2139 DRV_LOG(ERR, "port %u is shared host in use (%u)", 2140 dev->data->port_id, priv->shared_refcnt); 2141 rte_errno = EBUSY; 2142 return -EBUSY; 2143 } 2144 DRV_LOG(DEBUG, "port %u closing device \"%s\"", 2145 dev->data->port_id, 2146 ((priv->sh->cdev->ctx != NULL) ? 2147 mlx5_os_get_ctx_device_name(priv->sh->cdev->ctx) : "")); 2148 /* 2149 * If default mreg copy action is removed at the stop stage, 2150 * the search will return none and nothing will be done anymore. 2151 */ 2152 if (priv->sh->config.dv_flow_en != 2) 2153 mlx5_flow_stop_default(dev); 2154 mlx5_traffic_disable(dev); 2155 /* 2156 * If all the flows are already flushed in the device stop stage, 2157 * then this will return directly without any action. 2158 */ 2159 mlx5_flow_list_flush(dev, MLX5_FLOW_TYPE_GEN, true); 2160 mlx5_action_handle_flush(dev); 2161 mlx5_flow_meter_flush(dev, NULL); 2162 /* Prevent crashes when queues are still in use. */ 2163 dev->rx_pkt_burst = rte_eth_pkt_burst_dummy; 2164 dev->tx_pkt_burst = rte_eth_pkt_burst_dummy; 2165 rte_wmb(); 2166 /* Disable datapath on secondary process. */ 2167 mlx5_mp_os_req_stop_rxtx(dev); 2168 /* Free the eCPRI flex parser resource. */ 2169 mlx5_flex_parser_ecpri_release(dev); 2170 mlx5_flex_item_port_cleanup(dev); 2171 #ifdef HAVE_MLX5_HWS_SUPPORT 2172 flow_hw_destroy_vport_action(dev); 2173 flow_hw_resource_release(dev); 2174 flow_hw_clear_port_info(dev); 2175 if (priv->sh->config.dv_flow_en == 2) { 2176 flow_hw_clear_flow_metadata_config(); 2177 flow_hw_clear_tags_set(dev); 2178 } 2179 #endif 2180 if (priv->rxq_privs != NULL) { 2181 /* XXX race condition if mlx5_rx_burst() is still running. */ 2182 rte_delay_us_sleep(1000); 2183 for (i = 0; (i != priv->rxqs_n); ++i) 2184 mlx5_rxq_release(dev, i); 2185 priv->rxqs_n = 0; 2186 mlx5_free(priv->rxq_privs); 2187 priv->rxq_privs = NULL; 2188 } 2189 if (priv->txqs != NULL) { 2190 /* XXX race condition if mlx5_tx_burst() is still running. */ 2191 rte_delay_us_sleep(1000); 2192 for (i = 0; (i != priv->txqs_n); ++i) 2193 mlx5_txq_release(dev, i); 2194 priv->txqs_n = 0; 2195 priv->txqs = NULL; 2196 } 2197 mlx5_proc_priv_uninit(dev); 2198 if (priv->q_counters) { 2199 mlx5_devx_cmd_destroy(priv->q_counters); 2200 priv->q_counters = NULL; 2201 } 2202 if (priv->drop_queue.hrxq) 2203 mlx5_drop_action_destroy(dev); 2204 if (priv->mreg_cp_tbl) 2205 mlx5_hlist_destroy(priv->mreg_cp_tbl); 2206 mlx5_mprq_free_mp(dev); 2207 mlx5_os_free_shared_dr(priv); 2208 if (priv->rss_conf.rss_key != NULL) 2209 mlx5_free(priv->rss_conf.rss_key); 2210 if (priv->reta_idx != NULL) 2211 mlx5_free(priv->reta_idx); 2212 if (priv->sh->dev_cap.vf) 2213 mlx5_os_mac_addr_flush(dev); 2214 if (priv->nl_socket_route >= 0) 2215 close(priv->nl_socket_route); 2216 if (priv->nl_socket_rdma >= 0) 2217 close(priv->nl_socket_rdma); 2218 if (priv->vmwa_context) 2219 mlx5_vlan_vmwa_exit(priv->vmwa_context); 2220 ret = mlx5_hrxq_verify(dev); 2221 if (ret) 2222 DRV_LOG(WARNING, "port %u some hash Rx queue still remain", 2223 dev->data->port_id); 2224 ret = mlx5_ind_table_obj_verify(dev); 2225 if (ret) 2226 DRV_LOG(WARNING, "port %u some indirection table still remain", 2227 dev->data->port_id); 2228 ret = mlx5_rxq_obj_verify(dev); 2229 if (ret) 2230 DRV_LOG(WARNING, "port %u some Rx queue objects still remain", 2231 dev->data->port_id); 2232 ret = mlx5_ext_rxq_verify(dev); 2233 if (ret) 2234 DRV_LOG(WARNING, "Port %u some external RxQ still remain.", 2235 dev->data->port_id); 2236 ret = mlx5_rxq_verify(dev); 2237 if (ret) 2238 DRV_LOG(WARNING, "port %u some Rx queues still remain", 2239 dev->data->port_id); 2240 ret = mlx5_txq_obj_verify(dev); 2241 if (ret) 2242 DRV_LOG(WARNING, "port %u some Verbs Tx queue still remain", 2243 dev->data->port_id); 2244 ret = mlx5_txq_verify(dev); 2245 if (ret) 2246 DRV_LOG(WARNING, "port %u some Tx queues still remain", 2247 dev->data->port_id); 2248 ret = mlx5_flow_verify(dev); 2249 if (ret) 2250 DRV_LOG(WARNING, "port %u some flows still remain", 2251 dev->data->port_id); 2252 if (priv->hrxqs) 2253 mlx5_list_destroy(priv->hrxqs); 2254 mlx5_free(priv->ext_rxqs); 2255 priv->sh->port[priv->dev_port - 1].nl_ih_port_id = RTE_MAX_ETHPORTS; 2256 /* 2257 * The interrupt handler port id must be reset before priv is reset 2258 * since 'mlx5_dev_interrupt_nl_cb' uses priv. 2259 */ 2260 rte_io_wmb(); 2261 /* 2262 * Free the shared context in last turn, because the cleanup 2263 * routines above may use some shared fields, like 2264 * mlx5_os_mac_addr_flush() uses ibdev_path for retrieving 2265 * ifindex if Netlink fails. 2266 */ 2267 mlx5_free_shared_dev_ctx(priv->sh); 2268 if (priv->domain_id != RTE_ETH_DEV_SWITCH_DOMAIN_ID_INVALID) { 2269 unsigned int c = 0; 2270 uint16_t port_id; 2271 2272 MLX5_ETH_FOREACH_DEV(port_id, dev->device) { 2273 struct mlx5_priv *opriv = 2274 rte_eth_devices[port_id].data->dev_private; 2275 2276 if (!opriv || 2277 opriv->domain_id != priv->domain_id || 2278 &rte_eth_devices[port_id] == dev) 2279 continue; 2280 ++c; 2281 break; 2282 } 2283 if (!c) 2284 claim_zero(rte_eth_switch_domain_free(priv->domain_id)); 2285 } 2286 memset(priv, 0, sizeof(*priv)); 2287 priv->domain_id = RTE_ETH_DEV_SWITCH_DOMAIN_ID_INVALID; 2288 /* 2289 * Reset mac_addrs to NULL such that it is not freed as part of 2290 * rte_eth_dev_release_port(). mac_addrs is part of dev_private so 2291 * it is freed when dev_private is freed. 2292 */ 2293 dev->data->mac_addrs = NULL; 2294 return 0; 2295 } 2296 2297 const struct eth_dev_ops mlx5_dev_ops = { 2298 .dev_configure = mlx5_dev_configure, 2299 .dev_start = mlx5_dev_start, 2300 .dev_stop = mlx5_dev_stop, 2301 .dev_set_link_down = mlx5_set_link_down, 2302 .dev_set_link_up = mlx5_set_link_up, 2303 .dev_close = mlx5_dev_close, 2304 .promiscuous_enable = mlx5_promiscuous_enable, 2305 .promiscuous_disable = mlx5_promiscuous_disable, 2306 .allmulticast_enable = mlx5_allmulticast_enable, 2307 .allmulticast_disable = mlx5_allmulticast_disable, 2308 .link_update = mlx5_link_update, 2309 .stats_get = mlx5_stats_get, 2310 .stats_reset = mlx5_stats_reset, 2311 .xstats_get = mlx5_xstats_get, 2312 .xstats_reset = mlx5_xstats_reset, 2313 .xstats_get_names = mlx5_xstats_get_names, 2314 .fw_version_get = mlx5_fw_version_get, 2315 .dev_infos_get = mlx5_dev_infos_get, 2316 .representor_info_get = mlx5_representor_info_get, 2317 .read_clock = mlx5_txpp_read_clock, 2318 .dev_supported_ptypes_get = mlx5_dev_supported_ptypes_get, 2319 .vlan_filter_set = mlx5_vlan_filter_set, 2320 .rx_queue_setup = mlx5_rx_queue_setup, 2321 .rx_queue_avail_thresh_set = mlx5_rx_queue_lwm_set, 2322 .rx_queue_avail_thresh_query = mlx5_rx_queue_lwm_query, 2323 .rx_hairpin_queue_setup = mlx5_rx_hairpin_queue_setup, 2324 .tx_queue_setup = mlx5_tx_queue_setup, 2325 .tx_hairpin_queue_setup = mlx5_tx_hairpin_queue_setup, 2326 .rx_queue_release = mlx5_rx_queue_release, 2327 .tx_queue_release = mlx5_tx_queue_release, 2328 .rx_queue_start = mlx5_rx_queue_start, 2329 .rx_queue_stop = mlx5_rx_queue_stop, 2330 .tx_queue_start = mlx5_tx_queue_start, 2331 .tx_queue_stop = mlx5_tx_queue_stop, 2332 .flow_ctrl_get = mlx5_dev_get_flow_ctrl, 2333 .flow_ctrl_set = mlx5_dev_set_flow_ctrl, 2334 .mac_addr_remove = mlx5_mac_addr_remove, 2335 .mac_addr_add = mlx5_mac_addr_add, 2336 .mac_addr_set = mlx5_mac_addr_set, 2337 .set_mc_addr_list = mlx5_set_mc_addr_list, 2338 .mtu_set = mlx5_dev_set_mtu, 2339 .vlan_strip_queue_set = mlx5_vlan_strip_queue_set, 2340 .vlan_offload_set = mlx5_vlan_offload_set, 2341 .reta_update = mlx5_dev_rss_reta_update, 2342 .reta_query = mlx5_dev_rss_reta_query, 2343 .rss_hash_update = mlx5_rss_hash_update, 2344 .rss_hash_conf_get = mlx5_rss_hash_conf_get, 2345 .flow_ops_get = mlx5_flow_ops_get, 2346 .rxq_info_get = mlx5_rxq_info_get, 2347 .txq_info_get = mlx5_txq_info_get, 2348 .rx_burst_mode_get = mlx5_rx_burst_mode_get, 2349 .tx_burst_mode_get = mlx5_tx_burst_mode_get, 2350 .rx_queue_intr_enable = mlx5_rx_intr_enable, 2351 .rx_queue_intr_disable = mlx5_rx_intr_disable, 2352 .is_removed = mlx5_is_removed, 2353 .udp_tunnel_port_add = mlx5_udp_tunnel_port_add, 2354 .get_module_info = mlx5_get_module_info, 2355 .get_module_eeprom = mlx5_get_module_eeprom, 2356 .hairpin_cap_get = mlx5_hairpin_cap_get, 2357 .mtr_ops_get = mlx5_flow_meter_ops_get, 2358 .hairpin_bind = mlx5_hairpin_bind, 2359 .hairpin_unbind = mlx5_hairpin_unbind, 2360 .hairpin_get_peer_ports = mlx5_hairpin_get_peer_ports, 2361 .hairpin_queue_peer_update = mlx5_hairpin_queue_peer_update, 2362 .hairpin_queue_peer_bind = mlx5_hairpin_queue_peer_bind, 2363 .hairpin_queue_peer_unbind = mlx5_hairpin_queue_peer_unbind, 2364 .get_monitor_addr = mlx5_get_monitor_addr, 2365 .count_aggr_ports = mlx5_count_aggr_ports, 2366 .map_aggr_tx_affinity = mlx5_map_aggr_tx_affinity, 2367 .rx_metadata_negotiate = mlx5_flow_rx_metadata_negotiate, 2368 }; 2369 2370 /* Available operations from secondary process. */ 2371 const struct eth_dev_ops mlx5_dev_sec_ops = { 2372 .stats_get = mlx5_stats_get, 2373 .stats_reset = mlx5_stats_reset, 2374 .xstats_get = mlx5_xstats_get, 2375 .xstats_reset = mlx5_xstats_reset, 2376 .xstats_get_names = mlx5_xstats_get_names, 2377 .fw_version_get = mlx5_fw_version_get, 2378 .dev_infos_get = mlx5_dev_infos_get, 2379 .representor_info_get = mlx5_representor_info_get, 2380 .read_clock = mlx5_txpp_read_clock, 2381 .rx_queue_start = mlx5_rx_queue_start, 2382 .rx_queue_stop = mlx5_rx_queue_stop, 2383 .tx_queue_start = mlx5_tx_queue_start, 2384 .tx_queue_stop = mlx5_tx_queue_stop, 2385 .rxq_info_get = mlx5_rxq_info_get, 2386 .txq_info_get = mlx5_txq_info_get, 2387 .rx_burst_mode_get = mlx5_rx_burst_mode_get, 2388 .tx_burst_mode_get = mlx5_tx_burst_mode_get, 2389 .get_module_info = mlx5_get_module_info, 2390 .get_module_eeprom = mlx5_get_module_eeprom, 2391 .count_aggr_ports = mlx5_count_aggr_ports, 2392 .map_aggr_tx_affinity = mlx5_map_aggr_tx_affinity, 2393 .rx_metadata_negotiate = mlx5_flow_rx_metadata_negotiate, 2394 }; 2395 2396 /* Available operations in flow isolated mode. */ 2397 const struct eth_dev_ops mlx5_dev_ops_isolate = { 2398 .dev_configure = mlx5_dev_configure, 2399 .dev_start = mlx5_dev_start, 2400 .dev_stop = mlx5_dev_stop, 2401 .dev_set_link_down = mlx5_set_link_down, 2402 .dev_set_link_up = mlx5_set_link_up, 2403 .dev_close = mlx5_dev_close, 2404 .promiscuous_enable = mlx5_promiscuous_enable, 2405 .promiscuous_disable = mlx5_promiscuous_disable, 2406 .allmulticast_enable = mlx5_allmulticast_enable, 2407 .allmulticast_disable = mlx5_allmulticast_disable, 2408 .link_update = mlx5_link_update, 2409 .stats_get = mlx5_stats_get, 2410 .stats_reset = mlx5_stats_reset, 2411 .xstats_get = mlx5_xstats_get, 2412 .xstats_reset = mlx5_xstats_reset, 2413 .xstats_get_names = mlx5_xstats_get_names, 2414 .fw_version_get = mlx5_fw_version_get, 2415 .dev_infos_get = mlx5_dev_infos_get, 2416 .representor_info_get = mlx5_representor_info_get, 2417 .read_clock = mlx5_txpp_read_clock, 2418 .dev_supported_ptypes_get = mlx5_dev_supported_ptypes_get, 2419 .vlan_filter_set = mlx5_vlan_filter_set, 2420 .rx_queue_setup = mlx5_rx_queue_setup, 2421 .rx_hairpin_queue_setup = mlx5_rx_hairpin_queue_setup, 2422 .tx_queue_setup = mlx5_tx_queue_setup, 2423 .tx_hairpin_queue_setup = mlx5_tx_hairpin_queue_setup, 2424 .rx_queue_release = mlx5_rx_queue_release, 2425 .tx_queue_release = mlx5_tx_queue_release, 2426 .rx_queue_start = mlx5_rx_queue_start, 2427 .rx_queue_stop = mlx5_rx_queue_stop, 2428 .tx_queue_start = mlx5_tx_queue_start, 2429 .tx_queue_stop = mlx5_tx_queue_stop, 2430 .flow_ctrl_get = mlx5_dev_get_flow_ctrl, 2431 .flow_ctrl_set = mlx5_dev_set_flow_ctrl, 2432 .mac_addr_remove = mlx5_mac_addr_remove, 2433 .mac_addr_add = mlx5_mac_addr_add, 2434 .mac_addr_set = mlx5_mac_addr_set, 2435 .set_mc_addr_list = mlx5_set_mc_addr_list, 2436 .mtu_set = mlx5_dev_set_mtu, 2437 .vlan_strip_queue_set = mlx5_vlan_strip_queue_set, 2438 .vlan_offload_set = mlx5_vlan_offload_set, 2439 .flow_ops_get = mlx5_flow_ops_get, 2440 .rxq_info_get = mlx5_rxq_info_get, 2441 .txq_info_get = mlx5_txq_info_get, 2442 .rx_burst_mode_get = mlx5_rx_burst_mode_get, 2443 .tx_burst_mode_get = mlx5_tx_burst_mode_get, 2444 .rx_queue_intr_enable = mlx5_rx_intr_enable, 2445 .rx_queue_intr_disable = mlx5_rx_intr_disable, 2446 .is_removed = mlx5_is_removed, 2447 .get_module_info = mlx5_get_module_info, 2448 .get_module_eeprom = mlx5_get_module_eeprom, 2449 .hairpin_cap_get = mlx5_hairpin_cap_get, 2450 .mtr_ops_get = mlx5_flow_meter_ops_get, 2451 .hairpin_bind = mlx5_hairpin_bind, 2452 .hairpin_unbind = mlx5_hairpin_unbind, 2453 .hairpin_get_peer_ports = mlx5_hairpin_get_peer_ports, 2454 .hairpin_queue_peer_update = mlx5_hairpin_queue_peer_update, 2455 .hairpin_queue_peer_bind = mlx5_hairpin_queue_peer_bind, 2456 .hairpin_queue_peer_unbind = mlx5_hairpin_queue_peer_unbind, 2457 .get_monitor_addr = mlx5_get_monitor_addr, 2458 .count_aggr_ports = mlx5_count_aggr_ports, 2459 .map_aggr_tx_affinity = mlx5_map_aggr_tx_affinity, 2460 }; 2461 2462 /** 2463 * Verify and store value for device argument. 2464 * 2465 * @param[in] key 2466 * Key argument to verify. 2467 * @param[in] val 2468 * Value associated with key. 2469 * @param opaque 2470 * User data. 2471 * 2472 * @return 2473 * 0 on success, a negative errno value otherwise and rte_errno is set. 2474 */ 2475 static int 2476 mlx5_port_args_check_handler(const char *key, const char *val, void *opaque) 2477 { 2478 struct mlx5_port_config *config = opaque; 2479 signed long tmp; 2480 2481 /* No-op, port representors are processed in mlx5_dev_spawn(). */ 2482 if (!strcmp(MLX5_REPRESENTOR, key)) 2483 return 0; 2484 errno = 0; 2485 tmp = strtol(val, NULL, 0); 2486 if (errno) { 2487 rte_errno = errno; 2488 DRV_LOG(WARNING, "%s: \"%s\" is not a valid integer", key, val); 2489 return -rte_errno; 2490 } 2491 if (tmp < 0) { 2492 /* Negative values are acceptable for some keys only. */ 2493 rte_errno = EINVAL; 2494 DRV_LOG(WARNING, "%s: invalid negative value \"%s\"", key, val); 2495 return -rte_errno; 2496 } 2497 if (strcmp(MLX5_RXQ_CQE_COMP_EN, key) == 0) { 2498 if ((tmp & ~MLX5_RXQ_ENH_CQE_COMP_MASK) > 2499 MLX5_CQE_RESP_FORMAT_L34H_STRIDX) { 2500 DRV_LOG(ERR, "invalid CQE compression " 2501 "format parameter"); 2502 rte_errno = EINVAL; 2503 return -rte_errno; 2504 } 2505 config->cqe_comp = !!tmp; 2506 config->cqe_comp_fmt = tmp & ~MLX5_RXQ_ENH_CQE_COMP_MASK; 2507 config->enh_cqe_comp = !!(tmp & MLX5_RXQ_ENH_CQE_COMP_MASK); 2508 } else if (strcmp(MLX5_RXQ_PKT_PAD_EN, key) == 0) { 2509 config->hw_padding = !!tmp; 2510 } else if (strcmp(MLX5_RX_MPRQ_EN, key) == 0) { 2511 config->mprq.enabled = !!tmp; 2512 } else if (strcmp(MLX5_RX_MPRQ_LOG_STRIDE_NUM, key) == 0) { 2513 config->mprq.log_stride_num = tmp; 2514 } else if (strcmp(MLX5_RX_MPRQ_LOG_STRIDE_SIZE, key) == 0) { 2515 config->mprq.log_stride_size = tmp; 2516 } else if (strcmp(MLX5_RX_MPRQ_MAX_MEMCPY_LEN, key) == 0) { 2517 config->mprq.max_memcpy_len = tmp; 2518 } else if (strcmp(MLX5_RXQS_MIN_MPRQ, key) == 0) { 2519 config->mprq.min_rxqs_num = tmp; 2520 } else if (strcmp(MLX5_TXQ_INLINE, key) == 0) { 2521 DRV_LOG(WARNING, "%s: deprecated parameter," 2522 " converted to txq_inline_max", key); 2523 config->txq_inline_max = tmp; 2524 } else if (strcmp(MLX5_TXQ_INLINE_MAX, key) == 0) { 2525 config->txq_inline_max = tmp; 2526 } else if (strcmp(MLX5_TXQ_INLINE_MIN, key) == 0) { 2527 config->txq_inline_min = tmp; 2528 } else if (strcmp(MLX5_TXQ_INLINE_MPW, key) == 0) { 2529 config->txq_inline_mpw = tmp; 2530 } else if (strcmp(MLX5_TXQS_MIN_INLINE, key) == 0) { 2531 config->txqs_inline = tmp; 2532 } else if (strcmp(MLX5_TXQS_MAX_VEC, key) == 0) { 2533 DRV_LOG(WARNING, "%s: deprecated parameter, ignored", key); 2534 } else if (strcmp(MLX5_TXQ_MPW_EN, key) == 0) { 2535 config->mps = !!tmp; 2536 } else if (strcmp(MLX5_TXQ_MPW_HDR_DSEG_EN, key) == 0) { 2537 DRV_LOG(WARNING, "%s: deprecated parameter, ignored", key); 2538 } else if (strcmp(MLX5_TXQ_MAX_INLINE_LEN, key) == 0) { 2539 DRV_LOG(WARNING, "%s: deprecated parameter," 2540 " converted to txq_inline_mpw", key); 2541 config->txq_inline_mpw = tmp; 2542 } else if (strcmp(MLX5_TX_VEC_EN, key) == 0) { 2543 DRV_LOG(WARNING, "%s: deprecated parameter, ignored", key); 2544 } else if (strcmp(MLX5_RX_VEC_EN, key) == 0) { 2545 config->rx_vec_en = !!tmp; 2546 } else if (strcmp(MLX5_MAX_DUMP_FILES_NUM, key) == 0) { 2547 config->max_dump_files_num = tmp; 2548 } else if (strcmp(MLX5_LRO_TIMEOUT_USEC, key) == 0) { 2549 config->lro_timeout = tmp; 2550 } else if (strcmp(MLX5_HP_BUF_SIZE, key) == 0) { 2551 config->log_hp_size = tmp; 2552 } else if (strcmp(MLX5_DELAY_DROP, key) == 0) { 2553 config->std_delay_drop = !!(tmp & MLX5_DELAY_DROP_STANDARD); 2554 config->hp_delay_drop = !!(tmp & MLX5_DELAY_DROP_HAIRPIN); 2555 } 2556 return 0; 2557 } 2558 2559 /** 2560 * Parse user port parameters and adjust them according to device capabilities. 2561 * 2562 * @param priv 2563 * Pointer to shared device context. 2564 * @param mkvlist 2565 * Pointer to mlx5 kvargs control, can be NULL if there is no devargs. 2566 * @param config 2567 * Pointer to port configuration structure. 2568 * 2569 * @return 2570 * 0 on success, a negative errno value otherwise and rte_errno is set. 2571 */ 2572 int 2573 mlx5_port_args_config(struct mlx5_priv *priv, struct mlx5_kvargs_ctrl *mkvlist, 2574 struct mlx5_port_config *config) 2575 { 2576 struct mlx5_hca_attr *hca_attr = &priv->sh->cdev->config.hca_attr; 2577 struct mlx5_dev_cap *dev_cap = &priv->sh->dev_cap; 2578 bool devx = priv->sh->cdev->config.devx; 2579 const char **params = (const char *[]){ 2580 MLX5_RXQ_CQE_COMP_EN, 2581 MLX5_RXQ_PKT_PAD_EN, 2582 MLX5_RX_MPRQ_EN, 2583 MLX5_RX_MPRQ_LOG_STRIDE_NUM, 2584 MLX5_RX_MPRQ_LOG_STRIDE_SIZE, 2585 MLX5_RX_MPRQ_MAX_MEMCPY_LEN, 2586 MLX5_RXQS_MIN_MPRQ, 2587 MLX5_TXQ_INLINE, 2588 MLX5_TXQ_INLINE_MIN, 2589 MLX5_TXQ_INLINE_MAX, 2590 MLX5_TXQ_INLINE_MPW, 2591 MLX5_TXQS_MIN_INLINE, 2592 MLX5_TXQS_MAX_VEC, 2593 MLX5_TXQ_MPW_EN, 2594 MLX5_TXQ_MPW_HDR_DSEG_EN, 2595 MLX5_TXQ_MAX_INLINE_LEN, 2596 MLX5_TX_VEC_EN, 2597 MLX5_RX_VEC_EN, 2598 MLX5_REPRESENTOR, 2599 MLX5_MAX_DUMP_FILES_NUM, 2600 MLX5_LRO_TIMEOUT_USEC, 2601 MLX5_HP_BUF_SIZE, 2602 MLX5_DELAY_DROP, 2603 NULL, 2604 }; 2605 int ret = 0; 2606 2607 /* Default configuration. */ 2608 memset(config, 0, sizeof(*config)); 2609 config->mps = MLX5_ARG_UNSET; 2610 config->cqe_comp = 1; 2611 config->rx_vec_en = 1; 2612 config->txq_inline_max = MLX5_ARG_UNSET; 2613 config->txq_inline_min = MLX5_ARG_UNSET; 2614 config->txq_inline_mpw = MLX5_ARG_UNSET; 2615 config->txqs_inline = MLX5_ARG_UNSET; 2616 config->mprq.max_memcpy_len = MLX5_MPRQ_MEMCPY_DEFAULT_LEN; 2617 config->mprq.min_rxqs_num = MLX5_MPRQ_MIN_RXQS; 2618 config->mprq.log_stride_num = MLX5_MPRQ_DEFAULT_LOG_STRIDE_NUM; 2619 config->mprq.log_stride_size = MLX5_MPRQ_DEFAULT_LOG_STRIDE_SIZE; 2620 config->log_hp_size = MLX5_ARG_UNSET; 2621 config->std_delay_drop = 0; 2622 config->hp_delay_drop = 0; 2623 if (mkvlist != NULL) { 2624 /* Process parameters. */ 2625 ret = mlx5_kvargs_process(mkvlist, params, 2626 mlx5_port_args_check_handler, config); 2627 if (ret) { 2628 DRV_LOG(ERR, "Failed to process port arguments: %s", 2629 strerror(rte_errno)); 2630 return -rte_errno; 2631 } 2632 } 2633 /* Adjust parameters according to device capabilities. */ 2634 if (config->hw_padding && !dev_cap->hw_padding) { 2635 DRV_LOG(DEBUG, "Rx end alignment padding isn't supported."); 2636 config->hw_padding = 0; 2637 } else if (config->hw_padding) { 2638 DRV_LOG(DEBUG, "Rx end alignment padding is enabled."); 2639 } 2640 /* 2641 * MPW is disabled by default, while the Enhanced MPW is enabled 2642 * by default. 2643 */ 2644 if (config->mps == MLX5_ARG_UNSET) 2645 config->mps = (dev_cap->mps == MLX5_MPW_ENHANCED) ? 2646 MLX5_MPW_ENHANCED : MLX5_MPW_DISABLED; 2647 else 2648 config->mps = config->mps ? dev_cap->mps : MLX5_MPW_DISABLED; 2649 DRV_LOG(INFO, "%sMPS is %s", 2650 config->mps == MLX5_MPW_ENHANCED ? "enhanced " : 2651 config->mps == MLX5_MPW ? "legacy " : "", 2652 config->mps != MLX5_MPW_DISABLED ? "enabled" : "disabled"); 2653 if (priv->sh->config.lro_allowed) { 2654 /* 2655 * If LRO timeout is not configured by application, 2656 * use the minimal supported value. 2657 */ 2658 if (!config->lro_timeout) 2659 config->lro_timeout = 2660 hca_attr->lro_timer_supported_periods[0]; 2661 DRV_LOG(DEBUG, "LRO session timeout set to %d usec.", 2662 config->lro_timeout); 2663 } 2664 if (config->cqe_comp && !dev_cap->cqe_comp) { 2665 DRV_LOG(WARNING, "Rx CQE 128B compression is not supported."); 2666 config->cqe_comp = 0; 2667 } 2668 if (config->cqe_comp_fmt == MLX5_CQE_RESP_FORMAT_FTAG_STRIDX && 2669 (!devx || !hca_attr->mini_cqe_resp_flow_tag)) { 2670 DRV_LOG(WARNING, 2671 "Flow Tag CQE compression format isn't supported."); 2672 config->cqe_comp = 0; 2673 } 2674 if (config->cqe_comp_fmt == MLX5_CQE_RESP_FORMAT_L34H_STRIDX && 2675 (!devx || !hca_attr->mini_cqe_resp_l3_l4_tag)) { 2676 DRV_LOG(WARNING, 2677 "L3/L4 Header CQE compression format isn't supported."); 2678 config->cqe_comp = 0; 2679 } 2680 if (config->enh_cqe_comp && !hca_attr->enhanced_cqe_compression) { 2681 DRV_LOG(WARNING, 2682 "Enhanced CQE compression isn't supported."); 2683 config->enh_cqe_comp = 0; 2684 } 2685 DRV_LOG(DEBUG, "%sRx CQE compression is %ssupported.", 2686 config->enh_cqe_comp ? "Enhanced " : "", 2687 config->cqe_comp ? "" : "not "); 2688 if ((config->std_delay_drop || config->hp_delay_drop) && 2689 !dev_cap->rq_delay_drop_en) { 2690 config->std_delay_drop = 0; 2691 config->hp_delay_drop = 0; 2692 DRV_LOG(WARNING, "dev_port-%u: Rxq delay drop isn't supported.", 2693 priv->dev_port); 2694 } 2695 if (config->mprq.enabled && !priv->sh->dev_cap.mprq.enabled) { 2696 DRV_LOG(WARNING, "Multi-Packet RQ isn't supported."); 2697 config->mprq.enabled = 0; 2698 } 2699 if (config->max_dump_files_num == 0) 2700 config->max_dump_files_num = 128; 2701 /* Detect minimal data bytes to inline. */ 2702 mlx5_set_min_inline(priv); 2703 DRV_LOG(DEBUG, "VLAN insertion in WQE is %ssupported.", 2704 config->hw_vlan_insert ? "" : "not "); 2705 DRV_LOG(DEBUG, "\"rxq_pkt_pad_en\" is %u.", config->hw_padding); 2706 DRV_LOG(DEBUG, "\"rxq_cqe_comp_en\" is %u.", config->cqe_comp); 2707 DRV_LOG(DEBUG, "\"cqe_comp_fmt\" is %u.", config->cqe_comp_fmt); 2708 DRV_LOG(DEBUG, "\"enh_cqe_comp\" is %u.", config->enh_cqe_comp); 2709 DRV_LOG(DEBUG, "\"rx_vec_en\" is %u.", config->rx_vec_en); 2710 DRV_LOG(DEBUG, "Standard \"delay_drop\" is %u.", 2711 config->std_delay_drop); 2712 DRV_LOG(DEBUG, "Hairpin \"delay_drop\" is %u.", config->hp_delay_drop); 2713 DRV_LOG(DEBUG, "\"max_dump_files_num\" is %u.", 2714 config->max_dump_files_num); 2715 DRV_LOG(DEBUG, "\"log_hp_size\" is %u.", config->log_hp_size); 2716 DRV_LOG(DEBUG, "\"mprq_en\" is %u.", config->mprq.enabled); 2717 DRV_LOG(DEBUG, "\"mprq_log_stride_num\" is %u.", 2718 config->mprq.log_stride_num); 2719 DRV_LOG(DEBUG, "\"mprq_log_stride_size\" is %u.", 2720 config->mprq.log_stride_size); 2721 DRV_LOG(DEBUG, "\"mprq_max_memcpy_len\" is %u.", 2722 config->mprq.max_memcpy_len); 2723 DRV_LOG(DEBUG, "\"rxqs_min_mprq\" is %u.", config->mprq.min_rxqs_num); 2724 DRV_LOG(DEBUG, "\"lro_timeout_usec\" is %u.", config->lro_timeout); 2725 DRV_LOG(DEBUG, "\"txq_mpw_en\" is %d.", config->mps); 2726 DRV_LOG(DEBUG, "\"txqs_min_inline\" is %d.", config->txqs_inline); 2727 DRV_LOG(DEBUG, "\"txq_inline_min\" is %d.", config->txq_inline_min); 2728 DRV_LOG(DEBUG, "\"txq_inline_max\" is %d.", config->txq_inline_max); 2729 DRV_LOG(DEBUG, "\"txq_inline_mpw\" is %d.", config->txq_inline_mpw); 2730 return 0; 2731 } 2732 2733 /** 2734 * Print the key for device argument. 2735 * 2736 * It is "dummy" handler whose whole purpose is to enable using 2737 * mlx5_kvargs_process() function which set devargs as used. 2738 * 2739 * @param key 2740 * Key argument. 2741 * @param val 2742 * Value associated with key, unused. 2743 * @param opaque 2744 * Unused, can be NULL. 2745 * 2746 * @return 2747 * 0 on success, function cannot fail. 2748 */ 2749 static int 2750 mlx5_dummy_handler(const char *key, const char *val, void *opaque) 2751 { 2752 DRV_LOG(DEBUG, "\tKey: \"%s\" is set as used.", key); 2753 RTE_SET_USED(opaque); 2754 RTE_SET_USED(val); 2755 return 0; 2756 } 2757 2758 /** 2759 * Set requested devargs as used when device is already spawned. 2760 * 2761 * It is necessary since it is valid to ask probe again for existing device, 2762 * if its devargs don't assign as used, mlx5_kvargs_validate() will fail. 2763 * 2764 * @param name 2765 * Name of the existing device. 2766 * @param port_id 2767 * Port identifier of the device. 2768 * @param mkvlist 2769 * Pointer to mlx5 kvargs control to sign as used. 2770 */ 2771 void 2772 mlx5_port_args_set_used(const char *name, uint16_t port_id, 2773 struct mlx5_kvargs_ctrl *mkvlist) 2774 { 2775 const char **params = (const char *[]){ 2776 MLX5_RXQ_CQE_COMP_EN, 2777 MLX5_RXQ_PKT_PAD_EN, 2778 MLX5_RX_MPRQ_EN, 2779 MLX5_RX_MPRQ_LOG_STRIDE_NUM, 2780 MLX5_RX_MPRQ_LOG_STRIDE_SIZE, 2781 MLX5_RX_MPRQ_MAX_MEMCPY_LEN, 2782 MLX5_RXQS_MIN_MPRQ, 2783 MLX5_TXQ_INLINE, 2784 MLX5_TXQ_INLINE_MIN, 2785 MLX5_TXQ_INLINE_MAX, 2786 MLX5_TXQ_INLINE_MPW, 2787 MLX5_TXQS_MIN_INLINE, 2788 MLX5_TXQS_MAX_VEC, 2789 MLX5_TXQ_MPW_EN, 2790 MLX5_TXQ_MPW_HDR_DSEG_EN, 2791 MLX5_TXQ_MAX_INLINE_LEN, 2792 MLX5_TX_VEC_EN, 2793 MLX5_RX_VEC_EN, 2794 MLX5_REPRESENTOR, 2795 MLX5_MAX_DUMP_FILES_NUM, 2796 MLX5_LRO_TIMEOUT_USEC, 2797 MLX5_HP_BUF_SIZE, 2798 MLX5_DELAY_DROP, 2799 NULL, 2800 }; 2801 2802 /* Secondary process should not handle devargs. */ 2803 if (rte_eal_process_type() != RTE_PROC_PRIMARY) 2804 return; 2805 MLX5_ASSERT(mkvlist != NULL); 2806 DRV_LOG(DEBUG, "Ethernet device \"%s\" for port %u " 2807 "already exists, set devargs as used:", name, port_id); 2808 /* This function cannot fail with this handler. */ 2809 mlx5_kvargs_process(mkvlist, params, mlx5_dummy_handler, NULL); 2810 } 2811 2812 /** 2813 * Check sibling device configurations when probing again. 2814 * 2815 * Sibling devices sharing infiniband device context should have compatible 2816 * configurations. This regards representors and bonding device. 2817 * 2818 * @param cdev 2819 * Pointer to mlx5 device structure. 2820 * @param mkvlist 2821 * Pointer to mlx5 kvargs control, can be NULL if there is no devargs. 2822 * 2823 * @return 2824 * 0 on success, a negative errno value otherwise and rte_errno is set. 2825 */ 2826 int 2827 mlx5_probe_again_args_validate(struct mlx5_common_device *cdev, 2828 struct mlx5_kvargs_ctrl *mkvlist) 2829 { 2830 struct mlx5_dev_ctx_shared *sh = NULL; 2831 struct mlx5_sh_config *config; 2832 int ret; 2833 2834 /* Secondary process should not handle devargs. */ 2835 if (rte_eal_process_type() != RTE_PROC_PRIMARY) 2836 return 0; 2837 pthread_mutex_lock(&mlx5_dev_ctx_list_mutex); 2838 /* Search for IB context by common device pointer. */ 2839 LIST_FOREACH(sh, &mlx5_dev_ctx_list, next) 2840 if (sh->cdev == cdev) 2841 break; 2842 pthread_mutex_unlock(&mlx5_dev_ctx_list_mutex); 2843 /* There is sh for this device -> it isn't probe again. */ 2844 if (sh == NULL) 2845 return 0; 2846 config = mlx5_malloc(MLX5_MEM_ZERO | MLX5_MEM_RTE, 2847 sizeof(struct mlx5_sh_config), 2848 RTE_CACHE_LINE_SIZE, SOCKET_ID_ANY); 2849 if (config == NULL) { 2850 rte_errno = -ENOMEM; 2851 return -rte_errno; 2852 } 2853 /* 2854 * Creates a temporary IB context configure structure according to new 2855 * devargs attached in probing again. 2856 */ 2857 ret = mlx5_shared_dev_ctx_args_config(sh, mkvlist, config); 2858 if (ret) { 2859 DRV_LOG(ERR, "Failed to process device configure: %s", 2860 strerror(rte_errno)); 2861 mlx5_free(config); 2862 return ret; 2863 } 2864 /* 2865 * Checks the match between the temporary structure and the existing 2866 * IB context structure. 2867 */ 2868 if (sh->config.dv_flow_en ^ config->dv_flow_en) { 2869 DRV_LOG(ERR, "\"dv_flow_en\" " 2870 "configuration mismatch for shared %s context.", 2871 sh->ibdev_name); 2872 goto error; 2873 } 2874 if ((sh->config.dv_xmeta_en ^ config->dv_xmeta_en) || 2875 (sh->config.dv_miss_info ^ config->dv_miss_info)) { 2876 DRV_LOG(ERR, "\"dv_xmeta_en\" " 2877 "configuration mismatch for shared %s context.", 2878 sh->ibdev_name); 2879 goto error; 2880 } 2881 if (sh->config.dv_esw_en ^ config->dv_esw_en) { 2882 DRV_LOG(ERR, "\"dv_esw_en\" " 2883 "configuration mismatch for shared %s context.", 2884 sh->ibdev_name); 2885 goto error; 2886 } 2887 if (sh->config.reclaim_mode ^ config->reclaim_mode) { 2888 DRV_LOG(ERR, "\"reclaim_mode\" " 2889 "configuration mismatch for shared %s context.", 2890 sh->ibdev_name); 2891 goto error; 2892 } 2893 if (sh->config.allow_duplicate_pattern ^ 2894 config->allow_duplicate_pattern) { 2895 DRV_LOG(ERR, "\"allow_duplicate_pattern\" " 2896 "configuration mismatch for shared %s context.", 2897 sh->ibdev_name); 2898 goto error; 2899 } 2900 if (sh->config.fdb_def_rule ^ config->fdb_def_rule) { 2901 DRV_LOG(ERR, "\"fdb_def_rule_en\" configuration mismatch for shared %s context.", 2902 sh->ibdev_name); 2903 goto error; 2904 } 2905 if (sh->config.l3_vxlan_en ^ config->l3_vxlan_en) { 2906 DRV_LOG(ERR, "\"l3_vxlan_en\" " 2907 "configuration mismatch for shared %s context.", 2908 sh->ibdev_name); 2909 goto error; 2910 } 2911 if (sh->config.decap_en ^ config->decap_en) { 2912 DRV_LOG(ERR, "\"decap_en\" " 2913 "configuration mismatch for shared %s context.", 2914 sh->ibdev_name); 2915 goto error; 2916 } 2917 if (sh->config.lacp_by_user ^ config->lacp_by_user) { 2918 DRV_LOG(ERR, "\"lacp_by_user\" " 2919 "configuration mismatch for shared %s context.", 2920 sh->ibdev_name); 2921 goto error; 2922 } 2923 if (sh->config.tx_pp ^ config->tx_pp) { 2924 DRV_LOG(ERR, "\"tx_pp\" " 2925 "configuration mismatch for shared %s context.", 2926 sh->ibdev_name); 2927 goto error; 2928 } 2929 if (sh->config.tx_skew ^ config->tx_skew) { 2930 DRV_LOG(ERR, "\"tx_skew\" " 2931 "configuration mismatch for shared %s context.", 2932 sh->ibdev_name); 2933 goto error; 2934 } 2935 mlx5_free(config); 2936 return 0; 2937 error: 2938 mlx5_free(config); 2939 rte_errno = EINVAL; 2940 return -rte_errno; 2941 } 2942 2943 /** 2944 * Configures the minimal amount of data to inline into WQE 2945 * while sending packets. 2946 * 2947 * - the txq_inline_min has the maximal priority, if this 2948 * key is specified in devargs 2949 * - if DevX is enabled the inline mode is queried from the 2950 * device (HCA attributes and NIC vport context if needed). 2951 * - otherwise L2 mode (18 bytes) is assumed for ConnectX-4/4 Lx 2952 * and none (0 bytes) for other NICs 2953 * 2954 * @param priv 2955 * Pointer to the private device data structure. 2956 */ 2957 void 2958 mlx5_set_min_inline(struct mlx5_priv *priv) 2959 { 2960 struct mlx5_hca_attr *hca_attr = &priv->sh->cdev->config.hca_attr; 2961 struct mlx5_port_config *config = &priv->config; 2962 2963 if (config->txq_inline_min != MLX5_ARG_UNSET) { 2964 /* Application defines size of inlined data explicitly. */ 2965 if (priv->pci_dev != NULL) { 2966 switch (priv->pci_dev->id.device_id) { 2967 case PCI_DEVICE_ID_MELLANOX_CONNECTX4: 2968 case PCI_DEVICE_ID_MELLANOX_CONNECTX4VF: 2969 if (config->txq_inline_min < 2970 (int)MLX5_INLINE_HSIZE_L2) { 2971 DRV_LOG(DEBUG, 2972 "txq_inline_mix aligned to minimal ConnectX-4 required value %d", 2973 (int)MLX5_INLINE_HSIZE_L2); 2974 config->txq_inline_min = 2975 MLX5_INLINE_HSIZE_L2; 2976 } 2977 break; 2978 } 2979 } 2980 goto exit; 2981 } 2982 if (hca_attr->eth_net_offloads) { 2983 /* We have DevX enabled, inline mode queried successfully. */ 2984 switch (hca_attr->wqe_inline_mode) { 2985 case MLX5_CAP_INLINE_MODE_L2: 2986 /* outer L2 header must be inlined. */ 2987 config->txq_inline_min = MLX5_INLINE_HSIZE_L2; 2988 goto exit; 2989 case MLX5_CAP_INLINE_MODE_NOT_REQUIRED: 2990 /* No inline data are required by NIC. */ 2991 config->txq_inline_min = MLX5_INLINE_HSIZE_NONE; 2992 config->hw_vlan_insert = 2993 hca_attr->wqe_vlan_insert; 2994 DRV_LOG(DEBUG, "Tx VLAN insertion is supported"); 2995 goto exit; 2996 case MLX5_CAP_INLINE_MODE_VPORT_CONTEXT: 2997 /* inline mode is defined by NIC vport context. */ 2998 if (!hca_attr->eth_virt) 2999 break; 3000 switch (hca_attr->vport_inline_mode) { 3001 case MLX5_INLINE_MODE_NONE: 3002 config->txq_inline_min = 3003 MLX5_INLINE_HSIZE_NONE; 3004 goto exit; 3005 case MLX5_INLINE_MODE_L2: 3006 config->txq_inline_min = 3007 MLX5_INLINE_HSIZE_L2; 3008 goto exit; 3009 case MLX5_INLINE_MODE_IP: 3010 config->txq_inline_min = 3011 MLX5_INLINE_HSIZE_L3; 3012 goto exit; 3013 case MLX5_INLINE_MODE_TCP_UDP: 3014 config->txq_inline_min = 3015 MLX5_INLINE_HSIZE_L4; 3016 goto exit; 3017 case MLX5_INLINE_MODE_INNER_L2: 3018 config->txq_inline_min = 3019 MLX5_INLINE_HSIZE_INNER_L2; 3020 goto exit; 3021 case MLX5_INLINE_MODE_INNER_IP: 3022 config->txq_inline_min = 3023 MLX5_INLINE_HSIZE_INNER_L3; 3024 goto exit; 3025 case MLX5_INLINE_MODE_INNER_TCP_UDP: 3026 config->txq_inline_min = 3027 MLX5_INLINE_HSIZE_INNER_L4; 3028 goto exit; 3029 } 3030 } 3031 } 3032 if (priv->pci_dev == NULL) { 3033 config->txq_inline_min = MLX5_INLINE_HSIZE_NONE; 3034 goto exit; 3035 } 3036 /* 3037 * We get here if we are unable to deduce 3038 * inline data size with DevX. Try PCI ID 3039 * to determine old NICs. 3040 */ 3041 switch (priv->pci_dev->id.device_id) { 3042 case PCI_DEVICE_ID_MELLANOX_CONNECTX4: 3043 case PCI_DEVICE_ID_MELLANOX_CONNECTX4VF: 3044 case PCI_DEVICE_ID_MELLANOX_CONNECTX4LX: 3045 case PCI_DEVICE_ID_MELLANOX_CONNECTX4LXVF: 3046 config->txq_inline_min = MLX5_INLINE_HSIZE_L2; 3047 config->hw_vlan_insert = 0; 3048 break; 3049 case PCI_DEVICE_ID_MELLANOX_CONNECTX5: 3050 case PCI_DEVICE_ID_MELLANOX_CONNECTX5VF: 3051 case PCI_DEVICE_ID_MELLANOX_CONNECTX5EX: 3052 case PCI_DEVICE_ID_MELLANOX_CONNECTX5EXVF: 3053 /* 3054 * These NICs support VLAN insertion from WQE and 3055 * report the wqe_vlan_insert flag. But there is the bug 3056 * and PFC control may be broken, so disable feature. 3057 */ 3058 config->hw_vlan_insert = 0; 3059 config->txq_inline_min = MLX5_INLINE_HSIZE_NONE; 3060 break; 3061 default: 3062 config->txq_inline_min = MLX5_INLINE_HSIZE_NONE; 3063 break; 3064 } 3065 exit: 3066 DRV_LOG(DEBUG, "min tx inline configured: %d", config->txq_inline_min); 3067 } 3068 3069 /** 3070 * Configures the metadata mask fields in the shared context. 3071 * 3072 * @param [in] dev 3073 * Pointer to Ethernet device. 3074 */ 3075 void 3076 mlx5_set_metadata_mask(struct rte_eth_dev *dev) 3077 { 3078 struct mlx5_priv *priv = dev->data->dev_private; 3079 struct mlx5_dev_ctx_shared *sh = priv->sh; 3080 uint32_t meta, mark, reg_c0; 3081 3082 reg_c0 = ~priv->vport_meta_mask; 3083 switch (sh->config.dv_xmeta_en) { 3084 case MLX5_XMETA_MODE_LEGACY: 3085 meta = UINT32_MAX; 3086 mark = MLX5_FLOW_MARK_MASK; 3087 break; 3088 case MLX5_XMETA_MODE_META16: 3089 meta = reg_c0 >> rte_bsf32(reg_c0); 3090 mark = MLX5_FLOW_MARK_MASK; 3091 break; 3092 case MLX5_XMETA_MODE_META32: 3093 meta = UINT32_MAX; 3094 mark = (reg_c0 >> rte_bsf32(reg_c0)) & MLX5_FLOW_MARK_MASK; 3095 break; 3096 case MLX5_XMETA_MODE_META32_HWS: 3097 meta = UINT32_MAX; 3098 mark = MLX5_FLOW_MARK_MASK; 3099 break; 3100 default: 3101 meta = 0; 3102 mark = 0; 3103 MLX5_ASSERT(false); 3104 break; 3105 } 3106 if (sh->dv_mark_mask && sh->dv_mark_mask != mark) 3107 DRV_LOG(WARNING, "metadata MARK mask mismatch %08X:%08X", 3108 sh->dv_mark_mask, mark); 3109 else 3110 sh->dv_mark_mask = mark; 3111 if (sh->dv_meta_mask && sh->dv_meta_mask != meta) 3112 DRV_LOG(WARNING, "metadata META mask mismatch %08X:%08X", 3113 sh->dv_meta_mask, meta); 3114 else 3115 sh->dv_meta_mask = meta; 3116 if (sh->dv_regc0_mask && sh->dv_regc0_mask != reg_c0) 3117 DRV_LOG(WARNING, "metadata reg_c0 mask mismatch %08X:%08X", 3118 sh->dv_meta_mask, reg_c0); 3119 else 3120 sh->dv_regc0_mask = reg_c0; 3121 DRV_LOG(DEBUG, "metadata mode %u", sh->config.dv_xmeta_en); 3122 DRV_LOG(DEBUG, "metadata MARK mask %08X", sh->dv_mark_mask); 3123 DRV_LOG(DEBUG, "metadata META mask %08X", sh->dv_meta_mask); 3124 DRV_LOG(DEBUG, "metadata reg_c0 mask %08X", sh->dv_regc0_mask); 3125 } 3126 3127 int 3128 rte_pmd_mlx5_get_dyn_flag_names(char *names[], unsigned int n) 3129 { 3130 static const char *const dynf_names[] = { 3131 RTE_PMD_MLX5_FINE_GRANULARITY_INLINE, 3132 RTE_MBUF_DYNFLAG_METADATA_NAME, 3133 RTE_MBUF_DYNFLAG_TX_TIMESTAMP_NAME 3134 }; 3135 unsigned int i; 3136 3137 if (n < RTE_DIM(dynf_names)) 3138 return -ENOMEM; 3139 for (i = 0; i < RTE_DIM(dynf_names); i++) { 3140 if (names[i] == NULL) 3141 return -EINVAL; 3142 strcpy(names[i], dynf_names[i]); 3143 } 3144 return RTE_DIM(dynf_names); 3145 } 3146 3147 /** 3148 * Look for the ethernet device belonging to mlx5 driver. 3149 * 3150 * @param[in] port_id 3151 * port_id to start looking for device. 3152 * @param[in] odev 3153 * Pointer to the hint device. When device is being probed 3154 * the its siblings (master and preceding representors might 3155 * not have assigned driver yet (because the mlx5_os_pci_probe() 3156 * is not completed yet, for this case match on hint 3157 * device may be used to detect sibling device. 3158 * 3159 * @return 3160 * port_id of found device, RTE_MAX_ETHPORT if not found. 3161 */ 3162 uint16_t 3163 mlx5_eth_find_next(uint16_t port_id, struct rte_device *odev) 3164 { 3165 while (port_id < RTE_MAX_ETHPORTS) { 3166 struct rte_eth_dev *dev = &rte_eth_devices[port_id]; 3167 3168 if (dev->state != RTE_ETH_DEV_UNUSED && 3169 dev->device && 3170 (dev->device == odev || 3171 (dev->device->driver && 3172 dev->device->driver->name && 3173 ((strcmp(dev->device->driver->name, 3174 MLX5_PCI_DRIVER_NAME) == 0) || 3175 (strcmp(dev->device->driver->name, 3176 MLX5_AUXILIARY_DRIVER_NAME) == 0))))) 3177 break; 3178 port_id++; 3179 } 3180 if (port_id >= RTE_MAX_ETHPORTS) 3181 return RTE_MAX_ETHPORTS; 3182 return port_id; 3183 } 3184 3185 /** 3186 * Callback to remove a device. 3187 * 3188 * This function removes all Ethernet devices belong to a given device. 3189 * 3190 * @param[in] cdev 3191 * Pointer to the generic device. 3192 * 3193 * @return 3194 * 0 on success, the function cannot fail. 3195 */ 3196 int 3197 mlx5_net_remove(struct mlx5_common_device *cdev) 3198 { 3199 uint16_t port_id; 3200 int ret = 0; 3201 3202 RTE_ETH_FOREACH_DEV_OF(port_id, cdev->dev) { 3203 /* 3204 * mlx5_dev_close() is not registered to secondary process, 3205 * call the close function explicitly for secondary process. 3206 */ 3207 if (rte_eal_process_type() == RTE_PROC_SECONDARY) 3208 ret |= mlx5_dev_close(&rte_eth_devices[port_id]); 3209 else 3210 ret |= rte_eth_dev_close(port_id); 3211 } 3212 return ret == 0 ? 0 : -EIO; 3213 } 3214 3215 static const struct rte_pci_id mlx5_pci_id_map[] = { 3216 { 3217 RTE_PCI_DEVICE(PCI_VENDOR_ID_MELLANOX, 3218 PCI_DEVICE_ID_MELLANOX_CONNECTX4) 3219 }, 3220 { 3221 RTE_PCI_DEVICE(PCI_VENDOR_ID_MELLANOX, 3222 PCI_DEVICE_ID_MELLANOX_CONNECTX4VF) 3223 }, 3224 { 3225 RTE_PCI_DEVICE(PCI_VENDOR_ID_MELLANOX, 3226 PCI_DEVICE_ID_MELLANOX_CONNECTX4LX) 3227 }, 3228 { 3229 RTE_PCI_DEVICE(PCI_VENDOR_ID_MELLANOX, 3230 PCI_DEVICE_ID_MELLANOX_CONNECTX4LXVF) 3231 }, 3232 { 3233 RTE_PCI_DEVICE(PCI_VENDOR_ID_MELLANOX, 3234 PCI_DEVICE_ID_MELLANOX_CONNECTX5) 3235 }, 3236 { 3237 RTE_PCI_DEVICE(PCI_VENDOR_ID_MELLANOX, 3238 PCI_DEVICE_ID_MELLANOX_CONNECTX5VF) 3239 }, 3240 { 3241 RTE_PCI_DEVICE(PCI_VENDOR_ID_MELLANOX, 3242 PCI_DEVICE_ID_MELLANOX_CONNECTX5EX) 3243 }, 3244 { 3245 RTE_PCI_DEVICE(PCI_VENDOR_ID_MELLANOX, 3246 PCI_DEVICE_ID_MELLANOX_CONNECTX5EXVF) 3247 }, 3248 { 3249 RTE_PCI_DEVICE(PCI_VENDOR_ID_MELLANOX, 3250 PCI_DEVICE_ID_MELLANOX_BLUEFIELD) 3251 }, 3252 { 3253 RTE_PCI_DEVICE(PCI_VENDOR_ID_MELLANOX, 3254 PCI_DEVICE_ID_MELLANOX_BLUEFIELDVF) 3255 }, 3256 { 3257 RTE_PCI_DEVICE(PCI_VENDOR_ID_MELLANOX, 3258 PCI_DEVICE_ID_MELLANOX_CONNECTX6) 3259 }, 3260 { 3261 RTE_PCI_DEVICE(PCI_VENDOR_ID_MELLANOX, 3262 PCI_DEVICE_ID_MELLANOX_CONNECTX6VF) 3263 }, 3264 { 3265 RTE_PCI_DEVICE(PCI_VENDOR_ID_MELLANOX, 3266 PCI_DEVICE_ID_MELLANOX_CONNECTX6DX) 3267 }, 3268 { 3269 RTE_PCI_DEVICE(PCI_VENDOR_ID_MELLANOX, 3270 PCI_DEVICE_ID_MELLANOX_CONNECTXVF) 3271 }, 3272 { 3273 RTE_PCI_DEVICE(PCI_VENDOR_ID_MELLANOX, 3274 PCI_DEVICE_ID_MELLANOX_BLUEFIELD2) 3275 }, 3276 { 3277 RTE_PCI_DEVICE(PCI_VENDOR_ID_MELLANOX, 3278 PCI_DEVICE_ID_MELLANOX_CONNECTX6LX) 3279 }, 3280 { 3281 RTE_PCI_DEVICE(PCI_VENDOR_ID_MELLANOX, 3282 PCI_DEVICE_ID_MELLANOX_CONNECTX7) 3283 }, 3284 { 3285 RTE_PCI_DEVICE(PCI_VENDOR_ID_MELLANOX, 3286 PCI_DEVICE_ID_MELLANOX_BLUEFIELD3) 3287 }, 3288 { 3289 .vendor_id = 0 3290 } 3291 }; 3292 3293 static struct mlx5_class_driver mlx5_net_driver = { 3294 .drv_class = MLX5_CLASS_ETH, 3295 .name = RTE_STR(MLX5_ETH_DRIVER_NAME), 3296 .id_table = mlx5_pci_id_map, 3297 .probe = mlx5_os_net_probe, 3298 .remove = mlx5_net_remove, 3299 .probe_again = 1, 3300 .intr_lsc = 1, 3301 .intr_rmv = 1, 3302 }; 3303 3304 /* Initialize driver log type. */ 3305 RTE_LOG_REGISTER_DEFAULT(mlx5_logtype, NOTICE) 3306 3307 /** 3308 * Driver initialization routine. 3309 */ 3310 RTE_INIT(rte_mlx5_pmd_init) 3311 { 3312 pthread_mutex_init(&mlx5_dev_ctx_list_mutex, NULL); 3313 mlx5_common_init(); 3314 /* Build the static tables for Verbs conversion. */ 3315 mlx5_set_ptype_table(); 3316 mlx5_set_cksum_table(); 3317 mlx5_set_swp_types_table(); 3318 if (mlx5_glue) 3319 mlx5_class_driver_register(&mlx5_net_driver); 3320 } 3321 3322 RTE_PMD_EXPORT_NAME(MLX5_ETH_DRIVER_NAME, __COUNTER__); 3323 RTE_PMD_REGISTER_PCI_TABLE(MLX5_ETH_DRIVER_NAME, mlx5_pci_id_map); 3324 RTE_PMD_REGISTER_KMOD_DEP(MLX5_ETH_DRIVER_NAME, "* ib_uverbs & mlx5_core & mlx5_ib"); 3325