1 /* SPDX-License-Identifier: BSD-3-Clause 2 * Copyright 2015 6WIND S.A. 3 * Copyright 2015 Mellanox Technologies, Ltd 4 */ 5 6 #include <stddef.h> 7 #include <unistd.h> 8 #include <string.h> 9 #include <stdint.h> 10 #include <stdlib.h> 11 #include <errno.h> 12 #include <fcntl.h> 13 14 #include <rte_malloc.h> 15 #include <ethdev_driver.h> 16 #include <rte_pci.h> 17 #include <bus_pci_driver.h> 18 #include <rte_common.h> 19 #include <rte_kvargs.h> 20 #include <rte_rwlock.h> 21 #include <rte_spinlock.h> 22 #include <rte_string_fns.h> 23 #include <rte_eal_paging.h> 24 #include <rte_alarm.h> 25 #include <rte_cycles.h> 26 #include <rte_interrupts.h> 27 28 #include <mlx5_glue.h> 29 #include <mlx5_devx_cmds.h> 30 #include <mlx5_common.h> 31 #include <mlx5_common_os.h> 32 #include <mlx5_common_mp.h> 33 #include <mlx5_malloc.h> 34 35 #include "mlx5_defs.h" 36 #include "mlx5.h" 37 #include "mlx5_utils.h" 38 #include "mlx5_rxtx.h" 39 #include "mlx5_rx.h" 40 #include "mlx5_tx.h" 41 #include "mlx5_autoconf.h" 42 #include "mlx5_flow.h" 43 #include "mlx5_flow_os.h" 44 #include "rte_pmd_mlx5.h" 45 46 #define MLX5_ETH_DRIVER_NAME mlx5_eth 47 48 /* Device parameter to enable RX completion queue compression. */ 49 #define MLX5_RXQ_CQE_COMP_EN "rxq_cqe_comp_en" 50 51 /* Device parameter to enable padding Rx packet to cacheline size. */ 52 #define MLX5_RXQ_PKT_PAD_EN "rxq_pkt_pad_en" 53 54 /* Device parameter to enable Multi-Packet Rx queue. */ 55 #define MLX5_RX_MPRQ_EN "mprq_en" 56 57 /* Device parameter to configure log 2 of the number of strides for MPRQ. */ 58 #define MLX5_RX_MPRQ_LOG_STRIDE_NUM "mprq_log_stride_num" 59 60 /* Device parameter to configure log 2 of the stride size for MPRQ. */ 61 #define MLX5_RX_MPRQ_LOG_STRIDE_SIZE "mprq_log_stride_size" 62 63 /* Device parameter to limit the size of memcpy'd packet for MPRQ. */ 64 #define MLX5_RX_MPRQ_MAX_MEMCPY_LEN "mprq_max_memcpy_len" 65 66 /* Device parameter to set the minimum number of Rx queues to enable MPRQ. */ 67 #define MLX5_RXQS_MIN_MPRQ "rxqs_min_mprq" 68 69 /* Device parameter to configure inline send. Deprecated, ignored.*/ 70 #define MLX5_TXQ_INLINE "txq_inline" 71 72 /* Device parameter to limit packet size to inline with ordinary SEND. */ 73 #define MLX5_TXQ_INLINE_MAX "txq_inline_max" 74 75 /* Device parameter to configure minimal data size to inline. */ 76 #define MLX5_TXQ_INLINE_MIN "txq_inline_min" 77 78 /* Device parameter to limit packet size to inline with Enhanced MPW. */ 79 #define MLX5_TXQ_INLINE_MPW "txq_inline_mpw" 80 81 /* 82 * Device parameter to configure the number of TX queues threshold for 83 * enabling inline send. 84 */ 85 #define MLX5_TXQS_MIN_INLINE "txqs_min_inline" 86 87 /* 88 * Device parameter to configure the number of TX queues threshold for 89 * enabling vectorized Tx, deprecated, ignored (no vectorized Tx routines). 90 */ 91 #define MLX5_TXQS_MAX_VEC "txqs_max_vec" 92 93 /* Device parameter to enable multi-packet send WQEs. */ 94 #define MLX5_TXQ_MPW_EN "txq_mpw_en" 95 96 /* 97 * Device parameter to include 2 dsegs in the title WQEBB. 98 * Deprecated, ignored. 99 */ 100 #define MLX5_TXQ_MPW_HDR_DSEG_EN "txq_mpw_hdr_dseg_en" 101 102 /* 103 * Device parameter to limit the size of inlining packet. 104 * Deprecated, ignored. 105 */ 106 #define MLX5_TXQ_MAX_INLINE_LEN "txq_max_inline_len" 107 108 /* 109 * Device parameter to enable Tx scheduling on timestamps 110 * and specify the packet pacing granularity in nanoseconds. 111 */ 112 #define MLX5_TX_PP "tx_pp" 113 114 /* 115 * Device parameter to specify skew in nanoseconds on Tx datapath, 116 * it represents the time between SQ start WQE processing and 117 * appearing actual packet data on the wire. 118 */ 119 #define MLX5_TX_SKEW "tx_skew" 120 121 /* 122 * Device parameter to enable hardware Tx vector. 123 * Deprecated, ignored (no vectorized Tx routines anymore). 124 */ 125 #define MLX5_TX_VEC_EN "tx_vec_en" 126 127 /* Device parameter to enable hardware Rx vector. */ 128 #define MLX5_RX_VEC_EN "rx_vec_en" 129 130 /* Allow L3 VXLAN flow creation. */ 131 #define MLX5_L3_VXLAN_EN "l3_vxlan_en" 132 133 /* Activate DV E-Switch flow steering. */ 134 #define MLX5_DV_ESW_EN "dv_esw_en" 135 136 /* Activate DV flow steering. */ 137 #define MLX5_DV_FLOW_EN "dv_flow_en" 138 139 /* Enable extensive flow metadata support. */ 140 #define MLX5_DV_XMETA_EN "dv_xmeta_en" 141 142 /* Device parameter to let the user manage the lacp traffic of bonding device */ 143 #define MLX5_LACP_BY_USER "lacp_by_user" 144 145 /* Activate Netlink support in VF mode. */ 146 #define MLX5_VF_NL_EN "vf_nl_en" 147 148 /* Select port representors to instantiate. */ 149 #define MLX5_REPRESENTOR "representor" 150 151 /* Device parameter to configure the maximum number of dump files per queue. */ 152 #define MLX5_MAX_DUMP_FILES_NUM "max_dump_files_num" 153 154 /* Configure timeout of LRO session (in microseconds). */ 155 #define MLX5_LRO_TIMEOUT_USEC "lro_timeout_usec" 156 157 /* 158 * Device parameter to configure the total data buffer size for a single 159 * hairpin queue (logarithm value). 160 */ 161 #define MLX5_HP_BUF_SIZE "hp_buf_log_sz" 162 163 /* Flow memory reclaim mode. */ 164 #define MLX5_RECLAIM_MEM "reclaim_mem_mode" 165 166 /* Decap will be used or not. */ 167 #define MLX5_DECAP_EN "decap_en" 168 169 /* Device parameter to configure allow or prevent duplicate rules pattern. */ 170 #define MLX5_ALLOW_DUPLICATE_PATTERN "allow_duplicate_pattern" 171 172 /* Device parameter to configure the delay drop when creating Rxqs. */ 173 #define MLX5_DELAY_DROP "delay_drop" 174 175 /* Device parameter to create the fdb default rule in PMD */ 176 #define MLX5_FDB_DEFAULT_RULE_EN "fdb_def_rule_en" 177 178 /* HW steering counter configuration. */ 179 #define MLX5_HWS_CNT_SERVICE_CORE "service_core" 180 181 /* HW steering counter's query interval. */ 182 #define MLX5_HWS_CNT_CYCLE_TIME "svc_cycle_time" 183 184 /* Device parameter to control representor matching in ingress/egress flows with HWS. */ 185 #define MLX5_REPR_MATCHING_EN "repr_matching_en" 186 187 /* Shared memory between primary and secondary processes. */ 188 struct mlx5_shared_data *mlx5_shared_data; 189 190 /** Driver-specific log messages type. */ 191 int mlx5_logtype; 192 193 static LIST_HEAD(mlx5_dev_ctx_list, mlx5_dev_ctx_shared) dev_ctx_list = LIST_HEAD_INITIALIZER(); 194 static LIST_HEAD(mlx5_phdev_list, mlx5_physical_device) phdev_list = LIST_HEAD_INITIALIZER(); 195 static pthread_mutex_t mlx5_dev_ctx_list_mutex; 196 197 static const struct mlx5_indexed_pool_config mlx5_ipool_cfg[] = { 198 #if defined(HAVE_IBV_FLOW_DV_SUPPORT) || !defined(HAVE_INFINIBAND_VERBS_H) 199 [MLX5_IPOOL_DECAP_ENCAP] = { 200 .size = sizeof(struct mlx5_flow_dv_encap_decap_resource), 201 .trunk_size = 64, 202 .grow_trunk = 3, 203 .grow_shift = 2, 204 .need_lock = 1, 205 .release_mem_en = 1, 206 .malloc = mlx5_malloc, 207 .free = mlx5_free, 208 .type = "mlx5_encap_decap_ipool", 209 }, 210 [MLX5_IPOOL_PUSH_VLAN] = { 211 .size = sizeof(struct mlx5_flow_dv_push_vlan_action_resource), 212 .trunk_size = 64, 213 .grow_trunk = 3, 214 .grow_shift = 2, 215 .need_lock = 1, 216 .release_mem_en = 1, 217 .malloc = mlx5_malloc, 218 .free = mlx5_free, 219 .type = "mlx5_push_vlan_ipool", 220 }, 221 [MLX5_IPOOL_TAG] = { 222 .size = sizeof(struct mlx5_flow_dv_tag_resource), 223 .trunk_size = 64, 224 .grow_trunk = 3, 225 .grow_shift = 2, 226 .need_lock = 1, 227 .release_mem_en = 0, 228 .per_core_cache = (1 << 16), 229 .malloc = mlx5_malloc, 230 .free = mlx5_free, 231 .type = "mlx5_tag_ipool", 232 }, 233 [MLX5_IPOOL_PORT_ID] = { 234 .size = sizeof(struct mlx5_flow_dv_port_id_action_resource), 235 .trunk_size = 64, 236 .grow_trunk = 3, 237 .grow_shift = 2, 238 .need_lock = 1, 239 .release_mem_en = 1, 240 .malloc = mlx5_malloc, 241 .free = mlx5_free, 242 .type = "mlx5_port_id_ipool", 243 }, 244 [MLX5_IPOOL_JUMP] = { 245 /* 246 * MLX5_IPOOL_JUMP ipool entry size depends on selected flow engine. 247 * When HW steering is enabled mlx5_flow_group struct is used. 248 * Otherwise mlx5_flow_tbl_data_entry struct is used. 249 */ 250 .size = 0, 251 .trunk_size = 64, 252 .grow_trunk = 3, 253 .grow_shift = 2, 254 .need_lock = 1, 255 .release_mem_en = 1, 256 .malloc = mlx5_malloc, 257 .free = mlx5_free, 258 .type = "mlx5_jump_ipool", 259 }, 260 [MLX5_IPOOL_SAMPLE] = { 261 .size = sizeof(struct mlx5_flow_dv_sample_resource), 262 .trunk_size = 64, 263 .grow_trunk = 3, 264 .grow_shift = 2, 265 .need_lock = 1, 266 .release_mem_en = 1, 267 .malloc = mlx5_malloc, 268 .free = mlx5_free, 269 .type = "mlx5_sample_ipool", 270 }, 271 [MLX5_IPOOL_DEST_ARRAY] = { 272 .size = sizeof(struct mlx5_flow_dv_dest_array_resource), 273 .trunk_size = 64, 274 .grow_trunk = 3, 275 .grow_shift = 2, 276 .need_lock = 1, 277 .release_mem_en = 1, 278 .malloc = mlx5_malloc, 279 .free = mlx5_free, 280 .type = "mlx5_dest_array_ipool", 281 }, 282 [MLX5_IPOOL_TUNNEL_ID] = { 283 .size = sizeof(struct mlx5_flow_tunnel), 284 .trunk_size = MLX5_MAX_TUNNELS, 285 .need_lock = 1, 286 .release_mem_en = 1, 287 .type = "mlx5_tunnel_offload", 288 }, 289 [MLX5_IPOOL_TNL_TBL_ID] = { 290 .size = 0, 291 .need_lock = 1, 292 .type = "mlx5_flow_tnl_tbl_ipool", 293 }, 294 #endif 295 [MLX5_IPOOL_MTR] = { 296 /** 297 * The ipool index should grow continually from small to big, 298 * for meter idx, so not set grow_trunk to avoid meter index 299 * not jump continually. 300 */ 301 .size = sizeof(struct mlx5_legacy_flow_meter), 302 .trunk_size = 64, 303 .need_lock = 1, 304 .release_mem_en = 1, 305 .malloc = mlx5_malloc, 306 .free = mlx5_free, 307 .type = "mlx5_meter_ipool", 308 }, 309 [MLX5_IPOOL_MCP] = { 310 .size = sizeof(struct mlx5_flow_mreg_copy_resource), 311 .trunk_size = 64, 312 .grow_trunk = 3, 313 .grow_shift = 2, 314 .need_lock = 1, 315 .release_mem_en = 1, 316 .malloc = mlx5_malloc, 317 .free = mlx5_free, 318 .type = "mlx5_mcp_ipool", 319 }, 320 [MLX5_IPOOL_HRXQ] = { 321 .size = (sizeof(struct mlx5_hrxq) + MLX5_RSS_HASH_KEY_LEN), 322 .trunk_size = 64, 323 .grow_trunk = 3, 324 .grow_shift = 2, 325 .need_lock = 1, 326 .release_mem_en = 1, 327 .malloc = mlx5_malloc, 328 .free = mlx5_free, 329 .type = "mlx5_hrxq_ipool", 330 }, 331 [MLX5_IPOOL_MLX5_FLOW] = { 332 /* 333 * MLX5_IPOOL_MLX5_FLOW size varies for DV and VERBS flows. 334 * It set in run time according to PCI function configuration. 335 */ 336 .size = 0, 337 .trunk_size = 64, 338 .grow_trunk = 3, 339 .grow_shift = 2, 340 .need_lock = 1, 341 .release_mem_en = 0, 342 .per_core_cache = 1 << 19, 343 .malloc = mlx5_malloc, 344 .free = mlx5_free, 345 .type = "mlx5_flow_handle_ipool", 346 }, 347 [MLX5_IPOOL_RTE_FLOW] = { 348 .size = sizeof(struct rte_flow), 349 .trunk_size = 4096, 350 .need_lock = 1, 351 .release_mem_en = 1, 352 .malloc = mlx5_malloc, 353 .free = mlx5_free, 354 .type = "rte_flow_ipool", 355 }, 356 [MLX5_IPOOL_RSS_EXPANTION_FLOW_ID] = { 357 .size = 0, 358 .need_lock = 1, 359 .type = "mlx5_flow_rss_id_ipool", 360 }, 361 [MLX5_IPOOL_RSS_SHARED_ACTIONS] = { 362 .size = sizeof(struct mlx5_shared_action_rss), 363 .trunk_size = 64, 364 .grow_trunk = 3, 365 .grow_shift = 2, 366 .need_lock = 1, 367 .release_mem_en = 1, 368 .malloc = mlx5_malloc, 369 .free = mlx5_free, 370 .type = "mlx5_shared_action_rss", 371 }, 372 [MLX5_IPOOL_MTR_POLICY] = { 373 /** 374 * The ipool index should grow continually from small to big, 375 * for policy idx, so not set grow_trunk to avoid policy index 376 * not jump continually. 377 */ 378 .size = sizeof(struct mlx5_flow_meter_sub_policy), 379 .trunk_size = 64, 380 .need_lock = 1, 381 .release_mem_en = 1, 382 .malloc = mlx5_malloc, 383 .free = mlx5_free, 384 .type = "mlx5_meter_policy_ipool", 385 }, 386 }; 387 388 #define MLX5_FLOW_MIN_ID_POOL_SIZE 512 389 #define MLX5_ID_GENERATION_ARRAY_FACTOR 16 390 391 #define MLX5_FLOW_TABLE_HLIST_ARRAY_SIZE 1024 392 393 #define MLX5_RXQ_ENH_CQE_COMP_MASK 0x80 394 395 /** 396 * Decide whether representor ID is a HPF(host PF) port on BF2. 397 * 398 * @param dev 399 * Pointer to Ethernet device structure. 400 * 401 * @return 402 * Non-zero if HPF, otherwise 0. 403 */ 404 bool 405 mlx5_is_hpf(struct rte_eth_dev *dev) 406 { 407 struct mlx5_priv *priv = dev->data->dev_private; 408 uint16_t repr = MLX5_REPRESENTOR_REPR(priv->representor_id); 409 int type = MLX5_REPRESENTOR_TYPE(priv->representor_id); 410 411 return priv->representor != 0 && type == RTE_ETH_REPRESENTOR_VF && 412 MLX5_REPRESENTOR_REPR(-1) == repr; 413 } 414 415 /** 416 * Decide whether representor ID is a SF port representor. 417 * 418 * @param dev 419 * Pointer to Ethernet device structure. 420 * 421 * @return 422 * Non-zero if HPF, otherwise 0. 423 */ 424 bool 425 mlx5_is_sf_repr(struct rte_eth_dev *dev) 426 { 427 struct mlx5_priv *priv = dev->data->dev_private; 428 int type = MLX5_REPRESENTOR_TYPE(priv->representor_id); 429 430 return priv->representor != 0 && type == RTE_ETH_REPRESENTOR_SF; 431 } 432 433 /** 434 * Initialize the ASO aging management structure. 435 * 436 * @param[in] sh 437 * Pointer to mlx5_dev_ctx_shared object to free 438 * 439 * @return 440 * 0 on success, a negative errno value otherwise and rte_errno is set. 441 */ 442 int 443 mlx5_flow_aso_age_mng_init(struct mlx5_dev_ctx_shared *sh) 444 { 445 int err; 446 447 if (sh->aso_age_mng) 448 return 0; 449 sh->aso_age_mng = mlx5_malloc(MLX5_MEM_ZERO, sizeof(*sh->aso_age_mng), 450 RTE_CACHE_LINE_SIZE, SOCKET_ID_ANY); 451 if (!sh->aso_age_mng) { 452 DRV_LOG(ERR, "aso_age_mng allocation was failed."); 453 rte_errno = ENOMEM; 454 return -ENOMEM; 455 } 456 err = mlx5_aso_queue_init(sh, ASO_OPC_MOD_FLOW_HIT, 1); 457 if (err) { 458 mlx5_free(sh->aso_age_mng); 459 return -1; 460 } 461 rte_rwlock_init(&sh->aso_age_mng->resize_rwl); 462 rte_spinlock_init(&sh->aso_age_mng->free_sl); 463 LIST_INIT(&sh->aso_age_mng->free); 464 return 0; 465 } 466 467 /** 468 * Close and release all the resources of the ASO aging management structure. 469 * 470 * @param[in] sh 471 * Pointer to mlx5_dev_ctx_shared object to free. 472 */ 473 static void 474 mlx5_flow_aso_age_mng_close(struct mlx5_dev_ctx_shared *sh) 475 { 476 int i, j; 477 478 mlx5_aso_flow_hit_queue_poll_stop(sh); 479 mlx5_aso_queue_uninit(sh, ASO_OPC_MOD_FLOW_HIT); 480 if (sh->aso_age_mng->pools) { 481 struct mlx5_aso_age_pool *pool; 482 483 for (i = 0; i < sh->aso_age_mng->next; ++i) { 484 pool = sh->aso_age_mng->pools[i]; 485 claim_zero(mlx5_devx_cmd_destroy 486 (pool->flow_hit_aso_obj)); 487 for (j = 0; j < MLX5_COUNTERS_PER_POOL; ++j) 488 if (pool->actions[j].dr_action) 489 claim_zero 490 (mlx5_flow_os_destroy_flow_action 491 (pool->actions[j].dr_action)); 492 mlx5_free(pool); 493 } 494 mlx5_free(sh->aso_age_mng->pools); 495 } 496 mlx5_free(sh->aso_age_mng); 497 } 498 499 /** 500 * Initialize the shared aging list information per port. 501 * 502 * @param[in] sh 503 * Pointer to mlx5_dev_ctx_shared object. 504 */ 505 static void 506 mlx5_flow_aging_init(struct mlx5_dev_ctx_shared *sh) 507 { 508 uint32_t i; 509 struct mlx5_age_info *age_info; 510 511 /* 512 * In HW steering, aging information structure is initialized later 513 * during configure function. 514 */ 515 if (sh->config.dv_flow_en == 2) 516 return; 517 for (i = 0; i < sh->max_port; i++) { 518 age_info = &sh->port[i].age_info; 519 age_info->flags = 0; 520 TAILQ_INIT(&age_info->aged_counters); 521 LIST_INIT(&age_info->aged_aso); 522 rte_spinlock_init(&age_info->aged_sl); 523 MLX5_AGE_SET(age_info, MLX5_AGE_TRIGGER); 524 } 525 } 526 527 /** 528 * DV flow counter mode detect and config. 529 * 530 * @param dev 531 * Pointer to rte_eth_dev structure. 532 * 533 */ 534 void 535 mlx5_flow_counter_mode_config(struct rte_eth_dev *dev __rte_unused) 536 { 537 #ifdef HAVE_IBV_FLOW_DV_SUPPORT 538 struct mlx5_priv *priv = dev->data->dev_private; 539 struct mlx5_dev_ctx_shared *sh = priv->sh; 540 struct mlx5_hca_attr *hca_attr = &sh->cdev->config.hca_attr; 541 bool fallback; 542 543 #ifndef HAVE_IBV_DEVX_ASYNC 544 fallback = true; 545 #else 546 fallback = false; 547 if (!sh->cdev->config.devx || !sh->config.dv_flow_en || 548 !hca_attr->flow_counters_dump || 549 !(hca_attr->flow_counter_bulk_alloc_bitmap & 0x4) || 550 (mlx5_flow_dv_discover_counter_offset_support(dev) == -ENOTSUP)) 551 fallback = true; 552 #endif 553 if (fallback) 554 DRV_LOG(INFO, "Use fall-back DV counter management. Flow " 555 "counter dump:%d, bulk_alloc_bitmap:0x%hhx.", 556 hca_attr->flow_counters_dump, 557 hca_attr->flow_counter_bulk_alloc_bitmap); 558 /* Initialize fallback mode only on the port initializes sh. */ 559 if (sh->refcnt == 1) 560 sh->sws_cmng.counter_fallback = fallback; 561 else if (fallback != sh->sws_cmng.counter_fallback) 562 DRV_LOG(WARNING, "Port %d in sh has different fallback mode " 563 "with others:%d.", PORT_ID(priv), fallback); 564 #endif 565 } 566 567 /** 568 * Initialize the counters management structure. 569 * 570 * @param[in] sh 571 * Pointer to mlx5_dev_ctx_shared object to free 572 * 573 * @return 574 * 0 on success, otherwise negative errno value and rte_errno is set. 575 */ 576 static int 577 mlx5_flow_counters_mng_init(struct mlx5_dev_ctx_shared *sh) 578 { 579 int i, j; 580 581 if (sh->config.dv_flow_en < 2) { 582 void *pools; 583 584 pools = mlx5_malloc(MLX5_MEM_ZERO, 585 sizeof(struct mlx5_flow_counter_pool *) * 586 MLX5_COUNTER_POOLS_MAX_NUM, 587 0, SOCKET_ID_ANY); 588 if (!pools) { 589 DRV_LOG(ERR, 590 "Counter management allocation was failed."); 591 rte_errno = ENOMEM; 592 return -rte_errno; 593 } 594 memset(&sh->sws_cmng, 0, sizeof(sh->sws_cmng)); 595 TAILQ_INIT(&sh->sws_cmng.flow_counters); 596 sh->sws_cmng.min_id = MLX5_CNT_BATCH_OFFSET; 597 sh->sws_cmng.max_id = -1; 598 sh->sws_cmng.last_pool_idx = POOL_IDX_INVALID; 599 sh->sws_cmng.pools = pools; 600 rte_spinlock_init(&sh->sws_cmng.pool_update_sl); 601 for (i = 0; i < MLX5_COUNTER_TYPE_MAX; i++) { 602 TAILQ_INIT(&sh->sws_cmng.counters[i]); 603 rte_spinlock_init(&sh->sws_cmng.csl[i]); 604 } 605 } else { 606 struct mlx5_hca_attr *attr = &sh->cdev->config.hca_attr; 607 uint32_t fw_max_nb_cnts = attr->max_flow_counter; 608 uint8_t log_dcs = log2above(fw_max_nb_cnts) - 1; 609 uint32_t max_nb_cnts = 0; 610 611 for (i = 0, j = 0; j < MLX5_HWS_CNT_DCS_NUM; ++i) { 612 int log_dcs_i = log_dcs - i; 613 614 if (log_dcs_i < 0) 615 break; 616 if ((max_nb_cnts | RTE_BIT32(log_dcs_i)) > 617 fw_max_nb_cnts) 618 continue; 619 max_nb_cnts |= RTE_BIT32(log_dcs_i); 620 j++; 621 } 622 sh->hws_max_log_bulk_sz = log_dcs; 623 sh->hws_max_nb_counters = max_nb_cnts; 624 } 625 return 0; 626 } 627 628 /** 629 * Destroy all the resources allocated for a counter memory management. 630 * 631 * @param[in] mng 632 * Pointer to the memory management structure. 633 */ 634 static void 635 mlx5_flow_destroy_counter_stat_mem_mng(struct mlx5_counter_stats_mem_mng *mng) 636 { 637 uint8_t *mem = (uint8_t *)(uintptr_t)mng->raws[0].data; 638 639 LIST_REMOVE(mng, next); 640 mlx5_os_wrapped_mkey_destroy(&mng->wm); 641 mlx5_free(mem); 642 } 643 644 /** 645 * Close and release all the resources of the counters management. 646 * 647 * @param[in] sh 648 * Pointer to mlx5_dev_ctx_shared object to free. 649 */ 650 static void 651 mlx5_flow_counters_mng_close(struct mlx5_dev_ctx_shared *sh) 652 { 653 struct mlx5_counter_stats_mem_mng *mng; 654 int i, j; 655 int retries = 1024; 656 657 rte_errno = 0; 658 while (--retries) { 659 rte_eal_alarm_cancel(mlx5_flow_query_alarm, sh); 660 if (rte_errno != EINPROGRESS) 661 break; 662 rte_pause(); 663 } 664 665 if (sh->sws_cmng.pools) { 666 struct mlx5_flow_counter_pool *pool; 667 uint16_t n_valid = sh->sws_cmng.n_valid; 668 bool fallback = sh->sws_cmng.counter_fallback; 669 670 for (i = 0; i < n_valid; ++i) { 671 pool = sh->sws_cmng.pools[i]; 672 if (!fallback && pool->min_dcs) 673 claim_zero(mlx5_devx_cmd_destroy 674 (pool->min_dcs)); 675 for (j = 0; j < MLX5_COUNTERS_PER_POOL; ++j) { 676 struct mlx5_flow_counter *cnt = 677 MLX5_POOL_GET_CNT(pool, j); 678 679 if (cnt->action) 680 claim_zero 681 (mlx5_flow_os_destroy_flow_action 682 (cnt->action)); 683 if (fallback && cnt->dcs_when_free) 684 claim_zero(mlx5_devx_cmd_destroy 685 (cnt->dcs_when_free)); 686 } 687 mlx5_free(pool); 688 } 689 mlx5_free(sh->sws_cmng.pools); 690 } 691 mng = LIST_FIRST(&sh->sws_cmng.mem_mngs); 692 while (mng) { 693 mlx5_flow_destroy_counter_stat_mem_mng(mng); 694 mng = LIST_FIRST(&sh->sws_cmng.mem_mngs); 695 } 696 memset(&sh->sws_cmng, 0, sizeof(sh->sws_cmng)); 697 } 698 699 /** 700 * Initialize the aso flow meters management structure. 701 * 702 * @param[in] sh 703 * Pointer to mlx5_dev_ctx_shared object to free 704 */ 705 int 706 mlx5_aso_flow_mtrs_mng_init(struct mlx5_dev_ctx_shared *sh) 707 { 708 if (!sh->mtrmng) { 709 sh->mtrmng = mlx5_malloc(MLX5_MEM_ZERO, 710 sizeof(*sh->mtrmng), 711 RTE_CACHE_LINE_SIZE, SOCKET_ID_ANY); 712 if (!sh->mtrmng) { 713 DRV_LOG(ERR, 714 "meter management allocation was failed."); 715 rte_errno = ENOMEM; 716 return -ENOMEM; 717 } 718 if (sh->meter_aso_en) { 719 rte_spinlock_init(&sh->mtrmng->pools_mng.mtrsl); 720 rte_rwlock_init(&sh->mtrmng->pools_mng.resize_mtrwl); 721 LIST_INIT(&sh->mtrmng->pools_mng.meters); 722 } 723 sh->mtrmng->def_policy_id = MLX5_INVALID_POLICY_ID; 724 } 725 return 0; 726 } 727 728 /** 729 * Close and release all the resources of 730 * the ASO flow meter management structure. 731 * 732 * @param[in] sh 733 * Pointer to mlx5_dev_ctx_shared object to free. 734 */ 735 static void 736 mlx5_aso_flow_mtrs_mng_close(struct mlx5_dev_ctx_shared *sh) 737 { 738 struct mlx5_aso_mtr_pool *mtr_pool; 739 struct mlx5_flow_mtr_mng *mtrmng = sh->mtrmng; 740 uint32_t idx; 741 #ifdef HAVE_MLX5_DR_CREATE_ACTION_ASO 742 struct mlx5_aso_mtr *aso_mtr; 743 int i; 744 #endif /* HAVE_MLX5_DR_CREATE_ACTION_ASO */ 745 746 if (sh->meter_aso_en) { 747 mlx5_aso_queue_uninit(sh, ASO_OPC_MOD_POLICER); 748 idx = mtrmng->pools_mng.n_valid; 749 while (idx--) { 750 mtr_pool = mtrmng->pools_mng.pools[idx]; 751 #ifdef HAVE_MLX5_DR_CREATE_ACTION_ASO 752 for (i = 0; i < MLX5_ASO_MTRS_PER_POOL; i++) { 753 aso_mtr = &mtr_pool->mtrs[i]; 754 if (aso_mtr->fm.meter_action_g) 755 claim_zero 756 (mlx5_glue->destroy_flow_action 757 (aso_mtr->fm.meter_action_g)); 758 if (aso_mtr->fm.meter_action_y) 759 claim_zero 760 (mlx5_glue->destroy_flow_action 761 (aso_mtr->fm.meter_action_y)); 762 } 763 #endif /* HAVE_MLX5_DR_CREATE_ACTION_ASO */ 764 claim_zero(mlx5_devx_cmd_destroy 765 (mtr_pool->devx_obj)); 766 mtrmng->pools_mng.n_valid--; 767 mlx5_free(mtr_pool); 768 } 769 mlx5_free(sh->mtrmng->pools_mng.pools); 770 } 771 mlx5_free(sh->mtrmng); 772 sh->mtrmng = NULL; 773 } 774 775 /* Send FLOW_AGED event if needed. */ 776 void 777 mlx5_age_event_prepare(struct mlx5_dev_ctx_shared *sh) 778 { 779 struct mlx5_age_info *age_info; 780 uint32_t i; 781 782 for (i = 0; i < sh->max_port; i++) { 783 age_info = &sh->port[i].age_info; 784 if (!MLX5_AGE_GET(age_info, MLX5_AGE_EVENT_NEW)) 785 continue; 786 MLX5_AGE_UNSET(age_info, MLX5_AGE_EVENT_NEW); 787 if (MLX5_AGE_GET(age_info, MLX5_AGE_TRIGGER)) { 788 MLX5_AGE_UNSET(age_info, MLX5_AGE_TRIGGER); 789 rte_eth_dev_callback_process 790 (&rte_eth_devices[sh->port[i].devx_ih_port_id], 791 RTE_ETH_EVENT_FLOW_AGED, NULL); 792 } 793 } 794 } 795 796 /* 797 * Initialize the ASO connection tracking structure. 798 * 799 * @param[in] sh 800 * Pointer to mlx5_dev_ctx_shared object. 801 * 802 * @return 803 * 0 on success, a negative errno value otherwise and rte_errno is set. 804 */ 805 int 806 mlx5_flow_aso_ct_mng_init(struct mlx5_dev_ctx_shared *sh) 807 { 808 int err; 809 810 if (sh->ct_mng) 811 return 0; 812 sh->ct_mng = mlx5_malloc(MLX5_MEM_ZERO, sizeof(*sh->ct_mng) + 813 sizeof(struct mlx5_aso_sq) * MLX5_ASO_CT_SQ_NUM, 814 RTE_CACHE_LINE_SIZE, SOCKET_ID_ANY); 815 if (!sh->ct_mng) { 816 DRV_LOG(ERR, "ASO CT management allocation failed."); 817 rte_errno = ENOMEM; 818 return -rte_errno; 819 } 820 err = mlx5_aso_queue_init(sh, ASO_OPC_MOD_CONNECTION_TRACKING, MLX5_ASO_CT_SQ_NUM); 821 if (err) { 822 mlx5_free(sh->ct_mng); 823 /* rte_errno should be extracted from the failure. */ 824 rte_errno = EINVAL; 825 return -rte_errno; 826 } 827 rte_spinlock_init(&sh->ct_mng->ct_sl); 828 rte_rwlock_init(&sh->ct_mng->resize_rwl); 829 LIST_INIT(&sh->ct_mng->free_cts); 830 return 0; 831 } 832 833 /* 834 * Close and release all the resources of the 835 * ASO connection tracking management structure. 836 * 837 * @param[in] sh 838 * Pointer to mlx5_dev_ctx_shared object to free. 839 */ 840 static void 841 mlx5_flow_aso_ct_mng_close(struct mlx5_dev_ctx_shared *sh) 842 { 843 struct mlx5_aso_ct_pools_mng *mng = sh->ct_mng; 844 struct mlx5_aso_ct_pool *ct_pool; 845 struct mlx5_aso_ct_action *ct; 846 uint32_t idx; 847 uint32_t val; 848 uint32_t cnt; 849 int i; 850 851 mlx5_aso_queue_uninit(sh, ASO_OPC_MOD_CONNECTION_TRACKING); 852 idx = mng->next; 853 while (idx--) { 854 cnt = 0; 855 ct_pool = mng->pools[idx]; 856 for (i = 0; i < MLX5_ASO_CT_ACTIONS_PER_POOL; i++) { 857 ct = &ct_pool->actions[i]; 858 val = rte_atomic_fetch_sub_explicit(&ct->refcnt, 1, 859 rte_memory_order_relaxed); 860 MLX5_ASSERT(val == 1); 861 if (val > 1) 862 cnt++; 863 #ifdef HAVE_MLX5_DR_ACTION_ASO_CT 864 if (ct->dr_action_orig) 865 claim_zero(mlx5_glue->destroy_flow_action 866 (ct->dr_action_orig)); 867 if (ct->dr_action_rply) 868 claim_zero(mlx5_glue->destroy_flow_action 869 (ct->dr_action_rply)); 870 #endif 871 } 872 claim_zero(mlx5_devx_cmd_destroy(ct_pool->devx_obj)); 873 if (cnt) { 874 DRV_LOG(DEBUG, "%u ASO CT objects are being used in the pool %u", 875 cnt, i); 876 } 877 mlx5_free(ct_pool); 878 /* in case of failure. */ 879 mng->next--; 880 } 881 mlx5_free(mng->pools); 882 mlx5_free(mng); 883 /* Management structure must be cleared to 0s during allocation. */ 884 sh->ct_mng = NULL; 885 } 886 887 /** 888 * Initialize the flow resources' indexed mempool. 889 * 890 * @param[in] sh 891 * Pointer to mlx5_dev_ctx_shared object. 892 */ 893 static void 894 mlx5_flow_ipool_create(struct mlx5_dev_ctx_shared *sh) 895 { 896 uint8_t i; 897 struct mlx5_indexed_pool_config cfg; 898 899 for (i = 0; i < MLX5_IPOOL_MAX; ++i) { 900 cfg = mlx5_ipool_cfg[i]; 901 switch (i) { 902 default: 903 break; 904 /* 905 * Set MLX5_IPOOL_MLX5_FLOW ipool size 906 * according to PCI function flow configuration. 907 */ 908 case MLX5_IPOOL_MLX5_FLOW: 909 cfg.size = sh->config.dv_flow_en ? 910 RTE_ALIGN_MUL_CEIL(sizeof(struct mlx5_flow_handle), 8) : 911 MLX5_FLOW_HANDLE_VERBS_SIZE; 912 break; 913 #if defined(HAVE_IBV_FLOW_DV_SUPPORT) || !defined(HAVE_INFINIBAND_VERBS_H) 914 /* Set MLX5_IPOOL_JUMP ipool entry size depending on selected flow engine. */ 915 case MLX5_IPOOL_JUMP: 916 cfg.size = sh->config.dv_flow_en == 2 ? 917 sizeof(struct mlx5_flow_group) : 918 sizeof(struct mlx5_flow_tbl_data_entry); 919 break; 920 #endif 921 } 922 if (sh->config.reclaim_mode) { 923 cfg.release_mem_en = 1; 924 cfg.per_core_cache = 0; 925 } else { 926 cfg.release_mem_en = 0; 927 } 928 sh->ipool[i] = mlx5_ipool_create(&cfg); 929 } 930 } 931 932 933 /** 934 * Release the flow resources' indexed mempool. 935 * 936 * @param[in] sh 937 * Pointer to mlx5_dev_ctx_shared object. 938 */ 939 static void 940 mlx5_flow_ipool_destroy(struct mlx5_dev_ctx_shared *sh) 941 { 942 uint8_t i; 943 944 for (i = 0; i < MLX5_IPOOL_MAX; ++i) 945 mlx5_ipool_destroy(sh->ipool[i]); 946 for (i = 0; i < MLX5_MAX_MODIFY_NUM; ++i) 947 if (sh->mdh_ipools[i]) 948 mlx5_ipool_destroy(sh->mdh_ipools[i]); 949 } 950 951 /* 952 * Check if dynamic flex parser for eCPRI already exists. 953 * 954 * @param dev 955 * Pointer to Ethernet device structure. 956 * 957 * @return 958 * true on exists, false on not. 959 */ 960 bool 961 mlx5_flex_parser_ecpri_exist(struct rte_eth_dev *dev) 962 { 963 struct mlx5_priv *priv = dev->data->dev_private; 964 struct mlx5_ecpri_parser_profile *prf = &priv->sh->ecpri_parser; 965 966 return !!prf->obj; 967 } 968 969 /* 970 * Allocation of a flex parser for eCPRI. Once created, this parser related 971 * resources will be held until the device is closed. 972 * 973 * @param dev 974 * Pointer to Ethernet device structure. 975 * 976 * @return 977 * 0 on success, a negative errno value otherwise and rte_errno is set. 978 */ 979 int 980 mlx5_flex_parser_ecpri_alloc(struct rte_eth_dev *dev) 981 { 982 struct mlx5_priv *priv = dev->data->dev_private; 983 struct mlx5_ecpri_parser_profile *prf = &priv->sh->ecpri_parser; 984 struct mlx5_devx_graph_node_attr node = { 985 .modify_field_select = 0, 986 }; 987 uint32_t ids[8]; 988 int ret; 989 990 if (!priv->sh->cdev->config.hca_attr.parse_graph_flex_node) { 991 DRV_LOG(ERR, "Dynamic flex parser is not supported " 992 "for device %s.", priv->dev_data->name); 993 return -ENOTSUP; 994 } 995 node.header_length_mode = MLX5_GRAPH_NODE_LEN_FIXED; 996 /* 8 bytes now: 4B common header + 4B message body header. */ 997 node.header_length_base_value = 0x8; 998 /* After MAC layer: Ether / VLAN. */ 999 node.in[0].arc_parse_graph_node = MLX5_GRAPH_ARC_NODE_MAC; 1000 /* Type of compared condition should be 0xAEFE in the L2 layer. */ 1001 node.in[0].compare_condition_value = RTE_ETHER_TYPE_ECPRI; 1002 /* Sample #0: type in common header. */ 1003 node.sample[0].flow_match_sample_en = 1; 1004 /* Fixed offset. */ 1005 node.sample[0].flow_match_sample_offset_mode = 0x0; 1006 /* Only the 2nd byte will be used. */ 1007 node.sample[0].flow_match_sample_field_base_offset = 0x0; 1008 /* Sample #1: message payload. */ 1009 node.sample[1].flow_match_sample_en = 1; 1010 /* Fixed offset. */ 1011 node.sample[1].flow_match_sample_offset_mode = 0x0; 1012 /* 1013 * Only the first two bytes will be used right now, and its offset will 1014 * start after the common header that with the length of a DW(u32). 1015 */ 1016 node.sample[1].flow_match_sample_field_base_offset = sizeof(uint32_t); 1017 prf->obj = mlx5_devx_cmd_create_flex_parser(priv->sh->cdev->ctx, &node); 1018 if (!prf->obj) { 1019 DRV_LOG(ERR, "Failed to create flex parser node object."); 1020 return (rte_errno == 0) ? -ENODEV : -rte_errno; 1021 } 1022 prf->num = 2; 1023 ret = mlx5_devx_cmd_query_parse_samples(prf->obj, ids, prf->num, NULL); 1024 if (ret) { 1025 DRV_LOG(ERR, "Failed to query sample IDs."); 1026 goto error; 1027 } 1028 prf->offset[0] = 0x0; 1029 prf->offset[1] = sizeof(uint32_t); 1030 prf->ids[0] = ids[0]; 1031 prf->ids[1] = ids[1]; 1032 return 0; 1033 error: 1034 mlx5_devx_cmd_destroy(prf->obj); 1035 return (rte_errno == 0) ? -ENODEV : -rte_errno; 1036 } 1037 1038 /* 1039 * Destroy the flex parser node, including the parser itself, input / output 1040 * arcs and DW samples. Resources could be reused then. 1041 * 1042 * @param dev 1043 * Pointer to Ethernet device structure. 1044 */ 1045 static void 1046 mlx5_flex_parser_ecpri_release(struct rte_eth_dev *dev) 1047 { 1048 struct mlx5_priv *priv = dev->data->dev_private; 1049 struct mlx5_ecpri_parser_profile *prf = &priv->sh->ecpri_parser; 1050 1051 if (prf->obj) 1052 mlx5_devx_cmd_destroy(prf->obj); 1053 prf->obj = NULL; 1054 } 1055 1056 /* 1057 * Allocation of a flex parser for srh. Once refcnt is zero, the resources held 1058 * by this parser will be freed. 1059 * @param dev 1060 * Pointer to Ethernet device structure. 1061 * 1062 * @return 1063 * 0 on success, a negative errno value otherwise and rte_errno is set. 1064 */ 1065 int 1066 mlx5_alloc_srh_flex_parser(struct rte_eth_dev *dev) 1067 { 1068 struct mlx5_devx_graph_node_attr node = { 1069 .modify_field_select = 0, 1070 }; 1071 uint32_t i; 1072 uint32_t ids[MLX5_GRAPH_NODE_SAMPLE_NUM]; 1073 struct mlx5_priv *priv = dev->data->dev_private; 1074 struct mlx5_common_dev_config *config = &priv->sh->cdev->config; 1075 struct mlx5_hca_flex_attr *attr = &priv->sh->cdev->config.hca_attr.flex; 1076 void *fp = NULL, *ibv_ctx = priv->sh->cdev->ctx; 1077 int ret; 1078 1079 memset(ids, 0xff, sizeof(ids)); 1080 if (!config->hca_attr.parse_graph_flex_node || 1081 !config->hca_attr.flex.query_match_sample_info) { 1082 DRV_LOG(ERR, "Dynamic flex parser is not supported on HWS"); 1083 return -ENOTSUP; 1084 } 1085 if (rte_atomic_fetch_add_explicit(&priv->sh->srh_flex_parser.refcnt, 1, 1086 rte_memory_order_relaxed) + 1 > 1) 1087 return 0; 1088 priv->sh->srh_flex_parser.flex.devx_fp = mlx5_malloc(MLX5_MEM_ZERO, 1089 sizeof(struct mlx5_flex_parser_devx), 0, SOCKET_ID_ANY); 1090 if (!priv->sh->srh_flex_parser.flex.devx_fp) 1091 return -ENOMEM; 1092 node.header_length_mode = MLX5_GRAPH_NODE_LEN_FIELD; 1093 /* Srv6 first two DW are not counted in. */ 1094 node.header_length_base_value = 0x8; 1095 /* The unit is uint64_t. */ 1096 node.header_length_field_shift = 0x3; 1097 /* Header length is the 2nd byte. */ 1098 node.header_length_field_offset = 0x8; 1099 if (attr->header_length_mask_width < 8) 1100 node.header_length_field_offset += 8 - attr->header_length_mask_width; 1101 node.header_length_field_mask = 0xF; 1102 /* One byte next header protocol. */ 1103 node.next_header_field_size = 0x8; 1104 node.in[0].arc_parse_graph_node = MLX5_GRAPH_ARC_NODE_IP; 1105 node.in[0].compare_condition_value = IPPROTO_ROUTING; 1106 /* Final IPv6 address. */ 1107 for (i = 0; i <= MLX5_SRV6_SAMPLE_NUM - 1 && i < MLX5_GRAPH_NODE_SAMPLE_NUM; i++) { 1108 node.sample[i].flow_match_sample_en = 1; 1109 node.sample[i].flow_match_sample_offset_mode = 1110 MLX5_GRAPH_SAMPLE_OFFSET_FIXED; 1111 /* First come first serve no matter inner or outer. */ 1112 node.sample[i].flow_match_sample_tunnel_mode = 1113 MLX5_GRAPH_SAMPLE_TUNNEL_FIRST; 1114 node.sample[i].flow_match_sample_field_base_offset = 1115 (i + 1) * sizeof(uint32_t); /* in bytes */ 1116 } 1117 node.sample[0].flow_match_sample_field_base_offset = 0; 1118 node.out[0].arc_parse_graph_node = MLX5_GRAPH_ARC_NODE_TCP; 1119 node.out[0].compare_condition_value = IPPROTO_TCP; 1120 node.out[1].arc_parse_graph_node = MLX5_GRAPH_ARC_NODE_UDP; 1121 node.out[1].compare_condition_value = IPPROTO_UDP; 1122 node.out[2].arc_parse_graph_node = MLX5_GRAPH_ARC_NODE_IPV6; 1123 node.out[2].compare_condition_value = IPPROTO_IPV6; 1124 fp = mlx5_devx_cmd_create_flex_parser(ibv_ctx, &node); 1125 if (!fp) { 1126 DRV_LOG(ERR, "Failed to create flex parser node object."); 1127 goto error; 1128 } 1129 priv->sh->srh_flex_parser.flex.devx_fp->devx_obj = fp; 1130 priv->sh->srh_flex_parser.flex.mapnum = MLX5_SRV6_SAMPLE_NUM; 1131 priv->sh->srh_flex_parser.flex.devx_fp->num_samples = MLX5_SRV6_SAMPLE_NUM; 1132 1133 ret = mlx5_devx_cmd_query_parse_samples(fp, ids, priv->sh->srh_flex_parser.flex.mapnum, 1134 &priv->sh->srh_flex_parser.flex.devx_fp->anchor_id); 1135 if (ret) { 1136 DRV_LOG(ERR, "Failed to query sample IDs."); 1137 goto error; 1138 } 1139 for (i = 0; i <= MLX5_SRV6_SAMPLE_NUM - 1 && i < MLX5_GRAPH_NODE_SAMPLE_NUM; i++) { 1140 ret = mlx5_devx_cmd_match_sample_info_query(ibv_ctx, ids[i], 1141 &priv->sh->srh_flex_parser.flex.devx_fp->sample_info[i]); 1142 if (ret) { 1143 DRV_LOG(ERR, "Failed to query sample id %u information.", ids[i]); 1144 goto error; 1145 } 1146 } 1147 for (i = 0; i <= MLX5_SRV6_SAMPLE_NUM - 1 && i < MLX5_GRAPH_NODE_SAMPLE_NUM; i++) { 1148 priv->sh->srh_flex_parser.flex.devx_fp->sample_ids[i] = ids[i]; 1149 priv->sh->srh_flex_parser.flex.map[i].width = sizeof(uint32_t) * CHAR_BIT; 1150 priv->sh->srh_flex_parser.flex.map[i].reg_id = i; 1151 priv->sh->srh_flex_parser.flex.map[i].shift = 1152 (i + 1) * sizeof(uint32_t) * CHAR_BIT; 1153 } 1154 priv->sh->srh_flex_parser.flex.map[0].shift = 0; 1155 return 0; 1156 error: 1157 if (fp) 1158 mlx5_devx_cmd_destroy(fp); 1159 if (priv->sh->srh_flex_parser.flex.devx_fp) 1160 mlx5_free(priv->sh->srh_flex_parser.flex.devx_fp); 1161 return (rte_errno == 0) ? -ENODEV : -rte_errno; 1162 } 1163 1164 /* 1165 * Destroy the flex parser node, including the parser itself, input / output 1166 * arcs and DW samples. Resources could be reused then. 1167 * 1168 * @param dev 1169 * Pointer to Ethernet device structure 1170 */ 1171 void 1172 mlx5_free_srh_flex_parser(struct rte_eth_dev *dev) 1173 { 1174 struct mlx5_priv *priv = dev->data->dev_private; 1175 struct mlx5_internal_flex_parser_profile *fp = &priv->sh->srh_flex_parser; 1176 1177 if (rte_atomic_fetch_sub_explicit(&fp->refcnt, 1, rte_memory_order_relaxed) - 1) 1178 return; 1179 mlx5_devx_cmd_destroy(fp->flex.devx_fp->devx_obj); 1180 mlx5_free(fp->flex.devx_fp); 1181 fp->flex.devx_fp = NULL; 1182 } 1183 1184 uint32_t 1185 mlx5_get_supported_sw_parsing_offloads(const struct mlx5_hca_attr *attr) 1186 { 1187 uint32_t sw_parsing_offloads = 0; 1188 1189 if (attr->swp) { 1190 sw_parsing_offloads |= MLX5_SW_PARSING_CAP; 1191 if (attr->swp_csum) 1192 sw_parsing_offloads |= MLX5_SW_PARSING_CSUM_CAP; 1193 1194 if (attr->swp_lso) 1195 sw_parsing_offloads |= MLX5_SW_PARSING_TSO_CAP; 1196 } 1197 return sw_parsing_offloads; 1198 } 1199 1200 uint32_t 1201 mlx5_get_supported_tunneling_offloads(const struct mlx5_hca_attr *attr) 1202 { 1203 uint32_t tn_offloads = 0; 1204 1205 if (attr->tunnel_stateless_vxlan) 1206 tn_offloads |= MLX5_TUNNELED_OFFLOADS_VXLAN_CAP; 1207 if (attr->tunnel_stateless_gre) 1208 tn_offloads |= MLX5_TUNNELED_OFFLOADS_GRE_CAP; 1209 if (attr->tunnel_stateless_geneve_rx) 1210 tn_offloads |= MLX5_TUNNELED_OFFLOADS_GENEVE_CAP; 1211 return tn_offloads; 1212 } 1213 1214 /* Fill all fields of UAR structure. */ 1215 static int 1216 mlx5_rxtx_uars_prepare(struct mlx5_dev_ctx_shared *sh) 1217 { 1218 int ret; 1219 1220 ret = mlx5_devx_uar_prepare(sh->cdev, &sh->tx_uar); 1221 if (ret) { 1222 DRV_LOG(ERR, "Failed to prepare Tx DevX UAR."); 1223 return -rte_errno; 1224 } 1225 MLX5_ASSERT(sh->tx_uar.obj); 1226 MLX5_ASSERT(mlx5_os_get_devx_uar_base_addr(sh->tx_uar.obj)); 1227 ret = mlx5_devx_uar_prepare(sh->cdev, &sh->rx_uar); 1228 if (ret) { 1229 DRV_LOG(ERR, "Failed to prepare Rx DevX UAR."); 1230 mlx5_devx_uar_release(&sh->tx_uar); 1231 return -rte_errno; 1232 } 1233 MLX5_ASSERT(sh->rx_uar.obj); 1234 MLX5_ASSERT(mlx5_os_get_devx_uar_base_addr(sh->rx_uar.obj)); 1235 return 0; 1236 } 1237 1238 static void 1239 mlx5_rxtx_uars_release(struct mlx5_dev_ctx_shared *sh) 1240 { 1241 mlx5_devx_uar_release(&sh->rx_uar); 1242 mlx5_devx_uar_release(&sh->tx_uar); 1243 } 1244 1245 /** 1246 * rte_mempool_walk() callback to unregister Rx mempools. 1247 * It used when implicit mempool registration is disabled. 1248 * 1249 * @param mp 1250 * The mempool being walked. 1251 * @param arg 1252 * Pointer to the device shared context. 1253 */ 1254 static void 1255 mlx5_dev_ctx_shared_rx_mempool_unregister_cb(struct rte_mempool *mp, void *arg) 1256 { 1257 struct mlx5_dev_ctx_shared *sh = arg; 1258 1259 mlx5_dev_mempool_unregister(sh->cdev, mp); 1260 } 1261 1262 /** 1263 * Callback used when implicit mempool registration is disabled 1264 * in order to track Rx mempool destruction. 1265 * 1266 * @param event 1267 * Mempool life cycle event. 1268 * @param mp 1269 * An Rx mempool registered explicitly when the port is started. 1270 * @param arg 1271 * Pointer to a device shared context. 1272 */ 1273 static void 1274 mlx5_dev_ctx_shared_rx_mempool_event_cb(enum rte_mempool_event event, 1275 struct rte_mempool *mp, void *arg) 1276 { 1277 struct mlx5_dev_ctx_shared *sh = arg; 1278 1279 if (event == RTE_MEMPOOL_EVENT_DESTROY) 1280 mlx5_dev_mempool_unregister(sh->cdev, mp); 1281 } 1282 1283 int 1284 mlx5_dev_ctx_shared_mempool_subscribe(struct rte_eth_dev *dev) 1285 { 1286 struct mlx5_priv *priv = dev->data->dev_private; 1287 struct mlx5_dev_ctx_shared *sh = priv->sh; 1288 int ret; 1289 1290 /* Check if we only need to track Rx mempool destruction. */ 1291 if (!sh->cdev->config.mr_mempool_reg_en) { 1292 ret = rte_mempool_event_callback_register 1293 (mlx5_dev_ctx_shared_rx_mempool_event_cb, sh); 1294 return ret == 0 || rte_errno == EEXIST ? 0 : ret; 1295 } 1296 return mlx5_dev_mempool_subscribe(sh->cdev); 1297 } 1298 1299 /** 1300 * Set up multiple TISs with different affinities according to 1301 * number of bonding ports 1302 * 1303 * @param priv 1304 * Pointer of shared context. 1305 * 1306 * @return 1307 * Zero on success, -1 otherwise. 1308 */ 1309 static int 1310 mlx5_setup_tis(struct mlx5_dev_ctx_shared *sh) 1311 { 1312 struct mlx5_devx_lag_context lag_ctx = { 0 }; 1313 struct mlx5_devx_tis_attr tis_attr = { 0 }; 1314 int i; 1315 1316 tis_attr.transport_domain = sh->td->id; 1317 if (sh->bond.n_port) { 1318 if (!mlx5_devx_cmd_query_lag(sh->cdev->ctx, &lag_ctx)) { 1319 sh->lag.tx_remap_affinity[0] = 1320 lag_ctx.tx_remap_affinity_1; 1321 sh->lag.tx_remap_affinity[1] = 1322 lag_ctx.tx_remap_affinity_2; 1323 sh->lag.affinity_mode = lag_ctx.port_select_mode; 1324 } else { 1325 DRV_LOG(ERR, "Failed to query lag affinity."); 1326 return -1; 1327 } 1328 if (sh->lag.affinity_mode == MLX5_LAG_MODE_TIS) 1329 DRV_LOG(DEBUG, "LAG number of ports : %d, affinity_1 & 2 : pf%d & %d.\n", 1330 sh->bond.n_port, lag_ctx.tx_remap_affinity_1, 1331 lag_ctx.tx_remap_affinity_2); 1332 else if (sh->lag.affinity_mode == MLX5_LAG_MODE_HASH) 1333 DRV_LOG(INFO, "Device %s enabled HW hash based LAG.", 1334 sh->ibdev_name); 1335 } 1336 for (i = 0; i <= sh->bond.n_port; i++) { 1337 /* 1338 * lag_tx_port_affinity: 0 auto-selection, 1 PF1, 2 PF2 vice versa. 1339 * Each TIS binds to one PF by setting lag_tx_port_affinity (> 0). 1340 * Once LAG enabled, we create multiple TISs and bind each one to 1341 * different PFs, then TIS[i+1] gets affinity i+1 and goes to PF i+1. 1342 * TIS[0] is reserved for HW Hash mode. 1343 */ 1344 tis_attr.lag_tx_port_affinity = i; 1345 sh->tis[i] = mlx5_devx_cmd_create_tis(sh->cdev->ctx, &tis_attr); 1346 if (!sh->tis[i]) { 1347 DRV_LOG(ERR, "Failed to create TIS %d/%d for [bonding] device" 1348 " %s.", i, sh->bond.n_port, 1349 sh->ibdev_name); 1350 return -1; 1351 } 1352 } 1353 return 0; 1354 } 1355 1356 /** 1357 * Verify and store value for share device argument. 1358 * 1359 * @param[in] key 1360 * Key argument to verify. 1361 * @param[in] val 1362 * Value associated with key. 1363 * @param opaque 1364 * User data. 1365 * 1366 * @return 1367 * 0 on success, a negative errno value otherwise and rte_errno is set. 1368 */ 1369 static int 1370 mlx5_dev_args_check_handler(const char *key, const char *val, void *opaque) 1371 { 1372 struct mlx5_sh_config *config = opaque; 1373 signed long tmp; 1374 1375 errno = 0; 1376 tmp = strtol(val, NULL, 0); 1377 if (errno) { 1378 rte_errno = errno; 1379 DRV_LOG(WARNING, "%s: \"%s\" is not a valid integer", key, val); 1380 return -rte_errno; 1381 } 1382 if (tmp < 0 && strcmp(MLX5_TX_PP, key) && strcmp(MLX5_TX_SKEW, key)) { 1383 /* Negative values are acceptable for some keys only. */ 1384 rte_errno = EINVAL; 1385 DRV_LOG(WARNING, "%s: invalid negative value \"%s\"", key, val); 1386 return -rte_errno; 1387 } 1388 if (strcmp(MLX5_TX_PP, key) == 0) { 1389 unsigned long mod = tmp >= 0 ? tmp : -tmp; 1390 1391 if (!mod) { 1392 DRV_LOG(ERR, "Zero Tx packet pacing parameter."); 1393 rte_errno = EINVAL; 1394 return -rte_errno; 1395 } 1396 config->tx_pp = tmp; 1397 } else if (strcmp(MLX5_TX_SKEW, key) == 0) { 1398 config->tx_skew = tmp; 1399 } else if (strcmp(MLX5_L3_VXLAN_EN, key) == 0) { 1400 config->l3_vxlan_en = !!tmp; 1401 } else if (strcmp(MLX5_VF_NL_EN, key) == 0) { 1402 config->vf_nl_en = !!tmp; 1403 } else if (strcmp(MLX5_DV_ESW_EN, key) == 0) { 1404 config->dv_esw_en = !!tmp; 1405 } else if (strcmp(MLX5_DV_FLOW_EN, key) == 0) { 1406 if (tmp > 2) { 1407 DRV_LOG(ERR, "Invalid %s parameter.", key); 1408 rte_errno = EINVAL; 1409 return -rte_errno; 1410 } 1411 config->dv_flow_en = tmp; 1412 } else if (strcmp(MLX5_DV_XMETA_EN, key) == 0) { 1413 if (tmp != MLX5_XMETA_MODE_LEGACY && 1414 tmp != MLX5_XMETA_MODE_META16 && 1415 tmp != MLX5_XMETA_MODE_META32 && 1416 tmp != MLX5_XMETA_MODE_MISS_INFO && 1417 tmp != MLX5_XMETA_MODE_META32_HWS) { 1418 DRV_LOG(ERR, "Invalid extensive metadata parameter."); 1419 rte_errno = EINVAL; 1420 return -rte_errno; 1421 } 1422 if (tmp != MLX5_XMETA_MODE_MISS_INFO) 1423 config->dv_xmeta_en = tmp; 1424 else 1425 config->dv_miss_info = 1; 1426 } else if (strcmp(MLX5_LACP_BY_USER, key) == 0) { 1427 config->lacp_by_user = !!tmp; 1428 } else if (strcmp(MLX5_RECLAIM_MEM, key) == 0) { 1429 if (tmp != MLX5_RCM_NONE && 1430 tmp != MLX5_RCM_LIGHT && 1431 tmp != MLX5_RCM_AGGR) { 1432 DRV_LOG(ERR, "Unrecognize %s: \"%s\"", key, val); 1433 rte_errno = EINVAL; 1434 return -rte_errno; 1435 } 1436 config->reclaim_mode = tmp; 1437 } else if (strcmp(MLX5_DECAP_EN, key) == 0) { 1438 config->decap_en = !!tmp; 1439 } else if (strcmp(MLX5_ALLOW_DUPLICATE_PATTERN, key) == 0) { 1440 config->allow_duplicate_pattern = !!tmp; 1441 } else if (strcmp(MLX5_FDB_DEFAULT_RULE_EN, key) == 0) { 1442 config->fdb_def_rule = !!tmp; 1443 } else if (strcmp(MLX5_HWS_CNT_SERVICE_CORE, key) == 0) { 1444 config->cnt_svc.service_core = tmp; 1445 } else if (strcmp(MLX5_HWS_CNT_CYCLE_TIME, key) == 0) { 1446 config->cnt_svc.cycle_time = tmp; 1447 } else if (strcmp(MLX5_REPR_MATCHING_EN, key) == 0) { 1448 config->repr_matching = !!tmp; 1449 } 1450 return 0; 1451 } 1452 1453 /** 1454 * Parse user device parameters and adjust them according to device 1455 * capabilities. 1456 * 1457 * @param sh 1458 * Pointer to shared device context. 1459 * @param mkvlist 1460 * Pointer to mlx5 kvargs control, can be NULL if there is no devargs. 1461 * @param config 1462 * Pointer to shared device configuration structure. 1463 * 1464 * @return 1465 * 0 on success, a negative errno value otherwise and rte_errno is set. 1466 */ 1467 static int 1468 mlx5_shared_dev_ctx_args_config(struct mlx5_dev_ctx_shared *sh, 1469 struct mlx5_kvargs_ctrl *mkvlist, 1470 struct mlx5_sh_config *config) 1471 { 1472 const char **params = (const char *[]){ 1473 MLX5_TX_PP, 1474 MLX5_TX_SKEW, 1475 MLX5_L3_VXLAN_EN, 1476 MLX5_VF_NL_EN, 1477 MLX5_DV_ESW_EN, 1478 MLX5_DV_FLOW_EN, 1479 MLX5_DV_XMETA_EN, 1480 MLX5_LACP_BY_USER, 1481 MLX5_RECLAIM_MEM, 1482 MLX5_DECAP_EN, 1483 MLX5_ALLOW_DUPLICATE_PATTERN, 1484 MLX5_FDB_DEFAULT_RULE_EN, 1485 MLX5_HWS_CNT_SERVICE_CORE, 1486 MLX5_HWS_CNT_CYCLE_TIME, 1487 MLX5_REPR_MATCHING_EN, 1488 NULL, 1489 }; 1490 int ret = 0; 1491 1492 /* Default configuration. */ 1493 memset(config, 0, sizeof(*config)); 1494 config->vf_nl_en = 1; 1495 config->dv_esw_en = 1; 1496 config->dv_flow_en = 1; 1497 config->decap_en = 1; 1498 config->allow_duplicate_pattern = 1; 1499 config->fdb_def_rule = 1; 1500 config->cnt_svc.cycle_time = MLX5_CNT_SVC_CYCLE_TIME_DEFAULT; 1501 config->cnt_svc.service_core = rte_get_main_lcore(); 1502 config->repr_matching = 1; 1503 if (mkvlist != NULL) { 1504 /* Process parameters. */ 1505 ret = mlx5_kvargs_process(mkvlist, params, 1506 mlx5_dev_args_check_handler, config); 1507 if (ret) { 1508 DRV_LOG(ERR, "Failed to process device arguments: %s", 1509 strerror(rte_errno)); 1510 return -rte_errno; 1511 } 1512 } 1513 /* Adjust parameters according to device capabilities. */ 1514 if (config->dv_flow_en && !sh->dev_cap.dv_flow_en) { 1515 DRV_LOG(WARNING, "DV flow is not supported."); 1516 config->dv_flow_en = 0; 1517 } 1518 if (config->dv_esw_en && !sh->dev_cap.dv_esw_en) { 1519 DRV_LOG(DEBUG, "E-Switch DV flow is not supported."); 1520 config->dv_esw_en = 0; 1521 } 1522 if (config->dv_esw_en && !config->dv_flow_en) { 1523 DRV_LOG(DEBUG, 1524 "E-Switch DV flow is supported only when DV flow is enabled."); 1525 config->dv_esw_en = 0; 1526 } 1527 if (config->dv_miss_info && config->dv_esw_en) 1528 config->dv_xmeta_en = MLX5_XMETA_MODE_META16; 1529 if (!config->dv_esw_en && 1530 config->dv_xmeta_en != MLX5_XMETA_MODE_LEGACY) { 1531 DRV_LOG(WARNING, 1532 "Metadata mode %u is not supported (no E-Switch).", 1533 config->dv_xmeta_en); 1534 config->dv_xmeta_en = MLX5_XMETA_MODE_LEGACY; 1535 } 1536 if (config->dv_flow_en != 2 && !config->repr_matching) { 1537 DRV_LOG(DEBUG, "Disabling representor matching is valid only " 1538 "when HW Steering is enabled."); 1539 config->repr_matching = 1; 1540 } 1541 if (config->tx_pp && !sh->dev_cap.txpp_en) { 1542 DRV_LOG(ERR, "Packet pacing is not supported."); 1543 rte_errno = ENODEV; 1544 return -rte_errno; 1545 } 1546 if (!config->tx_pp && config->tx_skew && 1547 !sh->cdev->config.hca_attr.wait_on_time) { 1548 DRV_LOG(WARNING, 1549 "\"tx_skew\" doesn't affect without \"tx_pp\"."); 1550 } 1551 /* Check for LRO support. */ 1552 if (mlx5_devx_obj_ops_en(sh) && sh->cdev->config.hca_attr.lro_cap) { 1553 /* TBD check tunnel lro caps. */ 1554 config->lro_allowed = 1; 1555 DRV_LOG(DEBUG, "LRO is allowed."); 1556 DRV_LOG(DEBUG, 1557 "LRO minimal size of TCP segment required for coalescing is %d bytes.", 1558 sh->cdev->config.hca_attr.lro_min_mss_size); 1559 } 1560 /* 1561 * If HW has bug working with tunnel packet decapsulation and scatter 1562 * FCS, and decapsulation is needed, clear the hw_fcs_strip bit. 1563 * Then RTE_ETH_RX_OFFLOAD_KEEP_CRC bit will not be set anymore. 1564 */ 1565 if (sh->dev_cap.scatter_fcs_w_decap_disable && sh->config.decap_en) 1566 config->hw_fcs_strip = 0; 1567 else 1568 config->hw_fcs_strip = sh->dev_cap.hw_fcs_strip; 1569 DRV_LOG(DEBUG, "FCS stripping configuration is %ssupported", 1570 (config->hw_fcs_strip ? "" : "not ")); 1571 DRV_LOG(DEBUG, "\"tx_pp\" is %d.", config->tx_pp); 1572 DRV_LOG(DEBUG, "\"tx_skew\" is %d.", config->tx_skew); 1573 DRV_LOG(DEBUG, "\"reclaim_mode\" is %u.", config->reclaim_mode); 1574 DRV_LOG(DEBUG, "\"dv_esw_en\" is %u.", config->dv_esw_en); 1575 DRV_LOG(DEBUG, "\"dv_flow_en\" is %u.", config->dv_flow_en); 1576 DRV_LOG(DEBUG, "\"dv_xmeta_en\" is %u.", config->dv_xmeta_en); 1577 DRV_LOG(DEBUG, "\"dv_miss_info\" is %u.", config->dv_miss_info); 1578 DRV_LOG(DEBUG, "\"l3_vxlan_en\" is %u.", config->l3_vxlan_en); 1579 DRV_LOG(DEBUG, "\"vf_nl_en\" is %u.", config->vf_nl_en); 1580 DRV_LOG(DEBUG, "\"lacp_by_user\" is %u.", config->lacp_by_user); 1581 DRV_LOG(DEBUG, "\"decap_en\" is %u.", config->decap_en); 1582 DRV_LOG(DEBUG, "\"allow_duplicate_pattern\" is %u.", 1583 config->allow_duplicate_pattern); 1584 DRV_LOG(DEBUG, "\"fdb_def_rule_en\" is %u.", config->fdb_def_rule); 1585 DRV_LOG(DEBUG, "\"repr_matching_en\" is %u.", config->repr_matching); 1586 return 0; 1587 } 1588 1589 /** 1590 * Configure realtime timestamp format. 1591 * 1592 * @param sh 1593 * Pointer to mlx5_dev_ctx_shared object. 1594 * @param hca_attr 1595 * Pointer to DevX HCA capabilities structure. 1596 */ 1597 void 1598 mlx5_rt_timestamp_config(struct mlx5_dev_ctx_shared *sh, 1599 struct mlx5_hca_attr *hca_attr) 1600 { 1601 uint32_t dw_cnt = MLX5_ST_SZ_DW(register_mtutc); 1602 uint32_t reg[dw_cnt]; 1603 int ret = ENOTSUP; 1604 1605 if (hca_attr->access_register_user) 1606 ret = mlx5_devx_cmd_register_read(sh->cdev->ctx, 1607 MLX5_REGISTER_ID_MTUTC, 0, 1608 reg, dw_cnt); 1609 if (!ret) { 1610 uint32_t ts_mode; 1611 1612 /* MTUTC register is read successfully. */ 1613 ts_mode = MLX5_GET(register_mtutc, reg, time_stamp_mode); 1614 if (ts_mode == MLX5_MTUTC_TIMESTAMP_MODE_REAL_TIME) 1615 sh->dev_cap.rt_timestamp = 1; 1616 } else { 1617 /* Kernel does not support register reading. */ 1618 if (hca_attr->dev_freq_khz == (NS_PER_S / MS_PER_S)) 1619 sh->dev_cap.rt_timestamp = 1; 1620 } 1621 } 1622 1623 static void 1624 mlx5_init_hws_flow_tags_registers(struct mlx5_dev_ctx_shared *sh) 1625 { 1626 struct mlx5_dev_registers *reg = &sh->registers; 1627 uint32_t meta_mode = sh->config.dv_xmeta_en; 1628 uint16_t masks = (uint16_t)sh->cdev->config.hca_attr.set_reg_c; 1629 uint16_t unset = 0; 1630 uint32_t i, j; 1631 1632 /* 1633 * The CAPA is global for common device but only used in net. 1634 * It is shared per eswitch domain. 1635 */ 1636 if (reg->aso_reg != REG_NON) 1637 unset |= 1 << mlx5_regc_index(reg->aso_reg); 1638 unset |= 1 << mlx5_regc_index(REG_C_6); 1639 if (sh->config.dv_esw_en) 1640 unset |= 1 << mlx5_regc_index(REG_C_0); 1641 if (meta_mode == MLX5_XMETA_MODE_META32_HWS) 1642 unset |= 1 << mlx5_regc_index(REG_C_1); 1643 masks &= ~unset; 1644 for (i = 0, j = 0; i < MLX5_FLOW_HW_TAGS_MAX; i++) { 1645 if (!!((1 << i) & masks)) 1646 reg->hw_avl_tags[j++] = mlx5_regc_value(i); 1647 } 1648 /* 1649 * Set the registers for NAT64 usage internally. REG_C_6 is always used. 1650 * The other 2 registers will be fetched from right to left, at least 2 1651 * tag registers should be available. 1652 */ 1653 MLX5_ASSERT(j >= (MLX5_FLOW_NAT64_REGS_MAX - 1)); 1654 reg->nat64_regs[0] = REG_C_6; 1655 reg->nat64_regs[1] = reg->hw_avl_tags[j - 2]; 1656 reg->nat64_regs[2] = reg->hw_avl_tags[j - 1]; 1657 } 1658 1659 static void 1660 mlx5_init_aso_register(struct mlx5_dev_ctx_shared *sh) 1661 { 1662 #if defined(HAVE_MLX5_DR_CREATE_ACTION_ASO_EXT) 1663 const struct mlx5_hca_attr *hca_attr = &sh->cdev->config.hca_attr; 1664 const struct mlx5_hca_qos_attr *qos = &hca_attr->qos; 1665 uint8_t reg_c_mask = qos->flow_meter_reg_c_ids & 0xfc; 1666 1667 if (!(qos->sup && qos->flow_meter_old && sh->config.dv_flow_en)) 1668 return; 1669 /* 1670 * Meter needs two REG_C's for color match and pre-sfx 1671 * flow match. Here get the REG_C for color match. 1672 * REG_C_0 and REG_C_1 is reserved for metadata feature. 1673 */ 1674 if (rte_popcount32(reg_c_mask) > 0) { 1675 /* 1676 * The meter color register is used by the 1677 * flow-hit feature as well. 1678 * The flow-hit feature must use REG_C_3 1679 * Prefer REG_C_3 if it is available. 1680 */ 1681 if (reg_c_mask & (1 << mlx5_regc_index(REG_C_3))) 1682 sh->registers.aso_reg = REG_C_3; 1683 else 1684 sh->registers.aso_reg = 1685 mlx5_regc_value(ffs(reg_c_mask) - 1); 1686 } 1687 #else 1688 RTE_SET_USED(sh); 1689 #endif 1690 } 1691 1692 static void 1693 mlx5_init_shared_dev_registers(struct mlx5_dev_ctx_shared *sh) 1694 { 1695 if (sh->cdev->config.devx) 1696 mlx5_init_aso_register(sh); 1697 if (sh->registers.aso_reg != REG_NON) { 1698 DRV_LOG(DEBUG, "ASO register: REG_C%d", 1699 mlx5_regc_index(sh->registers.aso_reg)); 1700 } else { 1701 DRV_LOG(DEBUG, "ASO register: NONE"); 1702 } 1703 if (sh->config.dv_flow_en == 2) 1704 mlx5_init_hws_flow_tags_registers(sh); 1705 } 1706 1707 static struct mlx5_physical_device * 1708 mlx5_get_physical_device(struct mlx5_common_device *cdev) 1709 { 1710 struct mlx5_physical_device *phdev; 1711 struct mlx5_hca_attr *attr = &cdev->config.hca_attr; 1712 1713 /* Search for physical device by system_image_guid. */ 1714 LIST_FOREACH(phdev, &phdev_list, next) { 1715 if (phdev->guid == attr->system_image_guid) { 1716 phdev->refcnt++; 1717 return phdev; 1718 } 1719 } 1720 phdev = mlx5_malloc(MLX5_MEM_ZERO | MLX5_MEM_RTE, 1721 sizeof(struct mlx5_physical_device), 1722 RTE_CACHE_LINE_SIZE, SOCKET_ID_ANY); 1723 if (!phdev) { 1724 DRV_LOG(ERR, "Physical device allocation failure."); 1725 rte_errno = ENOMEM; 1726 return NULL; 1727 } 1728 phdev->guid = attr->system_image_guid; 1729 phdev->refcnt = 1; 1730 LIST_INSERT_HEAD(&phdev_list, phdev, next); 1731 DRV_LOG(DEBUG, "Physical device is created, guid=%" PRIu64 ".", 1732 phdev->guid); 1733 return phdev; 1734 } 1735 1736 struct mlx5_physical_device * 1737 mlx5_get_locked_physical_device(struct mlx5_priv *priv) 1738 { 1739 pthread_mutex_lock(&mlx5_dev_ctx_list_mutex); 1740 return priv->sh->phdev; 1741 } 1742 1743 void 1744 mlx5_unlock_physical_device(void) 1745 { 1746 pthread_mutex_unlock(&mlx5_dev_ctx_list_mutex); 1747 } 1748 1749 static void 1750 mlx5_physical_device_destroy(struct mlx5_physical_device *phdev) 1751 { 1752 #ifdef RTE_LIBRTE_MLX5_DEBUG 1753 /* Check the object presence in the list. */ 1754 struct mlx5_physical_device *lphdev; 1755 1756 LIST_FOREACH(lphdev, &phdev_list, next) 1757 if (lphdev == phdev) 1758 break; 1759 MLX5_ASSERT(lphdev); 1760 if (lphdev != phdev) { 1761 DRV_LOG(ERR, "Freeing non-existing physical device"); 1762 return; 1763 } 1764 #endif 1765 MLX5_ASSERT(phdev); 1766 MLX5_ASSERT(phdev->refcnt); 1767 if (--phdev->refcnt) 1768 return; 1769 /* Remove physical device from the global device list. */ 1770 LIST_REMOVE(phdev, next); 1771 mlx5_free(phdev); 1772 } 1773 1774 /** 1775 * Allocate shared device context. If there is multiport device the 1776 * master and representors will share this context, if there is single 1777 * port dedicated device, the context will be used by only given 1778 * port due to unification. 1779 * 1780 * Routine first searches the context for the specified device name, 1781 * if found the shared context assumed and reference counter is incremented. 1782 * If no context found the new one is created and initialized with specified 1783 * device context and parameters. 1784 * 1785 * @param[in] spawn 1786 * Pointer to the device attributes (name, port, etc). 1787 * @param mkvlist 1788 * Pointer to mlx5 kvargs control, can be NULL if there is no devargs. 1789 * 1790 * @return 1791 * Pointer to mlx5_dev_ctx_shared object on success, 1792 * otherwise NULL and rte_errno is set. 1793 */ 1794 struct mlx5_dev_ctx_shared * 1795 mlx5_alloc_shared_dev_ctx(const struct mlx5_dev_spawn_data *spawn, 1796 struct mlx5_kvargs_ctrl *mkvlist) 1797 { 1798 struct mlx5_dev_ctx_shared *sh; 1799 int err = 0; 1800 uint32_t i; 1801 1802 MLX5_ASSERT(spawn); 1803 /* Secondary process should not create the shared context. */ 1804 MLX5_ASSERT(rte_eal_process_type() == RTE_PROC_PRIMARY); 1805 pthread_mutex_lock(&mlx5_dev_ctx_list_mutex); 1806 /* Search for IB context by device name. */ 1807 LIST_FOREACH(sh, &dev_ctx_list, next) { 1808 if (!strcmp(sh->ibdev_name, spawn->phys_dev_name)) { 1809 sh->refcnt++; 1810 goto exit; 1811 } 1812 } 1813 /* No device found, we have to create new shared context. */ 1814 MLX5_ASSERT(spawn->max_port); 1815 sh = mlx5_malloc(MLX5_MEM_ZERO | MLX5_MEM_RTE, 1816 sizeof(struct mlx5_dev_ctx_shared) + 1817 spawn->max_port * sizeof(struct mlx5_dev_shared_port), 1818 RTE_CACHE_LINE_SIZE, SOCKET_ID_ANY); 1819 if (!sh) { 1820 DRV_LOG(ERR, "Shared context allocation failure."); 1821 rte_errno = ENOMEM; 1822 goto exit; 1823 } 1824 pthread_mutex_init(&sh->txpp.mutex, NULL); 1825 sh->numa_node = spawn->cdev->dev->numa_node; 1826 sh->cdev = spawn->cdev; 1827 sh->esw_mode = !!(spawn->info.master || spawn->info.representor); 1828 if (spawn->bond_info) 1829 sh->bond = *spawn->bond_info; 1830 err = mlx5_os_capabilities_prepare(sh); 1831 if (err) { 1832 DRV_LOG(ERR, "Fail to configure device capabilities."); 1833 goto error; 1834 } 1835 err = mlx5_shared_dev_ctx_args_config(sh, mkvlist, &sh->config); 1836 if (err) { 1837 DRV_LOG(ERR, "Failed to process device configure: %s", 1838 strerror(rte_errno)); 1839 goto error; 1840 } 1841 sh->refcnt = 1; 1842 sh->max_port = spawn->max_port; 1843 strncpy(sh->ibdev_name, mlx5_os_get_ctx_device_name(sh->cdev->ctx), 1844 sizeof(sh->ibdev_name) - 1); 1845 strncpy(sh->ibdev_path, mlx5_os_get_ctx_device_path(sh->cdev->ctx), 1846 sizeof(sh->ibdev_path) - 1); 1847 sh->phdev = mlx5_get_physical_device(sh->cdev); 1848 if (!sh->phdev) 1849 goto error; 1850 /* 1851 * Setting port_id to max unallowed value means there is no interrupt 1852 * subhandler installed for the given port index i. 1853 */ 1854 for (i = 0; i < sh->max_port; i++) { 1855 sh->port[i].ih_port_id = RTE_MAX_ETHPORTS; 1856 sh->port[i].devx_ih_port_id = RTE_MAX_ETHPORTS; 1857 sh->port[i].nl_ih_port_id = RTE_MAX_ETHPORTS; 1858 } 1859 if (sh->cdev->config.devx) { 1860 sh->td = mlx5_devx_cmd_create_td(sh->cdev->ctx); 1861 if (!sh->td) { 1862 DRV_LOG(ERR, "TD allocation failure"); 1863 rte_errno = ENOMEM; 1864 goto error; 1865 } 1866 if (mlx5_setup_tis(sh)) { 1867 DRV_LOG(ERR, "TIS allocation failure"); 1868 rte_errno = ENOMEM; 1869 goto error; 1870 } 1871 err = mlx5_rxtx_uars_prepare(sh); 1872 if (err) 1873 goto error; 1874 #ifndef RTE_ARCH_64 1875 } else { 1876 /* Initialize UAR access locks for 32bit implementations. */ 1877 rte_spinlock_init(&sh->uar_lock_cq); 1878 for (i = 0; i < MLX5_UAR_PAGE_NUM_MAX; i++) 1879 rte_spinlock_init(&sh->uar_lock[i]); 1880 #endif 1881 } 1882 mlx5_os_dev_shared_handler_install(sh); 1883 if (LIST_EMPTY(&dev_ctx_list)) { 1884 err = mlx5_flow_os_init_workspace_once(); 1885 if (err) 1886 goto error; 1887 } 1888 err = mlx5_flow_counters_mng_init(sh); 1889 if (err) { 1890 DRV_LOG(ERR, "Fail to initialize counters manage."); 1891 goto error; 1892 } 1893 mlx5_flow_aging_init(sh); 1894 mlx5_flow_ipool_create(sh); 1895 /* Add context to the global device list. */ 1896 LIST_INSERT_HEAD(&dev_ctx_list, sh, next); 1897 rte_spinlock_init(&sh->geneve_tlv_opt_sl); 1898 mlx5_init_shared_dev_registers(sh); 1899 /* Init counter pool list header and lock. */ 1900 LIST_INIT(&sh->hws_cpool_list); 1901 rte_spinlock_init(&sh->cpool_lock); 1902 exit: 1903 pthread_mutex_unlock(&mlx5_dev_ctx_list_mutex); 1904 return sh; 1905 error: 1906 err = rte_errno; 1907 pthread_mutex_destroy(&sh->txpp.mutex); 1908 pthread_mutex_unlock(&mlx5_dev_ctx_list_mutex); 1909 MLX5_ASSERT(sh); 1910 mlx5_rxtx_uars_release(sh); 1911 i = 0; 1912 do { 1913 if (sh->tis[i]) 1914 claim_zero(mlx5_devx_cmd_destroy(sh->tis[i])); 1915 } while (++i <= (uint32_t)sh->bond.n_port); 1916 if (sh->td) 1917 claim_zero(mlx5_devx_cmd_destroy(sh->td)); 1918 if (sh->phdev) 1919 mlx5_physical_device_destroy(sh->phdev); 1920 mlx5_free(sh); 1921 rte_errno = err; 1922 return NULL; 1923 } 1924 1925 /** 1926 * Create LWM event_channel and interrupt handle for shared device 1927 * context. All rxqs sharing the device context share the event_channel. 1928 * A callback is registered in interrupt thread to receive the LWM event. 1929 * 1930 * @param[in] priv 1931 * Pointer to mlx5_priv instance. 1932 * 1933 * @return 1934 * 0 on success, negative with rte_errno set. 1935 */ 1936 int 1937 mlx5_lwm_setup(struct mlx5_priv *priv) 1938 { 1939 int fd_lwm; 1940 1941 pthread_mutex_init(&priv->sh->lwm_config_lock, NULL); 1942 priv->sh->devx_channel_lwm = mlx5_os_devx_create_event_channel 1943 (priv->sh->cdev->ctx, 1944 MLX5DV_DEVX_CREATE_EVENT_CHANNEL_FLAGS_OMIT_EV_DATA); 1945 if (!priv->sh->devx_channel_lwm) 1946 goto err; 1947 fd_lwm = mlx5_os_get_devx_channel_fd(priv->sh->devx_channel_lwm); 1948 priv->sh->intr_handle_lwm = mlx5_os_interrupt_handler_create 1949 (RTE_INTR_INSTANCE_F_SHARED, true, 1950 fd_lwm, mlx5_dev_interrupt_handler_lwm, priv); 1951 if (!priv->sh->intr_handle_lwm) 1952 goto err; 1953 return 0; 1954 err: 1955 if (priv->sh->devx_channel_lwm) { 1956 mlx5_os_devx_destroy_event_channel 1957 (priv->sh->devx_channel_lwm); 1958 priv->sh->devx_channel_lwm = NULL; 1959 } 1960 pthread_mutex_destroy(&priv->sh->lwm_config_lock); 1961 return -rte_errno; 1962 } 1963 1964 /** 1965 * Destroy LWM event_channel and interrupt handle for shared device 1966 * context before free this context. The interrupt handler is also 1967 * unregistered. 1968 * 1969 * @param[in] sh 1970 * Pointer to shared device context. 1971 */ 1972 void 1973 mlx5_lwm_unset(struct mlx5_dev_ctx_shared *sh) 1974 { 1975 if (sh->intr_handle_lwm) { 1976 mlx5_os_interrupt_handler_destroy(sh->intr_handle_lwm, 1977 mlx5_dev_interrupt_handler_lwm, (void *)-1); 1978 sh->intr_handle_lwm = NULL; 1979 } 1980 if (sh->devx_channel_lwm) { 1981 mlx5_os_devx_destroy_event_channel 1982 (sh->devx_channel_lwm); 1983 sh->devx_channel_lwm = NULL; 1984 } 1985 pthread_mutex_destroy(&sh->lwm_config_lock); 1986 } 1987 1988 /** 1989 * Free shared IB device context. Decrement counter and if zero free 1990 * all allocated resources and close handles. 1991 * 1992 * @param[in] sh 1993 * Pointer to mlx5_dev_ctx_shared object to free 1994 */ 1995 void 1996 mlx5_free_shared_dev_ctx(struct mlx5_dev_ctx_shared *sh) 1997 { 1998 int ret; 1999 int i = 0; 2000 2001 pthread_mutex_lock(&mlx5_dev_ctx_list_mutex); 2002 #ifdef RTE_LIBRTE_MLX5_DEBUG 2003 /* Check the object presence in the list. */ 2004 struct mlx5_dev_ctx_shared *lctx; 2005 2006 LIST_FOREACH(lctx, &dev_ctx_list, next) 2007 if (lctx == sh) 2008 break; 2009 MLX5_ASSERT(lctx); 2010 if (lctx != sh) { 2011 DRV_LOG(ERR, "Freeing non-existing shared IB context"); 2012 goto exit; 2013 } 2014 #endif 2015 MLX5_ASSERT(sh); 2016 MLX5_ASSERT(sh->refcnt); 2017 /* Secondary process should not free the shared context. */ 2018 MLX5_ASSERT(rte_eal_process_type() == RTE_PROC_PRIMARY); 2019 if (--sh->refcnt) 2020 goto exit; 2021 /* Stop watching for mempool events and unregister all mempools. */ 2022 if (!sh->cdev->config.mr_mempool_reg_en) { 2023 ret = rte_mempool_event_callback_unregister 2024 (mlx5_dev_ctx_shared_rx_mempool_event_cb, sh); 2025 if (ret == 0) 2026 rte_mempool_walk 2027 (mlx5_dev_ctx_shared_rx_mempool_unregister_cb, sh); 2028 } 2029 /* Remove context from the global device list. */ 2030 LIST_REMOVE(sh, next); 2031 /* Release resources on the last device removal. */ 2032 if (LIST_EMPTY(&dev_ctx_list)) { 2033 mlx5_os_net_cleanup(); 2034 mlx5_flow_os_release_workspace(); 2035 } 2036 pthread_mutex_unlock(&mlx5_dev_ctx_list_mutex); 2037 if (sh->flex_parsers_dv) { 2038 mlx5_list_destroy(sh->flex_parsers_dv); 2039 sh->flex_parsers_dv = NULL; 2040 } 2041 /* 2042 * Ensure there is no async event handler installed. 2043 * Only primary process handles async device events. 2044 **/ 2045 mlx5_flow_counters_mng_close(sh); 2046 if (sh->ct_mng) 2047 mlx5_flow_aso_ct_mng_close(sh); 2048 if (sh->aso_age_mng) { 2049 mlx5_flow_aso_age_mng_close(sh); 2050 sh->aso_age_mng = NULL; 2051 } 2052 if (sh->mtrmng) 2053 mlx5_aso_flow_mtrs_mng_close(sh); 2054 mlx5_flow_ipool_destroy(sh); 2055 mlx5_os_dev_shared_handler_uninstall(sh); 2056 mlx5_rxtx_uars_release(sh); 2057 do { 2058 if (sh->tis[i]) 2059 claim_zero(mlx5_devx_cmd_destroy(sh->tis[i])); 2060 } while (++i <= sh->bond.n_port); 2061 if (sh->td) 2062 claim_zero(mlx5_devx_cmd_destroy(sh->td)); 2063 MLX5_ASSERT(sh->geneve_tlv_option_resource == NULL); 2064 pthread_mutex_destroy(&sh->txpp.mutex); 2065 mlx5_lwm_unset(sh); 2066 mlx5_physical_device_destroy(sh->phdev); 2067 mlx5_free(sh); 2068 return; 2069 exit: 2070 pthread_mutex_unlock(&mlx5_dev_ctx_list_mutex); 2071 } 2072 2073 /** 2074 * Destroy table hash list. 2075 * 2076 * @param[in] priv 2077 * Pointer to the private device data structure. 2078 */ 2079 void 2080 mlx5_free_table_hash_list(struct mlx5_priv *priv) 2081 { 2082 struct mlx5_dev_ctx_shared *sh = priv->sh; 2083 struct mlx5_hlist **tbls = (priv->sh->config.dv_flow_en == 2) ? 2084 &sh->groups : &sh->flow_tbls; 2085 if (*tbls == NULL) 2086 return; 2087 mlx5_hlist_destroy(*tbls); 2088 *tbls = NULL; 2089 } 2090 2091 #ifdef HAVE_MLX5_HWS_SUPPORT 2092 /** 2093 * Allocate HW steering group hash list. 2094 * 2095 * @param[in] priv 2096 * Pointer to the private device data structure. 2097 */ 2098 static int 2099 mlx5_alloc_hw_group_hash_list(struct mlx5_priv *priv) 2100 { 2101 int err = 0; 2102 struct mlx5_dev_ctx_shared *sh = priv->sh; 2103 char s[MLX5_NAME_SIZE]; 2104 2105 MLX5_ASSERT(sh); 2106 snprintf(s, sizeof(s), "%s_flow_groups", priv->sh->ibdev_name); 2107 sh->groups = mlx5_hlist_create 2108 (s, MLX5_FLOW_TABLE_HLIST_ARRAY_SIZE, 2109 false, true, sh, 2110 flow_hw_grp_create_cb, 2111 flow_hw_grp_match_cb, 2112 flow_hw_grp_remove_cb, 2113 flow_hw_grp_clone_cb, 2114 flow_hw_grp_clone_free_cb); 2115 if (!sh->groups) { 2116 DRV_LOG(ERR, "flow groups with hash creation failed."); 2117 err = ENOMEM; 2118 } 2119 return err; 2120 } 2121 #endif 2122 2123 2124 /** 2125 * Initialize flow table hash list and create the root tables entry 2126 * for each domain. 2127 * 2128 * @param[in] priv 2129 * Pointer to the private device data structure. 2130 * 2131 * @return 2132 * Zero on success, positive error code otherwise. 2133 */ 2134 int 2135 mlx5_alloc_table_hash_list(struct mlx5_priv *priv __rte_unused) 2136 { 2137 int err = 0; 2138 2139 /* Tables are only used in DV and DR modes. */ 2140 #if defined(HAVE_IBV_FLOW_DV_SUPPORT) || !defined(HAVE_INFINIBAND_VERBS_H) 2141 struct mlx5_dev_ctx_shared *sh = priv->sh; 2142 char s[MLX5_NAME_SIZE]; 2143 2144 #ifdef HAVE_MLX5_HWS_SUPPORT 2145 if (priv->sh->config.dv_flow_en == 2) 2146 return mlx5_alloc_hw_group_hash_list(priv); 2147 #endif 2148 MLX5_ASSERT(sh); 2149 snprintf(s, sizeof(s), "%s_flow_table", priv->sh->ibdev_name); 2150 sh->flow_tbls = mlx5_hlist_create(s, MLX5_FLOW_TABLE_HLIST_ARRAY_SIZE, 2151 false, true, sh, 2152 flow_dv_tbl_create_cb, 2153 flow_dv_tbl_match_cb, 2154 flow_dv_tbl_remove_cb, 2155 flow_dv_tbl_clone_cb, 2156 flow_dv_tbl_clone_free_cb); 2157 if (!sh->flow_tbls) { 2158 DRV_LOG(ERR, "flow tables with hash creation failed."); 2159 err = ENOMEM; 2160 return err; 2161 } 2162 #ifndef HAVE_MLX5DV_DR 2163 struct rte_flow_error error; 2164 struct rte_eth_dev *dev = &rte_eth_devices[priv->dev_data->port_id]; 2165 2166 /* 2167 * In case we have not DR support, the zero tables should be created 2168 * because DV expect to see them even if they cannot be created by 2169 * RDMA-CORE. 2170 */ 2171 if (!flow_dv_tbl_resource_get(dev, 0, 0, 0, 0, 2172 NULL, 0, 1, 0, &error) || 2173 !flow_dv_tbl_resource_get(dev, 0, 1, 0, 0, 2174 NULL, 0, 1, 0, &error) || 2175 !flow_dv_tbl_resource_get(dev, 0, 0, 1, 0, 2176 NULL, 0, 1, 0, &error)) { 2177 err = ENOMEM; 2178 goto error; 2179 } 2180 return err; 2181 error: 2182 mlx5_free_table_hash_list(priv); 2183 #endif /* HAVE_MLX5DV_DR */ 2184 #endif 2185 return err; 2186 } 2187 2188 /** 2189 * Retrieve integer value from environment variable. 2190 * 2191 * @param[in] name 2192 * Environment variable name. 2193 * 2194 * @return 2195 * Integer value, 0 if the variable is not set. 2196 */ 2197 int 2198 mlx5_getenv_int(const char *name) 2199 { 2200 const char *val = getenv(name); 2201 2202 if (val == NULL) 2203 return 0; 2204 return atoi(val); 2205 } 2206 2207 /** 2208 * DPDK callback to add udp tunnel port 2209 * 2210 * @param[in] dev 2211 * A pointer to eth_dev 2212 * @param[in] udp_tunnel 2213 * A pointer to udp tunnel 2214 * 2215 * @return 2216 * 0 on valid udp ports and tunnels, -ENOTSUP otherwise. 2217 */ 2218 int 2219 mlx5_udp_tunnel_port_add(struct rte_eth_dev *dev __rte_unused, 2220 struct rte_eth_udp_tunnel *udp_tunnel) 2221 { 2222 MLX5_ASSERT(udp_tunnel != NULL); 2223 if (udp_tunnel->prot_type == RTE_ETH_TUNNEL_TYPE_VXLAN && 2224 udp_tunnel->udp_port == 4789) 2225 return 0; 2226 if (udp_tunnel->prot_type == RTE_ETH_TUNNEL_TYPE_VXLAN_GPE && 2227 udp_tunnel->udp_port == 4790) 2228 return 0; 2229 return -ENOTSUP; 2230 } 2231 2232 /** 2233 * Initialize process private data structure. 2234 * 2235 * @param dev 2236 * Pointer to Ethernet device structure. 2237 * 2238 * @return 2239 * 0 on success, a negative errno value otherwise and rte_errno is set. 2240 */ 2241 int 2242 mlx5_proc_priv_init(struct rte_eth_dev *dev) 2243 { 2244 struct mlx5_priv *priv = dev->data->dev_private; 2245 struct mlx5_dev_ctx_shared *sh = priv->sh; 2246 struct mlx5_proc_priv *ppriv; 2247 size_t ppriv_size; 2248 2249 mlx5_proc_priv_uninit(dev); 2250 /* 2251 * UAR register table follows the process private structure. BlueFlame 2252 * registers for Tx queues are stored in the table. 2253 */ 2254 ppriv_size = sizeof(struct mlx5_proc_priv) + 2255 priv->txqs_n * sizeof(struct mlx5_uar_data); 2256 ppriv = mlx5_malloc(MLX5_MEM_RTE | MLX5_MEM_ZERO, ppriv_size, 2257 RTE_CACHE_LINE_SIZE, dev->device->numa_node); 2258 if (!ppriv) { 2259 rte_errno = ENOMEM; 2260 return -rte_errno; 2261 } 2262 ppriv->uar_table_sz = priv->txqs_n; 2263 dev->process_private = ppriv; 2264 if (rte_eal_process_type() == RTE_PROC_PRIMARY) 2265 priv->sh->pppriv = ppriv; 2266 /* Check and try to map HCA PCI BAR to allow reading real time. */ 2267 if (sh->dev_cap.rt_timestamp && mlx5_dev_is_pci(dev->device)) 2268 mlx5_txpp_map_hca_bar(dev); 2269 return 0; 2270 } 2271 2272 /** 2273 * Un-initialize process private data structure. 2274 * 2275 * @param dev 2276 * Pointer to Ethernet device structure. 2277 */ 2278 void 2279 mlx5_proc_priv_uninit(struct rte_eth_dev *dev) 2280 { 2281 struct mlx5_proc_priv *ppriv = dev->process_private; 2282 2283 if (!ppriv) 2284 return; 2285 if (ppriv->hca_bar) 2286 mlx5_txpp_unmap_hca_bar(dev); 2287 mlx5_free(dev->process_private); 2288 dev->process_private = NULL; 2289 } 2290 2291 /** 2292 * DPDK callback to close the device. 2293 * 2294 * Destroy all queues and objects, free memory. 2295 * 2296 * @param dev 2297 * Pointer to Ethernet device structure. 2298 */ 2299 int 2300 mlx5_dev_close(struct rte_eth_dev *dev) 2301 { 2302 struct mlx5_priv *priv = dev->data->dev_private; 2303 struct mlx5_dev_ctx_shared *sh; 2304 unsigned int i; 2305 int ret; 2306 2307 if (rte_eal_process_type() == RTE_PROC_SECONDARY) { 2308 if (!priv) 2309 DRV_LOG(WARNING, "primary process is already closed"); 2310 /* Check if process_private released. */ 2311 if (!dev->process_private) 2312 return 0; 2313 mlx5_tx_uar_uninit_secondary(dev); 2314 mlx5_proc_priv_uninit(dev); 2315 rte_eth_dev_release_port(dev); 2316 return 0; 2317 } 2318 sh = priv->sh; 2319 if (!sh) 2320 return 0; 2321 if (priv->shared_refcnt) { 2322 DRV_LOG(ERR, "port %u is shared host in use (%u)", 2323 dev->data->port_id, priv->shared_refcnt); 2324 rte_errno = EBUSY; 2325 return -EBUSY; 2326 } 2327 #ifdef HAVE_MLX5_HWS_SUPPORT 2328 /* Check if shared GENEVE options created on context being closed. */ 2329 ret = mlx5_geneve_tlv_options_check_busy(priv); 2330 if (ret) { 2331 DRV_LOG(ERR, "port %u maintains shared GENEVE TLV options", 2332 dev->data->port_id); 2333 return ret; 2334 } 2335 #endif 2336 DRV_LOG(DEBUG, "port %u closing device \"%s\"", 2337 dev->data->port_id, sh->ibdev_name); 2338 /* 2339 * If default mreg copy action is removed at the stop stage, 2340 * the search will return none and nothing will be done anymore. 2341 */ 2342 mlx5_flow_stop_default(dev); 2343 mlx5_traffic_disable(dev); 2344 /* 2345 * If all the flows are already flushed in the device stop stage, 2346 * then this will return directly without any action. 2347 */ 2348 mlx5_flow_list_flush(dev, MLX5_FLOW_TYPE_GEN, true); 2349 mlx5_action_handle_flush(dev); 2350 mlx5_flow_meter_flush(dev, NULL); 2351 /* Prevent crashes when queues are still in use. */ 2352 dev->rx_pkt_burst = rte_eth_pkt_burst_dummy; 2353 dev->tx_pkt_burst = rte_eth_pkt_burst_dummy; 2354 rte_wmb(); 2355 /* Disable datapath on secondary process. */ 2356 mlx5_mp_os_req_stop_rxtx(dev); 2357 /* Free the eCPRI flex parser resource. */ 2358 mlx5_flex_parser_ecpri_release(dev); 2359 mlx5_flex_item_port_cleanup(dev); 2360 mlx5_indirect_list_handles_release(dev); 2361 #ifdef HAVE_MLX5_HWS_SUPPORT 2362 flow_hw_destroy_vport_action(dev); 2363 /* dr context will be closed after mlx5_os_free_shared_dr. */ 2364 flow_hw_resource_release(dev); 2365 flow_hw_clear_port_info(dev); 2366 if (priv->tlv_options != NULL) { 2367 /* Free the GENEVE TLV parser resource. */ 2368 claim_zero(mlx5_geneve_tlv_options_destroy(priv->tlv_options, sh->phdev)); 2369 priv->tlv_options = NULL; 2370 } 2371 if (priv->ptype_rss_groups) { 2372 mlx5_ipool_destroy(priv->ptype_rss_groups); 2373 priv->ptype_rss_groups = NULL; 2374 } 2375 #endif 2376 if (priv->rxq_privs != NULL) { 2377 /* XXX race condition if mlx5_rx_burst() is still running. */ 2378 rte_delay_us_sleep(1000); 2379 for (i = 0; (i != priv->rxqs_n); ++i) 2380 mlx5_rxq_release(dev, i); 2381 priv->rxqs_n = 0; 2382 mlx5_free(priv->rxq_privs); 2383 priv->rxq_privs = NULL; 2384 } 2385 if (priv->txqs != NULL && dev->data->tx_queues != NULL) { 2386 /* XXX race condition if mlx5_tx_burst() is still running. */ 2387 rte_delay_us_sleep(1000); 2388 for (i = 0; (i != priv->txqs_n); ++i) 2389 mlx5_txq_release(dev, i); 2390 priv->txqs_n = 0; 2391 priv->txqs = NULL; 2392 } 2393 mlx5_proc_priv_uninit(dev); 2394 if (priv->drop_queue.hrxq) 2395 mlx5_drop_action_destroy(dev); 2396 if (priv->q_counters) { 2397 mlx5_devx_cmd_destroy(priv->q_counters); 2398 priv->q_counters = NULL; 2399 } 2400 if (priv->q_counters_hairpin) { 2401 mlx5_devx_cmd_destroy(priv->q_counters_hairpin); 2402 priv->q_counters_hairpin = NULL; 2403 } 2404 mlx5_mprq_free_mp(dev); 2405 mlx5_os_free_shared_dr(priv); 2406 #ifdef HAVE_MLX5_HWS_SUPPORT 2407 if (priv->dr_ctx) { 2408 claim_zero(mlx5dr_context_close(priv->dr_ctx)); 2409 priv->dr_ctx = NULL; 2410 } 2411 #endif 2412 if (priv->rss_conf.rss_key != NULL) 2413 mlx5_free(priv->rss_conf.rss_key); 2414 if (priv->reta_idx != NULL) 2415 mlx5_free(priv->reta_idx); 2416 if (sh->dev_cap.vf) 2417 mlx5_os_mac_addr_flush(dev); 2418 if (priv->nl_socket_route >= 0) 2419 close(priv->nl_socket_route); 2420 if (priv->nl_socket_rdma >= 0) 2421 close(priv->nl_socket_rdma); 2422 if (priv->vmwa_context) 2423 mlx5_vlan_vmwa_exit(priv->vmwa_context); 2424 ret = mlx5_hrxq_verify(dev); 2425 if (ret) 2426 DRV_LOG(WARNING, "port %u some hash Rx queue still remain", 2427 dev->data->port_id); 2428 ret = mlx5_ind_table_obj_verify(dev); 2429 if (ret) 2430 DRV_LOG(WARNING, "port %u some indirection table still remain", 2431 dev->data->port_id); 2432 ret = mlx5_rxq_obj_verify(dev); 2433 if (ret) 2434 DRV_LOG(WARNING, "port %u some Rx queue objects still remain", 2435 dev->data->port_id); 2436 ret = mlx5_ext_rxq_verify(dev); 2437 if (ret) 2438 DRV_LOG(WARNING, "Port %u some external RxQ still remain.", 2439 dev->data->port_id); 2440 ret = mlx5_rxq_verify(dev); 2441 if (ret) 2442 DRV_LOG(WARNING, "port %u some Rx queues still remain", 2443 dev->data->port_id); 2444 ret = mlx5_txq_obj_verify(dev); 2445 if (ret) 2446 DRV_LOG(WARNING, "port %u some Verbs Tx queue still remain", 2447 dev->data->port_id); 2448 ret = mlx5_ext_txq_verify(dev); 2449 if (ret) 2450 DRV_LOG(WARNING, "Port %u some external TxQ still remain.", 2451 dev->data->port_id); 2452 ret = mlx5_txq_verify(dev); 2453 if (ret) 2454 DRV_LOG(WARNING, "port %u some Tx queues still remain", 2455 dev->data->port_id); 2456 ret = mlx5_flow_verify(dev); 2457 if (ret) 2458 DRV_LOG(WARNING, "port %u some flows still remain", 2459 dev->data->port_id); 2460 if (priv->hrxqs) 2461 mlx5_list_destroy(priv->hrxqs); 2462 mlx5_free(priv->ext_rxqs); 2463 mlx5_free(priv->ext_txqs); 2464 sh->port[priv->dev_port - 1].nl_ih_port_id = RTE_MAX_ETHPORTS; 2465 /* 2466 * The interrupt handler port id must be reset before priv is reset 2467 * since 'mlx5_dev_interrupt_nl_cb' uses priv. 2468 */ 2469 rte_io_wmb(); 2470 /* 2471 * Free the shared context in last turn, because the cleanup 2472 * routines above may use some shared fields, like 2473 * mlx5_os_mac_addr_flush() uses ibdev_path for retrieving 2474 * ifindex if Netlink fails. 2475 */ 2476 mlx5_free_shared_dev_ctx(sh); 2477 if (priv->domain_id != RTE_ETH_DEV_SWITCH_DOMAIN_ID_INVALID) { 2478 unsigned int c = 0; 2479 uint16_t port_id; 2480 2481 MLX5_ETH_FOREACH_DEV(port_id, dev->device) { 2482 struct mlx5_priv *opriv = 2483 rte_eth_devices[port_id].data->dev_private; 2484 2485 if (!opriv || 2486 opriv->domain_id != priv->domain_id || 2487 &rte_eth_devices[port_id] == dev) 2488 continue; 2489 ++c; 2490 break; 2491 } 2492 if (!c) 2493 claim_zero(rte_eth_switch_domain_free(priv->domain_id)); 2494 } 2495 memset(priv, 0, sizeof(*priv)); 2496 priv->domain_id = RTE_ETH_DEV_SWITCH_DOMAIN_ID_INVALID; 2497 /* 2498 * Reset mac_addrs to NULL such that it is not freed as part of 2499 * rte_eth_dev_release_port(). mac_addrs is part of dev_private so 2500 * it is freed when dev_private is freed. 2501 */ 2502 dev->data->mac_addrs = NULL; 2503 return 0; 2504 } 2505 2506 const struct eth_dev_ops mlx5_dev_ops = { 2507 .dev_configure = mlx5_dev_configure, 2508 .dev_start = mlx5_dev_start, 2509 .dev_stop = mlx5_dev_stop, 2510 .dev_set_link_down = mlx5_set_link_down, 2511 .dev_set_link_up = mlx5_set_link_up, 2512 .dev_close = mlx5_dev_close, 2513 .promiscuous_enable = mlx5_promiscuous_enable, 2514 .promiscuous_disable = mlx5_promiscuous_disable, 2515 .allmulticast_enable = mlx5_allmulticast_enable, 2516 .allmulticast_disable = mlx5_allmulticast_disable, 2517 .link_update = mlx5_link_update, 2518 .stats_get = mlx5_stats_get, 2519 .stats_reset = mlx5_stats_reset, 2520 .xstats_get = mlx5_xstats_get, 2521 .xstats_reset = mlx5_xstats_reset, 2522 .xstats_get_names = mlx5_xstats_get_names, 2523 .fw_version_get = mlx5_fw_version_get, 2524 .dev_infos_get = mlx5_dev_infos_get, 2525 .representor_info_get = mlx5_representor_info_get, 2526 .read_clock = mlx5_txpp_read_clock, 2527 .dev_supported_ptypes_get = mlx5_dev_supported_ptypes_get, 2528 .vlan_filter_set = mlx5_vlan_filter_set, 2529 .rx_queue_setup = mlx5_rx_queue_setup, 2530 .rx_queue_avail_thresh_set = mlx5_rx_queue_lwm_set, 2531 .rx_queue_avail_thresh_query = mlx5_rx_queue_lwm_query, 2532 .rx_hairpin_queue_setup = mlx5_rx_hairpin_queue_setup, 2533 .tx_queue_setup = mlx5_tx_queue_setup, 2534 .tx_hairpin_queue_setup = mlx5_tx_hairpin_queue_setup, 2535 .rx_queue_release = mlx5_rx_queue_release, 2536 .tx_queue_release = mlx5_tx_queue_release, 2537 .rx_queue_start = mlx5_rx_queue_start, 2538 .rx_queue_stop = mlx5_rx_queue_stop, 2539 .tx_queue_start = mlx5_tx_queue_start, 2540 .tx_queue_stop = mlx5_tx_queue_stop, 2541 .flow_ctrl_get = mlx5_dev_get_flow_ctrl, 2542 .flow_ctrl_set = mlx5_dev_set_flow_ctrl, 2543 .mac_addr_remove = mlx5_mac_addr_remove, 2544 .mac_addr_add = mlx5_mac_addr_add, 2545 .mac_addr_set = mlx5_mac_addr_set, 2546 .set_mc_addr_list = mlx5_set_mc_addr_list, 2547 .mtu_set = mlx5_dev_set_mtu, 2548 .vlan_strip_queue_set = mlx5_vlan_strip_queue_set, 2549 .vlan_offload_set = mlx5_vlan_offload_set, 2550 .reta_update = mlx5_dev_rss_reta_update, 2551 .reta_query = mlx5_dev_rss_reta_query, 2552 .rss_hash_update = mlx5_rss_hash_update, 2553 .rss_hash_conf_get = mlx5_rss_hash_conf_get, 2554 .flow_ops_get = mlx5_flow_ops_get, 2555 .rxq_info_get = mlx5_rxq_info_get, 2556 .txq_info_get = mlx5_txq_info_get, 2557 .rx_burst_mode_get = mlx5_rx_burst_mode_get, 2558 .tx_burst_mode_get = mlx5_tx_burst_mode_get, 2559 .rx_queue_intr_enable = mlx5_rx_intr_enable, 2560 .rx_queue_intr_disable = mlx5_rx_intr_disable, 2561 .is_removed = mlx5_is_removed, 2562 .udp_tunnel_port_add = mlx5_udp_tunnel_port_add, 2563 .get_module_info = mlx5_get_module_info, 2564 .get_module_eeprom = mlx5_get_module_eeprom, 2565 .hairpin_cap_get = mlx5_hairpin_cap_get, 2566 .mtr_ops_get = mlx5_flow_meter_ops_get, 2567 .hairpin_bind = mlx5_hairpin_bind, 2568 .hairpin_unbind = mlx5_hairpin_unbind, 2569 .hairpin_get_peer_ports = mlx5_hairpin_get_peer_ports, 2570 .hairpin_queue_peer_update = mlx5_hairpin_queue_peer_update, 2571 .hairpin_queue_peer_bind = mlx5_hairpin_queue_peer_bind, 2572 .hairpin_queue_peer_unbind = mlx5_hairpin_queue_peer_unbind, 2573 .get_monitor_addr = mlx5_get_monitor_addr, 2574 .count_aggr_ports = mlx5_count_aggr_ports, 2575 .map_aggr_tx_affinity = mlx5_map_aggr_tx_affinity, 2576 .rx_metadata_negotiate = mlx5_flow_rx_metadata_negotiate, 2577 .get_restore_flags = mlx5_get_restore_flags, 2578 }; 2579 2580 /* Available operations from secondary process. */ 2581 const struct eth_dev_ops mlx5_dev_sec_ops = { 2582 .stats_get = mlx5_stats_get, 2583 .stats_reset = mlx5_stats_reset, 2584 .xstats_get = mlx5_xstats_get, 2585 .xstats_reset = mlx5_xstats_reset, 2586 .xstats_get_names = mlx5_xstats_get_names, 2587 .fw_version_get = mlx5_fw_version_get, 2588 .dev_infos_get = mlx5_dev_infos_get, 2589 .representor_info_get = mlx5_representor_info_get, 2590 .read_clock = mlx5_txpp_read_clock, 2591 .rx_queue_start = mlx5_rx_queue_start, 2592 .rx_queue_stop = mlx5_rx_queue_stop, 2593 .tx_queue_start = mlx5_tx_queue_start, 2594 .tx_queue_stop = mlx5_tx_queue_stop, 2595 .rxq_info_get = mlx5_rxq_info_get, 2596 .txq_info_get = mlx5_txq_info_get, 2597 .rx_burst_mode_get = mlx5_rx_burst_mode_get, 2598 .tx_burst_mode_get = mlx5_tx_burst_mode_get, 2599 .get_module_info = mlx5_get_module_info, 2600 .get_module_eeprom = mlx5_get_module_eeprom, 2601 .count_aggr_ports = mlx5_count_aggr_ports, 2602 .map_aggr_tx_affinity = mlx5_map_aggr_tx_affinity, 2603 .rx_metadata_negotiate = mlx5_flow_rx_metadata_negotiate, 2604 }; 2605 2606 /* Available operations in flow isolated mode. */ 2607 const struct eth_dev_ops mlx5_dev_ops_isolate = { 2608 .dev_configure = mlx5_dev_configure, 2609 .dev_start = mlx5_dev_start, 2610 .dev_stop = mlx5_dev_stop, 2611 .dev_set_link_down = mlx5_set_link_down, 2612 .dev_set_link_up = mlx5_set_link_up, 2613 .dev_close = mlx5_dev_close, 2614 .promiscuous_enable = mlx5_promiscuous_enable, 2615 .promiscuous_disable = mlx5_promiscuous_disable, 2616 .allmulticast_enable = mlx5_allmulticast_enable, 2617 .allmulticast_disable = mlx5_allmulticast_disable, 2618 .link_update = mlx5_link_update, 2619 .stats_get = mlx5_stats_get, 2620 .stats_reset = mlx5_stats_reset, 2621 .xstats_get = mlx5_xstats_get, 2622 .xstats_reset = mlx5_xstats_reset, 2623 .xstats_get_names = mlx5_xstats_get_names, 2624 .fw_version_get = mlx5_fw_version_get, 2625 .dev_infos_get = mlx5_dev_infos_get, 2626 .representor_info_get = mlx5_representor_info_get, 2627 .read_clock = mlx5_txpp_read_clock, 2628 .dev_supported_ptypes_get = mlx5_dev_supported_ptypes_get, 2629 .vlan_filter_set = mlx5_vlan_filter_set, 2630 .rx_queue_setup = mlx5_rx_queue_setup, 2631 .rx_hairpin_queue_setup = mlx5_rx_hairpin_queue_setup, 2632 .tx_queue_setup = mlx5_tx_queue_setup, 2633 .tx_hairpin_queue_setup = mlx5_tx_hairpin_queue_setup, 2634 .rx_queue_release = mlx5_rx_queue_release, 2635 .tx_queue_release = mlx5_tx_queue_release, 2636 .rx_queue_start = mlx5_rx_queue_start, 2637 .rx_queue_stop = mlx5_rx_queue_stop, 2638 .tx_queue_start = mlx5_tx_queue_start, 2639 .tx_queue_stop = mlx5_tx_queue_stop, 2640 .flow_ctrl_get = mlx5_dev_get_flow_ctrl, 2641 .flow_ctrl_set = mlx5_dev_set_flow_ctrl, 2642 .mac_addr_remove = mlx5_mac_addr_remove, 2643 .mac_addr_add = mlx5_mac_addr_add, 2644 .mac_addr_set = mlx5_mac_addr_set, 2645 .set_mc_addr_list = mlx5_set_mc_addr_list, 2646 .mtu_set = mlx5_dev_set_mtu, 2647 .vlan_strip_queue_set = mlx5_vlan_strip_queue_set, 2648 .vlan_offload_set = mlx5_vlan_offload_set, 2649 .flow_ops_get = mlx5_flow_ops_get, 2650 .rxq_info_get = mlx5_rxq_info_get, 2651 .txq_info_get = mlx5_txq_info_get, 2652 .rx_burst_mode_get = mlx5_rx_burst_mode_get, 2653 .tx_burst_mode_get = mlx5_tx_burst_mode_get, 2654 .rx_queue_intr_enable = mlx5_rx_intr_enable, 2655 .rx_queue_intr_disable = mlx5_rx_intr_disable, 2656 .is_removed = mlx5_is_removed, 2657 .get_module_info = mlx5_get_module_info, 2658 .get_module_eeprom = mlx5_get_module_eeprom, 2659 .hairpin_cap_get = mlx5_hairpin_cap_get, 2660 .mtr_ops_get = mlx5_flow_meter_ops_get, 2661 .hairpin_bind = mlx5_hairpin_bind, 2662 .hairpin_unbind = mlx5_hairpin_unbind, 2663 .hairpin_get_peer_ports = mlx5_hairpin_get_peer_ports, 2664 .hairpin_queue_peer_update = mlx5_hairpin_queue_peer_update, 2665 .hairpin_queue_peer_bind = mlx5_hairpin_queue_peer_bind, 2666 .hairpin_queue_peer_unbind = mlx5_hairpin_queue_peer_unbind, 2667 .get_monitor_addr = mlx5_get_monitor_addr, 2668 .count_aggr_ports = mlx5_count_aggr_ports, 2669 .map_aggr_tx_affinity = mlx5_map_aggr_tx_affinity, 2670 .get_restore_flags = mlx5_get_restore_flags, 2671 }; 2672 2673 /** 2674 * Verify and store value for device argument. 2675 * 2676 * @param[in] key 2677 * Key argument to verify. 2678 * @param[in] val 2679 * Value associated with key. 2680 * @param opaque 2681 * User data. 2682 * 2683 * @return 2684 * 0 on success, a negative errno value otherwise and rte_errno is set. 2685 */ 2686 static int 2687 mlx5_port_args_check_handler(const char *key, const char *val, void *opaque) 2688 { 2689 struct mlx5_port_config *config = opaque; 2690 signed long tmp; 2691 2692 /* No-op, port representors are processed in mlx5_dev_spawn(). */ 2693 if (!strcmp(MLX5_REPRESENTOR, key)) 2694 return 0; 2695 errno = 0; 2696 tmp = strtol(val, NULL, 0); 2697 if (errno) { 2698 rte_errno = errno; 2699 DRV_LOG(WARNING, "%s: \"%s\" is not a valid integer", key, val); 2700 return -rte_errno; 2701 } 2702 if (tmp < 0) { 2703 /* Negative values are acceptable for some keys only. */ 2704 rte_errno = EINVAL; 2705 DRV_LOG(WARNING, "%s: invalid negative value \"%s\"", key, val); 2706 return -rte_errno; 2707 } 2708 if (strcmp(MLX5_RXQ_CQE_COMP_EN, key) == 0) { 2709 if ((tmp & ~MLX5_RXQ_ENH_CQE_COMP_MASK) > 2710 MLX5_CQE_RESP_FORMAT_L34H_STRIDX) { 2711 DRV_LOG(ERR, "invalid CQE compression " 2712 "format parameter"); 2713 rte_errno = EINVAL; 2714 return -rte_errno; 2715 } 2716 config->cqe_comp = !!tmp; 2717 config->cqe_comp_fmt = tmp & ~MLX5_RXQ_ENH_CQE_COMP_MASK; 2718 config->enh_cqe_comp = !!(tmp & MLX5_RXQ_ENH_CQE_COMP_MASK); 2719 } else if (strcmp(MLX5_RXQ_PKT_PAD_EN, key) == 0) { 2720 config->hw_padding = !!tmp; 2721 } else if (strcmp(MLX5_RX_MPRQ_EN, key) == 0) { 2722 config->mprq.enabled = !!tmp; 2723 } else if (strcmp(MLX5_RX_MPRQ_LOG_STRIDE_NUM, key) == 0) { 2724 config->mprq.log_stride_num = tmp; 2725 } else if (strcmp(MLX5_RX_MPRQ_LOG_STRIDE_SIZE, key) == 0) { 2726 config->mprq.log_stride_size = tmp; 2727 } else if (strcmp(MLX5_RX_MPRQ_MAX_MEMCPY_LEN, key) == 0) { 2728 config->mprq.max_memcpy_len = tmp; 2729 } else if (strcmp(MLX5_RXQS_MIN_MPRQ, key) == 0) { 2730 config->mprq.min_rxqs_num = tmp; 2731 } else if (strcmp(MLX5_TXQ_INLINE, key) == 0) { 2732 DRV_LOG(WARNING, "%s: deprecated parameter," 2733 " converted to txq_inline_max", key); 2734 config->txq_inline_max = tmp; 2735 } else if (strcmp(MLX5_TXQ_INLINE_MAX, key) == 0) { 2736 config->txq_inline_max = tmp; 2737 } else if (strcmp(MLX5_TXQ_INLINE_MIN, key) == 0) { 2738 config->txq_inline_min = tmp; 2739 } else if (strcmp(MLX5_TXQ_INLINE_MPW, key) == 0) { 2740 config->txq_inline_mpw = tmp; 2741 } else if (strcmp(MLX5_TXQS_MIN_INLINE, key) == 0) { 2742 config->txqs_inline = tmp; 2743 } else if (strcmp(MLX5_TXQS_MAX_VEC, key) == 0) { 2744 DRV_LOG(WARNING, "%s: deprecated parameter, ignored", key); 2745 } else if (strcmp(MLX5_TXQ_MPW_EN, key) == 0) { 2746 config->mps = !!tmp; 2747 } else if (strcmp(MLX5_TXQ_MPW_HDR_DSEG_EN, key) == 0) { 2748 DRV_LOG(WARNING, "%s: deprecated parameter, ignored", key); 2749 } else if (strcmp(MLX5_TXQ_MAX_INLINE_LEN, key) == 0) { 2750 DRV_LOG(WARNING, "%s: deprecated parameter," 2751 " converted to txq_inline_mpw", key); 2752 config->txq_inline_mpw = tmp; 2753 } else if (strcmp(MLX5_TX_VEC_EN, key) == 0) { 2754 DRV_LOG(WARNING, "%s: deprecated parameter, ignored", key); 2755 } else if (strcmp(MLX5_RX_VEC_EN, key) == 0) { 2756 config->rx_vec_en = !!tmp; 2757 } else if (strcmp(MLX5_MAX_DUMP_FILES_NUM, key) == 0) { 2758 config->max_dump_files_num = tmp; 2759 } else if (strcmp(MLX5_LRO_TIMEOUT_USEC, key) == 0) { 2760 config->lro_timeout = tmp; 2761 } else if (strcmp(MLX5_HP_BUF_SIZE, key) == 0) { 2762 config->log_hp_size = tmp; 2763 } else if (strcmp(MLX5_DELAY_DROP, key) == 0) { 2764 config->std_delay_drop = !!(tmp & MLX5_DELAY_DROP_STANDARD); 2765 config->hp_delay_drop = !!(tmp & MLX5_DELAY_DROP_HAIRPIN); 2766 } 2767 return 0; 2768 } 2769 2770 /** 2771 * Parse user port parameters and adjust them according to device capabilities. 2772 * 2773 * @param priv 2774 * Pointer to shared device context. 2775 * @param mkvlist 2776 * Pointer to mlx5 kvargs control, can be NULL if there is no devargs. 2777 * @param config 2778 * Pointer to port configuration structure. 2779 * 2780 * @return 2781 * 0 on success, a negative errno value otherwise and rte_errno is set. 2782 */ 2783 int 2784 mlx5_port_args_config(struct mlx5_priv *priv, struct mlx5_kvargs_ctrl *mkvlist, 2785 struct mlx5_port_config *config) 2786 { 2787 struct mlx5_hca_attr *hca_attr = &priv->sh->cdev->config.hca_attr; 2788 struct mlx5_dev_cap *dev_cap = &priv->sh->dev_cap; 2789 bool devx = priv->sh->cdev->config.devx; 2790 const char **params = (const char *[]){ 2791 MLX5_RXQ_CQE_COMP_EN, 2792 MLX5_RXQ_PKT_PAD_EN, 2793 MLX5_RX_MPRQ_EN, 2794 MLX5_RX_MPRQ_LOG_STRIDE_NUM, 2795 MLX5_RX_MPRQ_LOG_STRIDE_SIZE, 2796 MLX5_RX_MPRQ_MAX_MEMCPY_LEN, 2797 MLX5_RXQS_MIN_MPRQ, 2798 MLX5_TXQ_INLINE, 2799 MLX5_TXQ_INLINE_MIN, 2800 MLX5_TXQ_INLINE_MAX, 2801 MLX5_TXQ_INLINE_MPW, 2802 MLX5_TXQS_MIN_INLINE, 2803 MLX5_TXQS_MAX_VEC, 2804 MLX5_TXQ_MPW_EN, 2805 MLX5_TXQ_MPW_HDR_DSEG_EN, 2806 MLX5_TXQ_MAX_INLINE_LEN, 2807 MLX5_TX_VEC_EN, 2808 MLX5_RX_VEC_EN, 2809 MLX5_REPRESENTOR, 2810 MLX5_MAX_DUMP_FILES_NUM, 2811 MLX5_LRO_TIMEOUT_USEC, 2812 MLX5_HP_BUF_SIZE, 2813 MLX5_DELAY_DROP, 2814 NULL, 2815 }; 2816 int ret = 0; 2817 2818 /* Default configuration. */ 2819 memset(config, 0, sizeof(*config)); 2820 config->mps = MLX5_ARG_UNSET; 2821 config->cqe_comp = 1; 2822 config->rx_vec_en = 1; 2823 config->txq_inline_max = MLX5_ARG_UNSET; 2824 config->txq_inline_min = MLX5_ARG_UNSET; 2825 config->txq_inline_mpw = MLX5_ARG_UNSET; 2826 config->txqs_inline = MLX5_ARG_UNSET; 2827 config->mprq.max_memcpy_len = MLX5_MPRQ_MEMCPY_DEFAULT_LEN; 2828 config->mprq.min_rxqs_num = MLX5_MPRQ_MIN_RXQS; 2829 config->mprq.log_stride_num = MLX5_MPRQ_DEFAULT_LOG_STRIDE_NUM; 2830 config->mprq.log_stride_size = MLX5_ARG_UNSET; 2831 config->log_hp_size = MLX5_ARG_UNSET; 2832 config->std_delay_drop = 0; 2833 config->hp_delay_drop = 0; 2834 if (mkvlist != NULL) { 2835 /* Process parameters. */ 2836 ret = mlx5_kvargs_process(mkvlist, params, 2837 mlx5_port_args_check_handler, config); 2838 if (ret) { 2839 DRV_LOG(ERR, "Failed to process port arguments: %s", 2840 strerror(rte_errno)); 2841 return -rte_errno; 2842 } 2843 } 2844 /* Adjust parameters according to device capabilities. */ 2845 if (config->hw_padding && !dev_cap->hw_padding) { 2846 DRV_LOG(DEBUG, "Rx end alignment padding isn't supported."); 2847 config->hw_padding = 0; 2848 } else if (config->hw_padding) { 2849 DRV_LOG(DEBUG, "Rx end alignment padding is enabled."); 2850 } 2851 /* 2852 * MPW is disabled by default, while the Enhanced MPW is enabled 2853 * by default. 2854 */ 2855 if (config->mps == MLX5_ARG_UNSET) 2856 config->mps = (dev_cap->mps == MLX5_MPW_ENHANCED) ? 2857 MLX5_MPW_ENHANCED : MLX5_MPW_DISABLED; 2858 else 2859 config->mps = config->mps ? dev_cap->mps : MLX5_MPW_DISABLED; 2860 DRV_LOG(INFO, "%sMPS is %s", 2861 config->mps == MLX5_MPW_ENHANCED ? "enhanced " : 2862 config->mps == MLX5_MPW ? "legacy " : "", 2863 config->mps != MLX5_MPW_DISABLED ? "enabled" : "disabled"); 2864 if (priv->sh->config.lro_allowed) { 2865 /* 2866 * If LRO timeout is not configured by application, 2867 * use the minimal supported value. 2868 */ 2869 if (!config->lro_timeout) 2870 config->lro_timeout = 2871 hca_attr->lro_timer_supported_periods[0]; 2872 DRV_LOG(DEBUG, "LRO session timeout set to %d usec.", 2873 config->lro_timeout); 2874 } 2875 if (config->cqe_comp && !dev_cap->cqe_comp) { 2876 DRV_LOG(WARNING, "Rx CQE 128B compression is not supported."); 2877 config->cqe_comp = 0; 2878 } 2879 if (config->cqe_comp_fmt == MLX5_CQE_RESP_FORMAT_FTAG_STRIDX && 2880 (!devx || !hca_attr->mini_cqe_resp_flow_tag)) { 2881 DRV_LOG(WARNING, 2882 "Flow Tag CQE compression format isn't supported."); 2883 config->cqe_comp = 0; 2884 } 2885 if (config->cqe_comp_fmt == MLX5_CQE_RESP_FORMAT_L34H_STRIDX && 2886 (!devx || !hca_attr->mini_cqe_resp_l3_l4_tag)) { 2887 DRV_LOG(WARNING, 2888 "L3/L4 Header CQE compression format isn't supported."); 2889 config->cqe_comp = 0; 2890 } 2891 if (config->enh_cqe_comp && !hca_attr->enhanced_cqe_compression) { 2892 DRV_LOG(WARNING, 2893 "Enhanced CQE compression isn't supported."); 2894 config->enh_cqe_comp = 0; 2895 } 2896 DRV_LOG(DEBUG, "%sRx CQE compression is %ssupported.", 2897 config->enh_cqe_comp ? "Enhanced " : "", 2898 config->cqe_comp ? "" : "not "); 2899 if ((config->std_delay_drop || config->hp_delay_drop) && 2900 !dev_cap->rq_delay_drop_en) { 2901 config->std_delay_drop = 0; 2902 config->hp_delay_drop = 0; 2903 DRV_LOG(WARNING, "dev_port-%u: Rxq delay drop isn't supported.", 2904 priv->dev_port); 2905 } 2906 if (config->mprq.enabled && !priv->sh->dev_cap.mprq.enabled) { 2907 DRV_LOG(WARNING, "Multi-Packet RQ isn't supported."); 2908 config->mprq.enabled = 0; 2909 } 2910 if (config->max_dump_files_num == 0) 2911 config->max_dump_files_num = 128; 2912 /* Detect minimal data bytes to inline. */ 2913 mlx5_set_min_inline(priv); 2914 DRV_LOG(DEBUG, "VLAN insertion in WQE is %ssupported.", 2915 config->hw_vlan_insert ? "" : "not "); 2916 DRV_LOG(DEBUG, "\"rxq_pkt_pad_en\" is %u.", config->hw_padding); 2917 DRV_LOG(DEBUG, "\"rxq_cqe_comp_en\" is %u.", config->cqe_comp); 2918 DRV_LOG(DEBUG, "\"cqe_comp_fmt\" is %u.", config->cqe_comp_fmt); 2919 DRV_LOG(DEBUG, "\"enh_cqe_comp\" is %u.", config->enh_cqe_comp); 2920 DRV_LOG(DEBUG, "\"rx_vec_en\" is %u.", config->rx_vec_en); 2921 DRV_LOG(DEBUG, "Standard \"delay_drop\" is %u.", 2922 config->std_delay_drop); 2923 DRV_LOG(DEBUG, "Hairpin \"delay_drop\" is %u.", config->hp_delay_drop); 2924 DRV_LOG(DEBUG, "\"max_dump_files_num\" is %u.", 2925 config->max_dump_files_num); 2926 DRV_LOG(DEBUG, "\"log_hp_size\" is %u.", config->log_hp_size); 2927 DRV_LOG(DEBUG, "\"mprq_en\" is %u.", config->mprq.enabled); 2928 DRV_LOG(DEBUG, "\"mprq_log_stride_num\" is %u.", 2929 config->mprq.log_stride_num); 2930 DRV_LOG(DEBUG, "\"mprq_log_stride_size\" is %u.", 2931 config->mprq.log_stride_size); 2932 DRV_LOG(DEBUG, "\"mprq_max_memcpy_len\" is %u.", 2933 config->mprq.max_memcpy_len); 2934 DRV_LOG(DEBUG, "\"rxqs_min_mprq\" is %u.", config->mprq.min_rxqs_num); 2935 DRV_LOG(DEBUG, "\"lro_timeout_usec\" is %u.", config->lro_timeout); 2936 DRV_LOG(DEBUG, "\"txq_mpw_en\" is %d.", config->mps); 2937 DRV_LOG(DEBUG, "\"txqs_min_inline\" is %d.", config->txqs_inline); 2938 DRV_LOG(DEBUG, "\"txq_inline_min\" is %d.", config->txq_inline_min); 2939 DRV_LOG(DEBUG, "\"txq_inline_max\" is %d.", config->txq_inline_max); 2940 DRV_LOG(DEBUG, "\"txq_inline_mpw\" is %d.", config->txq_inline_mpw); 2941 return 0; 2942 } 2943 2944 /** 2945 * Print the key for device argument. 2946 * 2947 * It is "dummy" handler whose whole purpose is to enable using 2948 * mlx5_kvargs_process() function which set devargs as used. 2949 * 2950 * @param key 2951 * Key argument. 2952 * @param val 2953 * Value associated with key, unused. 2954 * @param opaque 2955 * Unused, can be NULL. 2956 * 2957 * @return 2958 * 0 on success, function cannot fail. 2959 */ 2960 static int 2961 mlx5_dummy_handler(const char *key, const char *val, void *opaque) 2962 { 2963 DRV_LOG(DEBUG, "\tKey: \"%s\" is set as used.", key); 2964 RTE_SET_USED(opaque); 2965 RTE_SET_USED(val); 2966 return 0; 2967 } 2968 2969 /** 2970 * Set requested devargs as used when device is already spawned. 2971 * 2972 * It is necessary since it is valid to ask probe again for existing device, 2973 * if its devargs don't assign as used, mlx5_kvargs_validate() will fail. 2974 * 2975 * @param name 2976 * Name of the existing device. 2977 * @param port_id 2978 * Port identifier of the device. 2979 * @param mkvlist 2980 * Pointer to mlx5 kvargs control to sign as used. 2981 */ 2982 void 2983 mlx5_port_args_set_used(const char *name, uint16_t port_id, 2984 struct mlx5_kvargs_ctrl *mkvlist) 2985 { 2986 const char **params = (const char *[]){ 2987 MLX5_RXQ_CQE_COMP_EN, 2988 MLX5_RXQ_PKT_PAD_EN, 2989 MLX5_RX_MPRQ_EN, 2990 MLX5_RX_MPRQ_LOG_STRIDE_NUM, 2991 MLX5_RX_MPRQ_LOG_STRIDE_SIZE, 2992 MLX5_RX_MPRQ_MAX_MEMCPY_LEN, 2993 MLX5_RXQS_MIN_MPRQ, 2994 MLX5_TXQ_INLINE, 2995 MLX5_TXQ_INLINE_MIN, 2996 MLX5_TXQ_INLINE_MAX, 2997 MLX5_TXQ_INLINE_MPW, 2998 MLX5_TXQS_MIN_INLINE, 2999 MLX5_TXQS_MAX_VEC, 3000 MLX5_TXQ_MPW_EN, 3001 MLX5_TXQ_MPW_HDR_DSEG_EN, 3002 MLX5_TXQ_MAX_INLINE_LEN, 3003 MLX5_TX_VEC_EN, 3004 MLX5_RX_VEC_EN, 3005 MLX5_REPRESENTOR, 3006 MLX5_MAX_DUMP_FILES_NUM, 3007 MLX5_LRO_TIMEOUT_USEC, 3008 MLX5_HP_BUF_SIZE, 3009 MLX5_DELAY_DROP, 3010 NULL, 3011 }; 3012 3013 /* Secondary process should not handle devargs. */ 3014 if (rte_eal_process_type() != RTE_PROC_PRIMARY) 3015 return; 3016 MLX5_ASSERT(mkvlist != NULL); 3017 DRV_LOG(DEBUG, "Ethernet device \"%s\" for port %u " 3018 "already exists, set devargs as used:", name, port_id); 3019 /* This function cannot fail with this handler. */ 3020 mlx5_kvargs_process(mkvlist, params, mlx5_dummy_handler, NULL); 3021 } 3022 3023 /** 3024 * Check sibling device configurations when probing again. 3025 * 3026 * Sibling devices sharing infiniband device context should have compatible 3027 * configurations. This regards representors and bonding device. 3028 * 3029 * @param cdev 3030 * Pointer to mlx5 device structure. 3031 * @param mkvlist 3032 * Pointer to mlx5 kvargs control, can be NULL if there is no devargs. 3033 * 3034 * @return 3035 * 0 on success, a negative errno value otherwise and rte_errno is set. 3036 */ 3037 int 3038 mlx5_probe_again_args_validate(struct mlx5_common_device *cdev, 3039 struct mlx5_kvargs_ctrl *mkvlist) 3040 { 3041 struct mlx5_dev_ctx_shared *sh = NULL; 3042 struct mlx5_sh_config *config; 3043 int ret; 3044 3045 /* Secondary process should not handle devargs. */ 3046 if (rte_eal_process_type() != RTE_PROC_PRIMARY) 3047 return 0; 3048 pthread_mutex_lock(&mlx5_dev_ctx_list_mutex); 3049 /* Search for IB context by common device pointer. */ 3050 LIST_FOREACH(sh, &dev_ctx_list, next) 3051 if (sh->cdev == cdev) 3052 break; 3053 pthread_mutex_unlock(&mlx5_dev_ctx_list_mutex); 3054 /* There is sh for this device -> it isn't probe again. */ 3055 if (sh == NULL) 3056 return 0; 3057 config = mlx5_malloc(MLX5_MEM_ZERO | MLX5_MEM_RTE, 3058 sizeof(struct mlx5_sh_config), 3059 RTE_CACHE_LINE_SIZE, SOCKET_ID_ANY); 3060 if (config == NULL) { 3061 rte_errno = -ENOMEM; 3062 return -rte_errno; 3063 } 3064 /* 3065 * Creates a temporary IB context configure structure according to new 3066 * devargs attached in probing again. 3067 */ 3068 ret = mlx5_shared_dev_ctx_args_config(sh, mkvlist, config); 3069 if (ret) { 3070 DRV_LOG(ERR, "Failed to process device configure: %s", 3071 strerror(rte_errno)); 3072 mlx5_free(config); 3073 return ret; 3074 } 3075 /* 3076 * Checks the match between the temporary structure and the existing 3077 * IB context structure. 3078 */ 3079 if (sh->config.dv_flow_en ^ config->dv_flow_en) { 3080 DRV_LOG(ERR, "\"dv_flow_en\" " 3081 "configuration mismatch for shared %s context.", 3082 sh->ibdev_name); 3083 goto error; 3084 } 3085 if ((sh->config.dv_xmeta_en ^ config->dv_xmeta_en) || 3086 (sh->config.dv_miss_info ^ config->dv_miss_info)) { 3087 DRV_LOG(ERR, "\"dv_xmeta_en\" " 3088 "configuration mismatch for shared %s context.", 3089 sh->ibdev_name); 3090 goto error; 3091 } 3092 if (sh->config.dv_esw_en ^ config->dv_esw_en) { 3093 DRV_LOG(ERR, "\"dv_esw_en\" " 3094 "configuration mismatch for shared %s context.", 3095 sh->ibdev_name); 3096 goto error; 3097 } 3098 if (sh->config.reclaim_mode ^ config->reclaim_mode) { 3099 DRV_LOG(ERR, "\"reclaim_mode\" " 3100 "configuration mismatch for shared %s context.", 3101 sh->ibdev_name); 3102 goto error; 3103 } 3104 if (sh->config.allow_duplicate_pattern ^ 3105 config->allow_duplicate_pattern) { 3106 DRV_LOG(ERR, "\"allow_duplicate_pattern\" " 3107 "configuration mismatch for shared %s context.", 3108 sh->ibdev_name); 3109 goto error; 3110 } 3111 if (sh->config.fdb_def_rule ^ config->fdb_def_rule) { 3112 DRV_LOG(ERR, "\"fdb_def_rule_en\" configuration mismatch for shared %s context.", 3113 sh->ibdev_name); 3114 goto error; 3115 } 3116 if (sh->config.l3_vxlan_en ^ config->l3_vxlan_en) { 3117 DRV_LOG(ERR, "\"l3_vxlan_en\" " 3118 "configuration mismatch for shared %s context.", 3119 sh->ibdev_name); 3120 goto error; 3121 } 3122 if (sh->config.decap_en ^ config->decap_en) { 3123 DRV_LOG(ERR, "\"decap_en\" " 3124 "configuration mismatch for shared %s context.", 3125 sh->ibdev_name); 3126 goto error; 3127 } 3128 if (sh->config.lacp_by_user ^ config->lacp_by_user) { 3129 DRV_LOG(ERR, "\"lacp_by_user\" " 3130 "configuration mismatch for shared %s context.", 3131 sh->ibdev_name); 3132 goto error; 3133 } 3134 if (sh->config.tx_pp ^ config->tx_pp) { 3135 DRV_LOG(ERR, "\"tx_pp\" " 3136 "configuration mismatch for shared %s context.", 3137 sh->ibdev_name); 3138 goto error; 3139 } 3140 if (sh->config.tx_skew ^ config->tx_skew) { 3141 DRV_LOG(ERR, "\"tx_skew\" " 3142 "configuration mismatch for shared %s context.", 3143 sh->ibdev_name); 3144 goto error; 3145 } 3146 mlx5_free(config); 3147 return 0; 3148 error: 3149 mlx5_free(config); 3150 rte_errno = EINVAL; 3151 return -rte_errno; 3152 } 3153 3154 /** 3155 * Configures the minimal amount of data to inline into WQE 3156 * while sending packets. 3157 * 3158 * - the txq_inline_min has the maximal priority, if this 3159 * key is specified in devargs 3160 * - if DevX is enabled the inline mode is queried from the 3161 * device (HCA attributes and NIC vport context if needed). 3162 * - otherwise L2 mode (18 bytes) is assumed for ConnectX-4/4 Lx 3163 * and none (0 bytes) for other NICs 3164 * 3165 * @param priv 3166 * Pointer to the private device data structure. 3167 */ 3168 void 3169 mlx5_set_min_inline(struct mlx5_priv *priv) 3170 { 3171 struct mlx5_hca_attr *hca_attr = &priv->sh->cdev->config.hca_attr; 3172 struct mlx5_port_config *config = &priv->config; 3173 3174 if (config->txq_inline_min != MLX5_ARG_UNSET) { 3175 /* Application defines size of inlined data explicitly. */ 3176 if (priv->pci_dev != NULL) { 3177 switch (priv->pci_dev->id.device_id) { 3178 case PCI_DEVICE_ID_MELLANOX_CONNECTX4: 3179 case PCI_DEVICE_ID_MELLANOX_CONNECTX4VF: 3180 if (config->txq_inline_min < 3181 (int)MLX5_INLINE_HSIZE_L2) { 3182 DRV_LOG(DEBUG, 3183 "txq_inline_mix aligned to minimal ConnectX-4 required value %d", 3184 (int)MLX5_INLINE_HSIZE_L2); 3185 config->txq_inline_min = 3186 MLX5_INLINE_HSIZE_L2; 3187 } 3188 break; 3189 } 3190 } 3191 goto exit; 3192 } 3193 if (hca_attr->eth_net_offloads) { 3194 /* We have DevX enabled, inline mode queried successfully. */ 3195 switch (hca_attr->wqe_inline_mode) { 3196 case MLX5_CAP_INLINE_MODE_L2: 3197 /* outer L2 header must be inlined. */ 3198 config->txq_inline_min = MLX5_INLINE_HSIZE_L2; 3199 goto exit; 3200 case MLX5_CAP_INLINE_MODE_NOT_REQUIRED: 3201 /* No inline data are required by NIC. */ 3202 config->txq_inline_min = MLX5_INLINE_HSIZE_NONE; 3203 config->hw_vlan_insert = 3204 hca_attr->wqe_vlan_insert; 3205 DRV_LOG(DEBUG, "Tx VLAN insertion is supported"); 3206 goto exit; 3207 case MLX5_CAP_INLINE_MODE_VPORT_CONTEXT: 3208 /* inline mode is defined by NIC vport context. */ 3209 if (!hca_attr->eth_virt) 3210 break; 3211 switch (hca_attr->vport_inline_mode) { 3212 case MLX5_INLINE_MODE_NONE: 3213 config->txq_inline_min = 3214 MLX5_INLINE_HSIZE_NONE; 3215 goto exit; 3216 case MLX5_INLINE_MODE_L2: 3217 config->txq_inline_min = 3218 MLX5_INLINE_HSIZE_L2; 3219 goto exit; 3220 case MLX5_INLINE_MODE_IP: 3221 config->txq_inline_min = 3222 MLX5_INLINE_HSIZE_L3; 3223 goto exit; 3224 case MLX5_INLINE_MODE_TCP_UDP: 3225 config->txq_inline_min = 3226 MLX5_INLINE_HSIZE_L4; 3227 goto exit; 3228 case MLX5_INLINE_MODE_INNER_L2: 3229 config->txq_inline_min = 3230 MLX5_INLINE_HSIZE_INNER_L2; 3231 goto exit; 3232 case MLX5_INLINE_MODE_INNER_IP: 3233 config->txq_inline_min = 3234 MLX5_INLINE_HSIZE_INNER_L3; 3235 goto exit; 3236 case MLX5_INLINE_MODE_INNER_TCP_UDP: 3237 config->txq_inline_min = 3238 MLX5_INLINE_HSIZE_INNER_L4; 3239 goto exit; 3240 } 3241 } 3242 } 3243 if (priv->pci_dev == NULL) { 3244 config->txq_inline_min = MLX5_INLINE_HSIZE_NONE; 3245 goto exit; 3246 } 3247 /* 3248 * We get here if we are unable to deduce 3249 * inline data size with DevX. Try PCI ID 3250 * to determine old NICs. 3251 */ 3252 switch (priv->pci_dev->id.device_id) { 3253 case PCI_DEVICE_ID_MELLANOX_CONNECTX4: 3254 case PCI_DEVICE_ID_MELLANOX_CONNECTX4VF: 3255 case PCI_DEVICE_ID_MELLANOX_CONNECTX4LX: 3256 case PCI_DEVICE_ID_MELLANOX_CONNECTX4LXVF: 3257 config->txq_inline_min = MLX5_INLINE_HSIZE_L2; 3258 config->hw_vlan_insert = 0; 3259 break; 3260 case PCI_DEVICE_ID_MELLANOX_CONNECTX5: 3261 case PCI_DEVICE_ID_MELLANOX_CONNECTX5VF: 3262 case PCI_DEVICE_ID_MELLANOX_CONNECTX5EX: 3263 case PCI_DEVICE_ID_MELLANOX_CONNECTX5EXVF: 3264 /* 3265 * These NICs support VLAN insertion from WQE and 3266 * report the wqe_vlan_insert flag. But there is the bug 3267 * and PFC control may be broken, so disable feature. 3268 */ 3269 config->hw_vlan_insert = 0; 3270 config->txq_inline_min = MLX5_INLINE_HSIZE_NONE; 3271 break; 3272 default: 3273 config->txq_inline_min = MLX5_INLINE_HSIZE_NONE; 3274 break; 3275 } 3276 exit: 3277 DRV_LOG(DEBUG, "min tx inline configured: %d", config->txq_inline_min); 3278 } 3279 3280 /** 3281 * Configures the metadata mask fields in the shared context. 3282 * 3283 * @param [in] dev 3284 * Pointer to Ethernet device. 3285 */ 3286 void 3287 mlx5_set_metadata_mask(struct rte_eth_dev *dev) 3288 { 3289 struct mlx5_priv *priv = dev->data->dev_private; 3290 struct mlx5_dev_ctx_shared *sh = priv->sh; 3291 uint32_t meta, mark, reg_c0; 3292 3293 reg_c0 = ~priv->vport_meta_mask; 3294 switch (sh->config.dv_xmeta_en) { 3295 case MLX5_XMETA_MODE_LEGACY: 3296 meta = UINT32_MAX; 3297 mark = MLX5_FLOW_MARK_MASK; 3298 break; 3299 case MLX5_XMETA_MODE_META16: 3300 meta = reg_c0 >> rte_bsf32(reg_c0); 3301 mark = MLX5_FLOW_MARK_MASK; 3302 break; 3303 case MLX5_XMETA_MODE_META32: 3304 meta = UINT32_MAX; 3305 mark = (reg_c0 >> rte_bsf32(reg_c0)) & MLX5_FLOW_MARK_MASK; 3306 break; 3307 case MLX5_XMETA_MODE_META32_HWS: 3308 meta = UINT32_MAX; 3309 mark = (reg_c0 >> rte_bsf32(reg_c0)) & MLX5_FLOW_MARK_MASK; 3310 break; 3311 default: 3312 meta = 0; 3313 mark = 0; 3314 MLX5_ASSERT(false); 3315 break; 3316 } 3317 if (sh->dv_mark_mask && sh->dv_mark_mask != mark) 3318 DRV_LOG(WARNING, "metadata MARK mask mismatch %08X:%08X", 3319 sh->dv_mark_mask, mark); 3320 else 3321 sh->dv_mark_mask = mark; 3322 if (sh->dv_meta_mask && sh->dv_meta_mask != meta) 3323 DRV_LOG(WARNING, "metadata META mask mismatch %08X:%08X", 3324 sh->dv_meta_mask, meta); 3325 else 3326 sh->dv_meta_mask = meta; 3327 if (sh->dv_regc0_mask && sh->dv_regc0_mask != reg_c0) 3328 DRV_LOG(WARNING, "metadata reg_c0 mask mismatch %08X:%08X", 3329 sh->dv_meta_mask, reg_c0); 3330 else 3331 sh->dv_regc0_mask = reg_c0; 3332 DRV_LOG(DEBUG, "metadata mode %u", sh->config.dv_xmeta_en); 3333 DRV_LOG(DEBUG, "metadata MARK mask %08X", sh->dv_mark_mask); 3334 DRV_LOG(DEBUG, "metadata META mask %08X", sh->dv_meta_mask); 3335 DRV_LOG(DEBUG, "metadata reg_c0 mask %08X", sh->dv_regc0_mask); 3336 } 3337 3338 int 3339 rte_pmd_mlx5_get_dyn_flag_names(char *names[], unsigned int n) 3340 { 3341 static const char *const dynf_names[] = { 3342 RTE_PMD_MLX5_FINE_GRANULARITY_INLINE, 3343 RTE_MBUF_DYNFLAG_METADATA_NAME, 3344 RTE_MBUF_DYNFLAG_TX_TIMESTAMP_NAME 3345 }; 3346 unsigned int i; 3347 3348 if (n < RTE_DIM(dynf_names)) 3349 return -ENOMEM; 3350 for (i = 0; i < RTE_DIM(dynf_names); i++) { 3351 if (names[i] == NULL) 3352 return -EINVAL; 3353 strcpy(names[i], dynf_names[i]); 3354 } 3355 return RTE_DIM(dynf_names); 3356 } 3357 3358 /** 3359 * Look for the ethernet device belonging to mlx5 driver. 3360 * 3361 * @param[in] port_id 3362 * port_id to start looking for device. 3363 * @param[in] odev 3364 * Pointer to the hint device. When device is being probed 3365 * the its siblings (master and preceding representors might 3366 * not have assigned driver yet (because the mlx5_os_pci_probe() 3367 * is not completed yet, for this case match on hint 3368 * device may be used to detect sibling device. 3369 * 3370 * @return 3371 * port_id of found device, RTE_MAX_ETHPORT if not found. 3372 */ 3373 uint16_t 3374 mlx5_eth_find_next(uint16_t port_id, struct rte_device *odev) 3375 { 3376 while (port_id < RTE_MAX_ETHPORTS) { 3377 struct rte_eth_dev *dev = &rte_eth_devices[port_id]; 3378 3379 if (dev->state != RTE_ETH_DEV_UNUSED && 3380 dev->device && 3381 (dev->device == odev || 3382 (dev->device->driver && 3383 dev->device->driver->name && 3384 ((strcmp(dev->device->driver->name, 3385 MLX5_PCI_DRIVER_NAME) == 0) || 3386 (strcmp(dev->device->driver->name, 3387 MLX5_AUXILIARY_DRIVER_NAME) == 0))))) 3388 break; 3389 port_id++; 3390 } 3391 if (port_id >= RTE_MAX_ETHPORTS) 3392 return RTE_MAX_ETHPORTS; 3393 return port_id; 3394 } 3395 3396 /** 3397 * Callback to remove a device. 3398 * 3399 * This function removes all Ethernet devices belong to a given device. 3400 * 3401 * @param[in] cdev 3402 * Pointer to the generic device. 3403 * 3404 * @return 3405 * 0 on success, the function cannot fail. 3406 */ 3407 int 3408 mlx5_net_remove(struct mlx5_common_device *cdev) 3409 { 3410 uint16_t port_id; 3411 int ret = 0; 3412 3413 RTE_ETH_FOREACH_DEV_OF(port_id, cdev->dev) { 3414 /* 3415 * mlx5_dev_close() is not registered to secondary process, 3416 * call the close function explicitly for secondary process. 3417 */ 3418 if (rte_eal_process_type() == RTE_PROC_SECONDARY) 3419 ret |= mlx5_dev_close(&rte_eth_devices[port_id]); 3420 else 3421 ret |= rte_eth_dev_close(port_id); 3422 } 3423 return ret == 0 ? 0 : -EIO; 3424 } 3425 3426 static const struct rte_pci_id mlx5_pci_id_map[] = { 3427 { 3428 RTE_PCI_DEVICE(PCI_VENDOR_ID_MELLANOX, 3429 PCI_DEVICE_ID_MELLANOX_CONNECTX4) 3430 }, 3431 { 3432 RTE_PCI_DEVICE(PCI_VENDOR_ID_MELLANOX, 3433 PCI_DEVICE_ID_MELLANOX_CONNECTX4VF) 3434 }, 3435 { 3436 RTE_PCI_DEVICE(PCI_VENDOR_ID_MELLANOX, 3437 PCI_DEVICE_ID_MELLANOX_CONNECTX4LX) 3438 }, 3439 { 3440 RTE_PCI_DEVICE(PCI_VENDOR_ID_MELLANOX, 3441 PCI_DEVICE_ID_MELLANOX_CONNECTX4LXVF) 3442 }, 3443 { 3444 RTE_PCI_DEVICE(PCI_VENDOR_ID_MELLANOX, 3445 PCI_DEVICE_ID_MELLANOX_CONNECTX5) 3446 }, 3447 { 3448 RTE_PCI_DEVICE(PCI_VENDOR_ID_MELLANOX, 3449 PCI_DEVICE_ID_MELLANOX_CONNECTX5VF) 3450 }, 3451 { 3452 RTE_PCI_DEVICE(PCI_VENDOR_ID_MELLANOX, 3453 PCI_DEVICE_ID_MELLANOX_CONNECTX5EX) 3454 }, 3455 { 3456 RTE_PCI_DEVICE(PCI_VENDOR_ID_MELLANOX, 3457 PCI_DEVICE_ID_MELLANOX_CONNECTX5EXVF) 3458 }, 3459 { 3460 RTE_PCI_DEVICE(PCI_VENDOR_ID_MELLANOX, 3461 PCI_DEVICE_ID_MELLANOX_BLUEFIELD) 3462 }, 3463 { 3464 RTE_PCI_DEVICE(PCI_VENDOR_ID_MELLANOX, 3465 PCI_DEVICE_ID_MELLANOX_BLUEFIELDVF) 3466 }, 3467 { 3468 RTE_PCI_DEVICE(PCI_VENDOR_ID_MELLANOX, 3469 PCI_DEVICE_ID_MELLANOX_CONNECTX6) 3470 }, 3471 { 3472 RTE_PCI_DEVICE(PCI_VENDOR_ID_MELLANOX, 3473 PCI_DEVICE_ID_MELLANOX_CONNECTX6VF) 3474 }, 3475 { 3476 RTE_PCI_DEVICE(PCI_VENDOR_ID_MELLANOX, 3477 PCI_DEVICE_ID_MELLANOX_CONNECTX6DX) 3478 }, 3479 { 3480 RTE_PCI_DEVICE(PCI_VENDOR_ID_MELLANOX, 3481 PCI_DEVICE_ID_MELLANOX_CONNECTXVF) 3482 }, 3483 { 3484 RTE_PCI_DEVICE(PCI_VENDOR_ID_MELLANOX, 3485 PCI_DEVICE_ID_MELLANOX_BLUEFIELD2) 3486 }, 3487 { 3488 RTE_PCI_DEVICE(PCI_VENDOR_ID_MELLANOX, 3489 PCI_DEVICE_ID_MELLANOX_CONNECTX6LX) 3490 }, 3491 { 3492 RTE_PCI_DEVICE(PCI_VENDOR_ID_MELLANOX, 3493 PCI_DEVICE_ID_MELLANOX_CONNECTX7) 3494 }, 3495 { 3496 RTE_PCI_DEVICE(PCI_VENDOR_ID_MELLANOX, 3497 PCI_DEVICE_ID_MELLANOX_BLUEFIELD3) 3498 }, 3499 { 3500 .vendor_id = 0 3501 } 3502 }; 3503 3504 static struct mlx5_class_driver mlx5_net_driver = { 3505 .drv_class = MLX5_CLASS_ETH, 3506 .name = RTE_STR(MLX5_ETH_DRIVER_NAME), 3507 .id_table = mlx5_pci_id_map, 3508 .probe = mlx5_os_net_probe, 3509 .remove = mlx5_net_remove, 3510 .probe_again = 1, 3511 .intr_lsc = 1, 3512 .intr_rmv = 1, 3513 }; 3514 3515 /* Initialize driver log type. */ 3516 RTE_LOG_REGISTER_DEFAULT(mlx5_logtype, NOTICE) 3517 3518 /** 3519 * Driver initialization routine. 3520 */ 3521 RTE_INIT(rte_mlx5_pmd_init) 3522 { 3523 pthread_mutex_init(&mlx5_dev_ctx_list_mutex, NULL); 3524 mlx5_common_init(); 3525 /* Build the static tables for Verbs conversion. */ 3526 mlx5_set_ptype_table(); 3527 mlx5_set_cksum_table(); 3528 mlx5_set_swp_types_table(); 3529 if (mlx5_glue) 3530 mlx5_class_driver_register(&mlx5_net_driver); 3531 } 3532 3533 RTE_PMD_EXPORT_NAME(MLX5_ETH_DRIVER_NAME, __COUNTER__); 3534 RTE_PMD_REGISTER_PCI_TABLE(MLX5_ETH_DRIVER_NAME, mlx5_pci_id_map); 3535 RTE_PMD_REGISTER_KMOD_DEP(MLX5_ETH_DRIVER_NAME, "* ib_uverbs & mlx5_core & mlx5_ib"); 3536