1 /* SPDX-License-Identifier: BSD-3-Clause 2 * Copyright 2015 6WIND S.A. 3 * Copyright 2015 Mellanox Technologies, Ltd 4 */ 5 6 #include <stddef.h> 7 #include <unistd.h> 8 #include <string.h> 9 #include <stdint.h> 10 #include <stdlib.h> 11 #include <errno.h> 12 #include <net/if.h> 13 #include <sys/mman.h> 14 #include <linux/rtnetlink.h> 15 16 /* Verbs header. */ 17 /* ISO C doesn't support unnamed structs/unions, disabling -pedantic. */ 18 #ifdef PEDANTIC 19 #pragma GCC diagnostic ignored "-Wpedantic" 20 #endif 21 #include <infiniband/verbs.h> 22 #ifdef PEDANTIC 23 #pragma GCC diagnostic error "-Wpedantic" 24 #endif 25 26 #include <rte_malloc.h> 27 #include <rte_ethdev_driver.h> 28 #include <rte_ethdev_pci.h> 29 #include <rte_pci.h> 30 #include <rte_bus_pci.h> 31 #include <rte_common.h> 32 #include <rte_kvargs.h> 33 #include <rte_rwlock.h> 34 #include <rte_spinlock.h> 35 #include <rte_string_fns.h> 36 #include <rte_alarm.h> 37 38 #include <mlx5_glue.h> 39 #include <mlx5_devx_cmds.h> 40 #include <mlx5_common.h> 41 #include <mlx5_common_mp.h> 42 43 #include "mlx5_defs.h" 44 #include "mlx5.h" 45 #include "mlx5_utils.h" 46 #include "mlx5_rxtx.h" 47 #include "mlx5_autoconf.h" 48 #include "mlx5_mr.h" 49 #include "mlx5_flow.h" 50 #include "rte_pmd_mlx5.h" 51 52 /* Device parameter to enable RX completion queue compression. */ 53 #define MLX5_RXQ_CQE_COMP_EN "rxq_cqe_comp_en" 54 55 /* Device parameter to enable RX completion entry padding to 128B. */ 56 #define MLX5_RXQ_CQE_PAD_EN "rxq_cqe_pad_en" 57 58 /* Device parameter to enable padding Rx packet to cacheline size. */ 59 #define MLX5_RXQ_PKT_PAD_EN "rxq_pkt_pad_en" 60 61 /* Device parameter to enable Multi-Packet Rx queue. */ 62 #define MLX5_RX_MPRQ_EN "mprq_en" 63 64 /* Device parameter to configure log 2 of the number of strides for MPRQ. */ 65 #define MLX5_RX_MPRQ_LOG_STRIDE_NUM "mprq_log_stride_num" 66 67 /* Device parameter to configure log 2 of the stride size for MPRQ. */ 68 #define MLX5_RX_MPRQ_LOG_STRIDE_SIZE "mprq_log_stride_size" 69 70 /* Device parameter to limit the size of memcpy'd packet for MPRQ. */ 71 #define MLX5_RX_MPRQ_MAX_MEMCPY_LEN "mprq_max_memcpy_len" 72 73 /* Device parameter to set the minimum number of Rx queues to enable MPRQ. */ 74 #define MLX5_RXQS_MIN_MPRQ "rxqs_min_mprq" 75 76 /* Device parameter to configure inline send. Deprecated, ignored.*/ 77 #define MLX5_TXQ_INLINE "txq_inline" 78 79 /* Device parameter to limit packet size to inline with ordinary SEND. */ 80 #define MLX5_TXQ_INLINE_MAX "txq_inline_max" 81 82 /* Device parameter to configure minimal data size to inline. */ 83 #define MLX5_TXQ_INLINE_MIN "txq_inline_min" 84 85 /* Device parameter to limit packet size to inline with Enhanced MPW. */ 86 #define MLX5_TXQ_INLINE_MPW "txq_inline_mpw" 87 88 /* 89 * Device parameter to configure the number of TX queues threshold for 90 * enabling inline send. 91 */ 92 #define MLX5_TXQS_MIN_INLINE "txqs_min_inline" 93 94 /* 95 * Device parameter to configure the number of TX queues threshold for 96 * enabling vectorized Tx, deprecated, ignored (no vectorized Tx routines). 97 */ 98 #define MLX5_TXQS_MAX_VEC "txqs_max_vec" 99 100 /* Device parameter to enable multi-packet send WQEs. */ 101 #define MLX5_TXQ_MPW_EN "txq_mpw_en" 102 103 /* 104 * Device parameter to force doorbell register mapping 105 * to non-cahed region eliminating the extra write memory barrier. 106 */ 107 #define MLX5_TX_DB_NC "tx_db_nc" 108 109 /* 110 * Device parameter to include 2 dsegs in the title WQEBB. 111 * Deprecated, ignored. 112 */ 113 #define MLX5_TXQ_MPW_HDR_DSEG_EN "txq_mpw_hdr_dseg_en" 114 115 /* 116 * Device parameter to limit the size of inlining packet. 117 * Deprecated, ignored. 118 */ 119 #define MLX5_TXQ_MAX_INLINE_LEN "txq_max_inline_len" 120 121 /* 122 * Device parameter to enable hardware Tx vector. 123 * Deprecated, ignored (no vectorized Tx routines anymore). 124 */ 125 #define MLX5_TX_VEC_EN "tx_vec_en" 126 127 /* Device parameter to enable hardware Rx vector. */ 128 #define MLX5_RX_VEC_EN "rx_vec_en" 129 130 /* Allow L3 VXLAN flow creation. */ 131 #define MLX5_L3_VXLAN_EN "l3_vxlan_en" 132 133 /* Activate DV E-Switch flow steering. */ 134 #define MLX5_DV_ESW_EN "dv_esw_en" 135 136 /* Activate DV flow steering. */ 137 #define MLX5_DV_FLOW_EN "dv_flow_en" 138 139 /* Enable extensive flow metadata support. */ 140 #define MLX5_DV_XMETA_EN "dv_xmeta_en" 141 142 /* Activate Netlink support in VF mode. */ 143 #define MLX5_VF_NL_EN "vf_nl_en" 144 145 /* Enable extending memsegs when creating a MR. */ 146 #define MLX5_MR_EXT_MEMSEG_EN "mr_ext_memseg_en" 147 148 /* Select port representors to instantiate. */ 149 #define MLX5_REPRESENTOR "representor" 150 151 /* Device parameter to configure the maximum number of dump files per queue. */ 152 #define MLX5_MAX_DUMP_FILES_NUM "max_dump_files_num" 153 154 /* Configure timeout of LRO session (in microseconds). */ 155 #define MLX5_LRO_TIMEOUT_USEC "lro_timeout_usec" 156 157 /* 158 * Device parameter to configure the total data buffer size for a single 159 * hairpin queue (logarithm value). 160 */ 161 #define MLX5_HP_BUF_SIZE "hp_buf_log_sz" 162 163 #ifndef HAVE_IBV_MLX5_MOD_MPW 164 #define MLX5DV_CONTEXT_FLAGS_MPW_ALLOWED (1 << 2) 165 #define MLX5DV_CONTEXT_FLAGS_ENHANCED_MPW (1 << 3) 166 #endif 167 168 #ifndef HAVE_IBV_MLX5_MOD_CQE_128B_COMP 169 #define MLX5DV_CONTEXT_FLAGS_CQE_128B_COMP (1 << 4) 170 #endif 171 172 static const char *MZ_MLX5_PMD_SHARED_DATA = "mlx5_pmd_shared_data"; 173 174 /* Shared memory between primary and secondary processes. */ 175 struct mlx5_shared_data *mlx5_shared_data; 176 177 /* Spinlock for mlx5_shared_data allocation. */ 178 static rte_spinlock_t mlx5_shared_data_lock = RTE_SPINLOCK_INITIALIZER; 179 180 /* Process local data for secondary processes. */ 181 static struct mlx5_local_data mlx5_local_data; 182 183 /** Driver-specific log messages type. */ 184 int mlx5_logtype; 185 186 /** Data associated with devices to spawn. */ 187 struct mlx5_dev_spawn_data { 188 uint32_t ifindex; /**< Network interface index. */ 189 uint32_t max_port; /**< IB device maximal port index. */ 190 uint32_t ibv_port; /**< IB device physical port index. */ 191 int pf_bond; /**< bonding device PF index. < 0 - no bonding */ 192 struct mlx5_switch_info info; /**< Switch information. */ 193 struct ibv_device *ibv_dev; /**< Associated IB device. */ 194 struct rte_eth_dev *eth_dev; /**< Associated Ethernet device. */ 195 struct rte_pci_device *pci_dev; /**< Backend PCI device. */ 196 }; 197 198 static LIST_HEAD(, mlx5_ibv_shared) mlx5_ibv_list = LIST_HEAD_INITIALIZER(); 199 static pthread_mutex_t mlx5_ibv_list_mutex = PTHREAD_MUTEX_INITIALIZER; 200 201 static struct mlx5_indexed_pool_config mlx5_ipool_cfg[] = { 202 #ifdef HAVE_IBV_FLOW_DV_SUPPORT 203 { 204 .size = sizeof(struct mlx5_flow_dv_encap_decap_resource), 205 .trunk_size = 64, 206 .grow_trunk = 3, 207 .grow_shift = 2, 208 .need_lock = 0, 209 .release_mem_en = 1, 210 .malloc = rte_malloc_socket, 211 .free = rte_free, 212 .type = "mlx5_encap_decap_ipool", 213 }, 214 { 215 .size = sizeof(struct mlx5_flow_dv_push_vlan_action_resource), 216 .trunk_size = 64, 217 .grow_trunk = 3, 218 .grow_shift = 2, 219 .need_lock = 0, 220 .release_mem_en = 1, 221 .malloc = rte_malloc_socket, 222 .free = rte_free, 223 .type = "mlx5_push_vlan_ipool", 224 }, 225 { 226 .size = sizeof(struct mlx5_flow_dv_tag_resource), 227 .trunk_size = 64, 228 .grow_trunk = 3, 229 .grow_shift = 2, 230 .need_lock = 0, 231 .release_mem_en = 1, 232 .malloc = rte_malloc_socket, 233 .free = rte_free, 234 .type = "mlx5_tag_ipool", 235 }, 236 { 237 .size = sizeof(struct mlx5_flow_dv_port_id_action_resource), 238 .trunk_size = 64, 239 .grow_trunk = 3, 240 .grow_shift = 2, 241 .need_lock = 0, 242 .release_mem_en = 1, 243 .malloc = rte_malloc_socket, 244 .free = rte_free, 245 .type = "mlx5_port_id_ipool", 246 }, 247 { 248 .size = sizeof(struct mlx5_flow_tbl_data_entry), 249 .trunk_size = 64, 250 .grow_trunk = 3, 251 .grow_shift = 2, 252 .need_lock = 0, 253 .release_mem_en = 1, 254 .malloc = rte_malloc_socket, 255 .free = rte_free, 256 .type = "mlx5_jump_ipool", 257 }, 258 #endif 259 { 260 .size = sizeof(struct mlx5_flow_meter), 261 .trunk_size = 64, 262 .grow_trunk = 3, 263 .grow_shift = 2, 264 .need_lock = 0, 265 .release_mem_en = 1, 266 .malloc = rte_malloc_socket, 267 .free = rte_free, 268 .type = "mlx5_meter_ipool", 269 }, 270 { 271 .size = sizeof(struct mlx5_flow_mreg_copy_resource), 272 .trunk_size = 64, 273 .grow_trunk = 3, 274 .grow_shift = 2, 275 .need_lock = 0, 276 .release_mem_en = 1, 277 .malloc = rte_malloc_socket, 278 .free = rte_free, 279 .type = "mlx5_mcp_ipool", 280 }, 281 { 282 .size = (sizeof(struct mlx5_hrxq) + MLX5_RSS_HASH_KEY_LEN), 283 .trunk_size = 64, 284 .grow_trunk = 3, 285 .grow_shift = 2, 286 .need_lock = 0, 287 .release_mem_en = 1, 288 .malloc = rte_malloc_socket, 289 .free = rte_free, 290 .type = "mlx5_hrxq_ipool", 291 }, 292 { 293 .size = sizeof(struct mlx5_flow_handle), 294 .trunk_size = 64, 295 .grow_trunk = 3, 296 .grow_shift = 2, 297 .need_lock = 0, 298 .release_mem_en = 1, 299 .malloc = rte_malloc_socket, 300 .free = rte_free, 301 .type = "mlx5_flow_handle_ipool", 302 }, 303 { 304 .size = sizeof(struct rte_flow), 305 .trunk_size = 4096, 306 .need_lock = 1, 307 .release_mem_en = 1, 308 .malloc = rte_malloc_socket, 309 .free = rte_free, 310 .type = "rte_flow_ipool", 311 }, 312 }; 313 314 315 #define MLX5_FLOW_MIN_ID_POOL_SIZE 512 316 #define MLX5_ID_GENERATION_ARRAY_FACTOR 16 317 318 #define MLX5_FLOW_TABLE_HLIST_ARRAY_SIZE 4096 319 #define MLX5_TAGS_HLIST_ARRAY_SIZE 8192 320 321 /** 322 * Allocate ID pool structure. 323 * 324 * @param[in] max_id 325 * The maximum id can be allocated from the pool. 326 * 327 * @return 328 * Pointer to pool object, NULL value otherwise. 329 */ 330 struct mlx5_flow_id_pool * 331 mlx5_flow_id_pool_alloc(uint32_t max_id) 332 { 333 struct mlx5_flow_id_pool *pool; 334 void *mem; 335 336 pool = rte_zmalloc("id pool allocation", sizeof(*pool), 337 RTE_CACHE_LINE_SIZE); 338 if (!pool) { 339 DRV_LOG(ERR, "can't allocate id pool"); 340 rte_errno = ENOMEM; 341 return NULL; 342 } 343 mem = rte_zmalloc("", MLX5_FLOW_MIN_ID_POOL_SIZE * sizeof(uint32_t), 344 RTE_CACHE_LINE_SIZE); 345 if (!mem) { 346 DRV_LOG(ERR, "can't allocate mem for id pool"); 347 rte_errno = ENOMEM; 348 goto error; 349 } 350 pool->free_arr = mem; 351 pool->curr = pool->free_arr; 352 pool->last = pool->free_arr + MLX5_FLOW_MIN_ID_POOL_SIZE; 353 pool->base_index = 0; 354 pool->max_id = max_id; 355 return pool; 356 error: 357 rte_free(pool); 358 return NULL; 359 } 360 361 /** 362 * Release ID pool structure. 363 * 364 * @param[in] pool 365 * Pointer to flow id pool object to free. 366 */ 367 void 368 mlx5_flow_id_pool_release(struct mlx5_flow_id_pool *pool) 369 { 370 rte_free(pool->free_arr); 371 rte_free(pool); 372 } 373 374 /** 375 * Generate ID. 376 * 377 * @param[in] pool 378 * Pointer to flow id pool. 379 * @param[out] id 380 * The generated ID. 381 * 382 * @return 383 * 0 on success, error value otherwise. 384 */ 385 uint32_t 386 mlx5_flow_id_get(struct mlx5_flow_id_pool *pool, uint32_t *id) 387 { 388 if (pool->curr == pool->free_arr) { 389 if (pool->base_index == pool->max_id) { 390 rte_errno = ENOMEM; 391 DRV_LOG(ERR, "no free id"); 392 return -rte_errno; 393 } 394 *id = ++pool->base_index; 395 return 0; 396 } 397 *id = *(--pool->curr); 398 return 0; 399 } 400 401 /** 402 * Release ID. 403 * 404 * @param[in] pool 405 * Pointer to flow id pool. 406 * @param[out] id 407 * The generated ID. 408 * 409 * @return 410 * 0 on success, error value otherwise. 411 */ 412 uint32_t 413 mlx5_flow_id_release(struct mlx5_flow_id_pool *pool, uint32_t id) 414 { 415 uint32_t size; 416 uint32_t size2; 417 void *mem; 418 419 if (pool->curr == pool->last) { 420 size = pool->curr - pool->free_arr; 421 size2 = size * MLX5_ID_GENERATION_ARRAY_FACTOR; 422 MLX5_ASSERT(size2 > size); 423 mem = rte_malloc("", size2 * sizeof(uint32_t), 0); 424 if (!mem) { 425 DRV_LOG(ERR, "can't allocate mem for id pool"); 426 rte_errno = ENOMEM; 427 return -rte_errno; 428 } 429 memcpy(mem, pool->free_arr, size * sizeof(uint32_t)); 430 rte_free(pool->free_arr); 431 pool->free_arr = mem; 432 pool->curr = pool->free_arr + size; 433 pool->last = pool->free_arr + size2; 434 } 435 *pool->curr = id; 436 pool->curr++; 437 return 0; 438 } 439 440 /** 441 * Initialize the shared aging list information per port. 442 * 443 * @param[in] sh 444 * Pointer to mlx5_ibv_shared object. 445 */ 446 static void 447 mlx5_flow_aging_init(struct mlx5_ibv_shared *sh) 448 { 449 uint32_t i; 450 struct mlx5_age_info *age_info; 451 452 for (i = 0; i < sh->max_port; i++) { 453 age_info = &sh->port[i].age_info; 454 age_info->flags = 0; 455 TAILQ_INIT(&age_info->aged_counters); 456 rte_spinlock_init(&age_info->aged_sl); 457 MLX5_AGE_SET(age_info, MLX5_AGE_TRIGGER); 458 } 459 } 460 461 /** 462 * Initialize the counters management structure. 463 * 464 * @param[in] sh 465 * Pointer to mlx5_ibv_shared object to free 466 */ 467 static void 468 mlx5_flow_counters_mng_init(struct mlx5_ibv_shared *sh) 469 { 470 uint8_t i, age; 471 472 sh->cmng.age = 0; 473 TAILQ_INIT(&sh->cmng.flow_counters); 474 for (age = 0; age < RTE_DIM(sh->cmng.ccont[0]); ++age) { 475 for (i = 0; i < RTE_DIM(sh->cmng.ccont); ++i) 476 TAILQ_INIT(&sh->cmng.ccont[i][age].pool_list); 477 } 478 } 479 480 /** 481 * Destroy all the resources allocated for a counter memory management. 482 * 483 * @param[in] mng 484 * Pointer to the memory management structure. 485 */ 486 static void 487 mlx5_flow_destroy_counter_stat_mem_mng(struct mlx5_counter_stats_mem_mng *mng) 488 { 489 uint8_t *mem = (uint8_t *)(uintptr_t)mng->raws[0].data; 490 491 LIST_REMOVE(mng, next); 492 claim_zero(mlx5_devx_cmd_destroy(mng->dm)); 493 claim_zero(mlx5_glue->devx_umem_dereg(mng->umem)); 494 rte_free(mem); 495 } 496 497 /** 498 * Close and release all the resources of the counters management. 499 * 500 * @param[in] sh 501 * Pointer to mlx5_ibv_shared object to free. 502 */ 503 static void 504 mlx5_flow_counters_mng_close(struct mlx5_ibv_shared *sh) 505 { 506 struct mlx5_counter_stats_mem_mng *mng; 507 uint8_t i, age = 0; 508 int j; 509 int retries = 1024; 510 511 rte_errno = 0; 512 while (--retries) { 513 rte_eal_alarm_cancel(mlx5_flow_query_alarm, sh); 514 if (rte_errno != EINPROGRESS) 515 break; 516 rte_pause(); 517 } 518 519 for (age = 0; age < RTE_DIM(sh->cmng.ccont[0]); ++age) { 520 for (i = 0; i < RTE_DIM(sh->cmng.ccont); ++i) { 521 struct mlx5_flow_counter_pool *pool; 522 uint32_t batch = !!(i % 2); 523 524 if (!sh->cmng.ccont[i][age].pools) 525 continue; 526 pool = TAILQ_FIRST(&sh->cmng.ccont[i][age].pool_list); 527 while (pool) { 528 if (batch) { 529 if (pool->min_dcs) 530 claim_zero 531 (mlx5_devx_cmd_destroy 532 (pool->min_dcs)); 533 } 534 for (j = 0; j < MLX5_COUNTERS_PER_POOL; ++j) { 535 if (MLX5_POOL_GET_CNT(pool, j)->action) 536 claim_zero 537 (mlx5_glue->destroy_flow_action 538 (MLX5_POOL_GET_CNT 539 (pool, j)->action)); 540 if (!batch && MLX5_GET_POOL_CNT_EXT 541 (pool, j)->dcs) 542 claim_zero(mlx5_devx_cmd_destroy 543 (MLX5_GET_POOL_CNT_EXT 544 (pool, j)->dcs)); 545 } 546 TAILQ_REMOVE(&sh->cmng.ccont[i][age].pool_list, 547 pool, next); 548 rte_free(pool); 549 pool = TAILQ_FIRST 550 (&sh->cmng.ccont[i][age].pool_list); 551 } 552 rte_free(sh->cmng.ccont[i][age].pools); 553 } 554 } 555 mng = LIST_FIRST(&sh->cmng.mem_mngs); 556 while (mng) { 557 mlx5_flow_destroy_counter_stat_mem_mng(mng); 558 mng = LIST_FIRST(&sh->cmng.mem_mngs); 559 } 560 memset(&sh->cmng, 0, sizeof(sh->cmng)); 561 } 562 563 /** 564 * Initialize the flow resources' indexed mempool. 565 * 566 * @param[in] sh 567 * Pointer to mlx5_ibv_shared object. 568 * @param[in] sh 569 * Pointer to user dev config. 570 */ 571 static void 572 mlx5_flow_ipool_create(struct mlx5_ibv_shared *sh, 573 const struct mlx5_dev_config *config __rte_unused) 574 { 575 uint8_t i; 576 577 #ifdef HAVE_IBV_FLOW_DV_SUPPORT 578 /* 579 * While DV is supported, user chooses the verbs mode, 580 * the mlx5 flow handle size is different with the 581 * MLX5_FLOW_HANDLE_VERBS_SIZE. 582 */ 583 if (!config->dv_flow_en) 584 mlx5_ipool_cfg[MLX5_IPOOL_MLX5_FLOW].size = 585 MLX5_FLOW_HANDLE_VERBS_SIZE; 586 #endif 587 for (i = 0; i < MLX5_IPOOL_MAX; ++i) 588 sh->ipool[i] = mlx5_ipool_create(&mlx5_ipool_cfg[i]); 589 } 590 591 /** 592 * Release the flow resources' indexed mempool. 593 * 594 * @param[in] sh 595 * Pointer to mlx5_ibv_shared object. 596 */ 597 static void 598 mlx5_flow_ipool_destroy(struct mlx5_ibv_shared *sh) 599 { 600 uint8_t i; 601 602 for (i = 0; i < MLX5_IPOOL_MAX; ++i) 603 mlx5_ipool_destroy(sh->ipool[i]); 604 } 605 606 /** 607 * Extract pdn of PD object using DV API. 608 * 609 * @param[in] pd 610 * Pointer to the verbs PD object. 611 * @param[out] pdn 612 * Pointer to the PD object number variable. 613 * 614 * @return 615 * 0 on success, error value otherwise. 616 */ 617 #ifdef HAVE_IBV_FLOW_DV_SUPPORT 618 static int 619 mlx5_get_pdn(struct ibv_pd *pd __rte_unused, uint32_t *pdn __rte_unused) 620 { 621 struct mlx5dv_obj obj; 622 struct mlx5dv_pd pd_info; 623 int ret = 0; 624 625 obj.pd.in = pd; 626 obj.pd.out = &pd_info; 627 ret = mlx5_glue->dv_init_obj(&obj, MLX5DV_OBJ_PD); 628 if (ret) { 629 DRV_LOG(DEBUG, "Fail to get PD object info"); 630 return ret; 631 } 632 *pdn = pd_info.pdn; 633 return 0; 634 } 635 #endif /* HAVE_IBV_FLOW_DV_SUPPORT */ 636 637 static int 638 mlx5_config_doorbell_mapping_env(const struct mlx5_dev_config *config) 639 { 640 char *env; 641 int value; 642 643 MLX5_ASSERT(rte_eal_process_type() == RTE_PROC_PRIMARY); 644 /* Get environment variable to store. */ 645 env = getenv(MLX5_SHUT_UP_BF); 646 value = env ? !!strcmp(env, "0") : MLX5_ARG_UNSET; 647 if (config->dbnc == MLX5_ARG_UNSET) 648 setenv(MLX5_SHUT_UP_BF, MLX5_SHUT_UP_BF_DEFAULT, 1); 649 else 650 setenv(MLX5_SHUT_UP_BF, 651 config->dbnc == MLX5_TXDB_NCACHED ? "1" : "0", 1); 652 return value; 653 } 654 655 static void 656 mlx5_restore_doorbell_mapping_env(int value) 657 { 658 MLX5_ASSERT(rte_eal_process_type() == RTE_PROC_PRIMARY); 659 /* Restore the original environment variable state. */ 660 if (value == MLX5_ARG_UNSET) 661 unsetenv(MLX5_SHUT_UP_BF); 662 else 663 setenv(MLX5_SHUT_UP_BF, value ? "1" : "0", 1); 664 } 665 666 /** 667 * Allocate shared IB device context. If there is multiport device the 668 * master and representors will share this context, if there is single 669 * port dedicated IB device, the context will be used by only given 670 * port due to unification. 671 * 672 * Routine first searches the context for the specified IB device name, 673 * if found the shared context assumed and reference counter is incremented. 674 * If no context found the new one is created and initialized with specified 675 * IB device context and parameters. 676 * 677 * @param[in] spawn 678 * Pointer to the IB device attributes (name, port, etc). 679 * @param[in] config 680 * Pointer to device configuration structure. 681 * 682 * @return 683 * Pointer to mlx5_ibv_shared object on success, 684 * otherwise NULL and rte_errno is set. 685 */ 686 static struct mlx5_ibv_shared * 687 mlx5_alloc_shared_ibctx(const struct mlx5_dev_spawn_data *spawn, 688 const struct mlx5_dev_config *config) 689 { 690 struct mlx5_ibv_shared *sh; 691 int dbmap_env; 692 int err = 0; 693 uint32_t i; 694 #ifdef HAVE_IBV_FLOW_DV_SUPPORT 695 struct mlx5_devx_tis_attr tis_attr = { 0 }; 696 #endif 697 698 MLX5_ASSERT(spawn); 699 /* Secondary process should not create the shared context. */ 700 MLX5_ASSERT(rte_eal_process_type() == RTE_PROC_PRIMARY); 701 pthread_mutex_lock(&mlx5_ibv_list_mutex); 702 /* Search for IB context by device name. */ 703 LIST_FOREACH(sh, &mlx5_ibv_list, next) { 704 if (!strcmp(sh->ibdev_name, spawn->ibv_dev->name)) { 705 sh->refcnt++; 706 goto exit; 707 } 708 } 709 /* No device found, we have to create new shared context. */ 710 MLX5_ASSERT(spawn->max_port); 711 sh = rte_zmalloc("ethdev shared ib context", 712 sizeof(struct mlx5_ibv_shared) + 713 spawn->max_port * 714 sizeof(struct mlx5_ibv_shared_port), 715 RTE_CACHE_LINE_SIZE); 716 if (!sh) { 717 DRV_LOG(ERR, "shared context allocation failure"); 718 rte_errno = ENOMEM; 719 goto exit; 720 } 721 /* 722 * Configure environment variable "MLX5_BF_SHUT_UP" 723 * before the device creation. The rdma_core library 724 * checks the variable at device creation and 725 * stores the result internally. 726 */ 727 dbmap_env = mlx5_config_doorbell_mapping_env(config); 728 /* Try to open IB device with DV first, then usual Verbs. */ 729 errno = 0; 730 sh->ctx = mlx5_glue->dv_open_device(spawn->ibv_dev); 731 if (sh->ctx) { 732 sh->devx = 1; 733 DRV_LOG(DEBUG, "DevX is supported"); 734 /* The device is created, no need for environment. */ 735 mlx5_restore_doorbell_mapping_env(dbmap_env); 736 } else { 737 /* The environment variable is still configured. */ 738 sh->ctx = mlx5_glue->open_device(spawn->ibv_dev); 739 err = errno ? errno : ENODEV; 740 /* 741 * The environment variable is not needed anymore, 742 * all device creation attempts are completed. 743 */ 744 mlx5_restore_doorbell_mapping_env(dbmap_env); 745 if (!sh->ctx) 746 goto error; 747 DRV_LOG(DEBUG, "DevX is NOT supported"); 748 } 749 err = mlx5_glue->query_device_ex(sh->ctx, NULL, &sh->device_attr); 750 if (err) { 751 DRV_LOG(DEBUG, "ibv_query_device_ex() failed"); 752 goto error; 753 } 754 sh->refcnt = 1; 755 sh->max_port = spawn->max_port; 756 strncpy(sh->ibdev_name, sh->ctx->device->name, 757 sizeof(sh->ibdev_name)); 758 strncpy(sh->ibdev_path, sh->ctx->device->ibdev_path, 759 sizeof(sh->ibdev_path)); 760 pthread_mutex_init(&sh->intr_mutex, NULL); 761 /* 762 * Setting port_id to max unallowed value means 763 * there is no interrupt subhandler installed for 764 * the given port index i. 765 */ 766 for (i = 0; i < sh->max_port; i++) { 767 sh->port[i].ih_port_id = RTE_MAX_ETHPORTS; 768 sh->port[i].devx_ih_port_id = RTE_MAX_ETHPORTS; 769 } 770 sh->pd = mlx5_glue->alloc_pd(sh->ctx); 771 if (sh->pd == NULL) { 772 DRV_LOG(ERR, "PD allocation failure"); 773 err = ENOMEM; 774 goto error; 775 } 776 #ifdef HAVE_IBV_FLOW_DV_SUPPORT 777 if (sh->devx) { 778 err = mlx5_get_pdn(sh->pd, &sh->pdn); 779 if (err) { 780 DRV_LOG(ERR, "Fail to extract pdn from PD"); 781 goto error; 782 } 783 sh->td = mlx5_devx_cmd_create_td(sh->ctx); 784 if (!sh->td) { 785 DRV_LOG(ERR, "TD allocation failure"); 786 err = ENOMEM; 787 goto error; 788 } 789 tis_attr.transport_domain = sh->td->id; 790 sh->tis = mlx5_devx_cmd_create_tis(sh->ctx, &tis_attr); 791 if (!sh->tis) { 792 DRV_LOG(ERR, "TIS allocation failure"); 793 err = ENOMEM; 794 goto error; 795 } 796 } 797 sh->flow_id_pool = mlx5_flow_id_pool_alloc 798 ((1 << HAIRPIN_FLOW_ID_BITS) - 1); 799 if (!sh->flow_id_pool) { 800 DRV_LOG(ERR, "can't create flow id pool"); 801 err = ENOMEM; 802 goto error; 803 } 804 #endif /* HAVE_IBV_FLOW_DV_SUPPORT */ 805 /* 806 * Once the device is added to the list of memory event 807 * callback, its global MR cache table cannot be expanded 808 * on the fly because of deadlock. If it overflows, lookup 809 * should be done by searching MR list linearly, which is slow. 810 * 811 * At this point the device is not added to the memory 812 * event list yet, context is just being created. 813 */ 814 err = mlx5_mr_btree_init(&sh->share_cache.cache, 815 MLX5_MR_BTREE_CACHE_N * 2, 816 spawn->pci_dev->device.numa_node); 817 if (err) { 818 err = rte_errno; 819 goto error; 820 } 821 mlx5_flow_aging_init(sh); 822 mlx5_flow_counters_mng_init(sh); 823 mlx5_flow_ipool_create(sh, config); 824 /* Add device to memory callback list. */ 825 rte_rwlock_write_lock(&mlx5_shared_data->mem_event_rwlock); 826 LIST_INSERT_HEAD(&mlx5_shared_data->mem_event_cb_list, 827 sh, mem_event_cb); 828 rte_rwlock_write_unlock(&mlx5_shared_data->mem_event_rwlock); 829 /* Add context to the global device list. */ 830 LIST_INSERT_HEAD(&mlx5_ibv_list, sh, next); 831 exit: 832 pthread_mutex_unlock(&mlx5_ibv_list_mutex); 833 return sh; 834 error: 835 pthread_mutex_unlock(&mlx5_ibv_list_mutex); 836 MLX5_ASSERT(sh); 837 if (sh->tis) 838 claim_zero(mlx5_devx_cmd_destroy(sh->tis)); 839 if (sh->td) 840 claim_zero(mlx5_devx_cmd_destroy(sh->td)); 841 if (sh->pd) 842 claim_zero(mlx5_glue->dealloc_pd(sh->pd)); 843 if (sh->ctx) 844 claim_zero(mlx5_glue->close_device(sh->ctx)); 845 if (sh->flow_id_pool) 846 mlx5_flow_id_pool_release(sh->flow_id_pool); 847 rte_free(sh); 848 MLX5_ASSERT(err > 0); 849 rte_errno = err; 850 return NULL; 851 } 852 853 /** 854 * Free shared IB device context. Decrement counter and if zero free 855 * all allocated resources and close handles. 856 * 857 * @param[in] sh 858 * Pointer to mlx5_ibv_shared object to free 859 */ 860 static void 861 mlx5_free_shared_ibctx(struct mlx5_ibv_shared *sh) 862 { 863 pthread_mutex_lock(&mlx5_ibv_list_mutex); 864 #ifdef RTE_LIBRTE_MLX5_DEBUG 865 /* Check the object presence in the list. */ 866 struct mlx5_ibv_shared *lctx; 867 868 LIST_FOREACH(lctx, &mlx5_ibv_list, next) 869 if (lctx == sh) 870 break; 871 MLX5_ASSERT(lctx); 872 if (lctx != sh) { 873 DRV_LOG(ERR, "Freeing non-existing shared IB context"); 874 goto exit; 875 } 876 #endif 877 MLX5_ASSERT(sh); 878 MLX5_ASSERT(sh->refcnt); 879 /* Secondary process should not free the shared context. */ 880 MLX5_ASSERT(rte_eal_process_type() == RTE_PROC_PRIMARY); 881 if (--sh->refcnt) 882 goto exit; 883 /* Remove from memory callback device list. */ 884 rte_rwlock_write_lock(&mlx5_shared_data->mem_event_rwlock); 885 LIST_REMOVE(sh, mem_event_cb); 886 rte_rwlock_write_unlock(&mlx5_shared_data->mem_event_rwlock); 887 /* Release created Memory Regions. */ 888 mlx5_mr_release_cache(&sh->share_cache); 889 /* Remove context from the global device list. */ 890 LIST_REMOVE(sh, next); 891 /* 892 * Ensure there is no async event handler installed. 893 * Only primary process handles async device events. 894 **/ 895 mlx5_flow_counters_mng_close(sh); 896 mlx5_flow_ipool_destroy(sh); 897 MLX5_ASSERT(!sh->intr_cnt); 898 if (sh->intr_cnt) 899 mlx5_intr_callback_unregister 900 (&sh->intr_handle, mlx5_dev_interrupt_handler, sh); 901 #ifdef HAVE_MLX5_DEVX_ASYNC_SUPPORT 902 if (sh->devx_intr_cnt) { 903 if (sh->intr_handle_devx.fd) 904 rte_intr_callback_unregister(&sh->intr_handle_devx, 905 mlx5_dev_interrupt_handler_devx, sh); 906 if (sh->devx_comp) 907 mlx5dv_devx_destroy_cmd_comp(sh->devx_comp); 908 } 909 #endif 910 pthread_mutex_destroy(&sh->intr_mutex); 911 if (sh->pd) 912 claim_zero(mlx5_glue->dealloc_pd(sh->pd)); 913 if (sh->tis) 914 claim_zero(mlx5_devx_cmd_destroy(sh->tis)); 915 if (sh->td) 916 claim_zero(mlx5_devx_cmd_destroy(sh->td)); 917 if (sh->ctx) 918 claim_zero(mlx5_glue->close_device(sh->ctx)); 919 if (sh->flow_id_pool) 920 mlx5_flow_id_pool_release(sh->flow_id_pool); 921 rte_free(sh); 922 exit: 923 pthread_mutex_unlock(&mlx5_ibv_list_mutex); 924 } 925 926 /** 927 * Destroy table hash list and all the root entries per domain. 928 * 929 * @param[in] priv 930 * Pointer to the private device data structure. 931 */ 932 static void 933 mlx5_free_table_hash_list(struct mlx5_priv *priv) 934 { 935 struct mlx5_ibv_shared *sh = priv->sh; 936 struct mlx5_flow_tbl_data_entry *tbl_data; 937 union mlx5_flow_tbl_key table_key = { 938 { 939 .table_id = 0, 940 .reserved = 0, 941 .domain = 0, 942 .direction = 0, 943 } 944 }; 945 struct mlx5_hlist_entry *pos; 946 947 if (!sh->flow_tbls) 948 return; 949 pos = mlx5_hlist_lookup(sh->flow_tbls, table_key.v64); 950 if (pos) { 951 tbl_data = container_of(pos, struct mlx5_flow_tbl_data_entry, 952 entry); 953 MLX5_ASSERT(tbl_data); 954 mlx5_hlist_remove(sh->flow_tbls, pos); 955 rte_free(tbl_data); 956 } 957 table_key.direction = 1; 958 pos = mlx5_hlist_lookup(sh->flow_tbls, table_key.v64); 959 if (pos) { 960 tbl_data = container_of(pos, struct mlx5_flow_tbl_data_entry, 961 entry); 962 MLX5_ASSERT(tbl_data); 963 mlx5_hlist_remove(sh->flow_tbls, pos); 964 rte_free(tbl_data); 965 } 966 table_key.direction = 0; 967 table_key.domain = 1; 968 pos = mlx5_hlist_lookup(sh->flow_tbls, table_key.v64); 969 if (pos) { 970 tbl_data = container_of(pos, struct mlx5_flow_tbl_data_entry, 971 entry); 972 MLX5_ASSERT(tbl_data); 973 mlx5_hlist_remove(sh->flow_tbls, pos); 974 rte_free(tbl_data); 975 } 976 mlx5_hlist_destroy(sh->flow_tbls, NULL, NULL); 977 } 978 979 /** 980 * Initialize flow table hash list and create the root tables entry 981 * for each domain. 982 * 983 * @param[in] priv 984 * Pointer to the private device data structure. 985 * 986 * @return 987 * Zero on success, positive error code otherwise. 988 */ 989 static int 990 mlx5_alloc_table_hash_list(struct mlx5_priv *priv) 991 { 992 struct mlx5_ibv_shared *sh = priv->sh; 993 char s[MLX5_HLIST_NAMESIZE]; 994 int err = 0; 995 996 MLX5_ASSERT(sh); 997 snprintf(s, sizeof(s), "%s_flow_table", priv->sh->ibdev_name); 998 sh->flow_tbls = mlx5_hlist_create(s, MLX5_FLOW_TABLE_HLIST_ARRAY_SIZE); 999 if (!sh->flow_tbls) { 1000 DRV_LOG(ERR, "flow tables with hash creation failed.\n"); 1001 err = ENOMEM; 1002 return err; 1003 } 1004 #ifndef HAVE_MLX5DV_DR 1005 /* 1006 * In case we have not DR support, the zero tables should be created 1007 * because DV expect to see them even if they cannot be created by 1008 * RDMA-CORE. 1009 */ 1010 union mlx5_flow_tbl_key table_key = { 1011 { 1012 .table_id = 0, 1013 .reserved = 0, 1014 .domain = 0, 1015 .direction = 0, 1016 } 1017 }; 1018 struct mlx5_flow_tbl_data_entry *tbl_data = rte_zmalloc(NULL, 1019 sizeof(*tbl_data), 0); 1020 1021 if (!tbl_data) { 1022 err = ENOMEM; 1023 goto error; 1024 } 1025 tbl_data->entry.key = table_key.v64; 1026 err = mlx5_hlist_insert(sh->flow_tbls, &tbl_data->entry); 1027 if (err) 1028 goto error; 1029 rte_atomic32_init(&tbl_data->tbl.refcnt); 1030 rte_atomic32_inc(&tbl_data->tbl.refcnt); 1031 table_key.direction = 1; 1032 tbl_data = rte_zmalloc(NULL, sizeof(*tbl_data), 0); 1033 if (!tbl_data) { 1034 err = ENOMEM; 1035 goto error; 1036 } 1037 tbl_data->entry.key = table_key.v64; 1038 err = mlx5_hlist_insert(sh->flow_tbls, &tbl_data->entry); 1039 if (err) 1040 goto error; 1041 rte_atomic32_init(&tbl_data->tbl.refcnt); 1042 rte_atomic32_inc(&tbl_data->tbl.refcnt); 1043 table_key.direction = 0; 1044 table_key.domain = 1; 1045 tbl_data = rte_zmalloc(NULL, sizeof(*tbl_data), 0); 1046 if (!tbl_data) { 1047 err = ENOMEM; 1048 goto error; 1049 } 1050 tbl_data->entry.key = table_key.v64; 1051 err = mlx5_hlist_insert(sh->flow_tbls, &tbl_data->entry); 1052 if (err) 1053 goto error; 1054 rte_atomic32_init(&tbl_data->tbl.refcnt); 1055 rte_atomic32_inc(&tbl_data->tbl.refcnt); 1056 return err; 1057 error: 1058 mlx5_free_table_hash_list(priv); 1059 #endif /* HAVE_MLX5DV_DR */ 1060 return err; 1061 } 1062 1063 /** 1064 * Initialize DR related data within private structure. 1065 * Routine checks the reference counter and does actual 1066 * resources creation/initialization only if counter is zero. 1067 * 1068 * @param[in] priv 1069 * Pointer to the private device data structure. 1070 * 1071 * @return 1072 * Zero on success, positive error code otherwise. 1073 */ 1074 static int 1075 mlx5_alloc_shared_dr(struct mlx5_priv *priv) 1076 { 1077 struct mlx5_ibv_shared *sh = priv->sh; 1078 char s[MLX5_HLIST_NAMESIZE]; 1079 int err = 0; 1080 1081 if (!sh->flow_tbls) 1082 err = mlx5_alloc_table_hash_list(priv); 1083 else 1084 DRV_LOG(DEBUG, "sh->flow_tbls[%p] already created, reuse\n", 1085 (void *)sh->flow_tbls); 1086 if (err) 1087 return err; 1088 /* Create tags hash list table. */ 1089 snprintf(s, sizeof(s), "%s_tags", sh->ibdev_name); 1090 sh->tag_table = mlx5_hlist_create(s, MLX5_TAGS_HLIST_ARRAY_SIZE); 1091 if (!sh->tag_table) { 1092 DRV_LOG(ERR, "tags with hash creation failed.\n"); 1093 err = ENOMEM; 1094 goto error; 1095 } 1096 #ifdef HAVE_MLX5DV_DR 1097 void *domain; 1098 1099 if (sh->dv_refcnt) { 1100 /* Shared DV/DR structures is already initialized. */ 1101 sh->dv_refcnt++; 1102 priv->dr_shared = 1; 1103 return 0; 1104 } 1105 /* Reference counter is zero, we should initialize structures. */ 1106 domain = mlx5_glue->dr_create_domain(sh->ctx, 1107 MLX5DV_DR_DOMAIN_TYPE_NIC_RX); 1108 if (!domain) { 1109 DRV_LOG(ERR, "ingress mlx5dv_dr_create_domain failed"); 1110 err = errno; 1111 goto error; 1112 } 1113 sh->rx_domain = domain; 1114 domain = mlx5_glue->dr_create_domain(sh->ctx, 1115 MLX5DV_DR_DOMAIN_TYPE_NIC_TX); 1116 if (!domain) { 1117 DRV_LOG(ERR, "egress mlx5dv_dr_create_domain failed"); 1118 err = errno; 1119 goto error; 1120 } 1121 pthread_mutex_init(&sh->dv_mutex, NULL); 1122 sh->tx_domain = domain; 1123 #ifdef HAVE_MLX5DV_DR_ESWITCH 1124 if (priv->config.dv_esw_en) { 1125 domain = mlx5_glue->dr_create_domain 1126 (sh->ctx, MLX5DV_DR_DOMAIN_TYPE_FDB); 1127 if (!domain) { 1128 DRV_LOG(ERR, "FDB mlx5dv_dr_create_domain failed"); 1129 err = errno; 1130 goto error; 1131 } 1132 sh->fdb_domain = domain; 1133 sh->esw_drop_action = mlx5_glue->dr_create_flow_action_drop(); 1134 } 1135 #endif 1136 sh->pop_vlan_action = mlx5_glue->dr_create_flow_action_pop_vlan(); 1137 #endif /* HAVE_MLX5DV_DR */ 1138 sh->dv_refcnt++; 1139 priv->dr_shared = 1; 1140 return 0; 1141 error: 1142 /* Rollback the created objects. */ 1143 if (sh->rx_domain) { 1144 mlx5_glue->dr_destroy_domain(sh->rx_domain); 1145 sh->rx_domain = NULL; 1146 } 1147 if (sh->tx_domain) { 1148 mlx5_glue->dr_destroy_domain(sh->tx_domain); 1149 sh->tx_domain = NULL; 1150 } 1151 if (sh->fdb_domain) { 1152 mlx5_glue->dr_destroy_domain(sh->fdb_domain); 1153 sh->fdb_domain = NULL; 1154 } 1155 if (sh->esw_drop_action) { 1156 mlx5_glue->destroy_flow_action(sh->esw_drop_action); 1157 sh->esw_drop_action = NULL; 1158 } 1159 if (sh->pop_vlan_action) { 1160 mlx5_glue->destroy_flow_action(sh->pop_vlan_action); 1161 sh->pop_vlan_action = NULL; 1162 } 1163 if (sh->tag_table) { 1164 /* tags should be destroyed with flow before. */ 1165 mlx5_hlist_destroy(sh->tag_table, NULL, NULL); 1166 sh->tag_table = NULL; 1167 } 1168 mlx5_free_table_hash_list(priv); 1169 return err; 1170 } 1171 1172 /** 1173 * Destroy DR related data within private structure. 1174 * 1175 * @param[in] priv 1176 * Pointer to the private device data structure. 1177 */ 1178 static void 1179 mlx5_free_shared_dr(struct mlx5_priv *priv) 1180 { 1181 struct mlx5_ibv_shared *sh; 1182 1183 if (!priv->dr_shared) 1184 return; 1185 priv->dr_shared = 0; 1186 sh = priv->sh; 1187 MLX5_ASSERT(sh); 1188 #ifdef HAVE_MLX5DV_DR 1189 MLX5_ASSERT(sh->dv_refcnt); 1190 if (sh->dv_refcnt && --sh->dv_refcnt) 1191 return; 1192 if (sh->rx_domain) { 1193 mlx5_glue->dr_destroy_domain(sh->rx_domain); 1194 sh->rx_domain = NULL; 1195 } 1196 if (sh->tx_domain) { 1197 mlx5_glue->dr_destroy_domain(sh->tx_domain); 1198 sh->tx_domain = NULL; 1199 } 1200 #ifdef HAVE_MLX5DV_DR_ESWITCH 1201 if (sh->fdb_domain) { 1202 mlx5_glue->dr_destroy_domain(sh->fdb_domain); 1203 sh->fdb_domain = NULL; 1204 } 1205 if (sh->esw_drop_action) { 1206 mlx5_glue->destroy_flow_action(sh->esw_drop_action); 1207 sh->esw_drop_action = NULL; 1208 } 1209 #endif 1210 if (sh->pop_vlan_action) { 1211 mlx5_glue->destroy_flow_action(sh->pop_vlan_action); 1212 sh->pop_vlan_action = NULL; 1213 } 1214 pthread_mutex_destroy(&sh->dv_mutex); 1215 #endif /* HAVE_MLX5DV_DR */ 1216 if (sh->tag_table) { 1217 /* tags should be destroyed with flow before. */ 1218 mlx5_hlist_destroy(sh->tag_table, NULL, NULL); 1219 sh->tag_table = NULL; 1220 } 1221 mlx5_free_table_hash_list(priv); 1222 } 1223 1224 /** 1225 * Initialize shared data between primary and secondary process. 1226 * 1227 * A memzone is reserved by primary process and secondary processes attach to 1228 * the memzone. 1229 * 1230 * @return 1231 * 0 on success, a negative errno value otherwise and rte_errno is set. 1232 */ 1233 static int 1234 mlx5_init_shared_data(void) 1235 { 1236 const struct rte_memzone *mz; 1237 int ret = 0; 1238 1239 rte_spinlock_lock(&mlx5_shared_data_lock); 1240 if (mlx5_shared_data == NULL) { 1241 if (rte_eal_process_type() == RTE_PROC_PRIMARY) { 1242 /* Allocate shared memory. */ 1243 mz = rte_memzone_reserve(MZ_MLX5_PMD_SHARED_DATA, 1244 sizeof(*mlx5_shared_data), 1245 SOCKET_ID_ANY, 0); 1246 if (mz == NULL) { 1247 DRV_LOG(ERR, 1248 "Cannot allocate mlx5 shared data"); 1249 ret = -rte_errno; 1250 goto error; 1251 } 1252 mlx5_shared_data = mz->addr; 1253 memset(mlx5_shared_data, 0, sizeof(*mlx5_shared_data)); 1254 rte_spinlock_init(&mlx5_shared_data->lock); 1255 } else { 1256 /* Lookup allocated shared memory. */ 1257 mz = rte_memzone_lookup(MZ_MLX5_PMD_SHARED_DATA); 1258 if (mz == NULL) { 1259 DRV_LOG(ERR, 1260 "Cannot attach mlx5 shared data"); 1261 ret = -rte_errno; 1262 goto error; 1263 } 1264 mlx5_shared_data = mz->addr; 1265 memset(&mlx5_local_data, 0, sizeof(mlx5_local_data)); 1266 } 1267 } 1268 error: 1269 rte_spinlock_unlock(&mlx5_shared_data_lock); 1270 return ret; 1271 } 1272 1273 /** 1274 * Retrieve integer value from environment variable. 1275 * 1276 * @param[in] name 1277 * Environment variable name. 1278 * 1279 * @return 1280 * Integer value, 0 if the variable is not set. 1281 */ 1282 int 1283 mlx5_getenv_int(const char *name) 1284 { 1285 const char *val = getenv(name); 1286 1287 if (val == NULL) 1288 return 0; 1289 return atoi(val); 1290 } 1291 1292 /** 1293 * Verbs callback to allocate a memory. This function should allocate the space 1294 * according to the size provided residing inside a huge page. 1295 * Please note that all allocation must respect the alignment from libmlx5 1296 * (i.e. currently sysconf(_SC_PAGESIZE)). 1297 * 1298 * @param[in] size 1299 * The size in bytes of the memory to allocate. 1300 * @param[in] data 1301 * A pointer to the callback data. 1302 * 1303 * @return 1304 * Allocated buffer, NULL otherwise and rte_errno is set. 1305 */ 1306 static void * 1307 mlx5_alloc_verbs_buf(size_t size, void *data) 1308 { 1309 struct mlx5_priv *priv = data; 1310 void *ret; 1311 size_t alignment = sysconf(_SC_PAGESIZE); 1312 unsigned int socket = SOCKET_ID_ANY; 1313 1314 if (priv->verbs_alloc_ctx.type == MLX5_VERBS_ALLOC_TYPE_TX_QUEUE) { 1315 const struct mlx5_txq_ctrl *ctrl = priv->verbs_alloc_ctx.obj; 1316 1317 socket = ctrl->socket; 1318 } else if (priv->verbs_alloc_ctx.type == 1319 MLX5_VERBS_ALLOC_TYPE_RX_QUEUE) { 1320 const struct mlx5_rxq_ctrl *ctrl = priv->verbs_alloc_ctx.obj; 1321 1322 socket = ctrl->socket; 1323 } 1324 MLX5_ASSERT(data != NULL); 1325 ret = rte_malloc_socket(__func__, size, alignment, socket); 1326 if (!ret && size) 1327 rte_errno = ENOMEM; 1328 return ret; 1329 } 1330 1331 /** 1332 * Verbs callback to free a memory. 1333 * 1334 * @param[in] ptr 1335 * A pointer to the memory to free. 1336 * @param[in] data 1337 * A pointer to the callback data. 1338 */ 1339 static void 1340 mlx5_free_verbs_buf(void *ptr, void *data __rte_unused) 1341 { 1342 MLX5_ASSERT(data != NULL); 1343 rte_free(ptr); 1344 } 1345 1346 /** 1347 * DPDK callback to add udp tunnel port 1348 * 1349 * @param[in] dev 1350 * A pointer to eth_dev 1351 * @param[in] udp_tunnel 1352 * A pointer to udp tunnel 1353 * 1354 * @return 1355 * 0 on valid udp ports and tunnels, -ENOTSUP otherwise. 1356 */ 1357 int 1358 mlx5_udp_tunnel_port_add(struct rte_eth_dev *dev __rte_unused, 1359 struct rte_eth_udp_tunnel *udp_tunnel) 1360 { 1361 MLX5_ASSERT(udp_tunnel != NULL); 1362 if (udp_tunnel->prot_type == RTE_TUNNEL_TYPE_VXLAN && 1363 udp_tunnel->udp_port == 4789) 1364 return 0; 1365 if (udp_tunnel->prot_type == RTE_TUNNEL_TYPE_VXLAN_GPE && 1366 udp_tunnel->udp_port == 4790) 1367 return 0; 1368 return -ENOTSUP; 1369 } 1370 1371 /** 1372 * Initialize process private data structure. 1373 * 1374 * @param dev 1375 * Pointer to Ethernet device structure. 1376 * 1377 * @return 1378 * 0 on success, a negative errno value otherwise and rte_errno is set. 1379 */ 1380 int 1381 mlx5_proc_priv_init(struct rte_eth_dev *dev) 1382 { 1383 struct mlx5_priv *priv = dev->data->dev_private; 1384 struct mlx5_proc_priv *ppriv; 1385 size_t ppriv_size; 1386 1387 /* 1388 * UAR register table follows the process private structure. BlueFlame 1389 * registers for Tx queues are stored in the table. 1390 */ 1391 ppriv_size = 1392 sizeof(struct mlx5_proc_priv) + priv->txqs_n * sizeof(void *); 1393 ppriv = rte_malloc_socket("mlx5_proc_priv", ppriv_size, 1394 RTE_CACHE_LINE_SIZE, dev->device->numa_node); 1395 if (!ppriv) { 1396 rte_errno = ENOMEM; 1397 return -rte_errno; 1398 } 1399 ppriv->uar_table_sz = ppriv_size; 1400 dev->process_private = ppriv; 1401 return 0; 1402 } 1403 1404 /** 1405 * Un-initialize process private data structure. 1406 * 1407 * @param dev 1408 * Pointer to Ethernet device structure. 1409 */ 1410 static void 1411 mlx5_proc_priv_uninit(struct rte_eth_dev *dev) 1412 { 1413 if (!dev->process_private) 1414 return; 1415 rte_free(dev->process_private); 1416 dev->process_private = NULL; 1417 } 1418 1419 /** 1420 * DPDK callback to close the device. 1421 * 1422 * Destroy all queues and objects, free memory. 1423 * 1424 * @param dev 1425 * Pointer to Ethernet device structure. 1426 */ 1427 static void 1428 mlx5_dev_close(struct rte_eth_dev *dev) 1429 { 1430 struct mlx5_priv *priv = dev->data->dev_private; 1431 unsigned int i; 1432 int ret; 1433 1434 DRV_LOG(DEBUG, "port %u closing device \"%s\"", 1435 dev->data->port_id, 1436 ((priv->sh->ctx != NULL) ? priv->sh->ctx->device->name : "")); 1437 /* In case mlx5_dev_stop() has not been called. */ 1438 mlx5_dev_interrupt_handler_uninstall(dev); 1439 mlx5_dev_interrupt_handler_devx_uninstall(dev); 1440 /* 1441 * If default mreg copy action is removed at the stop stage, 1442 * the search will return none and nothing will be done anymore. 1443 */ 1444 mlx5_flow_stop_default(dev); 1445 mlx5_traffic_disable(dev); 1446 /* 1447 * If all the flows are already flushed in the device stop stage, 1448 * then this will return directly without any action. 1449 */ 1450 mlx5_flow_list_flush(dev, &priv->flows, true); 1451 mlx5_flow_meter_flush(dev, NULL); 1452 /* Free the intermediate buffers for flow creation. */ 1453 mlx5_flow_free_intermediate(dev); 1454 /* Prevent crashes when queues are still in use. */ 1455 dev->rx_pkt_burst = removed_rx_burst; 1456 dev->tx_pkt_burst = removed_tx_burst; 1457 rte_wmb(); 1458 /* Disable datapath on secondary process. */ 1459 mlx5_mp_req_stop_rxtx(dev); 1460 if (priv->rxqs != NULL) { 1461 /* XXX race condition if mlx5_rx_burst() is still running. */ 1462 usleep(1000); 1463 for (i = 0; (i != priv->rxqs_n); ++i) 1464 mlx5_rxq_release(dev, i); 1465 priv->rxqs_n = 0; 1466 priv->rxqs = NULL; 1467 } 1468 if (priv->txqs != NULL) { 1469 /* XXX race condition if mlx5_tx_burst() is still running. */ 1470 usleep(1000); 1471 for (i = 0; (i != priv->txqs_n); ++i) 1472 mlx5_txq_release(dev, i); 1473 priv->txqs_n = 0; 1474 priv->txqs = NULL; 1475 } 1476 mlx5_proc_priv_uninit(dev); 1477 if (priv->mreg_cp_tbl) 1478 mlx5_hlist_destroy(priv->mreg_cp_tbl, NULL, NULL); 1479 mlx5_mprq_free_mp(dev); 1480 mlx5_free_shared_dr(priv); 1481 if (priv->rss_conf.rss_key != NULL) 1482 rte_free(priv->rss_conf.rss_key); 1483 if (priv->reta_idx != NULL) 1484 rte_free(priv->reta_idx); 1485 if (priv->config.vf) 1486 mlx5_nl_mac_addr_flush(priv->nl_socket_route, mlx5_ifindex(dev), 1487 dev->data->mac_addrs, 1488 MLX5_MAX_MAC_ADDRESSES, priv->mac_own); 1489 if (priv->nl_socket_route >= 0) 1490 close(priv->nl_socket_route); 1491 if (priv->nl_socket_rdma >= 0) 1492 close(priv->nl_socket_rdma); 1493 if (priv->vmwa_context) 1494 mlx5_vlan_vmwa_exit(priv->vmwa_context); 1495 ret = mlx5_hrxq_verify(dev); 1496 if (ret) 1497 DRV_LOG(WARNING, "port %u some hash Rx queue still remain", 1498 dev->data->port_id); 1499 ret = mlx5_ind_table_obj_verify(dev); 1500 if (ret) 1501 DRV_LOG(WARNING, "port %u some indirection table still remain", 1502 dev->data->port_id); 1503 ret = mlx5_rxq_obj_verify(dev); 1504 if (ret) 1505 DRV_LOG(WARNING, "port %u some Rx queue objects still remain", 1506 dev->data->port_id); 1507 ret = mlx5_rxq_verify(dev); 1508 if (ret) 1509 DRV_LOG(WARNING, "port %u some Rx queues still remain", 1510 dev->data->port_id); 1511 ret = mlx5_txq_obj_verify(dev); 1512 if (ret) 1513 DRV_LOG(WARNING, "port %u some Verbs Tx queue still remain", 1514 dev->data->port_id); 1515 ret = mlx5_txq_verify(dev); 1516 if (ret) 1517 DRV_LOG(WARNING, "port %u some Tx queues still remain", 1518 dev->data->port_id); 1519 ret = mlx5_flow_verify(dev); 1520 if (ret) 1521 DRV_LOG(WARNING, "port %u some flows still remain", 1522 dev->data->port_id); 1523 if (priv->sh) { 1524 /* 1525 * Free the shared context in last turn, because the cleanup 1526 * routines above may use some shared fields, like 1527 * mlx5_nl_mac_addr_flush() uses ibdev_path for retrieveing 1528 * ifindex if Netlink fails. 1529 */ 1530 mlx5_free_shared_ibctx(priv->sh); 1531 priv->sh = NULL; 1532 } 1533 if (priv->domain_id != RTE_ETH_DEV_SWITCH_DOMAIN_ID_INVALID) { 1534 unsigned int c = 0; 1535 uint16_t port_id; 1536 1537 MLX5_ETH_FOREACH_DEV(port_id, priv->pci_dev) { 1538 struct mlx5_priv *opriv = 1539 rte_eth_devices[port_id].data->dev_private; 1540 1541 if (!opriv || 1542 opriv->domain_id != priv->domain_id || 1543 &rte_eth_devices[port_id] == dev) 1544 continue; 1545 ++c; 1546 break; 1547 } 1548 if (!c) 1549 claim_zero(rte_eth_switch_domain_free(priv->domain_id)); 1550 } 1551 memset(priv, 0, sizeof(*priv)); 1552 priv->domain_id = RTE_ETH_DEV_SWITCH_DOMAIN_ID_INVALID; 1553 /* 1554 * Reset mac_addrs to NULL such that it is not freed as part of 1555 * rte_eth_dev_release_port(). mac_addrs is part of dev_private so 1556 * it is freed when dev_private is freed. 1557 */ 1558 dev->data->mac_addrs = NULL; 1559 } 1560 1561 const struct eth_dev_ops mlx5_dev_ops = { 1562 .dev_configure = mlx5_dev_configure, 1563 .dev_start = mlx5_dev_start, 1564 .dev_stop = mlx5_dev_stop, 1565 .dev_set_link_down = mlx5_set_link_down, 1566 .dev_set_link_up = mlx5_set_link_up, 1567 .dev_close = mlx5_dev_close, 1568 .promiscuous_enable = mlx5_promiscuous_enable, 1569 .promiscuous_disable = mlx5_promiscuous_disable, 1570 .allmulticast_enable = mlx5_allmulticast_enable, 1571 .allmulticast_disable = mlx5_allmulticast_disable, 1572 .link_update = mlx5_link_update, 1573 .stats_get = mlx5_stats_get, 1574 .stats_reset = mlx5_stats_reset, 1575 .xstats_get = mlx5_xstats_get, 1576 .xstats_reset = mlx5_xstats_reset, 1577 .xstats_get_names = mlx5_xstats_get_names, 1578 .fw_version_get = mlx5_fw_version_get, 1579 .dev_infos_get = mlx5_dev_infos_get, 1580 .read_clock = mlx5_read_clock, 1581 .dev_supported_ptypes_get = mlx5_dev_supported_ptypes_get, 1582 .vlan_filter_set = mlx5_vlan_filter_set, 1583 .rx_queue_setup = mlx5_rx_queue_setup, 1584 .rx_hairpin_queue_setup = mlx5_rx_hairpin_queue_setup, 1585 .tx_queue_setup = mlx5_tx_queue_setup, 1586 .tx_hairpin_queue_setup = mlx5_tx_hairpin_queue_setup, 1587 .rx_queue_release = mlx5_rx_queue_release, 1588 .tx_queue_release = mlx5_tx_queue_release, 1589 .flow_ctrl_get = mlx5_dev_get_flow_ctrl, 1590 .flow_ctrl_set = mlx5_dev_set_flow_ctrl, 1591 .mac_addr_remove = mlx5_mac_addr_remove, 1592 .mac_addr_add = mlx5_mac_addr_add, 1593 .mac_addr_set = mlx5_mac_addr_set, 1594 .set_mc_addr_list = mlx5_set_mc_addr_list, 1595 .mtu_set = mlx5_dev_set_mtu, 1596 .vlan_strip_queue_set = mlx5_vlan_strip_queue_set, 1597 .vlan_offload_set = mlx5_vlan_offload_set, 1598 .reta_update = mlx5_dev_rss_reta_update, 1599 .reta_query = mlx5_dev_rss_reta_query, 1600 .rss_hash_update = mlx5_rss_hash_update, 1601 .rss_hash_conf_get = mlx5_rss_hash_conf_get, 1602 .filter_ctrl = mlx5_dev_filter_ctrl, 1603 .rx_descriptor_status = mlx5_rx_descriptor_status, 1604 .tx_descriptor_status = mlx5_tx_descriptor_status, 1605 .rxq_info_get = mlx5_rxq_info_get, 1606 .txq_info_get = mlx5_txq_info_get, 1607 .rx_burst_mode_get = mlx5_rx_burst_mode_get, 1608 .tx_burst_mode_get = mlx5_tx_burst_mode_get, 1609 .rx_queue_count = mlx5_rx_queue_count, 1610 .rx_queue_intr_enable = mlx5_rx_intr_enable, 1611 .rx_queue_intr_disable = mlx5_rx_intr_disable, 1612 .is_removed = mlx5_is_removed, 1613 .udp_tunnel_port_add = mlx5_udp_tunnel_port_add, 1614 .get_module_info = mlx5_get_module_info, 1615 .get_module_eeprom = mlx5_get_module_eeprom, 1616 .hairpin_cap_get = mlx5_hairpin_cap_get, 1617 .mtr_ops_get = mlx5_flow_meter_ops_get, 1618 }; 1619 1620 /* Available operations from secondary process. */ 1621 static const struct eth_dev_ops mlx5_dev_sec_ops = { 1622 .stats_get = mlx5_stats_get, 1623 .stats_reset = mlx5_stats_reset, 1624 .xstats_get = mlx5_xstats_get, 1625 .xstats_reset = mlx5_xstats_reset, 1626 .xstats_get_names = mlx5_xstats_get_names, 1627 .fw_version_get = mlx5_fw_version_get, 1628 .dev_infos_get = mlx5_dev_infos_get, 1629 .rx_descriptor_status = mlx5_rx_descriptor_status, 1630 .tx_descriptor_status = mlx5_tx_descriptor_status, 1631 .rxq_info_get = mlx5_rxq_info_get, 1632 .txq_info_get = mlx5_txq_info_get, 1633 .rx_burst_mode_get = mlx5_rx_burst_mode_get, 1634 .tx_burst_mode_get = mlx5_tx_burst_mode_get, 1635 .get_module_info = mlx5_get_module_info, 1636 .get_module_eeprom = mlx5_get_module_eeprom, 1637 }; 1638 1639 /* Available operations in flow isolated mode. */ 1640 const struct eth_dev_ops mlx5_dev_ops_isolate = { 1641 .dev_configure = mlx5_dev_configure, 1642 .dev_start = mlx5_dev_start, 1643 .dev_stop = mlx5_dev_stop, 1644 .dev_set_link_down = mlx5_set_link_down, 1645 .dev_set_link_up = mlx5_set_link_up, 1646 .dev_close = mlx5_dev_close, 1647 .promiscuous_enable = mlx5_promiscuous_enable, 1648 .promiscuous_disable = mlx5_promiscuous_disable, 1649 .allmulticast_enable = mlx5_allmulticast_enable, 1650 .allmulticast_disable = mlx5_allmulticast_disable, 1651 .link_update = mlx5_link_update, 1652 .stats_get = mlx5_stats_get, 1653 .stats_reset = mlx5_stats_reset, 1654 .xstats_get = mlx5_xstats_get, 1655 .xstats_reset = mlx5_xstats_reset, 1656 .xstats_get_names = mlx5_xstats_get_names, 1657 .fw_version_get = mlx5_fw_version_get, 1658 .dev_infos_get = mlx5_dev_infos_get, 1659 .dev_supported_ptypes_get = mlx5_dev_supported_ptypes_get, 1660 .vlan_filter_set = mlx5_vlan_filter_set, 1661 .rx_queue_setup = mlx5_rx_queue_setup, 1662 .rx_hairpin_queue_setup = mlx5_rx_hairpin_queue_setup, 1663 .tx_queue_setup = mlx5_tx_queue_setup, 1664 .tx_hairpin_queue_setup = mlx5_tx_hairpin_queue_setup, 1665 .rx_queue_release = mlx5_rx_queue_release, 1666 .tx_queue_release = mlx5_tx_queue_release, 1667 .flow_ctrl_get = mlx5_dev_get_flow_ctrl, 1668 .flow_ctrl_set = mlx5_dev_set_flow_ctrl, 1669 .mac_addr_remove = mlx5_mac_addr_remove, 1670 .mac_addr_add = mlx5_mac_addr_add, 1671 .mac_addr_set = mlx5_mac_addr_set, 1672 .set_mc_addr_list = mlx5_set_mc_addr_list, 1673 .mtu_set = mlx5_dev_set_mtu, 1674 .vlan_strip_queue_set = mlx5_vlan_strip_queue_set, 1675 .vlan_offload_set = mlx5_vlan_offload_set, 1676 .filter_ctrl = mlx5_dev_filter_ctrl, 1677 .rx_descriptor_status = mlx5_rx_descriptor_status, 1678 .tx_descriptor_status = mlx5_tx_descriptor_status, 1679 .rxq_info_get = mlx5_rxq_info_get, 1680 .txq_info_get = mlx5_txq_info_get, 1681 .rx_burst_mode_get = mlx5_rx_burst_mode_get, 1682 .tx_burst_mode_get = mlx5_tx_burst_mode_get, 1683 .rx_queue_intr_enable = mlx5_rx_intr_enable, 1684 .rx_queue_intr_disable = mlx5_rx_intr_disable, 1685 .is_removed = mlx5_is_removed, 1686 .get_module_info = mlx5_get_module_info, 1687 .get_module_eeprom = mlx5_get_module_eeprom, 1688 .hairpin_cap_get = mlx5_hairpin_cap_get, 1689 .mtr_ops_get = mlx5_flow_meter_ops_get, 1690 }; 1691 1692 /** 1693 * Verify and store value for device argument. 1694 * 1695 * @param[in] key 1696 * Key argument to verify. 1697 * @param[in] val 1698 * Value associated with key. 1699 * @param opaque 1700 * User data. 1701 * 1702 * @return 1703 * 0 on success, a negative errno value otherwise and rte_errno is set. 1704 */ 1705 static int 1706 mlx5_args_check(const char *key, const char *val, void *opaque) 1707 { 1708 struct mlx5_dev_config *config = opaque; 1709 unsigned long tmp; 1710 1711 /* No-op, port representors are processed in mlx5_dev_spawn(). */ 1712 if (!strcmp(MLX5_REPRESENTOR, key)) 1713 return 0; 1714 errno = 0; 1715 tmp = strtoul(val, NULL, 0); 1716 if (errno) { 1717 rte_errno = errno; 1718 DRV_LOG(WARNING, "%s: \"%s\" is not a valid integer", key, val); 1719 return -rte_errno; 1720 } 1721 if (strcmp(MLX5_RXQ_CQE_COMP_EN, key) == 0) { 1722 config->cqe_comp = !!tmp; 1723 } else if (strcmp(MLX5_RXQ_CQE_PAD_EN, key) == 0) { 1724 config->cqe_pad = !!tmp; 1725 } else if (strcmp(MLX5_RXQ_PKT_PAD_EN, key) == 0) { 1726 config->hw_padding = !!tmp; 1727 } else if (strcmp(MLX5_RX_MPRQ_EN, key) == 0) { 1728 config->mprq.enabled = !!tmp; 1729 } else if (strcmp(MLX5_RX_MPRQ_LOG_STRIDE_NUM, key) == 0) { 1730 config->mprq.stride_num_n = tmp; 1731 } else if (strcmp(MLX5_RX_MPRQ_LOG_STRIDE_SIZE, key) == 0) { 1732 config->mprq.stride_size_n = tmp; 1733 } else if (strcmp(MLX5_RX_MPRQ_MAX_MEMCPY_LEN, key) == 0) { 1734 config->mprq.max_memcpy_len = tmp; 1735 } else if (strcmp(MLX5_RXQS_MIN_MPRQ, key) == 0) { 1736 config->mprq.min_rxqs_num = tmp; 1737 } else if (strcmp(MLX5_TXQ_INLINE, key) == 0) { 1738 DRV_LOG(WARNING, "%s: deprecated parameter," 1739 " converted to txq_inline_max", key); 1740 config->txq_inline_max = tmp; 1741 } else if (strcmp(MLX5_TXQ_INLINE_MAX, key) == 0) { 1742 config->txq_inline_max = tmp; 1743 } else if (strcmp(MLX5_TXQ_INLINE_MIN, key) == 0) { 1744 config->txq_inline_min = tmp; 1745 } else if (strcmp(MLX5_TXQ_INLINE_MPW, key) == 0) { 1746 config->txq_inline_mpw = tmp; 1747 } else if (strcmp(MLX5_TXQS_MIN_INLINE, key) == 0) { 1748 config->txqs_inline = tmp; 1749 } else if (strcmp(MLX5_TXQS_MAX_VEC, key) == 0) { 1750 DRV_LOG(WARNING, "%s: deprecated parameter, ignored", key); 1751 } else if (strcmp(MLX5_TXQ_MPW_EN, key) == 0) { 1752 config->mps = !!tmp; 1753 } else if (strcmp(MLX5_TX_DB_NC, key) == 0) { 1754 if (tmp != MLX5_TXDB_CACHED && 1755 tmp != MLX5_TXDB_NCACHED && 1756 tmp != MLX5_TXDB_HEURISTIC) { 1757 DRV_LOG(ERR, "invalid Tx doorbell " 1758 "mapping parameter"); 1759 rte_errno = EINVAL; 1760 return -rte_errno; 1761 } 1762 config->dbnc = tmp; 1763 } else if (strcmp(MLX5_TXQ_MPW_HDR_DSEG_EN, key) == 0) { 1764 DRV_LOG(WARNING, "%s: deprecated parameter, ignored", key); 1765 } else if (strcmp(MLX5_TXQ_MAX_INLINE_LEN, key) == 0) { 1766 DRV_LOG(WARNING, "%s: deprecated parameter," 1767 " converted to txq_inline_mpw", key); 1768 config->txq_inline_mpw = tmp; 1769 } else if (strcmp(MLX5_TX_VEC_EN, key) == 0) { 1770 DRV_LOG(WARNING, "%s: deprecated parameter, ignored", key); 1771 } else if (strcmp(MLX5_RX_VEC_EN, key) == 0) { 1772 config->rx_vec_en = !!tmp; 1773 } else if (strcmp(MLX5_L3_VXLAN_EN, key) == 0) { 1774 config->l3_vxlan_en = !!tmp; 1775 } else if (strcmp(MLX5_VF_NL_EN, key) == 0) { 1776 config->vf_nl_en = !!tmp; 1777 } else if (strcmp(MLX5_DV_ESW_EN, key) == 0) { 1778 config->dv_esw_en = !!tmp; 1779 } else if (strcmp(MLX5_DV_FLOW_EN, key) == 0) { 1780 config->dv_flow_en = !!tmp; 1781 } else if (strcmp(MLX5_DV_XMETA_EN, key) == 0) { 1782 if (tmp != MLX5_XMETA_MODE_LEGACY && 1783 tmp != MLX5_XMETA_MODE_META16 && 1784 tmp != MLX5_XMETA_MODE_META32) { 1785 DRV_LOG(ERR, "invalid extensive " 1786 "metadata parameter"); 1787 rte_errno = EINVAL; 1788 return -rte_errno; 1789 } 1790 config->dv_xmeta_en = tmp; 1791 } else if (strcmp(MLX5_MR_EXT_MEMSEG_EN, key) == 0) { 1792 config->mr_ext_memseg_en = !!tmp; 1793 } else if (strcmp(MLX5_MAX_DUMP_FILES_NUM, key) == 0) { 1794 config->max_dump_files_num = tmp; 1795 } else if (strcmp(MLX5_LRO_TIMEOUT_USEC, key) == 0) { 1796 config->lro.timeout = tmp; 1797 } else if (strcmp(MLX5_CLASS_ARG_NAME, key) == 0) { 1798 DRV_LOG(DEBUG, "class argument is %s.", val); 1799 } else if (strcmp(MLX5_HP_BUF_SIZE, key) == 0) { 1800 config->log_hp_size = tmp; 1801 } else { 1802 DRV_LOG(WARNING, "%s: unknown parameter", key); 1803 rte_errno = EINVAL; 1804 return -rte_errno; 1805 } 1806 return 0; 1807 } 1808 1809 /** 1810 * Parse device parameters. 1811 * 1812 * @param config 1813 * Pointer to device configuration structure. 1814 * @param devargs 1815 * Device arguments structure. 1816 * 1817 * @return 1818 * 0 on success, a negative errno value otherwise and rte_errno is set. 1819 */ 1820 static int 1821 mlx5_args(struct mlx5_dev_config *config, struct rte_devargs *devargs) 1822 { 1823 const char **params = (const char *[]){ 1824 MLX5_RXQ_CQE_COMP_EN, 1825 MLX5_RXQ_CQE_PAD_EN, 1826 MLX5_RXQ_PKT_PAD_EN, 1827 MLX5_RX_MPRQ_EN, 1828 MLX5_RX_MPRQ_LOG_STRIDE_NUM, 1829 MLX5_RX_MPRQ_LOG_STRIDE_SIZE, 1830 MLX5_RX_MPRQ_MAX_MEMCPY_LEN, 1831 MLX5_RXQS_MIN_MPRQ, 1832 MLX5_TXQ_INLINE, 1833 MLX5_TXQ_INLINE_MIN, 1834 MLX5_TXQ_INLINE_MAX, 1835 MLX5_TXQ_INLINE_MPW, 1836 MLX5_TXQS_MIN_INLINE, 1837 MLX5_TXQS_MAX_VEC, 1838 MLX5_TXQ_MPW_EN, 1839 MLX5_TXQ_MPW_HDR_DSEG_EN, 1840 MLX5_TXQ_MAX_INLINE_LEN, 1841 MLX5_TX_DB_NC, 1842 MLX5_TX_VEC_EN, 1843 MLX5_RX_VEC_EN, 1844 MLX5_L3_VXLAN_EN, 1845 MLX5_VF_NL_EN, 1846 MLX5_DV_ESW_EN, 1847 MLX5_DV_FLOW_EN, 1848 MLX5_DV_XMETA_EN, 1849 MLX5_MR_EXT_MEMSEG_EN, 1850 MLX5_REPRESENTOR, 1851 MLX5_MAX_DUMP_FILES_NUM, 1852 MLX5_LRO_TIMEOUT_USEC, 1853 MLX5_CLASS_ARG_NAME, 1854 MLX5_HP_BUF_SIZE, 1855 NULL, 1856 }; 1857 struct rte_kvargs *kvlist; 1858 int ret = 0; 1859 int i; 1860 1861 if (devargs == NULL) 1862 return 0; 1863 /* Following UGLY cast is done to pass checkpatch. */ 1864 kvlist = rte_kvargs_parse(devargs->args, params); 1865 if (kvlist == NULL) { 1866 rte_errno = EINVAL; 1867 return -rte_errno; 1868 } 1869 /* Process parameters. */ 1870 for (i = 0; (params[i] != NULL); ++i) { 1871 if (rte_kvargs_count(kvlist, params[i])) { 1872 ret = rte_kvargs_process(kvlist, params[i], 1873 mlx5_args_check, config); 1874 if (ret) { 1875 rte_errno = EINVAL; 1876 rte_kvargs_free(kvlist); 1877 return -rte_errno; 1878 } 1879 } 1880 } 1881 rte_kvargs_free(kvlist); 1882 return 0; 1883 } 1884 1885 static struct rte_pci_driver mlx5_driver; 1886 1887 /** 1888 * PMD global initialization. 1889 * 1890 * Independent from individual device, this function initializes global 1891 * per-PMD data structures distinguishing primary and secondary processes. 1892 * Hence, each initialization is called once per a process. 1893 * 1894 * @return 1895 * 0 on success, a negative errno value otherwise and rte_errno is set. 1896 */ 1897 static int 1898 mlx5_init_once(void) 1899 { 1900 struct mlx5_shared_data *sd; 1901 struct mlx5_local_data *ld = &mlx5_local_data; 1902 int ret = 0; 1903 1904 if (mlx5_init_shared_data()) 1905 return -rte_errno; 1906 sd = mlx5_shared_data; 1907 MLX5_ASSERT(sd); 1908 rte_spinlock_lock(&sd->lock); 1909 switch (rte_eal_process_type()) { 1910 case RTE_PROC_PRIMARY: 1911 if (sd->init_done) 1912 break; 1913 LIST_INIT(&sd->mem_event_cb_list); 1914 rte_rwlock_init(&sd->mem_event_rwlock); 1915 rte_mem_event_callback_register("MLX5_MEM_EVENT_CB", 1916 mlx5_mr_mem_event_cb, NULL); 1917 ret = mlx5_mp_init_primary(MLX5_MP_NAME, 1918 mlx5_mp_primary_handle); 1919 if (ret) 1920 goto out; 1921 sd->init_done = true; 1922 break; 1923 case RTE_PROC_SECONDARY: 1924 if (ld->init_done) 1925 break; 1926 ret = mlx5_mp_init_secondary(MLX5_MP_NAME, 1927 mlx5_mp_secondary_handle); 1928 if (ret) 1929 goto out; 1930 ++sd->secondary_cnt; 1931 ld->init_done = true; 1932 break; 1933 default: 1934 break; 1935 } 1936 out: 1937 rte_spinlock_unlock(&sd->lock); 1938 return ret; 1939 } 1940 1941 /** 1942 * Configures the minimal amount of data to inline into WQE 1943 * while sending packets. 1944 * 1945 * - the txq_inline_min has the maximal priority, if this 1946 * key is specified in devargs 1947 * - if DevX is enabled the inline mode is queried from the 1948 * device (HCA attributes and NIC vport context if needed). 1949 * - otherwise L2 mode (18 bytes) is assumed for ConnectX-4/4 Lx 1950 * and none (0 bytes) for other NICs 1951 * 1952 * @param spawn 1953 * Verbs device parameters (name, port, switch_info) to spawn. 1954 * @param config 1955 * Device configuration parameters. 1956 */ 1957 static void 1958 mlx5_set_min_inline(struct mlx5_dev_spawn_data *spawn, 1959 struct mlx5_dev_config *config) 1960 { 1961 if (config->txq_inline_min != MLX5_ARG_UNSET) { 1962 /* Application defines size of inlined data explicitly. */ 1963 switch (spawn->pci_dev->id.device_id) { 1964 case PCI_DEVICE_ID_MELLANOX_CONNECTX4: 1965 case PCI_DEVICE_ID_MELLANOX_CONNECTX4VF: 1966 if (config->txq_inline_min < 1967 (int)MLX5_INLINE_HSIZE_L2) { 1968 DRV_LOG(DEBUG, 1969 "txq_inline_mix aligned to minimal" 1970 " ConnectX-4 required value %d", 1971 (int)MLX5_INLINE_HSIZE_L2); 1972 config->txq_inline_min = MLX5_INLINE_HSIZE_L2; 1973 } 1974 break; 1975 } 1976 goto exit; 1977 } 1978 if (config->hca_attr.eth_net_offloads) { 1979 /* We have DevX enabled, inline mode queried successfully. */ 1980 switch (config->hca_attr.wqe_inline_mode) { 1981 case MLX5_CAP_INLINE_MODE_L2: 1982 /* outer L2 header must be inlined. */ 1983 config->txq_inline_min = MLX5_INLINE_HSIZE_L2; 1984 goto exit; 1985 case MLX5_CAP_INLINE_MODE_NOT_REQUIRED: 1986 /* No inline data are required by NIC. */ 1987 config->txq_inline_min = MLX5_INLINE_HSIZE_NONE; 1988 config->hw_vlan_insert = 1989 config->hca_attr.wqe_vlan_insert; 1990 DRV_LOG(DEBUG, "Tx VLAN insertion is supported"); 1991 goto exit; 1992 case MLX5_CAP_INLINE_MODE_VPORT_CONTEXT: 1993 /* inline mode is defined by NIC vport context. */ 1994 if (!config->hca_attr.eth_virt) 1995 break; 1996 switch (config->hca_attr.vport_inline_mode) { 1997 case MLX5_INLINE_MODE_NONE: 1998 config->txq_inline_min = 1999 MLX5_INLINE_HSIZE_NONE; 2000 goto exit; 2001 case MLX5_INLINE_MODE_L2: 2002 config->txq_inline_min = 2003 MLX5_INLINE_HSIZE_L2; 2004 goto exit; 2005 case MLX5_INLINE_MODE_IP: 2006 config->txq_inline_min = 2007 MLX5_INLINE_HSIZE_L3; 2008 goto exit; 2009 case MLX5_INLINE_MODE_TCP_UDP: 2010 config->txq_inline_min = 2011 MLX5_INLINE_HSIZE_L4; 2012 goto exit; 2013 case MLX5_INLINE_MODE_INNER_L2: 2014 config->txq_inline_min = 2015 MLX5_INLINE_HSIZE_INNER_L2; 2016 goto exit; 2017 case MLX5_INLINE_MODE_INNER_IP: 2018 config->txq_inline_min = 2019 MLX5_INLINE_HSIZE_INNER_L3; 2020 goto exit; 2021 case MLX5_INLINE_MODE_INNER_TCP_UDP: 2022 config->txq_inline_min = 2023 MLX5_INLINE_HSIZE_INNER_L4; 2024 goto exit; 2025 } 2026 } 2027 } 2028 /* 2029 * We get here if we are unable to deduce 2030 * inline data size with DevX. Try PCI ID 2031 * to determine old NICs. 2032 */ 2033 switch (spawn->pci_dev->id.device_id) { 2034 case PCI_DEVICE_ID_MELLANOX_CONNECTX4: 2035 case PCI_DEVICE_ID_MELLANOX_CONNECTX4VF: 2036 case PCI_DEVICE_ID_MELLANOX_CONNECTX4LX: 2037 case PCI_DEVICE_ID_MELLANOX_CONNECTX4LXVF: 2038 config->txq_inline_min = MLX5_INLINE_HSIZE_L2; 2039 config->hw_vlan_insert = 0; 2040 break; 2041 case PCI_DEVICE_ID_MELLANOX_CONNECTX5: 2042 case PCI_DEVICE_ID_MELLANOX_CONNECTX5VF: 2043 case PCI_DEVICE_ID_MELLANOX_CONNECTX5EX: 2044 case PCI_DEVICE_ID_MELLANOX_CONNECTX5EXVF: 2045 /* 2046 * These NICs support VLAN insertion from WQE and 2047 * report the wqe_vlan_insert flag. But there is the bug 2048 * and PFC control may be broken, so disable feature. 2049 */ 2050 config->hw_vlan_insert = 0; 2051 config->txq_inline_min = MLX5_INLINE_HSIZE_NONE; 2052 break; 2053 default: 2054 config->txq_inline_min = MLX5_INLINE_HSIZE_NONE; 2055 break; 2056 } 2057 exit: 2058 DRV_LOG(DEBUG, "min tx inline configured: %d", config->txq_inline_min); 2059 } 2060 2061 /** 2062 * Configures the metadata mask fields in the shared context. 2063 * 2064 * @param [in] dev 2065 * Pointer to Ethernet device. 2066 */ 2067 static void 2068 mlx5_set_metadata_mask(struct rte_eth_dev *dev) 2069 { 2070 struct mlx5_priv *priv = dev->data->dev_private; 2071 struct mlx5_ibv_shared *sh = priv->sh; 2072 uint32_t meta, mark, reg_c0; 2073 2074 reg_c0 = ~priv->vport_meta_mask; 2075 switch (priv->config.dv_xmeta_en) { 2076 case MLX5_XMETA_MODE_LEGACY: 2077 meta = UINT32_MAX; 2078 mark = MLX5_FLOW_MARK_MASK; 2079 break; 2080 case MLX5_XMETA_MODE_META16: 2081 meta = reg_c0 >> rte_bsf32(reg_c0); 2082 mark = MLX5_FLOW_MARK_MASK; 2083 break; 2084 case MLX5_XMETA_MODE_META32: 2085 meta = UINT32_MAX; 2086 mark = (reg_c0 >> rte_bsf32(reg_c0)) & MLX5_FLOW_MARK_MASK; 2087 break; 2088 default: 2089 meta = 0; 2090 mark = 0; 2091 MLX5_ASSERT(false); 2092 break; 2093 } 2094 if (sh->dv_mark_mask && sh->dv_mark_mask != mark) 2095 DRV_LOG(WARNING, "metadata MARK mask mismatche %08X:%08X", 2096 sh->dv_mark_mask, mark); 2097 else 2098 sh->dv_mark_mask = mark; 2099 if (sh->dv_meta_mask && sh->dv_meta_mask != meta) 2100 DRV_LOG(WARNING, "metadata META mask mismatche %08X:%08X", 2101 sh->dv_meta_mask, meta); 2102 else 2103 sh->dv_meta_mask = meta; 2104 if (sh->dv_regc0_mask && sh->dv_regc0_mask != reg_c0) 2105 DRV_LOG(WARNING, "metadata reg_c0 mask mismatche %08X:%08X", 2106 sh->dv_meta_mask, reg_c0); 2107 else 2108 sh->dv_regc0_mask = reg_c0; 2109 DRV_LOG(DEBUG, "metadata mode %u", priv->config.dv_xmeta_en); 2110 DRV_LOG(DEBUG, "metadata MARK mask %08X", sh->dv_mark_mask); 2111 DRV_LOG(DEBUG, "metadata META mask %08X", sh->dv_meta_mask); 2112 DRV_LOG(DEBUG, "metadata reg_c0 mask %08X", sh->dv_regc0_mask); 2113 } 2114 2115 /** 2116 * Allocate page of door-bells and register it using DevX API. 2117 * 2118 * @param [in] dev 2119 * Pointer to Ethernet device. 2120 * 2121 * @return 2122 * Pointer to new page on success, NULL otherwise. 2123 */ 2124 static struct mlx5_devx_dbr_page * 2125 mlx5_alloc_dbr_page(struct rte_eth_dev *dev) 2126 { 2127 struct mlx5_priv *priv = dev->data->dev_private; 2128 struct mlx5_devx_dbr_page *page; 2129 2130 /* Allocate space for door-bell page and management data. */ 2131 page = rte_calloc_socket(__func__, 1, sizeof(struct mlx5_devx_dbr_page), 2132 RTE_CACHE_LINE_SIZE, dev->device->numa_node); 2133 if (!page) { 2134 DRV_LOG(ERR, "port %u cannot allocate dbr page", 2135 dev->data->port_id); 2136 return NULL; 2137 } 2138 /* Register allocated memory. */ 2139 page->umem = mlx5_glue->devx_umem_reg(priv->sh->ctx, page->dbrs, 2140 MLX5_DBR_PAGE_SIZE, 0); 2141 if (!page->umem) { 2142 DRV_LOG(ERR, "port %u cannot umem reg dbr page", 2143 dev->data->port_id); 2144 rte_free(page); 2145 return NULL; 2146 } 2147 return page; 2148 } 2149 2150 /** 2151 * Find the next available door-bell, allocate new page if needed. 2152 * 2153 * @param [in] dev 2154 * Pointer to Ethernet device. 2155 * @param [out] dbr_page 2156 * Door-bell page containing the page data. 2157 * 2158 * @return 2159 * Door-bell address offset on success, a negative error value otherwise. 2160 */ 2161 int64_t 2162 mlx5_get_dbr(struct rte_eth_dev *dev, struct mlx5_devx_dbr_page **dbr_page) 2163 { 2164 struct mlx5_priv *priv = dev->data->dev_private; 2165 struct mlx5_devx_dbr_page *page = NULL; 2166 uint32_t i, j; 2167 2168 LIST_FOREACH(page, &priv->dbrpgs, next) 2169 if (page->dbr_count < MLX5_DBR_PER_PAGE) 2170 break; 2171 if (!page) { /* No page with free door-bell exists. */ 2172 page = mlx5_alloc_dbr_page(dev); 2173 if (!page) /* Failed to allocate new page. */ 2174 return (-1); 2175 LIST_INSERT_HEAD(&priv->dbrpgs, page, next); 2176 } 2177 /* Loop to find bitmap part with clear bit. */ 2178 for (i = 0; 2179 i < MLX5_DBR_BITMAP_SIZE && page->dbr_bitmap[i] == UINT64_MAX; 2180 i++) 2181 ; /* Empty. */ 2182 /* Find the first clear bit. */ 2183 MLX5_ASSERT(i < MLX5_DBR_BITMAP_SIZE); 2184 j = rte_bsf64(~page->dbr_bitmap[i]); 2185 page->dbr_bitmap[i] |= (1 << j); 2186 page->dbr_count++; 2187 *dbr_page = page; 2188 return (((i * 64) + j) * sizeof(uint64_t)); 2189 } 2190 2191 /** 2192 * Release a door-bell record. 2193 * 2194 * @param [in] dev 2195 * Pointer to Ethernet device. 2196 * @param [in] umem_id 2197 * UMEM ID of page containing the door-bell record to release. 2198 * @param [in] offset 2199 * Offset of door-bell record in page. 2200 * 2201 * @return 2202 * 0 on success, a negative error value otherwise. 2203 */ 2204 int32_t 2205 mlx5_release_dbr(struct rte_eth_dev *dev, uint32_t umem_id, uint64_t offset) 2206 { 2207 struct mlx5_priv *priv = dev->data->dev_private; 2208 struct mlx5_devx_dbr_page *page = NULL; 2209 int ret = 0; 2210 2211 LIST_FOREACH(page, &priv->dbrpgs, next) 2212 /* Find the page this address belongs to. */ 2213 if (page->umem->umem_id == umem_id) 2214 break; 2215 if (!page) 2216 return -EINVAL; 2217 page->dbr_count--; 2218 if (!page->dbr_count) { 2219 /* Page not used, free it and remove from list. */ 2220 LIST_REMOVE(page, next); 2221 if (page->umem) 2222 ret = -mlx5_glue->devx_umem_dereg(page->umem); 2223 rte_free(page); 2224 } else { 2225 /* Mark in bitmap that this door-bell is not in use. */ 2226 offset /= MLX5_DBR_SIZE; 2227 int i = offset / 64; 2228 int j = offset % 64; 2229 2230 page->dbr_bitmap[i] &= ~(1 << j); 2231 } 2232 return ret; 2233 } 2234 2235 int 2236 rte_pmd_mlx5_get_dyn_flag_names(char *names[], unsigned int n) 2237 { 2238 static const char *const dynf_names[] = { 2239 RTE_PMD_MLX5_FINE_GRANULARITY_INLINE, 2240 RTE_MBUF_DYNFLAG_METADATA_NAME 2241 }; 2242 unsigned int i; 2243 2244 if (n < RTE_DIM(dynf_names)) 2245 return -ENOMEM; 2246 for (i = 0; i < RTE_DIM(dynf_names); i++) { 2247 if (names[i] == NULL) 2248 return -EINVAL; 2249 strcpy(names[i], dynf_names[i]); 2250 } 2251 return RTE_DIM(dynf_names); 2252 } 2253 2254 /** 2255 * Check sibling device configurations. 2256 * 2257 * Sibling devices sharing the Infiniband device context 2258 * should have compatible configurations. This regards 2259 * representors and bonding slaves. 2260 * 2261 * @param priv 2262 * Private device descriptor. 2263 * @param config 2264 * Configuration of the device is going to be created. 2265 * 2266 * @return 2267 * 0 on success, EINVAL otherwise 2268 */ 2269 static int 2270 mlx5_dev_check_sibling_config(struct mlx5_priv *priv, 2271 struct mlx5_dev_config *config) 2272 { 2273 struct mlx5_ibv_shared *sh = priv->sh; 2274 struct mlx5_dev_config *sh_conf = NULL; 2275 uint16_t port_id; 2276 2277 MLX5_ASSERT(sh); 2278 /* Nothing to compare for the single/first device. */ 2279 if (sh->refcnt == 1) 2280 return 0; 2281 /* Find the device with shared context. */ 2282 MLX5_ETH_FOREACH_DEV(port_id, priv->pci_dev) { 2283 struct mlx5_priv *opriv = 2284 rte_eth_devices[port_id].data->dev_private; 2285 2286 if (opriv && opriv != priv && opriv->sh == sh) { 2287 sh_conf = &opriv->config; 2288 break; 2289 } 2290 } 2291 if (!sh_conf) 2292 return 0; 2293 if (sh_conf->dv_flow_en ^ config->dv_flow_en) { 2294 DRV_LOG(ERR, "\"dv_flow_en\" configuration mismatch" 2295 " for shared %s context", sh->ibdev_name); 2296 rte_errno = EINVAL; 2297 return rte_errno; 2298 } 2299 if (sh_conf->dv_xmeta_en ^ config->dv_xmeta_en) { 2300 DRV_LOG(ERR, "\"dv_xmeta_en\" configuration mismatch" 2301 " for shared %s context", sh->ibdev_name); 2302 rte_errno = EINVAL; 2303 return rte_errno; 2304 } 2305 return 0; 2306 } 2307 /** 2308 * Spawn an Ethernet device from Verbs information. 2309 * 2310 * @param dpdk_dev 2311 * Backing DPDK device. 2312 * @param spawn 2313 * Verbs device parameters (name, port, switch_info) to spawn. 2314 * @param config 2315 * Device configuration parameters. 2316 * 2317 * @return 2318 * A valid Ethernet device object on success, NULL otherwise and rte_errno 2319 * is set. The following errors are defined: 2320 * 2321 * EBUSY: device is not supposed to be spawned. 2322 * EEXIST: device is already spawned 2323 */ 2324 static struct rte_eth_dev * 2325 mlx5_dev_spawn(struct rte_device *dpdk_dev, 2326 struct mlx5_dev_spawn_data *spawn, 2327 struct mlx5_dev_config config) 2328 { 2329 const struct mlx5_switch_info *switch_info = &spawn->info; 2330 struct mlx5_ibv_shared *sh = NULL; 2331 struct ibv_port_attr port_attr; 2332 struct mlx5dv_context dv_attr = { .comp_mask = 0 }; 2333 struct rte_eth_dev *eth_dev = NULL; 2334 struct mlx5_priv *priv = NULL; 2335 int err = 0; 2336 unsigned int hw_padding = 0; 2337 unsigned int mps; 2338 unsigned int cqe_comp; 2339 unsigned int cqe_pad = 0; 2340 unsigned int tunnel_en = 0; 2341 unsigned int mpls_en = 0; 2342 unsigned int swp = 0; 2343 unsigned int mprq = 0; 2344 unsigned int mprq_min_stride_size_n = 0; 2345 unsigned int mprq_max_stride_size_n = 0; 2346 unsigned int mprq_min_stride_num_n = 0; 2347 unsigned int mprq_max_stride_num_n = 0; 2348 struct rte_ether_addr mac; 2349 char name[RTE_ETH_NAME_MAX_LEN]; 2350 int own_domain_id = 0; 2351 uint16_t port_id; 2352 unsigned int i; 2353 #ifdef HAVE_MLX5DV_DR_DEVX_PORT 2354 struct mlx5dv_devx_port devx_port = { .comp_mask = 0 }; 2355 #endif 2356 2357 /* Determine if this port representor is supposed to be spawned. */ 2358 if (switch_info->representor && dpdk_dev->devargs) { 2359 struct rte_eth_devargs eth_da; 2360 2361 err = rte_eth_devargs_parse(dpdk_dev->devargs->args, ð_da); 2362 if (err) { 2363 rte_errno = -err; 2364 DRV_LOG(ERR, "failed to process device arguments: %s", 2365 strerror(rte_errno)); 2366 return NULL; 2367 } 2368 for (i = 0; i < eth_da.nb_representor_ports; ++i) 2369 if (eth_da.representor_ports[i] == 2370 (uint16_t)switch_info->port_name) 2371 break; 2372 if (i == eth_da.nb_representor_ports) { 2373 rte_errno = EBUSY; 2374 return NULL; 2375 } 2376 } 2377 /* Build device name. */ 2378 if (spawn->pf_bond < 0) { 2379 /* Single device. */ 2380 if (!switch_info->representor) 2381 strlcpy(name, dpdk_dev->name, sizeof(name)); 2382 else 2383 snprintf(name, sizeof(name), "%s_representor_%u", 2384 dpdk_dev->name, switch_info->port_name); 2385 } else { 2386 /* Bonding device. */ 2387 if (!switch_info->representor) 2388 snprintf(name, sizeof(name), "%s_%s", 2389 dpdk_dev->name, spawn->ibv_dev->name); 2390 else 2391 snprintf(name, sizeof(name), "%s_%s_representor_%u", 2392 dpdk_dev->name, spawn->ibv_dev->name, 2393 switch_info->port_name); 2394 } 2395 /* check if the device is already spawned */ 2396 if (rte_eth_dev_get_port_by_name(name, &port_id) == 0) { 2397 rte_errno = EEXIST; 2398 return NULL; 2399 } 2400 DRV_LOG(DEBUG, "naming Ethernet device \"%s\"", name); 2401 if (rte_eal_process_type() == RTE_PROC_SECONDARY) { 2402 struct mlx5_mp_id mp_id; 2403 2404 eth_dev = rte_eth_dev_attach_secondary(name); 2405 if (eth_dev == NULL) { 2406 DRV_LOG(ERR, "can not attach rte ethdev"); 2407 rte_errno = ENOMEM; 2408 return NULL; 2409 } 2410 eth_dev->device = dpdk_dev; 2411 eth_dev->dev_ops = &mlx5_dev_sec_ops; 2412 err = mlx5_proc_priv_init(eth_dev); 2413 if (err) 2414 return NULL; 2415 mp_id.port_id = eth_dev->data->port_id; 2416 strlcpy(mp_id.name, MLX5_MP_NAME, RTE_MP_MAX_NAME_LEN); 2417 /* Receive command fd from primary process */ 2418 err = mlx5_mp_req_verbs_cmd_fd(&mp_id); 2419 if (err < 0) 2420 return NULL; 2421 /* Remap UAR for Tx queues. */ 2422 err = mlx5_tx_uar_init_secondary(eth_dev, err); 2423 if (err) 2424 return NULL; 2425 /* 2426 * Ethdev pointer is still required as input since 2427 * the primary device is not accessible from the 2428 * secondary process. 2429 */ 2430 eth_dev->rx_pkt_burst = mlx5_select_rx_function(eth_dev); 2431 eth_dev->tx_pkt_burst = mlx5_select_tx_function(eth_dev); 2432 return eth_dev; 2433 } 2434 /* 2435 * Some parameters ("tx_db_nc" in particularly) are needed in 2436 * advance to create dv/verbs device context. We proceed the 2437 * devargs here to get ones, and later proceed devargs again 2438 * to override some hardware settings. 2439 */ 2440 err = mlx5_args(&config, dpdk_dev->devargs); 2441 if (err) { 2442 err = rte_errno; 2443 DRV_LOG(ERR, "failed to process device arguments: %s", 2444 strerror(rte_errno)); 2445 goto error; 2446 } 2447 sh = mlx5_alloc_shared_ibctx(spawn, &config); 2448 if (!sh) 2449 return NULL; 2450 config.devx = sh->devx; 2451 #ifdef HAVE_MLX5DV_DR_ACTION_DEST_DEVX_TIR 2452 config.dest_tir = 1; 2453 #endif 2454 #ifdef HAVE_IBV_MLX5_MOD_SWP 2455 dv_attr.comp_mask |= MLX5DV_CONTEXT_MASK_SWP; 2456 #endif 2457 /* 2458 * Multi-packet send is supported by ConnectX-4 Lx PF as well 2459 * as all ConnectX-5 devices. 2460 */ 2461 #ifdef HAVE_IBV_DEVICE_TUNNEL_SUPPORT 2462 dv_attr.comp_mask |= MLX5DV_CONTEXT_MASK_TUNNEL_OFFLOADS; 2463 #endif 2464 #ifdef HAVE_IBV_DEVICE_STRIDING_RQ_SUPPORT 2465 dv_attr.comp_mask |= MLX5DV_CONTEXT_MASK_STRIDING_RQ; 2466 #endif 2467 mlx5_glue->dv_query_device(sh->ctx, &dv_attr); 2468 if (dv_attr.flags & MLX5DV_CONTEXT_FLAGS_MPW_ALLOWED) { 2469 if (dv_attr.flags & MLX5DV_CONTEXT_FLAGS_ENHANCED_MPW) { 2470 DRV_LOG(DEBUG, "enhanced MPW is supported"); 2471 mps = MLX5_MPW_ENHANCED; 2472 } else { 2473 DRV_LOG(DEBUG, "MPW is supported"); 2474 mps = MLX5_MPW; 2475 } 2476 } else { 2477 DRV_LOG(DEBUG, "MPW isn't supported"); 2478 mps = MLX5_MPW_DISABLED; 2479 } 2480 #ifdef HAVE_IBV_MLX5_MOD_SWP 2481 if (dv_attr.comp_mask & MLX5DV_CONTEXT_MASK_SWP) 2482 swp = dv_attr.sw_parsing_caps.sw_parsing_offloads; 2483 DRV_LOG(DEBUG, "SWP support: %u", swp); 2484 #endif 2485 config.swp = !!swp; 2486 #ifdef HAVE_IBV_DEVICE_STRIDING_RQ_SUPPORT 2487 if (dv_attr.comp_mask & MLX5DV_CONTEXT_MASK_STRIDING_RQ) { 2488 struct mlx5dv_striding_rq_caps mprq_caps = 2489 dv_attr.striding_rq_caps; 2490 2491 DRV_LOG(DEBUG, "\tmin_single_stride_log_num_of_bytes: %d", 2492 mprq_caps.min_single_stride_log_num_of_bytes); 2493 DRV_LOG(DEBUG, "\tmax_single_stride_log_num_of_bytes: %d", 2494 mprq_caps.max_single_stride_log_num_of_bytes); 2495 DRV_LOG(DEBUG, "\tmin_single_wqe_log_num_of_strides: %d", 2496 mprq_caps.min_single_wqe_log_num_of_strides); 2497 DRV_LOG(DEBUG, "\tmax_single_wqe_log_num_of_strides: %d", 2498 mprq_caps.max_single_wqe_log_num_of_strides); 2499 DRV_LOG(DEBUG, "\tsupported_qpts: %d", 2500 mprq_caps.supported_qpts); 2501 DRV_LOG(DEBUG, "device supports Multi-Packet RQ"); 2502 mprq = 1; 2503 mprq_min_stride_size_n = 2504 mprq_caps.min_single_stride_log_num_of_bytes; 2505 mprq_max_stride_size_n = 2506 mprq_caps.max_single_stride_log_num_of_bytes; 2507 mprq_min_stride_num_n = 2508 mprq_caps.min_single_wqe_log_num_of_strides; 2509 mprq_max_stride_num_n = 2510 mprq_caps.max_single_wqe_log_num_of_strides; 2511 } 2512 #endif 2513 if (RTE_CACHE_LINE_SIZE == 128 && 2514 !(dv_attr.flags & MLX5DV_CONTEXT_FLAGS_CQE_128B_COMP)) 2515 cqe_comp = 0; 2516 else 2517 cqe_comp = 1; 2518 config.cqe_comp = cqe_comp; 2519 #ifdef HAVE_IBV_MLX5_MOD_CQE_128B_PAD 2520 /* Whether device supports 128B Rx CQE padding. */ 2521 cqe_pad = RTE_CACHE_LINE_SIZE == 128 && 2522 (dv_attr.flags & MLX5DV_CONTEXT_FLAGS_CQE_128B_PAD); 2523 #endif 2524 #ifdef HAVE_IBV_DEVICE_TUNNEL_SUPPORT 2525 if (dv_attr.comp_mask & MLX5DV_CONTEXT_MASK_TUNNEL_OFFLOADS) { 2526 tunnel_en = ((dv_attr.tunnel_offloads_caps & 2527 MLX5DV_RAW_PACKET_CAP_TUNNELED_OFFLOAD_VXLAN) && 2528 (dv_attr.tunnel_offloads_caps & 2529 MLX5DV_RAW_PACKET_CAP_TUNNELED_OFFLOAD_GRE) && 2530 (dv_attr.tunnel_offloads_caps & 2531 MLX5DV_RAW_PACKET_CAP_TUNNELED_OFFLOAD_GENEVE)); 2532 } 2533 DRV_LOG(DEBUG, "tunnel offloading is %ssupported", 2534 tunnel_en ? "" : "not "); 2535 #else 2536 DRV_LOG(WARNING, 2537 "tunnel offloading disabled due to old OFED/rdma-core version"); 2538 #endif 2539 config.tunnel_en = tunnel_en; 2540 #ifdef HAVE_IBV_DEVICE_MPLS_SUPPORT 2541 mpls_en = ((dv_attr.tunnel_offloads_caps & 2542 MLX5DV_RAW_PACKET_CAP_TUNNELED_OFFLOAD_CW_MPLS_OVER_GRE) && 2543 (dv_attr.tunnel_offloads_caps & 2544 MLX5DV_RAW_PACKET_CAP_TUNNELED_OFFLOAD_CW_MPLS_OVER_UDP)); 2545 DRV_LOG(DEBUG, "MPLS over GRE/UDP tunnel offloading is %ssupported", 2546 mpls_en ? "" : "not "); 2547 #else 2548 DRV_LOG(WARNING, "MPLS over GRE/UDP tunnel offloading disabled due to" 2549 " old OFED/rdma-core version or firmware configuration"); 2550 #endif 2551 config.mpls_en = mpls_en; 2552 /* Check port status. */ 2553 err = mlx5_glue->query_port(sh->ctx, spawn->ibv_port, &port_attr); 2554 if (err) { 2555 DRV_LOG(ERR, "port query failed: %s", strerror(err)); 2556 goto error; 2557 } 2558 if (port_attr.link_layer != IBV_LINK_LAYER_ETHERNET) { 2559 DRV_LOG(ERR, "port is not configured in Ethernet mode"); 2560 err = EINVAL; 2561 goto error; 2562 } 2563 if (port_attr.state != IBV_PORT_ACTIVE) 2564 DRV_LOG(DEBUG, "port is not active: \"%s\" (%d)", 2565 mlx5_glue->port_state_str(port_attr.state), 2566 port_attr.state); 2567 /* Allocate private eth device data. */ 2568 priv = rte_zmalloc("ethdev private structure", 2569 sizeof(*priv), 2570 RTE_CACHE_LINE_SIZE); 2571 if (priv == NULL) { 2572 DRV_LOG(ERR, "priv allocation failure"); 2573 err = ENOMEM; 2574 goto error; 2575 } 2576 priv->sh = sh; 2577 priv->ibv_port = spawn->ibv_port; 2578 priv->pci_dev = spawn->pci_dev; 2579 priv->mtu = RTE_ETHER_MTU; 2580 priv->mp_id.port_id = port_id; 2581 strlcpy(priv->mp_id.name, MLX5_MP_NAME, RTE_MP_MAX_NAME_LEN); 2582 #ifndef RTE_ARCH_64 2583 /* Initialize UAR access locks for 32bit implementations. */ 2584 rte_spinlock_init(&priv->uar_lock_cq); 2585 for (i = 0; i < MLX5_UAR_PAGE_NUM_MAX; i++) 2586 rte_spinlock_init(&priv->uar_lock[i]); 2587 #endif 2588 /* Some internal functions rely on Netlink sockets, open them now. */ 2589 priv->nl_socket_rdma = mlx5_nl_init(NETLINK_RDMA); 2590 priv->nl_socket_route = mlx5_nl_init(NETLINK_ROUTE); 2591 priv->representor = !!switch_info->representor; 2592 priv->master = !!switch_info->master; 2593 priv->domain_id = RTE_ETH_DEV_SWITCH_DOMAIN_ID_INVALID; 2594 priv->vport_meta_tag = 0; 2595 priv->vport_meta_mask = 0; 2596 priv->pf_bond = spawn->pf_bond; 2597 #ifdef HAVE_MLX5DV_DR_DEVX_PORT 2598 /* 2599 * The DevX port query API is implemented. E-Switch may use 2600 * either vport or reg_c[0] metadata register to match on 2601 * vport index. The engaged part of metadata register is 2602 * defined by mask. 2603 */ 2604 if (switch_info->representor || switch_info->master) { 2605 devx_port.comp_mask = MLX5DV_DEVX_PORT_VPORT | 2606 MLX5DV_DEVX_PORT_MATCH_REG_C_0; 2607 err = mlx5_glue->devx_port_query(sh->ctx, spawn->ibv_port, 2608 &devx_port); 2609 if (err) { 2610 DRV_LOG(WARNING, 2611 "can't query devx port %d on device %s", 2612 spawn->ibv_port, spawn->ibv_dev->name); 2613 devx_port.comp_mask = 0; 2614 } 2615 } 2616 if (devx_port.comp_mask & MLX5DV_DEVX_PORT_MATCH_REG_C_0) { 2617 priv->vport_meta_tag = devx_port.reg_c_0.value; 2618 priv->vport_meta_mask = devx_port.reg_c_0.mask; 2619 if (!priv->vport_meta_mask) { 2620 DRV_LOG(ERR, "vport zero mask for port %d" 2621 " on bonding device %s", 2622 spawn->ibv_port, spawn->ibv_dev->name); 2623 err = ENOTSUP; 2624 goto error; 2625 } 2626 if (priv->vport_meta_tag & ~priv->vport_meta_mask) { 2627 DRV_LOG(ERR, "invalid vport tag for port %d" 2628 " on bonding device %s", 2629 spawn->ibv_port, spawn->ibv_dev->name); 2630 err = ENOTSUP; 2631 goto error; 2632 } 2633 } 2634 if (devx_port.comp_mask & MLX5DV_DEVX_PORT_VPORT) { 2635 priv->vport_id = devx_port.vport_num; 2636 } else if (spawn->pf_bond >= 0) { 2637 DRV_LOG(ERR, "can't deduce vport index for port %d" 2638 " on bonding device %s", 2639 spawn->ibv_port, spawn->ibv_dev->name); 2640 err = ENOTSUP; 2641 goto error; 2642 } else { 2643 /* Suppose vport index in compatible way. */ 2644 priv->vport_id = switch_info->representor ? 2645 switch_info->port_name + 1 : -1; 2646 } 2647 #else 2648 /* 2649 * Kernel/rdma_core support single E-Switch per PF configurations 2650 * only and vport_id field contains the vport index for 2651 * associated VF, which is deduced from representor port name. 2652 * For example, let's have the IB device port 10, it has 2653 * attached network device eth0, which has port name attribute 2654 * pf0vf2, we can deduce the VF number as 2, and set vport index 2655 * as 3 (2+1). This assigning schema should be changed if the 2656 * multiple E-Switch instances per PF configurations or/and PCI 2657 * subfunctions are added. 2658 */ 2659 priv->vport_id = switch_info->representor ? 2660 switch_info->port_name + 1 : -1; 2661 #endif 2662 /* representor_id field keeps the unmodified VF index. */ 2663 priv->representor_id = switch_info->representor ? 2664 switch_info->port_name : -1; 2665 /* 2666 * Look for sibling devices in order to reuse their switch domain 2667 * if any, otherwise allocate one. 2668 */ 2669 MLX5_ETH_FOREACH_DEV(port_id, priv->pci_dev) { 2670 const struct mlx5_priv *opriv = 2671 rte_eth_devices[port_id].data->dev_private; 2672 2673 if (!opriv || 2674 opriv->sh != priv->sh || 2675 opriv->domain_id == 2676 RTE_ETH_DEV_SWITCH_DOMAIN_ID_INVALID) 2677 continue; 2678 priv->domain_id = opriv->domain_id; 2679 break; 2680 } 2681 if (priv->domain_id == RTE_ETH_DEV_SWITCH_DOMAIN_ID_INVALID) { 2682 err = rte_eth_switch_domain_alloc(&priv->domain_id); 2683 if (err) { 2684 err = rte_errno; 2685 DRV_LOG(ERR, "unable to allocate switch domain: %s", 2686 strerror(rte_errno)); 2687 goto error; 2688 } 2689 own_domain_id = 1; 2690 } 2691 /* Override some values set by hardware configuration. */ 2692 mlx5_args(&config, dpdk_dev->devargs); 2693 err = mlx5_dev_check_sibling_config(priv, &config); 2694 if (err) 2695 goto error; 2696 config.hw_csum = !!(sh->device_attr.device_cap_flags_ex & 2697 IBV_DEVICE_RAW_IP_CSUM); 2698 DRV_LOG(DEBUG, "checksum offloading is %ssupported", 2699 (config.hw_csum ? "" : "not ")); 2700 #if !defined(HAVE_IBV_DEVICE_COUNTERS_SET_V42) && \ 2701 !defined(HAVE_IBV_DEVICE_COUNTERS_SET_V45) 2702 DRV_LOG(DEBUG, "counters are not supported"); 2703 #endif 2704 #if !defined(HAVE_IBV_FLOW_DV_SUPPORT) || !defined(HAVE_MLX5DV_DR) 2705 if (config.dv_flow_en) { 2706 DRV_LOG(WARNING, "DV flow is not supported"); 2707 config.dv_flow_en = 0; 2708 } 2709 #endif 2710 config.ind_table_max_size = 2711 sh->device_attr.rss_caps.max_rwq_indirection_table_size; 2712 /* 2713 * Remove this check once DPDK supports larger/variable 2714 * indirection tables. 2715 */ 2716 if (config.ind_table_max_size > (unsigned int)ETH_RSS_RETA_SIZE_512) 2717 config.ind_table_max_size = ETH_RSS_RETA_SIZE_512; 2718 DRV_LOG(DEBUG, "maximum Rx indirection table size is %u", 2719 config.ind_table_max_size); 2720 config.hw_vlan_strip = !!(sh->device_attr.raw_packet_caps & 2721 IBV_RAW_PACKET_CAP_CVLAN_STRIPPING); 2722 DRV_LOG(DEBUG, "VLAN stripping is %ssupported", 2723 (config.hw_vlan_strip ? "" : "not ")); 2724 config.hw_fcs_strip = !!(sh->device_attr.raw_packet_caps & 2725 IBV_RAW_PACKET_CAP_SCATTER_FCS); 2726 DRV_LOG(DEBUG, "FCS stripping configuration is %ssupported", 2727 (config.hw_fcs_strip ? "" : "not ")); 2728 #if defined(HAVE_IBV_WQ_FLAG_RX_END_PADDING) 2729 hw_padding = !!sh->device_attr.rx_pad_end_addr_align; 2730 #elif defined(HAVE_IBV_WQ_FLAGS_PCI_WRITE_END_PADDING) 2731 hw_padding = !!(sh->device_attr.device_cap_flags_ex & 2732 IBV_DEVICE_PCI_WRITE_END_PADDING); 2733 #endif 2734 if (config.hw_padding && !hw_padding) { 2735 DRV_LOG(DEBUG, "Rx end alignment padding isn't supported"); 2736 config.hw_padding = 0; 2737 } else if (config.hw_padding) { 2738 DRV_LOG(DEBUG, "Rx end alignment padding is enabled"); 2739 } 2740 config.tso = (sh->device_attr.tso_caps.max_tso > 0 && 2741 (sh->device_attr.tso_caps.supported_qpts & 2742 (1 << IBV_QPT_RAW_PACKET))); 2743 if (config.tso) 2744 config.tso_max_payload_sz = sh->device_attr.tso_caps.max_tso; 2745 /* 2746 * MPW is disabled by default, while the Enhanced MPW is enabled 2747 * by default. 2748 */ 2749 if (config.mps == MLX5_ARG_UNSET) 2750 config.mps = (mps == MLX5_MPW_ENHANCED) ? MLX5_MPW_ENHANCED : 2751 MLX5_MPW_DISABLED; 2752 else 2753 config.mps = config.mps ? mps : MLX5_MPW_DISABLED; 2754 DRV_LOG(INFO, "%sMPS is %s", 2755 config.mps == MLX5_MPW_ENHANCED ? "enhanced " : 2756 config.mps == MLX5_MPW ? "legacy " : "", 2757 config.mps != MLX5_MPW_DISABLED ? "enabled" : "disabled"); 2758 if (config.cqe_comp && !cqe_comp) { 2759 DRV_LOG(WARNING, "Rx CQE compression isn't supported"); 2760 config.cqe_comp = 0; 2761 } 2762 if (config.cqe_pad && !cqe_pad) { 2763 DRV_LOG(WARNING, "Rx CQE padding isn't supported"); 2764 config.cqe_pad = 0; 2765 } else if (config.cqe_pad) { 2766 DRV_LOG(INFO, "Rx CQE padding is enabled"); 2767 } 2768 if (config.devx) { 2769 priv->counter_fallback = 0; 2770 err = mlx5_devx_cmd_query_hca_attr(sh->ctx, &config.hca_attr); 2771 if (err) { 2772 err = -err; 2773 goto error; 2774 } 2775 if (!config.hca_attr.flow_counters_dump) 2776 priv->counter_fallback = 1; 2777 #ifndef HAVE_IBV_DEVX_ASYNC 2778 priv->counter_fallback = 1; 2779 #endif 2780 if (priv->counter_fallback) 2781 DRV_LOG(INFO, "Use fall-back DV counter management"); 2782 /* Check for LRO support. */ 2783 if (config.dest_tir && config.hca_attr.lro_cap && 2784 config.dv_flow_en) { 2785 /* TBD check tunnel lro caps. */ 2786 config.lro.supported = config.hca_attr.lro_cap; 2787 DRV_LOG(DEBUG, "Device supports LRO"); 2788 /* 2789 * If LRO timeout is not configured by application, 2790 * use the minimal supported value. 2791 */ 2792 if (!config.lro.timeout) 2793 config.lro.timeout = 2794 config.hca_attr.lro_timer_supported_periods[0]; 2795 DRV_LOG(DEBUG, "LRO session timeout set to %d usec", 2796 config.lro.timeout); 2797 } 2798 #if defined(HAVE_MLX5DV_DR) && defined(HAVE_MLX5_DR_CREATE_ACTION_FLOW_METER) 2799 if (config.hca_attr.qos.sup && config.hca_attr.qos.srtcm_sup && 2800 config.dv_flow_en) { 2801 uint8_t reg_c_mask = 2802 config.hca_attr.qos.flow_meter_reg_c_ids; 2803 /* 2804 * Meter needs two REG_C's for color match and pre-sfx 2805 * flow match. Here get the REG_C for color match. 2806 * REG_C_0 and REG_C_1 is reserved for metadata feature. 2807 */ 2808 reg_c_mask &= 0xfc; 2809 if (__builtin_popcount(reg_c_mask) < 1) { 2810 priv->mtr_en = 0; 2811 DRV_LOG(WARNING, "No available register for" 2812 " meter."); 2813 } else { 2814 priv->mtr_color_reg = ffs(reg_c_mask) - 1 + 2815 REG_C_0; 2816 priv->mtr_en = 1; 2817 priv->mtr_reg_share = 2818 config.hca_attr.qos.flow_meter_reg_share; 2819 DRV_LOG(DEBUG, "The REG_C meter uses is %d", 2820 priv->mtr_color_reg); 2821 } 2822 } 2823 #endif 2824 } 2825 if (config.mprq.enabled && mprq) { 2826 if (config.mprq.stride_num_n && 2827 (config.mprq.stride_num_n > mprq_max_stride_num_n || 2828 config.mprq.stride_num_n < mprq_min_stride_num_n)) { 2829 config.mprq.stride_num_n = 2830 RTE_MIN(RTE_MAX(MLX5_MPRQ_STRIDE_NUM_N, 2831 mprq_min_stride_num_n), 2832 mprq_max_stride_num_n); 2833 DRV_LOG(WARNING, 2834 "the number of strides" 2835 " for Multi-Packet RQ is out of range," 2836 " setting default value (%u)", 2837 1 << config.mprq.stride_num_n); 2838 } 2839 if (config.mprq.stride_size_n && 2840 (config.mprq.stride_size_n > mprq_max_stride_size_n || 2841 config.mprq.stride_size_n < mprq_min_stride_size_n)) { 2842 config.mprq.stride_size_n = 2843 RTE_MIN(RTE_MAX(MLX5_MPRQ_STRIDE_SIZE_N, 2844 mprq_min_stride_size_n), 2845 mprq_max_stride_size_n); 2846 DRV_LOG(WARNING, 2847 "the size of a stride" 2848 " for Multi-Packet RQ is out of range," 2849 " setting default value (%u)", 2850 1 << config.mprq.stride_size_n); 2851 } 2852 config.mprq.min_stride_size_n = mprq_min_stride_size_n; 2853 config.mprq.max_stride_size_n = mprq_max_stride_size_n; 2854 } else if (config.mprq.enabled && !mprq) { 2855 DRV_LOG(WARNING, "Multi-Packet RQ isn't supported"); 2856 config.mprq.enabled = 0; 2857 } 2858 if (config.max_dump_files_num == 0) 2859 config.max_dump_files_num = 128; 2860 eth_dev = rte_eth_dev_allocate(name); 2861 if (eth_dev == NULL) { 2862 DRV_LOG(ERR, "can not allocate rte ethdev"); 2863 err = ENOMEM; 2864 goto error; 2865 } 2866 /* Flag to call rte_eth_dev_release_port() in rte_eth_dev_close(). */ 2867 eth_dev->data->dev_flags |= RTE_ETH_DEV_CLOSE_REMOVE; 2868 if (priv->representor) { 2869 eth_dev->data->dev_flags |= RTE_ETH_DEV_REPRESENTOR; 2870 eth_dev->data->representor_id = priv->representor_id; 2871 } 2872 /* 2873 * Store associated network device interface index. This index 2874 * is permanent throughout the lifetime of device. So, we may store 2875 * the ifindex here and use the cached value further. 2876 */ 2877 MLX5_ASSERT(spawn->ifindex); 2878 priv->if_index = spawn->ifindex; 2879 eth_dev->data->dev_private = priv; 2880 priv->dev_data = eth_dev->data; 2881 eth_dev->data->mac_addrs = priv->mac; 2882 eth_dev->device = dpdk_dev; 2883 /* Configure the first MAC address by default. */ 2884 if (mlx5_get_mac(eth_dev, &mac.addr_bytes)) { 2885 DRV_LOG(ERR, 2886 "port %u cannot get MAC address, is mlx5_en" 2887 " loaded? (errno: %s)", 2888 eth_dev->data->port_id, strerror(rte_errno)); 2889 err = ENODEV; 2890 goto error; 2891 } 2892 DRV_LOG(INFO, 2893 "port %u MAC address is %02x:%02x:%02x:%02x:%02x:%02x", 2894 eth_dev->data->port_id, 2895 mac.addr_bytes[0], mac.addr_bytes[1], 2896 mac.addr_bytes[2], mac.addr_bytes[3], 2897 mac.addr_bytes[4], mac.addr_bytes[5]); 2898 #ifdef RTE_LIBRTE_MLX5_DEBUG 2899 { 2900 char ifname[IF_NAMESIZE]; 2901 2902 if (mlx5_get_ifname(eth_dev, &ifname) == 0) 2903 DRV_LOG(DEBUG, "port %u ifname is \"%s\"", 2904 eth_dev->data->port_id, ifname); 2905 else 2906 DRV_LOG(DEBUG, "port %u ifname is unknown", 2907 eth_dev->data->port_id); 2908 } 2909 #endif 2910 /* Get actual MTU if possible. */ 2911 err = mlx5_get_mtu(eth_dev, &priv->mtu); 2912 if (err) { 2913 err = rte_errno; 2914 goto error; 2915 } 2916 DRV_LOG(DEBUG, "port %u MTU is %u", eth_dev->data->port_id, 2917 priv->mtu); 2918 /* Initialize burst functions to prevent crashes before link-up. */ 2919 eth_dev->rx_pkt_burst = removed_rx_burst; 2920 eth_dev->tx_pkt_burst = removed_tx_burst; 2921 eth_dev->dev_ops = &mlx5_dev_ops; 2922 /* Register MAC address. */ 2923 claim_zero(mlx5_mac_addr_add(eth_dev, &mac, 0, 0)); 2924 if (config.vf && config.vf_nl_en) 2925 mlx5_nl_mac_addr_sync(priv->nl_socket_route, 2926 mlx5_ifindex(eth_dev), 2927 eth_dev->data->mac_addrs, 2928 MLX5_MAX_MAC_ADDRESSES); 2929 priv->flows = 0; 2930 priv->ctrl_flows = 0; 2931 TAILQ_INIT(&priv->flow_meters); 2932 TAILQ_INIT(&priv->flow_meter_profiles); 2933 /* Hint libmlx5 to use PMD allocator for data plane resources */ 2934 struct mlx5dv_ctx_allocators alctr = { 2935 .alloc = &mlx5_alloc_verbs_buf, 2936 .free = &mlx5_free_verbs_buf, 2937 .data = priv, 2938 }; 2939 mlx5_glue->dv_set_context_attr(sh->ctx, 2940 MLX5DV_CTX_ATTR_BUF_ALLOCATORS, 2941 (void *)((uintptr_t)&alctr)); 2942 /* Bring Ethernet device up. */ 2943 DRV_LOG(DEBUG, "port %u forcing Ethernet interface up", 2944 eth_dev->data->port_id); 2945 mlx5_set_link_up(eth_dev); 2946 /* 2947 * Even though the interrupt handler is not installed yet, 2948 * interrupts will still trigger on the async_fd from 2949 * Verbs context returned by ibv_open_device(). 2950 */ 2951 mlx5_link_update(eth_dev, 0); 2952 #ifdef HAVE_MLX5DV_DR_ESWITCH 2953 if (!(config.hca_attr.eswitch_manager && config.dv_flow_en && 2954 (switch_info->representor || switch_info->master))) 2955 config.dv_esw_en = 0; 2956 #else 2957 config.dv_esw_en = 0; 2958 #endif 2959 /* Detect minimal data bytes to inline. */ 2960 mlx5_set_min_inline(spawn, &config); 2961 /* Store device configuration on private structure. */ 2962 priv->config = config; 2963 /* Create context for virtual machine VLAN workaround. */ 2964 priv->vmwa_context = mlx5_vlan_vmwa_init(eth_dev, spawn->ifindex); 2965 if (config.dv_flow_en) { 2966 err = mlx5_alloc_shared_dr(priv); 2967 if (err) 2968 goto error; 2969 /* 2970 * RSS id is shared with meter flow id. Meter flow id can only 2971 * use the 24 MSB of the register. 2972 */ 2973 priv->qrss_id_pool = mlx5_flow_id_pool_alloc(UINT32_MAX >> 2974 MLX5_MTR_COLOR_BITS); 2975 if (!priv->qrss_id_pool) { 2976 DRV_LOG(ERR, "can't create flow id pool"); 2977 err = ENOMEM; 2978 goto error; 2979 } 2980 } 2981 /* Supported Verbs flow priority number detection. */ 2982 err = mlx5_flow_discover_priorities(eth_dev); 2983 if (err < 0) { 2984 err = -err; 2985 goto error; 2986 } 2987 priv->config.flow_prio = err; 2988 if (!priv->config.dv_esw_en && 2989 priv->config.dv_xmeta_en != MLX5_XMETA_MODE_LEGACY) { 2990 DRV_LOG(WARNING, "metadata mode %u is not supported " 2991 "(no E-Switch)", priv->config.dv_xmeta_en); 2992 priv->config.dv_xmeta_en = MLX5_XMETA_MODE_LEGACY; 2993 } 2994 mlx5_set_metadata_mask(eth_dev); 2995 if (priv->config.dv_xmeta_en != MLX5_XMETA_MODE_LEGACY && 2996 !priv->sh->dv_regc0_mask) { 2997 DRV_LOG(ERR, "metadata mode %u is not supported " 2998 "(no metadata reg_c[0] is available)", 2999 priv->config.dv_xmeta_en); 3000 err = ENOTSUP; 3001 goto error; 3002 } 3003 /* 3004 * Allocate the buffer for flow creating, just once. 3005 * The allocation must be done before any flow creating. 3006 */ 3007 mlx5_flow_alloc_intermediate(eth_dev); 3008 /* Query availibility of metadata reg_c's. */ 3009 err = mlx5_flow_discover_mreg_c(eth_dev); 3010 if (err < 0) { 3011 err = -err; 3012 goto error; 3013 } 3014 if (!mlx5_flow_ext_mreg_supported(eth_dev)) { 3015 DRV_LOG(DEBUG, 3016 "port %u extensive metadata register is not supported", 3017 eth_dev->data->port_id); 3018 if (priv->config.dv_xmeta_en != MLX5_XMETA_MODE_LEGACY) { 3019 DRV_LOG(ERR, "metadata mode %u is not supported " 3020 "(no metadata registers available)", 3021 priv->config.dv_xmeta_en); 3022 err = ENOTSUP; 3023 goto error; 3024 } 3025 } 3026 if (priv->config.dv_flow_en && 3027 priv->config.dv_xmeta_en != MLX5_XMETA_MODE_LEGACY && 3028 mlx5_flow_ext_mreg_supported(eth_dev) && 3029 priv->sh->dv_regc0_mask) { 3030 priv->mreg_cp_tbl = mlx5_hlist_create(MLX5_FLOW_MREG_HNAME, 3031 MLX5_FLOW_MREG_HTABLE_SZ); 3032 if (!priv->mreg_cp_tbl) { 3033 err = ENOMEM; 3034 goto error; 3035 } 3036 } 3037 return eth_dev; 3038 error: 3039 if (priv) { 3040 if (priv->mreg_cp_tbl) 3041 mlx5_hlist_destroy(priv->mreg_cp_tbl, NULL, NULL); 3042 if (priv->sh) 3043 mlx5_free_shared_dr(priv); 3044 if (priv->nl_socket_route >= 0) 3045 close(priv->nl_socket_route); 3046 if (priv->nl_socket_rdma >= 0) 3047 close(priv->nl_socket_rdma); 3048 if (priv->vmwa_context) 3049 mlx5_vlan_vmwa_exit(priv->vmwa_context); 3050 if (priv->qrss_id_pool) 3051 mlx5_flow_id_pool_release(priv->qrss_id_pool); 3052 if (own_domain_id) 3053 claim_zero(rte_eth_switch_domain_free(priv->domain_id)); 3054 rte_free(priv); 3055 if (eth_dev != NULL) 3056 eth_dev->data->dev_private = NULL; 3057 } 3058 if (eth_dev != NULL) { 3059 /* mac_addrs must not be freed alone because part of dev_private */ 3060 eth_dev->data->mac_addrs = NULL; 3061 rte_eth_dev_release_port(eth_dev); 3062 } 3063 if (sh) 3064 mlx5_free_shared_ibctx(sh); 3065 MLX5_ASSERT(err > 0); 3066 rte_errno = err; 3067 return NULL; 3068 } 3069 3070 /** 3071 * Comparison callback to sort device data. 3072 * 3073 * This is meant to be used with qsort(). 3074 * 3075 * @param a[in] 3076 * Pointer to pointer to first data object. 3077 * @param b[in] 3078 * Pointer to pointer to second data object. 3079 * 3080 * @return 3081 * 0 if both objects are equal, less than 0 if the first argument is less 3082 * than the second, greater than 0 otherwise. 3083 */ 3084 static int 3085 mlx5_dev_spawn_data_cmp(const void *a, const void *b) 3086 { 3087 const struct mlx5_switch_info *si_a = 3088 &((const struct mlx5_dev_spawn_data *)a)->info; 3089 const struct mlx5_switch_info *si_b = 3090 &((const struct mlx5_dev_spawn_data *)b)->info; 3091 int ret; 3092 3093 /* Master device first. */ 3094 ret = si_b->master - si_a->master; 3095 if (ret) 3096 return ret; 3097 /* Then representor devices. */ 3098 ret = si_b->representor - si_a->representor; 3099 if (ret) 3100 return ret; 3101 /* Unidentified devices come last in no specific order. */ 3102 if (!si_a->representor) 3103 return 0; 3104 /* Order representors by name. */ 3105 return si_a->port_name - si_b->port_name; 3106 } 3107 3108 /** 3109 * Match PCI information for possible slaves of bonding device. 3110 * 3111 * @param[in] ibv_dev 3112 * Pointer to Infiniband device structure. 3113 * @param[in] pci_dev 3114 * Pointer to PCI device structure to match PCI address. 3115 * @param[in] nl_rdma 3116 * Netlink RDMA group socket handle. 3117 * 3118 * @return 3119 * negative value if no bonding device found, otherwise 3120 * positive index of slave PF in bonding. 3121 */ 3122 static int 3123 mlx5_device_bond_pci_match(const struct ibv_device *ibv_dev, 3124 const struct rte_pci_device *pci_dev, 3125 int nl_rdma) 3126 { 3127 char ifname[IF_NAMESIZE + 1]; 3128 unsigned int ifindex; 3129 unsigned int np, i; 3130 FILE *file = NULL; 3131 int pf = -1; 3132 3133 /* 3134 * Try to get master device name. If something goes 3135 * wrong suppose the lack of kernel support and no 3136 * bonding devices. 3137 */ 3138 if (nl_rdma < 0) 3139 return -1; 3140 if (!strstr(ibv_dev->name, "bond")) 3141 return -1; 3142 np = mlx5_nl_portnum(nl_rdma, ibv_dev->name); 3143 if (!np) 3144 return -1; 3145 /* 3146 * The Master device might not be on the predefined 3147 * port (not on port index 1, it is not garanted), 3148 * we have to scan all Infiniband device port and 3149 * find master. 3150 */ 3151 for (i = 1; i <= np; ++i) { 3152 /* Check whether Infiniband port is populated. */ 3153 ifindex = mlx5_nl_ifindex(nl_rdma, ibv_dev->name, i); 3154 if (!ifindex) 3155 continue; 3156 if (!if_indextoname(ifindex, ifname)) 3157 continue; 3158 /* Try to read bonding slave names from sysfs. */ 3159 MKSTR(slaves, 3160 "/sys/class/net/%s/master/bonding/slaves", ifname); 3161 file = fopen(slaves, "r"); 3162 if (file) 3163 break; 3164 } 3165 if (!file) 3166 return -1; 3167 /* Use safe format to check maximal buffer length. */ 3168 MLX5_ASSERT(atol(RTE_STR(IF_NAMESIZE)) == IF_NAMESIZE); 3169 while (fscanf(file, "%" RTE_STR(IF_NAMESIZE) "s", ifname) == 1) { 3170 char tmp_str[IF_NAMESIZE + 32]; 3171 struct rte_pci_addr pci_addr; 3172 struct mlx5_switch_info info; 3173 3174 /* Process slave interface names in the loop. */ 3175 snprintf(tmp_str, sizeof(tmp_str), 3176 "/sys/class/net/%s", ifname); 3177 if (mlx5_dev_to_pci_addr(tmp_str, &pci_addr)) { 3178 DRV_LOG(WARNING, "can not get PCI address" 3179 " for netdev \"%s\"", ifname); 3180 continue; 3181 } 3182 if (pci_dev->addr.domain != pci_addr.domain || 3183 pci_dev->addr.bus != pci_addr.bus || 3184 pci_dev->addr.devid != pci_addr.devid || 3185 pci_dev->addr.function != pci_addr.function) 3186 continue; 3187 /* Slave interface PCI address match found. */ 3188 fclose(file); 3189 snprintf(tmp_str, sizeof(tmp_str), 3190 "/sys/class/net/%s/phys_port_name", ifname); 3191 file = fopen(tmp_str, "rb"); 3192 if (!file) 3193 break; 3194 info.name_type = MLX5_PHYS_PORT_NAME_TYPE_NOTSET; 3195 if (fscanf(file, "%32s", tmp_str) == 1) 3196 mlx5_translate_port_name(tmp_str, &info); 3197 if (info.name_type == MLX5_PHYS_PORT_NAME_TYPE_LEGACY || 3198 info.name_type == MLX5_PHYS_PORT_NAME_TYPE_UPLINK) 3199 pf = info.port_name; 3200 break; 3201 } 3202 if (file) 3203 fclose(file); 3204 return pf; 3205 } 3206 3207 /** 3208 * DPDK callback to register a PCI device. 3209 * 3210 * This function spawns Ethernet devices out of a given PCI device. 3211 * 3212 * @param[in] pci_drv 3213 * PCI driver structure (mlx5_driver). 3214 * @param[in] pci_dev 3215 * PCI device information. 3216 * 3217 * @return 3218 * 0 on success, a negative errno value otherwise and rte_errno is set. 3219 */ 3220 static int 3221 mlx5_pci_probe(struct rte_pci_driver *pci_drv __rte_unused, 3222 struct rte_pci_device *pci_dev) 3223 { 3224 struct ibv_device **ibv_list; 3225 /* 3226 * Number of found IB Devices matching with requested PCI BDF. 3227 * nd != 1 means there are multiple IB devices over the same 3228 * PCI device and we have representors and master. 3229 */ 3230 unsigned int nd = 0; 3231 /* 3232 * Number of found IB device Ports. nd = 1 and np = 1..n means 3233 * we have the single multiport IB device, and there may be 3234 * representors attached to some of found ports. 3235 */ 3236 unsigned int np = 0; 3237 /* 3238 * Number of DPDK ethernet devices to Spawn - either over 3239 * multiple IB devices or multiple ports of single IB device. 3240 * Actually this is the number of iterations to spawn. 3241 */ 3242 unsigned int ns = 0; 3243 /* 3244 * Bonding device 3245 * < 0 - no bonding device (single one) 3246 * >= 0 - bonding device (value is slave PF index) 3247 */ 3248 int bd = -1; 3249 struct mlx5_dev_spawn_data *list = NULL; 3250 struct mlx5_dev_config dev_config; 3251 int ret; 3252 3253 if (mlx5_class_get(pci_dev->device.devargs) != MLX5_CLASS_NET) { 3254 DRV_LOG(DEBUG, "Skip probing - should be probed by other mlx5" 3255 " driver."); 3256 return 1; 3257 } 3258 if (rte_eal_process_type() == RTE_PROC_PRIMARY) 3259 mlx5_pmd_socket_init(); 3260 ret = mlx5_init_once(); 3261 if (ret) { 3262 DRV_LOG(ERR, "unable to init PMD global data: %s", 3263 strerror(rte_errno)); 3264 return -rte_errno; 3265 } 3266 MLX5_ASSERT(pci_drv == &mlx5_driver); 3267 errno = 0; 3268 ibv_list = mlx5_glue->get_device_list(&ret); 3269 if (!ibv_list) { 3270 rte_errno = errno ? errno : ENOSYS; 3271 DRV_LOG(ERR, "cannot list devices, is ib_uverbs loaded?"); 3272 return -rte_errno; 3273 } 3274 /* 3275 * First scan the list of all Infiniband devices to find 3276 * matching ones, gathering into the list. 3277 */ 3278 struct ibv_device *ibv_match[ret + 1]; 3279 int nl_route = mlx5_nl_init(NETLINK_ROUTE); 3280 int nl_rdma = mlx5_nl_init(NETLINK_RDMA); 3281 unsigned int i; 3282 3283 while (ret-- > 0) { 3284 struct rte_pci_addr pci_addr; 3285 3286 DRV_LOG(DEBUG, "checking device \"%s\"", ibv_list[ret]->name); 3287 bd = mlx5_device_bond_pci_match 3288 (ibv_list[ret], pci_dev, nl_rdma); 3289 if (bd >= 0) { 3290 /* 3291 * Bonding device detected. Only one match is allowed, 3292 * the bonding is supported over multi-port IB device, 3293 * there should be no matches on representor PCI 3294 * functions or non VF LAG bonding devices with 3295 * specified address. 3296 */ 3297 if (nd) { 3298 DRV_LOG(ERR, 3299 "multiple PCI match on bonding device" 3300 "\"%s\" found", ibv_list[ret]->name); 3301 rte_errno = ENOENT; 3302 ret = -rte_errno; 3303 goto exit; 3304 } 3305 DRV_LOG(INFO, "PCI information matches for" 3306 " slave %d bonding device \"%s\"", 3307 bd, ibv_list[ret]->name); 3308 ibv_match[nd++] = ibv_list[ret]; 3309 break; 3310 } 3311 if (mlx5_dev_to_pci_addr 3312 (ibv_list[ret]->ibdev_path, &pci_addr)) 3313 continue; 3314 if (pci_dev->addr.domain != pci_addr.domain || 3315 pci_dev->addr.bus != pci_addr.bus || 3316 pci_dev->addr.devid != pci_addr.devid || 3317 pci_dev->addr.function != pci_addr.function) 3318 continue; 3319 DRV_LOG(INFO, "PCI information matches for device \"%s\"", 3320 ibv_list[ret]->name); 3321 ibv_match[nd++] = ibv_list[ret]; 3322 } 3323 ibv_match[nd] = NULL; 3324 if (!nd) { 3325 /* No device matches, just complain and bail out. */ 3326 DRV_LOG(WARNING, 3327 "no Verbs device matches PCI device " PCI_PRI_FMT "," 3328 " are kernel drivers loaded?", 3329 pci_dev->addr.domain, pci_dev->addr.bus, 3330 pci_dev->addr.devid, pci_dev->addr.function); 3331 rte_errno = ENOENT; 3332 ret = -rte_errno; 3333 goto exit; 3334 } 3335 if (nd == 1) { 3336 /* 3337 * Found single matching device may have multiple ports. 3338 * Each port may be representor, we have to check the port 3339 * number and check the representors existence. 3340 */ 3341 if (nl_rdma >= 0) 3342 np = mlx5_nl_portnum(nl_rdma, ibv_match[0]->name); 3343 if (!np) 3344 DRV_LOG(WARNING, "can not get IB device \"%s\"" 3345 " ports number", ibv_match[0]->name); 3346 if (bd >= 0 && !np) { 3347 DRV_LOG(ERR, "can not get ports" 3348 " for bonding device"); 3349 rte_errno = ENOENT; 3350 ret = -rte_errno; 3351 goto exit; 3352 } 3353 } 3354 #ifndef HAVE_MLX5DV_DR_DEVX_PORT 3355 if (bd >= 0) { 3356 /* 3357 * This may happen if there is VF LAG kernel support and 3358 * application is compiled with older rdma_core library. 3359 */ 3360 DRV_LOG(ERR, 3361 "No kernel/verbs support for VF LAG bonding found."); 3362 rte_errno = ENOTSUP; 3363 ret = -rte_errno; 3364 goto exit; 3365 } 3366 #endif 3367 /* 3368 * Now we can determine the maximal 3369 * amount of devices to be spawned. 3370 */ 3371 list = rte_zmalloc("device spawn data", 3372 sizeof(struct mlx5_dev_spawn_data) * 3373 (np ? np : nd), 3374 RTE_CACHE_LINE_SIZE); 3375 if (!list) { 3376 DRV_LOG(ERR, "spawn data array allocation failure"); 3377 rte_errno = ENOMEM; 3378 ret = -rte_errno; 3379 goto exit; 3380 } 3381 if (bd >= 0 || np > 1) { 3382 /* 3383 * Single IB device with multiple ports found, 3384 * it may be E-Switch master device and representors. 3385 * We have to perform identification trough the ports. 3386 */ 3387 MLX5_ASSERT(nl_rdma >= 0); 3388 MLX5_ASSERT(ns == 0); 3389 MLX5_ASSERT(nd == 1); 3390 MLX5_ASSERT(np); 3391 for (i = 1; i <= np; ++i) { 3392 list[ns].max_port = np; 3393 list[ns].ibv_port = i; 3394 list[ns].ibv_dev = ibv_match[0]; 3395 list[ns].eth_dev = NULL; 3396 list[ns].pci_dev = pci_dev; 3397 list[ns].pf_bond = bd; 3398 list[ns].ifindex = mlx5_nl_ifindex 3399 (nl_rdma, list[ns].ibv_dev->name, i); 3400 if (!list[ns].ifindex) { 3401 /* 3402 * No network interface index found for the 3403 * specified port, it means there is no 3404 * representor on this port. It's OK, 3405 * there can be disabled ports, for example 3406 * if sriov_numvfs < sriov_totalvfs. 3407 */ 3408 continue; 3409 } 3410 ret = -1; 3411 if (nl_route >= 0) 3412 ret = mlx5_nl_switch_info 3413 (nl_route, 3414 list[ns].ifindex, 3415 &list[ns].info); 3416 if (ret || (!list[ns].info.representor && 3417 !list[ns].info.master)) { 3418 /* 3419 * We failed to recognize representors with 3420 * Netlink, let's try to perform the task 3421 * with sysfs. 3422 */ 3423 ret = mlx5_sysfs_switch_info 3424 (list[ns].ifindex, 3425 &list[ns].info); 3426 } 3427 if (!ret && bd >= 0) { 3428 switch (list[ns].info.name_type) { 3429 case MLX5_PHYS_PORT_NAME_TYPE_UPLINK: 3430 if (list[ns].info.port_name == bd) 3431 ns++; 3432 break; 3433 case MLX5_PHYS_PORT_NAME_TYPE_PFVF: 3434 if (list[ns].info.pf_num == bd) 3435 ns++; 3436 break; 3437 default: 3438 break; 3439 } 3440 continue; 3441 } 3442 if (!ret && (list[ns].info.representor ^ 3443 list[ns].info.master)) 3444 ns++; 3445 } 3446 if (!ns) { 3447 DRV_LOG(ERR, 3448 "unable to recognize master/representors" 3449 " on the IB device with multiple ports"); 3450 rte_errno = ENOENT; 3451 ret = -rte_errno; 3452 goto exit; 3453 } 3454 } else { 3455 /* 3456 * The existence of several matching entries (nd > 1) means 3457 * port representors have been instantiated. No existing Verbs 3458 * call nor sysfs entries can tell them apart, this can only 3459 * be done through Netlink calls assuming kernel drivers are 3460 * recent enough to support them. 3461 * 3462 * In the event of identification failure through Netlink, 3463 * try again through sysfs, then: 3464 * 3465 * 1. A single IB device matches (nd == 1) with single 3466 * port (np=0/1) and is not a representor, assume 3467 * no switch support. 3468 * 3469 * 2. Otherwise no safe assumptions can be made; 3470 * complain louder and bail out. 3471 */ 3472 np = 1; 3473 for (i = 0; i != nd; ++i) { 3474 memset(&list[ns].info, 0, sizeof(list[ns].info)); 3475 list[ns].max_port = 1; 3476 list[ns].ibv_port = 1; 3477 list[ns].ibv_dev = ibv_match[i]; 3478 list[ns].eth_dev = NULL; 3479 list[ns].pci_dev = pci_dev; 3480 list[ns].pf_bond = -1; 3481 list[ns].ifindex = 0; 3482 if (nl_rdma >= 0) 3483 list[ns].ifindex = mlx5_nl_ifindex 3484 (nl_rdma, list[ns].ibv_dev->name, 1); 3485 if (!list[ns].ifindex) { 3486 char ifname[IF_NAMESIZE]; 3487 3488 /* 3489 * Netlink failed, it may happen with old 3490 * ib_core kernel driver (before 4.16). 3491 * We can assume there is old driver because 3492 * here we are processing single ports IB 3493 * devices. Let's try sysfs to retrieve 3494 * the ifindex. The method works for 3495 * master device only. 3496 */ 3497 if (nd > 1) { 3498 /* 3499 * Multiple devices found, assume 3500 * representors, can not distinguish 3501 * master/representor and retrieve 3502 * ifindex via sysfs. 3503 */ 3504 continue; 3505 } 3506 ret = mlx5_get_master_ifname 3507 (ibv_match[i]->ibdev_path, &ifname); 3508 if (!ret) 3509 list[ns].ifindex = 3510 if_nametoindex(ifname); 3511 if (!list[ns].ifindex) { 3512 /* 3513 * No network interface index found 3514 * for the specified device, it means 3515 * there it is neither representor 3516 * nor master. 3517 */ 3518 continue; 3519 } 3520 } 3521 ret = -1; 3522 if (nl_route >= 0) 3523 ret = mlx5_nl_switch_info 3524 (nl_route, 3525 list[ns].ifindex, 3526 &list[ns].info); 3527 if (ret || (!list[ns].info.representor && 3528 !list[ns].info.master)) { 3529 /* 3530 * We failed to recognize representors with 3531 * Netlink, let's try to perform the task 3532 * with sysfs. 3533 */ 3534 ret = mlx5_sysfs_switch_info 3535 (list[ns].ifindex, 3536 &list[ns].info); 3537 } 3538 if (!ret && (list[ns].info.representor ^ 3539 list[ns].info.master)) { 3540 ns++; 3541 } else if ((nd == 1) && 3542 !list[ns].info.representor && 3543 !list[ns].info.master) { 3544 /* 3545 * Single IB device with 3546 * one physical port and 3547 * attached network device. 3548 * May be SRIOV is not enabled 3549 * or there is no representors. 3550 */ 3551 DRV_LOG(INFO, "no E-Switch support detected"); 3552 ns++; 3553 break; 3554 } 3555 } 3556 if (!ns) { 3557 DRV_LOG(ERR, 3558 "unable to recognize master/representors" 3559 " on the multiple IB devices"); 3560 rte_errno = ENOENT; 3561 ret = -rte_errno; 3562 goto exit; 3563 } 3564 } 3565 MLX5_ASSERT(ns); 3566 /* 3567 * Sort list to probe devices in natural order for users convenience 3568 * (i.e. master first, then representors from lowest to highest ID). 3569 */ 3570 qsort(list, ns, sizeof(*list), mlx5_dev_spawn_data_cmp); 3571 /* Default configuration. */ 3572 dev_config = (struct mlx5_dev_config){ 3573 .hw_padding = 0, 3574 .mps = MLX5_ARG_UNSET, 3575 .dbnc = MLX5_ARG_UNSET, 3576 .rx_vec_en = 1, 3577 .txq_inline_max = MLX5_ARG_UNSET, 3578 .txq_inline_min = MLX5_ARG_UNSET, 3579 .txq_inline_mpw = MLX5_ARG_UNSET, 3580 .txqs_inline = MLX5_ARG_UNSET, 3581 .vf_nl_en = 1, 3582 .mr_ext_memseg_en = 1, 3583 .mprq = { 3584 .enabled = 0, /* Disabled by default. */ 3585 .stride_num_n = 0, 3586 .stride_size_n = 0, 3587 .max_memcpy_len = MLX5_MPRQ_MEMCPY_DEFAULT_LEN, 3588 .min_rxqs_num = MLX5_MPRQ_MIN_RXQS, 3589 }, 3590 .dv_esw_en = 1, 3591 .dv_flow_en = 1, 3592 .log_hp_size = MLX5_ARG_UNSET, 3593 }; 3594 /* Device specific configuration. */ 3595 switch (pci_dev->id.device_id) { 3596 case PCI_DEVICE_ID_MELLANOX_CONNECTX4VF: 3597 case PCI_DEVICE_ID_MELLANOX_CONNECTX4LXVF: 3598 case PCI_DEVICE_ID_MELLANOX_CONNECTX5VF: 3599 case PCI_DEVICE_ID_MELLANOX_CONNECTX5EXVF: 3600 case PCI_DEVICE_ID_MELLANOX_CONNECTX5BFVF: 3601 case PCI_DEVICE_ID_MELLANOX_CONNECTX6VF: 3602 case PCI_DEVICE_ID_MELLANOX_CONNECTX6DXVF: 3603 dev_config.vf = 1; 3604 break; 3605 default: 3606 break; 3607 } 3608 for (i = 0; i != ns; ++i) { 3609 uint32_t restore; 3610 3611 list[i].eth_dev = mlx5_dev_spawn(&pci_dev->device, 3612 &list[i], 3613 dev_config); 3614 if (!list[i].eth_dev) { 3615 if (rte_errno != EBUSY && rte_errno != EEXIST) 3616 break; 3617 /* Device is disabled or already spawned. Ignore it. */ 3618 continue; 3619 } 3620 restore = list[i].eth_dev->data->dev_flags; 3621 rte_eth_copy_pci_info(list[i].eth_dev, pci_dev); 3622 /* Restore non-PCI flags cleared by the above call. */ 3623 list[i].eth_dev->data->dev_flags |= restore; 3624 mlx5_dev_interrupt_handler_devx_install(list[i].eth_dev); 3625 rte_eth_dev_probing_finish(list[i].eth_dev); 3626 } 3627 if (i != ns) { 3628 DRV_LOG(ERR, 3629 "probe of PCI device " PCI_PRI_FMT " aborted after" 3630 " encountering an error: %s", 3631 pci_dev->addr.domain, pci_dev->addr.bus, 3632 pci_dev->addr.devid, pci_dev->addr.function, 3633 strerror(rte_errno)); 3634 ret = -rte_errno; 3635 /* Roll back. */ 3636 while (i--) { 3637 if (!list[i].eth_dev) 3638 continue; 3639 mlx5_dev_close(list[i].eth_dev); 3640 /* mac_addrs must not be freed because in dev_private */ 3641 list[i].eth_dev->data->mac_addrs = NULL; 3642 claim_zero(rte_eth_dev_release_port(list[i].eth_dev)); 3643 } 3644 /* Restore original error. */ 3645 rte_errno = -ret; 3646 } else { 3647 ret = 0; 3648 } 3649 exit: 3650 /* 3651 * Do the routine cleanup: 3652 * - close opened Netlink sockets 3653 * - free allocated spawn data array 3654 * - free the Infiniband device list 3655 */ 3656 if (nl_rdma >= 0) 3657 close(nl_rdma); 3658 if (nl_route >= 0) 3659 close(nl_route); 3660 if (list) 3661 rte_free(list); 3662 MLX5_ASSERT(ibv_list); 3663 mlx5_glue->free_device_list(ibv_list); 3664 return ret; 3665 } 3666 3667 /** 3668 * Look for the ethernet device belonging to mlx5 driver. 3669 * 3670 * @param[in] port_id 3671 * port_id to start looking for device. 3672 * @param[in] pci_dev 3673 * Pointer to the hint PCI device. When device is being probed 3674 * the its siblings (master and preceding representors might 3675 * not have assigned driver yet (because the mlx5_pci_probe() 3676 * is not completed yet, for this case match on hint PCI 3677 * device may be used to detect sibling device. 3678 * 3679 * @return 3680 * port_id of found device, RTE_MAX_ETHPORT if not found. 3681 */ 3682 uint16_t 3683 mlx5_eth_find_next(uint16_t port_id, struct rte_pci_device *pci_dev) 3684 { 3685 while (port_id < RTE_MAX_ETHPORTS) { 3686 struct rte_eth_dev *dev = &rte_eth_devices[port_id]; 3687 3688 if (dev->state != RTE_ETH_DEV_UNUSED && 3689 dev->device && 3690 (dev->device == &pci_dev->device || 3691 (dev->device->driver && 3692 dev->device->driver->name && 3693 !strcmp(dev->device->driver->name, MLX5_DRIVER_NAME)))) 3694 break; 3695 port_id++; 3696 } 3697 if (port_id >= RTE_MAX_ETHPORTS) 3698 return RTE_MAX_ETHPORTS; 3699 return port_id; 3700 } 3701 3702 /** 3703 * DPDK callback to remove a PCI device. 3704 * 3705 * This function removes all Ethernet devices belong to a given PCI device. 3706 * 3707 * @param[in] pci_dev 3708 * Pointer to the PCI device. 3709 * 3710 * @return 3711 * 0 on success, the function cannot fail. 3712 */ 3713 static int 3714 mlx5_pci_remove(struct rte_pci_device *pci_dev) 3715 { 3716 uint16_t port_id; 3717 3718 RTE_ETH_FOREACH_DEV_OF(port_id, &pci_dev->device) 3719 rte_eth_dev_close(port_id); 3720 return 0; 3721 } 3722 3723 static const struct rte_pci_id mlx5_pci_id_map[] = { 3724 { 3725 RTE_PCI_DEVICE(PCI_VENDOR_ID_MELLANOX, 3726 PCI_DEVICE_ID_MELLANOX_CONNECTX4) 3727 }, 3728 { 3729 RTE_PCI_DEVICE(PCI_VENDOR_ID_MELLANOX, 3730 PCI_DEVICE_ID_MELLANOX_CONNECTX4VF) 3731 }, 3732 { 3733 RTE_PCI_DEVICE(PCI_VENDOR_ID_MELLANOX, 3734 PCI_DEVICE_ID_MELLANOX_CONNECTX4LX) 3735 }, 3736 { 3737 RTE_PCI_DEVICE(PCI_VENDOR_ID_MELLANOX, 3738 PCI_DEVICE_ID_MELLANOX_CONNECTX4LXVF) 3739 }, 3740 { 3741 RTE_PCI_DEVICE(PCI_VENDOR_ID_MELLANOX, 3742 PCI_DEVICE_ID_MELLANOX_CONNECTX5) 3743 }, 3744 { 3745 RTE_PCI_DEVICE(PCI_VENDOR_ID_MELLANOX, 3746 PCI_DEVICE_ID_MELLANOX_CONNECTX5VF) 3747 }, 3748 { 3749 RTE_PCI_DEVICE(PCI_VENDOR_ID_MELLANOX, 3750 PCI_DEVICE_ID_MELLANOX_CONNECTX5EX) 3751 }, 3752 { 3753 RTE_PCI_DEVICE(PCI_VENDOR_ID_MELLANOX, 3754 PCI_DEVICE_ID_MELLANOX_CONNECTX5EXVF) 3755 }, 3756 { 3757 RTE_PCI_DEVICE(PCI_VENDOR_ID_MELLANOX, 3758 PCI_DEVICE_ID_MELLANOX_CONNECTX5BF) 3759 }, 3760 { 3761 RTE_PCI_DEVICE(PCI_VENDOR_ID_MELLANOX, 3762 PCI_DEVICE_ID_MELLANOX_CONNECTX5BFVF) 3763 }, 3764 { 3765 RTE_PCI_DEVICE(PCI_VENDOR_ID_MELLANOX, 3766 PCI_DEVICE_ID_MELLANOX_CONNECTX6) 3767 }, 3768 { 3769 RTE_PCI_DEVICE(PCI_VENDOR_ID_MELLANOX, 3770 PCI_DEVICE_ID_MELLANOX_CONNECTX6VF) 3771 }, 3772 { 3773 RTE_PCI_DEVICE(PCI_VENDOR_ID_MELLANOX, 3774 PCI_DEVICE_ID_MELLANOX_CONNECTX6DX) 3775 }, 3776 { 3777 RTE_PCI_DEVICE(PCI_VENDOR_ID_MELLANOX, 3778 PCI_DEVICE_ID_MELLANOX_CONNECTX6DXVF) 3779 }, 3780 { 3781 RTE_PCI_DEVICE(PCI_VENDOR_ID_MELLANOX, 3782 PCI_DEVICE_ID_MELLANOX_CONNECTX6DXBF) 3783 }, 3784 { 3785 .vendor_id = 0 3786 } 3787 }; 3788 3789 static struct rte_pci_driver mlx5_driver = { 3790 .driver = { 3791 .name = MLX5_DRIVER_NAME 3792 }, 3793 .id_table = mlx5_pci_id_map, 3794 .probe = mlx5_pci_probe, 3795 .remove = mlx5_pci_remove, 3796 .dma_map = mlx5_dma_map, 3797 .dma_unmap = mlx5_dma_unmap, 3798 .drv_flags = RTE_PCI_DRV_INTR_LSC | RTE_PCI_DRV_INTR_RMV | 3799 RTE_PCI_DRV_PROBE_AGAIN, 3800 }; 3801 3802 /** 3803 * Driver initialization routine. 3804 */ 3805 RTE_INIT(rte_mlx5_pmd_init) 3806 { 3807 /* Initialize driver log type. */ 3808 mlx5_logtype = rte_log_register("pmd.net.mlx5"); 3809 if (mlx5_logtype >= 0) 3810 rte_log_set_level(mlx5_logtype, RTE_LOG_NOTICE); 3811 3812 /* Build the static tables for Verbs conversion. */ 3813 mlx5_set_ptype_table(); 3814 mlx5_set_cksum_table(); 3815 mlx5_set_swp_types_table(); 3816 if (mlx5_glue) 3817 rte_pci_register(&mlx5_driver); 3818 } 3819 3820 RTE_PMD_EXPORT_NAME(net_mlx5, __COUNTER__); 3821 RTE_PMD_REGISTER_PCI_TABLE(net_mlx5, mlx5_pci_id_map); 3822 RTE_PMD_REGISTER_KMOD_DEP(net_mlx5, "* ib_uverbs & mlx5_core & mlx5_ib"); 3823