1 /* SPDX-License-Identifier: BSD-3-Clause 2 * Copyright 2015 6WIND S.A. 3 * Copyright 2015 Mellanox Technologies, Ltd 4 */ 5 6 #include <stddef.h> 7 #include <unistd.h> 8 #include <string.h> 9 #include <assert.h> 10 #include <dlfcn.h> 11 #include <stdint.h> 12 #include <stdlib.h> 13 #include <errno.h> 14 #include <net/if.h> 15 #include <sys/mman.h> 16 #include <linux/netlink.h> 17 #include <linux/rtnetlink.h> 18 19 /* Verbs header. */ 20 /* ISO C doesn't support unnamed structs/unions, disabling -pedantic. */ 21 #ifdef PEDANTIC 22 #pragma GCC diagnostic ignored "-Wpedantic" 23 #endif 24 #include <infiniband/verbs.h> 25 #ifdef PEDANTIC 26 #pragma GCC diagnostic error "-Wpedantic" 27 #endif 28 29 #include <rte_malloc.h> 30 #include <rte_ethdev_driver.h> 31 #include <rte_ethdev_pci.h> 32 #include <rte_pci.h> 33 #include <rte_bus_pci.h> 34 #include <rte_common.h> 35 #include <rte_config.h> 36 #include <rte_eal_memconfig.h> 37 #include <rte_kvargs.h> 38 #include <rte_rwlock.h> 39 #include <rte_spinlock.h> 40 #include <rte_string_fns.h> 41 42 #include "mlx5.h" 43 #include "mlx5_utils.h" 44 #include "mlx5_rxtx.h" 45 #include "mlx5_autoconf.h" 46 #include "mlx5_defs.h" 47 #include "mlx5_glue.h" 48 #include "mlx5_mr.h" 49 50 /* Device parameter to enable RX completion queue compression. */ 51 #define MLX5_RXQ_CQE_COMP_EN "rxq_cqe_comp_en" 52 53 /* Device parameter to enable Multi-Packet Rx queue. */ 54 #define MLX5_RX_MPRQ_EN "mprq_en" 55 56 /* Device parameter to configure log 2 of the number of strides for MPRQ. */ 57 #define MLX5_RX_MPRQ_LOG_STRIDE_NUM "mprq_log_stride_num" 58 59 /* Device parameter to limit the size of memcpy'd packet for MPRQ. */ 60 #define MLX5_RX_MPRQ_MAX_MEMCPY_LEN "mprq_max_memcpy_len" 61 62 /* Device parameter to set the minimum number of Rx queues to enable MPRQ. */ 63 #define MLX5_RXQS_MIN_MPRQ "rxqs_min_mprq" 64 65 /* Device parameter to configure inline send. */ 66 #define MLX5_TXQ_INLINE "txq_inline" 67 68 /* 69 * Device parameter to configure the number of TX queues threshold for 70 * enabling inline send. 71 */ 72 #define MLX5_TXQS_MIN_INLINE "txqs_min_inline" 73 74 /* Device parameter to enable multi-packet send WQEs. */ 75 #define MLX5_TXQ_MPW_EN "txq_mpw_en" 76 77 /* Device parameter to include 2 dsegs in the title WQEBB. */ 78 #define MLX5_TXQ_MPW_HDR_DSEG_EN "txq_mpw_hdr_dseg_en" 79 80 /* Device parameter to limit the size of inlining packet. */ 81 #define MLX5_TXQ_MAX_INLINE_LEN "txq_max_inline_len" 82 83 /* Device parameter to enable hardware Tx vector. */ 84 #define MLX5_TX_VEC_EN "tx_vec_en" 85 86 /* Device parameter to enable hardware Rx vector. */ 87 #define MLX5_RX_VEC_EN "rx_vec_en" 88 89 /* Allow L3 VXLAN flow creation. */ 90 #define MLX5_L3_VXLAN_EN "l3_vxlan_en" 91 92 /* Activate Netlink support in VF mode. */ 93 #define MLX5_VF_NL_EN "vf_nl_en" 94 95 /* Select port representors to instantiate. */ 96 #define MLX5_REPRESENTOR "representor" 97 98 #ifndef HAVE_IBV_MLX5_MOD_MPW 99 #define MLX5DV_CONTEXT_FLAGS_MPW_ALLOWED (1 << 2) 100 #define MLX5DV_CONTEXT_FLAGS_ENHANCED_MPW (1 << 3) 101 #endif 102 103 #ifndef HAVE_IBV_MLX5_MOD_CQE_128B_COMP 104 #define MLX5DV_CONTEXT_FLAGS_CQE_128B_COMP (1 << 4) 105 #endif 106 107 static const char *MZ_MLX5_PMD_SHARED_DATA = "mlx5_pmd_shared_data"; 108 109 /* Shared memory between primary and secondary processes. */ 110 struct mlx5_shared_data *mlx5_shared_data; 111 112 /* Spinlock for mlx5_shared_data allocation. */ 113 static rte_spinlock_t mlx5_shared_data_lock = RTE_SPINLOCK_INITIALIZER; 114 115 /** Driver-specific log messages type. */ 116 int mlx5_logtype; 117 118 /** 119 * Prepare shared data between primary and secondary process. 120 */ 121 static void 122 mlx5_prepare_shared_data(void) 123 { 124 const struct rte_memzone *mz; 125 126 rte_spinlock_lock(&mlx5_shared_data_lock); 127 if (mlx5_shared_data == NULL) { 128 if (rte_eal_process_type() == RTE_PROC_PRIMARY) { 129 /* Allocate shared memory. */ 130 mz = rte_memzone_reserve(MZ_MLX5_PMD_SHARED_DATA, 131 sizeof(*mlx5_shared_data), 132 SOCKET_ID_ANY, 0); 133 } else { 134 /* Lookup allocated shared memory. */ 135 mz = rte_memzone_lookup(MZ_MLX5_PMD_SHARED_DATA); 136 } 137 if (mz == NULL) 138 rte_panic("Cannot allocate mlx5 shared data\n"); 139 mlx5_shared_data = mz->addr; 140 /* Initialize shared data. */ 141 if (rte_eal_process_type() == RTE_PROC_PRIMARY) { 142 LIST_INIT(&mlx5_shared_data->mem_event_cb_list); 143 rte_rwlock_init(&mlx5_shared_data->mem_event_rwlock); 144 } 145 rte_mem_event_callback_register("MLX5_MEM_EVENT_CB", 146 mlx5_mr_mem_event_cb, NULL); 147 } 148 rte_spinlock_unlock(&mlx5_shared_data_lock); 149 } 150 151 /** 152 * Retrieve integer value from environment variable. 153 * 154 * @param[in] name 155 * Environment variable name. 156 * 157 * @return 158 * Integer value, 0 if the variable is not set. 159 */ 160 int 161 mlx5_getenv_int(const char *name) 162 { 163 const char *val = getenv(name); 164 165 if (val == NULL) 166 return 0; 167 return atoi(val); 168 } 169 170 /** 171 * Verbs callback to allocate a memory. This function should allocate the space 172 * according to the size provided residing inside a huge page. 173 * Please note that all allocation must respect the alignment from libmlx5 174 * (i.e. currently sysconf(_SC_PAGESIZE)). 175 * 176 * @param[in] size 177 * The size in bytes of the memory to allocate. 178 * @param[in] data 179 * A pointer to the callback data. 180 * 181 * @return 182 * Allocated buffer, NULL otherwise and rte_errno is set. 183 */ 184 static void * 185 mlx5_alloc_verbs_buf(size_t size, void *data) 186 { 187 struct priv *priv = data; 188 void *ret; 189 size_t alignment = sysconf(_SC_PAGESIZE); 190 unsigned int socket = SOCKET_ID_ANY; 191 192 if (priv->verbs_alloc_ctx.type == MLX5_VERBS_ALLOC_TYPE_TX_QUEUE) { 193 const struct mlx5_txq_ctrl *ctrl = priv->verbs_alloc_ctx.obj; 194 195 socket = ctrl->socket; 196 } else if (priv->verbs_alloc_ctx.type == 197 MLX5_VERBS_ALLOC_TYPE_RX_QUEUE) { 198 const struct mlx5_rxq_ctrl *ctrl = priv->verbs_alloc_ctx.obj; 199 200 socket = ctrl->socket; 201 } 202 assert(data != NULL); 203 ret = rte_malloc_socket(__func__, size, alignment, socket); 204 if (!ret && size) 205 rte_errno = ENOMEM; 206 return ret; 207 } 208 209 /** 210 * Verbs callback to free a memory. 211 * 212 * @param[in] ptr 213 * A pointer to the memory to free. 214 * @param[in] data 215 * A pointer to the callback data. 216 */ 217 static void 218 mlx5_free_verbs_buf(void *ptr, void *data __rte_unused) 219 { 220 assert(data != NULL); 221 rte_free(ptr); 222 } 223 224 /** 225 * DPDK callback to close the device. 226 * 227 * Destroy all queues and objects, free memory. 228 * 229 * @param dev 230 * Pointer to Ethernet device structure. 231 */ 232 static void 233 mlx5_dev_close(struct rte_eth_dev *dev) 234 { 235 struct priv *priv = dev->data->dev_private; 236 unsigned int i; 237 int ret; 238 239 DRV_LOG(DEBUG, "port %u closing device \"%s\"", 240 dev->data->port_id, 241 ((priv->ctx != NULL) ? priv->ctx->device->name : "")); 242 /* In case mlx5_dev_stop() has not been called. */ 243 mlx5_dev_interrupt_handler_uninstall(dev); 244 mlx5_traffic_disable(dev); 245 mlx5_flow_flush(dev, NULL); 246 /* Prevent crashes when queues are still in use. */ 247 dev->rx_pkt_burst = removed_rx_burst; 248 dev->tx_pkt_burst = removed_tx_burst; 249 if (priv->rxqs != NULL) { 250 /* XXX race condition if mlx5_rx_burst() is still running. */ 251 usleep(1000); 252 for (i = 0; (i != priv->rxqs_n); ++i) 253 mlx5_rxq_release(dev, i); 254 priv->rxqs_n = 0; 255 priv->rxqs = NULL; 256 } 257 if (priv->txqs != NULL) { 258 /* XXX race condition if mlx5_tx_burst() is still running. */ 259 usleep(1000); 260 for (i = 0; (i != priv->txqs_n); ++i) 261 mlx5_txq_release(dev, i); 262 priv->txqs_n = 0; 263 priv->txqs = NULL; 264 } 265 mlx5_mprq_free_mp(dev); 266 mlx5_mr_release(dev); 267 if (priv->pd != NULL) { 268 assert(priv->ctx != NULL); 269 claim_zero(mlx5_glue->dealloc_pd(priv->pd)); 270 claim_zero(mlx5_glue->close_device(priv->ctx)); 271 } else 272 assert(priv->ctx == NULL); 273 if (priv->rss_conf.rss_key != NULL) 274 rte_free(priv->rss_conf.rss_key); 275 if (priv->reta_idx != NULL) 276 rte_free(priv->reta_idx); 277 if (priv->primary_socket) 278 mlx5_socket_uninit(dev); 279 if (priv->config.vf) 280 mlx5_nl_mac_addr_flush(dev); 281 if (priv->nl_socket_route >= 0) 282 close(priv->nl_socket_route); 283 if (priv->nl_socket_rdma >= 0) 284 close(priv->nl_socket_rdma); 285 if (priv->mnl_socket) 286 mlx5_nl_flow_socket_destroy(priv->mnl_socket); 287 ret = mlx5_hrxq_ibv_verify(dev); 288 if (ret) 289 DRV_LOG(WARNING, "port %u some hash Rx queue still remain", 290 dev->data->port_id); 291 ret = mlx5_ind_table_ibv_verify(dev); 292 if (ret) 293 DRV_LOG(WARNING, "port %u some indirection table still remain", 294 dev->data->port_id); 295 ret = mlx5_rxq_ibv_verify(dev); 296 if (ret) 297 DRV_LOG(WARNING, "port %u some Verbs Rx queue still remain", 298 dev->data->port_id); 299 ret = mlx5_rxq_verify(dev); 300 if (ret) 301 DRV_LOG(WARNING, "port %u some Rx queues still remain", 302 dev->data->port_id); 303 ret = mlx5_txq_ibv_verify(dev); 304 if (ret) 305 DRV_LOG(WARNING, "port %u some Verbs Tx queue still remain", 306 dev->data->port_id); 307 ret = mlx5_txq_verify(dev); 308 if (ret) 309 DRV_LOG(WARNING, "port %u some Tx queues still remain", 310 dev->data->port_id); 311 ret = mlx5_flow_verify(dev); 312 if (ret) 313 DRV_LOG(WARNING, "port %u some flows still remain", 314 dev->data->port_id); 315 if (priv->domain_id != RTE_ETH_DEV_SWITCH_DOMAIN_ID_INVALID) { 316 unsigned int c = 0; 317 unsigned int i = mlx5_dev_to_port_id(dev->device, NULL, 0); 318 uint16_t port_id[i]; 319 320 i = RTE_MIN(mlx5_dev_to_port_id(dev->device, port_id, i), i); 321 while (i--) { 322 struct priv *opriv = 323 rte_eth_devices[port_id[i]].data->dev_private; 324 325 if (!opriv || 326 opriv->domain_id != priv->domain_id || 327 &rte_eth_devices[port_id[i]] == dev) 328 continue; 329 ++c; 330 } 331 if (!c) 332 claim_zero(rte_eth_switch_domain_free(priv->domain_id)); 333 } 334 memset(priv, 0, sizeof(*priv)); 335 priv->domain_id = RTE_ETH_DEV_SWITCH_DOMAIN_ID_INVALID; 336 } 337 338 const struct eth_dev_ops mlx5_dev_ops = { 339 .dev_configure = mlx5_dev_configure, 340 .dev_start = mlx5_dev_start, 341 .dev_stop = mlx5_dev_stop, 342 .dev_set_link_down = mlx5_set_link_down, 343 .dev_set_link_up = mlx5_set_link_up, 344 .dev_close = mlx5_dev_close, 345 .promiscuous_enable = mlx5_promiscuous_enable, 346 .promiscuous_disable = mlx5_promiscuous_disable, 347 .allmulticast_enable = mlx5_allmulticast_enable, 348 .allmulticast_disable = mlx5_allmulticast_disable, 349 .link_update = mlx5_link_update, 350 .stats_get = mlx5_stats_get, 351 .stats_reset = mlx5_stats_reset, 352 .xstats_get = mlx5_xstats_get, 353 .xstats_reset = mlx5_xstats_reset, 354 .xstats_get_names = mlx5_xstats_get_names, 355 .dev_infos_get = mlx5_dev_infos_get, 356 .dev_supported_ptypes_get = mlx5_dev_supported_ptypes_get, 357 .vlan_filter_set = mlx5_vlan_filter_set, 358 .rx_queue_setup = mlx5_rx_queue_setup, 359 .tx_queue_setup = mlx5_tx_queue_setup, 360 .rx_queue_release = mlx5_rx_queue_release, 361 .tx_queue_release = mlx5_tx_queue_release, 362 .flow_ctrl_get = mlx5_dev_get_flow_ctrl, 363 .flow_ctrl_set = mlx5_dev_set_flow_ctrl, 364 .mac_addr_remove = mlx5_mac_addr_remove, 365 .mac_addr_add = mlx5_mac_addr_add, 366 .mac_addr_set = mlx5_mac_addr_set, 367 .set_mc_addr_list = mlx5_set_mc_addr_list, 368 .mtu_set = mlx5_dev_set_mtu, 369 .vlan_strip_queue_set = mlx5_vlan_strip_queue_set, 370 .vlan_offload_set = mlx5_vlan_offload_set, 371 .reta_update = mlx5_dev_rss_reta_update, 372 .reta_query = mlx5_dev_rss_reta_query, 373 .rss_hash_update = mlx5_rss_hash_update, 374 .rss_hash_conf_get = mlx5_rss_hash_conf_get, 375 .filter_ctrl = mlx5_dev_filter_ctrl, 376 .rx_descriptor_status = mlx5_rx_descriptor_status, 377 .tx_descriptor_status = mlx5_tx_descriptor_status, 378 .rx_queue_intr_enable = mlx5_rx_intr_enable, 379 .rx_queue_intr_disable = mlx5_rx_intr_disable, 380 .is_removed = mlx5_is_removed, 381 }; 382 383 static const struct eth_dev_ops mlx5_dev_sec_ops = { 384 .stats_get = mlx5_stats_get, 385 .stats_reset = mlx5_stats_reset, 386 .xstats_get = mlx5_xstats_get, 387 .xstats_reset = mlx5_xstats_reset, 388 .xstats_get_names = mlx5_xstats_get_names, 389 .dev_infos_get = mlx5_dev_infos_get, 390 .rx_descriptor_status = mlx5_rx_descriptor_status, 391 .tx_descriptor_status = mlx5_tx_descriptor_status, 392 }; 393 394 /* Available operators in flow isolated mode. */ 395 const struct eth_dev_ops mlx5_dev_ops_isolate = { 396 .dev_configure = mlx5_dev_configure, 397 .dev_start = mlx5_dev_start, 398 .dev_stop = mlx5_dev_stop, 399 .dev_set_link_down = mlx5_set_link_down, 400 .dev_set_link_up = mlx5_set_link_up, 401 .dev_close = mlx5_dev_close, 402 .promiscuous_enable = mlx5_promiscuous_enable, 403 .promiscuous_disable = mlx5_promiscuous_disable, 404 .allmulticast_enable = mlx5_allmulticast_enable, 405 .allmulticast_disable = mlx5_allmulticast_disable, 406 .link_update = mlx5_link_update, 407 .stats_get = mlx5_stats_get, 408 .stats_reset = mlx5_stats_reset, 409 .xstats_get = mlx5_xstats_get, 410 .xstats_reset = mlx5_xstats_reset, 411 .xstats_get_names = mlx5_xstats_get_names, 412 .dev_infos_get = mlx5_dev_infos_get, 413 .dev_supported_ptypes_get = mlx5_dev_supported_ptypes_get, 414 .vlan_filter_set = mlx5_vlan_filter_set, 415 .rx_queue_setup = mlx5_rx_queue_setup, 416 .tx_queue_setup = mlx5_tx_queue_setup, 417 .rx_queue_release = mlx5_rx_queue_release, 418 .tx_queue_release = mlx5_tx_queue_release, 419 .flow_ctrl_get = mlx5_dev_get_flow_ctrl, 420 .flow_ctrl_set = mlx5_dev_set_flow_ctrl, 421 .mac_addr_remove = mlx5_mac_addr_remove, 422 .mac_addr_add = mlx5_mac_addr_add, 423 .mac_addr_set = mlx5_mac_addr_set, 424 .set_mc_addr_list = mlx5_set_mc_addr_list, 425 .mtu_set = mlx5_dev_set_mtu, 426 .vlan_strip_queue_set = mlx5_vlan_strip_queue_set, 427 .vlan_offload_set = mlx5_vlan_offload_set, 428 .filter_ctrl = mlx5_dev_filter_ctrl, 429 .rx_descriptor_status = mlx5_rx_descriptor_status, 430 .tx_descriptor_status = mlx5_tx_descriptor_status, 431 .rx_queue_intr_enable = mlx5_rx_intr_enable, 432 .rx_queue_intr_disable = mlx5_rx_intr_disable, 433 .is_removed = mlx5_is_removed, 434 }; 435 436 /** 437 * Verify and store value for device argument. 438 * 439 * @param[in] key 440 * Key argument to verify. 441 * @param[in] val 442 * Value associated with key. 443 * @param opaque 444 * User data. 445 * 446 * @return 447 * 0 on success, a negative errno value otherwise and rte_errno is set. 448 */ 449 static int 450 mlx5_args_check(const char *key, const char *val, void *opaque) 451 { 452 struct mlx5_dev_config *config = opaque; 453 unsigned long tmp; 454 455 /* No-op, port representors are processed in mlx5_dev_spawn(). */ 456 if (!strcmp(MLX5_REPRESENTOR, key)) 457 return 0; 458 errno = 0; 459 tmp = strtoul(val, NULL, 0); 460 if (errno) { 461 rte_errno = errno; 462 DRV_LOG(WARNING, "%s: \"%s\" is not a valid integer", key, val); 463 return -rte_errno; 464 } 465 if (strcmp(MLX5_RXQ_CQE_COMP_EN, key) == 0) { 466 config->cqe_comp = !!tmp; 467 } else if (strcmp(MLX5_RX_MPRQ_EN, key) == 0) { 468 config->mprq.enabled = !!tmp; 469 } else if (strcmp(MLX5_RX_MPRQ_LOG_STRIDE_NUM, key) == 0) { 470 config->mprq.stride_num_n = tmp; 471 } else if (strcmp(MLX5_RX_MPRQ_MAX_MEMCPY_LEN, key) == 0) { 472 config->mprq.max_memcpy_len = tmp; 473 } else if (strcmp(MLX5_RXQS_MIN_MPRQ, key) == 0) { 474 config->mprq.min_rxqs_num = tmp; 475 } else if (strcmp(MLX5_TXQ_INLINE, key) == 0) { 476 config->txq_inline = tmp; 477 } else if (strcmp(MLX5_TXQS_MIN_INLINE, key) == 0) { 478 config->txqs_inline = tmp; 479 } else if (strcmp(MLX5_TXQ_MPW_EN, key) == 0) { 480 config->mps = !!tmp; 481 } else if (strcmp(MLX5_TXQ_MPW_HDR_DSEG_EN, key) == 0) { 482 config->mpw_hdr_dseg = !!tmp; 483 } else if (strcmp(MLX5_TXQ_MAX_INLINE_LEN, key) == 0) { 484 config->inline_max_packet_sz = tmp; 485 } else if (strcmp(MLX5_TX_VEC_EN, key) == 0) { 486 config->tx_vec_en = !!tmp; 487 } else if (strcmp(MLX5_RX_VEC_EN, key) == 0) { 488 config->rx_vec_en = !!tmp; 489 } else if (strcmp(MLX5_L3_VXLAN_EN, key) == 0) { 490 config->l3_vxlan_en = !!tmp; 491 } else if (strcmp(MLX5_VF_NL_EN, key) == 0) { 492 config->vf_nl_en = !!tmp; 493 } else { 494 DRV_LOG(WARNING, "%s: unknown parameter", key); 495 rte_errno = EINVAL; 496 return -rte_errno; 497 } 498 return 0; 499 } 500 501 /** 502 * Parse device parameters. 503 * 504 * @param config 505 * Pointer to device configuration structure. 506 * @param devargs 507 * Device arguments structure. 508 * 509 * @return 510 * 0 on success, a negative errno value otherwise and rte_errno is set. 511 */ 512 static int 513 mlx5_args(struct mlx5_dev_config *config, struct rte_devargs *devargs) 514 { 515 const char **params = (const char *[]){ 516 MLX5_RXQ_CQE_COMP_EN, 517 MLX5_RX_MPRQ_EN, 518 MLX5_RX_MPRQ_LOG_STRIDE_NUM, 519 MLX5_RX_MPRQ_MAX_MEMCPY_LEN, 520 MLX5_RXQS_MIN_MPRQ, 521 MLX5_TXQ_INLINE, 522 MLX5_TXQS_MIN_INLINE, 523 MLX5_TXQ_MPW_EN, 524 MLX5_TXQ_MPW_HDR_DSEG_EN, 525 MLX5_TXQ_MAX_INLINE_LEN, 526 MLX5_TX_VEC_EN, 527 MLX5_RX_VEC_EN, 528 MLX5_L3_VXLAN_EN, 529 MLX5_VF_NL_EN, 530 MLX5_REPRESENTOR, 531 NULL, 532 }; 533 struct rte_kvargs *kvlist; 534 int ret = 0; 535 int i; 536 537 if (devargs == NULL) 538 return 0; 539 /* Following UGLY cast is done to pass checkpatch. */ 540 kvlist = rte_kvargs_parse(devargs->args, params); 541 if (kvlist == NULL) 542 return 0; 543 /* Process parameters. */ 544 for (i = 0; (params[i] != NULL); ++i) { 545 if (rte_kvargs_count(kvlist, params[i])) { 546 ret = rte_kvargs_process(kvlist, params[i], 547 mlx5_args_check, config); 548 if (ret) { 549 rte_errno = EINVAL; 550 rte_kvargs_free(kvlist); 551 return -rte_errno; 552 } 553 } 554 } 555 rte_kvargs_free(kvlist); 556 return 0; 557 } 558 559 static struct rte_pci_driver mlx5_driver; 560 561 /* 562 * Reserved UAR address space for TXQ UAR(hw doorbell) mapping, process 563 * local resource used by both primary and secondary to avoid duplicate 564 * reservation. 565 * The space has to be available on both primary and secondary process, 566 * TXQ UAR maps to this area using fixed mmap w/o double check. 567 */ 568 static void *uar_base; 569 570 static int 571 find_lower_va_bound(const struct rte_memseg_list *msl, 572 const struct rte_memseg *ms, void *arg) 573 { 574 void **addr = arg; 575 576 if (msl->external) 577 return 0; 578 if (*addr == NULL) 579 *addr = ms->addr; 580 else 581 *addr = RTE_MIN(*addr, ms->addr); 582 583 return 0; 584 } 585 586 /** 587 * Reserve UAR address space for primary process. 588 * 589 * @param[in] dev 590 * Pointer to Ethernet device. 591 * 592 * @return 593 * 0 on success, a negative errno value otherwise and rte_errno is set. 594 */ 595 static int 596 mlx5_uar_init_primary(struct rte_eth_dev *dev) 597 { 598 struct priv *priv = dev->data->dev_private; 599 void *addr = (void *)0; 600 601 if (uar_base) { /* UAR address space mapped. */ 602 priv->uar_base = uar_base; 603 return 0; 604 } 605 /* find out lower bound of hugepage segments */ 606 rte_memseg_walk(find_lower_va_bound, &addr); 607 608 /* keep distance to hugepages to minimize potential conflicts. */ 609 addr = RTE_PTR_SUB(addr, (uintptr_t)(MLX5_UAR_OFFSET + MLX5_UAR_SIZE)); 610 /* anonymous mmap, no real memory consumption. */ 611 addr = mmap(addr, MLX5_UAR_SIZE, 612 PROT_NONE, MAP_PRIVATE | MAP_ANONYMOUS, -1, 0); 613 if (addr == MAP_FAILED) { 614 DRV_LOG(ERR, 615 "port %u failed to reserve UAR address space, please" 616 " adjust MLX5_UAR_SIZE or try --base-virtaddr", 617 dev->data->port_id); 618 rte_errno = ENOMEM; 619 return -rte_errno; 620 } 621 /* Accept either same addr or a new addr returned from mmap if target 622 * range occupied. 623 */ 624 DRV_LOG(INFO, "port %u reserved UAR address space: %p", 625 dev->data->port_id, addr); 626 priv->uar_base = addr; /* for primary and secondary UAR re-mmap. */ 627 uar_base = addr; /* process local, don't reserve again. */ 628 return 0; 629 } 630 631 /** 632 * Reserve UAR address space for secondary process, align with 633 * primary process. 634 * 635 * @param[in] dev 636 * Pointer to Ethernet device. 637 * 638 * @return 639 * 0 on success, a negative errno value otherwise and rte_errno is set. 640 */ 641 static int 642 mlx5_uar_init_secondary(struct rte_eth_dev *dev) 643 { 644 struct priv *priv = dev->data->dev_private; 645 void *addr; 646 647 assert(priv->uar_base); 648 if (uar_base) { /* already reserved. */ 649 assert(uar_base == priv->uar_base); 650 return 0; 651 } 652 /* anonymous mmap, no real memory consumption. */ 653 addr = mmap(priv->uar_base, MLX5_UAR_SIZE, 654 PROT_NONE, MAP_PRIVATE | MAP_ANONYMOUS, -1, 0); 655 if (addr == MAP_FAILED) { 656 DRV_LOG(ERR, "port %u UAR mmap failed: %p size: %llu", 657 dev->data->port_id, priv->uar_base, MLX5_UAR_SIZE); 658 rte_errno = ENXIO; 659 return -rte_errno; 660 } 661 if (priv->uar_base != addr) { 662 DRV_LOG(ERR, 663 "port %u UAR address %p size %llu occupied, please" 664 " adjust MLX5_UAR_OFFSET or try EAL parameter" 665 " --base-virtaddr", 666 dev->data->port_id, priv->uar_base, MLX5_UAR_SIZE); 667 rte_errno = ENXIO; 668 return -rte_errno; 669 } 670 uar_base = addr; /* process local, don't reserve again */ 671 DRV_LOG(INFO, "port %u reserved UAR address space: %p", 672 dev->data->port_id, addr); 673 return 0; 674 } 675 676 /** 677 * Spawn an Ethernet device from Verbs information. 678 * 679 * @param dpdk_dev 680 * Backing DPDK device. 681 * @param ibv_dev 682 * Verbs device. 683 * @param vf 684 * If nonzero, enable VF-specific features. 685 * @param[in] switch_info 686 * Switch properties of Ethernet device. 687 * 688 * @return 689 * A valid Ethernet device object on success, NULL otherwise and rte_errno 690 * is set. The following error is defined: 691 * 692 * EBUSY: device is not supposed to be spawned. 693 */ 694 static struct rte_eth_dev * 695 mlx5_dev_spawn(struct rte_device *dpdk_dev, 696 struct ibv_device *ibv_dev, 697 int vf, 698 const struct mlx5_switch_info *switch_info) 699 { 700 struct ibv_context *ctx; 701 struct ibv_device_attr_ex attr; 702 struct ibv_port_attr port_attr; 703 struct ibv_pd *pd = NULL; 704 struct mlx5dv_context dv_attr = { .comp_mask = 0 }; 705 struct mlx5_dev_config config = { 706 .vf = !!vf, 707 .mps = MLX5_ARG_UNSET, 708 .tx_vec_en = 1, 709 .rx_vec_en = 1, 710 .mpw_hdr_dseg = 0, 711 .txq_inline = MLX5_ARG_UNSET, 712 .txqs_inline = MLX5_ARG_UNSET, 713 .inline_max_packet_sz = MLX5_ARG_UNSET, 714 .vf_nl_en = 1, 715 .mprq = { 716 .enabled = 0, 717 .stride_num_n = MLX5_MPRQ_STRIDE_NUM_N, 718 .max_memcpy_len = MLX5_MPRQ_MEMCPY_DEFAULT_LEN, 719 .min_rxqs_num = MLX5_MPRQ_MIN_RXQS, 720 }, 721 }; 722 struct rte_eth_dev *eth_dev = NULL; 723 struct priv *priv = NULL; 724 int err = 0; 725 unsigned int mps; 726 unsigned int cqe_comp; 727 unsigned int tunnel_en = 0; 728 unsigned int mpls_en = 0; 729 unsigned int swp = 0; 730 unsigned int mprq = 0; 731 unsigned int mprq_min_stride_size_n = 0; 732 unsigned int mprq_max_stride_size_n = 0; 733 unsigned int mprq_min_stride_num_n = 0; 734 unsigned int mprq_max_stride_num_n = 0; 735 #ifdef HAVE_IBV_DEVICE_COUNTERS_SET_SUPPORT 736 struct ibv_counter_set_description cs_desc = { .counter_type = 0 }; 737 #endif 738 struct ether_addr mac; 739 char name[RTE_ETH_NAME_MAX_LEN]; 740 int own_domain_id = 0; 741 unsigned int i; 742 743 /* Determine if this port representor is supposed to be spawned. */ 744 if (switch_info->representor && dpdk_dev->devargs) { 745 struct rte_eth_devargs eth_da; 746 747 err = rte_eth_devargs_parse(dpdk_dev->devargs->args, ð_da); 748 if (err) { 749 rte_errno = -err; 750 DRV_LOG(ERR, "failed to process device arguments: %s", 751 strerror(rte_errno)); 752 return NULL; 753 } 754 for (i = 0; i < eth_da.nb_representor_ports; ++i) 755 if (eth_da.representor_ports[i] == 756 (uint16_t)switch_info->port_name) 757 break; 758 if (i == eth_da.nb_representor_ports) { 759 rte_errno = EBUSY; 760 return NULL; 761 } 762 } 763 /* Prepare shared data between primary and secondary process. */ 764 mlx5_prepare_shared_data(); 765 errno = 0; 766 ctx = mlx5_glue->open_device(ibv_dev); 767 if (!ctx) { 768 rte_errno = errno ? errno : ENODEV; 769 return NULL; 770 } 771 #ifdef HAVE_IBV_MLX5_MOD_SWP 772 dv_attr.comp_mask |= MLX5DV_CONTEXT_MASK_SWP; 773 #endif 774 /* 775 * Multi-packet send is supported by ConnectX-4 Lx PF as well 776 * as all ConnectX-5 devices. 777 */ 778 #ifdef HAVE_IBV_DEVICE_TUNNEL_SUPPORT 779 dv_attr.comp_mask |= MLX5DV_CONTEXT_MASK_TUNNEL_OFFLOADS; 780 #endif 781 #ifdef HAVE_IBV_DEVICE_STRIDING_RQ_SUPPORT 782 dv_attr.comp_mask |= MLX5DV_CONTEXT_MASK_STRIDING_RQ; 783 #endif 784 mlx5_glue->dv_query_device(ctx, &dv_attr); 785 if (dv_attr.flags & MLX5DV_CONTEXT_FLAGS_MPW_ALLOWED) { 786 if (dv_attr.flags & MLX5DV_CONTEXT_FLAGS_ENHANCED_MPW) { 787 DRV_LOG(DEBUG, "enhanced MPW is supported"); 788 mps = MLX5_MPW_ENHANCED; 789 } else { 790 DRV_LOG(DEBUG, "MPW is supported"); 791 mps = MLX5_MPW; 792 } 793 } else { 794 DRV_LOG(DEBUG, "MPW isn't supported"); 795 mps = MLX5_MPW_DISABLED; 796 } 797 #ifdef HAVE_IBV_MLX5_MOD_SWP 798 if (dv_attr.comp_mask & MLX5DV_CONTEXT_MASK_SWP) 799 swp = dv_attr.sw_parsing_caps.sw_parsing_offloads; 800 DRV_LOG(DEBUG, "SWP support: %u", swp); 801 #endif 802 config.swp = !!swp; 803 #ifdef HAVE_IBV_DEVICE_STRIDING_RQ_SUPPORT 804 if (dv_attr.comp_mask & MLX5DV_CONTEXT_MASK_STRIDING_RQ) { 805 struct mlx5dv_striding_rq_caps mprq_caps = 806 dv_attr.striding_rq_caps; 807 808 DRV_LOG(DEBUG, "\tmin_single_stride_log_num_of_bytes: %d", 809 mprq_caps.min_single_stride_log_num_of_bytes); 810 DRV_LOG(DEBUG, "\tmax_single_stride_log_num_of_bytes: %d", 811 mprq_caps.max_single_stride_log_num_of_bytes); 812 DRV_LOG(DEBUG, "\tmin_single_wqe_log_num_of_strides: %d", 813 mprq_caps.min_single_wqe_log_num_of_strides); 814 DRV_LOG(DEBUG, "\tmax_single_wqe_log_num_of_strides: %d", 815 mprq_caps.max_single_wqe_log_num_of_strides); 816 DRV_LOG(DEBUG, "\tsupported_qpts: %d", 817 mprq_caps.supported_qpts); 818 DRV_LOG(DEBUG, "device supports Multi-Packet RQ"); 819 mprq = 1; 820 mprq_min_stride_size_n = 821 mprq_caps.min_single_stride_log_num_of_bytes; 822 mprq_max_stride_size_n = 823 mprq_caps.max_single_stride_log_num_of_bytes; 824 mprq_min_stride_num_n = 825 mprq_caps.min_single_wqe_log_num_of_strides; 826 mprq_max_stride_num_n = 827 mprq_caps.max_single_wqe_log_num_of_strides; 828 config.mprq.stride_num_n = RTE_MAX(MLX5_MPRQ_STRIDE_NUM_N, 829 mprq_min_stride_num_n); 830 } 831 #endif 832 if (RTE_CACHE_LINE_SIZE == 128 && 833 !(dv_attr.flags & MLX5DV_CONTEXT_FLAGS_CQE_128B_COMP)) 834 cqe_comp = 0; 835 else 836 cqe_comp = 1; 837 config.cqe_comp = cqe_comp; 838 #ifdef HAVE_IBV_DEVICE_TUNNEL_SUPPORT 839 if (dv_attr.comp_mask & MLX5DV_CONTEXT_MASK_TUNNEL_OFFLOADS) { 840 tunnel_en = ((dv_attr.tunnel_offloads_caps & 841 MLX5DV_RAW_PACKET_CAP_TUNNELED_OFFLOAD_VXLAN) && 842 (dv_attr.tunnel_offloads_caps & 843 MLX5DV_RAW_PACKET_CAP_TUNNELED_OFFLOAD_GRE)); 844 } 845 DRV_LOG(DEBUG, "tunnel offloading is %ssupported", 846 tunnel_en ? "" : "not "); 847 #else 848 DRV_LOG(WARNING, 849 "tunnel offloading disabled due to old OFED/rdma-core version"); 850 #endif 851 config.tunnel_en = tunnel_en; 852 #ifdef HAVE_IBV_DEVICE_MPLS_SUPPORT 853 mpls_en = ((dv_attr.tunnel_offloads_caps & 854 MLX5DV_RAW_PACKET_CAP_TUNNELED_OFFLOAD_CW_MPLS_OVER_GRE) && 855 (dv_attr.tunnel_offloads_caps & 856 MLX5DV_RAW_PACKET_CAP_TUNNELED_OFFLOAD_CW_MPLS_OVER_UDP)); 857 DRV_LOG(DEBUG, "MPLS over GRE/UDP tunnel offloading is %ssupported", 858 mpls_en ? "" : "not "); 859 #else 860 DRV_LOG(WARNING, "MPLS over GRE/UDP tunnel offloading disabled due to" 861 " old OFED/rdma-core version or firmware configuration"); 862 #endif 863 config.mpls_en = mpls_en; 864 err = mlx5_glue->query_device_ex(ctx, NULL, &attr); 865 if (err) { 866 DEBUG("ibv_query_device_ex() failed"); 867 goto error; 868 } 869 if (!switch_info->representor) 870 rte_strlcpy(name, dpdk_dev->name, sizeof(name)); 871 else 872 snprintf(name, sizeof(name), "%s_representor_%u", 873 dpdk_dev->name, switch_info->port_name); 874 DRV_LOG(DEBUG, "naming Ethernet device \"%s\"", name); 875 if (rte_eal_process_type() == RTE_PROC_SECONDARY) { 876 eth_dev = rte_eth_dev_attach_secondary(name); 877 if (eth_dev == NULL) { 878 DRV_LOG(ERR, "can not attach rte ethdev"); 879 rte_errno = ENOMEM; 880 err = rte_errno; 881 goto error; 882 } 883 eth_dev->device = dpdk_dev; 884 eth_dev->dev_ops = &mlx5_dev_sec_ops; 885 err = mlx5_uar_init_secondary(eth_dev); 886 if (err) { 887 err = rte_errno; 888 goto error; 889 } 890 /* Receive command fd from primary process */ 891 err = mlx5_socket_connect(eth_dev); 892 if (err < 0) { 893 err = rte_errno; 894 goto error; 895 } 896 /* Remap UAR for Tx queues. */ 897 err = mlx5_tx_uar_remap(eth_dev, err); 898 if (err) { 899 err = rte_errno; 900 goto error; 901 } 902 /* 903 * Ethdev pointer is still required as input since 904 * the primary device is not accessible from the 905 * secondary process. 906 */ 907 eth_dev->rx_pkt_burst = mlx5_select_rx_function(eth_dev); 908 eth_dev->tx_pkt_burst = mlx5_select_tx_function(eth_dev); 909 claim_zero(mlx5_glue->close_device(ctx)); 910 return eth_dev; 911 } 912 /* Check port status. */ 913 err = mlx5_glue->query_port(ctx, 1, &port_attr); 914 if (err) { 915 DRV_LOG(ERR, "port query failed: %s", strerror(err)); 916 goto error; 917 } 918 if (port_attr.link_layer != IBV_LINK_LAYER_ETHERNET) { 919 DRV_LOG(ERR, "port is not configured in Ethernet mode"); 920 err = EINVAL; 921 goto error; 922 } 923 if (port_attr.state != IBV_PORT_ACTIVE) 924 DRV_LOG(DEBUG, "port is not active: \"%s\" (%d)", 925 mlx5_glue->port_state_str(port_attr.state), 926 port_attr.state); 927 /* Allocate protection domain. */ 928 pd = mlx5_glue->alloc_pd(ctx); 929 if (pd == NULL) { 930 DRV_LOG(ERR, "PD allocation failure"); 931 err = ENOMEM; 932 goto error; 933 } 934 priv = rte_zmalloc("ethdev private structure", 935 sizeof(*priv), 936 RTE_CACHE_LINE_SIZE); 937 if (priv == NULL) { 938 DRV_LOG(ERR, "priv allocation failure"); 939 err = ENOMEM; 940 goto error; 941 } 942 priv->ctx = ctx; 943 strncpy(priv->ibdev_name, priv->ctx->device->name, 944 sizeof(priv->ibdev_name)); 945 strncpy(priv->ibdev_path, priv->ctx->device->ibdev_path, 946 sizeof(priv->ibdev_path)); 947 priv->device_attr = attr; 948 priv->pd = pd; 949 priv->mtu = ETHER_MTU; 950 #ifndef RTE_ARCH_64 951 /* Initialize UAR access locks for 32bit implementations. */ 952 rte_spinlock_init(&priv->uar_lock_cq); 953 for (i = 0; i < MLX5_UAR_PAGE_NUM_MAX; i++) 954 rte_spinlock_init(&priv->uar_lock[i]); 955 #endif 956 /* Some internal functions rely on Netlink sockets, open them now. */ 957 priv->nl_socket_rdma = mlx5_nl_init(NETLINK_RDMA); 958 priv->nl_socket_route = mlx5_nl_init(NETLINK_ROUTE); 959 priv->nl_sn = 0; 960 priv->representor = !!switch_info->representor; 961 priv->domain_id = RTE_ETH_DEV_SWITCH_DOMAIN_ID_INVALID; 962 priv->representor_id = 963 switch_info->representor ? switch_info->port_name : -1; 964 /* 965 * Look for sibling devices in order to reuse their switch domain 966 * if any, otherwise allocate one. 967 */ 968 i = mlx5_dev_to_port_id(dpdk_dev, NULL, 0); 969 if (i > 0) { 970 uint16_t port_id[i]; 971 972 i = RTE_MIN(mlx5_dev_to_port_id(dpdk_dev, port_id, i), i); 973 while (i--) { 974 const struct priv *opriv = 975 rte_eth_devices[port_id[i]].data->dev_private; 976 977 if (!opriv || 978 opriv->domain_id == 979 RTE_ETH_DEV_SWITCH_DOMAIN_ID_INVALID) 980 continue; 981 priv->domain_id = opriv->domain_id; 982 break; 983 } 984 } 985 if (priv->domain_id == RTE_ETH_DEV_SWITCH_DOMAIN_ID_INVALID) { 986 err = rte_eth_switch_domain_alloc(&priv->domain_id); 987 if (err) { 988 err = rte_errno; 989 DRV_LOG(ERR, "unable to allocate switch domain: %s", 990 strerror(rte_errno)); 991 goto error; 992 } 993 own_domain_id = 1; 994 } 995 err = mlx5_args(&config, dpdk_dev->devargs); 996 if (err) { 997 err = rte_errno; 998 DRV_LOG(ERR, "failed to process device arguments: %s", 999 strerror(rte_errno)); 1000 goto error; 1001 } 1002 config.hw_csum = !!(attr.device_cap_flags_ex & IBV_DEVICE_RAW_IP_CSUM); 1003 DRV_LOG(DEBUG, "checksum offloading is %ssupported", 1004 (config.hw_csum ? "" : "not ")); 1005 #ifdef HAVE_IBV_DEVICE_COUNTERS_SET_SUPPORT 1006 config.flow_counter_en = !!attr.max_counter_sets; 1007 mlx5_glue->describe_counter_set(ctx, 0, &cs_desc); 1008 DRV_LOG(DEBUG, "counter type = %d, num of cs = %ld, attributes = %d", 1009 cs_desc.counter_type, cs_desc.num_of_cs, 1010 cs_desc.attributes); 1011 #endif 1012 config.ind_table_max_size = 1013 attr.rss_caps.max_rwq_indirection_table_size; 1014 /* 1015 * Remove this check once DPDK supports larger/variable 1016 * indirection tables. 1017 */ 1018 if (config.ind_table_max_size > (unsigned int)ETH_RSS_RETA_SIZE_512) 1019 config.ind_table_max_size = ETH_RSS_RETA_SIZE_512; 1020 DRV_LOG(DEBUG, "maximum Rx indirection table size is %u", 1021 config.ind_table_max_size); 1022 config.hw_vlan_strip = !!(attr.raw_packet_caps & 1023 IBV_RAW_PACKET_CAP_CVLAN_STRIPPING); 1024 DRV_LOG(DEBUG, "VLAN stripping is %ssupported", 1025 (config.hw_vlan_strip ? "" : "not ")); 1026 config.hw_fcs_strip = !!(attr.raw_packet_caps & 1027 IBV_RAW_PACKET_CAP_SCATTER_FCS); 1028 DRV_LOG(DEBUG, "FCS stripping configuration is %ssupported", 1029 (config.hw_fcs_strip ? "" : "not ")); 1030 #ifdef HAVE_IBV_WQ_FLAG_RX_END_PADDING 1031 config.hw_padding = !!attr.rx_pad_end_addr_align; 1032 #endif 1033 DRV_LOG(DEBUG, "hardware Rx end alignment padding is %ssupported", 1034 (config.hw_padding ? "" : "not ")); 1035 config.tso = (attr.tso_caps.max_tso > 0 && 1036 (attr.tso_caps.supported_qpts & 1037 (1 << IBV_QPT_RAW_PACKET))); 1038 if (config.tso) 1039 config.tso_max_payload_sz = attr.tso_caps.max_tso; 1040 /* 1041 * MPW is disabled by default, while the Enhanced MPW is enabled 1042 * by default. 1043 */ 1044 if (config.mps == MLX5_ARG_UNSET) 1045 config.mps = (mps == MLX5_MPW_ENHANCED) ? MLX5_MPW_ENHANCED : 1046 MLX5_MPW_DISABLED; 1047 else 1048 config.mps = config.mps ? mps : MLX5_MPW_DISABLED; 1049 DRV_LOG(INFO, "%sMPS is %s", 1050 config.mps == MLX5_MPW_ENHANCED ? "enhanced " : "", 1051 config.mps != MLX5_MPW_DISABLED ? "enabled" : "disabled"); 1052 if (config.cqe_comp && !cqe_comp) { 1053 DRV_LOG(WARNING, "Rx CQE compression isn't supported"); 1054 config.cqe_comp = 0; 1055 } 1056 if (config.mprq.enabled && mprq) { 1057 if (config.mprq.stride_num_n > mprq_max_stride_num_n || 1058 config.mprq.stride_num_n < mprq_min_stride_num_n) { 1059 config.mprq.stride_num_n = 1060 RTE_MAX(MLX5_MPRQ_STRIDE_NUM_N, 1061 mprq_min_stride_num_n); 1062 DRV_LOG(WARNING, 1063 "the number of strides" 1064 " for Multi-Packet RQ is out of range," 1065 " setting default value (%u)", 1066 1 << config.mprq.stride_num_n); 1067 } 1068 config.mprq.min_stride_size_n = mprq_min_stride_size_n; 1069 config.mprq.max_stride_size_n = mprq_max_stride_size_n; 1070 } else if (config.mprq.enabled && !mprq) { 1071 DRV_LOG(WARNING, "Multi-Packet RQ isn't supported"); 1072 config.mprq.enabled = 0; 1073 } 1074 eth_dev = rte_eth_dev_allocate(name); 1075 if (eth_dev == NULL) { 1076 DRV_LOG(ERR, "can not allocate rte ethdev"); 1077 err = ENOMEM; 1078 goto error; 1079 } 1080 if (priv->representor) 1081 eth_dev->data->dev_flags |= RTE_ETH_DEV_REPRESENTOR; 1082 eth_dev->data->dev_private = priv; 1083 priv->dev_data = eth_dev->data; 1084 eth_dev->data->mac_addrs = priv->mac; 1085 eth_dev->device = dpdk_dev; 1086 eth_dev->device->driver = &mlx5_driver.driver; 1087 err = mlx5_uar_init_primary(eth_dev); 1088 if (err) { 1089 err = rte_errno; 1090 goto error; 1091 } 1092 /* Configure the first MAC address by default. */ 1093 if (mlx5_get_mac(eth_dev, &mac.addr_bytes)) { 1094 DRV_LOG(ERR, 1095 "port %u cannot get MAC address, is mlx5_en" 1096 " loaded? (errno: %s)", 1097 eth_dev->data->port_id, strerror(rte_errno)); 1098 err = ENODEV; 1099 goto error; 1100 } 1101 DRV_LOG(INFO, 1102 "port %u MAC address is %02x:%02x:%02x:%02x:%02x:%02x", 1103 eth_dev->data->port_id, 1104 mac.addr_bytes[0], mac.addr_bytes[1], 1105 mac.addr_bytes[2], mac.addr_bytes[3], 1106 mac.addr_bytes[4], mac.addr_bytes[5]); 1107 #ifndef NDEBUG 1108 { 1109 char ifname[IF_NAMESIZE]; 1110 1111 if (mlx5_get_ifname(eth_dev, &ifname) == 0) 1112 DRV_LOG(DEBUG, "port %u ifname is \"%s\"", 1113 eth_dev->data->port_id, ifname); 1114 else 1115 DRV_LOG(DEBUG, "port %u ifname is unknown", 1116 eth_dev->data->port_id); 1117 } 1118 #endif 1119 /* Get actual MTU if possible. */ 1120 err = mlx5_get_mtu(eth_dev, &priv->mtu); 1121 if (err) { 1122 err = rte_errno; 1123 goto error; 1124 } 1125 DRV_LOG(DEBUG, "port %u MTU is %u", eth_dev->data->port_id, 1126 priv->mtu); 1127 /* Initialize burst functions to prevent crashes before link-up. */ 1128 eth_dev->rx_pkt_burst = removed_rx_burst; 1129 eth_dev->tx_pkt_burst = removed_tx_burst; 1130 eth_dev->dev_ops = &mlx5_dev_ops; 1131 /* Register MAC address. */ 1132 claim_zero(mlx5_mac_addr_add(eth_dev, &mac, 0, 0)); 1133 if (vf && config.vf_nl_en) 1134 mlx5_nl_mac_addr_sync(eth_dev); 1135 priv->mnl_socket = mlx5_nl_flow_socket_create(); 1136 if (!priv->mnl_socket) { 1137 err = -rte_errno; 1138 DRV_LOG(WARNING, 1139 "flow rules relying on switch offloads will not be" 1140 " supported: cannot open libmnl socket: %s", 1141 strerror(rte_errno)); 1142 } else { 1143 struct rte_flow_error error; 1144 unsigned int ifindex = mlx5_ifindex(eth_dev); 1145 1146 if (!ifindex) { 1147 err = -rte_errno; 1148 error.message = 1149 "cannot retrieve network interface index"; 1150 } else { 1151 err = mlx5_nl_flow_init(priv->mnl_socket, ifindex, 1152 &error); 1153 } 1154 if (err) { 1155 DRV_LOG(WARNING, 1156 "flow rules relying on switch offloads will" 1157 " not be supported: %s: %s", 1158 error.message, strerror(rte_errno)); 1159 mlx5_nl_flow_socket_destroy(priv->mnl_socket); 1160 priv->mnl_socket = NULL; 1161 } 1162 } 1163 TAILQ_INIT(&priv->flows); 1164 TAILQ_INIT(&priv->ctrl_flows); 1165 /* Hint libmlx5 to use PMD allocator for data plane resources */ 1166 struct mlx5dv_ctx_allocators alctr = { 1167 .alloc = &mlx5_alloc_verbs_buf, 1168 .free = &mlx5_free_verbs_buf, 1169 .data = priv, 1170 }; 1171 mlx5_glue->dv_set_context_attr(ctx, MLX5DV_CTX_ATTR_BUF_ALLOCATORS, 1172 (void *)((uintptr_t)&alctr)); 1173 /* Bring Ethernet device up. */ 1174 DRV_LOG(DEBUG, "port %u forcing Ethernet interface up", 1175 eth_dev->data->port_id); 1176 mlx5_set_link_up(eth_dev); 1177 /* 1178 * Even though the interrupt handler is not installed yet, 1179 * interrupts will still trigger on the asyn_fd from 1180 * Verbs context returned by ibv_open_device(). 1181 */ 1182 mlx5_link_update(eth_dev, 0); 1183 /* Store device configuration on private structure. */ 1184 priv->config = config; 1185 /* Supported Verbs flow priority number detection. */ 1186 err = mlx5_flow_discover_priorities(eth_dev); 1187 if (err < 0) 1188 goto error; 1189 priv->config.flow_prio = err; 1190 /* 1191 * Once the device is added to the list of memory event 1192 * callback, its global MR cache table cannot be expanded 1193 * on the fly because of deadlock. If it overflows, lookup 1194 * should be done by searching MR list linearly, which is slow. 1195 */ 1196 err = mlx5_mr_btree_init(&priv->mr.cache, 1197 MLX5_MR_BTREE_CACHE_N * 2, 1198 eth_dev->device->numa_node); 1199 if (err) { 1200 err = rte_errno; 1201 goto error; 1202 } 1203 /* Add device to memory callback list. */ 1204 rte_rwlock_write_lock(&mlx5_shared_data->mem_event_rwlock); 1205 LIST_INSERT_HEAD(&mlx5_shared_data->mem_event_cb_list, 1206 priv, mem_event_cb); 1207 rte_rwlock_write_unlock(&mlx5_shared_data->mem_event_rwlock); 1208 return eth_dev; 1209 error: 1210 if (priv) { 1211 if (priv->nl_socket_route >= 0) 1212 close(priv->nl_socket_route); 1213 if (priv->nl_socket_rdma >= 0) 1214 close(priv->nl_socket_rdma); 1215 if (priv->mnl_socket) 1216 mlx5_nl_flow_socket_destroy(priv->mnl_socket); 1217 if (own_domain_id) 1218 claim_zero(rte_eth_switch_domain_free(priv->domain_id)); 1219 rte_free(priv); 1220 } 1221 if (pd) 1222 claim_zero(mlx5_glue->dealloc_pd(pd)); 1223 if (eth_dev) 1224 rte_eth_dev_release_port(eth_dev); 1225 if (ctx) 1226 claim_zero(mlx5_glue->close_device(ctx)); 1227 assert(err > 0); 1228 rte_errno = err; 1229 return NULL; 1230 } 1231 1232 /** Data associated with devices to spawn. */ 1233 struct mlx5_dev_spawn_data { 1234 unsigned int ifindex; /**< Network interface index. */ 1235 struct mlx5_switch_info info; /**< Switch information. */ 1236 struct ibv_device *ibv_dev; /**< Associated IB device. */ 1237 struct rte_eth_dev *eth_dev; /**< Associated Ethernet device. */ 1238 }; 1239 1240 /** 1241 * Comparison callback to sort device data. 1242 * 1243 * This is meant to be used with qsort(). 1244 * 1245 * @param a[in] 1246 * Pointer to pointer to first data object. 1247 * @param b[in] 1248 * Pointer to pointer to second data object. 1249 * 1250 * @return 1251 * 0 if both objects are equal, less than 0 if the first argument is less 1252 * than the second, greater than 0 otherwise. 1253 */ 1254 static int 1255 mlx5_dev_spawn_data_cmp(const void *a, const void *b) 1256 { 1257 const struct mlx5_switch_info *si_a = 1258 &((const struct mlx5_dev_spawn_data *)a)->info; 1259 const struct mlx5_switch_info *si_b = 1260 &((const struct mlx5_dev_spawn_data *)b)->info; 1261 int ret; 1262 1263 /* Master device first. */ 1264 ret = si_b->master - si_a->master; 1265 if (ret) 1266 return ret; 1267 /* Then representor devices. */ 1268 ret = si_b->representor - si_a->representor; 1269 if (ret) 1270 return ret; 1271 /* Unidentified devices come last in no specific order. */ 1272 if (!si_a->representor) 1273 return 0; 1274 /* Order representors by name. */ 1275 return si_a->port_name - si_b->port_name; 1276 } 1277 1278 /** 1279 * DPDK callback to register a PCI device. 1280 * 1281 * This function spawns Ethernet devices out of a given PCI device. 1282 * 1283 * @param[in] pci_drv 1284 * PCI driver structure (mlx5_driver). 1285 * @param[in] pci_dev 1286 * PCI device information. 1287 * 1288 * @return 1289 * 0 on success, a negative errno value otherwise and rte_errno is set. 1290 */ 1291 static int 1292 mlx5_pci_probe(struct rte_pci_driver *pci_drv __rte_unused, 1293 struct rte_pci_device *pci_dev) 1294 { 1295 struct ibv_device **ibv_list; 1296 unsigned int n = 0; 1297 int vf; 1298 int ret; 1299 1300 assert(pci_drv == &mlx5_driver); 1301 errno = 0; 1302 ibv_list = mlx5_glue->get_device_list(&ret); 1303 if (!ibv_list) { 1304 rte_errno = errno ? errno : ENOSYS; 1305 DRV_LOG(ERR, "cannot list devices, is ib_uverbs loaded?"); 1306 return -rte_errno; 1307 } 1308 1309 struct ibv_device *ibv_match[ret + 1]; 1310 1311 while (ret-- > 0) { 1312 struct rte_pci_addr pci_addr; 1313 1314 DRV_LOG(DEBUG, "checking device \"%s\"", ibv_list[ret]->name); 1315 if (mlx5_ibv_device_to_pci_addr(ibv_list[ret], &pci_addr)) 1316 continue; 1317 if (pci_dev->addr.domain != pci_addr.domain || 1318 pci_dev->addr.bus != pci_addr.bus || 1319 pci_dev->addr.devid != pci_addr.devid || 1320 pci_dev->addr.function != pci_addr.function) 1321 continue; 1322 DRV_LOG(INFO, "PCI information matches for device \"%s\"", 1323 ibv_list[ret]->name); 1324 ibv_match[n++] = ibv_list[ret]; 1325 } 1326 ibv_match[n] = NULL; 1327 1328 struct mlx5_dev_spawn_data list[n]; 1329 int nl_route = n ? mlx5_nl_init(NETLINK_ROUTE) : -1; 1330 int nl_rdma = n ? mlx5_nl_init(NETLINK_RDMA) : -1; 1331 unsigned int i; 1332 unsigned int u; 1333 1334 /* 1335 * The existence of several matching entries (n > 1) means port 1336 * representors have been instantiated. No existing Verbs call nor 1337 * /sys entries can tell them apart, this can only be done through 1338 * Netlink calls assuming kernel drivers are recent enough to 1339 * support them. 1340 * 1341 * In the event of identification failure through Netlink, try again 1342 * through sysfs, then either: 1343 * 1344 * 1. No device matches (n == 0), complain and bail out. 1345 * 2. A single IB device matches (n == 1) and is not a representor, 1346 * assume no switch support. 1347 * 3. Otherwise no safe assumptions can be made; complain louder and 1348 * bail out. 1349 */ 1350 for (i = 0; i != n; ++i) { 1351 list[i].ibv_dev = ibv_match[i]; 1352 list[i].eth_dev = NULL; 1353 if (nl_rdma < 0) 1354 list[i].ifindex = 0; 1355 else 1356 list[i].ifindex = mlx5_nl_ifindex 1357 (nl_rdma, list[i].ibv_dev->name); 1358 if (nl_route < 0 || 1359 !list[i].ifindex || 1360 mlx5_nl_switch_info(nl_route, list[i].ifindex, 1361 &list[i].info) || 1362 ((!list[i].info.representor && !list[i].info.master) && 1363 mlx5_sysfs_switch_info(list[i].ifindex, &list[i].info))) { 1364 list[i].ifindex = 0; 1365 memset(&list[i].info, 0, sizeof(list[i].info)); 1366 continue; 1367 } 1368 } 1369 if (nl_rdma >= 0) 1370 close(nl_rdma); 1371 if (nl_route >= 0) 1372 close(nl_route); 1373 /* Count unidentified devices. */ 1374 for (u = 0, i = 0; i != n; ++i) 1375 if (!list[i].info.master && !list[i].info.representor) 1376 ++u; 1377 if (u) { 1378 if (n == 1 && u == 1) { 1379 /* Case #2. */ 1380 DRV_LOG(INFO, "no switch support detected"); 1381 } else { 1382 /* Case #3. */ 1383 DRV_LOG(ERR, 1384 "unable to tell which of the matching devices" 1385 " is the master (lack of kernel support?)"); 1386 n = 0; 1387 } 1388 } 1389 /* 1390 * Sort list to probe devices in natural order for users convenience 1391 * (i.e. master first, then representors from lowest to highest ID). 1392 */ 1393 if (n) 1394 qsort(list, n, sizeof(*list), mlx5_dev_spawn_data_cmp); 1395 switch (pci_dev->id.device_id) { 1396 case PCI_DEVICE_ID_MELLANOX_CONNECTX4VF: 1397 case PCI_DEVICE_ID_MELLANOX_CONNECTX4LXVF: 1398 case PCI_DEVICE_ID_MELLANOX_CONNECTX5VF: 1399 case PCI_DEVICE_ID_MELLANOX_CONNECTX5EXVF: 1400 vf = 1; 1401 break; 1402 default: 1403 vf = 0; 1404 } 1405 for (i = 0; i != n; ++i) { 1406 uint32_t restore; 1407 1408 list[i].eth_dev = mlx5_dev_spawn 1409 (&pci_dev->device, list[i].ibv_dev, vf, &list[i].info); 1410 if (!list[i].eth_dev) { 1411 if (rte_errno != EBUSY) 1412 break; 1413 /* Device is disabled, ignore it. */ 1414 continue; 1415 } 1416 restore = list[i].eth_dev->data->dev_flags; 1417 rte_eth_copy_pci_info(list[i].eth_dev, pci_dev); 1418 /* Restore non-PCI flags cleared by the above call. */ 1419 list[i].eth_dev->data->dev_flags |= restore; 1420 rte_eth_dev_probing_finish(list[i].eth_dev); 1421 } 1422 mlx5_glue->free_device_list(ibv_list); 1423 if (!n) { 1424 DRV_LOG(WARNING, 1425 "no Verbs device matches PCI device " PCI_PRI_FMT "," 1426 " are kernel drivers loaded?", 1427 pci_dev->addr.domain, pci_dev->addr.bus, 1428 pci_dev->addr.devid, pci_dev->addr.function); 1429 rte_errno = ENOENT; 1430 ret = -rte_errno; 1431 } else if (i != n) { 1432 DRV_LOG(ERR, 1433 "probe of PCI device " PCI_PRI_FMT " aborted after" 1434 " encountering an error: %s", 1435 pci_dev->addr.domain, pci_dev->addr.bus, 1436 pci_dev->addr.devid, pci_dev->addr.function, 1437 strerror(rte_errno)); 1438 ret = -rte_errno; 1439 /* Roll back. */ 1440 while (i--) { 1441 if (!list[i].eth_dev) 1442 continue; 1443 mlx5_dev_close(list[i].eth_dev); 1444 if (rte_eal_process_type() == RTE_PROC_PRIMARY) 1445 rte_free(list[i].eth_dev->data->dev_private); 1446 claim_zero(rte_eth_dev_release_port(list[i].eth_dev)); 1447 } 1448 /* Restore original error. */ 1449 rte_errno = -ret; 1450 } else { 1451 ret = 0; 1452 } 1453 return ret; 1454 } 1455 1456 static const struct rte_pci_id mlx5_pci_id_map[] = { 1457 { 1458 RTE_PCI_DEVICE(PCI_VENDOR_ID_MELLANOX, 1459 PCI_DEVICE_ID_MELLANOX_CONNECTX4) 1460 }, 1461 { 1462 RTE_PCI_DEVICE(PCI_VENDOR_ID_MELLANOX, 1463 PCI_DEVICE_ID_MELLANOX_CONNECTX4VF) 1464 }, 1465 { 1466 RTE_PCI_DEVICE(PCI_VENDOR_ID_MELLANOX, 1467 PCI_DEVICE_ID_MELLANOX_CONNECTX4LX) 1468 }, 1469 { 1470 RTE_PCI_DEVICE(PCI_VENDOR_ID_MELLANOX, 1471 PCI_DEVICE_ID_MELLANOX_CONNECTX4LXVF) 1472 }, 1473 { 1474 RTE_PCI_DEVICE(PCI_VENDOR_ID_MELLANOX, 1475 PCI_DEVICE_ID_MELLANOX_CONNECTX5) 1476 }, 1477 { 1478 RTE_PCI_DEVICE(PCI_VENDOR_ID_MELLANOX, 1479 PCI_DEVICE_ID_MELLANOX_CONNECTX5VF) 1480 }, 1481 { 1482 RTE_PCI_DEVICE(PCI_VENDOR_ID_MELLANOX, 1483 PCI_DEVICE_ID_MELLANOX_CONNECTX5EX) 1484 }, 1485 { 1486 RTE_PCI_DEVICE(PCI_VENDOR_ID_MELLANOX, 1487 PCI_DEVICE_ID_MELLANOX_CONNECTX5EXVF) 1488 }, 1489 { 1490 RTE_PCI_DEVICE(PCI_VENDOR_ID_MELLANOX, 1491 PCI_DEVICE_ID_MELLANOX_CONNECTX5BF) 1492 }, 1493 { 1494 RTE_PCI_DEVICE(PCI_VENDOR_ID_MELLANOX, 1495 PCI_DEVICE_ID_MELLANOX_CONNECTX5BFVF) 1496 }, 1497 { 1498 .vendor_id = 0 1499 } 1500 }; 1501 1502 static struct rte_pci_driver mlx5_driver = { 1503 .driver = { 1504 .name = MLX5_DRIVER_NAME 1505 }, 1506 .id_table = mlx5_pci_id_map, 1507 .probe = mlx5_pci_probe, 1508 .drv_flags = RTE_PCI_DRV_INTR_LSC | RTE_PCI_DRV_INTR_RMV, 1509 }; 1510 1511 #ifdef RTE_LIBRTE_MLX5_DLOPEN_DEPS 1512 1513 /** 1514 * Suffix RTE_EAL_PMD_PATH with "-glue". 1515 * 1516 * This function performs a sanity check on RTE_EAL_PMD_PATH before 1517 * suffixing its last component. 1518 * 1519 * @param buf[out] 1520 * Output buffer, should be large enough otherwise NULL is returned. 1521 * @param size 1522 * Size of @p out. 1523 * 1524 * @return 1525 * Pointer to @p buf or @p NULL in case suffix cannot be appended. 1526 */ 1527 static char * 1528 mlx5_glue_path(char *buf, size_t size) 1529 { 1530 static const char *const bad[] = { "/", ".", "..", NULL }; 1531 const char *path = RTE_EAL_PMD_PATH; 1532 size_t len = strlen(path); 1533 size_t off; 1534 int i; 1535 1536 while (len && path[len - 1] == '/') 1537 --len; 1538 for (off = len; off && path[off - 1] != '/'; --off) 1539 ; 1540 for (i = 0; bad[i]; ++i) 1541 if (!strncmp(path + off, bad[i], (int)(len - off))) 1542 goto error; 1543 i = snprintf(buf, size, "%.*s-glue", (int)len, path); 1544 if (i == -1 || (size_t)i >= size) 1545 goto error; 1546 return buf; 1547 error: 1548 DRV_LOG(ERR, 1549 "unable to append \"-glue\" to last component of" 1550 " RTE_EAL_PMD_PATH (\"" RTE_EAL_PMD_PATH "\")," 1551 " please re-configure DPDK"); 1552 return NULL; 1553 } 1554 1555 /** 1556 * Initialization routine for run-time dependency on rdma-core. 1557 */ 1558 static int 1559 mlx5_glue_init(void) 1560 { 1561 char glue_path[sizeof(RTE_EAL_PMD_PATH) - 1 + sizeof("-glue")]; 1562 const char *path[] = { 1563 /* 1564 * A basic security check is necessary before trusting 1565 * MLX5_GLUE_PATH, which may override RTE_EAL_PMD_PATH. 1566 */ 1567 (geteuid() == getuid() && getegid() == getgid() ? 1568 getenv("MLX5_GLUE_PATH") : NULL), 1569 /* 1570 * When RTE_EAL_PMD_PATH is set, use its glue-suffixed 1571 * variant, otherwise let dlopen() look up libraries on its 1572 * own. 1573 */ 1574 (*RTE_EAL_PMD_PATH ? 1575 mlx5_glue_path(glue_path, sizeof(glue_path)) : ""), 1576 }; 1577 unsigned int i = 0; 1578 void *handle = NULL; 1579 void **sym; 1580 const char *dlmsg; 1581 1582 while (!handle && i != RTE_DIM(path)) { 1583 const char *end; 1584 size_t len; 1585 int ret; 1586 1587 if (!path[i]) { 1588 ++i; 1589 continue; 1590 } 1591 end = strpbrk(path[i], ":;"); 1592 if (!end) 1593 end = path[i] + strlen(path[i]); 1594 len = end - path[i]; 1595 ret = 0; 1596 do { 1597 char name[ret + 1]; 1598 1599 ret = snprintf(name, sizeof(name), "%.*s%s" MLX5_GLUE, 1600 (int)len, path[i], 1601 (!len || *(end - 1) == '/') ? "" : "/"); 1602 if (ret == -1) 1603 break; 1604 if (sizeof(name) != (size_t)ret + 1) 1605 continue; 1606 DRV_LOG(DEBUG, "looking for rdma-core glue as \"%s\"", 1607 name); 1608 handle = dlopen(name, RTLD_LAZY); 1609 break; 1610 } while (1); 1611 path[i] = end + 1; 1612 if (!*end) 1613 ++i; 1614 } 1615 if (!handle) { 1616 rte_errno = EINVAL; 1617 dlmsg = dlerror(); 1618 if (dlmsg) 1619 DRV_LOG(WARNING, "cannot load glue library: %s", dlmsg); 1620 goto glue_error; 1621 } 1622 sym = dlsym(handle, "mlx5_glue"); 1623 if (!sym || !*sym) { 1624 rte_errno = EINVAL; 1625 dlmsg = dlerror(); 1626 if (dlmsg) 1627 DRV_LOG(ERR, "cannot resolve glue symbol: %s", dlmsg); 1628 goto glue_error; 1629 } 1630 mlx5_glue = *sym; 1631 return 0; 1632 glue_error: 1633 if (handle) 1634 dlclose(handle); 1635 DRV_LOG(WARNING, 1636 "cannot initialize PMD due to missing run-time dependency on" 1637 " rdma-core libraries (libibverbs, libmlx5)"); 1638 return -rte_errno; 1639 } 1640 1641 #endif 1642 1643 /** 1644 * Driver initialization routine. 1645 */ 1646 RTE_INIT(rte_mlx5_pmd_init) 1647 { 1648 /* Initialize driver log type. */ 1649 mlx5_logtype = rte_log_register("pmd.net.mlx5"); 1650 if (mlx5_logtype >= 0) 1651 rte_log_set_level(mlx5_logtype, RTE_LOG_NOTICE); 1652 1653 /* Build the static tables for Verbs conversion. */ 1654 mlx5_set_ptype_table(); 1655 mlx5_set_cksum_table(); 1656 mlx5_set_swp_types_table(); 1657 /* 1658 * RDMAV_HUGEPAGES_SAFE tells ibv_fork_init() we intend to use 1659 * huge pages. Calling ibv_fork_init() during init allows 1660 * applications to use fork() safely for purposes other than 1661 * using this PMD, which is not supported in forked processes. 1662 */ 1663 setenv("RDMAV_HUGEPAGES_SAFE", "1", 1); 1664 /* Match the size of Rx completion entry to the size of a cacheline. */ 1665 if (RTE_CACHE_LINE_SIZE == 128) 1666 setenv("MLX5_CQE_SIZE", "128", 0); 1667 /* 1668 * MLX5_DEVICE_FATAL_CLEANUP tells ibv_destroy functions to 1669 * cleanup all the Verbs resources even when the device was removed. 1670 */ 1671 setenv("MLX5_DEVICE_FATAL_CLEANUP", "1", 1); 1672 #ifdef RTE_LIBRTE_MLX5_DLOPEN_DEPS 1673 if (mlx5_glue_init()) 1674 return; 1675 assert(mlx5_glue); 1676 #endif 1677 #ifndef NDEBUG 1678 /* Glue structure must not contain any NULL pointers. */ 1679 { 1680 unsigned int i; 1681 1682 for (i = 0; i != sizeof(*mlx5_glue) / sizeof(void *); ++i) 1683 assert(((const void *const *)mlx5_glue)[i]); 1684 } 1685 #endif 1686 if (strcmp(mlx5_glue->version, MLX5_GLUE_VERSION)) { 1687 DRV_LOG(ERR, 1688 "rdma-core glue \"%s\" mismatch: \"%s\" is required", 1689 mlx5_glue->version, MLX5_GLUE_VERSION); 1690 return; 1691 } 1692 mlx5_glue->fork_init(); 1693 rte_pci_register(&mlx5_driver); 1694 } 1695 1696 RTE_PMD_EXPORT_NAME(net_mlx5, __COUNTER__); 1697 RTE_PMD_REGISTER_PCI_TABLE(net_mlx5, mlx5_pci_id_map); 1698 RTE_PMD_REGISTER_KMOD_DEP(net_mlx5, "* ib_uverbs & mlx5_core & mlx5_ib"); 1699