1 /* SPDX-License-Identifier: BSD-3-Clause 2 * Copyright 2015 6WIND S.A. 3 * Copyright 2015 Mellanox Technologies, Ltd 4 */ 5 6 #include <stddef.h> 7 #include <unistd.h> 8 #include <string.h> 9 #include <assert.h> 10 #include <dlfcn.h> 11 #include <stdint.h> 12 #include <stdlib.h> 13 #include <errno.h> 14 #include <net/if.h> 15 #include <sys/mman.h> 16 #include <linux/netlink.h> 17 #include <linux/rtnetlink.h> 18 19 /* Verbs header. */ 20 /* ISO C doesn't support unnamed structs/unions, disabling -pedantic. */ 21 #ifdef PEDANTIC 22 #pragma GCC diagnostic ignored "-Wpedantic" 23 #endif 24 #include <infiniband/verbs.h> 25 #ifdef PEDANTIC 26 #pragma GCC diagnostic error "-Wpedantic" 27 #endif 28 29 #include <rte_malloc.h> 30 #include <rte_ethdev_driver.h> 31 #include <rte_ethdev_pci.h> 32 #include <rte_pci.h> 33 #include <rte_bus_pci.h> 34 #include <rte_common.h> 35 #include <rte_config.h> 36 #include <rte_eal_memconfig.h> 37 #include <rte_kvargs.h> 38 #include <rte_rwlock.h> 39 #include <rte_spinlock.h> 40 #include <rte_string_fns.h> 41 42 #include "mlx5.h" 43 #include "mlx5_utils.h" 44 #include "mlx5_rxtx.h" 45 #include "mlx5_autoconf.h" 46 #include "mlx5_defs.h" 47 #include "mlx5_glue.h" 48 #include "mlx5_mr.h" 49 #include "mlx5_flow.h" 50 51 /* Device parameter to enable RX completion queue compression. */ 52 #define MLX5_RXQ_CQE_COMP_EN "rxq_cqe_comp_en" 53 54 /* Device parameter to enable Multi-Packet Rx queue. */ 55 #define MLX5_RX_MPRQ_EN "mprq_en" 56 57 /* Device parameter to configure log 2 of the number of strides for MPRQ. */ 58 #define MLX5_RX_MPRQ_LOG_STRIDE_NUM "mprq_log_stride_num" 59 60 /* Device parameter to limit the size of memcpy'd packet for MPRQ. */ 61 #define MLX5_RX_MPRQ_MAX_MEMCPY_LEN "mprq_max_memcpy_len" 62 63 /* Device parameter to set the minimum number of Rx queues to enable MPRQ. */ 64 #define MLX5_RXQS_MIN_MPRQ "rxqs_min_mprq" 65 66 /* Device parameter to configure inline send. */ 67 #define MLX5_TXQ_INLINE "txq_inline" 68 69 /* 70 * Device parameter to configure the number of TX queues threshold for 71 * enabling inline send. 72 */ 73 #define MLX5_TXQS_MIN_INLINE "txqs_min_inline" 74 75 /* Device parameter to enable multi-packet send WQEs. */ 76 #define MLX5_TXQ_MPW_EN "txq_mpw_en" 77 78 /* Device parameter to include 2 dsegs in the title WQEBB. */ 79 #define MLX5_TXQ_MPW_HDR_DSEG_EN "txq_mpw_hdr_dseg_en" 80 81 /* Device parameter to limit the size of inlining packet. */ 82 #define MLX5_TXQ_MAX_INLINE_LEN "txq_max_inline_len" 83 84 /* Device parameter to enable hardware Tx vector. */ 85 #define MLX5_TX_VEC_EN "tx_vec_en" 86 87 /* Device parameter to enable hardware Rx vector. */ 88 #define MLX5_RX_VEC_EN "rx_vec_en" 89 90 /* Allow L3 VXLAN flow creation. */ 91 #define MLX5_L3_VXLAN_EN "l3_vxlan_en" 92 93 /* Activate DV flow steering. */ 94 #define MLX5_DV_FLOW_EN "dv_flow_en" 95 96 /* Activate Netlink support in VF mode. */ 97 #define MLX5_VF_NL_EN "vf_nl_en" 98 99 /* Select port representors to instantiate. */ 100 #define MLX5_REPRESENTOR "representor" 101 102 #ifndef HAVE_IBV_MLX5_MOD_MPW 103 #define MLX5DV_CONTEXT_FLAGS_MPW_ALLOWED (1 << 2) 104 #define MLX5DV_CONTEXT_FLAGS_ENHANCED_MPW (1 << 3) 105 #endif 106 107 #ifndef HAVE_IBV_MLX5_MOD_CQE_128B_COMP 108 #define MLX5DV_CONTEXT_FLAGS_CQE_128B_COMP (1 << 4) 109 #endif 110 111 static const char *MZ_MLX5_PMD_SHARED_DATA = "mlx5_pmd_shared_data"; 112 113 /* Shared memory between primary and secondary processes. */ 114 struct mlx5_shared_data *mlx5_shared_data; 115 116 /* Spinlock for mlx5_shared_data allocation. */ 117 static rte_spinlock_t mlx5_shared_data_lock = RTE_SPINLOCK_INITIALIZER; 118 119 /** Driver-specific log messages type. */ 120 int mlx5_logtype; 121 122 /** 123 * Prepare shared data between primary and secondary process. 124 */ 125 static void 126 mlx5_prepare_shared_data(void) 127 { 128 const struct rte_memzone *mz; 129 130 rte_spinlock_lock(&mlx5_shared_data_lock); 131 if (mlx5_shared_data == NULL) { 132 if (rte_eal_process_type() == RTE_PROC_PRIMARY) { 133 /* Allocate shared memory. */ 134 mz = rte_memzone_reserve(MZ_MLX5_PMD_SHARED_DATA, 135 sizeof(*mlx5_shared_data), 136 SOCKET_ID_ANY, 0); 137 } else { 138 /* Lookup allocated shared memory. */ 139 mz = rte_memzone_lookup(MZ_MLX5_PMD_SHARED_DATA); 140 } 141 if (mz == NULL) 142 rte_panic("Cannot allocate mlx5 shared data\n"); 143 mlx5_shared_data = mz->addr; 144 /* Initialize shared data. */ 145 if (rte_eal_process_type() == RTE_PROC_PRIMARY) { 146 LIST_INIT(&mlx5_shared_data->mem_event_cb_list); 147 rte_rwlock_init(&mlx5_shared_data->mem_event_rwlock); 148 } 149 rte_mem_event_callback_register("MLX5_MEM_EVENT_CB", 150 mlx5_mr_mem_event_cb, NULL); 151 } 152 rte_spinlock_unlock(&mlx5_shared_data_lock); 153 } 154 155 /** 156 * Retrieve integer value from environment variable. 157 * 158 * @param[in] name 159 * Environment variable name. 160 * 161 * @return 162 * Integer value, 0 if the variable is not set. 163 */ 164 int 165 mlx5_getenv_int(const char *name) 166 { 167 const char *val = getenv(name); 168 169 if (val == NULL) 170 return 0; 171 return atoi(val); 172 } 173 174 /** 175 * Verbs callback to allocate a memory. This function should allocate the space 176 * according to the size provided residing inside a huge page. 177 * Please note that all allocation must respect the alignment from libmlx5 178 * (i.e. currently sysconf(_SC_PAGESIZE)). 179 * 180 * @param[in] size 181 * The size in bytes of the memory to allocate. 182 * @param[in] data 183 * A pointer to the callback data. 184 * 185 * @return 186 * Allocated buffer, NULL otherwise and rte_errno is set. 187 */ 188 static void * 189 mlx5_alloc_verbs_buf(size_t size, void *data) 190 { 191 struct priv *priv = data; 192 void *ret; 193 size_t alignment = sysconf(_SC_PAGESIZE); 194 unsigned int socket = SOCKET_ID_ANY; 195 196 if (priv->verbs_alloc_ctx.type == MLX5_VERBS_ALLOC_TYPE_TX_QUEUE) { 197 const struct mlx5_txq_ctrl *ctrl = priv->verbs_alloc_ctx.obj; 198 199 socket = ctrl->socket; 200 } else if (priv->verbs_alloc_ctx.type == 201 MLX5_VERBS_ALLOC_TYPE_RX_QUEUE) { 202 const struct mlx5_rxq_ctrl *ctrl = priv->verbs_alloc_ctx.obj; 203 204 socket = ctrl->socket; 205 } 206 assert(data != NULL); 207 ret = rte_malloc_socket(__func__, size, alignment, socket); 208 if (!ret && size) 209 rte_errno = ENOMEM; 210 return ret; 211 } 212 213 /** 214 * Verbs callback to free a memory. 215 * 216 * @param[in] ptr 217 * A pointer to the memory to free. 218 * @param[in] data 219 * A pointer to the callback data. 220 */ 221 static void 222 mlx5_free_verbs_buf(void *ptr, void *data __rte_unused) 223 { 224 assert(data != NULL); 225 rte_free(ptr); 226 } 227 228 /** 229 * DPDK callback to close the device. 230 * 231 * Destroy all queues and objects, free memory. 232 * 233 * @param dev 234 * Pointer to Ethernet device structure. 235 */ 236 static void 237 mlx5_dev_close(struct rte_eth_dev *dev) 238 { 239 struct priv *priv = dev->data->dev_private; 240 unsigned int i; 241 int ret; 242 243 DRV_LOG(DEBUG, "port %u closing device \"%s\"", 244 dev->data->port_id, 245 ((priv->ctx != NULL) ? priv->ctx->device->name : "")); 246 /* In case mlx5_dev_stop() has not been called. */ 247 mlx5_dev_interrupt_handler_uninstall(dev); 248 mlx5_traffic_disable(dev); 249 mlx5_flow_flush(dev, NULL); 250 /* Prevent crashes when queues are still in use. */ 251 dev->rx_pkt_burst = removed_rx_burst; 252 dev->tx_pkt_burst = removed_tx_burst; 253 if (priv->rxqs != NULL) { 254 /* XXX race condition if mlx5_rx_burst() is still running. */ 255 usleep(1000); 256 for (i = 0; (i != priv->rxqs_n); ++i) 257 mlx5_rxq_release(dev, i); 258 priv->rxqs_n = 0; 259 priv->rxqs = NULL; 260 } 261 if (priv->txqs != NULL) { 262 /* XXX race condition if mlx5_tx_burst() is still running. */ 263 usleep(1000); 264 for (i = 0; (i != priv->txqs_n); ++i) 265 mlx5_txq_release(dev, i); 266 priv->txqs_n = 0; 267 priv->txqs = NULL; 268 } 269 mlx5_mprq_free_mp(dev); 270 mlx5_mr_release(dev); 271 if (priv->pd != NULL) { 272 assert(priv->ctx != NULL); 273 claim_zero(mlx5_glue->dealloc_pd(priv->pd)); 274 claim_zero(mlx5_glue->close_device(priv->ctx)); 275 } else 276 assert(priv->ctx == NULL); 277 if (priv->rss_conf.rss_key != NULL) 278 rte_free(priv->rss_conf.rss_key); 279 if (priv->reta_idx != NULL) 280 rte_free(priv->reta_idx); 281 if (priv->primary_socket) 282 mlx5_socket_uninit(dev); 283 if (priv->config.vf) 284 mlx5_nl_mac_addr_flush(dev); 285 if (priv->nl_socket_route >= 0) 286 close(priv->nl_socket_route); 287 if (priv->nl_socket_rdma >= 0) 288 close(priv->nl_socket_rdma); 289 if (priv->mnl_socket) 290 mlx5_flow_tcf_socket_destroy(priv->mnl_socket); 291 ret = mlx5_hrxq_ibv_verify(dev); 292 if (ret) 293 DRV_LOG(WARNING, "port %u some hash Rx queue still remain", 294 dev->data->port_id); 295 ret = mlx5_ind_table_ibv_verify(dev); 296 if (ret) 297 DRV_LOG(WARNING, "port %u some indirection table still remain", 298 dev->data->port_id); 299 ret = mlx5_rxq_ibv_verify(dev); 300 if (ret) 301 DRV_LOG(WARNING, "port %u some Verbs Rx queue still remain", 302 dev->data->port_id); 303 ret = mlx5_rxq_verify(dev); 304 if (ret) 305 DRV_LOG(WARNING, "port %u some Rx queues still remain", 306 dev->data->port_id); 307 ret = mlx5_txq_ibv_verify(dev); 308 if (ret) 309 DRV_LOG(WARNING, "port %u some Verbs Tx queue still remain", 310 dev->data->port_id); 311 ret = mlx5_txq_verify(dev); 312 if (ret) 313 DRV_LOG(WARNING, "port %u some Tx queues still remain", 314 dev->data->port_id); 315 ret = mlx5_flow_verify(dev); 316 if (ret) 317 DRV_LOG(WARNING, "port %u some flows still remain", 318 dev->data->port_id); 319 if (priv->domain_id != RTE_ETH_DEV_SWITCH_DOMAIN_ID_INVALID) { 320 unsigned int c = 0; 321 unsigned int i = mlx5_dev_to_port_id(dev->device, NULL, 0); 322 uint16_t port_id[i]; 323 324 i = RTE_MIN(mlx5_dev_to_port_id(dev->device, port_id, i), i); 325 while (i--) { 326 struct priv *opriv = 327 rte_eth_devices[port_id[i]].data->dev_private; 328 329 if (!opriv || 330 opriv->domain_id != priv->domain_id || 331 &rte_eth_devices[port_id[i]] == dev) 332 continue; 333 ++c; 334 } 335 if (!c) 336 claim_zero(rte_eth_switch_domain_free(priv->domain_id)); 337 } 338 memset(priv, 0, sizeof(*priv)); 339 priv->domain_id = RTE_ETH_DEV_SWITCH_DOMAIN_ID_INVALID; 340 } 341 342 const struct eth_dev_ops mlx5_dev_ops = { 343 .dev_configure = mlx5_dev_configure, 344 .dev_start = mlx5_dev_start, 345 .dev_stop = mlx5_dev_stop, 346 .dev_set_link_down = mlx5_set_link_down, 347 .dev_set_link_up = mlx5_set_link_up, 348 .dev_close = mlx5_dev_close, 349 .promiscuous_enable = mlx5_promiscuous_enable, 350 .promiscuous_disable = mlx5_promiscuous_disable, 351 .allmulticast_enable = mlx5_allmulticast_enable, 352 .allmulticast_disable = mlx5_allmulticast_disable, 353 .link_update = mlx5_link_update, 354 .stats_get = mlx5_stats_get, 355 .stats_reset = mlx5_stats_reset, 356 .xstats_get = mlx5_xstats_get, 357 .xstats_reset = mlx5_xstats_reset, 358 .xstats_get_names = mlx5_xstats_get_names, 359 .dev_infos_get = mlx5_dev_infos_get, 360 .dev_supported_ptypes_get = mlx5_dev_supported_ptypes_get, 361 .vlan_filter_set = mlx5_vlan_filter_set, 362 .rx_queue_setup = mlx5_rx_queue_setup, 363 .tx_queue_setup = mlx5_tx_queue_setup, 364 .rx_queue_release = mlx5_rx_queue_release, 365 .tx_queue_release = mlx5_tx_queue_release, 366 .flow_ctrl_get = mlx5_dev_get_flow_ctrl, 367 .flow_ctrl_set = mlx5_dev_set_flow_ctrl, 368 .mac_addr_remove = mlx5_mac_addr_remove, 369 .mac_addr_add = mlx5_mac_addr_add, 370 .mac_addr_set = mlx5_mac_addr_set, 371 .set_mc_addr_list = mlx5_set_mc_addr_list, 372 .mtu_set = mlx5_dev_set_mtu, 373 .vlan_strip_queue_set = mlx5_vlan_strip_queue_set, 374 .vlan_offload_set = mlx5_vlan_offload_set, 375 .reta_update = mlx5_dev_rss_reta_update, 376 .reta_query = mlx5_dev_rss_reta_query, 377 .rss_hash_update = mlx5_rss_hash_update, 378 .rss_hash_conf_get = mlx5_rss_hash_conf_get, 379 .filter_ctrl = mlx5_dev_filter_ctrl, 380 .rx_descriptor_status = mlx5_rx_descriptor_status, 381 .tx_descriptor_status = mlx5_tx_descriptor_status, 382 .rx_queue_intr_enable = mlx5_rx_intr_enable, 383 .rx_queue_intr_disable = mlx5_rx_intr_disable, 384 .is_removed = mlx5_is_removed, 385 }; 386 387 static const struct eth_dev_ops mlx5_dev_sec_ops = { 388 .stats_get = mlx5_stats_get, 389 .stats_reset = mlx5_stats_reset, 390 .xstats_get = mlx5_xstats_get, 391 .xstats_reset = mlx5_xstats_reset, 392 .xstats_get_names = mlx5_xstats_get_names, 393 .dev_infos_get = mlx5_dev_infos_get, 394 .rx_descriptor_status = mlx5_rx_descriptor_status, 395 .tx_descriptor_status = mlx5_tx_descriptor_status, 396 }; 397 398 /* Available operators in flow isolated mode. */ 399 const struct eth_dev_ops mlx5_dev_ops_isolate = { 400 .dev_configure = mlx5_dev_configure, 401 .dev_start = mlx5_dev_start, 402 .dev_stop = mlx5_dev_stop, 403 .dev_set_link_down = mlx5_set_link_down, 404 .dev_set_link_up = mlx5_set_link_up, 405 .dev_close = mlx5_dev_close, 406 .promiscuous_enable = mlx5_promiscuous_enable, 407 .promiscuous_disable = mlx5_promiscuous_disable, 408 .allmulticast_enable = mlx5_allmulticast_enable, 409 .allmulticast_disable = mlx5_allmulticast_disable, 410 .link_update = mlx5_link_update, 411 .stats_get = mlx5_stats_get, 412 .stats_reset = mlx5_stats_reset, 413 .xstats_get = mlx5_xstats_get, 414 .xstats_reset = mlx5_xstats_reset, 415 .xstats_get_names = mlx5_xstats_get_names, 416 .dev_infos_get = mlx5_dev_infos_get, 417 .dev_supported_ptypes_get = mlx5_dev_supported_ptypes_get, 418 .vlan_filter_set = mlx5_vlan_filter_set, 419 .rx_queue_setup = mlx5_rx_queue_setup, 420 .tx_queue_setup = mlx5_tx_queue_setup, 421 .rx_queue_release = mlx5_rx_queue_release, 422 .tx_queue_release = mlx5_tx_queue_release, 423 .flow_ctrl_get = mlx5_dev_get_flow_ctrl, 424 .flow_ctrl_set = mlx5_dev_set_flow_ctrl, 425 .mac_addr_remove = mlx5_mac_addr_remove, 426 .mac_addr_add = mlx5_mac_addr_add, 427 .mac_addr_set = mlx5_mac_addr_set, 428 .set_mc_addr_list = mlx5_set_mc_addr_list, 429 .mtu_set = mlx5_dev_set_mtu, 430 .vlan_strip_queue_set = mlx5_vlan_strip_queue_set, 431 .vlan_offload_set = mlx5_vlan_offload_set, 432 .filter_ctrl = mlx5_dev_filter_ctrl, 433 .rx_descriptor_status = mlx5_rx_descriptor_status, 434 .tx_descriptor_status = mlx5_tx_descriptor_status, 435 .rx_queue_intr_enable = mlx5_rx_intr_enable, 436 .rx_queue_intr_disable = mlx5_rx_intr_disable, 437 .is_removed = mlx5_is_removed, 438 }; 439 440 /** 441 * Verify and store value for device argument. 442 * 443 * @param[in] key 444 * Key argument to verify. 445 * @param[in] val 446 * Value associated with key. 447 * @param opaque 448 * User data. 449 * 450 * @return 451 * 0 on success, a negative errno value otherwise and rte_errno is set. 452 */ 453 static int 454 mlx5_args_check(const char *key, const char *val, void *opaque) 455 { 456 struct mlx5_dev_config *config = opaque; 457 unsigned long tmp; 458 459 /* No-op, port representors are processed in mlx5_dev_spawn(). */ 460 if (!strcmp(MLX5_REPRESENTOR, key)) 461 return 0; 462 errno = 0; 463 tmp = strtoul(val, NULL, 0); 464 if (errno) { 465 rte_errno = errno; 466 DRV_LOG(WARNING, "%s: \"%s\" is not a valid integer", key, val); 467 return -rte_errno; 468 } 469 if (strcmp(MLX5_RXQ_CQE_COMP_EN, key) == 0) { 470 config->cqe_comp = !!tmp; 471 } else if (strcmp(MLX5_RX_MPRQ_EN, key) == 0) { 472 config->mprq.enabled = !!tmp; 473 } else if (strcmp(MLX5_RX_MPRQ_LOG_STRIDE_NUM, key) == 0) { 474 config->mprq.stride_num_n = tmp; 475 } else if (strcmp(MLX5_RX_MPRQ_MAX_MEMCPY_LEN, key) == 0) { 476 config->mprq.max_memcpy_len = tmp; 477 } else if (strcmp(MLX5_RXQS_MIN_MPRQ, key) == 0) { 478 config->mprq.min_rxqs_num = tmp; 479 } else if (strcmp(MLX5_TXQ_INLINE, key) == 0) { 480 config->txq_inline = tmp; 481 } else if (strcmp(MLX5_TXQS_MIN_INLINE, key) == 0) { 482 config->txqs_inline = tmp; 483 } else if (strcmp(MLX5_TXQ_MPW_EN, key) == 0) { 484 config->mps = !!tmp; 485 } else if (strcmp(MLX5_TXQ_MPW_HDR_DSEG_EN, key) == 0) { 486 config->mpw_hdr_dseg = !!tmp; 487 } else if (strcmp(MLX5_TXQ_MAX_INLINE_LEN, key) == 0) { 488 config->inline_max_packet_sz = tmp; 489 } else if (strcmp(MLX5_TX_VEC_EN, key) == 0) { 490 config->tx_vec_en = !!tmp; 491 } else if (strcmp(MLX5_RX_VEC_EN, key) == 0) { 492 config->rx_vec_en = !!tmp; 493 } else if (strcmp(MLX5_L3_VXLAN_EN, key) == 0) { 494 config->l3_vxlan_en = !!tmp; 495 } else if (strcmp(MLX5_VF_NL_EN, key) == 0) { 496 config->vf_nl_en = !!tmp; 497 } else if (strcmp(MLX5_DV_FLOW_EN, key) == 0) { 498 config->dv_flow_en = !!tmp; 499 } else { 500 DRV_LOG(WARNING, "%s: unknown parameter", key); 501 rte_errno = EINVAL; 502 return -rte_errno; 503 } 504 return 0; 505 } 506 507 /** 508 * Parse device parameters. 509 * 510 * @param config 511 * Pointer to device configuration structure. 512 * @param devargs 513 * Device arguments structure. 514 * 515 * @return 516 * 0 on success, a negative errno value otherwise and rte_errno is set. 517 */ 518 static int 519 mlx5_args(struct mlx5_dev_config *config, struct rte_devargs *devargs) 520 { 521 const char **params = (const char *[]){ 522 MLX5_RXQ_CQE_COMP_EN, 523 MLX5_RX_MPRQ_EN, 524 MLX5_RX_MPRQ_LOG_STRIDE_NUM, 525 MLX5_RX_MPRQ_MAX_MEMCPY_LEN, 526 MLX5_RXQS_MIN_MPRQ, 527 MLX5_TXQ_INLINE, 528 MLX5_TXQS_MIN_INLINE, 529 MLX5_TXQ_MPW_EN, 530 MLX5_TXQ_MPW_HDR_DSEG_EN, 531 MLX5_TXQ_MAX_INLINE_LEN, 532 MLX5_TX_VEC_EN, 533 MLX5_RX_VEC_EN, 534 MLX5_L3_VXLAN_EN, 535 MLX5_VF_NL_EN, 536 MLX5_DV_FLOW_EN, 537 MLX5_REPRESENTOR, 538 NULL, 539 }; 540 struct rte_kvargs *kvlist; 541 int ret = 0; 542 int i; 543 544 if (devargs == NULL) 545 return 0; 546 /* Following UGLY cast is done to pass checkpatch. */ 547 kvlist = rte_kvargs_parse(devargs->args, params); 548 if (kvlist == NULL) 549 return 0; 550 /* Process parameters. */ 551 for (i = 0; (params[i] != NULL); ++i) { 552 if (rte_kvargs_count(kvlist, params[i])) { 553 ret = rte_kvargs_process(kvlist, params[i], 554 mlx5_args_check, config); 555 if (ret) { 556 rte_errno = EINVAL; 557 rte_kvargs_free(kvlist); 558 return -rte_errno; 559 } 560 } 561 } 562 rte_kvargs_free(kvlist); 563 return 0; 564 } 565 566 static struct rte_pci_driver mlx5_driver; 567 568 /* 569 * Reserved UAR address space for TXQ UAR(hw doorbell) mapping, process 570 * local resource used by both primary and secondary to avoid duplicate 571 * reservation. 572 * The space has to be available on both primary and secondary process, 573 * TXQ UAR maps to this area using fixed mmap w/o double check. 574 */ 575 static void *uar_base; 576 577 static int 578 find_lower_va_bound(const struct rte_memseg_list *msl, 579 const struct rte_memseg *ms, void *arg) 580 { 581 void **addr = arg; 582 583 if (msl->external) 584 return 0; 585 if (*addr == NULL) 586 *addr = ms->addr; 587 else 588 *addr = RTE_MIN(*addr, ms->addr); 589 590 return 0; 591 } 592 593 /** 594 * Reserve UAR address space for primary process. 595 * 596 * @param[in] dev 597 * Pointer to Ethernet device. 598 * 599 * @return 600 * 0 on success, a negative errno value otherwise and rte_errno is set. 601 */ 602 static int 603 mlx5_uar_init_primary(struct rte_eth_dev *dev) 604 { 605 struct priv *priv = dev->data->dev_private; 606 void *addr = (void *)0; 607 608 if (uar_base) { /* UAR address space mapped. */ 609 priv->uar_base = uar_base; 610 return 0; 611 } 612 /* find out lower bound of hugepage segments */ 613 rte_memseg_walk(find_lower_va_bound, &addr); 614 615 /* keep distance to hugepages to minimize potential conflicts. */ 616 addr = RTE_PTR_SUB(addr, (uintptr_t)(MLX5_UAR_OFFSET + MLX5_UAR_SIZE)); 617 /* anonymous mmap, no real memory consumption. */ 618 addr = mmap(addr, MLX5_UAR_SIZE, 619 PROT_NONE, MAP_PRIVATE | MAP_ANONYMOUS, -1, 0); 620 if (addr == MAP_FAILED) { 621 DRV_LOG(ERR, 622 "port %u failed to reserve UAR address space, please" 623 " adjust MLX5_UAR_SIZE or try --base-virtaddr", 624 dev->data->port_id); 625 rte_errno = ENOMEM; 626 return -rte_errno; 627 } 628 /* Accept either same addr or a new addr returned from mmap if target 629 * range occupied. 630 */ 631 DRV_LOG(INFO, "port %u reserved UAR address space: %p", 632 dev->data->port_id, addr); 633 priv->uar_base = addr; /* for primary and secondary UAR re-mmap. */ 634 uar_base = addr; /* process local, don't reserve again. */ 635 return 0; 636 } 637 638 /** 639 * Reserve UAR address space for secondary process, align with 640 * primary process. 641 * 642 * @param[in] dev 643 * Pointer to Ethernet device. 644 * 645 * @return 646 * 0 on success, a negative errno value otherwise and rte_errno is set. 647 */ 648 static int 649 mlx5_uar_init_secondary(struct rte_eth_dev *dev) 650 { 651 struct priv *priv = dev->data->dev_private; 652 void *addr; 653 654 assert(priv->uar_base); 655 if (uar_base) { /* already reserved. */ 656 assert(uar_base == priv->uar_base); 657 return 0; 658 } 659 /* anonymous mmap, no real memory consumption. */ 660 addr = mmap(priv->uar_base, MLX5_UAR_SIZE, 661 PROT_NONE, MAP_PRIVATE | MAP_ANONYMOUS, -1, 0); 662 if (addr == MAP_FAILED) { 663 DRV_LOG(ERR, "port %u UAR mmap failed: %p size: %llu", 664 dev->data->port_id, priv->uar_base, MLX5_UAR_SIZE); 665 rte_errno = ENXIO; 666 return -rte_errno; 667 } 668 if (priv->uar_base != addr) { 669 DRV_LOG(ERR, 670 "port %u UAR address %p size %llu occupied, please" 671 " adjust MLX5_UAR_OFFSET or try EAL parameter" 672 " --base-virtaddr", 673 dev->data->port_id, priv->uar_base, MLX5_UAR_SIZE); 674 rte_errno = ENXIO; 675 return -rte_errno; 676 } 677 uar_base = addr; /* process local, don't reserve again */ 678 DRV_LOG(INFO, "port %u reserved UAR address space: %p", 679 dev->data->port_id, addr); 680 return 0; 681 } 682 683 /** 684 * Spawn an Ethernet device from Verbs information. 685 * 686 * @param dpdk_dev 687 * Backing DPDK device. 688 * @param ibv_dev 689 * Verbs device. 690 * @param vf 691 * If nonzero, enable VF-specific features. 692 * @param[in] switch_info 693 * Switch properties of Ethernet device. 694 * 695 * @return 696 * A valid Ethernet device object on success, NULL otherwise and rte_errno 697 * is set. The following error is defined: 698 * 699 * EBUSY: device is not supposed to be spawned. 700 */ 701 static struct rte_eth_dev * 702 mlx5_dev_spawn(struct rte_device *dpdk_dev, 703 struct ibv_device *ibv_dev, 704 int vf, 705 const struct mlx5_switch_info *switch_info) 706 { 707 struct ibv_context *ctx; 708 struct ibv_device_attr_ex attr; 709 struct ibv_port_attr port_attr; 710 struct ibv_pd *pd = NULL; 711 struct mlx5dv_context dv_attr = { .comp_mask = 0 }; 712 struct mlx5_dev_config config = { 713 .vf = !!vf, 714 .mps = MLX5_ARG_UNSET, 715 .tx_vec_en = 1, 716 .rx_vec_en = 1, 717 .mpw_hdr_dseg = 0, 718 .txq_inline = MLX5_ARG_UNSET, 719 .txqs_inline = MLX5_ARG_UNSET, 720 .inline_max_packet_sz = MLX5_ARG_UNSET, 721 .vf_nl_en = 1, 722 .mprq = { 723 .enabled = 0, 724 .stride_num_n = MLX5_MPRQ_STRIDE_NUM_N, 725 .max_memcpy_len = MLX5_MPRQ_MEMCPY_DEFAULT_LEN, 726 .min_rxqs_num = MLX5_MPRQ_MIN_RXQS, 727 }, 728 }; 729 struct rte_eth_dev *eth_dev = NULL; 730 struct priv *priv = NULL; 731 int err = 0; 732 unsigned int mps; 733 unsigned int cqe_comp; 734 unsigned int tunnel_en = 0; 735 unsigned int mpls_en = 0; 736 unsigned int swp = 0; 737 unsigned int mprq = 0; 738 unsigned int mprq_min_stride_size_n = 0; 739 unsigned int mprq_max_stride_size_n = 0; 740 unsigned int mprq_min_stride_num_n = 0; 741 unsigned int mprq_max_stride_num_n = 0; 742 #ifdef HAVE_IBV_DEVICE_COUNTERS_SET_SUPPORT 743 struct ibv_counter_set_description cs_desc = { .counter_type = 0 }; 744 #endif 745 struct ether_addr mac; 746 char name[RTE_ETH_NAME_MAX_LEN]; 747 int own_domain_id = 0; 748 unsigned int i; 749 750 /* Determine if this port representor is supposed to be spawned. */ 751 if (switch_info->representor && dpdk_dev->devargs) { 752 struct rte_eth_devargs eth_da; 753 754 err = rte_eth_devargs_parse(dpdk_dev->devargs->args, ð_da); 755 if (err) { 756 rte_errno = -err; 757 DRV_LOG(ERR, "failed to process device arguments: %s", 758 strerror(rte_errno)); 759 return NULL; 760 } 761 for (i = 0; i < eth_da.nb_representor_ports; ++i) 762 if (eth_da.representor_ports[i] == 763 (uint16_t)switch_info->port_name) 764 break; 765 if (i == eth_da.nb_representor_ports) { 766 rte_errno = EBUSY; 767 return NULL; 768 } 769 } 770 /* Prepare shared data between primary and secondary process. */ 771 mlx5_prepare_shared_data(); 772 errno = 0; 773 ctx = mlx5_glue->open_device(ibv_dev); 774 if (!ctx) { 775 rte_errno = errno ? errno : ENODEV; 776 return NULL; 777 } 778 #ifdef HAVE_IBV_MLX5_MOD_SWP 779 dv_attr.comp_mask |= MLX5DV_CONTEXT_MASK_SWP; 780 #endif 781 /* 782 * Multi-packet send is supported by ConnectX-4 Lx PF as well 783 * as all ConnectX-5 devices. 784 */ 785 #ifdef HAVE_IBV_DEVICE_TUNNEL_SUPPORT 786 dv_attr.comp_mask |= MLX5DV_CONTEXT_MASK_TUNNEL_OFFLOADS; 787 #endif 788 #ifdef HAVE_IBV_DEVICE_STRIDING_RQ_SUPPORT 789 dv_attr.comp_mask |= MLX5DV_CONTEXT_MASK_STRIDING_RQ; 790 #endif 791 mlx5_glue->dv_query_device(ctx, &dv_attr); 792 if (dv_attr.flags & MLX5DV_CONTEXT_FLAGS_MPW_ALLOWED) { 793 if (dv_attr.flags & MLX5DV_CONTEXT_FLAGS_ENHANCED_MPW) { 794 DRV_LOG(DEBUG, "enhanced MPW is supported"); 795 mps = MLX5_MPW_ENHANCED; 796 } else { 797 DRV_LOG(DEBUG, "MPW is supported"); 798 mps = MLX5_MPW; 799 } 800 } else { 801 DRV_LOG(DEBUG, "MPW isn't supported"); 802 mps = MLX5_MPW_DISABLED; 803 } 804 #ifdef HAVE_IBV_MLX5_MOD_SWP 805 if (dv_attr.comp_mask & MLX5DV_CONTEXT_MASK_SWP) 806 swp = dv_attr.sw_parsing_caps.sw_parsing_offloads; 807 DRV_LOG(DEBUG, "SWP support: %u", swp); 808 #endif 809 config.swp = !!swp; 810 #ifdef HAVE_IBV_DEVICE_STRIDING_RQ_SUPPORT 811 if (dv_attr.comp_mask & MLX5DV_CONTEXT_MASK_STRIDING_RQ) { 812 struct mlx5dv_striding_rq_caps mprq_caps = 813 dv_attr.striding_rq_caps; 814 815 DRV_LOG(DEBUG, "\tmin_single_stride_log_num_of_bytes: %d", 816 mprq_caps.min_single_stride_log_num_of_bytes); 817 DRV_LOG(DEBUG, "\tmax_single_stride_log_num_of_bytes: %d", 818 mprq_caps.max_single_stride_log_num_of_bytes); 819 DRV_LOG(DEBUG, "\tmin_single_wqe_log_num_of_strides: %d", 820 mprq_caps.min_single_wqe_log_num_of_strides); 821 DRV_LOG(DEBUG, "\tmax_single_wqe_log_num_of_strides: %d", 822 mprq_caps.max_single_wqe_log_num_of_strides); 823 DRV_LOG(DEBUG, "\tsupported_qpts: %d", 824 mprq_caps.supported_qpts); 825 DRV_LOG(DEBUG, "device supports Multi-Packet RQ"); 826 mprq = 1; 827 mprq_min_stride_size_n = 828 mprq_caps.min_single_stride_log_num_of_bytes; 829 mprq_max_stride_size_n = 830 mprq_caps.max_single_stride_log_num_of_bytes; 831 mprq_min_stride_num_n = 832 mprq_caps.min_single_wqe_log_num_of_strides; 833 mprq_max_stride_num_n = 834 mprq_caps.max_single_wqe_log_num_of_strides; 835 config.mprq.stride_num_n = RTE_MAX(MLX5_MPRQ_STRIDE_NUM_N, 836 mprq_min_stride_num_n); 837 } 838 #endif 839 if (RTE_CACHE_LINE_SIZE == 128 && 840 !(dv_attr.flags & MLX5DV_CONTEXT_FLAGS_CQE_128B_COMP)) 841 cqe_comp = 0; 842 else 843 cqe_comp = 1; 844 config.cqe_comp = cqe_comp; 845 #ifdef HAVE_IBV_DEVICE_TUNNEL_SUPPORT 846 if (dv_attr.comp_mask & MLX5DV_CONTEXT_MASK_TUNNEL_OFFLOADS) { 847 tunnel_en = ((dv_attr.tunnel_offloads_caps & 848 MLX5DV_RAW_PACKET_CAP_TUNNELED_OFFLOAD_VXLAN) && 849 (dv_attr.tunnel_offloads_caps & 850 MLX5DV_RAW_PACKET_CAP_TUNNELED_OFFLOAD_GRE)); 851 } 852 DRV_LOG(DEBUG, "tunnel offloading is %ssupported", 853 tunnel_en ? "" : "not "); 854 #else 855 DRV_LOG(WARNING, 856 "tunnel offloading disabled due to old OFED/rdma-core version"); 857 #endif 858 config.tunnel_en = tunnel_en; 859 #ifdef HAVE_IBV_DEVICE_MPLS_SUPPORT 860 mpls_en = ((dv_attr.tunnel_offloads_caps & 861 MLX5DV_RAW_PACKET_CAP_TUNNELED_OFFLOAD_CW_MPLS_OVER_GRE) && 862 (dv_attr.tunnel_offloads_caps & 863 MLX5DV_RAW_PACKET_CAP_TUNNELED_OFFLOAD_CW_MPLS_OVER_UDP)); 864 DRV_LOG(DEBUG, "MPLS over GRE/UDP tunnel offloading is %ssupported", 865 mpls_en ? "" : "not "); 866 #else 867 DRV_LOG(WARNING, "MPLS over GRE/UDP tunnel offloading disabled due to" 868 " old OFED/rdma-core version or firmware configuration"); 869 #endif 870 config.mpls_en = mpls_en; 871 err = mlx5_glue->query_device_ex(ctx, NULL, &attr); 872 if (err) { 873 DEBUG("ibv_query_device_ex() failed"); 874 goto error; 875 } 876 if (!switch_info->representor) 877 rte_strlcpy(name, dpdk_dev->name, sizeof(name)); 878 else 879 snprintf(name, sizeof(name), "%s_representor_%u", 880 dpdk_dev->name, switch_info->port_name); 881 DRV_LOG(DEBUG, "naming Ethernet device \"%s\"", name); 882 if (rte_eal_process_type() == RTE_PROC_SECONDARY) { 883 eth_dev = rte_eth_dev_attach_secondary(name); 884 if (eth_dev == NULL) { 885 DRV_LOG(ERR, "can not attach rte ethdev"); 886 rte_errno = ENOMEM; 887 err = rte_errno; 888 goto error; 889 } 890 eth_dev->device = dpdk_dev; 891 eth_dev->dev_ops = &mlx5_dev_sec_ops; 892 err = mlx5_uar_init_secondary(eth_dev); 893 if (err) { 894 err = rte_errno; 895 goto error; 896 } 897 /* Receive command fd from primary process */ 898 err = mlx5_socket_connect(eth_dev); 899 if (err < 0) { 900 err = rte_errno; 901 goto error; 902 } 903 /* Remap UAR for Tx queues. */ 904 err = mlx5_tx_uar_remap(eth_dev, err); 905 if (err) { 906 err = rte_errno; 907 goto error; 908 } 909 /* 910 * Ethdev pointer is still required as input since 911 * the primary device is not accessible from the 912 * secondary process. 913 */ 914 eth_dev->rx_pkt_burst = mlx5_select_rx_function(eth_dev); 915 eth_dev->tx_pkt_burst = mlx5_select_tx_function(eth_dev); 916 claim_zero(mlx5_glue->close_device(ctx)); 917 return eth_dev; 918 } 919 /* Check port status. */ 920 err = mlx5_glue->query_port(ctx, 1, &port_attr); 921 if (err) { 922 DRV_LOG(ERR, "port query failed: %s", strerror(err)); 923 goto error; 924 } 925 if (port_attr.link_layer != IBV_LINK_LAYER_ETHERNET) { 926 DRV_LOG(ERR, "port is not configured in Ethernet mode"); 927 err = EINVAL; 928 goto error; 929 } 930 if (port_attr.state != IBV_PORT_ACTIVE) 931 DRV_LOG(DEBUG, "port is not active: \"%s\" (%d)", 932 mlx5_glue->port_state_str(port_attr.state), 933 port_attr.state); 934 /* Allocate protection domain. */ 935 pd = mlx5_glue->alloc_pd(ctx); 936 if (pd == NULL) { 937 DRV_LOG(ERR, "PD allocation failure"); 938 err = ENOMEM; 939 goto error; 940 } 941 priv = rte_zmalloc("ethdev private structure", 942 sizeof(*priv), 943 RTE_CACHE_LINE_SIZE); 944 if (priv == NULL) { 945 DRV_LOG(ERR, "priv allocation failure"); 946 err = ENOMEM; 947 goto error; 948 } 949 priv->ctx = ctx; 950 strncpy(priv->ibdev_name, priv->ctx->device->name, 951 sizeof(priv->ibdev_name)); 952 strncpy(priv->ibdev_path, priv->ctx->device->ibdev_path, 953 sizeof(priv->ibdev_path)); 954 priv->device_attr = attr; 955 priv->pd = pd; 956 priv->mtu = ETHER_MTU; 957 #ifndef RTE_ARCH_64 958 /* Initialize UAR access locks for 32bit implementations. */ 959 rte_spinlock_init(&priv->uar_lock_cq); 960 for (i = 0; i < MLX5_UAR_PAGE_NUM_MAX; i++) 961 rte_spinlock_init(&priv->uar_lock[i]); 962 #endif 963 /* Some internal functions rely on Netlink sockets, open them now. */ 964 priv->nl_socket_rdma = mlx5_nl_init(NETLINK_RDMA); 965 priv->nl_socket_route = mlx5_nl_init(NETLINK_ROUTE); 966 priv->nl_sn = 0; 967 priv->representor = !!switch_info->representor; 968 priv->domain_id = RTE_ETH_DEV_SWITCH_DOMAIN_ID_INVALID; 969 priv->representor_id = 970 switch_info->representor ? switch_info->port_name : -1; 971 /* 972 * Look for sibling devices in order to reuse their switch domain 973 * if any, otherwise allocate one. 974 */ 975 i = mlx5_dev_to_port_id(dpdk_dev, NULL, 0); 976 if (i > 0) { 977 uint16_t port_id[i]; 978 979 i = RTE_MIN(mlx5_dev_to_port_id(dpdk_dev, port_id, i), i); 980 while (i--) { 981 const struct priv *opriv = 982 rte_eth_devices[port_id[i]].data->dev_private; 983 984 if (!opriv || 985 opriv->domain_id == 986 RTE_ETH_DEV_SWITCH_DOMAIN_ID_INVALID) 987 continue; 988 priv->domain_id = opriv->domain_id; 989 break; 990 } 991 } 992 if (priv->domain_id == RTE_ETH_DEV_SWITCH_DOMAIN_ID_INVALID) { 993 err = rte_eth_switch_domain_alloc(&priv->domain_id); 994 if (err) { 995 err = rte_errno; 996 DRV_LOG(ERR, "unable to allocate switch domain: %s", 997 strerror(rte_errno)); 998 goto error; 999 } 1000 own_domain_id = 1; 1001 } 1002 err = mlx5_args(&config, dpdk_dev->devargs); 1003 if (err) { 1004 err = rte_errno; 1005 DRV_LOG(ERR, "failed to process device arguments: %s", 1006 strerror(rte_errno)); 1007 goto error; 1008 } 1009 config.hw_csum = !!(attr.device_cap_flags_ex & IBV_DEVICE_RAW_IP_CSUM); 1010 DRV_LOG(DEBUG, "checksum offloading is %ssupported", 1011 (config.hw_csum ? "" : "not ")); 1012 #ifdef HAVE_IBV_DEVICE_COUNTERS_SET_SUPPORT 1013 config.flow_counter_en = !!attr.max_counter_sets; 1014 mlx5_glue->describe_counter_set(ctx, 0, &cs_desc); 1015 DRV_LOG(DEBUG, "counter type = %d, num of cs = %ld, attributes = %d", 1016 cs_desc.counter_type, cs_desc.num_of_cs, 1017 cs_desc.attributes); 1018 #endif 1019 config.ind_table_max_size = 1020 attr.rss_caps.max_rwq_indirection_table_size; 1021 /* 1022 * Remove this check once DPDK supports larger/variable 1023 * indirection tables. 1024 */ 1025 if (config.ind_table_max_size > (unsigned int)ETH_RSS_RETA_SIZE_512) 1026 config.ind_table_max_size = ETH_RSS_RETA_SIZE_512; 1027 DRV_LOG(DEBUG, "maximum Rx indirection table size is %u", 1028 config.ind_table_max_size); 1029 config.hw_vlan_strip = !!(attr.raw_packet_caps & 1030 IBV_RAW_PACKET_CAP_CVLAN_STRIPPING); 1031 DRV_LOG(DEBUG, "VLAN stripping is %ssupported", 1032 (config.hw_vlan_strip ? "" : "not ")); 1033 config.hw_fcs_strip = !!(attr.raw_packet_caps & 1034 IBV_RAW_PACKET_CAP_SCATTER_FCS); 1035 DRV_LOG(DEBUG, "FCS stripping configuration is %ssupported", 1036 (config.hw_fcs_strip ? "" : "not ")); 1037 #ifdef HAVE_IBV_WQ_FLAG_RX_END_PADDING 1038 config.hw_padding = !!attr.rx_pad_end_addr_align; 1039 #endif 1040 DRV_LOG(DEBUG, "hardware Rx end alignment padding is %ssupported", 1041 (config.hw_padding ? "" : "not ")); 1042 config.tso = (attr.tso_caps.max_tso > 0 && 1043 (attr.tso_caps.supported_qpts & 1044 (1 << IBV_QPT_RAW_PACKET))); 1045 if (config.tso) 1046 config.tso_max_payload_sz = attr.tso_caps.max_tso; 1047 /* 1048 * MPW is disabled by default, while the Enhanced MPW is enabled 1049 * by default. 1050 */ 1051 if (config.mps == MLX5_ARG_UNSET) 1052 config.mps = (mps == MLX5_MPW_ENHANCED) ? MLX5_MPW_ENHANCED : 1053 MLX5_MPW_DISABLED; 1054 else 1055 config.mps = config.mps ? mps : MLX5_MPW_DISABLED; 1056 DRV_LOG(INFO, "%sMPS is %s", 1057 config.mps == MLX5_MPW_ENHANCED ? "enhanced " : "", 1058 config.mps != MLX5_MPW_DISABLED ? "enabled" : "disabled"); 1059 if (config.cqe_comp && !cqe_comp) { 1060 DRV_LOG(WARNING, "Rx CQE compression isn't supported"); 1061 config.cqe_comp = 0; 1062 } 1063 if (config.mprq.enabled && mprq) { 1064 if (config.mprq.stride_num_n > mprq_max_stride_num_n || 1065 config.mprq.stride_num_n < mprq_min_stride_num_n) { 1066 config.mprq.stride_num_n = 1067 RTE_MAX(MLX5_MPRQ_STRIDE_NUM_N, 1068 mprq_min_stride_num_n); 1069 DRV_LOG(WARNING, 1070 "the number of strides" 1071 " for Multi-Packet RQ is out of range," 1072 " setting default value (%u)", 1073 1 << config.mprq.stride_num_n); 1074 } 1075 config.mprq.min_stride_size_n = mprq_min_stride_size_n; 1076 config.mprq.max_stride_size_n = mprq_max_stride_size_n; 1077 } else if (config.mprq.enabled && !mprq) { 1078 DRV_LOG(WARNING, "Multi-Packet RQ isn't supported"); 1079 config.mprq.enabled = 0; 1080 } 1081 eth_dev = rte_eth_dev_allocate(name); 1082 if (eth_dev == NULL) { 1083 DRV_LOG(ERR, "can not allocate rte ethdev"); 1084 err = ENOMEM; 1085 goto error; 1086 } 1087 if (priv->representor) 1088 eth_dev->data->dev_flags |= RTE_ETH_DEV_REPRESENTOR; 1089 eth_dev->data->dev_private = priv; 1090 priv->dev_data = eth_dev->data; 1091 eth_dev->data->mac_addrs = priv->mac; 1092 eth_dev->device = dpdk_dev; 1093 err = mlx5_uar_init_primary(eth_dev); 1094 if (err) { 1095 err = rte_errno; 1096 goto error; 1097 } 1098 /* Configure the first MAC address by default. */ 1099 if (mlx5_get_mac(eth_dev, &mac.addr_bytes)) { 1100 DRV_LOG(ERR, 1101 "port %u cannot get MAC address, is mlx5_en" 1102 " loaded? (errno: %s)", 1103 eth_dev->data->port_id, strerror(rte_errno)); 1104 err = ENODEV; 1105 goto error; 1106 } 1107 DRV_LOG(INFO, 1108 "port %u MAC address is %02x:%02x:%02x:%02x:%02x:%02x", 1109 eth_dev->data->port_id, 1110 mac.addr_bytes[0], mac.addr_bytes[1], 1111 mac.addr_bytes[2], mac.addr_bytes[3], 1112 mac.addr_bytes[4], mac.addr_bytes[5]); 1113 #ifndef NDEBUG 1114 { 1115 char ifname[IF_NAMESIZE]; 1116 1117 if (mlx5_get_ifname(eth_dev, &ifname) == 0) 1118 DRV_LOG(DEBUG, "port %u ifname is \"%s\"", 1119 eth_dev->data->port_id, ifname); 1120 else 1121 DRV_LOG(DEBUG, "port %u ifname is unknown", 1122 eth_dev->data->port_id); 1123 } 1124 #endif 1125 /* Get actual MTU if possible. */ 1126 err = mlx5_get_mtu(eth_dev, &priv->mtu); 1127 if (err) { 1128 err = rte_errno; 1129 goto error; 1130 } 1131 DRV_LOG(DEBUG, "port %u MTU is %u", eth_dev->data->port_id, 1132 priv->mtu); 1133 /* Initialize burst functions to prevent crashes before link-up. */ 1134 eth_dev->rx_pkt_burst = removed_rx_burst; 1135 eth_dev->tx_pkt_burst = removed_tx_burst; 1136 eth_dev->dev_ops = &mlx5_dev_ops; 1137 /* Register MAC address. */ 1138 claim_zero(mlx5_mac_addr_add(eth_dev, &mac, 0, 0)); 1139 if (vf && config.vf_nl_en) 1140 mlx5_nl_mac_addr_sync(eth_dev); 1141 priv->mnl_socket = mlx5_flow_tcf_socket_create(); 1142 if (!priv->mnl_socket) { 1143 err = -rte_errno; 1144 DRV_LOG(WARNING, 1145 "flow rules relying on switch offloads will not be" 1146 " supported: cannot open libmnl socket: %s", 1147 strerror(rte_errno)); 1148 } else { 1149 struct rte_flow_error error; 1150 unsigned int ifindex = mlx5_ifindex(eth_dev); 1151 1152 if (!ifindex) { 1153 err = -rte_errno; 1154 error.message = 1155 "cannot retrieve network interface index"; 1156 } else { 1157 err = mlx5_flow_tcf_init(priv->mnl_socket, ifindex, 1158 &error); 1159 } 1160 if (err) { 1161 DRV_LOG(WARNING, 1162 "flow rules relying on switch offloads will" 1163 " not be supported: %s: %s", 1164 error.message, strerror(rte_errno)); 1165 mlx5_flow_tcf_socket_destroy(priv->mnl_socket); 1166 priv->mnl_socket = NULL; 1167 } 1168 } 1169 TAILQ_INIT(&priv->flows); 1170 TAILQ_INIT(&priv->ctrl_flows); 1171 /* Hint libmlx5 to use PMD allocator for data plane resources */ 1172 struct mlx5dv_ctx_allocators alctr = { 1173 .alloc = &mlx5_alloc_verbs_buf, 1174 .free = &mlx5_free_verbs_buf, 1175 .data = priv, 1176 }; 1177 mlx5_glue->dv_set_context_attr(ctx, MLX5DV_CTX_ATTR_BUF_ALLOCATORS, 1178 (void *)((uintptr_t)&alctr)); 1179 /* Bring Ethernet device up. */ 1180 DRV_LOG(DEBUG, "port %u forcing Ethernet interface up", 1181 eth_dev->data->port_id); 1182 mlx5_set_link_up(eth_dev); 1183 /* 1184 * Even though the interrupt handler is not installed yet, 1185 * interrupts will still trigger on the asyn_fd from 1186 * Verbs context returned by ibv_open_device(). 1187 */ 1188 mlx5_link_update(eth_dev, 0); 1189 /* Store device configuration on private structure. */ 1190 priv->config = config; 1191 /* Supported Verbs flow priority number detection. */ 1192 err = mlx5_flow_discover_priorities(eth_dev); 1193 if (err < 0) 1194 goto error; 1195 priv->config.flow_prio = err; 1196 /* 1197 * Once the device is added to the list of memory event 1198 * callback, its global MR cache table cannot be expanded 1199 * on the fly because of deadlock. If it overflows, lookup 1200 * should be done by searching MR list linearly, which is slow. 1201 */ 1202 err = mlx5_mr_btree_init(&priv->mr.cache, 1203 MLX5_MR_BTREE_CACHE_N * 2, 1204 eth_dev->device->numa_node); 1205 if (err) { 1206 err = rte_errno; 1207 goto error; 1208 } 1209 /* Add device to memory callback list. */ 1210 rte_rwlock_write_lock(&mlx5_shared_data->mem_event_rwlock); 1211 LIST_INSERT_HEAD(&mlx5_shared_data->mem_event_cb_list, 1212 priv, mem_event_cb); 1213 rte_rwlock_write_unlock(&mlx5_shared_data->mem_event_rwlock); 1214 return eth_dev; 1215 error: 1216 if (priv) { 1217 if (priv->nl_socket_route >= 0) 1218 close(priv->nl_socket_route); 1219 if (priv->nl_socket_rdma >= 0) 1220 close(priv->nl_socket_rdma); 1221 if (priv->mnl_socket) 1222 mlx5_flow_tcf_socket_destroy(priv->mnl_socket); 1223 if (own_domain_id) 1224 claim_zero(rte_eth_switch_domain_free(priv->domain_id)); 1225 rte_free(priv); 1226 if (eth_dev != NULL) 1227 eth_dev->data->dev_private = NULL; 1228 } 1229 if (pd) 1230 claim_zero(mlx5_glue->dealloc_pd(pd)); 1231 if (eth_dev != NULL) { 1232 /* mac_addrs must not be freed alone because part of dev_private */ 1233 eth_dev->data->mac_addrs = NULL; 1234 rte_eth_dev_release_port(eth_dev); 1235 } 1236 if (ctx) 1237 claim_zero(mlx5_glue->close_device(ctx)); 1238 assert(err > 0); 1239 rte_errno = err; 1240 return NULL; 1241 } 1242 1243 /** Data associated with devices to spawn. */ 1244 struct mlx5_dev_spawn_data { 1245 unsigned int ifindex; /**< Network interface index. */ 1246 struct mlx5_switch_info info; /**< Switch information. */ 1247 struct ibv_device *ibv_dev; /**< Associated IB device. */ 1248 struct rte_eth_dev *eth_dev; /**< Associated Ethernet device. */ 1249 }; 1250 1251 /** 1252 * Comparison callback to sort device data. 1253 * 1254 * This is meant to be used with qsort(). 1255 * 1256 * @param a[in] 1257 * Pointer to pointer to first data object. 1258 * @param b[in] 1259 * Pointer to pointer to second data object. 1260 * 1261 * @return 1262 * 0 if both objects are equal, less than 0 if the first argument is less 1263 * than the second, greater than 0 otherwise. 1264 */ 1265 static int 1266 mlx5_dev_spawn_data_cmp(const void *a, const void *b) 1267 { 1268 const struct mlx5_switch_info *si_a = 1269 &((const struct mlx5_dev_spawn_data *)a)->info; 1270 const struct mlx5_switch_info *si_b = 1271 &((const struct mlx5_dev_spawn_data *)b)->info; 1272 int ret; 1273 1274 /* Master device first. */ 1275 ret = si_b->master - si_a->master; 1276 if (ret) 1277 return ret; 1278 /* Then representor devices. */ 1279 ret = si_b->representor - si_a->representor; 1280 if (ret) 1281 return ret; 1282 /* Unidentified devices come last in no specific order. */ 1283 if (!si_a->representor) 1284 return 0; 1285 /* Order representors by name. */ 1286 return si_a->port_name - si_b->port_name; 1287 } 1288 1289 /** 1290 * DPDK callback to register a PCI device. 1291 * 1292 * This function spawns Ethernet devices out of a given PCI device. 1293 * 1294 * @param[in] pci_drv 1295 * PCI driver structure (mlx5_driver). 1296 * @param[in] pci_dev 1297 * PCI device information. 1298 * 1299 * @return 1300 * 0 on success, a negative errno value otherwise and rte_errno is set. 1301 */ 1302 static int 1303 mlx5_pci_probe(struct rte_pci_driver *pci_drv __rte_unused, 1304 struct rte_pci_device *pci_dev) 1305 { 1306 struct ibv_device **ibv_list; 1307 unsigned int n = 0; 1308 int vf; 1309 int ret; 1310 1311 assert(pci_drv == &mlx5_driver); 1312 errno = 0; 1313 ibv_list = mlx5_glue->get_device_list(&ret); 1314 if (!ibv_list) { 1315 rte_errno = errno ? errno : ENOSYS; 1316 DRV_LOG(ERR, "cannot list devices, is ib_uverbs loaded?"); 1317 return -rte_errno; 1318 } 1319 1320 struct ibv_device *ibv_match[ret + 1]; 1321 1322 while (ret-- > 0) { 1323 struct rte_pci_addr pci_addr; 1324 1325 DRV_LOG(DEBUG, "checking device \"%s\"", ibv_list[ret]->name); 1326 if (mlx5_ibv_device_to_pci_addr(ibv_list[ret], &pci_addr)) 1327 continue; 1328 if (pci_dev->addr.domain != pci_addr.domain || 1329 pci_dev->addr.bus != pci_addr.bus || 1330 pci_dev->addr.devid != pci_addr.devid || 1331 pci_dev->addr.function != pci_addr.function) 1332 continue; 1333 DRV_LOG(INFO, "PCI information matches for device \"%s\"", 1334 ibv_list[ret]->name); 1335 ibv_match[n++] = ibv_list[ret]; 1336 } 1337 ibv_match[n] = NULL; 1338 1339 struct mlx5_dev_spawn_data list[n]; 1340 int nl_route = n ? mlx5_nl_init(NETLINK_ROUTE) : -1; 1341 int nl_rdma = n ? mlx5_nl_init(NETLINK_RDMA) : -1; 1342 unsigned int i; 1343 unsigned int u; 1344 1345 /* 1346 * The existence of several matching entries (n > 1) means port 1347 * representors have been instantiated. No existing Verbs call nor 1348 * /sys entries can tell them apart, this can only be done through 1349 * Netlink calls assuming kernel drivers are recent enough to 1350 * support them. 1351 * 1352 * In the event of identification failure through Netlink, try again 1353 * through sysfs, then either: 1354 * 1355 * 1. No device matches (n == 0), complain and bail out. 1356 * 2. A single IB device matches (n == 1) and is not a representor, 1357 * assume no switch support. 1358 * 3. Otherwise no safe assumptions can be made; complain louder and 1359 * bail out. 1360 */ 1361 for (i = 0; i != n; ++i) { 1362 list[i].ibv_dev = ibv_match[i]; 1363 list[i].eth_dev = NULL; 1364 if (nl_rdma < 0) 1365 list[i].ifindex = 0; 1366 else 1367 list[i].ifindex = mlx5_nl_ifindex 1368 (nl_rdma, list[i].ibv_dev->name); 1369 if (nl_route < 0 || 1370 !list[i].ifindex || 1371 mlx5_nl_switch_info(nl_route, list[i].ifindex, 1372 &list[i].info) || 1373 ((!list[i].info.representor && !list[i].info.master) && 1374 mlx5_sysfs_switch_info(list[i].ifindex, &list[i].info))) { 1375 list[i].ifindex = 0; 1376 memset(&list[i].info, 0, sizeof(list[i].info)); 1377 continue; 1378 } 1379 } 1380 if (nl_rdma >= 0) 1381 close(nl_rdma); 1382 if (nl_route >= 0) 1383 close(nl_route); 1384 /* Count unidentified devices. */ 1385 for (u = 0, i = 0; i != n; ++i) 1386 if (!list[i].info.master && !list[i].info.representor) 1387 ++u; 1388 if (u) { 1389 if (n == 1 && u == 1) { 1390 /* Case #2. */ 1391 DRV_LOG(INFO, "no switch support detected"); 1392 } else { 1393 /* Case #3. */ 1394 DRV_LOG(ERR, 1395 "unable to tell which of the matching devices" 1396 " is the master (lack of kernel support?)"); 1397 n = 0; 1398 } 1399 } 1400 /* 1401 * Sort list to probe devices in natural order for users convenience 1402 * (i.e. master first, then representors from lowest to highest ID). 1403 */ 1404 if (n) 1405 qsort(list, n, sizeof(*list), mlx5_dev_spawn_data_cmp); 1406 switch (pci_dev->id.device_id) { 1407 case PCI_DEVICE_ID_MELLANOX_CONNECTX4VF: 1408 case PCI_DEVICE_ID_MELLANOX_CONNECTX4LXVF: 1409 case PCI_DEVICE_ID_MELLANOX_CONNECTX5VF: 1410 case PCI_DEVICE_ID_MELLANOX_CONNECTX5EXVF: 1411 vf = 1; 1412 break; 1413 default: 1414 vf = 0; 1415 } 1416 for (i = 0; i != n; ++i) { 1417 uint32_t restore; 1418 1419 list[i].eth_dev = mlx5_dev_spawn 1420 (&pci_dev->device, list[i].ibv_dev, vf, &list[i].info); 1421 if (!list[i].eth_dev) { 1422 if (rte_errno != EBUSY) 1423 break; 1424 /* Device is disabled, ignore it. */ 1425 continue; 1426 } 1427 restore = list[i].eth_dev->data->dev_flags; 1428 rte_eth_copy_pci_info(list[i].eth_dev, pci_dev); 1429 /* Restore non-PCI flags cleared by the above call. */ 1430 list[i].eth_dev->data->dev_flags |= restore; 1431 rte_eth_dev_probing_finish(list[i].eth_dev); 1432 } 1433 mlx5_glue->free_device_list(ibv_list); 1434 if (!n) { 1435 DRV_LOG(WARNING, 1436 "no Verbs device matches PCI device " PCI_PRI_FMT "," 1437 " are kernel drivers loaded?", 1438 pci_dev->addr.domain, pci_dev->addr.bus, 1439 pci_dev->addr.devid, pci_dev->addr.function); 1440 rte_errno = ENOENT; 1441 ret = -rte_errno; 1442 } else if (i != n) { 1443 DRV_LOG(ERR, 1444 "probe of PCI device " PCI_PRI_FMT " aborted after" 1445 " encountering an error: %s", 1446 pci_dev->addr.domain, pci_dev->addr.bus, 1447 pci_dev->addr.devid, pci_dev->addr.function, 1448 strerror(rte_errno)); 1449 ret = -rte_errno; 1450 /* Roll back. */ 1451 while (i--) { 1452 if (!list[i].eth_dev) 1453 continue; 1454 mlx5_dev_close(list[i].eth_dev); 1455 /* mac_addrs must not be freed because in dev_private */ 1456 list[i].eth_dev->data->mac_addrs = NULL; 1457 claim_zero(rte_eth_dev_release_port(list[i].eth_dev)); 1458 } 1459 /* Restore original error. */ 1460 rte_errno = -ret; 1461 } else { 1462 ret = 0; 1463 } 1464 return ret; 1465 } 1466 1467 static const struct rte_pci_id mlx5_pci_id_map[] = { 1468 { 1469 RTE_PCI_DEVICE(PCI_VENDOR_ID_MELLANOX, 1470 PCI_DEVICE_ID_MELLANOX_CONNECTX4) 1471 }, 1472 { 1473 RTE_PCI_DEVICE(PCI_VENDOR_ID_MELLANOX, 1474 PCI_DEVICE_ID_MELLANOX_CONNECTX4VF) 1475 }, 1476 { 1477 RTE_PCI_DEVICE(PCI_VENDOR_ID_MELLANOX, 1478 PCI_DEVICE_ID_MELLANOX_CONNECTX4LX) 1479 }, 1480 { 1481 RTE_PCI_DEVICE(PCI_VENDOR_ID_MELLANOX, 1482 PCI_DEVICE_ID_MELLANOX_CONNECTX4LXVF) 1483 }, 1484 { 1485 RTE_PCI_DEVICE(PCI_VENDOR_ID_MELLANOX, 1486 PCI_DEVICE_ID_MELLANOX_CONNECTX5) 1487 }, 1488 { 1489 RTE_PCI_DEVICE(PCI_VENDOR_ID_MELLANOX, 1490 PCI_DEVICE_ID_MELLANOX_CONNECTX5VF) 1491 }, 1492 { 1493 RTE_PCI_DEVICE(PCI_VENDOR_ID_MELLANOX, 1494 PCI_DEVICE_ID_MELLANOX_CONNECTX5EX) 1495 }, 1496 { 1497 RTE_PCI_DEVICE(PCI_VENDOR_ID_MELLANOX, 1498 PCI_DEVICE_ID_MELLANOX_CONNECTX5EXVF) 1499 }, 1500 { 1501 RTE_PCI_DEVICE(PCI_VENDOR_ID_MELLANOX, 1502 PCI_DEVICE_ID_MELLANOX_CONNECTX5BF) 1503 }, 1504 { 1505 RTE_PCI_DEVICE(PCI_VENDOR_ID_MELLANOX, 1506 PCI_DEVICE_ID_MELLANOX_CONNECTX5BFVF) 1507 }, 1508 { 1509 .vendor_id = 0 1510 } 1511 }; 1512 1513 static struct rte_pci_driver mlx5_driver = { 1514 .driver = { 1515 .name = MLX5_DRIVER_NAME 1516 }, 1517 .id_table = mlx5_pci_id_map, 1518 .probe = mlx5_pci_probe, 1519 .drv_flags = RTE_PCI_DRV_INTR_LSC | RTE_PCI_DRV_INTR_RMV, 1520 }; 1521 1522 #ifdef RTE_LIBRTE_MLX5_DLOPEN_DEPS 1523 1524 /** 1525 * Suffix RTE_EAL_PMD_PATH with "-glue". 1526 * 1527 * This function performs a sanity check on RTE_EAL_PMD_PATH before 1528 * suffixing its last component. 1529 * 1530 * @param buf[out] 1531 * Output buffer, should be large enough otherwise NULL is returned. 1532 * @param size 1533 * Size of @p out. 1534 * 1535 * @return 1536 * Pointer to @p buf or @p NULL in case suffix cannot be appended. 1537 */ 1538 static char * 1539 mlx5_glue_path(char *buf, size_t size) 1540 { 1541 static const char *const bad[] = { "/", ".", "..", NULL }; 1542 const char *path = RTE_EAL_PMD_PATH; 1543 size_t len = strlen(path); 1544 size_t off; 1545 int i; 1546 1547 while (len && path[len - 1] == '/') 1548 --len; 1549 for (off = len; off && path[off - 1] != '/'; --off) 1550 ; 1551 for (i = 0; bad[i]; ++i) 1552 if (!strncmp(path + off, bad[i], (int)(len - off))) 1553 goto error; 1554 i = snprintf(buf, size, "%.*s-glue", (int)len, path); 1555 if (i == -1 || (size_t)i >= size) 1556 goto error; 1557 return buf; 1558 error: 1559 DRV_LOG(ERR, 1560 "unable to append \"-glue\" to last component of" 1561 " RTE_EAL_PMD_PATH (\"" RTE_EAL_PMD_PATH "\")," 1562 " please re-configure DPDK"); 1563 return NULL; 1564 } 1565 1566 /** 1567 * Initialization routine for run-time dependency on rdma-core. 1568 */ 1569 static int 1570 mlx5_glue_init(void) 1571 { 1572 char glue_path[sizeof(RTE_EAL_PMD_PATH) - 1 + sizeof("-glue")]; 1573 const char *path[] = { 1574 /* 1575 * A basic security check is necessary before trusting 1576 * MLX5_GLUE_PATH, which may override RTE_EAL_PMD_PATH. 1577 */ 1578 (geteuid() == getuid() && getegid() == getgid() ? 1579 getenv("MLX5_GLUE_PATH") : NULL), 1580 /* 1581 * When RTE_EAL_PMD_PATH is set, use its glue-suffixed 1582 * variant, otherwise let dlopen() look up libraries on its 1583 * own. 1584 */ 1585 (*RTE_EAL_PMD_PATH ? 1586 mlx5_glue_path(glue_path, sizeof(glue_path)) : ""), 1587 }; 1588 unsigned int i = 0; 1589 void *handle = NULL; 1590 void **sym; 1591 const char *dlmsg; 1592 1593 while (!handle && i != RTE_DIM(path)) { 1594 const char *end; 1595 size_t len; 1596 int ret; 1597 1598 if (!path[i]) { 1599 ++i; 1600 continue; 1601 } 1602 end = strpbrk(path[i], ":;"); 1603 if (!end) 1604 end = path[i] + strlen(path[i]); 1605 len = end - path[i]; 1606 ret = 0; 1607 do { 1608 char name[ret + 1]; 1609 1610 ret = snprintf(name, sizeof(name), "%.*s%s" MLX5_GLUE, 1611 (int)len, path[i], 1612 (!len || *(end - 1) == '/') ? "" : "/"); 1613 if (ret == -1) 1614 break; 1615 if (sizeof(name) != (size_t)ret + 1) 1616 continue; 1617 DRV_LOG(DEBUG, "looking for rdma-core glue as \"%s\"", 1618 name); 1619 handle = dlopen(name, RTLD_LAZY); 1620 break; 1621 } while (1); 1622 path[i] = end + 1; 1623 if (!*end) 1624 ++i; 1625 } 1626 if (!handle) { 1627 rte_errno = EINVAL; 1628 dlmsg = dlerror(); 1629 if (dlmsg) 1630 DRV_LOG(WARNING, "cannot load glue library: %s", dlmsg); 1631 goto glue_error; 1632 } 1633 sym = dlsym(handle, "mlx5_glue"); 1634 if (!sym || !*sym) { 1635 rte_errno = EINVAL; 1636 dlmsg = dlerror(); 1637 if (dlmsg) 1638 DRV_LOG(ERR, "cannot resolve glue symbol: %s", dlmsg); 1639 goto glue_error; 1640 } 1641 mlx5_glue = *sym; 1642 return 0; 1643 glue_error: 1644 if (handle) 1645 dlclose(handle); 1646 DRV_LOG(WARNING, 1647 "cannot initialize PMD due to missing run-time dependency on" 1648 " rdma-core libraries (libibverbs, libmlx5)"); 1649 return -rte_errno; 1650 } 1651 1652 #endif 1653 1654 /** 1655 * Driver initialization routine. 1656 */ 1657 RTE_INIT(rte_mlx5_pmd_init) 1658 { 1659 /* Initialize driver log type. */ 1660 mlx5_logtype = rte_log_register("pmd.net.mlx5"); 1661 if (mlx5_logtype >= 0) 1662 rte_log_set_level(mlx5_logtype, RTE_LOG_NOTICE); 1663 1664 /* Build the static tables for Verbs conversion. */ 1665 mlx5_set_ptype_table(); 1666 mlx5_set_cksum_table(); 1667 mlx5_set_swp_types_table(); 1668 /* 1669 * RDMAV_HUGEPAGES_SAFE tells ibv_fork_init() we intend to use 1670 * huge pages. Calling ibv_fork_init() during init allows 1671 * applications to use fork() safely for purposes other than 1672 * using this PMD, which is not supported in forked processes. 1673 */ 1674 setenv("RDMAV_HUGEPAGES_SAFE", "1", 1); 1675 /* Match the size of Rx completion entry to the size of a cacheline. */ 1676 if (RTE_CACHE_LINE_SIZE == 128) 1677 setenv("MLX5_CQE_SIZE", "128", 0); 1678 /* 1679 * MLX5_DEVICE_FATAL_CLEANUP tells ibv_destroy functions to 1680 * cleanup all the Verbs resources even when the device was removed. 1681 */ 1682 setenv("MLX5_DEVICE_FATAL_CLEANUP", "1", 1); 1683 #ifdef RTE_LIBRTE_MLX5_DLOPEN_DEPS 1684 if (mlx5_glue_init()) 1685 return; 1686 assert(mlx5_glue); 1687 #endif 1688 #ifndef NDEBUG 1689 /* Glue structure must not contain any NULL pointers. */ 1690 { 1691 unsigned int i; 1692 1693 for (i = 0; i != sizeof(*mlx5_glue) / sizeof(void *); ++i) 1694 assert(((const void *const *)mlx5_glue)[i]); 1695 } 1696 #endif 1697 if (strcmp(mlx5_glue->version, MLX5_GLUE_VERSION)) { 1698 DRV_LOG(ERR, 1699 "rdma-core glue \"%s\" mismatch: \"%s\" is required", 1700 mlx5_glue->version, MLX5_GLUE_VERSION); 1701 return; 1702 } 1703 mlx5_glue->fork_init(); 1704 rte_pci_register(&mlx5_driver); 1705 } 1706 1707 RTE_PMD_EXPORT_NAME(net_mlx5, __COUNTER__); 1708 RTE_PMD_REGISTER_PCI_TABLE(net_mlx5, mlx5_pci_id_map); 1709 RTE_PMD_REGISTER_KMOD_DEP(net_mlx5, "* ib_uverbs & mlx5_core & mlx5_ib"); 1710