1 /* SPDX-License-Identifier: BSD-3-Clause 2 * Copyright 2015 6WIND S.A. 3 * Copyright 2015 Mellanox Technologies, Ltd 4 */ 5 6 #include <stddef.h> 7 #include <unistd.h> 8 #include <string.h> 9 #include <assert.h> 10 #include <dlfcn.h> 11 #include <stdint.h> 12 #include <stdlib.h> 13 #include <errno.h> 14 #include <net/if.h> 15 #include <sys/mman.h> 16 #include <linux/rtnetlink.h> 17 18 /* Verbs header. */ 19 /* ISO C doesn't support unnamed structs/unions, disabling -pedantic. */ 20 #ifdef PEDANTIC 21 #pragma GCC diagnostic ignored "-Wpedantic" 22 #endif 23 #include <infiniband/verbs.h> 24 #ifdef PEDANTIC 25 #pragma GCC diagnostic error "-Wpedantic" 26 #endif 27 28 #include <rte_malloc.h> 29 #include <rte_ethdev_driver.h> 30 #include <rte_ethdev_pci.h> 31 #include <rte_pci.h> 32 #include <rte_bus_pci.h> 33 #include <rte_common.h> 34 #include <rte_config.h> 35 #include <rte_eal_memconfig.h> 36 #include <rte_kvargs.h> 37 #include <rte_rwlock.h> 38 #include <rte_spinlock.h> 39 #include <rte_string_fns.h> 40 41 #include "mlx5.h" 42 #include "mlx5_utils.h" 43 #include "mlx5_rxtx.h" 44 #include "mlx5_autoconf.h" 45 #include "mlx5_defs.h" 46 #include "mlx5_glue.h" 47 #include "mlx5_mr.h" 48 #include "mlx5_flow.h" 49 50 /* Device parameter to enable RX completion queue compression. */ 51 #define MLX5_RXQ_CQE_COMP_EN "rxq_cqe_comp_en" 52 53 /* Device parameter to enable RX completion entry padding to 128B. */ 54 #define MLX5_RXQ_CQE_PAD_EN "rxq_cqe_pad_en" 55 56 /* Device parameter to enable padding Rx packet to cacheline size. */ 57 #define MLX5_RXQ_PKT_PAD_EN "rxq_pkt_pad_en" 58 59 /* Device parameter to enable Multi-Packet Rx queue. */ 60 #define MLX5_RX_MPRQ_EN "mprq_en" 61 62 /* Device parameter to configure log 2 of the number of strides for MPRQ. */ 63 #define MLX5_RX_MPRQ_LOG_STRIDE_NUM "mprq_log_stride_num" 64 65 /* Device parameter to limit the size of memcpy'd packet for MPRQ. */ 66 #define MLX5_RX_MPRQ_MAX_MEMCPY_LEN "mprq_max_memcpy_len" 67 68 /* Device parameter to set the minimum number of Rx queues to enable MPRQ. */ 69 #define MLX5_RXQS_MIN_MPRQ "rxqs_min_mprq" 70 71 /* Device parameter to configure inline send. */ 72 #define MLX5_TXQ_INLINE "txq_inline" 73 74 /* 75 * Device parameter to configure the number of TX queues threshold for 76 * enabling inline send. 77 */ 78 #define MLX5_TXQS_MIN_INLINE "txqs_min_inline" 79 80 /* 81 * Device parameter to configure the number of TX queues threshold for 82 * enabling vectorized Tx. 83 */ 84 #define MLX5_TXQS_MAX_VEC "txqs_max_vec" 85 86 /* Device parameter to enable multi-packet send WQEs. */ 87 #define MLX5_TXQ_MPW_EN "txq_mpw_en" 88 89 /* Device parameter to include 2 dsegs in the title WQEBB. */ 90 #define MLX5_TXQ_MPW_HDR_DSEG_EN "txq_mpw_hdr_dseg_en" 91 92 /* Device parameter to limit the size of inlining packet. */ 93 #define MLX5_TXQ_MAX_INLINE_LEN "txq_max_inline_len" 94 95 /* Device parameter to enable hardware Tx vector. */ 96 #define MLX5_TX_VEC_EN "tx_vec_en" 97 98 /* Device parameter to enable hardware Rx vector. */ 99 #define MLX5_RX_VEC_EN "rx_vec_en" 100 101 /* Allow L3 VXLAN flow creation. */ 102 #define MLX5_L3_VXLAN_EN "l3_vxlan_en" 103 104 /* Activate DV E-Switch flow steering. */ 105 #define MLX5_DV_ESW_EN "dv_esw_en" 106 107 /* Activate DV flow steering. */ 108 #define MLX5_DV_FLOW_EN "dv_flow_en" 109 110 /* Activate Netlink support in VF mode. */ 111 #define MLX5_VF_NL_EN "vf_nl_en" 112 113 /* Enable extending memsegs when creating a MR. */ 114 #define MLX5_MR_EXT_MEMSEG_EN "mr_ext_memseg_en" 115 116 /* Select port representors to instantiate. */ 117 #define MLX5_REPRESENTOR "representor" 118 119 #ifndef HAVE_IBV_MLX5_MOD_MPW 120 #define MLX5DV_CONTEXT_FLAGS_MPW_ALLOWED (1 << 2) 121 #define MLX5DV_CONTEXT_FLAGS_ENHANCED_MPW (1 << 3) 122 #endif 123 124 #ifndef HAVE_IBV_MLX5_MOD_CQE_128B_COMP 125 #define MLX5DV_CONTEXT_FLAGS_CQE_128B_COMP (1 << 4) 126 #endif 127 128 static const char *MZ_MLX5_PMD_SHARED_DATA = "mlx5_pmd_shared_data"; 129 130 /* Shared memory between primary and secondary processes. */ 131 struct mlx5_shared_data *mlx5_shared_data; 132 133 /* Spinlock for mlx5_shared_data allocation. */ 134 static rte_spinlock_t mlx5_shared_data_lock = RTE_SPINLOCK_INITIALIZER; 135 136 /* Process local data for secondary processes. */ 137 static struct mlx5_local_data mlx5_local_data; 138 139 /** Driver-specific log messages type. */ 140 int mlx5_logtype; 141 142 /** Data associated with devices to spawn. */ 143 struct mlx5_dev_spawn_data { 144 uint32_t ifindex; /**< Network interface index. */ 145 uint32_t max_port; /**< IB device maximal port index. */ 146 uint32_t ibv_port; /**< IB device physical port index. */ 147 struct mlx5_switch_info info; /**< Switch information. */ 148 struct ibv_device *ibv_dev; /**< Associated IB device. */ 149 struct rte_eth_dev *eth_dev; /**< Associated Ethernet device. */ 150 }; 151 152 static LIST_HEAD(, mlx5_ibv_shared) mlx5_ibv_list = LIST_HEAD_INITIALIZER(); 153 static pthread_mutex_t mlx5_ibv_list_mutex = PTHREAD_MUTEX_INITIALIZER; 154 155 /** 156 * Allocate shared IB device context. If there is multiport device the 157 * master and representors will share this context, if there is single 158 * port dedicated IB device, the context will be used by only given 159 * port due to unification. 160 * 161 * Routine first searches the context for the specified IB device name, 162 * if found the shared context assumed and reference counter is incremented. 163 * If no context found the new one is created and initialized with specified 164 * IB device context and parameters. 165 * 166 * @param[in] spawn 167 * Pointer to the IB device attributes (name, port, etc). 168 * 169 * @return 170 * Pointer to mlx5_ibv_shared object on success, 171 * otherwise NULL and rte_errno is set. 172 */ 173 static struct mlx5_ibv_shared * 174 mlx5_alloc_shared_ibctx(const struct mlx5_dev_spawn_data *spawn) 175 { 176 struct mlx5_ibv_shared *sh; 177 int err = 0; 178 uint32_t i; 179 180 assert(spawn); 181 /* Secondary process should not create the shared context. */ 182 assert(rte_eal_process_type() == RTE_PROC_PRIMARY); 183 pthread_mutex_lock(&mlx5_ibv_list_mutex); 184 /* Search for IB context by device name. */ 185 LIST_FOREACH(sh, &mlx5_ibv_list, next) { 186 if (!strcmp(sh->ibdev_name, spawn->ibv_dev->name)) { 187 sh->refcnt++; 188 goto exit; 189 } 190 } 191 /* No device found, we have to create new shared context. */ 192 assert(spawn->max_port); 193 sh = rte_zmalloc("ethdev shared ib context", 194 sizeof(struct mlx5_ibv_shared) + 195 spawn->max_port * 196 sizeof(struct mlx5_ibv_shared_port), 197 RTE_CACHE_LINE_SIZE); 198 if (!sh) { 199 DRV_LOG(ERR, "shared context allocation failure"); 200 rte_errno = ENOMEM; 201 goto exit; 202 } 203 /* Try to open IB device with DV first, then usual Verbs. */ 204 errno = 0; 205 sh->ctx = mlx5_glue->dv_open_device(spawn->ibv_dev); 206 if (sh->ctx) { 207 sh->devx = 1; 208 DRV_LOG(DEBUG, "DevX is supported"); 209 } else { 210 sh->ctx = mlx5_glue->open_device(spawn->ibv_dev); 211 if (!sh->ctx) { 212 err = errno ? errno : ENODEV; 213 goto error; 214 } 215 DRV_LOG(DEBUG, "DevX is NOT supported"); 216 } 217 err = mlx5_glue->query_device_ex(sh->ctx, NULL, &sh->device_attr); 218 if (err) { 219 DRV_LOG(DEBUG, "ibv_query_device_ex() failed"); 220 goto error; 221 } 222 sh->refcnt = 1; 223 sh->max_port = spawn->max_port; 224 strncpy(sh->ibdev_name, sh->ctx->device->name, 225 sizeof(sh->ibdev_name)); 226 strncpy(sh->ibdev_path, sh->ctx->device->ibdev_path, 227 sizeof(sh->ibdev_path)); 228 pthread_mutex_init(&sh->intr_mutex, NULL); 229 /* 230 * Setting port_id to max unallowed value means 231 * there is no interrupt subhandler installed for 232 * the given port index i. 233 */ 234 for (i = 0; i < sh->max_port; i++) 235 sh->port[i].ih_port_id = RTE_MAX_ETHPORTS; 236 sh->pd = mlx5_glue->alloc_pd(sh->ctx); 237 if (sh->pd == NULL) { 238 DRV_LOG(ERR, "PD allocation failure"); 239 err = ENOMEM; 240 goto error; 241 } 242 LIST_INSERT_HEAD(&mlx5_ibv_list, sh, next); 243 exit: 244 pthread_mutex_unlock(&mlx5_ibv_list_mutex); 245 return sh; 246 error: 247 pthread_mutex_unlock(&mlx5_ibv_list_mutex); 248 assert(sh); 249 if (sh->pd) 250 claim_zero(mlx5_glue->dealloc_pd(sh->pd)); 251 if (sh->ctx) 252 claim_zero(mlx5_glue->close_device(sh->ctx)); 253 rte_free(sh); 254 assert(err > 0); 255 rte_errno = err; 256 return NULL; 257 } 258 259 /** 260 * Free shared IB device context. Decrement counter and if zero free 261 * all allocated resources and close handles. 262 * 263 * @param[in] sh 264 * Pointer to mlx5_ibv_shared object to free 265 */ 266 static void 267 mlx5_free_shared_ibctx(struct mlx5_ibv_shared *sh) 268 { 269 pthread_mutex_lock(&mlx5_ibv_list_mutex); 270 #ifndef NDEBUG 271 /* Check the object presence in the list. */ 272 struct mlx5_ibv_shared *lctx; 273 274 LIST_FOREACH(lctx, &mlx5_ibv_list, next) 275 if (lctx == sh) 276 break; 277 assert(lctx); 278 if (lctx != sh) { 279 DRV_LOG(ERR, "Freeing non-existing shared IB context"); 280 goto exit; 281 } 282 #endif 283 assert(sh); 284 assert(sh->refcnt); 285 /* Secondary process should not free the shared context. */ 286 assert(rte_eal_process_type() == RTE_PROC_PRIMARY); 287 if (--sh->refcnt) 288 goto exit; 289 LIST_REMOVE(sh, next); 290 /* 291 * Ensure there is no async event handler installed. 292 * Only primary process handles async device events. 293 **/ 294 assert(!sh->intr_cnt); 295 if (sh->intr_cnt) 296 rte_intr_callback_unregister 297 (&sh->intr_handle, mlx5_dev_interrupt_handler, sh); 298 pthread_mutex_destroy(&sh->intr_mutex); 299 if (sh->pd) 300 claim_zero(mlx5_glue->dealloc_pd(sh->pd)); 301 if (sh->ctx) 302 claim_zero(mlx5_glue->close_device(sh->ctx)); 303 rte_free(sh); 304 exit: 305 pthread_mutex_unlock(&mlx5_ibv_list_mutex); 306 } 307 308 /** 309 * Initialize DR related data within private structure. 310 * Routine checks the reference counter and does actual 311 * resources creation/initialization only if counter is zero. 312 * 313 * @param[in] priv 314 * Pointer to the private device data structure. 315 * 316 * @return 317 * Zero on success, positive error code otherwise. 318 */ 319 static int 320 mlx5_alloc_shared_dr(struct mlx5_priv *priv) 321 { 322 #ifdef HAVE_MLX5DV_DR 323 struct mlx5_ibv_shared *sh = priv->sh; 324 int err = 0; 325 void *ns; 326 327 assert(sh); 328 if (sh->dv_refcnt) { 329 /* Shared DV/DR structures is already initialized. */ 330 sh->dv_refcnt++; 331 priv->dr_shared = 1; 332 return 0; 333 } 334 /* Reference counter is zero, we should initialize structures. */ 335 ns = mlx5dv_dr_create_ns(sh->ctx, MLX5DV_DR_NS_DOMAIN_INGRESS_BYPASS); 336 if (!ns) { 337 DRV_LOG(ERR, "ingress mlx5dv_dr_create_ns failed"); 338 err = errno; 339 goto error; 340 } 341 sh->rx_ns = ns; 342 ns = mlx5dv_dr_create_ns(sh->ctx, MLX5DV_DR_NS_DOMAIN_EGRESS_BYPASS); 343 if (!ns) { 344 DRV_LOG(ERR, "egress mlx5dv_dr_create_ns failed"); 345 err = errno; 346 goto error; 347 } 348 pthread_mutex_init(&sh->dv_mutex, NULL); 349 sh->tx_ns = ns; 350 #ifdef HAVE_MLX5DV_DR_ESWITCH 351 if (priv->config.dv_esw_en) { 352 ns = mlx5_glue->dr_create_ns(sh->ctx, 353 MLX5DV_DR_NS_DOMAIN_FDB_BYPASS); 354 if (!ns) { 355 DRV_LOG(ERR, "FDB mlx5dv_dr_create_ns failed"); 356 err = errno; 357 goto error; 358 } 359 sh->fdb_ns = ns; 360 sh->esw_drop_action = mlx5_glue->dr_create_flow_action_drop(); 361 } 362 #endif 363 sh->dv_refcnt++; 364 priv->dr_shared = 1; 365 return 0; 366 367 error: 368 /* Rollback the created objects. */ 369 if (sh->rx_ns) { 370 mlx5dv_dr_destroy_ns(sh->rx_ns); 371 sh->rx_ns = NULL; 372 } 373 if (sh->tx_ns) { 374 mlx5dv_dr_destroy_ns(sh->tx_ns); 375 sh->tx_ns = NULL; 376 } 377 if (sh->fdb_ns) { 378 mlx5_glue->dr_destroy_ns(sh->fdb_ns); 379 sh->fdb_ns = NULL; 380 } 381 if (sh->esw_drop_action) { 382 mlx5_glue->destroy_flow_action(sh->esw_drop_action); 383 sh->esw_drop_action = NULL; 384 } 385 return err; 386 #else 387 (void)priv; 388 return 0; 389 #endif 390 } 391 392 /** 393 * Destroy DR related data within private structure. 394 * 395 * @param[in] priv 396 * Pointer to the private device data structure. 397 */ 398 static void 399 mlx5_free_shared_dr(struct mlx5_priv *priv) 400 { 401 #ifdef HAVE_MLX5DV_DR 402 struct mlx5_ibv_shared *sh; 403 404 if (!priv->dr_shared) 405 return; 406 priv->dr_shared = 0; 407 sh = priv->sh; 408 assert(sh); 409 assert(sh->dv_refcnt); 410 if (sh->dv_refcnt && --sh->dv_refcnt) 411 return; 412 if (sh->rx_ns) { 413 mlx5dv_dr_destroy_ns(sh->rx_ns); 414 sh->rx_ns = NULL; 415 } 416 if (sh->tx_ns) { 417 mlx5dv_dr_destroy_ns(sh->tx_ns); 418 sh->tx_ns = NULL; 419 } 420 #ifdef HAVE_MLX5DV_DR_ESWITCH 421 if (sh->fdb_ns) { 422 mlx5_glue->dr_destroy_ns(sh->fdb_ns); 423 sh->fdb_ns = NULL; 424 } 425 if (sh->esw_drop_action) { 426 mlx5_glue->destroy_flow_action(sh->esw_drop_action); 427 sh->esw_drop_action = NULL; 428 } 429 #endif 430 pthread_mutex_destroy(&sh->dv_mutex); 431 #else 432 (void)priv; 433 #endif 434 } 435 436 /** 437 * Initialize shared data between primary and secondary process. 438 * 439 * A memzone is reserved by primary process and secondary processes attach to 440 * the memzone. 441 * 442 * @return 443 * 0 on success, a negative errno value otherwise and rte_errno is set. 444 */ 445 static int 446 mlx5_init_shared_data(void) 447 { 448 const struct rte_memzone *mz; 449 int ret = 0; 450 451 rte_spinlock_lock(&mlx5_shared_data_lock); 452 if (mlx5_shared_data == NULL) { 453 if (rte_eal_process_type() == RTE_PROC_PRIMARY) { 454 /* Allocate shared memory. */ 455 mz = rte_memzone_reserve(MZ_MLX5_PMD_SHARED_DATA, 456 sizeof(*mlx5_shared_data), 457 SOCKET_ID_ANY, 0); 458 if (mz == NULL) { 459 DRV_LOG(ERR, 460 "Cannot allocate mlx5 shared data\n"); 461 ret = -rte_errno; 462 goto error; 463 } 464 mlx5_shared_data = mz->addr; 465 memset(mlx5_shared_data, 0, sizeof(*mlx5_shared_data)); 466 rte_spinlock_init(&mlx5_shared_data->lock); 467 } else { 468 /* Lookup allocated shared memory. */ 469 mz = rte_memzone_lookup(MZ_MLX5_PMD_SHARED_DATA); 470 if (mz == NULL) { 471 DRV_LOG(ERR, 472 "Cannot attach mlx5 shared data\n"); 473 ret = -rte_errno; 474 goto error; 475 } 476 mlx5_shared_data = mz->addr; 477 memset(&mlx5_local_data, 0, sizeof(mlx5_local_data)); 478 } 479 } 480 error: 481 rte_spinlock_unlock(&mlx5_shared_data_lock); 482 return ret; 483 } 484 485 /** 486 * Retrieve integer value from environment variable. 487 * 488 * @param[in] name 489 * Environment variable name. 490 * 491 * @return 492 * Integer value, 0 if the variable is not set. 493 */ 494 int 495 mlx5_getenv_int(const char *name) 496 { 497 const char *val = getenv(name); 498 499 if (val == NULL) 500 return 0; 501 return atoi(val); 502 } 503 504 /** 505 * Verbs callback to allocate a memory. This function should allocate the space 506 * according to the size provided residing inside a huge page. 507 * Please note that all allocation must respect the alignment from libmlx5 508 * (i.e. currently sysconf(_SC_PAGESIZE)). 509 * 510 * @param[in] size 511 * The size in bytes of the memory to allocate. 512 * @param[in] data 513 * A pointer to the callback data. 514 * 515 * @return 516 * Allocated buffer, NULL otherwise and rte_errno is set. 517 */ 518 static void * 519 mlx5_alloc_verbs_buf(size_t size, void *data) 520 { 521 struct mlx5_priv *priv = data; 522 void *ret; 523 size_t alignment = sysconf(_SC_PAGESIZE); 524 unsigned int socket = SOCKET_ID_ANY; 525 526 if (priv->verbs_alloc_ctx.type == MLX5_VERBS_ALLOC_TYPE_TX_QUEUE) { 527 const struct mlx5_txq_ctrl *ctrl = priv->verbs_alloc_ctx.obj; 528 529 socket = ctrl->socket; 530 } else if (priv->verbs_alloc_ctx.type == 531 MLX5_VERBS_ALLOC_TYPE_RX_QUEUE) { 532 const struct mlx5_rxq_ctrl *ctrl = priv->verbs_alloc_ctx.obj; 533 534 socket = ctrl->socket; 535 } 536 assert(data != NULL); 537 ret = rte_malloc_socket(__func__, size, alignment, socket); 538 if (!ret && size) 539 rte_errno = ENOMEM; 540 return ret; 541 } 542 543 /** 544 * Verbs callback to free a memory. 545 * 546 * @param[in] ptr 547 * A pointer to the memory to free. 548 * @param[in] data 549 * A pointer to the callback data. 550 */ 551 static void 552 mlx5_free_verbs_buf(void *ptr, void *data __rte_unused) 553 { 554 assert(data != NULL); 555 rte_free(ptr); 556 } 557 558 /** 559 * Initialize process private data structure. 560 * 561 * @param dev 562 * Pointer to Ethernet device structure. 563 * 564 * @return 565 * 0 on success, a negative errno value otherwise and rte_errno is set. 566 */ 567 int 568 mlx5_proc_priv_init(struct rte_eth_dev *dev) 569 { 570 struct mlx5_priv *priv = dev->data->dev_private; 571 struct mlx5_proc_priv *ppriv; 572 size_t ppriv_size; 573 574 /* 575 * UAR register table follows the process private structure. BlueFlame 576 * registers for Tx queues are stored in the table. 577 */ 578 ppriv_size = 579 sizeof(struct mlx5_proc_priv) + priv->txqs_n * sizeof(void *); 580 ppriv = rte_malloc_socket("mlx5_proc_priv", ppriv_size, 581 RTE_CACHE_LINE_SIZE, dev->device->numa_node); 582 if (!ppriv) { 583 rte_errno = ENOMEM; 584 return -rte_errno; 585 } 586 ppriv->uar_table_sz = ppriv_size; 587 dev->process_private = ppriv; 588 return 0; 589 } 590 591 /** 592 * Un-initialize process private data structure. 593 * 594 * @param dev 595 * Pointer to Ethernet device structure. 596 */ 597 static void 598 mlx5_proc_priv_uninit(struct rte_eth_dev *dev) 599 { 600 if (!dev->process_private) 601 return; 602 rte_free(dev->process_private); 603 dev->process_private = NULL; 604 } 605 606 /** 607 * DPDK callback to close the device. 608 * 609 * Destroy all queues and objects, free memory. 610 * 611 * @param dev 612 * Pointer to Ethernet device structure. 613 */ 614 static void 615 mlx5_dev_close(struct rte_eth_dev *dev) 616 { 617 struct mlx5_priv *priv = dev->data->dev_private; 618 unsigned int i; 619 int ret; 620 621 DRV_LOG(DEBUG, "port %u closing device \"%s\"", 622 dev->data->port_id, 623 ((priv->sh->ctx != NULL) ? priv->sh->ctx->device->name : "")); 624 /* In case mlx5_dev_stop() has not been called. */ 625 mlx5_dev_interrupt_handler_uninstall(dev); 626 mlx5_traffic_disable(dev); 627 mlx5_flow_flush(dev, NULL); 628 /* Prevent crashes when queues are still in use. */ 629 dev->rx_pkt_burst = removed_rx_burst; 630 dev->tx_pkt_burst = removed_tx_burst; 631 rte_wmb(); 632 /* Disable datapath on secondary process. */ 633 mlx5_mp_req_stop_rxtx(dev); 634 if (priv->rxqs != NULL) { 635 /* XXX race condition if mlx5_rx_burst() is still running. */ 636 usleep(1000); 637 for (i = 0; (i != priv->rxqs_n); ++i) 638 mlx5_rxq_release(dev, i); 639 priv->rxqs_n = 0; 640 priv->rxqs = NULL; 641 } 642 if (priv->txqs != NULL) { 643 /* XXX race condition if mlx5_tx_burst() is still running. */ 644 usleep(1000); 645 for (i = 0; (i != priv->txqs_n); ++i) 646 mlx5_txq_release(dev, i); 647 priv->txqs_n = 0; 648 priv->txqs = NULL; 649 } 650 mlx5_proc_priv_uninit(dev); 651 mlx5_mprq_free_mp(dev); 652 mlx5_mr_release(dev); 653 assert(priv->sh); 654 mlx5_free_shared_dr(priv); 655 if (priv->rss_conf.rss_key != NULL) 656 rte_free(priv->rss_conf.rss_key); 657 if (priv->reta_idx != NULL) 658 rte_free(priv->reta_idx); 659 if (priv->config.vf) 660 mlx5_nl_mac_addr_flush(dev); 661 if (priv->nl_socket_route >= 0) 662 close(priv->nl_socket_route); 663 if (priv->nl_socket_rdma >= 0) 664 close(priv->nl_socket_rdma); 665 if (priv->tcf_context) 666 mlx5_flow_tcf_context_destroy(priv->tcf_context); 667 if (priv->sh) { 668 /* 669 * Free the shared context in last turn, because the cleanup 670 * routines above may use some shared fields, like 671 * mlx5_nl_mac_addr_flush() uses ibdev_path for retrieveing 672 * ifindex if Netlink fails. 673 */ 674 mlx5_free_shared_ibctx(priv->sh); 675 priv->sh = NULL; 676 } 677 ret = mlx5_hrxq_ibv_verify(dev); 678 if (ret) 679 DRV_LOG(WARNING, "port %u some hash Rx queue still remain", 680 dev->data->port_id); 681 ret = mlx5_ind_table_ibv_verify(dev); 682 if (ret) 683 DRV_LOG(WARNING, "port %u some indirection table still remain", 684 dev->data->port_id); 685 ret = mlx5_rxq_ibv_verify(dev); 686 if (ret) 687 DRV_LOG(WARNING, "port %u some Verbs Rx queue still remain", 688 dev->data->port_id); 689 ret = mlx5_rxq_verify(dev); 690 if (ret) 691 DRV_LOG(WARNING, "port %u some Rx queues still remain", 692 dev->data->port_id); 693 ret = mlx5_txq_ibv_verify(dev); 694 if (ret) 695 DRV_LOG(WARNING, "port %u some Verbs Tx queue still remain", 696 dev->data->port_id); 697 ret = mlx5_txq_verify(dev); 698 if (ret) 699 DRV_LOG(WARNING, "port %u some Tx queues still remain", 700 dev->data->port_id); 701 ret = mlx5_flow_verify(dev); 702 if (ret) 703 DRV_LOG(WARNING, "port %u some flows still remain", 704 dev->data->port_id); 705 if (priv->domain_id != RTE_ETH_DEV_SWITCH_DOMAIN_ID_INVALID) { 706 unsigned int c = 0; 707 uint16_t port_id; 708 709 RTE_ETH_FOREACH_DEV_OF(port_id, dev->device) { 710 struct mlx5_priv *opriv = 711 rte_eth_devices[port_id].data->dev_private; 712 713 if (!opriv || 714 opriv->domain_id != priv->domain_id || 715 &rte_eth_devices[port_id] == dev) 716 continue; 717 ++c; 718 } 719 if (!c) 720 claim_zero(rte_eth_switch_domain_free(priv->domain_id)); 721 } 722 memset(priv, 0, sizeof(*priv)); 723 priv->domain_id = RTE_ETH_DEV_SWITCH_DOMAIN_ID_INVALID; 724 /* 725 * Reset mac_addrs to NULL such that it is not freed as part of 726 * rte_eth_dev_release_port(). mac_addrs is part of dev_private so 727 * it is freed when dev_private is freed. 728 */ 729 dev->data->mac_addrs = NULL; 730 } 731 732 const struct eth_dev_ops mlx5_dev_ops = { 733 .dev_configure = mlx5_dev_configure, 734 .dev_start = mlx5_dev_start, 735 .dev_stop = mlx5_dev_stop, 736 .dev_set_link_down = mlx5_set_link_down, 737 .dev_set_link_up = mlx5_set_link_up, 738 .dev_close = mlx5_dev_close, 739 .promiscuous_enable = mlx5_promiscuous_enable, 740 .promiscuous_disable = mlx5_promiscuous_disable, 741 .allmulticast_enable = mlx5_allmulticast_enable, 742 .allmulticast_disable = mlx5_allmulticast_disable, 743 .link_update = mlx5_link_update, 744 .stats_get = mlx5_stats_get, 745 .stats_reset = mlx5_stats_reset, 746 .xstats_get = mlx5_xstats_get, 747 .xstats_reset = mlx5_xstats_reset, 748 .xstats_get_names = mlx5_xstats_get_names, 749 .fw_version_get = mlx5_fw_version_get, 750 .dev_infos_get = mlx5_dev_infos_get, 751 .dev_supported_ptypes_get = mlx5_dev_supported_ptypes_get, 752 .vlan_filter_set = mlx5_vlan_filter_set, 753 .rx_queue_setup = mlx5_rx_queue_setup, 754 .tx_queue_setup = mlx5_tx_queue_setup, 755 .rx_queue_release = mlx5_rx_queue_release, 756 .tx_queue_release = mlx5_tx_queue_release, 757 .flow_ctrl_get = mlx5_dev_get_flow_ctrl, 758 .flow_ctrl_set = mlx5_dev_set_flow_ctrl, 759 .mac_addr_remove = mlx5_mac_addr_remove, 760 .mac_addr_add = mlx5_mac_addr_add, 761 .mac_addr_set = mlx5_mac_addr_set, 762 .set_mc_addr_list = mlx5_set_mc_addr_list, 763 .mtu_set = mlx5_dev_set_mtu, 764 .vlan_strip_queue_set = mlx5_vlan_strip_queue_set, 765 .vlan_offload_set = mlx5_vlan_offload_set, 766 .reta_update = mlx5_dev_rss_reta_update, 767 .reta_query = mlx5_dev_rss_reta_query, 768 .rss_hash_update = mlx5_rss_hash_update, 769 .rss_hash_conf_get = mlx5_rss_hash_conf_get, 770 .filter_ctrl = mlx5_dev_filter_ctrl, 771 .rx_descriptor_status = mlx5_rx_descriptor_status, 772 .tx_descriptor_status = mlx5_tx_descriptor_status, 773 .rx_queue_count = mlx5_rx_queue_count, 774 .rx_queue_intr_enable = mlx5_rx_intr_enable, 775 .rx_queue_intr_disable = mlx5_rx_intr_disable, 776 .is_removed = mlx5_is_removed, 777 }; 778 779 /* Available operations from secondary process. */ 780 static const struct eth_dev_ops mlx5_dev_sec_ops = { 781 .stats_get = mlx5_stats_get, 782 .stats_reset = mlx5_stats_reset, 783 .xstats_get = mlx5_xstats_get, 784 .xstats_reset = mlx5_xstats_reset, 785 .xstats_get_names = mlx5_xstats_get_names, 786 .fw_version_get = mlx5_fw_version_get, 787 .dev_infos_get = mlx5_dev_infos_get, 788 .rx_descriptor_status = mlx5_rx_descriptor_status, 789 .tx_descriptor_status = mlx5_tx_descriptor_status, 790 }; 791 792 /* Available operations in flow isolated mode. */ 793 const struct eth_dev_ops mlx5_dev_ops_isolate = { 794 .dev_configure = mlx5_dev_configure, 795 .dev_start = mlx5_dev_start, 796 .dev_stop = mlx5_dev_stop, 797 .dev_set_link_down = mlx5_set_link_down, 798 .dev_set_link_up = mlx5_set_link_up, 799 .dev_close = mlx5_dev_close, 800 .promiscuous_enable = mlx5_promiscuous_enable, 801 .promiscuous_disable = mlx5_promiscuous_disable, 802 .allmulticast_enable = mlx5_allmulticast_enable, 803 .allmulticast_disable = mlx5_allmulticast_disable, 804 .link_update = mlx5_link_update, 805 .stats_get = mlx5_stats_get, 806 .stats_reset = mlx5_stats_reset, 807 .xstats_get = mlx5_xstats_get, 808 .xstats_reset = mlx5_xstats_reset, 809 .xstats_get_names = mlx5_xstats_get_names, 810 .fw_version_get = mlx5_fw_version_get, 811 .dev_infos_get = mlx5_dev_infos_get, 812 .dev_supported_ptypes_get = mlx5_dev_supported_ptypes_get, 813 .vlan_filter_set = mlx5_vlan_filter_set, 814 .rx_queue_setup = mlx5_rx_queue_setup, 815 .tx_queue_setup = mlx5_tx_queue_setup, 816 .rx_queue_release = mlx5_rx_queue_release, 817 .tx_queue_release = mlx5_tx_queue_release, 818 .flow_ctrl_get = mlx5_dev_get_flow_ctrl, 819 .flow_ctrl_set = mlx5_dev_set_flow_ctrl, 820 .mac_addr_remove = mlx5_mac_addr_remove, 821 .mac_addr_add = mlx5_mac_addr_add, 822 .mac_addr_set = mlx5_mac_addr_set, 823 .set_mc_addr_list = mlx5_set_mc_addr_list, 824 .mtu_set = mlx5_dev_set_mtu, 825 .vlan_strip_queue_set = mlx5_vlan_strip_queue_set, 826 .vlan_offload_set = mlx5_vlan_offload_set, 827 .filter_ctrl = mlx5_dev_filter_ctrl, 828 .rx_descriptor_status = mlx5_rx_descriptor_status, 829 .tx_descriptor_status = mlx5_tx_descriptor_status, 830 .rx_queue_intr_enable = mlx5_rx_intr_enable, 831 .rx_queue_intr_disable = mlx5_rx_intr_disable, 832 .is_removed = mlx5_is_removed, 833 }; 834 835 /** 836 * Verify and store value for device argument. 837 * 838 * @param[in] key 839 * Key argument to verify. 840 * @param[in] val 841 * Value associated with key. 842 * @param opaque 843 * User data. 844 * 845 * @return 846 * 0 on success, a negative errno value otherwise and rte_errno is set. 847 */ 848 static int 849 mlx5_args_check(const char *key, const char *val, void *opaque) 850 { 851 struct mlx5_dev_config *config = opaque; 852 unsigned long tmp; 853 854 /* No-op, port representors are processed in mlx5_dev_spawn(). */ 855 if (!strcmp(MLX5_REPRESENTOR, key)) 856 return 0; 857 errno = 0; 858 tmp = strtoul(val, NULL, 0); 859 if (errno) { 860 rte_errno = errno; 861 DRV_LOG(WARNING, "%s: \"%s\" is not a valid integer", key, val); 862 return -rte_errno; 863 } 864 if (strcmp(MLX5_RXQ_CQE_COMP_EN, key) == 0) { 865 config->cqe_comp = !!tmp; 866 } else if (strcmp(MLX5_RXQ_CQE_PAD_EN, key) == 0) { 867 config->cqe_pad = !!tmp; 868 } else if (strcmp(MLX5_RXQ_PKT_PAD_EN, key) == 0) { 869 config->hw_padding = !!tmp; 870 } else if (strcmp(MLX5_RX_MPRQ_EN, key) == 0) { 871 config->mprq.enabled = !!tmp; 872 } else if (strcmp(MLX5_RX_MPRQ_LOG_STRIDE_NUM, key) == 0) { 873 config->mprq.stride_num_n = tmp; 874 } else if (strcmp(MLX5_RX_MPRQ_MAX_MEMCPY_LEN, key) == 0) { 875 config->mprq.max_memcpy_len = tmp; 876 } else if (strcmp(MLX5_RXQS_MIN_MPRQ, key) == 0) { 877 config->mprq.min_rxqs_num = tmp; 878 } else if (strcmp(MLX5_TXQ_INLINE, key) == 0) { 879 config->txq_inline = tmp; 880 } else if (strcmp(MLX5_TXQS_MIN_INLINE, key) == 0) { 881 config->txqs_inline = tmp; 882 } else if (strcmp(MLX5_TXQS_MAX_VEC, key) == 0) { 883 config->txqs_vec = tmp; 884 } else if (strcmp(MLX5_TXQ_MPW_EN, key) == 0) { 885 config->mps = !!tmp; 886 } else if (strcmp(MLX5_TXQ_MPW_HDR_DSEG_EN, key) == 0) { 887 config->mpw_hdr_dseg = !!tmp; 888 } else if (strcmp(MLX5_TXQ_MAX_INLINE_LEN, key) == 0) { 889 config->inline_max_packet_sz = tmp; 890 } else if (strcmp(MLX5_TX_VEC_EN, key) == 0) { 891 config->tx_vec_en = !!tmp; 892 } else if (strcmp(MLX5_RX_VEC_EN, key) == 0) { 893 config->rx_vec_en = !!tmp; 894 } else if (strcmp(MLX5_L3_VXLAN_EN, key) == 0) { 895 config->l3_vxlan_en = !!tmp; 896 } else if (strcmp(MLX5_VF_NL_EN, key) == 0) { 897 config->vf_nl_en = !!tmp; 898 } else if (strcmp(MLX5_DV_ESW_EN, key) == 0) { 899 config->dv_esw_en = !!tmp; 900 } else if (strcmp(MLX5_DV_FLOW_EN, key) == 0) { 901 config->dv_flow_en = !!tmp; 902 } else if (strcmp(MLX5_MR_EXT_MEMSEG_EN, key) == 0) { 903 config->mr_ext_memseg_en = !!tmp; 904 } else { 905 DRV_LOG(WARNING, "%s: unknown parameter", key); 906 rte_errno = EINVAL; 907 return -rte_errno; 908 } 909 return 0; 910 } 911 912 /** 913 * Parse device parameters. 914 * 915 * @param config 916 * Pointer to device configuration structure. 917 * @param devargs 918 * Device arguments structure. 919 * 920 * @return 921 * 0 on success, a negative errno value otherwise and rte_errno is set. 922 */ 923 static int 924 mlx5_args(struct mlx5_dev_config *config, struct rte_devargs *devargs) 925 { 926 const char **params = (const char *[]){ 927 MLX5_RXQ_CQE_COMP_EN, 928 MLX5_RXQ_CQE_PAD_EN, 929 MLX5_RXQ_PKT_PAD_EN, 930 MLX5_RX_MPRQ_EN, 931 MLX5_RX_MPRQ_LOG_STRIDE_NUM, 932 MLX5_RX_MPRQ_MAX_MEMCPY_LEN, 933 MLX5_RXQS_MIN_MPRQ, 934 MLX5_TXQ_INLINE, 935 MLX5_TXQS_MIN_INLINE, 936 MLX5_TXQS_MAX_VEC, 937 MLX5_TXQ_MPW_EN, 938 MLX5_TXQ_MPW_HDR_DSEG_EN, 939 MLX5_TXQ_MAX_INLINE_LEN, 940 MLX5_TX_VEC_EN, 941 MLX5_RX_VEC_EN, 942 MLX5_L3_VXLAN_EN, 943 MLX5_VF_NL_EN, 944 MLX5_DV_ESW_EN, 945 MLX5_DV_FLOW_EN, 946 MLX5_MR_EXT_MEMSEG_EN, 947 MLX5_REPRESENTOR, 948 NULL, 949 }; 950 struct rte_kvargs *kvlist; 951 int ret = 0; 952 int i; 953 954 if (devargs == NULL) 955 return 0; 956 /* Following UGLY cast is done to pass checkpatch. */ 957 kvlist = rte_kvargs_parse(devargs->args, params); 958 if (kvlist == NULL) 959 return 0; 960 /* Process parameters. */ 961 for (i = 0; (params[i] != NULL); ++i) { 962 if (rte_kvargs_count(kvlist, params[i])) { 963 ret = rte_kvargs_process(kvlist, params[i], 964 mlx5_args_check, config); 965 if (ret) { 966 rte_errno = EINVAL; 967 rte_kvargs_free(kvlist); 968 return -rte_errno; 969 } 970 } 971 } 972 rte_kvargs_free(kvlist); 973 return 0; 974 } 975 976 static struct rte_pci_driver mlx5_driver; 977 978 /** 979 * PMD global initialization. 980 * 981 * Independent from individual device, this function initializes global 982 * per-PMD data structures distinguishing primary and secondary processes. 983 * Hence, each initialization is called once per a process. 984 * 985 * @return 986 * 0 on success, a negative errno value otherwise and rte_errno is set. 987 */ 988 static int 989 mlx5_init_once(void) 990 { 991 struct mlx5_shared_data *sd; 992 struct mlx5_local_data *ld = &mlx5_local_data; 993 994 if (mlx5_init_shared_data()) 995 return -rte_errno; 996 sd = mlx5_shared_data; 997 assert(sd); 998 rte_spinlock_lock(&sd->lock); 999 switch (rte_eal_process_type()) { 1000 case RTE_PROC_PRIMARY: 1001 if (sd->init_done) 1002 break; 1003 LIST_INIT(&sd->mem_event_cb_list); 1004 rte_rwlock_init(&sd->mem_event_rwlock); 1005 rte_mem_event_callback_register("MLX5_MEM_EVENT_CB", 1006 mlx5_mr_mem_event_cb, NULL); 1007 mlx5_mp_init_primary(); 1008 sd->init_done = true; 1009 break; 1010 case RTE_PROC_SECONDARY: 1011 if (ld->init_done) 1012 break; 1013 mlx5_mp_init_secondary(); 1014 ++sd->secondary_cnt; 1015 ld->init_done = true; 1016 break; 1017 default: 1018 break; 1019 } 1020 rte_spinlock_unlock(&sd->lock); 1021 return 0; 1022 } 1023 1024 /** 1025 * Spawn an Ethernet device from Verbs information. 1026 * 1027 * @param dpdk_dev 1028 * Backing DPDK device. 1029 * @param spawn 1030 * Verbs device parameters (name, port, switch_info) to spawn. 1031 * @param config 1032 * Device configuration parameters. 1033 * 1034 * @return 1035 * A valid Ethernet device object on success, NULL otherwise and rte_errno 1036 * is set. The following errors are defined: 1037 * 1038 * EBUSY: device is not supposed to be spawned. 1039 * EEXIST: device is already spawned 1040 */ 1041 static struct rte_eth_dev * 1042 mlx5_dev_spawn(struct rte_device *dpdk_dev, 1043 struct mlx5_dev_spawn_data *spawn, 1044 struct mlx5_dev_config config) 1045 { 1046 const struct mlx5_switch_info *switch_info = &spawn->info; 1047 struct mlx5_ibv_shared *sh = NULL; 1048 struct ibv_port_attr port_attr; 1049 struct mlx5dv_context dv_attr = { .comp_mask = 0 }; 1050 struct rte_eth_dev *eth_dev = NULL; 1051 struct mlx5_priv *priv = NULL; 1052 int err = 0; 1053 unsigned int hw_padding = 0; 1054 unsigned int mps; 1055 unsigned int cqe_comp; 1056 unsigned int cqe_pad = 0; 1057 unsigned int tunnel_en = 0; 1058 unsigned int mpls_en = 0; 1059 unsigned int swp = 0; 1060 unsigned int mprq = 0; 1061 unsigned int mprq_min_stride_size_n = 0; 1062 unsigned int mprq_max_stride_size_n = 0; 1063 unsigned int mprq_min_stride_num_n = 0; 1064 unsigned int mprq_max_stride_num_n = 0; 1065 struct ether_addr mac; 1066 char name[RTE_ETH_NAME_MAX_LEN]; 1067 int own_domain_id = 0; 1068 uint16_t port_id; 1069 unsigned int i; 1070 1071 /* Determine if this port representor is supposed to be spawned. */ 1072 if (switch_info->representor && dpdk_dev->devargs) { 1073 struct rte_eth_devargs eth_da; 1074 1075 err = rte_eth_devargs_parse(dpdk_dev->devargs->args, ð_da); 1076 if (err) { 1077 rte_errno = -err; 1078 DRV_LOG(ERR, "failed to process device arguments: %s", 1079 strerror(rte_errno)); 1080 return NULL; 1081 } 1082 for (i = 0; i < eth_da.nb_representor_ports; ++i) 1083 if (eth_da.representor_ports[i] == 1084 (uint16_t)switch_info->port_name) 1085 break; 1086 if (i == eth_da.nb_representor_ports) { 1087 rte_errno = EBUSY; 1088 return NULL; 1089 } 1090 } 1091 /* Build device name. */ 1092 if (!switch_info->representor) 1093 strlcpy(name, dpdk_dev->name, sizeof(name)); 1094 else 1095 snprintf(name, sizeof(name), "%s_representor_%u", 1096 dpdk_dev->name, switch_info->port_name); 1097 /* check if the device is already spawned */ 1098 if (rte_eth_dev_get_port_by_name(name, &port_id) == 0) { 1099 rte_errno = EEXIST; 1100 return NULL; 1101 } 1102 DRV_LOG(DEBUG, "naming Ethernet device \"%s\"", name); 1103 if (rte_eal_process_type() == RTE_PROC_SECONDARY) { 1104 eth_dev = rte_eth_dev_attach_secondary(name); 1105 if (eth_dev == NULL) { 1106 DRV_LOG(ERR, "can not attach rte ethdev"); 1107 rte_errno = ENOMEM; 1108 return NULL; 1109 } 1110 eth_dev->device = dpdk_dev; 1111 eth_dev->dev_ops = &mlx5_dev_sec_ops; 1112 err = mlx5_proc_priv_init(eth_dev); 1113 if (err) 1114 return NULL; 1115 /* Receive command fd from primary process */ 1116 err = mlx5_mp_req_verbs_cmd_fd(eth_dev); 1117 if (err < 0) 1118 return NULL; 1119 /* Remap UAR for Tx queues. */ 1120 err = mlx5_tx_uar_init_secondary(eth_dev, err); 1121 if (err) 1122 return NULL; 1123 /* 1124 * Ethdev pointer is still required as input since 1125 * the primary device is not accessible from the 1126 * secondary process. 1127 */ 1128 eth_dev->rx_pkt_burst = mlx5_select_rx_function(eth_dev); 1129 eth_dev->tx_pkt_burst = mlx5_select_tx_function(eth_dev); 1130 return eth_dev; 1131 } 1132 sh = mlx5_alloc_shared_ibctx(spawn); 1133 if (!sh) 1134 return NULL; 1135 config.devx = sh->devx; 1136 #ifdef HAVE_IBV_MLX5_MOD_SWP 1137 dv_attr.comp_mask |= MLX5DV_CONTEXT_MASK_SWP; 1138 #endif 1139 /* 1140 * Multi-packet send is supported by ConnectX-4 Lx PF as well 1141 * as all ConnectX-5 devices. 1142 */ 1143 #ifdef HAVE_IBV_DEVICE_TUNNEL_SUPPORT 1144 dv_attr.comp_mask |= MLX5DV_CONTEXT_MASK_TUNNEL_OFFLOADS; 1145 #endif 1146 #ifdef HAVE_IBV_DEVICE_STRIDING_RQ_SUPPORT 1147 dv_attr.comp_mask |= MLX5DV_CONTEXT_MASK_STRIDING_RQ; 1148 #endif 1149 mlx5_glue->dv_query_device(sh->ctx, &dv_attr); 1150 if (dv_attr.flags & MLX5DV_CONTEXT_FLAGS_MPW_ALLOWED) { 1151 if (dv_attr.flags & MLX5DV_CONTEXT_FLAGS_ENHANCED_MPW) { 1152 DRV_LOG(DEBUG, "enhanced MPW is supported"); 1153 mps = MLX5_MPW_ENHANCED; 1154 } else { 1155 DRV_LOG(DEBUG, "MPW is supported"); 1156 mps = MLX5_MPW; 1157 } 1158 } else { 1159 DRV_LOG(DEBUG, "MPW isn't supported"); 1160 mps = MLX5_MPW_DISABLED; 1161 } 1162 #ifdef HAVE_IBV_MLX5_MOD_SWP 1163 if (dv_attr.comp_mask & MLX5DV_CONTEXT_MASK_SWP) 1164 swp = dv_attr.sw_parsing_caps.sw_parsing_offloads; 1165 DRV_LOG(DEBUG, "SWP support: %u", swp); 1166 #endif 1167 config.swp = !!swp; 1168 #ifdef HAVE_IBV_DEVICE_STRIDING_RQ_SUPPORT 1169 if (dv_attr.comp_mask & MLX5DV_CONTEXT_MASK_STRIDING_RQ) { 1170 struct mlx5dv_striding_rq_caps mprq_caps = 1171 dv_attr.striding_rq_caps; 1172 1173 DRV_LOG(DEBUG, "\tmin_single_stride_log_num_of_bytes: %d", 1174 mprq_caps.min_single_stride_log_num_of_bytes); 1175 DRV_LOG(DEBUG, "\tmax_single_stride_log_num_of_bytes: %d", 1176 mprq_caps.max_single_stride_log_num_of_bytes); 1177 DRV_LOG(DEBUG, "\tmin_single_wqe_log_num_of_strides: %d", 1178 mprq_caps.min_single_wqe_log_num_of_strides); 1179 DRV_LOG(DEBUG, "\tmax_single_wqe_log_num_of_strides: %d", 1180 mprq_caps.max_single_wqe_log_num_of_strides); 1181 DRV_LOG(DEBUG, "\tsupported_qpts: %d", 1182 mprq_caps.supported_qpts); 1183 DRV_LOG(DEBUG, "device supports Multi-Packet RQ"); 1184 mprq = 1; 1185 mprq_min_stride_size_n = 1186 mprq_caps.min_single_stride_log_num_of_bytes; 1187 mprq_max_stride_size_n = 1188 mprq_caps.max_single_stride_log_num_of_bytes; 1189 mprq_min_stride_num_n = 1190 mprq_caps.min_single_wqe_log_num_of_strides; 1191 mprq_max_stride_num_n = 1192 mprq_caps.max_single_wqe_log_num_of_strides; 1193 config.mprq.stride_num_n = RTE_MAX(MLX5_MPRQ_STRIDE_NUM_N, 1194 mprq_min_stride_num_n); 1195 } 1196 #endif 1197 if (RTE_CACHE_LINE_SIZE == 128 && 1198 !(dv_attr.flags & MLX5DV_CONTEXT_FLAGS_CQE_128B_COMP)) 1199 cqe_comp = 0; 1200 else 1201 cqe_comp = 1; 1202 config.cqe_comp = cqe_comp; 1203 #ifdef HAVE_IBV_MLX5_MOD_CQE_128B_PAD 1204 /* Whether device supports 128B Rx CQE padding. */ 1205 cqe_pad = RTE_CACHE_LINE_SIZE == 128 && 1206 (dv_attr.flags & MLX5DV_CONTEXT_FLAGS_CQE_128B_PAD); 1207 #endif 1208 #ifdef HAVE_IBV_DEVICE_TUNNEL_SUPPORT 1209 if (dv_attr.comp_mask & MLX5DV_CONTEXT_MASK_TUNNEL_OFFLOADS) { 1210 tunnel_en = ((dv_attr.tunnel_offloads_caps & 1211 MLX5DV_RAW_PACKET_CAP_TUNNELED_OFFLOAD_VXLAN) && 1212 (dv_attr.tunnel_offloads_caps & 1213 MLX5DV_RAW_PACKET_CAP_TUNNELED_OFFLOAD_GRE)); 1214 } 1215 DRV_LOG(DEBUG, "tunnel offloading is %ssupported", 1216 tunnel_en ? "" : "not "); 1217 #else 1218 DRV_LOG(WARNING, 1219 "tunnel offloading disabled due to old OFED/rdma-core version"); 1220 #endif 1221 config.tunnel_en = tunnel_en; 1222 #ifdef HAVE_IBV_DEVICE_MPLS_SUPPORT 1223 mpls_en = ((dv_attr.tunnel_offloads_caps & 1224 MLX5DV_RAW_PACKET_CAP_TUNNELED_OFFLOAD_CW_MPLS_OVER_GRE) && 1225 (dv_attr.tunnel_offloads_caps & 1226 MLX5DV_RAW_PACKET_CAP_TUNNELED_OFFLOAD_CW_MPLS_OVER_UDP)); 1227 DRV_LOG(DEBUG, "MPLS over GRE/UDP tunnel offloading is %ssupported", 1228 mpls_en ? "" : "not "); 1229 #else 1230 DRV_LOG(WARNING, "MPLS over GRE/UDP tunnel offloading disabled due to" 1231 " old OFED/rdma-core version or firmware configuration"); 1232 #endif 1233 config.mpls_en = mpls_en; 1234 /* Check port status. */ 1235 err = mlx5_glue->query_port(sh->ctx, spawn->ibv_port, &port_attr); 1236 if (err) { 1237 DRV_LOG(ERR, "port query failed: %s", strerror(err)); 1238 goto error; 1239 } 1240 if (port_attr.link_layer != IBV_LINK_LAYER_ETHERNET) { 1241 DRV_LOG(ERR, "port is not configured in Ethernet mode"); 1242 err = EINVAL; 1243 goto error; 1244 } 1245 if (port_attr.state != IBV_PORT_ACTIVE) 1246 DRV_LOG(DEBUG, "port is not active: \"%s\" (%d)", 1247 mlx5_glue->port_state_str(port_attr.state), 1248 port_attr.state); 1249 /* Allocate private eth device data. */ 1250 priv = rte_zmalloc("ethdev private structure", 1251 sizeof(*priv), 1252 RTE_CACHE_LINE_SIZE); 1253 if (priv == NULL) { 1254 DRV_LOG(ERR, "priv allocation failure"); 1255 err = ENOMEM; 1256 goto error; 1257 } 1258 priv->sh = sh; 1259 priv->ibv_port = spawn->ibv_port; 1260 priv->mtu = ETHER_MTU; 1261 #ifndef RTE_ARCH_64 1262 /* Initialize UAR access locks for 32bit implementations. */ 1263 rte_spinlock_init(&priv->uar_lock_cq); 1264 for (i = 0; i < MLX5_UAR_PAGE_NUM_MAX; i++) 1265 rte_spinlock_init(&priv->uar_lock[i]); 1266 #endif 1267 /* Some internal functions rely on Netlink sockets, open them now. */ 1268 priv->nl_socket_rdma = mlx5_nl_init(NETLINK_RDMA); 1269 priv->nl_socket_route = mlx5_nl_init(NETLINK_ROUTE); 1270 priv->nl_sn = 0; 1271 priv->representor = !!switch_info->representor; 1272 priv->master = !!switch_info->master; 1273 priv->domain_id = RTE_ETH_DEV_SWITCH_DOMAIN_ID_INVALID; 1274 /* 1275 * Currently we support single E-Switch per PF configurations 1276 * only and vport_id field contains the vport index for 1277 * associated VF, which is deduced from representor port name. 1278 * For example, let's have the IB device port 10, it has 1279 * attached network device eth0, which has port name attribute 1280 * pf0vf2, we can deduce the VF number as 2, and set vport index 1281 * as 3 (2+1). This assigning schema should be changed if the 1282 * multiple E-Switch instances per PF configurations or/and PCI 1283 * subfunctions are added. 1284 */ 1285 priv->vport_id = switch_info->representor ? 1286 switch_info->port_name + 1 : -1; 1287 /* representor_id field keeps the unmodified port/VF index. */ 1288 priv->representor_id = switch_info->representor ? 1289 switch_info->port_name : -1; 1290 /* 1291 * Look for sibling devices in order to reuse their switch domain 1292 * if any, otherwise allocate one. 1293 */ 1294 RTE_ETH_FOREACH_DEV_OF(port_id, dpdk_dev) { 1295 const struct mlx5_priv *opriv = 1296 rte_eth_devices[port_id].data->dev_private; 1297 1298 if (!opriv || 1299 opriv->domain_id == 1300 RTE_ETH_DEV_SWITCH_DOMAIN_ID_INVALID) 1301 continue; 1302 priv->domain_id = opriv->domain_id; 1303 break; 1304 } 1305 if (priv->domain_id == RTE_ETH_DEV_SWITCH_DOMAIN_ID_INVALID) { 1306 err = rte_eth_switch_domain_alloc(&priv->domain_id); 1307 if (err) { 1308 err = rte_errno; 1309 DRV_LOG(ERR, "unable to allocate switch domain: %s", 1310 strerror(rte_errno)); 1311 goto error; 1312 } 1313 own_domain_id = 1; 1314 } 1315 err = mlx5_args(&config, dpdk_dev->devargs); 1316 if (err) { 1317 err = rte_errno; 1318 DRV_LOG(ERR, "failed to process device arguments: %s", 1319 strerror(rte_errno)); 1320 goto error; 1321 } 1322 config.hw_csum = !!(sh->device_attr.device_cap_flags_ex & 1323 IBV_DEVICE_RAW_IP_CSUM); 1324 DRV_LOG(DEBUG, "checksum offloading is %ssupported", 1325 (config.hw_csum ? "" : "not ")); 1326 #if !defined(HAVE_IBV_DEVICE_COUNTERS_SET_V42) && \ 1327 !defined(HAVE_IBV_DEVICE_COUNTERS_SET_V45) 1328 DRV_LOG(DEBUG, "counters are not supported"); 1329 #endif 1330 #ifndef HAVE_IBV_FLOW_DV_SUPPORT 1331 if (config.dv_flow_en) { 1332 DRV_LOG(WARNING, "DV flow is not supported"); 1333 config.dv_flow_en = 0; 1334 } 1335 #endif 1336 config.ind_table_max_size = 1337 sh->device_attr.rss_caps.max_rwq_indirection_table_size; 1338 /* 1339 * Remove this check once DPDK supports larger/variable 1340 * indirection tables. 1341 */ 1342 if (config.ind_table_max_size > (unsigned int)ETH_RSS_RETA_SIZE_512) 1343 config.ind_table_max_size = ETH_RSS_RETA_SIZE_512; 1344 DRV_LOG(DEBUG, "maximum Rx indirection table size is %u", 1345 config.ind_table_max_size); 1346 config.hw_vlan_strip = !!(sh->device_attr.raw_packet_caps & 1347 IBV_RAW_PACKET_CAP_CVLAN_STRIPPING); 1348 DRV_LOG(DEBUG, "VLAN stripping is %ssupported", 1349 (config.hw_vlan_strip ? "" : "not ")); 1350 config.hw_fcs_strip = !!(sh->device_attr.raw_packet_caps & 1351 IBV_RAW_PACKET_CAP_SCATTER_FCS); 1352 DRV_LOG(DEBUG, "FCS stripping configuration is %ssupported", 1353 (config.hw_fcs_strip ? "" : "not ")); 1354 #if defined(HAVE_IBV_WQ_FLAG_RX_END_PADDING) 1355 hw_padding = !!sh->device_attr.rx_pad_end_addr_align; 1356 #elif defined(HAVE_IBV_WQ_FLAGS_PCI_WRITE_END_PADDING) 1357 hw_padding = !!(sh->device_attr.device_cap_flags_ex & 1358 IBV_DEVICE_PCI_WRITE_END_PADDING); 1359 #endif 1360 if (config.hw_padding && !hw_padding) { 1361 DRV_LOG(DEBUG, "Rx end alignment padding isn't supported"); 1362 config.hw_padding = 0; 1363 } else if (config.hw_padding) { 1364 DRV_LOG(DEBUG, "Rx end alignment padding is enabled"); 1365 } 1366 config.tso = (sh->device_attr.tso_caps.max_tso > 0 && 1367 (sh->device_attr.tso_caps.supported_qpts & 1368 (1 << IBV_QPT_RAW_PACKET))); 1369 if (config.tso) 1370 config.tso_max_payload_sz = sh->device_attr.tso_caps.max_tso; 1371 /* 1372 * MPW is disabled by default, while the Enhanced MPW is enabled 1373 * by default. 1374 */ 1375 if (config.mps == MLX5_ARG_UNSET) 1376 config.mps = (mps == MLX5_MPW_ENHANCED) ? MLX5_MPW_ENHANCED : 1377 MLX5_MPW_DISABLED; 1378 else 1379 config.mps = config.mps ? mps : MLX5_MPW_DISABLED; 1380 DRV_LOG(INFO, "%sMPS is %s", 1381 config.mps == MLX5_MPW_ENHANCED ? "enhanced " : "", 1382 config.mps != MLX5_MPW_DISABLED ? "enabled" : "disabled"); 1383 if (config.cqe_comp && !cqe_comp) { 1384 DRV_LOG(WARNING, "Rx CQE compression isn't supported"); 1385 config.cqe_comp = 0; 1386 } 1387 if (config.cqe_pad && !cqe_pad) { 1388 DRV_LOG(WARNING, "Rx CQE padding isn't supported"); 1389 config.cqe_pad = 0; 1390 } else if (config.cqe_pad) { 1391 DRV_LOG(INFO, "Rx CQE padding is enabled"); 1392 } 1393 if (config.mprq.enabled && mprq) { 1394 if (config.mprq.stride_num_n > mprq_max_stride_num_n || 1395 config.mprq.stride_num_n < mprq_min_stride_num_n) { 1396 config.mprq.stride_num_n = 1397 RTE_MAX(MLX5_MPRQ_STRIDE_NUM_N, 1398 mprq_min_stride_num_n); 1399 DRV_LOG(WARNING, 1400 "the number of strides" 1401 " for Multi-Packet RQ is out of range," 1402 " setting default value (%u)", 1403 1 << config.mprq.stride_num_n); 1404 } 1405 config.mprq.min_stride_size_n = mprq_min_stride_size_n; 1406 config.mprq.max_stride_size_n = mprq_max_stride_size_n; 1407 } else if (config.mprq.enabled && !mprq) { 1408 DRV_LOG(WARNING, "Multi-Packet RQ isn't supported"); 1409 config.mprq.enabled = 0; 1410 } 1411 eth_dev = rte_eth_dev_allocate(name); 1412 if (eth_dev == NULL) { 1413 DRV_LOG(ERR, "can not allocate rte ethdev"); 1414 err = ENOMEM; 1415 goto error; 1416 } 1417 /* Flag to call rte_eth_dev_release_port() in rte_eth_dev_close(). */ 1418 eth_dev->data->dev_flags |= RTE_ETH_DEV_CLOSE_REMOVE; 1419 if (priv->representor) { 1420 eth_dev->data->dev_flags |= RTE_ETH_DEV_REPRESENTOR; 1421 eth_dev->data->representor_id = priv->representor_id; 1422 } 1423 eth_dev->data->dev_private = priv; 1424 priv->dev_data = eth_dev->data; 1425 eth_dev->data->mac_addrs = priv->mac; 1426 eth_dev->device = dpdk_dev; 1427 /* Configure the first MAC address by default. */ 1428 if (mlx5_get_mac(eth_dev, &mac.addr_bytes)) { 1429 DRV_LOG(ERR, 1430 "port %u cannot get MAC address, is mlx5_en" 1431 " loaded? (errno: %s)", 1432 eth_dev->data->port_id, strerror(rte_errno)); 1433 err = ENODEV; 1434 goto error; 1435 } 1436 DRV_LOG(INFO, 1437 "port %u MAC address is %02x:%02x:%02x:%02x:%02x:%02x", 1438 eth_dev->data->port_id, 1439 mac.addr_bytes[0], mac.addr_bytes[1], 1440 mac.addr_bytes[2], mac.addr_bytes[3], 1441 mac.addr_bytes[4], mac.addr_bytes[5]); 1442 #ifndef NDEBUG 1443 { 1444 char ifname[IF_NAMESIZE]; 1445 1446 if (mlx5_get_ifname(eth_dev, &ifname) == 0) 1447 DRV_LOG(DEBUG, "port %u ifname is \"%s\"", 1448 eth_dev->data->port_id, ifname); 1449 else 1450 DRV_LOG(DEBUG, "port %u ifname is unknown", 1451 eth_dev->data->port_id); 1452 } 1453 #endif 1454 /* Get actual MTU if possible. */ 1455 err = mlx5_get_mtu(eth_dev, &priv->mtu); 1456 if (err) { 1457 err = rte_errno; 1458 goto error; 1459 } 1460 DRV_LOG(DEBUG, "port %u MTU is %u", eth_dev->data->port_id, 1461 priv->mtu); 1462 /* Initialize burst functions to prevent crashes before link-up. */ 1463 eth_dev->rx_pkt_burst = removed_rx_burst; 1464 eth_dev->tx_pkt_burst = removed_tx_burst; 1465 eth_dev->dev_ops = &mlx5_dev_ops; 1466 /* Register MAC address. */ 1467 claim_zero(mlx5_mac_addr_add(eth_dev, &mac, 0, 0)); 1468 if (config.vf && config.vf_nl_en) 1469 mlx5_nl_mac_addr_sync(eth_dev); 1470 priv->tcf_context = mlx5_flow_tcf_context_create(); 1471 if (!priv->tcf_context) { 1472 err = -rte_errno; 1473 DRV_LOG(WARNING, 1474 "flow rules relying on switch offloads will not be" 1475 " supported: cannot open libmnl socket: %s", 1476 strerror(rte_errno)); 1477 } else { 1478 struct rte_flow_error error; 1479 unsigned int ifindex = mlx5_ifindex(eth_dev); 1480 1481 if (!ifindex) { 1482 err = -rte_errno; 1483 error.message = 1484 "cannot retrieve network interface index"; 1485 } else { 1486 err = mlx5_flow_tcf_init(priv->tcf_context, 1487 ifindex, &error); 1488 } 1489 if (err) { 1490 DRV_LOG(WARNING, 1491 "flow rules relying on switch offloads will" 1492 " not be supported: %s: %s", 1493 error.message, strerror(rte_errno)); 1494 mlx5_flow_tcf_context_destroy(priv->tcf_context); 1495 priv->tcf_context = NULL; 1496 } 1497 } 1498 TAILQ_INIT(&priv->flows); 1499 TAILQ_INIT(&priv->ctrl_flows); 1500 /* Hint libmlx5 to use PMD allocator for data plane resources */ 1501 struct mlx5dv_ctx_allocators alctr = { 1502 .alloc = &mlx5_alloc_verbs_buf, 1503 .free = &mlx5_free_verbs_buf, 1504 .data = priv, 1505 }; 1506 mlx5_glue->dv_set_context_attr(sh->ctx, 1507 MLX5DV_CTX_ATTR_BUF_ALLOCATORS, 1508 (void *)((uintptr_t)&alctr)); 1509 /* Bring Ethernet device up. */ 1510 DRV_LOG(DEBUG, "port %u forcing Ethernet interface up", 1511 eth_dev->data->port_id); 1512 mlx5_set_link_up(eth_dev); 1513 /* 1514 * Even though the interrupt handler is not installed yet, 1515 * interrupts will still trigger on the async_fd from 1516 * Verbs context returned by ibv_open_device(). 1517 */ 1518 mlx5_link_update(eth_dev, 0); 1519 #ifdef HAVE_IBV_DEVX_OBJ 1520 err = mlx5_devx_cmd_query_hca_attr(sh->ctx, &config.hca_attr); 1521 if (err) { 1522 err = -err; 1523 goto error; 1524 } 1525 #endif 1526 #ifdef HAVE_MLX5DV_DR_ESWITCH 1527 if (!(config.hca_attr.eswitch_manager && config.dv_flow_en && 1528 (switch_info->representor || switch_info->master))) 1529 config.dv_esw_en = 0; 1530 #else 1531 config.dv_esw_en = 0; 1532 #endif 1533 /* Store device configuration on private structure. */ 1534 priv->config = config; 1535 if (config.dv_flow_en) { 1536 err = mlx5_alloc_shared_dr(priv); 1537 if (err) 1538 goto error; 1539 } 1540 /* Supported Verbs flow priority number detection. */ 1541 err = mlx5_flow_discover_priorities(eth_dev); 1542 if (err < 0) { 1543 err = -err; 1544 goto error; 1545 } 1546 priv->config.flow_prio = err; 1547 /* 1548 * Once the device is added to the list of memory event 1549 * callback, its global MR cache table cannot be expanded 1550 * on the fly because of deadlock. If it overflows, lookup 1551 * should be done by searching MR list linearly, which is slow. 1552 */ 1553 err = mlx5_mr_btree_init(&priv->mr.cache, 1554 MLX5_MR_BTREE_CACHE_N * 2, 1555 eth_dev->device->numa_node); 1556 if (err) { 1557 err = rte_errno; 1558 goto error; 1559 } 1560 /* Add device to memory callback list. */ 1561 rte_rwlock_write_lock(&mlx5_shared_data->mem_event_rwlock); 1562 LIST_INSERT_HEAD(&mlx5_shared_data->mem_event_cb_list, 1563 priv, mem_event_cb); 1564 rte_rwlock_write_unlock(&mlx5_shared_data->mem_event_rwlock); 1565 return eth_dev; 1566 error: 1567 if (priv) { 1568 if (priv->sh) 1569 mlx5_free_shared_dr(priv); 1570 if (priv->nl_socket_route >= 0) 1571 close(priv->nl_socket_route); 1572 if (priv->nl_socket_rdma >= 0) 1573 close(priv->nl_socket_rdma); 1574 if (priv->tcf_context) 1575 mlx5_flow_tcf_context_destroy(priv->tcf_context); 1576 if (own_domain_id) 1577 claim_zero(rte_eth_switch_domain_free(priv->domain_id)); 1578 rte_free(priv); 1579 if (eth_dev != NULL) 1580 eth_dev->data->dev_private = NULL; 1581 } 1582 if (eth_dev != NULL) { 1583 /* mac_addrs must not be freed alone because part of dev_private */ 1584 eth_dev->data->mac_addrs = NULL; 1585 rte_eth_dev_release_port(eth_dev); 1586 } 1587 if (sh) 1588 mlx5_free_shared_ibctx(sh); 1589 assert(err > 0); 1590 rte_errno = err; 1591 return NULL; 1592 } 1593 1594 /** 1595 * Comparison callback to sort device data. 1596 * 1597 * This is meant to be used with qsort(). 1598 * 1599 * @param a[in] 1600 * Pointer to pointer to first data object. 1601 * @param b[in] 1602 * Pointer to pointer to second data object. 1603 * 1604 * @return 1605 * 0 if both objects are equal, less than 0 if the first argument is less 1606 * than the second, greater than 0 otherwise. 1607 */ 1608 static int 1609 mlx5_dev_spawn_data_cmp(const void *a, const void *b) 1610 { 1611 const struct mlx5_switch_info *si_a = 1612 &((const struct mlx5_dev_spawn_data *)a)->info; 1613 const struct mlx5_switch_info *si_b = 1614 &((const struct mlx5_dev_spawn_data *)b)->info; 1615 int ret; 1616 1617 /* Master device first. */ 1618 ret = si_b->master - si_a->master; 1619 if (ret) 1620 return ret; 1621 /* Then representor devices. */ 1622 ret = si_b->representor - si_a->representor; 1623 if (ret) 1624 return ret; 1625 /* Unidentified devices come last in no specific order. */ 1626 if (!si_a->representor) 1627 return 0; 1628 /* Order representors by name. */ 1629 return si_a->port_name - si_b->port_name; 1630 } 1631 1632 /** 1633 * DPDK callback to register a PCI device. 1634 * 1635 * This function spawns Ethernet devices out of a given PCI device. 1636 * 1637 * @param[in] pci_drv 1638 * PCI driver structure (mlx5_driver). 1639 * @param[in] pci_dev 1640 * PCI device information. 1641 * 1642 * @return 1643 * 0 on success, a negative errno value otherwise and rte_errno is set. 1644 */ 1645 static int 1646 mlx5_pci_probe(struct rte_pci_driver *pci_drv __rte_unused, 1647 struct rte_pci_device *pci_dev) 1648 { 1649 struct ibv_device **ibv_list; 1650 /* 1651 * Number of found IB Devices matching with requested PCI BDF. 1652 * nd != 1 means there are multiple IB devices over the same 1653 * PCI device and we have representors and master. 1654 */ 1655 unsigned int nd = 0; 1656 /* 1657 * Number of found IB device Ports. nd = 1 and np = 1..n means 1658 * we have the single multiport IB device, and there may be 1659 * representors attached to some of found ports. 1660 */ 1661 unsigned int np = 0; 1662 /* 1663 * Number of DPDK ethernet devices to Spawn - either over 1664 * multiple IB devices or multiple ports of single IB device. 1665 * Actually this is the number of iterations to spawn. 1666 */ 1667 unsigned int ns = 0; 1668 struct mlx5_dev_config dev_config; 1669 int ret; 1670 1671 ret = mlx5_init_once(); 1672 if (ret) { 1673 DRV_LOG(ERR, "unable to init PMD global data: %s", 1674 strerror(rte_errno)); 1675 return -rte_errno; 1676 } 1677 assert(pci_drv == &mlx5_driver); 1678 errno = 0; 1679 ibv_list = mlx5_glue->get_device_list(&ret); 1680 if (!ibv_list) { 1681 rte_errno = errno ? errno : ENOSYS; 1682 DRV_LOG(ERR, "cannot list devices, is ib_uverbs loaded?"); 1683 return -rte_errno; 1684 } 1685 /* 1686 * First scan the list of all Infiniband devices to find 1687 * matching ones, gathering into the list. 1688 */ 1689 struct ibv_device *ibv_match[ret + 1]; 1690 int nl_route = -1; 1691 int nl_rdma = -1; 1692 unsigned int i; 1693 1694 while (ret-- > 0) { 1695 struct rte_pci_addr pci_addr; 1696 1697 DRV_LOG(DEBUG, "checking device \"%s\"", ibv_list[ret]->name); 1698 if (mlx5_ibv_device_to_pci_addr(ibv_list[ret], &pci_addr)) 1699 continue; 1700 if (pci_dev->addr.domain != pci_addr.domain || 1701 pci_dev->addr.bus != pci_addr.bus || 1702 pci_dev->addr.devid != pci_addr.devid || 1703 pci_dev->addr.function != pci_addr.function) 1704 continue; 1705 DRV_LOG(INFO, "PCI information matches for device \"%s\"", 1706 ibv_list[ret]->name); 1707 ibv_match[nd++] = ibv_list[ret]; 1708 } 1709 ibv_match[nd] = NULL; 1710 if (!nd) { 1711 /* No device matches, just complain and bail out. */ 1712 mlx5_glue->free_device_list(ibv_list); 1713 DRV_LOG(WARNING, 1714 "no Verbs device matches PCI device " PCI_PRI_FMT "," 1715 " are kernel drivers loaded?", 1716 pci_dev->addr.domain, pci_dev->addr.bus, 1717 pci_dev->addr.devid, pci_dev->addr.function); 1718 rte_errno = ENOENT; 1719 ret = -rte_errno; 1720 return ret; 1721 } 1722 nl_route = mlx5_nl_init(NETLINK_ROUTE); 1723 nl_rdma = mlx5_nl_init(NETLINK_RDMA); 1724 if (nd == 1) { 1725 /* 1726 * Found single matching device may have multiple ports. 1727 * Each port may be representor, we have to check the port 1728 * number and check the representors existence. 1729 */ 1730 if (nl_rdma >= 0) 1731 np = mlx5_nl_portnum(nl_rdma, ibv_match[0]->name); 1732 if (!np) 1733 DRV_LOG(WARNING, "can not get IB device \"%s\"" 1734 " ports number", ibv_match[0]->name); 1735 } 1736 /* 1737 * Now we can determine the maximal 1738 * amount of devices to be spawned. 1739 */ 1740 struct mlx5_dev_spawn_data list[np ? np : nd]; 1741 1742 if (np > 1) { 1743 /* 1744 * Single IB device with multiple ports found, 1745 * it may be E-Switch master device and representors. 1746 * We have to perform identification trough the ports. 1747 */ 1748 assert(nl_rdma >= 0); 1749 assert(ns == 0); 1750 assert(nd == 1); 1751 for (i = 1; i <= np; ++i) { 1752 list[ns].max_port = np; 1753 list[ns].ibv_port = i; 1754 list[ns].ibv_dev = ibv_match[0]; 1755 list[ns].eth_dev = NULL; 1756 list[ns].ifindex = mlx5_nl_ifindex 1757 (nl_rdma, list[ns].ibv_dev->name, i); 1758 if (!list[ns].ifindex) { 1759 /* 1760 * No network interface index found for the 1761 * specified port, it means there is no 1762 * representor on this port. It's OK, 1763 * there can be disabled ports, for example 1764 * if sriov_numvfs < sriov_totalvfs. 1765 */ 1766 continue; 1767 } 1768 ret = -1; 1769 if (nl_route >= 0) 1770 ret = mlx5_nl_switch_info 1771 (nl_route, 1772 list[ns].ifindex, 1773 &list[ns].info); 1774 if (ret || (!list[ns].info.representor && 1775 !list[ns].info.master)) { 1776 /* 1777 * We failed to recognize representors with 1778 * Netlink, let's try to perform the task 1779 * with sysfs. 1780 */ 1781 ret = mlx5_sysfs_switch_info 1782 (list[ns].ifindex, 1783 &list[ns].info); 1784 } 1785 if (!ret && (list[ns].info.representor ^ 1786 list[ns].info.master)) 1787 ns++; 1788 } 1789 if (!ns) { 1790 DRV_LOG(ERR, 1791 "unable to recognize master/representors" 1792 " on the IB device with multiple ports"); 1793 rte_errno = ENOENT; 1794 ret = -rte_errno; 1795 goto exit; 1796 } 1797 } else { 1798 /* 1799 * The existence of several matching entries (nd > 1) means 1800 * port representors have been instantiated. No existing Verbs 1801 * call nor sysfs entries can tell them apart, this can only 1802 * be done through Netlink calls assuming kernel drivers are 1803 * recent enough to support them. 1804 * 1805 * In the event of identification failure through Netlink, 1806 * try again through sysfs, then: 1807 * 1808 * 1. A single IB device matches (nd == 1) with single 1809 * port (np=0/1) and is not a representor, assume 1810 * no switch support. 1811 * 1812 * 2. Otherwise no safe assumptions can be made; 1813 * complain louder and bail out. 1814 */ 1815 np = 1; 1816 for (i = 0; i != nd; ++i) { 1817 memset(&list[ns].info, 0, sizeof(list[ns].info)); 1818 list[ns].max_port = 1; 1819 list[ns].ibv_port = 1; 1820 list[ns].ibv_dev = ibv_match[i]; 1821 list[ns].eth_dev = NULL; 1822 list[ns].ifindex = 0; 1823 if (nl_rdma >= 0) 1824 list[ns].ifindex = mlx5_nl_ifindex 1825 (nl_rdma, list[ns].ibv_dev->name, 1); 1826 if (!list[ns].ifindex) { 1827 char ifname[IF_NAMESIZE]; 1828 1829 /* 1830 * Netlink failed, it may happen with old 1831 * ib_core kernel driver (before 4.16). 1832 * We can assume there is old driver because 1833 * here we are processing single ports IB 1834 * devices. Let's try sysfs to retrieve 1835 * the ifindex. The method works for 1836 * master device only. 1837 */ 1838 if (nd > 1) { 1839 /* 1840 * Multiple devices found, assume 1841 * representors, can not distinguish 1842 * master/representor and retrieve 1843 * ifindex via sysfs. 1844 */ 1845 continue; 1846 } 1847 ret = mlx5_get_master_ifname 1848 (ibv_match[i]->ibdev_path, &ifname); 1849 if (!ret) 1850 list[ns].ifindex = 1851 if_nametoindex(ifname); 1852 if (!list[ns].ifindex) { 1853 /* 1854 * No network interface index found 1855 * for the specified device, it means 1856 * there it is neither representor 1857 * nor master. 1858 */ 1859 continue; 1860 } 1861 } 1862 ret = -1; 1863 if (nl_route >= 0) 1864 ret = mlx5_nl_switch_info 1865 (nl_route, 1866 list[ns].ifindex, 1867 &list[ns].info); 1868 if (ret || (!list[ns].info.representor && 1869 !list[ns].info.master)) { 1870 /* 1871 * We failed to recognize representors with 1872 * Netlink, let's try to perform the task 1873 * with sysfs. 1874 */ 1875 ret = mlx5_sysfs_switch_info 1876 (list[ns].ifindex, 1877 &list[ns].info); 1878 } 1879 if (!ret && (list[ns].info.representor ^ 1880 list[ns].info.master)) { 1881 ns++; 1882 } else if ((nd == 1) && 1883 !list[ns].info.representor && 1884 !list[ns].info.master) { 1885 /* 1886 * Single IB device with 1887 * one physical port and 1888 * attached network device. 1889 * May be SRIOV is not enabled 1890 * or there is no representors. 1891 */ 1892 DRV_LOG(INFO, "no E-Switch support detected"); 1893 ns++; 1894 break; 1895 } 1896 } 1897 if (!ns) { 1898 DRV_LOG(ERR, 1899 "unable to recognize master/representors" 1900 " on the multiple IB devices"); 1901 rte_errno = ENOENT; 1902 ret = -rte_errno; 1903 goto exit; 1904 } 1905 } 1906 assert(ns); 1907 /* 1908 * Sort list to probe devices in natural order for users convenience 1909 * (i.e. master first, then representors from lowest to highest ID). 1910 */ 1911 qsort(list, ns, sizeof(*list), mlx5_dev_spawn_data_cmp); 1912 /* Default configuration. */ 1913 dev_config = (struct mlx5_dev_config){ 1914 .hw_padding = 0, 1915 .mps = MLX5_ARG_UNSET, 1916 .tx_vec_en = 1, 1917 .rx_vec_en = 1, 1918 .txq_inline = MLX5_ARG_UNSET, 1919 .txqs_inline = MLX5_ARG_UNSET, 1920 .txqs_vec = MLX5_ARG_UNSET, 1921 .inline_max_packet_sz = MLX5_ARG_UNSET, 1922 .vf_nl_en = 1, 1923 .mr_ext_memseg_en = 1, 1924 .mprq = { 1925 .enabled = 0, /* Disabled by default. */ 1926 .stride_num_n = MLX5_MPRQ_STRIDE_NUM_N, 1927 .max_memcpy_len = MLX5_MPRQ_MEMCPY_DEFAULT_LEN, 1928 .min_rxqs_num = MLX5_MPRQ_MIN_RXQS, 1929 }, 1930 .dv_esw_en = 1, 1931 }; 1932 /* Device specific configuration. */ 1933 switch (pci_dev->id.device_id) { 1934 case PCI_DEVICE_ID_MELLANOX_CONNECTX5BF: 1935 dev_config.txqs_vec = MLX5_VPMD_MAX_TXQS_BLUEFIELD; 1936 break; 1937 case PCI_DEVICE_ID_MELLANOX_CONNECTX4VF: 1938 case PCI_DEVICE_ID_MELLANOX_CONNECTX4LXVF: 1939 case PCI_DEVICE_ID_MELLANOX_CONNECTX5VF: 1940 case PCI_DEVICE_ID_MELLANOX_CONNECTX5EXVF: 1941 dev_config.vf = 1; 1942 break; 1943 default: 1944 break; 1945 } 1946 /* Set architecture-dependent default value if unset. */ 1947 if (dev_config.txqs_vec == MLX5_ARG_UNSET) 1948 dev_config.txqs_vec = MLX5_VPMD_MAX_TXQS; 1949 for (i = 0; i != ns; ++i) { 1950 uint32_t restore; 1951 1952 list[i].eth_dev = mlx5_dev_spawn(&pci_dev->device, 1953 &list[i], 1954 dev_config); 1955 if (!list[i].eth_dev) { 1956 if (rte_errno != EBUSY && rte_errno != EEXIST) 1957 break; 1958 /* Device is disabled or already spawned. Ignore it. */ 1959 continue; 1960 } 1961 restore = list[i].eth_dev->data->dev_flags; 1962 rte_eth_copy_pci_info(list[i].eth_dev, pci_dev); 1963 /* Restore non-PCI flags cleared by the above call. */ 1964 list[i].eth_dev->data->dev_flags |= restore; 1965 rte_eth_dev_probing_finish(list[i].eth_dev); 1966 } 1967 if (i != ns) { 1968 DRV_LOG(ERR, 1969 "probe of PCI device " PCI_PRI_FMT " aborted after" 1970 " encountering an error: %s", 1971 pci_dev->addr.domain, pci_dev->addr.bus, 1972 pci_dev->addr.devid, pci_dev->addr.function, 1973 strerror(rte_errno)); 1974 ret = -rte_errno; 1975 /* Roll back. */ 1976 while (i--) { 1977 if (!list[i].eth_dev) 1978 continue; 1979 mlx5_dev_close(list[i].eth_dev); 1980 /* mac_addrs must not be freed because in dev_private */ 1981 list[i].eth_dev->data->mac_addrs = NULL; 1982 claim_zero(rte_eth_dev_release_port(list[i].eth_dev)); 1983 } 1984 /* Restore original error. */ 1985 rte_errno = -ret; 1986 } else { 1987 ret = 0; 1988 } 1989 exit: 1990 /* 1991 * Do the routine cleanup: 1992 * - close opened Netlink sockets 1993 * - free the Infiniband device list 1994 */ 1995 if (nl_rdma >= 0) 1996 close(nl_rdma); 1997 if (nl_route >= 0) 1998 close(nl_route); 1999 assert(ibv_list); 2000 mlx5_glue->free_device_list(ibv_list); 2001 return ret; 2002 } 2003 2004 /** 2005 * DPDK callback to remove a PCI device. 2006 * 2007 * This function removes all Ethernet devices belong to a given PCI device. 2008 * 2009 * @param[in] pci_dev 2010 * Pointer to the PCI device. 2011 * 2012 * @return 2013 * 0 on success, the function cannot fail. 2014 */ 2015 static int 2016 mlx5_pci_remove(struct rte_pci_device *pci_dev) 2017 { 2018 uint16_t port_id; 2019 2020 RTE_ETH_FOREACH_DEV_OF(port_id, &pci_dev->device) 2021 rte_eth_dev_close(port_id); 2022 return 0; 2023 } 2024 2025 static const struct rte_pci_id mlx5_pci_id_map[] = { 2026 { 2027 RTE_PCI_DEVICE(PCI_VENDOR_ID_MELLANOX, 2028 PCI_DEVICE_ID_MELLANOX_CONNECTX4) 2029 }, 2030 { 2031 RTE_PCI_DEVICE(PCI_VENDOR_ID_MELLANOX, 2032 PCI_DEVICE_ID_MELLANOX_CONNECTX4VF) 2033 }, 2034 { 2035 RTE_PCI_DEVICE(PCI_VENDOR_ID_MELLANOX, 2036 PCI_DEVICE_ID_MELLANOX_CONNECTX4LX) 2037 }, 2038 { 2039 RTE_PCI_DEVICE(PCI_VENDOR_ID_MELLANOX, 2040 PCI_DEVICE_ID_MELLANOX_CONNECTX4LXVF) 2041 }, 2042 { 2043 RTE_PCI_DEVICE(PCI_VENDOR_ID_MELLANOX, 2044 PCI_DEVICE_ID_MELLANOX_CONNECTX5) 2045 }, 2046 { 2047 RTE_PCI_DEVICE(PCI_VENDOR_ID_MELLANOX, 2048 PCI_DEVICE_ID_MELLANOX_CONNECTX5VF) 2049 }, 2050 { 2051 RTE_PCI_DEVICE(PCI_VENDOR_ID_MELLANOX, 2052 PCI_DEVICE_ID_MELLANOX_CONNECTX5EX) 2053 }, 2054 { 2055 RTE_PCI_DEVICE(PCI_VENDOR_ID_MELLANOX, 2056 PCI_DEVICE_ID_MELLANOX_CONNECTX5EXVF) 2057 }, 2058 { 2059 RTE_PCI_DEVICE(PCI_VENDOR_ID_MELLANOX, 2060 PCI_DEVICE_ID_MELLANOX_CONNECTX5BF) 2061 }, 2062 { 2063 RTE_PCI_DEVICE(PCI_VENDOR_ID_MELLANOX, 2064 PCI_DEVICE_ID_MELLANOX_CONNECTX5BFVF) 2065 }, 2066 { 2067 RTE_PCI_DEVICE(PCI_VENDOR_ID_MELLANOX, 2068 PCI_DEVICE_ID_MELLANOX_CONNECTX6) 2069 }, 2070 { 2071 RTE_PCI_DEVICE(PCI_VENDOR_ID_MELLANOX, 2072 PCI_DEVICE_ID_MELLANOX_CONNECTX6VF) 2073 }, 2074 { 2075 .vendor_id = 0 2076 } 2077 }; 2078 2079 static struct rte_pci_driver mlx5_driver = { 2080 .driver = { 2081 .name = MLX5_DRIVER_NAME 2082 }, 2083 .id_table = mlx5_pci_id_map, 2084 .probe = mlx5_pci_probe, 2085 .remove = mlx5_pci_remove, 2086 .dma_map = mlx5_dma_map, 2087 .dma_unmap = mlx5_dma_unmap, 2088 .drv_flags = (RTE_PCI_DRV_INTR_LSC | RTE_PCI_DRV_INTR_RMV | 2089 RTE_PCI_DRV_PROBE_AGAIN), 2090 }; 2091 2092 #ifdef RTE_IBVERBS_LINK_DLOPEN 2093 2094 /** 2095 * Suffix RTE_EAL_PMD_PATH with "-glue". 2096 * 2097 * This function performs a sanity check on RTE_EAL_PMD_PATH before 2098 * suffixing its last component. 2099 * 2100 * @param buf[out] 2101 * Output buffer, should be large enough otherwise NULL is returned. 2102 * @param size 2103 * Size of @p out. 2104 * 2105 * @return 2106 * Pointer to @p buf or @p NULL in case suffix cannot be appended. 2107 */ 2108 static char * 2109 mlx5_glue_path(char *buf, size_t size) 2110 { 2111 static const char *const bad[] = { "/", ".", "..", NULL }; 2112 const char *path = RTE_EAL_PMD_PATH; 2113 size_t len = strlen(path); 2114 size_t off; 2115 int i; 2116 2117 while (len && path[len - 1] == '/') 2118 --len; 2119 for (off = len; off && path[off - 1] != '/'; --off) 2120 ; 2121 for (i = 0; bad[i]; ++i) 2122 if (!strncmp(path + off, bad[i], (int)(len - off))) 2123 goto error; 2124 i = snprintf(buf, size, "%.*s-glue", (int)len, path); 2125 if (i == -1 || (size_t)i >= size) 2126 goto error; 2127 return buf; 2128 error: 2129 DRV_LOG(ERR, 2130 "unable to append \"-glue\" to last component of" 2131 " RTE_EAL_PMD_PATH (\"" RTE_EAL_PMD_PATH "\")," 2132 " please re-configure DPDK"); 2133 return NULL; 2134 } 2135 2136 /** 2137 * Initialization routine for run-time dependency on rdma-core. 2138 */ 2139 static int 2140 mlx5_glue_init(void) 2141 { 2142 char glue_path[sizeof(RTE_EAL_PMD_PATH) - 1 + sizeof("-glue")]; 2143 const char *path[] = { 2144 /* 2145 * A basic security check is necessary before trusting 2146 * MLX5_GLUE_PATH, which may override RTE_EAL_PMD_PATH. 2147 */ 2148 (geteuid() == getuid() && getegid() == getgid() ? 2149 getenv("MLX5_GLUE_PATH") : NULL), 2150 /* 2151 * When RTE_EAL_PMD_PATH is set, use its glue-suffixed 2152 * variant, otherwise let dlopen() look up libraries on its 2153 * own. 2154 */ 2155 (*RTE_EAL_PMD_PATH ? 2156 mlx5_glue_path(glue_path, sizeof(glue_path)) : ""), 2157 }; 2158 unsigned int i = 0; 2159 void *handle = NULL; 2160 void **sym; 2161 const char *dlmsg; 2162 2163 while (!handle && i != RTE_DIM(path)) { 2164 const char *end; 2165 size_t len; 2166 int ret; 2167 2168 if (!path[i]) { 2169 ++i; 2170 continue; 2171 } 2172 end = strpbrk(path[i], ":;"); 2173 if (!end) 2174 end = path[i] + strlen(path[i]); 2175 len = end - path[i]; 2176 ret = 0; 2177 do { 2178 char name[ret + 1]; 2179 2180 ret = snprintf(name, sizeof(name), "%.*s%s" MLX5_GLUE, 2181 (int)len, path[i], 2182 (!len || *(end - 1) == '/') ? "" : "/"); 2183 if (ret == -1) 2184 break; 2185 if (sizeof(name) != (size_t)ret + 1) 2186 continue; 2187 DRV_LOG(DEBUG, "looking for rdma-core glue as \"%s\"", 2188 name); 2189 handle = dlopen(name, RTLD_LAZY); 2190 break; 2191 } while (1); 2192 path[i] = end + 1; 2193 if (!*end) 2194 ++i; 2195 } 2196 if (!handle) { 2197 rte_errno = EINVAL; 2198 dlmsg = dlerror(); 2199 if (dlmsg) 2200 DRV_LOG(WARNING, "cannot load glue library: %s", dlmsg); 2201 goto glue_error; 2202 } 2203 sym = dlsym(handle, "mlx5_glue"); 2204 if (!sym || !*sym) { 2205 rte_errno = EINVAL; 2206 dlmsg = dlerror(); 2207 if (dlmsg) 2208 DRV_LOG(ERR, "cannot resolve glue symbol: %s", dlmsg); 2209 goto glue_error; 2210 } 2211 mlx5_glue = *sym; 2212 return 0; 2213 glue_error: 2214 if (handle) 2215 dlclose(handle); 2216 DRV_LOG(WARNING, 2217 "cannot initialize PMD due to missing run-time dependency on" 2218 " rdma-core libraries (libibverbs, libmlx5)"); 2219 return -rte_errno; 2220 } 2221 2222 #endif 2223 2224 /** 2225 * Driver initialization routine. 2226 */ 2227 RTE_INIT(rte_mlx5_pmd_init) 2228 { 2229 /* Initialize driver log type. */ 2230 mlx5_logtype = rte_log_register("pmd.net.mlx5"); 2231 if (mlx5_logtype >= 0) 2232 rte_log_set_level(mlx5_logtype, RTE_LOG_NOTICE); 2233 2234 /* Build the static tables for Verbs conversion. */ 2235 mlx5_set_ptype_table(); 2236 mlx5_set_cksum_table(); 2237 mlx5_set_swp_types_table(); 2238 /* 2239 * RDMAV_HUGEPAGES_SAFE tells ibv_fork_init() we intend to use 2240 * huge pages. Calling ibv_fork_init() during init allows 2241 * applications to use fork() safely for purposes other than 2242 * using this PMD, which is not supported in forked processes. 2243 */ 2244 setenv("RDMAV_HUGEPAGES_SAFE", "1", 1); 2245 /* Match the size of Rx completion entry to the size of a cacheline. */ 2246 if (RTE_CACHE_LINE_SIZE == 128) 2247 setenv("MLX5_CQE_SIZE", "128", 0); 2248 /* 2249 * MLX5_DEVICE_FATAL_CLEANUP tells ibv_destroy functions to 2250 * cleanup all the Verbs resources even when the device was removed. 2251 */ 2252 setenv("MLX5_DEVICE_FATAL_CLEANUP", "1", 1); 2253 #ifdef RTE_IBVERBS_LINK_DLOPEN 2254 if (mlx5_glue_init()) 2255 return; 2256 assert(mlx5_glue); 2257 #endif 2258 #ifndef NDEBUG 2259 /* Glue structure must not contain any NULL pointers. */ 2260 { 2261 unsigned int i; 2262 2263 for (i = 0; i != sizeof(*mlx5_glue) / sizeof(void *); ++i) 2264 assert(((const void *const *)mlx5_glue)[i]); 2265 } 2266 #endif 2267 if (strcmp(mlx5_glue->version, MLX5_GLUE_VERSION)) { 2268 DRV_LOG(ERR, 2269 "rdma-core glue \"%s\" mismatch: \"%s\" is required", 2270 mlx5_glue->version, MLX5_GLUE_VERSION); 2271 return; 2272 } 2273 mlx5_glue->fork_init(); 2274 rte_pci_register(&mlx5_driver); 2275 } 2276 2277 RTE_PMD_EXPORT_NAME(net_mlx5, __COUNTER__); 2278 RTE_PMD_REGISTER_PCI_TABLE(net_mlx5, mlx5_pci_id_map); 2279 RTE_PMD_REGISTER_KMOD_DEP(net_mlx5, "* ib_uverbs & mlx5_core & mlx5_ib"); 2280