1 /* SPDX-License-Identifier: BSD-3-Clause 2 * Copyright 2015 6WIND S.A. 3 * Copyright 2015 Mellanox Technologies, Ltd 4 */ 5 6 #include <stddef.h> 7 #include <unistd.h> 8 #include <string.h> 9 #include <assert.h> 10 #include <dlfcn.h> 11 #include <stdint.h> 12 #include <stdlib.h> 13 #include <errno.h> 14 #include <net/if.h> 15 #include <sys/mman.h> 16 #include <linux/netlink.h> 17 #include <linux/rtnetlink.h> 18 19 /* Verbs header. */ 20 /* ISO C doesn't support unnamed structs/unions, disabling -pedantic. */ 21 #ifdef PEDANTIC 22 #pragma GCC diagnostic ignored "-Wpedantic" 23 #endif 24 #include <infiniband/verbs.h> 25 #ifdef PEDANTIC 26 #pragma GCC diagnostic error "-Wpedantic" 27 #endif 28 29 #include <rte_malloc.h> 30 #include <rte_ethdev_driver.h> 31 #include <rte_ethdev_pci.h> 32 #include <rte_pci.h> 33 #include <rte_bus_pci.h> 34 #include <rte_common.h> 35 #include <rte_config.h> 36 #include <rte_eal_memconfig.h> 37 #include <rte_kvargs.h> 38 #include <rte_rwlock.h> 39 #include <rte_spinlock.h> 40 #include <rte_string_fns.h> 41 42 #include "mlx5.h" 43 #include "mlx5_utils.h" 44 #include "mlx5_rxtx.h" 45 #include "mlx5_autoconf.h" 46 #include "mlx5_defs.h" 47 #include "mlx5_glue.h" 48 #include "mlx5_mr.h" 49 #include "mlx5_flow.h" 50 51 /* Device parameter to enable RX completion queue compression. */ 52 #define MLX5_RXQ_CQE_COMP_EN "rxq_cqe_comp_en" 53 54 /* Device parameter to enable RX completion entry padding to 128B. */ 55 #define MLX5_RXQ_CQE_PAD_EN "rxq_cqe_pad_en" 56 57 /* Device parameter to enable Multi-Packet Rx queue. */ 58 #define MLX5_RX_MPRQ_EN "mprq_en" 59 60 /* Device parameter to configure log 2 of the number of strides for MPRQ. */ 61 #define MLX5_RX_MPRQ_LOG_STRIDE_NUM "mprq_log_stride_num" 62 63 /* Device parameter to limit the size of memcpy'd packet for MPRQ. */ 64 #define MLX5_RX_MPRQ_MAX_MEMCPY_LEN "mprq_max_memcpy_len" 65 66 /* Device parameter to set the minimum number of Rx queues to enable MPRQ. */ 67 #define MLX5_RXQS_MIN_MPRQ "rxqs_min_mprq" 68 69 /* Device parameter to configure inline send. */ 70 #define MLX5_TXQ_INLINE "txq_inline" 71 72 /* 73 * Device parameter to configure the number of TX queues threshold for 74 * enabling inline send. 75 */ 76 #define MLX5_TXQS_MIN_INLINE "txqs_min_inline" 77 78 /* 79 * Device parameter to configure the number of TX queues threshold for 80 * enabling vectorized Tx. 81 */ 82 #define MLX5_TXQS_MAX_VEC "txqs_max_vec" 83 84 /* Device parameter to enable multi-packet send WQEs. */ 85 #define MLX5_TXQ_MPW_EN "txq_mpw_en" 86 87 /* Device parameter to include 2 dsegs in the title WQEBB. */ 88 #define MLX5_TXQ_MPW_HDR_DSEG_EN "txq_mpw_hdr_dseg_en" 89 90 /* Device parameter to limit the size of inlining packet. */ 91 #define MLX5_TXQ_MAX_INLINE_LEN "txq_max_inline_len" 92 93 /* Device parameter to enable hardware Tx vector. */ 94 #define MLX5_TX_VEC_EN "tx_vec_en" 95 96 /* Device parameter to enable hardware Rx vector. */ 97 #define MLX5_RX_VEC_EN "rx_vec_en" 98 99 /* Allow L3 VXLAN flow creation. */ 100 #define MLX5_L3_VXLAN_EN "l3_vxlan_en" 101 102 /* Activate DV flow steering. */ 103 #define MLX5_DV_FLOW_EN "dv_flow_en" 104 105 /* Activate Netlink support in VF mode. */ 106 #define MLX5_VF_NL_EN "vf_nl_en" 107 108 /* Select port representors to instantiate. */ 109 #define MLX5_REPRESENTOR "representor" 110 111 #ifndef HAVE_IBV_MLX5_MOD_MPW 112 #define MLX5DV_CONTEXT_FLAGS_MPW_ALLOWED (1 << 2) 113 #define MLX5DV_CONTEXT_FLAGS_ENHANCED_MPW (1 << 3) 114 #endif 115 116 #ifndef HAVE_IBV_MLX5_MOD_CQE_128B_COMP 117 #define MLX5DV_CONTEXT_FLAGS_CQE_128B_COMP (1 << 4) 118 #endif 119 120 static const char *MZ_MLX5_PMD_SHARED_DATA = "mlx5_pmd_shared_data"; 121 122 /* Shared memory between primary and secondary processes. */ 123 struct mlx5_shared_data *mlx5_shared_data; 124 125 /* Spinlock for mlx5_shared_data allocation. */ 126 static rte_spinlock_t mlx5_shared_data_lock = RTE_SPINLOCK_INITIALIZER; 127 128 /** Driver-specific log messages type. */ 129 int mlx5_logtype; 130 131 /** 132 * Prepare shared data between primary and secondary process. 133 */ 134 static void 135 mlx5_prepare_shared_data(void) 136 { 137 const struct rte_memzone *mz; 138 139 rte_spinlock_lock(&mlx5_shared_data_lock); 140 if (mlx5_shared_data == NULL) { 141 if (rte_eal_process_type() == RTE_PROC_PRIMARY) { 142 /* Allocate shared memory. */ 143 mz = rte_memzone_reserve(MZ_MLX5_PMD_SHARED_DATA, 144 sizeof(*mlx5_shared_data), 145 SOCKET_ID_ANY, 0); 146 } else { 147 /* Lookup allocated shared memory. */ 148 mz = rte_memzone_lookup(MZ_MLX5_PMD_SHARED_DATA); 149 } 150 if (mz == NULL) 151 rte_panic("Cannot allocate mlx5 shared data\n"); 152 mlx5_shared_data = mz->addr; 153 /* Initialize shared data. */ 154 if (rte_eal_process_type() == RTE_PROC_PRIMARY) { 155 LIST_INIT(&mlx5_shared_data->mem_event_cb_list); 156 rte_rwlock_init(&mlx5_shared_data->mem_event_rwlock); 157 } 158 rte_mem_event_callback_register("MLX5_MEM_EVENT_CB", 159 mlx5_mr_mem_event_cb, NULL); 160 } 161 rte_spinlock_unlock(&mlx5_shared_data_lock); 162 } 163 164 /** 165 * Retrieve integer value from environment variable. 166 * 167 * @param[in] name 168 * Environment variable name. 169 * 170 * @return 171 * Integer value, 0 if the variable is not set. 172 */ 173 int 174 mlx5_getenv_int(const char *name) 175 { 176 const char *val = getenv(name); 177 178 if (val == NULL) 179 return 0; 180 return atoi(val); 181 } 182 183 /** 184 * Verbs callback to allocate a memory. This function should allocate the space 185 * according to the size provided residing inside a huge page. 186 * Please note that all allocation must respect the alignment from libmlx5 187 * (i.e. currently sysconf(_SC_PAGESIZE)). 188 * 189 * @param[in] size 190 * The size in bytes of the memory to allocate. 191 * @param[in] data 192 * A pointer to the callback data. 193 * 194 * @return 195 * Allocated buffer, NULL otherwise and rte_errno is set. 196 */ 197 static void * 198 mlx5_alloc_verbs_buf(size_t size, void *data) 199 { 200 struct priv *priv = data; 201 void *ret; 202 size_t alignment = sysconf(_SC_PAGESIZE); 203 unsigned int socket = SOCKET_ID_ANY; 204 205 if (priv->verbs_alloc_ctx.type == MLX5_VERBS_ALLOC_TYPE_TX_QUEUE) { 206 const struct mlx5_txq_ctrl *ctrl = priv->verbs_alloc_ctx.obj; 207 208 socket = ctrl->socket; 209 } else if (priv->verbs_alloc_ctx.type == 210 MLX5_VERBS_ALLOC_TYPE_RX_QUEUE) { 211 const struct mlx5_rxq_ctrl *ctrl = priv->verbs_alloc_ctx.obj; 212 213 socket = ctrl->socket; 214 } 215 assert(data != NULL); 216 ret = rte_malloc_socket(__func__, size, alignment, socket); 217 if (!ret && size) 218 rte_errno = ENOMEM; 219 return ret; 220 } 221 222 /** 223 * Verbs callback to free a memory. 224 * 225 * @param[in] ptr 226 * A pointer to the memory to free. 227 * @param[in] data 228 * A pointer to the callback data. 229 */ 230 static void 231 mlx5_free_verbs_buf(void *ptr, void *data __rte_unused) 232 { 233 assert(data != NULL); 234 rte_free(ptr); 235 } 236 237 /** 238 * DPDK callback to close the device. 239 * 240 * Destroy all queues and objects, free memory. 241 * 242 * @param dev 243 * Pointer to Ethernet device structure. 244 */ 245 static void 246 mlx5_dev_close(struct rte_eth_dev *dev) 247 { 248 struct priv *priv = dev->data->dev_private; 249 unsigned int i; 250 int ret; 251 252 DRV_LOG(DEBUG, "port %u closing device \"%s\"", 253 dev->data->port_id, 254 ((priv->ctx != NULL) ? priv->ctx->device->name : "")); 255 /* In case mlx5_dev_stop() has not been called. */ 256 mlx5_dev_interrupt_handler_uninstall(dev); 257 mlx5_traffic_disable(dev); 258 mlx5_flow_flush(dev, NULL); 259 /* Prevent crashes when queues are still in use. */ 260 dev->rx_pkt_burst = removed_rx_burst; 261 dev->tx_pkt_burst = removed_tx_burst; 262 if (priv->rxqs != NULL) { 263 /* XXX race condition if mlx5_rx_burst() is still running. */ 264 usleep(1000); 265 for (i = 0; (i != priv->rxqs_n); ++i) 266 mlx5_rxq_release(dev, i); 267 priv->rxqs_n = 0; 268 priv->rxqs = NULL; 269 } 270 if (priv->txqs != NULL) { 271 /* XXX race condition if mlx5_tx_burst() is still running. */ 272 usleep(1000); 273 for (i = 0; (i != priv->txqs_n); ++i) 274 mlx5_txq_release(dev, i); 275 priv->txqs_n = 0; 276 priv->txqs = NULL; 277 } 278 mlx5_mprq_free_mp(dev); 279 mlx5_mr_release(dev); 280 if (priv->pd != NULL) { 281 assert(priv->ctx != NULL); 282 claim_zero(mlx5_glue->dealloc_pd(priv->pd)); 283 claim_zero(mlx5_glue->close_device(priv->ctx)); 284 } else 285 assert(priv->ctx == NULL); 286 if (priv->rss_conf.rss_key != NULL) 287 rte_free(priv->rss_conf.rss_key); 288 if (priv->reta_idx != NULL) 289 rte_free(priv->reta_idx); 290 if (priv->primary_socket) 291 mlx5_socket_uninit(dev); 292 if (priv->config.vf) 293 mlx5_nl_mac_addr_flush(dev); 294 if (priv->nl_socket_route >= 0) 295 close(priv->nl_socket_route); 296 if (priv->nl_socket_rdma >= 0) 297 close(priv->nl_socket_rdma); 298 if (priv->tcf_context) 299 mlx5_flow_tcf_context_destroy(priv->tcf_context); 300 ret = mlx5_hrxq_ibv_verify(dev); 301 if (ret) 302 DRV_LOG(WARNING, "port %u some hash Rx queue still remain", 303 dev->data->port_id); 304 ret = mlx5_ind_table_ibv_verify(dev); 305 if (ret) 306 DRV_LOG(WARNING, "port %u some indirection table still remain", 307 dev->data->port_id); 308 ret = mlx5_rxq_ibv_verify(dev); 309 if (ret) 310 DRV_LOG(WARNING, "port %u some Verbs Rx queue still remain", 311 dev->data->port_id); 312 ret = mlx5_rxq_verify(dev); 313 if (ret) 314 DRV_LOG(WARNING, "port %u some Rx queues still remain", 315 dev->data->port_id); 316 ret = mlx5_txq_ibv_verify(dev); 317 if (ret) 318 DRV_LOG(WARNING, "port %u some Verbs Tx queue still remain", 319 dev->data->port_id); 320 ret = mlx5_txq_verify(dev); 321 if (ret) 322 DRV_LOG(WARNING, "port %u some Tx queues still remain", 323 dev->data->port_id); 324 ret = mlx5_flow_verify(dev); 325 if (ret) 326 DRV_LOG(WARNING, "port %u some flows still remain", 327 dev->data->port_id); 328 if (priv->domain_id != RTE_ETH_DEV_SWITCH_DOMAIN_ID_INVALID) { 329 unsigned int c = 0; 330 unsigned int i = mlx5_dev_to_port_id(dev->device, NULL, 0); 331 uint16_t port_id[i]; 332 333 i = RTE_MIN(mlx5_dev_to_port_id(dev->device, port_id, i), i); 334 while (i--) { 335 struct priv *opriv = 336 rte_eth_devices[port_id[i]].data->dev_private; 337 338 if (!opriv || 339 opriv->domain_id != priv->domain_id || 340 &rte_eth_devices[port_id[i]] == dev) 341 continue; 342 ++c; 343 } 344 if (!c) 345 claim_zero(rte_eth_switch_domain_free(priv->domain_id)); 346 } 347 memset(priv, 0, sizeof(*priv)); 348 priv->domain_id = RTE_ETH_DEV_SWITCH_DOMAIN_ID_INVALID; 349 /* 350 * Reset mac_addrs to NULL such that it is not freed as part of 351 * rte_eth_dev_release_port(). mac_addrs is part of dev_private so 352 * it is freed when dev_private is freed. 353 */ 354 dev->data->mac_addrs = NULL; 355 } 356 357 const struct eth_dev_ops mlx5_dev_ops = { 358 .dev_configure = mlx5_dev_configure, 359 .dev_start = mlx5_dev_start, 360 .dev_stop = mlx5_dev_stop, 361 .dev_set_link_down = mlx5_set_link_down, 362 .dev_set_link_up = mlx5_set_link_up, 363 .dev_close = mlx5_dev_close, 364 .promiscuous_enable = mlx5_promiscuous_enable, 365 .promiscuous_disable = mlx5_promiscuous_disable, 366 .allmulticast_enable = mlx5_allmulticast_enable, 367 .allmulticast_disable = mlx5_allmulticast_disable, 368 .link_update = mlx5_link_update, 369 .stats_get = mlx5_stats_get, 370 .stats_reset = mlx5_stats_reset, 371 .xstats_get = mlx5_xstats_get, 372 .xstats_reset = mlx5_xstats_reset, 373 .xstats_get_names = mlx5_xstats_get_names, 374 .dev_infos_get = mlx5_dev_infos_get, 375 .dev_supported_ptypes_get = mlx5_dev_supported_ptypes_get, 376 .vlan_filter_set = mlx5_vlan_filter_set, 377 .rx_queue_setup = mlx5_rx_queue_setup, 378 .tx_queue_setup = mlx5_tx_queue_setup, 379 .rx_queue_release = mlx5_rx_queue_release, 380 .tx_queue_release = mlx5_tx_queue_release, 381 .flow_ctrl_get = mlx5_dev_get_flow_ctrl, 382 .flow_ctrl_set = mlx5_dev_set_flow_ctrl, 383 .mac_addr_remove = mlx5_mac_addr_remove, 384 .mac_addr_add = mlx5_mac_addr_add, 385 .mac_addr_set = mlx5_mac_addr_set, 386 .set_mc_addr_list = mlx5_set_mc_addr_list, 387 .mtu_set = mlx5_dev_set_mtu, 388 .vlan_strip_queue_set = mlx5_vlan_strip_queue_set, 389 .vlan_offload_set = mlx5_vlan_offload_set, 390 .reta_update = mlx5_dev_rss_reta_update, 391 .reta_query = mlx5_dev_rss_reta_query, 392 .rss_hash_update = mlx5_rss_hash_update, 393 .rss_hash_conf_get = mlx5_rss_hash_conf_get, 394 .filter_ctrl = mlx5_dev_filter_ctrl, 395 .rx_descriptor_status = mlx5_rx_descriptor_status, 396 .tx_descriptor_status = mlx5_tx_descriptor_status, 397 .rx_queue_count = mlx5_rx_queue_count, 398 .rx_queue_intr_enable = mlx5_rx_intr_enable, 399 .rx_queue_intr_disable = mlx5_rx_intr_disable, 400 .is_removed = mlx5_is_removed, 401 }; 402 403 static const struct eth_dev_ops mlx5_dev_sec_ops = { 404 .stats_get = mlx5_stats_get, 405 .stats_reset = mlx5_stats_reset, 406 .xstats_get = mlx5_xstats_get, 407 .xstats_reset = mlx5_xstats_reset, 408 .xstats_get_names = mlx5_xstats_get_names, 409 .dev_infos_get = mlx5_dev_infos_get, 410 .rx_descriptor_status = mlx5_rx_descriptor_status, 411 .tx_descriptor_status = mlx5_tx_descriptor_status, 412 }; 413 414 /* Available operators in flow isolated mode. */ 415 const struct eth_dev_ops mlx5_dev_ops_isolate = { 416 .dev_configure = mlx5_dev_configure, 417 .dev_start = mlx5_dev_start, 418 .dev_stop = mlx5_dev_stop, 419 .dev_set_link_down = mlx5_set_link_down, 420 .dev_set_link_up = mlx5_set_link_up, 421 .dev_close = mlx5_dev_close, 422 .promiscuous_enable = mlx5_promiscuous_enable, 423 .promiscuous_disable = mlx5_promiscuous_disable, 424 .allmulticast_enable = mlx5_allmulticast_enable, 425 .allmulticast_disable = mlx5_allmulticast_disable, 426 .link_update = mlx5_link_update, 427 .stats_get = mlx5_stats_get, 428 .stats_reset = mlx5_stats_reset, 429 .xstats_get = mlx5_xstats_get, 430 .xstats_reset = mlx5_xstats_reset, 431 .xstats_get_names = mlx5_xstats_get_names, 432 .dev_infos_get = mlx5_dev_infos_get, 433 .dev_supported_ptypes_get = mlx5_dev_supported_ptypes_get, 434 .vlan_filter_set = mlx5_vlan_filter_set, 435 .rx_queue_setup = mlx5_rx_queue_setup, 436 .tx_queue_setup = mlx5_tx_queue_setup, 437 .rx_queue_release = mlx5_rx_queue_release, 438 .tx_queue_release = mlx5_tx_queue_release, 439 .flow_ctrl_get = mlx5_dev_get_flow_ctrl, 440 .flow_ctrl_set = mlx5_dev_set_flow_ctrl, 441 .mac_addr_remove = mlx5_mac_addr_remove, 442 .mac_addr_add = mlx5_mac_addr_add, 443 .mac_addr_set = mlx5_mac_addr_set, 444 .set_mc_addr_list = mlx5_set_mc_addr_list, 445 .mtu_set = mlx5_dev_set_mtu, 446 .vlan_strip_queue_set = mlx5_vlan_strip_queue_set, 447 .vlan_offload_set = mlx5_vlan_offload_set, 448 .filter_ctrl = mlx5_dev_filter_ctrl, 449 .rx_descriptor_status = mlx5_rx_descriptor_status, 450 .tx_descriptor_status = mlx5_tx_descriptor_status, 451 .rx_queue_intr_enable = mlx5_rx_intr_enable, 452 .rx_queue_intr_disable = mlx5_rx_intr_disable, 453 .is_removed = mlx5_is_removed, 454 }; 455 456 /** 457 * Verify and store value for device argument. 458 * 459 * @param[in] key 460 * Key argument to verify. 461 * @param[in] val 462 * Value associated with key. 463 * @param opaque 464 * User data. 465 * 466 * @return 467 * 0 on success, a negative errno value otherwise and rte_errno is set. 468 */ 469 static int 470 mlx5_args_check(const char *key, const char *val, void *opaque) 471 { 472 struct mlx5_dev_config *config = opaque; 473 unsigned long tmp; 474 475 /* No-op, port representors are processed in mlx5_dev_spawn(). */ 476 if (!strcmp(MLX5_REPRESENTOR, key)) 477 return 0; 478 errno = 0; 479 tmp = strtoul(val, NULL, 0); 480 if (errno) { 481 rte_errno = errno; 482 DRV_LOG(WARNING, "%s: \"%s\" is not a valid integer", key, val); 483 return -rte_errno; 484 } 485 if (strcmp(MLX5_RXQ_CQE_COMP_EN, key) == 0) { 486 config->cqe_comp = !!tmp; 487 } else if (strcmp(MLX5_RXQ_CQE_PAD_EN, key) == 0) { 488 config->cqe_pad = !!tmp; 489 } else if (strcmp(MLX5_RX_MPRQ_EN, key) == 0) { 490 config->mprq.enabled = !!tmp; 491 } else if (strcmp(MLX5_RX_MPRQ_LOG_STRIDE_NUM, key) == 0) { 492 config->mprq.stride_num_n = tmp; 493 } else if (strcmp(MLX5_RX_MPRQ_MAX_MEMCPY_LEN, key) == 0) { 494 config->mprq.max_memcpy_len = tmp; 495 } else if (strcmp(MLX5_RXQS_MIN_MPRQ, key) == 0) { 496 config->mprq.min_rxqs_num = tmp; 497 } else if (strcmp(MLX5_TXQ_INLINE, key) == 0) { 498 config->txq_inline = tmp; 499 } else if (strcmp(MLX5_TXQS_MIN_INLINE, key) == 0) { 500 config->txqs_inline = tmp; 501 } else if (strcmp(MLX5_TXQS_MAX_VEC, key) == 0) { 502 config->txqs_vec = tmp; 503 } else if (strcmp(MLX5_TXQ_MPW_EN, key) == 0) { 504 config->mps = !!tmp; 505 } else if (strcmp(MLX5_TXQ_MPW_HDR_DSEG_EN, key) == 0) { 506 config->mpw_hdr_dseg = !!tmp; 507 } else if (strcmp(MLX5_TXQ_MAX_INLINE_LEN, key) == 0) { 508 config->inline_max_packet_sz = tmp; 509 } else if (strcmp(MLX5_TX_VEC_EN, key) == 0) { 510 config->tx_vec_en = !!tmp; 511 } else if (strcmp(MLX5_RX_VEC_EN, key) == 0) { 512 config->rx_vec_en = !!tmp; 513 } else if (strcmp(MLX5_L3_VXLAN_EN, key) == 0) { 514 config->l3_vxlan_en = !!tmp; 515 } else if (strcmp(MLX5_VF_NL_EN, key) == 0) { 516 config->vf_nl_en = !!tmp; 517 } else if (strcmp(MLX5_DV_FLOW_EN, key) == 0) { 518 config->dv_flow_en = !!tmp; 519 } else { 520 DRV_LOG(WARNING, "%s: unknown parameter", key); 521 rte_errno = EINVAL; 522 return -rte_errno; 523 } 524 return 0; 525 } 526 527 /** 528 * Parse device parameters. 529 * 530 * @param config 531 * Pointer to device configuration structure. 532 * @param devargs 533 * Device arguments structure. 534 * 535 * @return 536 * 0 on success, a negative errno value otherwise and rte_errno is set. 537 */ 538 static int 539 mlx5_args(struct mlx5_dev_config *config, struct rte_devargs *devargs) 540 { 541 const char **params = (const char *[]){ 542 MLX5_RXQ_CQE_COMP_EN, 543 MLX5_RXQ_CQE_PAD_EN, 544 MLX5_RX_MPRQ_EN, 545 MLX5_RX_MPRQ_LOG_STRIDE_NUM, 546 MLX5_RX_MPRQ_MAX_MEMCPY_LEN, 547 MLX5_RXQS_MIN_MPRQ, 548 MLX5_TXQ_INLINE, 549 MLX5_TXQS_MIN_INLINE, 550 MLX5_TXQS_MAX_VEC, 551 MLX5_TXQ_MPW_EN, 552 MLX5_TXQ_MPW_HDR_DSEG_EN, 553 MLX5_TXQ_MAX_INLINE_LEN, 554 MLX5_TX_VEC_EN, 555 MLX5_RX_VEC_EN, 556 MLX5_L3_VXLAN_EN, 557 MLX5_VF_NL_EN, 558 MLX5_DV_FLOW_EN, 559 MLX5_REPRESENTOR, 560 NULL, 561 }; 562 struct rte_kvargs *kvlist; 563 int ret = 0; 564 int i; 565 566 if (devargs == NULL) 567 return 0; 568 /* Following UGLY cast is done to pass checkpatch. */ 569 kvlist = rte_kvargs_parse(devargs->args, params); 570 if (kvlist == NULL) 571 return 0; 572 /* Process parameters. */ 573 for (i = 0; (params[i] != NULL); ++i) { 574 if (rte_kvargs_count(kvlist, params[i])) { 575 ret = rte_kvargs_process(kvlist, params[i], 576 mlx5_args_check, config); 577 if (ret) { 578 rte_errno = EINVAL; 579 rte_kvargs_free(kvlist); 580 return -rte_errno; 581 } 582 } 583 } 584 rte_kvargs_free(kvlist); 585 return 0; 586 } 587 588 static struct rte_pci_driver mlx5_driver; 589 590 /* 591 * Reserved UAR address space for TXQ UAR(hw doorbell) mapping, process 592 * local resource used by both primary and secondary to avoid duplicate 593 * reservation. 594 * The space has to be available on both primary and secondary process, 595 * TXQ UAR maps to this area using fixed mmap w/o double check. 596 */ 597 static void *uar_base; 598 599 static int 600 find_lower_va_bound(const struct rte_memseg_list *msl, 601 const struct rte_memseg *ms, void *arg) 602 { 603 void **addr = arg; 604 605 if (msl->external) 606 return 0; 607 if (*addr == NULL) 608 *addr = ms->addr; 609 else 610 *addr = RTE_MIN(*addr, ms->addr); 611 612 return 0; 613 } 614 615 /** 616 * Reserve UAR address space for primary process. 617 * 618 * @param[in] dev 619 * Pointer to Ethernet device. 620 * 621 * @return 622 * 0 on success, a negative errno value otherwise and rte_errno is set. 623 */ 624 static int 625 mlx5_uar_init_primary(struct rte_eth_dev *dev) 626 { 627 struct priv *priv = dev->data->dev_private; 628 void *addr = (void *)0; 629 630 if (uar_base) { /* UAR address space mapped. */ 631 priv->uar_base = uar_base; 632 return 0; 633 } 634 /* find out lower bound of hugepage segments */ 635 rte_memseg_walk(find_lower_va_bound, &addr); 636 637 /* keep distance to hugepages to minimize potential conflicts. */ 638 addr = RTE_PTR_SUB(addr, (uintptr_t)(MLX5_UAR_OFFSET + MLX5_UAR_SIZE)); 639 /* anonymous mmap, no real memory consumption. */ 640 addr = mmap(addr, MLX5_UAR_SIZE, 641 PROT_NONE, MAP_PRIVATE | MAP_ANONYMOUS, -1, 0); 642 if (addr == MAP_FAILED) { 643 DRV_LOG(ERR, 644 "port %u failed to reserve UAR address space, please" 645 " adjust MLX5_UAR_SIZE or try --base-virtaddr", 646 dev->data->port_id); 647 rte_errno = ENOMEM; 648 return -rte_errno; 649 } 650 /* Accept either same addr or a new addr returned from mmap if target 651 * range occupied. 652 */ 653 DRV_LOG(INFO, "port %u reserved UAR address space: %p", 654 dev->data->port_id, addr); 655 priv->uar_base = addr; /* for primary and secondary UAR re-mmap. */ 656 uar_base = addr; /* process local, don't reserve again. */ 657 return 0; 658 } 659 660 /** 661 * Reserve UAR address space for secondary process, align with 662 * primary process. 663 * 664 * @param[in] dev 665 * Pointer to Ethernet device. 666 * 667 * @return 668 * 0 on success, a negative errno value otherwise and rte_errno is set. 669 */ 670 static int 671 mlx5_uar_init_secondary(struct rte_eth_dev *dev) 672 { 673 struct priv *priv = dev->data->dev_private; 674 void *addr; 675 676 assert(priv->uar_base); 677 if (uar_base) { /* already reserved. */ 678 assert(uar_base == priv->uar_base); 679 return 0; 680 } 681 /* anonymous mmap, no real memory consumption. */ 682 addr = mmap(priv->uar_base, MLX5_UAR_SIZE, 683 PROT_NONE, MAP_PRIVATE | MAP_ANONYMOUS, -1, 0); 684 if (addr == MAP_FAILED) { 685 DRV_LOG(ERR, "port %u UAR mmap failed: %p size: %llu", 686 dev->data->port_id, priv->uar_base, MLX5_UAR_SIZE); 687 rte_errno = ENXIO; 688 return -rte_errno; 689 } 690 if (priv->uar_base != addr) { 691 DRV_LOG(ERR, 692 "port %u UAR address %p size %llu occupied, please" 693 " adjust MLX5_UAR_OFFSET or try EAL parameter" 694 " --base-virtaddr", 695 dev->data->port_id, priv->uar_base, MLX5_UAR_SIZE); 696 rte_errno = ENXIO; 697 return -rte_errno; 698 } 699 uar_base = addr; /* process local, don't reserve again */ 700 DRV_LOG(INFO, "port %u reserved UAR address space: %p", 701 dev->data->port_id, addr); 702 return 0; 703 } 704 705 /** 706 * Spawn an Ethernet device from Verbs information. 707 * 708 * @param dpdk_dev 709 * Backing DPDK device. 710 * @param ibv_dev 711 * Verbs device. 712 * @param config 713 * Device configuration parameters. 714 * @param[in] switch_info 715 * Switch properties of Ethernet device. 716 * 717 * @return 718 * A valid Ethernet device object on success, NULL otherwise and rte_errno 719 * is set. The following errors are defined: 720 * 721 * EBUSY: device is not supposed to be spawned. 722 * EEXIST: device is already spawned 723 */ 724 static struct rte_eth_dev * 725 mlx5_dev_spawn(struct rte_device *dpdk_dev, 726 struct ibv_device *ibv_dev, 727 struct mlx5_dev_config config, 728 const struct mlx5_switch_info *switch_info) 729 { 730 struct ibv_context *ctx; 731 struct ibv_device_attr_ex attr; 732 struct ibv_port_attr port_attr; 733 struct ibv_pd *pd = NULL; 734 struct mlx5dv_context dv_attr = { .comp_mask = 0 }; 735 struct rte_eth_dev *eth_dev = NULL; 736 struct priv *priv = NULL; 737 int err = 0; 738 unsigned int mps; 739 unsigned int cqe_comp; 740 unsigned int cqe_pad = 0; 741 unsigned int tunnel_en = 0; 742 unsigned int mpls_en = 0; 743 unsigned int swp = 0; 744 unsigned int mprq = 0; 745 unsigned int mprq_min_stride_size_n = 0; 746 unsigned int mprq_max_stride_size_n = 0; 747 unsigned int mprq_min_stride_num_n = 0; 748 unsigned int mprq_max_stride_num_n = 0; 749 struct ether_addr mac; 750 char name[RTE_ETH_NAME_MAX_LEN]; 751 int own_domain_id = 0; 752 uint16_t port_id; 753 unsigned int i; 754 755 /* Determine if this port representor is supposed to be spawned. */ 756 if (switch_info->representor && dpdk_dev->devargs) { 757 struct rte_eth_devargs eth_da; 758 759 err = rte_eth_devargs_parse(dpdk_dev->devargs->args, ð_da); 760 if (err) { 761 rte_errno = -err; 762 DRV_LOG(ERR, "failed to process device arguments: %s", 763 strerror(rte_errno)); 764 return NULL; 765 } 766 for (i = 0; i < eth_da.nb_representor_ports; ++i) 767 if (eth_da.representor_ports[i] == 768 (uint16_t)switch_info->port_name) 769 break; 770 if (i == eth_da.nb_representor_ports) { 771 rte_errno = EBUSY; 772 return NULL; 773 } 774 } 775 /* Build device name. */ 776 if (!switch_info->representor) 777 rte_strlcpy(name, dpdk_dev->name, sizeof(name)); 778 else 779 snprintf(name, sizeof(name), "%s_representor_%u", 780 dpdk_dev->name, switch_info->port_name); 781 /* check if the device is already spawned */ 782 if (rte_eth_dev_get_port_by_name(name, &port_id) == 0) { 783 rte_errno = EEXIST; 784 return NULL; 785 } 786 /* Prepare shared data between primary and secondary process. */ 787 mlx5_prepare_shared_data(); 788 errno = 0; 789 ctx = mlx5_glue->open_device(ibv_dev); 790 if (!ctx) { 791 rte_errno = errno ? errno : ENODEV; 792 return NULL; 793 } 794 #ifdef HAVE_IBV_MLX5_MOD_SWP 795 dv_attr.comp_mask |= MLX5DV_CONTEXT_MASK_SWP; 796 #endif 797 /* 798 * Multi-packet send is supported by ConnectX-4 Lx PF as well 799 * as all ConnectX-5 devices. 800 */ 801 #ifdef HAVE_IBV_DEVICE_TUNNEL_SUPPORT 802 dv_attr.comp_mask |= MLX5DV_CONTEXT_MASK_TUNNEL_OFFLOADS; 803 #endif 804 #ifdef HAVE_IBV_DEVICE_STRIDING_RQ_SUPPORT 805 dv_attr.comp_mask |= MLX5DV_CONTEXT_MASK_STRIDING_RQ; 806 #endif 807 mlx5_glue->dv_query_device(ctx, &dv_attr); 808 if (dv_attr.flags & MLX5DV_CONTEXT_FLAGS_MPW_ALLOWED) { 809 if (dv_attr.flags & MLX5DV_CONTEXT_FLAGS_ENHANCED_MPW) { 810 DRV_LOG(DEBUG, "enhanced MPW is supported"); 811 mps = MLX5_MPW_ENHANCED; 812 } else { 813 DRV_LOG(DEBUG, "MPW is supported"); 814 mps = MLX5_MPW; 815 } 816 } else { 817 DRV_LOG(DEBUG, "MPW isn't supported"); 818 mps = MLX5_MPW_DISABLED; 819 } 820 #ifdef HAVE_IBV_MLX5_MOD_SWP 821 if (dv_attr.comp_mask & MLX5DV_CONTEXT_MASK_SWP) 822 swp = dv_attr.sw_parsing_caps.sw_parsing_offloads; 823 DRV_LOG(DEBUG, "SWP support: %u", swp); 824 #endif 825 config.swp = !!swp; 826 #ifdef HAVE_IBV_DEVICE_STRIDING_RQ_SUPPORT 827 if (dv_attr.comp_mask & MLX5DV_CONTEXT_MASK_STRIDING_RQ) { 828 struct mlx5dv_striding_rq_caps mprq_caps = 829 dv_attr.striding_rq_caps; 830 831 DRV_LOG(DEBUG, "\tmin_single_stride_log_num_of_bytes: %d", 832 mprq_caps.min_single_stride_log_num_of_bytes); 833 DRV_LOG(DEBUG, "\tmax_single_stride_log_num_of_bytes: %d", 834 mprq_caps.max_single_stride_log_num_of_bytes); 835 DRV_LOG(DEBUG, "\tmin_single_wqe_log_num_of_strides: %d", 836 mprq_caps.min_single_wqe_log_num_of_strides); 837 DRV_LOG(DEBUG, "\tmax_single_wqe_log_num_of_strides: %d", 838 mprq_caps.max_single_wqe_log_num_of_strides); 839 DRV_LOG(DEBUG, "\tsupported_qpts: %d", 840 mprq_caps.supported_qpts); 841 DRV_LOG(DEBUG, "device supports Multi-Packet RQ"); 842 mprq = 1; 843 mprq_min_stride_size_n = 844 mprq_caps.min_single_stride_log_num_of_bytes; 845 mprq_max_stride_size_n = 846 mprq_caps.max_single_stride_log_num_of_bytes; 847 mprq_min_stride_num_n = 848 mprq_caps.min_single_wqe_log_num_of_strides; 849 mprq_max_stride_num_n = 850 mprq_caps.max_single_wqe_log_num_of_strides; 851 config.mprq.stride_num_n = RTE_MAX(MLX5_MPRQ_STRIDE_NUM_N, 852 mprq_min_stride_num_n); 853 } 854 #endif 855 if (RTE_CACHE_LINE_SIZE == 128 && 856 !(dv_attr.flags & MLX5DV_CONTEXT_FLAGS_CQE_128B_COMP)) 857 cqe_comp = 0; 858 else 859 cqe_comp = 1; 860 config.cqe_comp = cqe_comp; 861 #ifdef HAVE_IBV_MLX5_MOD_CQE_128B_PAD 862 /* Whether device supports 128B Rx CQE padding. */ 863 cqe_pad = RTE_CACHE_LINE_SIZE == 128 && 864 (dv_attr.flags & MLX5DV_CONTEXT_FLAGS_CQE_128B_PAD); 865 #endif 866 #ifdef HAVE_IBV_DEVICE_TUNNEL_SUPPORT 867 if (dv_attr.comp_mask & MLX5DV_CONTEXT_MASK_TUNNEL_OFFLOADS) { 868 tunnel_en = ((dv_attr.tunnel_offloads_caps & 869 MLX5DV_RAW_PACKET_CAP_TUNNELED_OFFLOAD_VXLAN) && 870 (dv_attr.tunnel_offloads_caps & 871 MLX5DV_RAW_PACKET_CAP_TUNNELED_OFFLOAD_GRE)); 872 } 873 DRV_LOG(DEBUG, "tunnel offloading is %ssupported", 874 tunnel_en ? "" : "not "); 875 #else 876 DRV_LOG(WARNING, 877 "tunnel offloading disabled due to old OFED/rdma-core version"); 878 #endif 879 config.tunnel_en = tunnel_en; 880 #ifdef HAVE_IBV_DEVICE_MPLS_SUPPORT 881 mpls_en = ((dv_attr.tunnel_offloads_caps & 882 MLX5DV_RAW_PACKET_CAP_TUNNELED_OFFLOAD_CW_MPLS_OVER_GRE) && 883 (dv_attr.tunnel_offloads_caps & 884 MLX5DV_RAW_PACKET_CAP_TUNNELED_OFFLOAD_CW_MPLS_OVER_UDP)); 885 DRV_LOG(DEBUG, "MPLS over GRE/UDP tunnel offloading is %ssupported", 886 mpls_en ? "" : "not "); 887 #else 888 DRV_LOG(WARNING, "MPLS over GRE/UDP tunnel offloading disabled due to" 889 " old OFED/rdma-core version or firmware configuration"); 890 #endif 891 config.mpls_en = mpls_en; 892 err = mlx5_glue->query_device_ex(ctx, NULL, &attr); 893 if (err) { 894 DEBUG("ibv_query_device_ex() failed"); 895 goto error; 896 } 897 DRV_LOG(DEBUG, "naming Ethernet device \"%s\"", name); 898 if (rte_eal_process_type() == RTE_PROC_SECONDARY) { 899 eth_dev = rte_eth_dev_attach_secondary(name); 900 if (eth_dev == NULL) { 901 DRV_LOG(ERR, "can not attach rte ethdev"); 902 rte_errno = ENOMEM; 903 err = rte_errno; 904 goto error; 905 } 906 eth_dev->device = dpdk_dev; 907 eth_dev->dev_ops = &mlx5_dev_sec_ops; 908 err = mlx5_uar_init_secondary(eth_dev); 909 if (err) { 910 err = rte_errno; 911 goto error; 912 } 913 /* Receive command fd from primary process */ 914 err = mlx5_socket_connect(eth_dev); 915 if (err < 0) { 916 err = rte_errno; 917 goto error; 918 } 919 /* Remap UAR for Tx queues. */ 920 err = mlx5_tx_uar_remap(eth_dev, err); 921 if (err) { 922 err = rte_errno; 923 goto error; 924 } 925 /* 926 * Ethdev pointer is still required as input since 927 * the primary device is not accessible from the 928 * secondary process. 929 */ 930 eth_dev->rx_pkt_burst = mlx5_select_rx_function(eth_dev); 931 eth_dev->tx_pkt_burst = mlx5_select_tx_function(eth_dev); 932 claim_zero(mlx5_glue->close_device(ctx)); 933 return eth_dev; 934 } 935 /* Check port status. */ 936 err = mlx5_glue->query_port(ctx, 1, &port_attr); 937 if (err) { 938 DRV_LOG(ERR, "port query failed: %s", strerror(err)); 939 goto error; 940 } 941 if (port_attr.link_layer != IBV_LINK_LAYER_ETHERNET) { 942 DRV_LOG(ERR, "port is not configured in Ethernet mode"); 943 err = EINVAL; 944 goto error; 945 } 946 if (port_attr.state != IBV_PORT_ACTIVE) 947 DRV_LOG(DEBUG, "port is not active: \"%s\" (%d)", 948 mlx5_glue->port_state_str(port_attr.state), 949 port_attr.state); 950 /* Allocate protection domain. */ 951 pd = mlx5_glue->alloc_pd(ctx); 952 if (pd == NULL) { 953 DRV_LOG(ERR, "PD allocation failure"); 954 err = ENOMEM; 955 goto error; 956 } 957 priv = rte_zmalloc("ethdev private structure", 958 sizeof(*priv), 959 RTE_CACHE_LINE_SIZE); 960 if (priv == NULL) { 961 DRV_LOG(ERR, "priv allocation failure"); 962 err = ENOMEM; 963 goto error; 964 } 965 priv->ctx = ctx; 966 strncpy(priv->ibdev_name, priv->ctx->device->name, 967 sizeof(priv->ibdev_name)); 968 strncpy(priv->ibdev_path, priv->ctx->device->ibdev_path, 969 sizeof(priv->ibdev_path)); 970 priv->device_attr = attr; 971 priv->pd = pd; 972 priv->mtu = ETHER_MTU; 973 #ifndef RTE_ARCH_64 974 /* Initialize UAR access locks for 32bit implementations. */ 975 rte_spinlock_init(&priv->uar_lock_cq); 976 for (i = 0; i < MLX5_UAR_PAGE_NUM_MAX; i++) 977 rte_spinlock_init(&priv->uar_lock[i]); 978 #endif 979 /* Some internal functions rely on Netlink sockets, open them now. */ 980 priv->nl_socket_rdma = mlx5_nl_init(NETLINK_RDMA); 981 priv->nl_socket_route = mlx5_nl_init(NETLINK_ROUTE); 982 priv->nl_sn = 0; 983 priv->representor = !!switch_info->representor; 984 priv->domain_id = RTE_ETH_DEV_SWITCH_DOMAIN_ID_INVALID; 985 priv->representor_id = 986 switch_info->representor ? switch_info->port_name : -1; 987 /* 988 * Look for sibling devices in order to reuse their switch domain 989 * if any, otherwise allocate one. 990 */ 991 i = mlx5_dev_to_port_id(dpdk_dev, NULL, 0); 992 if (i > 0) { 993 uint16_t port_id[i]; 994 995 i = RTE_MIN(mlx5_dev_to_port_id(dpdk_dev, port_id, i), i); 996 while (i--) { 997 const struct priv *opriv = 998 rte_eth_devices[port_id[i]].data->dev_private; 999 1000 if (!opriv || 1001 opriv->domain_id == 1002 RTE_ETH_DEV_SWITCH_DOMAIN_ID_INVALID) 1003 continue; 1004 priv->domain_id = opriv->domain_id; 1005 break; 1006 } 1007 } 1008 if (priv->domain_id == RTE_ETH_DEV_SWITCH_DOMAIN_ID_INVALID) { 1009 err = rte_eth_switch_domain_alloc(&priv->domain_id); 1010 if (err) { 1011 err = rte_errno; 1012 DRV_LOG(ERR, "unable to allocate switch domain: %s", 1013 strerror(rte_errno)); 1014 goto error; 1015 } 1016 own_domain_id = 1; 1017 } 1018 err = mlx5_args(&config, dpdk_dev->devargs); 1019 if (err) { 1020 err = rte_errno; 1021 DRV_LOG(ERR, "failed to process device arguments: %s", 1022 strerror(rte_errno)); 1023 goto error; 1024 } 1025 config.hw_csum = !!(attr.device_cap_flags_ex & IBV_DEVICE_RAW_IP_CSUM); 1026 DRV_LOG(DEBUG, "checksum offloading is %ssupported", 1027 (config.hw_csum ? "" : "not ")); 1028 #if !defined(HAVE_IBV_DEVICE_COUNTERS_SET_V42) && \ 1029 !defined(HAVE_IBV_DEVICE_COUNTERS_SET_V45) 1030 DRV_LOG(DEBUG, "counters are not supported"); 1031 #endif 1032 #ifndef HAVE_IBV_FLOW_DV_SUPPORT 1033 if (config.dv_flow_en) { 1034 DRV_LOG(WARNING, "DV flow is not supported"); 1035 config.dv_flow_en = 0; 1036 } 1037 #endif 1038 config.ind_table_max_size = 1039 attr.rss_caps.max_rwq_indirection_table_size; 1040 /* 1041 * Remove this check once DPDK supports larger/variable 1042 * indirection tables. 1043 */ 1044 if (config.ind_table_max_size > (unsigned int)ETH_RSS_RETA_SIZE_512) 1045 config.ind_table_max_size = ETH_RSS_RETA_SIZE_512; 1046 DRV_LOG(DEBUG, "maximum Rx indirection table size is %u", 1047 config.ind_table_max_size); 1048 config.hw_vlan_strip = !!(attr.raw_packet_caps & 1049 IBV_RAW_PACKET_CAP_CVLAN_STRIPPING); 1050 DRV_LOG(DEBUG, "VLAN stripping is %ssupported", 1051 (config.hw_vlan_strip ? "" : "not ")); 1052 config.hw_fcs_strip = !!(attr.raw_packet_caps & 1053 IBV_RAW_PACKET_CAP_SCATTER_FCS); 1054 DRV_LOG(DEBUG, "FCS stripping configuration is %ssupported", 1055 (config.hw_fcs_strip ? "" : "not ")); 1056 #ifdef HAVE_IBV_WQ_FLAG_RX_END_PADDING 1057 config.hw_padding = !!attr.rx_pad_end_addr_align; 1058 #endif 1059 DRV_LOG(DEBUG, "hardware Rx end alignment padding is %ssupported", 1060 (config.hw_padding ? "" : "not ")); 1061 config.tso = (attr.tso_caps.max_tso > 0 && 1062 (attr.tso_caps.supported_qpts & 1063 (1 << IBV_QPT_RAW_PACKET))); 1064 if (config.tso) 1065 config.tso_max_payload_sz = attr.tso_caps.max_tso; 1066 /* 1067 * MPW is disabled by default, while the Enhanced MPW is enabled 1068 * by default. 1069 */ 1070 if (config.mps == MLX5_ARG_UNSET) 1071 config.mps = (mps == MLX5_MPW_ENHANCED) ? MLX5_MPW_ENHANCED : 1072 MLX5_MPW_DISABLED; 1073 else 1074 config.mps = config.mps ? mps : MLX5_MPW_DISABLED; 1075 DRV_LOG(INFO, "%sMPS is %s", 1076 config.mps == MLX5_MPW_ENHANCED ? "enhanced " : "", 1077 config.mps != MLX5_MPW_DISABLED ? "enabled" : "disabled"); 1078 if (config.cqe_comp && !cqe_comp) { 1079 DRV_LOG(WARNING, "Rx CQE compression isn't supported"); 1080 config.cqe_comp = 0; 1081 } 1082 if (config.cqe_pad && !cqe_pad) { 1083 DRV_LOG(WARNING, "Rx CQE padding isn't supported"); 1084 config.cqe_pad = 0; 1085 } else if (config.cqe_pad) { 1086 DRV_LOG(INFO, "Rx CQE padding is enabled"); 1087 } 1088 if (config.mprq.enabled && mprq) { 1089 if (config.mprq.stride_num_n > mprq_max_stride_num_n || 1090 config.mprq.stride_num_n < mprq_min_stride_num_n) { 1091 config.mprq.stride_num_n = 1092 RTE_MAX(MLX5_MPRQ_STRIDE_NUM_N, 1093 mprq_min_stride_num_n); 1094 DRV_LOG(WARNING, 1095 "the number of strides" 1096 " for Multi-Packet RQ is out of range," 1097 " setting default value (%u)", 1098 1 << config.mprq.stride_num_n); 1099 } 1100 config.mprq.min_stride_size_n = mprq_min_stride_size_n; 1101 config.mprq.max_stride_size_n = mprq_max_stride_size_n; 1102 } else if (config.mprq.enabled && !mprq) { 1103 DRV_LOG(WARNING, "Multi-Packet RQ isn't supported"); 1104 config.mprq.enabled = 0; 1105 } 1106 eth_dev = rte_eth_dev_allocate(name); 1107 if (eth_dev == NULL) { 1108 DRV_LOG(ERR, "can not allocate rte ethdev"); 1109 err = ENOMEM; 1110 goto error; 1111 } 1112 /* Flag to call rte_eth_dev_release_port() in rte_eth_dev_close(). */ 1113 eth_dev->data->dev_flags |= RTE_ETH_DEV_CLOSE_REMOVE; 1114 if (priv->representor) { 1115 eth_dev->data->dev_flags |= RTE_ETH_DEV_REPRESENTOR; 1116 eth_dev->data->representor_id = priv->representor_id; 1117 } 1118 eth_dev->data->dev_private = priv; 1119 priv->dev_data = eth_dev->data; 1120 eth_dev->data->mac_addrs = priv->mac; 1121 eth_dev->device = dpdk_dev; 1122 err = mlx5_uar_init_primary(eth_dev); 1123 if (err) { 1124 err = rte_errno; 1125 goto error; 1126 } 1127 /* Configure the first MAC address by default. */ 1128 if (mlx5_get_mac(eth_dev, &mac.addr_bytes)) { 1129 DRV_LOG(ERR, 1130 "port %u cannot get MAC address, is mlx5_en" 1131 " loaded? (errno: %s)", 1132 eth_dev->data->port_id, strerror(rte_errno)); 1133 err = ENODEV; 1134 goto error; 1135 } 1136 DRV_LOG(INFO, 1137 "port %u MAC address is %02x:%02x:%02x:%02x:%02x:%02x", 1138 eth_dev->data->port_id, 1139 mac.addr_bytes[0], mac.addr_bytes[1], 1140 mac.addr_bytes[2], mac.addr_bytes[3], 1141 mac.addr_bytes[4], mac.addr_bytes[5]); 1142 #ifndef NDEBUG 1143 { 1144 char ifname[IF_NAMESIZE]; 1145 1146 if (mlx5_get_ifname(eth_dev, &ifname) == 0) 1147 DRV_LOG(DEBUG, "port %u ifname is \"%s\"", 1148 eth_dev->data->port_id, ifname); 1149 else 1150 DRV_LOG(DEBUG, "port %u ifname is unknown", 1151 eth_dev->data->port_id); 1152 } 1153 #endif 1154 /* Get actual MTU if possible. */ 1155 err = mlx5_get_mtu(eth_dev, &priv->mtu); 1156 if (err) { 1157 err = rte_errno; 1158 goto error; 1159 } 1160 DRV_LOG(DEBUG, "port %u MTU is %u", eth_dev->data->port_id, 1161 priv->mtu); 1162 /* Initialize burst functions to prevent crashes before link-up. */ 1163 eth_dev->rx_pkt_burst = removed_rx_burst; 1164 eth_dev->tx_pkt_burst = removed_tx_burst; 1165 eth_dev->dev_ops = &mlx5_dev_ops; 1166 /* Register MAC address. */ 1167 claim_zero(mlx5_mac_addr_add(eth_dev, &mac, 0, 0)); 1168 if (config.vf && config.vf_nl_en) 1169 mlx5_nl_mac_addr_sync(eth_dev); 1170 priv->tcf_context = mlx5_flow_tcf_context_create(); 1171 if (!priv->tcf_context) { 1172 err = -rte_errno; 1173 DRV_LOG(WARNING, 1174 "flow rules relying on switch offloads will not be" 1175 " supported: cannot open libmnl socket: %s", 1176 strerror(rte_errno)); 1177 } else { 1178 struct rte_flow_error error; 1179 unsigned int ifindex = mlx5_ifindex(eth_dev); 1180 1181 if (!ifindex) { 1182 err = -rte_errno; 1183 error.message = 1184 "cannot retrieve network interface index"; 1185 } else { 1186 err = mlx5_flow_tcf_init(priv->tcf_context, 1187 ifindex, &error); 1188 } 1189 if (err) { 1190 DRV_LOG(WARNING, 1191 "flow rules relying on switch offloads will" 1192 " not be supported: %s: %s", 1193 error.message, strerror(rte_errno)); 1194 mlx5_flow_tcf_context_destroy(priv->tcf_context); 1195 priv->tcf_context = NULL; 1196 } 1197 } 1198 TAILQ_INIT(&priv->flows); 1199 TAILQ_INIT(&priv->ctrl_flows); 1200 /* Hint libmlx5 to use PMD allocator for data plane resources */ 1201 struct mlx5dv_ctx_allocators alctr = { 1202 .alloc = &mlx5_alloc_verbs_buf, 1203 .free = &mlx5_free_verbs_buf, 1204 .data = priv, 1205 }; 1206 mlx5_glue->dv_set_context_attr(ctx, MLX5DV_CTX_ATTR_BUF_ALLOCATORS, 1207 (void *)((uintptr_t)&alctr)); 1208 /* Bring Ethernet device up. */ 1209 DRV_LOG(DEBUG, "port %u forcing Ethernet interface up", 1210 eth_dev->data->port_id); 1211 mlx5_set_link_up(eth_dev); 1212 /* 1213 * Even though the interrupt handler is not installed yet, 1214 * interrupts will still trigger on the asyn_fd from 1215 * Verbs context returned by ibv_open_device(). 1216 */ 1217 mlx5_link_update(eth_dev, 0); 1218 /* Store device configuration on private structure. */ 1219 priv->config = config; 1220 /* Supported Verbs flow priority number detection. */ 1221 err = mlx5_flow_discover_priorities(eth_dev); 1222 if (err < 0) 1223 goto error; 1224 priv->config.flow_prio = err; 1225 /* 1226 * Once the device is added to the list of memory event 1227 * callback, its global MR cache table cannot be expanded 1228 * on the fly because of deadlock. If it overflows, lookup 1229 * should be done by searching MR list linearly, which is slow. 1230 */ 1231 err = mlx5_mr_btree_init(&priv->mr.cache, 1232 MLX5_MR_BTREE_CACHE_N * 2, 1233 eth_dev->device->numa_node); 1234 if (err) { 1235 err = rte_errno; 1236 goto error; 1237 } 1238 /* Add device to memory callback list. */ 1239 rte_rwlock_write_lock(&mlx5_shared_data->mem_event_rwlock); 1240 LIST_INSERT_HEAD(&mlx5_shared_data->mem_event_cb_list, 1241 priv, mem_event_cb); 1242 rte_rwlock_write_unlock(&mlx5_shared_data->mem_event_rwlock); 1243 return eth_dev; 1244 error: 1245 if (priv) { 1246 if (priv->nl_socket_route >= 0) 1247 close(priv->nl_socket_route); 1248 if (priv->nl_socket_rdma >= 0) 1249 close(priv->nl_socket_rdma); 1250 if (priv->tcf_context) 1251 mlx5_flow_tcf_context_destroy(priv->tcf_context); 1252 if (own_domain_id) 1253 claim_zero(rte_eth_switch_domain_free(priv->domain_id)); 1254 rte_free(priv); 1255 if (eth_dev != NULL) 1256 eth_dev->data->dev_private = NULL; 1257 } 1258 if (pd) 1259 claim_zero(mlx5_glue->dealloc_pd(pd)); 1260 if (eth_dev != NULL) { 1261 /* mac_addrs must not be freed alone because part of dev_private */ 1262 eth_dev->data->mac_addrs = NULL; 1263 rte_eth_dev_release_port(eth_dev); 1264 } 1265 if (ctx) 1266 claim_zero(mlx5_glue->close_device(ctx)); 1267 assert(err > 0); 1268 rte_errno = err; 1269 return NULL; 1270 } 1271 1272 /** Data associated with devices to spawn. */ 1273 struct mlx5_dev_spawn_data { 1274 unsigned int ifindex; /**< Network interface index. */ 1275 struct mlx5_switch_info info; /**< Switch information. */ 1276 struct ibv_device *ibv_dev; /**< Associated IB device. */ 1277 struct rte_eth_dev *eth_dev; /**< Associated Ethernet device. */ 1278 }; 1279 1280 /** 1281 * Comparison callback to sort device data. 1282 * 1283 * This is meant to be used with qsort(). 1284 * 1285 * @param a[in] 1286 * Pointer to pointer to first data object. 1287 * @param b[in] 1288 * Pointer to pointer to second data object. 1289 * 1290 * @return 1291 * 0 if both objects are equal, less than 0 if the first argument is less 1292 * than the second, greater than 0 otherwise. 1293 */ 1294 static int 1295 mlx5_dev_spawn_data_cmp(const void *a, const void *b) 1296 { 1297 const struct mlx5_switch_info *si_a = 1298 &((const struct mlx5_dev_spawn_data *)a)->info; 1299 const struct mlx5_switch_info *si_b = 1300 &((const struct mlx5_dev_spawn_data *)b)->info; 1301 int ret; 1302 1303 /* Master device first. */ 1304 ret = si_b->master - si_a->master; 1305 if (ret) 1306 return ret; 1307 /* Then representor devices. */ 1308 ret = si_b->representor - si_a->representor; 1309 if (ret) 1310 return ret; 1311 /* Unidentified devices come last in no specific order. */ 1312 if (!si_a->representor) 1313 return 0; 1314 /* Order representors by name. */ 1315 return si_a->port_name - si_b->port_name; 1316 } 1317 1318 /** 1319 * DPDK callback to register a PCI device. 1320 * 1321 * This function spawns Ethernet devices out of a given PCI device. 1322 * 1323 * @param[in] pci_drv 1324 * PCI driver structure (mlx5_driver). 1325 * @param[in] pci_dev 1326 * PCI device information. 1327 * 1328 * @return 1329 * 0 on success, a negative errno value otherwise and rte_errno is set. 1330 */ 1331 static int 1332 mlx5_pci_probe(struct rte_pci_driver *pci_drv __rte_unused, 1333 struct rte_pci_device *pci_dev) 1334 { 1335 struct ibv_device **ibv_list; 1336 unsigned int n = 0; 1337 struct mlx5_dev_config dev_config; 1338 int ret; 1339 1340 assert(pci_drv == &mlx5_driver); 1341 errno = 0; 1342 ibv_list = mlx5_glue->get_device_list(&ret); 1343 if (!ibv_list) { 1344 rte_errno = errno ? errno : ENOSYS; 1345 DRV_LOG(ERR, "cannot list devices, is ib_uverbs loaded?"); 1346 return -rte_errno; 1347 } 1348 1349 struct ibv_device *ibv_match[ret + 1]; 1350 1351 while (ret-- > 0) { 1352 struct rte_pci_addr pci_addr; 1353 1354 DRV_LOG(DEBUG, "checking device \"%s\"", ibv_list[ret]->name); 1355 if (mlx5_ibv_device_to_pci_addr(ibv_list[ret], &pci_addr)) 1356 continue; 1357 if (pci_dev->addr.domain != pci_addr.domain || 1358 pci_dev->addr.bus != pci_addr.bus || 1359 pci_dev->addr.devid != pci_addr.devid || 1360 pci_dev->addr.function != pci_addr.function) 1361 continue; 1362 DRV_LOG(INFO, "PCI information matches for device \"%s\"", 1363 ibv_list[ret]->name); 1364 ibv_match[n++] = ibv_list[ret]; 1365 } 1366 ibv_match[n] = NULL; 1367 1368 struct mlx5_dev_spawn_data list[n]; 1369 int nl_route = n ? mlx5_nl_init(NETLINK_ROUTE) : -1; 1370 int nl_rdma = n ? mlx5_nl_init(NETLINK_RDMA) : -1; 1371 unsigned int i; 1372 unsigned int u; 1373 1374 /* 1375 * The existence of several matching entries (n > 1) means port 1376 * representors have been instantiated. No existing Verbs call nor 1377 * /sys entries can tell them apart, this can only be done through 1378 * Netlink calls assuming kernel drivers are recent enough to 1379 * support them. 1380 * 1381 * In the event of identification failure through Netlink, try again 1382 * through sysfs, then either: 1383 * 1384 * 1. No device matches (n == 0), complain and bail out. 1385 * 2. A single IB device matches (n == 1) and is not a representor, 1386 * assume no switch support. 1387 * 3. Otherwise no safe assumptions can be made; complain louder and 1388 * bail out. 1389 */ 1390 for (i = 0; i != n; ++i) { 1391 list[i].ibv_dev = ibv_match[i]; 1392 list[i].eth_dev = NULL; 1393 if (nl_rdma < 0) 1394 list[i].ifindex = 0; 1395 else 1396 list[i].ifindex = mlx5_nl_ifindex 1397 (nl_rdma, list[i].ibv_dev->name); 1398 if (nl_route < 0 || 1399 !list[i].ifindex || 1400 mlx5_nl_switch_info(nl_route, list[i].ifindex, 1401 &list[i].info) || 1402 ((!list[i].info.representor && !list[i].info.master) && 1403 mlx5_sysfs_switch_info(list[i].ifindex, &list[i].info))) { 1404 list[i].ifindex = 0; 1405 memset(&list[i].info, 0, sizeof(list[i].info)); 1406 continue; 1407 } 1408 } 1409 if (nl_rdma >= 0) 1410 close(nl_rdma); 1411 if (nl_route >= 0) 1412 close(nl_route); 1413 /* Count unidentified devices. */ 1414 for (u = 0, i = 0; i != n; ++i) 1415 if (!list[i].info.master && !list[i].info.representor) 1416 ++u; 1417 if (u) { 1418 if (n == 1 && u == 1) { 1419 /* Case #2. */ 1420 DRV_LOG(INFO, "no switch support detected"); 1421 } else { 1422 /* Case #3. */ 1423 DRV_LOG(ERR, 1424 "unable to tell which of the matching devices" 1425 " is the master (lack of kernel support?)"); 1426 n = 0; 1427 } 1428 } 1429 /* 1430 * Sort list to probe devices in natural order for users convenience 1431 * (i.e. master first, then representors from lowest to highest ID). 1432 */ 1433 if (n) 1434 qsort(list, n, sizeof(*list), mlx5_dev_spawn_data_cmp); 1435 /* Default configuration. */ 1436 dev_config = (struct mlx5_dev_config){ 1437 .mps = MLX5_ARG_UNSET, 1438 .tx_vec_en = 1, 1439 .rx_vec_en = 1, 1440 .txq_inline = MLX5_ARG_UNSET, 1441 .txqs_inline = MLX5_ARG_UNSET, 1442 .txqs_vec = MLX5_ARG_UNSET, 1443 .inline_max_packet_sz = MLX5_ARG_UNSET, 1444 .vf_nl_en = 1, 1445 .mprq = { 1446 .enabled = 0, /* Disabled by default. */ 1447 .stride_num_n = MLX5_MPRQ_STRIDE_NUM_N, 1448 .max_memcpy_len = MLX5_MPRQ_MEMCPY_DEFAULT_LEN, 1449 .min_rxqs_num = MLX5_MPRQ_MIN_RXQS, 1450 }, 1451 }; 1452 /* Device speicific configuration. */ 1453 switch (pci_dev->id.device_id) { 1454 case PCI_DEVICE_ID_MELLANOX_CONNECTX5BF: 1455 dev_config.txqs_vec = MLX5_VPMD_MAX_TXQS_BLUEFIELD; 1456 break; 1457 case PCI_DEVICE_ID_MELLANOX_CONNECTX4VF: 1458 case PCI_DEVICE_ID_MELLANOX_CONNECTX4LXVF: 1459 case PCI_DEVICE_ID_MELLANOX_CONNECTX5VF: 1460 case PCI_DEVICE_ID_MELLANOX_CONNECTX5EXVF: 1461 dev_config.vf = 1; 1462 break; 1463 default: 1464 break; 1465 } 1466 /* Set architecture-dependent default value if unset. */ 1467 if (dev_config.txqs_vec == MLX5_ARG_UNSET) 1468 dev_config.txqs_vec = MLX5_VPMD_MAX_TXQS; 1469 for (i = 0; i != n; ++i) { 1470 uint32_t restore; 1471 1472 list[i].eth_dev = mlx5_dev_spawn(&pci_dev->device, 1473 list[i].ibv_dev, dev_config, 1474 &list[i].info); 1475 if (!list[i].eth_dev) { 1476 if (rte_errno != EBUSY && rte_errno != EEXIST) 1477 break; 1478 /* Device is disabled or already spawned. Ignore it. */ 1479 continue; 1480 } 1481 restore = list[i].eth_dev->data->dev_flags; 1482 rte_eth_copy_pci_info(list[i].eth_dev, pci_dev); 1483 /* Restore non-PCI flags cleared by the above call. */ 1484 list[i].eth_dev->data->dev_flags |= restore; 1485 rte_eth_dev_probing_finish(list[i].eth_dev); 1486 } 1487 mlx5_glue->free_device_list(ibv_list); 1488 if (!n) { 1489 DRV_LOG(WARNING, 1490 "no Verbs device matches PCI device " PCI_PRI_FMT "," 1491 " are kernel drivers loaded?", 1492 pci_dev->addr.domain, pci_dev->addr.bus, 1493 pci_dev->addr.devid, pci_dev->addr.function); 1494 rte_errno = ENOENT; 1495 ret = -rte_errno; 1496 } else if (i != n) { 1497 DRV_LOG(ERR, 1498 "probe of PCI device " PCI_PRI_FMT " aborted after" 1499 " encountering an error: %s", 1500 pci_dev->addr.domain, pci_dev->addr.bus, 1501 pci_dev->addr.devid, pci_dev->addr.function, 1502 strerror(rte_errno)); 1503 ret = -rte_errno; 1504 /* Roll back. */ 1505 while (i--) { 1506 if (!list[i].eth_dev) 1507 continue; 1508 mlx5_dev_close(list[i].eth_dev); 1509 /* mac_addrs must not be freed because in dev_private */ 1510 list[i].eth_dev->data->mac_addrs = NULL; 1511 claim_zero(rte_eth_dev_release_port(list[i].eth_dev)); 1512 } 1513 /* Restore original error. */ 1514 rte_errno = -ret; 1515 } else { 1516 ret = 0; 1517 } 1518 return ret; 1519 } 1520 1521 /** 1522 * DPDK callback to remove a PCI device. 1523 * 1524 * This function removes all Ethernet devices belong to a given PCI device. 1525 * 1526 * @param[in] pci_dev 1527 * Pointer to the PCI device. 1528 * 1529 * @return 1530 * 0 on success, the function cannot fail. 1531 */ 1532 static int 1533 mlx5_pci_remove(struct rte_pci_device *pci_dev) 1534 { 1535 uint16_t port_id; 1536 struct rte_eth_dev *port; 1537 1538 for (port_id = 0; port_id < RTE_MAX_ETHPORTS; port_id++) { 1539 port = &rte_eth_devices[port_id]; 1540 if (port->state != RTE_ETH_DEV_UNUSED && 1541 port->device == &pci_dev->device) 1542 rte_eth_dev_close(port_id); 1543 } 1544 return 0; 1545 } 1546 1547 static const struct rte_pci_id mlx5_pci_id_map[] = { 1548 { 1549 RTE_PCI_DEVICE(PCI_VENDOR_ID_MELLANOX, 1550 PCI_DEVICE_ID_MELLANOX_CONNECTX4) 1551 }, 1552 { 1553 RTE_PCI_DEVICE(PCI_VENDOR_ID_MELLANOX, 1554 PCI_DEVICE_ID_MELLANOX_CONNECTX4VF) 1555 }, 1556 { 1557 RTE_PCI_DEVICE(PCI_VENDOR_ID_MELLANOX, 1558 PCI_DEVICE_ID_MELLANOX_CONNECTX4LX) 1559 }, 1560 { 1561 RTE_PCI_DEVICE(PCI_VENDOR_ID_MELLANOX, 1562 PCI_DEVICE_ID_MELLANOX_CONNECTX4LXVF) 1563 }, 1564 { 1565 RTE_PCI_DEVICE(PCI_VENDOR_ID_MELLANOX, 1566 PCI_DEVICE_ID_MELLANOX_CONNECTX5) 1567 }, 1568 { 1569 RTE_PCI_DEVICE(PCI_VENDOR_ID_MELLANOX, 1570 PCI_DEVICE_ID_MELLANOX_CONNECTX5VF) 1571 }, 1572 { 1573 RTE_PCI_DEVICE(PCI_VENDOR_ID_MELLANOX, 1574 PCI_DEVICE_ID_MELLANOX_CONNECTX5EX) 1575 }, 1576 { 1577 RTE_PCI_DEVICE(PCI_VENDOR_ID_MELLANOX, 1578 PCI_DEVICE_ID_MELLANOX_CONNECTX5EXVF) 1579 }, 1580 { 1581 RTE_PCI_DEVICE(PCI_VENDOR_ID_MELLANOX, 1582 PCI_DEVICE_ID_MELLANOX_CONNECTX5BF) 1583 }, 1584 { 1585 RTE_PCI_DEVICE(PCI_VENDOR_ID_MELLANOX, 1586 PCI_DEVICE_ID_MELLANOX_CONNECTX5BFVF) 1587 }, 1588 { 1589 RTE_PCI_DEVICE(PCI_VENDOR_ID_MELLANOX, 1590 PCI_DEVICE_ID_MELLANOX_CONNECTX6) 1591 }, 1592 { 1593 RTE_PCI_DEVICE(PCI_VENDOR_ID_MELLANOX, 1594 PCI_DEVICE_ID_MELLANOX_CONNECTX6VF) 1595 }, 1596 { 1597 .vendor_id = 0 1598 } 1599 }; 1600 1601 static struct rte_pci_driver mlx5_driver = { 1602 .driver = { 1603 .name = MLX5_DRIVER_NAME 1604 }, 1605 .id_table = mlx5_pci_id_map, 1606 .probe = mlx5_pci_probe, 1607 .remove = mlx5_pci_remove, 1608 .drv_flags = (RTE_PCI_DRV_INTR_LSC | RTE_PCI_DRV_INTR_RMV | 1609 RTE_PCI_DRV_PROBE_AGAIN), 1610 }; 1611 1612 #ifdef RTE_LIBRTE_MLX5_DLOPEN_DEPS 1613 1614 /** 1615 * Suffix RTE_EAL_PMD_PATH with "-glue". 1616 * 1617 * This function performs a sanity check on RTE_EAL_PMD_PATH before 1618 * suffixing its last component. 1619 * 1620 * @param buf[out] 1621 * Output buffer, should be large enough otherwise NULL is returned. 1622 * @param size 1623 * Size of @p out. 1624 * 1625 * @return 1626 * Pointer to @p buf or @p NULL in case suffix cannot be appended. 1627 */ 1628 static char * 1629 mlx5_glue_path(char *buf, size_t size) 1630 { 1631 static const char *const bad[] = { "/", ".", "..", NULL }; 1632 const char *path = RTE_EAL_PMD_PATH; 1633 size_t len = strlen(path); 1634 size_t off; 1635 int i; 1636 1637 while (len && path[len - 1] == '/') 1638 --len; 1639 for (off = len; off && path[off - 1] != '/'; --off) 1640 ; 1641 for (i = 0; bad[i]; ++i) 1642 if (!strncmp(path + off, bad[i], (int)(len - off))) 1643 goto error; 1644 i = snprintf(buf, size, "%.*s-glue", (int)len, path); 1645 if (i == -1 || (size_t)i >= size) 1646 goto error; 1647 return buf; 1648 error: 1649 DRV_LOG(ERR, 1650 "unable to append \"-glue\" to last component of" 1651 " RTE_EAL_PMD_PATH (\"" RTE_EAL_PMD_PATH "\")," 1652 " please re-configure DPDK"); 1653 return NULL; 1654 } 1655 1656 /** 1657 * Initialization routine for run-time dependency on rdma-core. 1658 */ 1659 static int 1660 mlx5_glue_init(void) 1661 { 1662 char glue_path[sizeof(RTE_EAL_PMD_PATH) - 1 + sizeof("-glue")]; 1663 const char *path[] = { 1664 /* 1665 * A basic security check is necessary before trusting 1666 * MLX5_GLUE_PATH, which may override RTE_EAL_PMD_PATH. 1667 */ 1668 (geteuid() == getuid() && getegid() == getgid() ? 1669 getenv("MLX5_GLUE_PATH") : NULL), 1670 /* 1671 * When RTE_EAL_PMD_PATH is set, use its glue-suffixed 1672 * variant, otherwise let dlopen() look up libraries on its 1673 * own. 1674 */ 1675 (*RTE_EAL_PMD_PATH ? 1676 mlx5_glue_path(glue_path, sizeof(glue_path)) : ""), 1677 }; 1678 unsigned int i = 0; 1679 void *handle = NULL; 1680 void **sym; 1681 const char *dlmsg; 1682 1683 while (!handle && i != RTE_DIM(path)) { 1684 const char *end; 1685 size_t len; 1686 int ret; 1687 1688 if (!path[i]) { 1689 ++i; 1690 continue; 1691 } 1692 end = strpbrk(path[i], ":;"); 1693 if (!end) 1694 end = path[i] + strlen(path[i]); 1695 len = end - path[i]; 1696 ret = 0; 1697 do { 1698 char name[ret + 1]; 1699 1700 ret = snprintf(name, sizeof(name), "%.*s%s" MLX5_GLUE, 1701 (int)len, path[i], 1702 (!len || *(end - 1) == '/') ? "" : "/"); 1703 if (ret == -1) 1704 break; 1705 if (sizeof(name) != (size_t)ret + 1) 1706 continue; 1707 DRV_LOG(DEBUG, "looking for rdma-core glue as \"%s\"", 1708 name); 1709 handle = dlopen(name, RTLD_LAZY); 1710 break; 1711 } while (1); 1712 path[i] = end + 1; 1713 if (!*end) 1714 ++i; 1715 } 1716 if (!handle) { 1717 rte_errno = EINVAL; 1718 dlmsg = dlerror(); 1719 if (dlmsg) 1720 DRV_LOG(WARNING, "cannot load glue library: %s", dlmsg); 1721 goto glue_error; 1722 } 1723 sym = dlsym(handle, "mlx5_glue"); 1724 if (!sym || !*sym) { 1725 rte_errno = EINVAL; 1726 dlmsg = dlerror(); 1727 if (dlmsg) 1728 DRV_LOG(ERR, "cannot resolve glue symbol: %s", dlmsg); 1729 goto glue_error; 1730 } 1731 mlx5_glue = *sym; 1732 return 0; 1733 glue_error: 1734 if (handle) 1735 dlclose(handle); 1736 DRV_LOG(WARNING, 1737 "cannot initialize PMD due to missing run-time dependency on" 1738 " rdma-core libraries (libibverbs, libmlx5)"); 1739 return -rte_errno; 1740 } 1741 1742 #endif 1743 1744 /** 1745 * Driver initialization routine. 1746 */ 1747 RTE_INIT(rte_mlx5_pmd_init) 1748 { 1749 /* Initialize driver log type. */ 1750 mlx5_logtype = rte_log_register("pmd.net.mlx5"); 1751 if (mlx5_logtype >= 0) 1752 rte_log_set_level(mlx5_logtype, RTE_LOG_NOTICE); 1753 1754 /* Build the static tables for Verbs conversion. */ 1755 mlx5_set_ptype_table(); 1756 mlx5_set_cksum_table(); 1757 mlx5_set_swp_types_table(); 1758 /* 1759 * RDMAV_HUGEPAGES_SAFE tells ibv_fork_init() we intend to use 1760 * huge pages. Calling ibv_fork_init() during init allows 1761 * applications to use fork() safely for purposes other than 1762 * using this PMD, which is not supported in forked processes. 1763 */ 1764 setenv("RDMAV_HUGEPAGES_SAFE", "1", 1); 1765 /* Match the size of Rx completion entry to the size of a cacheline. */ 1766 if (RTE_CACHE_LINE_SIZE == 128) 1767 setenv("MLX5_CQE_SIZE", "128", 0); 1768 /* 1769 * MLX5_DEVICE_FATAL_CLEANUP tells ibv_destroy functions to 1770 * cleanup all the Verbs resources even when the device was removed. 1771 */ 1772 setenv("MLX5_DEVICE_FATAL_CLEANUP", "1", 1); 1773 #ifdef RTE_LIBRTE_MLX5_DLOPEN_DEPS 1774 if (mlx5_glue_init()) 1775 return; 1776 assert(mlx5_glue); 1777 #endif 1778 #ifndef NDEBUG 1779 /* Glue structure must not contain any NULL pointers. */ 1780 { 1781 unsigned int i; 1782 1783 for (i = 0; i != sizeof(*mlx5_glue) / sizeof(void *); ++i) 1784 assert(((const void *const *)mlx5_glue)[i]); 1785 } 1786 #endif 1787 if (strcmp(mlx5_glue->version, MLX5_GLUE_VERSION)) { 1788 DRV_LOG(ERR, 1789 "rdma-core glue \"%s\" mismatch: \"%s\" is required", 1790 mlx5_glue->version, MLX5_GLUE_VERSION); 1791 return; 1792 } 1793 mlx5_glue->fork_init(); 1794 rte_pci_register(&mlx5_driver); 1795 } 1796 1797 RTE_PMD_EXPORT_NAME(net_mlx5, __COUNTER__); 1798 RTE_PMD_REGISTER_PCI_TABLE(net_mlx5, mlx5_pci_id_map); 1799 RTE_PMD_REGISTER_KMOD_DEP(net_mlx5, "* ib_uverbs & mlx5_core & mlx5_ib"); 1800