1 /* SPDX-License-Identifier: BSD-3-Clause 2 * Copyright 2015 6WIND S.A. 3 * Copyright 2015 Mellanox Technologies, Ltd 4 */ 5 6 #include <stddef.h> 7 #include <unistd.h> 8 #include <string.h> 9 #include <assert.h> 10 #include <dlfcn.h> 11 #include <stdint.h> 12 #include <stdlib.h> 13 #include <errno.h> 14 #include <net/if.h> 15 #include <sys/mman.h> 16 #include <linux/netlink.h> 17 #include <linux/rtnetlink.h> 18 19 /* Verbs header. */ 20 /* ISO C doesn't support unnamed structs/unions, disabling -pedantic. */ 21 #ifdef PEDANTIC 22 #pragma GCC diagnostic ignored "-Wpedantic" 23 #endif 24 #include <infiniband/verbs.h> 25 #ifdef PEDANTIC 26 #pragma GCC diagnostic error "-Wpedantic" 27 #endif 28 29 #include <rte_malloc.h> 30 #include <rte_ethdev_driver.h> 31 #include <rte_ethdev_pci.h> 32 #include <rte_pci.h> 33 #include <rte_bus_pci.h> 34 #include <rte_common.h> 35 #include <rte_config.h> 36 #include <rte_eal_memconfig.h> 37 #include <rte_kvargs.h> 38 #include <rte_rwlock.h> 39 #include <rte_spinlock.h> 40 #include <rte_string_fns.h> 41 42 #include "mlx5.h" 43 #include "mlx5_utils.h" 44 #include "mlx5_rxtx.h" 45 #include "mlx5_autoconf.h" 46 #include "mlx5_defs.h" 47 #include "mlx5_glue.h" 48 #include "mlx5_mr.h" 49 50 /* Device parameter to enable RX completion queue compression. */ 51 #define MLX5_RXQ_CQE_COMP_EN "rxq_cqe_comp_en" 52 53 /* Device parameter to enable Multi-Packet Rx queue. */ 54 #define MLX5_RX_MPRQ_EN "mprq_en" 55 56 /* Device parameter to configure log 2 of the number of strides for MPRQ. */ 57 #define MLX5_RX_MPRQ_LOG_STRIDE_NUM "mprq_log_stride_num" 58 59 /* Device parameter to limit the size of memcpy'd packet for MPRQ. */ 60 #define MLX5_RX_MPRQ_MAX_MEMCPY_LEN "mprq_max_memcpy_len" 61 62 /* Device parameter to set the minimum number of Rx queues to enable MPRQ. */ 63 #define MLX5_RXQS_MIN_MPRQ "rxqs_min_mprq" 64 65 /* Device parameter to configure inline send. */ 66 #define MLX5_TXQ_INLINE "txq_inline" 67 68 /* 69 * Device parameter to configure the number of TX queues threshold for 70 * enabling inline send. 71 */ 72 #define MLX5_TXQS_MIN_INLINE "txqs_min_inline" 73 74 /* Device parameter to enable multi-packet send WQEs. */ 75 #define MLX5_TXQ_MPW_EN "txq_mpw_en" 76 77 /* Device parameter to include 2 dsegs in the title WQEBB. */ 78 #define MLX5_TXQ_MPW_HDR_DSEG_EN "txq_mpw_hdr_dseg_en" 79 80 /* Device parameter to limit the size of inlining packet. */ 81 #define MLX5_TXQ_MAX_INLINE_LEN "txq_max_inline_len" 82 83 /* Device parameter to enable hardware Tx vector. */ 84 #define MLX5_TX_VEC_EN "tx_vec_en" 85 86 /* Device parameter to enable hardware Rx vector. */ 87 #define MLX5_RX_VEC_EN "rx_vec_en" 88 89 /* Allow L3 VXLAN flow creation. */ 90 #define MLX5_L3_VXLAN_EN "l3_vxlan_en" 91 92 /* Activate Netlink support in VF mode. */ 93 #define MLX5_VF_NL_EN "vf_nl_en" 94 95 /* Select port representors to instantiate. */ 96 #define MLX5_REPRESENTOR "representor" 97 98 #ifndef HAVE_IBV_MLX5_MOD_MPW 99 #define MLX5DV_CONTEXT_FLAGS_MPW_ALLOWED (1 << 2) 100 #define MLX5DV_CONTEXT_FLAGS_ENHANCED_MPW (1 << 3) 101 #endif 102 103 #ifndef HAVE_IBV_MLX5_MOD_CQE_128B_COMP 104 #define MLX5DV_CONTEXT_FLAGS_CQE_128B_COMP (1 << 4) 105 #endif 106 107 static const char *MZ_MLX5_PMD_SHARED_DATA = "mlx5_pmd_shared_data"; 108 109 /* Shared memory between primary and secondary processes. */ 110 struct mlx5_shared_data *mlx5_shared_data; 111 112 /* Spinlock for mlx5_shared_data allocation. */ 113 static rte_spinlock_t mlx5_shared_data_lock = RTE_SPINLOCK_INITIALIZER; 114 115 /** Driver-specific log messages type. */ 116 int mlx5_logtype; 117 118 /** 119 * Prepare shared data between primary and secondary process. 120 */ 121 static void 122 mlx5_prepare_shared_data(void) 123 { 124 const struct rte_memzone *mz; 125 126 rte_spinlock_lock(&mlx5_shared_data_lock); 127 if (mlx5_shared_data == NULL) { 128 if (rte_eal_process_type() == RTE_PROC_PRIMARY) { 129 /* Allocate shared memory. */ 130 mz = rte_memzone_reserve(MZ_MLX5_PMD_SHARED_DATA, 131 sizeof(*mlx5_shared_data), 132 SOCKET_ID_ANY, 0); 133 } else { 134 /* Lookup allocated shared memory. */ 135 mz = rte_memzone_lookup(MZ_MLX5_PMD_SHARED_DATA); 136 } 137 if (mz == NULL) 138 rte_panic("Cannot allocate mlx5 shared data\n"); 139 mlx5_shared_data = mz->addr; 140 /* Initialize shared data. */ 141 if (rte_eal_process_type() == RTE_PROC_PRIMARY) { 142 LIST_INIT(&mlx5_shared_data->mem_event_cb_list); 143 rte_rwlock_init(&mlx5_shared_data->mem_event_rwlock); 144 } 145 rte_mem_event_callback_register("MLX5_MEM_EVENT_CB", 146 mlx5_mr_mem_event_cb, NULL); 147 } 148 rte_spinlock_unlock(&mlx5_shared_data_lock); 149 } 150 151 /** 152 * Retrieve integer value from environment variable. 153 * 154 * @param[in] name 155 * Environment variable name. 156 * 157 * @return 158 * Integer value, 0 if the variable is not set. 159 */ 160 int 161 mlx5_getenv_int(const char *name) 162 { 163 const char *val = getenv(name); 164 165 if (val == NULL) 166 return 0; 167 return atoi(val); 168 } 169 170 /** 171 * Verbs callback to allocate a memory. This function should allocate the space 172 * according to the size provided residing inside a huge page. 173 * Please note that all allocation must respect the alignment from libmlx5 174 * (i.e. currently sysconf(_SC_PAGESIZE)). 175 * 176 * @param[in] size 177 * The size in bytes of the memory to allocate. 178 * @param[in] data 179 * A pointer to the callback data. 180 * 181 * @return 182 * Allocated buffer, NULL otherwise and rte_errno is set. 183 */ 184 static void * 185 mlx5_alloc_verbs_buf(size_t size, void *data) 186 { 187 struct priv *priv = data; 188 void *ret; 189 size_t alignment = sysconf(_SC_PAGESIZE); 190 unsigned int socket = SOCKET_ID_ANY; 191 192 if (priv->verbs_alloc_ctx.type == MLX5_VERBS_ALLOC_TYPE_TX_QUEUE) { 193 const struct mlx5_txq_ctrl *ctrl = priv->verbs_alloc_ctx.obj; 194 195 socket = ctrl->socket; 196 } else if (priv->verbs_alloc_ctx.type == 197 MLX5_VERBS_ALLOC_TYPE_RX_QUEUE) { 198 const struct mlx5_rxq_ctrl *ctrl = priv->verbs_alloc_ctx.obj; 199 200 socket = ctrl->socket; 201 } 202 assert(data != NULL); 203 ret = rte_malloc_socket(__func__, size, alignment, socket); 204 if (!ret && size) 205 rte_errno = ENOMEM; 206 return ret; 207 } 208 209 /** 210 * Verbs callback to free a memory. 211 * 212 * @param[in] ptr 213 * A pointer to the memory to free. 214 * @param[in] data 215 * A pointer to the callback data. 216 */ 217 static void 218 mlx5_free_verbs_buf(void *ptr, void *data __rte_unused) 219 { 220 assert(data != NULL); 221 rte_free(ptr); 222 } 223 224 /** 225 * DPDK callback to close the device. 226 * 227 * Destroy all queues and objects, free memory. 228 * 229 * @param dev 230 * Pointer to Ethernet device structure. 231 */ 232 static void 233 mlx5_dev_close(struct rte_eth_dev *dev) 234 { 235 struct priv *priv = dev->data->dev_private; 236 unsigned int i; 237 int ret; 238 239 DRV_LOG(DEBUG, "port %u closing device \"%s\"", 240 dev->data->port_id, 241 ((priv->ctx != NULL) ? priv->ctx->device->name : "")); 242 /* In case mlx5_dev_stop() has not been called. */ 243 mlx5_dev_interrupt_handler_uninstall(dev); 244 mlx5_traffic_disable(dev); 245 mlx5_flow_flush(dev, NULL); 246 /* Prevent crashes when queues are still in use. */ 247 dev->rx_pkt_burst = removed_rx_burst; 248 dev->tx_pkt_burst = removed_tx_burst; 249 if (priv->rxqs != NULL) { 250 /* XXX race condition if mlx5_rx_burst() is still running. */ 251 usleep(1000); 252 for (i = 0; (i != priv->rxqs_n); ++i) 253 mlx5_rxq_release(dev, i); 254 priv->rxqs_n = 0; 255 priv->rxqs = NULL; 256 } 257 if (priv->txqs != NULL) { 258 /* XXX race condition if mlx5_tx_burst() is still running. */ 259 usleep(1000); 260 for (i = 0; (i != priv->txqs_n); ++i) 261 mlx5_txq_release(dev, i); 262 priv->txqs_n = 0; 263 priv->txqs = NULL; 264 } 265 mlx5_mprq_free_mp(dev); 266 mlx5_mr_release(dev); 267 if (priv->pd != NULL) { 268 assert(priv->ctx != NULL); 269 claim_zero(mlx5_glue->dealloc_pd(priv->pd)); 270 claim_zero(mlx5_glue->close_device(priv->ctx)); 271 } else 272 assert(priv->ctx == NULL); 273 if (priv->rss_conf.rss_key != NULL) 274 rte_free(priv->rss_conf.rss_key); 275 if (priv->reta_idx != NULL) 276 rte_free(priv->reta_idx); 277 if (priv->primary_socket) 278 mlx5_socket_uninit(dev); 279 if (priv->config.vf) 280 mlx5_nl_mac_addr_flush(dev); 281 if (priv->nl_socket_route >= 0) 282 close(priv->nl_socket_route); 283 if (priv->nl_socket_rdma >= 0) 284 close(priv->nl_socket_rdma); 285 if (priv->mnl_socket) 286 mlx5_nl_flow_socket_destroy(priv->mnl_socket); 287 ret = mlx5_hrxq_ibv_verify(dev); 288 if (ret) 289 DRV_LOG(WARNING, "port %u some hash Rx queue still remain", 290 dev->data->port_id); 291 ret = mlx5_ind_table_ibv_verify(dev); 292 if (ret) 293 DRV_LOG(WARNING, "port %u some indirection table still remain", 294 dev->data->port_id); 295 ret = mlx5_rxq_ibv_verify(dev); 296 if (ret) 297 DRV_LOG(WARNING, "port %u some Verbs Rx queue still remain", 298 dev->data->port_id); 299 ret = mlx5_rxq_verify(dev); 300 if (ret) 301 DRV_LOG(WARNING, "port %u some Rx queues still remain", 302 dev->data->port_id); 303 ret = mlx5_txq_ibv_verify(dev); 304 if (ret) 305 DRV_LOG(WARNING, "port %u some Verbs Tx queue still remain", 306 dev->data->port_id); 307 ret = mlx5_txq_verify(dev); 308 if (ret) 309 DRV_LOG(WARNING, "port %u some Tx queues still remain", 310 dev->data->port_id); 311 ret = mlx5_flow_verify(dev); 312 if (ret) 313 DRV_LOG(WARNING, "port %u some flows still remain", 314 dev->data->port_id); 315 if (priv->domain_id != RTE_ETH_DEV_SWITCH_DOMAIN_ID_INVALID) { 316 unsigned int c = 0; 317 unsigned int i = mlx5_dev_to_port_id(dev->device, NULL, 0); 318 uint16_t port_id[i]; 319 320 i = RTE_MIN(mlx5_dev_to_port_id(dev->device, port_id, i), i); 321 while (i--) { 322 struct priv *opriv = 323 rte_eth_devices[port_id[i]].data->dev_private; 324 325 if (!opriv || 326 opriv->domain_id != priv->domain_id || 327 &rte_eth_devices[port_id[i]] == dev) 328 continue; 329 ++c; 330 } 331 if (!c) 332 claim_zero(rte_eth_switch_domain_free(priv->domain_id)); 333 } 334 memset(priv, 0, sizeof(*priv)); 335 priv->domain_id = RTE_ETH_DEV_SWITCH_DOMAIN_ID_INVALID; 336 } 337 338 const struct eth_dev_ops mlx5_dev_ops = { 339 .dev_configure = mlx5_dev_configure, 340 .dev_start = mlx5_dev_start, 341 .dev_stop = mlx5_dev_stop, 342 .dev_set_link_down = mlx5_set_link_down, 343 .dev_set_link_up = mlx5_set_link_up, 344 .dev_close = mlx5_dev_close, 345 .promiscuous_enable = mlx5_promiscuous_enable, 346 .promiscuous_disable = mlx5_promiscuous_disable, 347 .allmulticast_enable = mlx5_allmulticast_enable, 348 .allmulticast_disable = mlx5_allmulticast_disable, 349 .link_update = mlx5_link_update, 350 .stats_get = mlx5_stats_get, 351 .stats_reset = mlx5_stats_reset, 352 .xstats_get = mlx5_xstats_get, 353 .xstats_reset = mlx5_xstats_reset, 354 .xstats_get_names = mlx5_xstats_get_names, 355 .dev_infos_get = mlx5_dev_infos_get, 356 .dev_supported_ptypes_get = mlx5_dev_supported_ptypes_get, 357 .vlan_filter_set = mlx5_vlan_filter_set, 358 .rx_queue_setup = mlx5_rx_queue_setup, 359 .tx_queue_setup = mlx5_tx_queue_setup, 360 .rx_queue_release = mlx5_rx_queue_release, 361 .tx_queue_release = mlx5_tx_queue_release, 362 .flow_ctrl_get = mlx5_dev_get_flow_ctrl, 363 .flow_ctrl_set = mlx5_dev_set_flow_ctrl, 364 .mac_addr_remove = mlx5_mac_addr_remove, 365 .mac_addr_add = mlx5_mac_addr_add, 366 .mac_addr_set = mlx5_mac_addr_set, 367 .set_mc_addr_list = mlx5_set_mc_addr_list, 368 .mtu_set = mlx5_dev_set_mtu, 369 .vlan_strip_queue_set = mlx5_vlan_strip_queue_set, 370 .vlan_offload_set = mlx5_vlan_offload_set, 371 .reta_update = mlx5_dev_rss_reta_update, 372 .reta_query = mlx5_dev_rss_reta_query, 373 .rss_hash_update = mlx5_rss_hash_update, 374 .rss_hash_conf_get = mlx5_rss_hash_conf_get, 375 .filter_ctrl = mlx5_dev_filter_ctrl, 376 .rx_descriptor_status = mlx5_rx_descriptor_status, 377 .tx_descriptor_status = mlx5_tx_descriptor_status, 378 .rx_queue_intr_enable = mlx5_rx_intr_enable, 379 .rx_queue_intr_disable = mlx5_rx_intr_disable, 380 .is_removed = mlx5_is_removed, 381 }; 382 383 static const struct eth_dev_ops mlx5_dev_sec_ops = { 384 .stats_get = mlx5_stats_get, 385 .stats_reset = mlx5_stats_reset, 386 .xstats_get = mlx5_xstats_get, 387 .xstats_reset = mlx5_xstats_reset, 388 .xstats_get_names = mlx5_xstats_get_names, 389 .dev_infos_get = mlx5_dev_infos_get, 390 .rx_descriptor_status = mlx5_rx_descriptor_status, 391 .tx_descriptor_status = mlx5_tx_descriptor_status, 392 }; 393 394 /* Available operators in flow isolated mode. */ 395 const struct eth_dev_ops mlx5_dev_ops_isolate = { 396 .dev_configure = mlx5_dev_configure, 397 .dev_start = mlx5_dev_start, 398 .dev_stop = mlx5_dev_stop, 399 .dev_set_link_down = mlx5_set_link_down, 400 .dev_set_link_up = mlx5_set_link_up, 401 .dev_close = mlx5_dev_close, 402 .promiscuous_enable = mlx5_promiscuous_enable, 403 .promiscuous_disable = mlx5_promiscuous_disable, 404 .allmulticast_enable = mlx5_allmulticast_enable, 405 .allmulticast_disable = mlx5_allmulticast_disable, 406 .link_update = mlx5_link_update, 407 .stats_get = mlx5_stats_get, 408 .stats_reset = mlx5_stats_reset, 409 .xstats_get = mlx5_xstats_get, 410 .xstats_reset = mlx5_xstats_reset, 411 .xstats_get_names = mlx5_xstats_get_names, 412 .dev_infos_get = mlx5_dev_infos_get, 413 .dev_supported_ptypes_get = mlx5_dev_supported_ptypes_get, 414 .vlan_filter_set = mlx5_vlan_filter_set, 415 .rx_queue_setup = mlx5_rx_queue_setup, 416 .tx_queue_setup = mlx5_tx_queue_setup, 417 .rx_queue_release = mlx5_rx_queue_release, 418 .tx_queue_release = mlx5_tx_queue_release, 419 .flow_ctrl_get = mlx5_dev_get_flow_ctrl, 420 .flow_ctrl_set = mlx5_dev_set_flow_ctrl, 421 .mac_addr_remove = mlx5_mac_addr_remove, 422 .mac_addr_add = mlx5_mac_addr_add, 423 .mac_addr_set = mlx5_mac_addr_set, 424 .set_mc_addr_list = mlx5_set_mc_addr_list, 425 .mtu_set = mlx5_dev_set_mtu, 426 .vlan_strip_queue_set = mlx5_vlan_strip_queue_set, 427 .vlan_offload_set = mlx5_vlan_offload_set, 428 .filter_ctrl = mlx5_dev_filter_ctrl, 429 .rx_descriptor_status = mlx5_rx_descriptor_status, 430 .tx_descriptor_status = mlx5_tx_descriptor_status, 431 .rx_queue_intr_enable = mlx5_rx_intr_enable, 432 .rx_queue_intr_disable = mlx5_rx_intr_disable, 433 .is_removed = mlx5_is_removed, 434 }; 435 436 /** 437 * Verify and store value for device argument. 438 * 439 * @param[in] key 440 * Key argument to verify. 441 * @param[in] val 442 * Value associated with key. 443 * @param opaque 444 * User data. 445 * 446 * @return 447 * 0 on success, a negative errno value otherwise and rte_errno is set. 448 */ 449 static int 450 mlx5_args_check(const char *key, const char *val, void *opaque) 451 { 452 struct mlx5_dev_config *config = opaque; 453 unsigned long tmp; 454 455 /* No-op, port representors are processed in mlx5_dev_spawn(). */ 456 if (!strcmp(MLX5_REPRESENTOR, key)) 457 return 0; 458 errno = 0; 459 tmp = strtoul(val, NULL, 0); 460 if (errno) { 461 rte_errno = errno; 462 DRV_LOG(WARNING, "%s: \"%s\" is not a valid integer", key, val); 463 return -rte_errno; 464 } 465 if (strcmp(MLX5_RXQ_CQE_COMP_EN, key) == 0) { 466 config->cqe_comp = !!tmp; 467 } else if (strcmp(MLX5_RX_MPRQ_EN, key) == 0) { 468 config->mprq.enabled = !!tmp; 469 } else if (strcmp(MLX5_RX_MPRQ_LOG_STRIDE_NUM, key) == 0) { 470 config->mprq.stride_num_n = tmp; 471 } else if (strcmp(MLX5_RX_MPRQ_MAX_MEMCPY_LEN, key) == 0) { 472 config->mprq.max_memcpy_len = tmp; 473 } else if (strcmp(MLX5_RXQS_MIN_MPRQ, key) == 0) { 474 config->mprq.min_rxqs_num = tmp; 475 } else if (strcmp(MLX5_TXQ_INLINE, key) == 0) { 476 config->txq_inline = tmp; 477 } else if (strcmp(MLX5_TXQS_MIN_INLINE, key) == 0) { 478 config->txqs_inline = tmp; 479 } else if (strcmp(MLX5_TXQ_MPW_EN, key) == 0) { 480 config->mps = !!tmp; 481 } else if (strcmp(MLX5_TXQ_MPW_HDR_DSEG_EN, key) == 0) { 482 config->mpw_hdr_dseg = !!tmp; 483 } else if (strcmp(MLX5_TXQ_MAX_INLINE_LEN, key) == 0) { 484 config->inline_max_packet_sz = tmp; 485 } else if (strcmp(MLX5_TX_VEC_EN, key) == 0) { 486 config->tx_vec_en = !!tmp; 487 } else if (strcmp(MLX5_RX_VEC_EN, key) == 0) { 488 config->rx_vec_en = !!tmp; 489 } else if (strcmp(MLX5_L3_VXLAN_EN, key) == 0) { 490 config->l3_vxlan_en = !!tmp; 491 } else if (strcmp(MLX5_VF_NL_EN, key) == 0) { 492 config->vf_nl_en = !!tmp; 493 } else { 494 DRV_LOG(WARNING, "%s: unknown parameter", key); 495 rte_errno = EINVAL; 496 return -rte_errno; 497 } 498 return 0; 499 } 500 501 /** 502 * Parse device parameters. 503 * 504 * @param config 505 * Pointer to device configuration structure. 506 * @param devargs 507 * Device arguments structure. 508 * 509 * @return 510 * 0 on success, a negative errno value otherwise and rte_errno is set. 511 */ 512 static int 513 mlx5_args(struct mlx5_dev_config *config, struct rte_devargs *devargs) 514 { 515 const char **params = (const char *[]){ 516 MLX5_RXQ_CQE_COMP_EN, 517 MLX5_RX_MPRQ_EN, 518 MLX5_RX_MPRQ_LOG_STRIDE_NUM, 519 MLX5_RX_MPRQ_MAX_MEMCPY_LEN, 520 MLX5_RXQS_MIN_MPRQ, 521 MLX5_TXQ_INLINE, 522 MLX5_TXQS_MIN_INLINE, 523 MLX5_TXQ_MPW_EN, 524 MLX5_TXQ_MPW_HDR_DSEG_EN, 525 MLX5_TXQ_MAX_INLINE_LEN, 526 MLX5_TX_VEC_EN, 527 MLX5_RX_VEC_EN, 528 MLX5_L3_VXLAN_EN, 529 MLX5_VF_NL_EN, 530 MLX5_REPRESENTOR, 531 NULL, 532 }; 533 struct rte_kvargs *kvlist; 534 int ret = 0; 535 int i; 536 537 if (devargs == NULL) 538 return 0; 539 /* Following UGLY cast is done to pass checkpatch. */ 540 kvlist = rte_kvargs_parse(devargs->args, params); 541 if (kvlist == NULL) 542 return 0; 543 /* Process parameters. */ 544 for (i = 0; (params[i] != NULL); ++i) { 545 if (rte_kvargs_count(kvlist, params[i])) { 546 ret = rte_kvargs_process(kvlist, params[i], 547 mlx5_args_check, config); 548 if (ret) { 549 rte_errno = EINVAL; 550 rte_kvargs_free(kvlist); 551 return -rte_errno; 552 } 553 } 554 } 555 rte_kvargs_free(kvlist); 556 return 0; 557 } 558 559 static struct rte_pci_driver mlx5_driver; 560 561 /* 562 * Reserved UAR address space for TXQ UAR(hw doorbell) mapping, process 563 * local resource used by both primary and secondary to avoid duplicate 564 * reservation. 565 * The space has to be available on both primary and secondary process, 566 * TXQ UAR maps to this area using fixed mmap w/o double check. 567 */ 568 static void *uar_base; 569 570 static int 571 find_lower_va_bound(const struct rte_memseg_list *msl __rte_unused, 572 const struct rte_memseg *ms, void *arg) 573 { 574 void **addr = arg; 575 576 if (*addr == NULL) 577 *addr = ms->addr; 578 else 579 *addr = RTE_MIN(*addr, ms->addr); 580 581 return 0; 582 } 583 584 /** 585 * Reserve UAR address space for primary process. 586 * 587 * @param[in] dev 588 * Pointer to Ethernet device. 589 * 590 * @return 591 * 0 on success, a negative errno value otherwise and rte_errno is set. 592 */ 593 static int 594 mlx5_uar_init_primary(struct rte_eth_dev *dev) 595 { 596 struct priv *priv = dev->data->dev_private; 597 void *addr = (void *)0; 598 599 if (uar_base) { /* UAR address space mapped. */ 600 priv->uar_base = uar_base; 601 return 0; 602 } 603 /* find out lower bound of hugepage segments */ 604 rte_memseg_walk(find_lower_va_bound, &addr); 605 606 /* keep distance to hugepages to minimize potential conflicts. */ 607 addr = RTE_PTR_SUB(addr, (uintptr_t)(MLX5_UAR_OFFSET + MLX5_UAR_SIZE)); 608 /* anonymous mmap, no real memory consumption. */ 609 addr = mmap(addr, MLX5_UAR_SIZE, 610 PROT_NONE, MAP_PRIVATE | MAP_ANONYMOUS, -1, 0); 611 if (addr == MAP_FAILED) { 612 DRV_LOG(ERR, 613 "port %u failed to reserve UAR address space, please" 614 " adjust MLX5_UAR_SIZE or try --base-virtaddr", 615 dev->data->port_id); 616 rte_errno = ENOMEM; 617 return -rte_errno; 618 } 619 /* Accept either same addr or a new addr returned from mmap if target 620 * range occupied. 621 */ 622 DRV_LOG(INFO, "port %u reserved UAR address space: %p", 623 dev->data->port_id, addr); 624 priv->uar_base = addr; /* for primary and secondary UAR re-mmap. */ 625 uar_base = addr; /* process local, don't reserve again. */ 626 return 0; 627 } 628 629 /** 630 * Reserve UAR address space for secondary process, align with 631 * primary process. 632 * 633 * @param[in] dev 634 * Pointer to Ethernet device. 635 * 636 * @return 637 * 0 on success, a negative errno value otherwise and rte_errno is set. 638 */ 639 static int 640 mlx5_uar_init_secondary(struct rte_eth_dev *dev) 641 { 642 struct priv *priv = dev->data->dev_private; 643 void *addr; 644 645 assert(priv->uar_base); 646 if (uar_base) { /* already reserved. */ 647 assert(uar_base == priv->uar_base); 648 return 0; 649 } 650 /* anonymous mmap, no real memory consumption. */ 651 addr = mmap(priv->uar_base, MLX5_UAR_SIZE, 652 PROT_NONE, MAP_PRIVATE | MAP_ANONYMOUS, -1, 0); 653 if (addr == MAP_FAILED) { 654 DRV_LOG(ERR, "port %u UAR mmap failed: %p size: %llu", 655 dev->data->port_id, priv->uar_base, MLX5_UAR_SIZE); 656 rte_errno = ENXIO; 657 return -rte_errno; 658 } 659 if (priv->uar_base != addr) { 660 DRV_LOG(ERR, 661 "port %u UAR address %p size %llu occupied, please" 662 " adjust MLX5_UAR_OFFSET or try EAL parameter" 663 " --base-virtaddr", 664 dev->data->port_id, priv->uar_base, MLX5_UAR_SIZE); 665 rte_errno = ENXIO; 666 return -rte_errno; 667 } 668 uar_base = addr; /* process local, don't reserve again */ 669 DRV_LOG(INFO, "port %u reserved UAR address space: %p", 670 dev->data->port_id, addr); 671 return 0; 672 } 673 674 /** 675 * Spawn an Ethernet device from Verbs information. 676 * 677 * @param dpdk_dev 678 * Backing DPDK device. 679 * @param ibv_dev 680 * Verbs device. 681 * @param vf 682 * If nonzero, enable VF-specific features. 683 * @param[in] switch_info 684 * Switch properties of Ethernet device. 685 * 686 * @return 687 * A valid Ethernet device object on success, NULL otherwise and rte_errno 688 * is set. The following error is defined: 689 * 690 * EBUSY: device is not supposed to be spawned. 691 */ 692 static struct rte_eth_dev * 693 mlx5_dev_spawn(struct rte_device *dpdk_dev, 694 struct ibv_device *ibv_dev, 695 int vf, 696 const struct mlx5_switch_info *switch_info) 697 { 698 struct ibv_context *ctx; 699 struct ibv_device_attr_ex attr; 700 struct ibv_port_attr port_attr; 701 struct ibv_pd *pd = NULL; 702 struct mlx5dv_context dv_attr = { .comp_mask = 0 }; 703 struct mlx5_dev_config config = { 704 .vf = !!vf, 705 .mps = MLX5_ARG_UNSET, 706 .tx_vec_en = 1, 707 .rx_vec_en = 1, 708 .mpw_hdr_dseg = 0, 709 .txq_inline = MLX5_ARG_UNSET, 710 .txqs_inline = MLX5_ARG_UNSET, 711 .inline_max_packet_sz = MLX5_ARG_UNSET, 712 .vf_nl_en = 1, 713 .mprq = { 714 .enabled = 0, 715 .stride_num_n = MLX5_MPRQ_STRIDE_NUM_N, 716 .max_memcpy_len = MLX5_MPRQ_MEMCPY_DEFAULT_LEN, 717 .min_rxqs_num = MLX5_MPRQ_MIN_RXQS, 718 }, 719 }; 720 struct rte_eth_dev *eth_dev = NULL; 721 struct priv *priv = NULL; 722 int err = 0; 723 unsigned int mps; 724 unsigned int cqe_comp; 725 unsigned int tunnel_en = 0; 726 unsigned int mpls_en = 0; 727 unsigned int swp = 0; 728 unsigned int mprq = 0; 729 unsigned int mprq_min_stride_size_n = 0; 730 unsigned int mprq_max_stride_size_n = 0; 731 unsigned int mprq_min_stride_num_n = 0; 732 unsigned int mprq_max_stride_num_n = 0; 733 #ifdef HAVE_IBV_DEVICE_COUNTERS_SET_SUPPORT 734 struct ibv_counter_set_description cs_desc = { .counter_type = 0 }; 735 #endif 736 struct ether_addr mac; 737 char name[RTE_ETH_NAME_MAX_LEN]; 738 int own_domain_id = 0; 739 unsigned int i; 740 741 /* Determine if this port representor is supposed to be spawned. */ 742 if (switch_info->representor && dpdk_dev->devargs) { 743 struct rte_eth_devargs eth_da; 744 745 err = rte_eth_devargs_parse(dpdk_dev->devargs->args, ð_da); 746 if (err) { 747 rte_errno = -err; 748 DRV_LOG(ERR, "failed to process device arguments: %s", 749 strerror(rte_errno)); 750 return NULL; 751 } 752 for (i = 0; i < eth_da.nb_representor_ports; ++i) 753 if (eth_da.representor_ports[i] == 754 (uint16_t)switch_info->port_name) 755 break; 756 if (i == eth_da.nb_representor_ports) { 757 rte_errno = EBUSY; 758 return NULL; 759 } 760 } 761 /* Prepare shared data between primary and secondary process. */ 762 mlx5_prepare_shared_data(); 763 errno = 0; 764 ctx = mlx5_glue->open_device(ibv_dev); 765 if (!ctx) { 766 rte_errno = errno ? errno : ENODEV; 767 return NULL; 768 } 769 #ifdef HAVE_IBV_MLX5_MOD_SWP 770 dv_attr.comp_mask |= MLX5DV_CONTEXT_MASK_SWP; 771 #endif 772 /* 773 * Multi-packet send is supported by ConnectX-4 Lx PF as well 774 * as all ConnectX-5 devices. 775 */ 776 #ifdef HAVE_IBV_DEVICE_TUNNEL_SUPPORT 777 dv_attr.comp_mask |= MLX5DV_CONTEXT_MASK_TUNNEL_OFFLOADS; 778 #endif 779 #ifdef HAVE_IBV_DEVICE_STRIDING_RQ_SUPPORT 780 dv_attr.comp_mask |= MLX5DV_CONTEXT_MASK_STRIDING_RQ; 781 #endif 782 mlx5_glue->dv_query_device(ctx, &dv_attr); 783 if (dv_attr.flags & MLX5DV_CONTEXT_FLAGS_MPW_ALLOWED) { 784 if (dv_attr.flags & MLX5DV_CONTEXT_FLAGS_ENHANCED_MPW) { 785 DRV_LOG(DEBUG, "enhanced MPW is supported"); 786 mps = MLX5_MPW_ENHANCED; 787 } else { 788 DRV_LOG(DEBUG, "MPW is supported"); 789 mps = MLX5_MPW; 790 } 791 } else { 792 DRV_LOG(DEBUG, "MPW isn't supported"); 793 mps = MLX5_MPW_DISABLED; 794 } 795 #ifdef HAVE_IBV_MLX5_MOD_SWP 796 if (dv_attr.comp_mask & MLX5DV_CONTEXT_MASK_SWP) 797 swp = dv_attr.sw_parsing_caps.sw_parsing_offloads; 798 DRV_LOG(DEBUG, "SWP support: %u", swp); 799 #endif 800 config.swp = !!swp; 801 #ifdef HAVE_IBV_DEVICE_STRIDING_RQ_SUPPORT 802 if (dv_attr.comp_mask & MLX5DV_CONTEXT_MASK_STRIDING_RQ) { 803 struct mlx5dv_striding_rq_caps mprq_caps = 804 dv_attr.striding_rq_caps; 805 806 DRV_LOG(DEBUG, "\tmin_single_stride_log_num_of_bytes: %d", 807 mprq_caps.min_single_stride_log_num_of_bytes); 808 DRV_LOG(DEBUG, "\tmax_single_stride_log_num_of_bytes: %d", 809 mprq_caps.max_single_stride_log_num_of_bytes); 810 DRV_LOG(DEBUG, "\tmin_single_wqe_log_num_of_strides: %d", 811 mprq_caps.min_single_wqe_log_num_of_strides); 812 DRV_LOG(DEBUG, "\tmax_single_wqe_log_num_of_strides: %d", 813 mprq_caps.max_single_wqe_log_num_of_strides); 814 DRV_LOG(DEBUG, "\tsupported_qpts: %d", 815 mprq_caps.supported_qpts); 816 DRV_LOG(DEBUG, "device supports Multi-Packet RQ"); 817 mprq = 1; 818 mprq_min_stride_size_n = 819 mprq_caps.min_single_stride_log_num_of_bytes; 820 mprq_max_stride_size_n = 821 mprq_caps.max_single_stride_log_num_of_bytes; 822 mprq_min_stride_num_n = 823 mprq_caps.min_single_wqe_log_num_of_strides; 824 mprq_max_stride_num_n = 825 mprq_caps.max_single_wqe_log_num_of_strides; 826 config.mprq.stride_num_n = RTE_MAX(MLX5_MPRQ_STRIDE_NUM_N, 827 mprq_min_stride_num_n); 828 } 829 #endif 830 if (RTE_CACHE_LINE_SIZE == 128 && 831 !(dv_attr.flags & MLX5DV_CONTEXT_FLAGS_CQE_128B_COMP)) 832 cqe_comp = 0; 833 else 834 cqe_comp = 1; 835 config.cqe_comp = cqe_comp; 836 #ifdef HAVE_IBV_DEVICE_TUNNEL_SUPPORT 837 if (dv_attr.comp_mask & MLX5DV_CONTEXT_MASK_TUNNEL_OFFLOADS) { 838 tunnel_en = ((dv_attr.tunnel_offloads_caps & 839 MLX5DV_RAW_PACKET_CAP_TUNNELED_OFFLOAD_VXLAN) && 840 (dv_attr.tunnel_offloads_caps & 841 MLX5DV_RAW_PACKET_CAP_TUNNELED_OFFLOAD_GRE)); 842 } 843 DRV_LOG(DEBUG, "tunnel offloading is %ssupported", 844 tunnel_en ? "" : "not "); 845 #else 846 DRV_LOG(WARNING, 847 "tunnel offloading disabled due to old OFED/rdma-core version"); 848 #endif 849 config.tunnel_en = tunnel_en; 850 #ifdef HAVE_IBV_DEVICE_MPLS_SUPPORT 851 mpls_en = ((dv_attr.tunnel_offloads_caps & 852 MLX5DV_RAW_PACKET_CAP_TUNNELED_OFFLOAD_CW_MPLS_OVER_GRE) && 853 (dv_attr.tunnel_offloads_caps & 854 MLX5DV_RAW_PACKET_CAP_TUNNELED_OFFLOAD_CW_MPLS_OVER_UDP)); 855 DRV_LOG(DEBUG, "MPLS over GRE/UDP tunnel offloading is %ssupported", 856 mpls_en ? "" : "not "); 857 #else 858 DRV_LOG(WARNING, "MPLS over GRE/UDP tunnel offloading disabled due to" 859 " old OFED/rdma-core version or firmware configuration"); 860 #endif 861 config.mpls_en = mpls_en; 862 err = mlx5_glue->query_device_ex(ctx, NULL, &attr); 863 if (err) { 864 DEBUG("ibv_query_device_ex() failed"); 865 goto error; 866 } 867 if (!switch_info->representor) 868 rte_strlcpy(name, dpdk_dev->name, sizeof(name)); 869 else 870 snprintf(name, sizeof(name), "%s_representor_%u", 871 dpdk_dev->name, switch_info->port_name); 872 DRV_LOG(DEBUG, "naming Ethernet device \"%s\"", name); 873 if (rte_eal_process_type() == RTE_PROC_SECONDARY) { 874 eth_dev = rte_eth_dev_attach_secondary(name); 875 if (eth_dev == NULL) { 876 DRV_LOG(ERR, "can not attach rte ethdev"); 877 rte_errno = ENOMEM; 878 err = rte_errno; 879 goto error; 880 } 881 eth_dev->device = dpdk_dev; 882 eth_dev->dev_ops = &mlx5_dev_sec_ops; 883 err = mlx5_uar_init_secondary(eth_dev); 884 if (err) { 885 err = rte_errno; 886 goto error; 887 } 888 /* Receive command fd from primary process */ 889 err = mlx5_socket_connect(eth_dev); 890 if (err < 0) { 891 err = rte_errno; 892 goto error; 893 } 894 /* Remap UAR for Tx queues. */ 895 err = mlx5_tx_uar_remap(eth_dev, err); 896 if (err) { 897 err = rte_errno; 898 goto error; 899 } 900 /* 901 * Ethdev pointer is still required as input since 902 * the primary device is not accessible from the 903 * secondary process. 904 */ 905 eth_dev->rx_pkt_burst = mlx5_select_rx_function(eth_dev); 906 eth_dev->tx_pkt_burst = mlx5_select_tx_function(eth_dev); 907 claim_zero(mlx5_glue->close_device(ctx)); 908 return eth_dev; 909 } 910 /* Check port status. */ 911 err = mlx5_glue->query_port(ctx, 1, &port_attr); 912 if (err) { 913 DRV_LOG(ERR, "port query failed: %s", strerror(err)); 914 goto error; 915 } 916 if (port_attr.link_layer != IBV_LINK_LAYER_ETHERNET) { 917 DRV_LOG(ERR, "port is not configured in Ethernet mode"); 918 err = EINVAL; 919 goto error; 920 } 921 if (port_attr.state != IBV_PORT_ACTIVE) 922 DRV_LOG(DEBUG, "port is not active: \"%s\" (%d)", 923 mlx5_glue->port_state_str(port_attr.state), 924 port_attr.state); 925 /* Allocate protection domain. */ 926 pd = mlx5_glue->alloc_pd(ctx); 927 if (pd == NULL) { 928 DRV_LOG(ERR, "PD allocation failure"); 929 err = ENOMEM; 930 goto error; 931 } 932 priv = rte_zmalloc("ethdev private structure", 933 sizeof(*priv), 934 RTE_CACHE_LINE_SIZE); 935 if (priv == NULL) { 936 DRV_LOG(ERR, "priv allocation failure"); 937 err = ENOMEM; 938 goto error; 939 } 940 priv->ctx = ctx; 941 strncpy(priv->ibdev_name, priv->ctx->device->name, 942 sizeof(priv->ibdev_name)); 943 strncpy(priv->ibdev_path, priv->ctx->device->ibdev_path, 944 sizeof(priv->ibdev_path)); 945 priv->device_attr = attr; 946 priv->pd = pd; 947 priv->mtu = ETHER_MTU; 948 #ifndef RTE_ARCH_64 949 /* Initialize UAR access locks for 32bit implementations. */ 950 rte_spinlock_init(&priv->uar_lock_cq); 951 for (i = 0; i < MLX5_UAR_PAGE_NUM_MAX; i++) 952 rte_spinlock_init(&priv->uar_lock[i]); 953 #endif 954 /* Some internal functions rely on Netlink sockets, open them now. */ 955 priv->nl_socket_rdma = mlx5_nl_init(NETLINK_RDMA); 956 priv->nl_socket_route = mlx5_nl_init(NETLINK_ROUTE); 957 priv->nl_sn = 0; 958 priv->representor = !!switch_info->representor; 959 priv->domain_id = RTE_ETH_DEV_SWITCH_DOMAIN_ID_INVALID; 960 priv->representor_id = 961 switch_info->representor ? switch_info->port_name : -1; 962 /* 963 * Look for sibling devices in order to reuse their switch domain 964 * if any, otherwise allocate one. 965 */ 966 i = mlx5_dev_to_port_id(dpdk_dev, NULL, 0); 967 if (i > 0) { 968 uint16_t port_id[i]; 969 970 i = RTE_MIN(mlx5_dev_to_port_id(dpdk_dev, port_id, i), i); 971 while (i--) { 972 const struct priv *opriv = 973 rte_eth_devices[port_id[i]].data->dev_private; 974 975 if (!opriv || 976 opriv->domain_id == 977 RTE_ETH_DEV_SWITCH_DOMAIN_ID_INVALID) 978 continue; 979 priv->domain_id = opriv->domain_id; 980 break; 981 } 982 } 983 if (priv->domain_id == RTE_ETH_DEV_SWITCH_DOMAIN_ID_INVALID) { 984 err = rte_eth_switch_domain_alloc(&priv->domain_id); 985 if (err) { 986 err = rte_errno; 987 DRV_LOG(ERR, "unable to allocate switch domain: %s", 988 strerror(rte_errno)); 989 goto error; 990 } 991 own_domain_id = 1; 992 } 993 err = mlx5_args(&config, dpdk_dev->devargs); 994 if (err) { 995 err = rte_errno; 996 DRV_LOG(ERR, "failed to process device arguments: %s", 997 strerror(rte_errno)); 998 goto error; 999 } 1000 config.hw_csum = !!(attr.device_cap_flags_ex & IBV_DEVICE_RAW_IP_CSUM); 1001 DRV_LOG(DEBUG, "checksum offloading is %ssupported", 1002 (config.hw_csum ? "" : "not ")); 1003 #ifdef HAVE_IBV_DEVICE_COUNTERS_SET_SUPPORT 1004 config.flow_counter_en = !!attr.max_counter_sets; 1005 mlx5_glue->describe_counter_set(ctx, 0, &cs_desc); 1006 DRV_LOG(DEBUG, "counter type = %d, num of cs = %ld, attributes = %d", 1007 cs_desc.counter_type, cs_desc.num_of_cs, 1008 cs_desc.attributes); 1009 #endif 1010 config.ind_table_max_size = 1011 attr.rss_caps.max_rwq_indirection_table_size; 1012 /* 1013 * Remove this check once DPDK supports larger/variable 1014 * indirection tables. 1015 */ 1016 if (config.ind_table_max_size > (unsigned int)ETH_RSS_RETA_SIZE_512) 1017 config.ind_table_max_size = ETH_RSS_RETA_SIZE_512; 1018 DRV_LOG(DEBUG, "maximum Rx indirection table size is %u", 1019 config.ind_table_max_size); 1020 config.hw_vlan_strip = !!(attr.raw_packet_caps & 1021 IBV_RAW_PACKET_CAP_CVLAN_STRIPPING); 1022 DRV_LOG(DEBUG, "VLAN stripping is %ssupported", 1023 (config.hw_vlan_strip ? "" : "not ")); 1024 config.hw_fcs_strip = !!(attr.raw_packet_caps & 1025 IBV_RAW_PACKET_CAP_SCATTER_FCS); 1026 DRV_LOG(DEBUG, "FCS stripping configuration is %ssupported", 1027 (config.hw_fcs_strip ? "" : "not ")); 1028 #ifdef HAVE_IBV_WQ_FLAG_RX_END_PADDING 1029 config.hw_padding = !!attr.rx_pad_end_addr_align; 1030 #endif 1031 DRV_LOG(DEBUG, "hardware Rx end alignment padding is %ssupported", 1032 (config.hw_padding ? "" : "not ")); 1033 config.tso = (attr.tso_caps.max_tso > 0 && 1034 (attr.tso_caps.supported_qpts & 1035 (1 << IBV_QPT_RAW_PACKET))); 1036 if (config.tso) 1037 config.tso_max_payload_sz = attr.tso_caps.max_tso; 1038 /* 1039 * MPW is disabled by default, while the Enhanced MPW is enabled 1040 * by default. 1041 */ 1042 if (config.mps == MLX5_ARG_UNSET) 1043 config.mps = (mps == MLX5_MPW_ENHANCED) ? MLX5_MPW_ENHANCED : 1044 MLX5_MPW_DISABLED; 1045 else 1046 config.mps = config.mps ? mps : MLX5_MPW_DISABLED; 1047 DRV_LOG(INFO, "%sMPS is %s", 1048 config.mps == MLX5_MPW_ENHANCED ? "enhanced " : "", 1049 config.mps != MLX5_MPW_DISABLED ? "enabled" : "disabled"); 1050 if (config.cqe_comp && !cqe_comp) { 1051 DRV_LOG(WARNING, "Rx CQE compression isn't supported"); 1052 config.cqe_comp = 0; 1053 } 1054 if (config.mprq.enabled && mprq) { 1055 if (config.mprq.stride_num_n > mprq_max_stride_num_n || 1056 config.mprq.stride_num_n < mprq_min_stride_num_n) { 1057 config.mprq.stride_num_n = 1058 RTE_MAX(MLX5_MPRQ_STRIDE_NUM_N, 1059 mprq_min_stride_num_n); 1060 DRV_LOG(WARNING, 1061 "the number of strides" 1062 " for Multi-Packet RQ is out of range," 1063 " setting default value (%u)", 1064 1 << config.mprq.stride_num_n); 1065 } 1066 config.mprq.min_stride_size_n = mprq_min_stride_size_n; 1067 config.mprq.max_stride_size_n = mprq_max_stride_size_n; 1068 } else if (config.mprq.enabled && !mprq) { 1069 DRV_LOG(WARNING, "Multi-Packet RQ isn't supported"); 1070 config.mprq.enabled = 0; 1071 } 1072 eth_dev = rte_eth_dev_allocate(name); 1073 if (eth_dev == NULL) { 1074 DRV_LOG(ERR, "can not allocate rte ethdev"); 1075 err = ENOMEM; 1076 goto error; 1077 } 1078 if (priv->representor) 1079 eth_dev->data->dev_flags |= RTE_ETH_DEV_REPRESENTOR; 1080 eth_dev->data->dev_private = priv; 1081 priv->dev_data = eth_dev->data; 1082 eth_dev->data->mac_addrs = priv->mac; 1083 eth_dev->device = dpdk_dev; 1084 eth_dev->device->driver = &mlx5_driver.driver; 1085 err = mlx5_uar_init_primary(eth_dev); 1086 if (err) { 1087 err = rte_errno; 1088 goto error; 1089 } 1090 /* Configure the first MAC address by default. */ 1091 if (mlx5_get_mac(eth_dev, &mac.addr_bytes)) { 1092 DRV_LOG(ERR, 1093 "port %u cannot get MAC address, is mlx5_en" 1094 " loaded? (errno: %s)", 1095 eth_dev->data->port_id, strerror(rte_errno)); 1096 err = ENODEV; 1097 goto error; 1098 } 1099 DRV_LOG(INFO, 1100 "port %u MAC address is %02x:%02x:%02x:%02x:%02x:%02x", 1101 eth_dev->data->port_id, 1102 mac.addr_bytes[0], mac.addr_bytes[1], 1103 mac.addr_bytes[2], mac.addr_bytes[3], 1104 mac.addr_bytes[4], mac.addr_bytes[5]); 1105 #ifndef NDEBUG 1106 { 1107 char ifname[IF_NAMESIZE]; 1108 1109 if (mlx5_get_ifname(eth_dev, &ifname) == 0) 1110 DRV_LOG(DEBUG, "port %u ifname is \"%s\"", 1111 eth_dev->data->port_id, ifname); 1112 else 1113 DRV_LOG(DEBUG, "port %u ifname is unknown", 1114 eth_dev->data->port_id); 1115 } 1116 #endif 1117 /* Get actual MTU if possible. */ 1118 err = mlx5_get_mtu(eth_dev, &priv->mtu); 1119 if (err) { 1120 err = rte_errno; 1121 goto error; 1122 } 1123 DRV_LOG(DEBUG, "port %u MTU is %u", eth_dev->data->port_id, 1124 priv->mtu); 1125 /* Initialize burst functions to prevent crashes before link-up. */ 1126 eth_dev->rx_pkt_burst = removed_rx_burst; 1127 eth_dev->tx_pkt_burst = removed_tx_burst; 1128 eth_dev->dev_ops = &mlx5_dev_ops; 1129 /* Register MAC address. */ 1130 claim_zero(mlx5_mac_addr_add(eth_dev, &mac, 0, 0)); 1131 if (vf && config.vf_nl_en) 1132 mlx5_nl_mac_addr_sync(eth_dev); 1133 priv->mnl_socket = mlx5_nl_flow_socket_create(); 1134 if (!priv->mnl_socket) { 1135 err = -rte_errno; 1136 DRV_LOG(WARNING, 1137 "flow rules relying on switch offloads will not be" 1138 " supported: cannot open libmnl socket: %s", 1139 strerror(rte_errno)); 1140 } else { 1141 struct rte_flow_error error; 1142 unsigned int ifindex = mlx5_ifindex(eth_dev); 1143 1144 if (!ifindex) { 1145 err = -rte_errno; 1146 error.message = 1147 "cannot retrieve network interface index"; 1148 } else { 1149 err = mlx5_nl_flow_init(priv->mnl_socket, ifindex, 1150 &error); 1151 } 1152 if (err) { 1153 DRV_LOG(WARNING, 1154 "flow rules relying on switch offloads will" 1155 " not be supported: %s: %s", 1156 error.message, strerror(rte_errno)); 1157 mlx5_nl_flow_socket_destroy(priv->mnl_socket); 1158 priv->mnl_socket = NULL; 1159 } 1160 } 1161 TAILQ_INIT(&priv->flows); 1162 TAILQ_INIT(&priv->ctrl_flows); 1163 /* Hint libmlx5 to use PMD allocator for data plane resources */ 1164 struct mlx5dv_ctx_allocators alctr = { 1165 .alloc = &mlx5_alloc_verbs_buf, 1166 .free = &mlx5_free_verbs_buf, 1167 .data = priv, 1168 }; 1169 mlx5_glue->dv_set_context_attr(ctx, MLX5DV_CTX_ATTR_BUF_ALLOCATORS, 1170 (void *)((uintptr_t)&alctr)); 1171 /* Bring Ethernet device up. */ 1172 DRV_LOG(DEBUG, "port %u forcing Ethernet interface up", 1173 eth_dev->data->port_id); 1174 mlx5_set_link_up(eth_dev); 1175 /* 1176 * Even though the interrupt handler is not installed yet, 1177 * interrupts will still trigger on the asyn_fd from 1178 * Verbs context returned by ibv_open_device(). 1179 */ 1180 mlx5_link_update(eth_dev, 0); 1181 /* Store device configuration on private structure. */ 1182 priv->config = config; 1183 /* Supported Verbs flow priority number detection. */ 1184 err = mlx5_flow_discover_priorities(eth_dev); 1185 if (err < 0) 1186 goto error; 1187 priv->config.flow_prio = err; 1188 /* 1189 * Once the device is added to the list of memory event 1190 * callback, its global MR cache table cannot be expanded 1191 * on the fly because of deadlock. If it overflows, lookup 1192 * should be done by searching MR list linearly, which is slow. 1193 */ 1194 err = mlx5_mr_btree_init(&priv->mr.cache, 1195 MLX5_MR_BTREE_CACHE_N * 2, 1196 eth_dev->device->numa_node); 1197 if (err) { 1198 err = rte_errno; 1199 goto error; 1200 } 1201 /* Add device to memory callback list. */ 1202 rte_rwlock_write_lock(&mlx5_shared_data->mem_event_rwlock); 1203 LIST_INSERT_HEAD(&mlx5_shared_data->mem_event_cb_list, 1204 priv, mem_event_cb); 1205 rte_rwlock_write_unlock(&mlx5_shared_data->mem_event_rwlock); 1206 return eth_dev; 1207 error: 1208 if (priv) { 1209 if (priv->nl_socket_route >= 0) 1210 close(priv->nl_socket_route); 1211 if (priv->nl_socket_rdma >= 0) 1212 close(priv->nl_socket_rdma); 1213 if (priv->mnl_socket) 1214 mlx5_nl_flow_socket_destroy(priv->mnl_socket); 1215 if (own_domain_id) 1216 claim_zero(rte_eth_switch_domain_free(priv->domain_id)); 1217 rte_free(priv); 1218 } 1219 if (pd) 1220 claim_zero(mlx5_glue->dealloc_pd(pd)); 1221 if (eth_dev) 1222 rte_eth_dev_release_port(eth_dev); 1223 if (ctx) 1224 claim_zero(mlx5_glue->close_device(ctx)); 1225 assert(err > 0); 1226 rte_errno = err; 1227 return NULL; 1228 } 1229 1230 /** Data associated with devices to spawn. */ 1231 struct mlx5_dev_spawn_data { 1232 unsigned int ifindex; /**< Network interface index. */ 1233 struct mlx5_switch_info info; /**< Switch information. */ 1234 struct ibv_device *ibv_dev; /**< Associated IB device. */ 1235 struct rte_eth_dev *eth_dev; /**< Associated Ethernet device. */ 1236 }; 1237 1238 /** 1239 * Comparison callback to sort device data. 1240 * 1241 * This is meant to be used with qsort(). 1242 * 1243 * @param a[in] 1244 * Pointer to pointer to first data object. 1245 * @param b[in] 1246 * Pointer to pointer to second data object. 1247 * 1248 * @return 1249 * 0 if both objects are equal, less than 0 if the first argument is less 1250 * than the second, greater than 0 otherwise. 1251 */ 1252 static int 1253 mlx5_dev_spawn_data_cmp(const void *a, const void *b) 1254 { 1255 const struct mlx5_switch_info *si_a = 1256 &((const struct mlx5_dev_spawn_data *)a)->info; 1257 const struct mlx5_switch_info *si_b = 1258 &((const struct mlx5_dev_spawn_data *)b)->info; 1259 int ret; 1260 1261 /* Master device first. */ 1262 ret = si_b->master - si_a->master; 1263 if (ret) 1264 return ret; 1265 /* Then representor devices. */ 1266 ret = si_b->representor - si_a->representor; 1267 if (ret) 1268 return ret; 1269 /* Unidentified devices come last in no specific order. */ 1270 if (!si_a->representor) 1271 return 0; 1272 /* Order representors by name. */ 1273 return si_a->port_name - si_b->port_name; 1274 } 1275 1276 /** 1277 * DPDK callback to register a PCI device. 1278 * 1279 * This function spawns Ethernet devices out of a given PCI device. 1280 * 1281 * @param[in] pci_drv 1282 * PCI driver structure (mlx5_driver). 1283 * @param[in] pci_dev 1284 * PCI device information. 1285 * 1286 * @return 1287 * 0 on success, a negative errno value otherwise and rte_errno is set. 1288 */ 1289 static int 1290 mlx5_pci_probe(struct rte_pci_driver *pci_drv __rte_unused, 1291 struct rte_pci_device *pci_dev) 1292 { 1293 struct ibv_device **ibv_list; 1294 unsigned int n = 0; 1295 int vf; 1296 int ret; 1297 1298 assert(pci_drv == &mlx5_driver); 1299 errno = 0; 1300 ibv_list = mlx5_glue->get_device_list(&ret); 1301 if (!ibv_list) { 1302 rte_errno = errno ? errno : ENOSYS; 1303 DRV_LOG(ERR, "cannot list devices, is ib_uverbs loaded?"); 1304 return -rte_errno; 1305 } 1306 1307 struct ibv_device *ibv_match[ret + 1]; 1308 1309 while (ret-- > 0) { 1310 struct rte_pci_addr pci_addr; 1311 1312 DRV_LOG(DEBUG, "checking device \"%s\"", ibv_list[ret]->name); 1313 if (mlx5_ibv_device_to_pci_addr(ibv_list[ret], &pci_addr)) 1314 continue; 1315 if (pci_dev->addr.domain != pci_addr.domain || 1316 pci_dev->addr.bus != pci_addr.bus || 1317 pci_dev->addr.devid != pci_addr.devid || 1318 pci_dev->addr.function != pci_addr.function) 1319 continue; 1320 DRV_LOG(INFO, "PCI information matches for device \"%s\"", 1321 ibv_list[ret]->name); 1322 ibv_match[n++] = ibv_list[ret]; 1323 } 1324 ibv_match[n] = NULL; 1325 1326 struct mlx5_dev_spawn_data list[n]; 1327 int nl_route = n ? mlx5_nl_init(NETLINK_ROUTE) : -1; 1328 int nl_rdma = n ? mlx5_nl_init(NETLINK_RDMA) : -1; 1329 unsigned int i; 1330 unsigned int u; 1331 1332 /* 1333 * The existence of several matching entries (n > 1) means port 1334 * representors have been instantiated. No existing Verbs call nor 1335 * /sys entries can tell them apart, this can only be done through 1336 * Netlink calls assuming kernel drivers are recent enough to 1337 * support them. 1338 * 1339 * In the event of identification failure through Netlink, try again 1340 * through sysfs, then either: 1341 * 1342 * 1. No device matches (n == 0), complain and bail out. 1343 * 2. A single IB device matches (n == 1) and is not a representor, 1344 * assume no switch support. 1345 * 3. Otherwise no safe assumptions can be made; complain louder and 1346 * bail out. 1347 */ 1348 for (i = 0; i != n; ++i) { 1349 list[i].ibv_dev = ibv_match[i]; 1350 list[i].eth_dev = NULL; 1351 if (nl_rdma < 0) 1352 list[i].ifindex = 0; 1353 else 1354 list[i].ifindex = mlx5_nl_ifindex 1355 (nl_rdma, list[i].ibv_dev->name); 1356 if (nl_route < 0 || 1357 !list[i].ifindex || 1358 mlx5_nl_switch_info(nl_route, list[i].ifindex, 1359 &list[i].info) || 1360 ((!list[i].info.representor && !list[i].info.master) && 1361 mlx5_sysfs_switch_info(list[i].ifindex, &list[i].info))) { 1362 list[i].ifindex = 0; 1363 memset(&list[i].info, 0, sizeof(list[i].info)); 1364 continue; 1365 } 1366 } 1367 if (nl_rdma >= 0) 1368 close(nl_rdma); 1369 if (nl_route >= 0) 1370 close(nl_route); 1371 /* Count unidentified devices. */ 1372 for (u = 0, i = 0; i != n; ++i) 1373 if (!list[i].info.master && !list[i].info.representor) 1374 ++u; 1375 if (u) { 1376 if (n == 1 && u == 1) { 1377 /* Case #2. */ 1378 DRV_LOG(INFO, "no switch support detected"); 1379 } else { 1380 /* Case #3. */ 1381 DRV_LOG(ERR, 1382 "unable to tell which of the matching devices" 1383 " is the master (lack of kernel support?)"); 1384 n = 0; 1385 } 1386 } 1387 /* 1388 * Sort list to probe devices in natural order for users convenience 1389 * (i.e. master first, then representors from lowest to highest ID). 1390 */ 1391 if (n) 1392 qsort(list, n, sizeof(*list), mlx5_dev_spawn_data_cmp); 1393 switch (pci_dev->id.device_id) { 1394 case PCI_DEVICE_ID_MELLANOX_CONNECTX4VF: 1395 case PCI_DEVICE_ID_MELLANOX_CONNECTX4LXVF: 1396 case PCI_DEVICE_ID_MELLANOX_CONNECTX5VF: 1397 case PCI_DEVICE_ID_MELLANOX_CONNECTX5EXVF: 1398 vf = 1; 1399 break; 1400 default: 1401 vf = 0; 1402 } 1403 for (i = 0; i != n; ++i) { 1404 uint32_t restore; 1405 1406 list[i].eth_dev = mlx5_dev_spawn 1407 (&pci_dev->device, list[i].ibv_dev, vf, &list[i].info); 1408 if (!list[i].eth_dev) { 1409 if (rte_errno != EBUSY) 1410 break; 1411 /* Device is disabled, ignore it. */ 1412 continue; 1413 } 1414 restore = list[i].eth_dev->data->dev_flags; 1415 rte_eth_copy_pci_info(list[i].eth_dev, pci_dev); 1416 /* Restore non-PCI flags cleared by the above call. */ 1417 list[i].eth_dev->data->dev_flags |= restore; 1418 rte_eth_dev_probing_finish(list[i].eth_dev); 1419 } 1420 mlx5_glue->free_device_list(ibv_list); 1421 if (!n) { 1422 DRV_LOG(WARNING, 1423 "no Verbs device matches PCI device " PCI_PRI_FMT "," 1424 " are kernel drivers loaded?", 1425 pci_dev->addr.domain, pci_dev->addr.bus, 1426 pci_dev->addr.devid, pci_dev->addr.function); 1427 rte_errno = ENOENT; 1428 ret = -rte_errno; 1429 } else if (i != n) { 1430 DRV_LOG(ERR, 1431 "probe of PCI device " PCI_PRI_FMT " aborted after" 1432 " encountering an error: %s", 1433 pci_dev->addr.domain, pci_dev->addr.bus, 1434 pci_dev->addr.devid, pci_dev->addr.function, 1435 strerror(rte_errno)); 1436 ret = -rte_errno; 1437 /* Roll back. */ 1438 while (i--) { 1439 if (!list[i].eth_dev) 1440 continue; 1441 mlx5_dev_close(list[i].eth_dev); 1442 if (rte_eal_process_type() == RTE_PROC_PRIMARY) 1443 rte_free(list[i].eth_dev->data->dev_private); 1444 claim_zero(rte_eth_dev_release_port(list[i].eth_dev)); 1445 } 1446 /* Restore original error. */ 1447 rte_errno = -ret; 1448 } else { 1449 ret = 0; 1450 } 1451 return ret; 1452 } 1453 1454 static const struct rte_pci_id mlx5_pci_id_map[] = { 1455 { 1456 RTE_PCI_DEVICE(PCI_VENDOR_ID_MELLANOX, 1457 PCI_DEVICE_ID_MELLANOX_CONNECTX4) 1458 }, 1459 { 1460 RTE_PCI_DEVICE(PCI_VENDOR_ID_MELLANOX, 1461 PCI_DEVICE_ID_MELLANOX_CONNECTX4VF) 1462 }, 1463 { 1464 RTE_PCI_DEVICE(PCI_VENDOR_ID_MELLANOX, 1465 PCI_DEVICE_ID_MELLANOX_CONNECTX4LX) 1466 }, 1467 { 1468 RTE_PCI_DEVICE(PCI_VENDOR_ID_MELLANOX, 1469 PCI_DEVICE_ID_MELLANOX_CONNECTX4LXVF) 1470 }, 1471 { 1472 RTE_PCI_DEVICE(PCI_VENDOR_ID_MELLANOX, 1473 PCI_DEVICE_ID_MELLANOX_CONNECTX5) 1474 }, 1475 { 1476 RTE_PCI_DEVICE(PCI_VENDOR_ID_MELLANOX, 1477 PCI_DEVICE_ID_MELLANOX_CONNECTX5VF) 1478 }, 1479 { 1480 RTE_PCI_DEVICE(PCI_VENDOR_ID_MELLANOX, 1481 PCI_DEVICE_ID_MELLANOX_CONNECTX5EX) 1482 }, 1483 { 1484 RTE_PCI_DEVICE(PCI_VENDOR_ID_MELLANOX, 1485 PCI_DEVICE_ID_MELLANOX_CONNECTX5EXVF) 1486 }, 1487 { 1488 RTE_PCI_DEVICE(PCI_VENDOR_ID_MELLANOX, 1489 PCI_DEVICE_ID_MELLANOX_CONNECTX5BF) 1490 }, 1491 { 1492 .vendor_id = 0 1493 } 1494 }; 1495 1496 static struct rte_pci_driver mlx5_driver = { 1497 .driver = { 1498 .name = MLX5_DRIVER_NAME 1499 }, 1500 .id_table = mlx5_pci_id_map, 1501 .probe = mlx5_pci_probe, 1502 .drv_flags = RTE_PCI_DRV_INTR_LSC | RTE_PCI_DRV_INTR_RMV, 1503 }; 1504 1505 #ifdef RTE_LIBRTE_MLX5_DLOPEN_DEPS 1506 1507 /** 1508 * Suffix RTE_EAL_PMD_PATH with "-glue". 1509 * 1510 * This function performs a sanity check on RTE_EAL_PMD_PATH before 1511 * suffixing its last component. 1512 * 1513 * @param buf[out] 1514 * Output buffer, should be large enough otherwise NULL is returned. 1515 * @param size 1516 * Size of @p out. 1517 * 1518 * @return 1519 * Pointer to @p buf or @p NULL in case suffix cannot be appended. 1520 */ 1521 static char * 1522 mlx5_glue_path(char *buf, size_t size) 1523 { 1524 static const char *const bad[] = { "/", ".", "..", NULL }; 1525 const char *path = RTE_EAL_PMD_PATH; 1526 size_t len = strlen(path); 1527 size_t off; 1528 int i; 1529 1530 while (len && path[len - 1] == '/') 1531 --len; 1532 for (off = len; off && path[off - 1] != '/'; --off) 1533 ; 1534 for (i = 0; bad[i]; ++i) 1535 if (!strncmp(path + off, bad[i], (int)(len - off))) 1536 goto error; 1537 i = snprintf(buf, size, "%.*s-glue", (int)len, path); 1538 if (i == -1 || (size_t)i >= size) 1539 goto error; 1540 return buf; 1541 error: 1542 DRV_LOG(ERR, 1543 "unable to append \"-glue\" to last component of" 1544 " RTE_EAL_PMD_PATH (\"" RTE_EAL_PMD_PATH "\")," 1545 " please re-configure DPDK"); 1546 return NULL; 1547 } 1548 1549 /** 1550 * Initialization routine for run-time dependency on rdma-core. 1551 */ 1552 static int 1553 mlx5_glue_init(void) 1554 { 1555 char glue_path[sizeof(RTE_EAL_PMD_PATH) - 1 + sizeof("-glue")]; 1556 const char *path[] = { 1557 /* 1558 * A basic security check is necessary before trusting 1559 * MLX5_GLUE_PATH, which may override RTE_EAL_PMD_PATH. 1560 */ 1561 (geteuid() == getuid() && getegid() == getgid() ? 1562 getenv("MLX5_GLUE_PATH") : NULL), 1563 /* 1564 * When RTE_EAL_PMD_PATH is set, use its glue-suffixed 1565 * variant, otherwise let dlopen() look up libraries on its 1566 * own. 1567 */ 1568 (*RTE_EAL_PMD_PATH ? 1569 mlx5_glue_path(glue_path, sizeof(glue_path)) : ""), 1570 }; 1571 unsigned int i = 0; 1572 void *handle = NULL; 1573 void **sym; 1574 const char *dlmsg; 1575 1576 while (!handle && i != RTE_DIM(path)) { 1577 const char *end; 1578 size_t len; 1579 int ret; 1580 1581 if (!path[i]) { 1582 ++i; 1583 continue; 1584 } 1585 end = strpbrk(path[i], ":;"); 1586 if (!end) 1587 end = path[i] + strlen(path[i]); 1588 len = end - path[i]; 1589 ret = 0; 1590 do { 1591 char name[ret + 1]; 1592 1593 ret = snprintf(name, sizeof(name), "%.*s%s" MLX5_GLUE, 1594 (int)len, path[i], 1595 (!len || *(end - 1) == '/') ? "" : "/"); 1596 if (ret == -1) 1597 break; 1598 if (sizeof(name) != (size_t)ret + 1) 1599 continue; 1600 DRV_LOG(DEBUG, "looking for rdma-core glue as \"%s\"", 1601 name); 1602 handle = dlopen(name, RTLD_LAZY); 1603 break; 1604 } while (1); 1605 path[i] = end + 1; 1606 if (!*end) 1607 ++i; 1608 } 1609 if (!handle) { 1610 rte_errno = EINVAL; 1611 dlmsg = dlerror(); 1612 if (dlmsg) 1613 DRV_LOG(WARNING, "cannot load glue library: %s", dlmsg); 1614 goto glue_error; 1615 } 1616 sym = dlsym(handle, "mlx5_glue"); 1617 if (!sym || !*sym) { 1618 rte_errno = EINVAL; 1619 dlmsg = dlerror(); 1620 if (dlmsg) 1621 DRV_LOG(ERR, "cannot resolve glue symbol: %s", dlmsg); 1622 goto glue_error; 1623 } 1624 mlx5_glue = *sym; 1625 return 0; 1626 glue_error: 1627 if (handle) 1628 dlclose(handle); 1629 DRV_LOG(WARNING, 1630 "cannot initialize PMD due to missing run-time dependency on" 1631 " rdma-core libraries (libibverbs, libmlx5)"); 1632 return -rte_errno; 1633 } 1634 1635 #endif 1636 1637 /** 1638 * Driver initialization routine. 1639 */ 1640 RTE_INIT(rte_mlx5_pmd_init) 1641 { 1642 /* Initialize driver log type. */ 1643 mlx5_logtype = rte_log_register("pmd.net.mlx5"); 1644 if (mlx5_logtype >= 0) 1645 rte_log_set_level(mlx5_logtype, RTE_LOG_NOTICE); 1646 1647 /* Build the static tables for Verbs conversion. */ 1648 mlx5_set_ptype_table(); 1649 mlx5_set_cksum_table(); 1650 mlx5_set_swp_types_table(); 1651 /* 1652 * RDMAV_HUGEPAGES_SAFE tells ibv_fork_init() we intend to use 1653 * huge pages. Calling ibv_fork_init() during init allows 1654 * applications to use fork() safely for purposes other than 1655 * using this PMD, which is not supported in forked processes. 1656 */ 1657 setenv("RDMAV_HUGEPAGES_SAFE", "1", 1); 1658 /* Match the size of Rx completion entry to the size of a cacheline. */ 1659 if (RTE_CACHE_LINE_SIZE == 128) 1660 setenv("MLX5_CQE_SIZE", "128", 0); 1661 /* 1662 * MLX5_DEVICE_FATAL_CLEANUP tells ibv_destroy functions to 1663 * cleanup all the Verbs resources even when the device was removed. 1664 */ 1665 setenv("MLX5_DEVICE_FATAL_CLEANUP", "1", 1); 1666 #ifdef RTE_LIBRTE_MLX5_DLOPEN_DEPS 1667 if (mlx5_glue_init()) 1668 return; 1669 assert(mlx5_glue); 1670 #endif 1671 #ifndef NDEBUG 1672 /* Glue structure must not contain any NULL pointers. */ 1673 { 1674 unsigned int i; 1675 1676 for (i = 0; i != sizeof(*mlx5_glue) / sizeof(void *); ++i) 1677 assert(((const void *const *)mlx5_glue)[i]); 1678 } 1679 #endif 1680 if (strcmp(mlx5_glue->version, MLX5_GLUE_VERSION)) { 1681 DRV_LOG(ERR, 1682 "rdma-core glue \"%s\" mismatch: \"%s\" is required", 1683 mlx5_glue->version, MLX5_GLUE_VERSION); 1684 return; 1685 } 1686 mlx5_glue->fork_init(); 1687 rte_pci_register(&mlx5_driver); 1688 } 1689 1690 RTE_PMD_EXPORT_NAME(net_mlx5, __COUNTER__); 1691 RTE_PMD_REGISTER_PCI_TABLE(net_mlx5, mlx5_pci_id_map); 1692 RTE_PMD_REGISTER_KMOD_DEP(net_mlx5, "* ib_uverbs & mlx5_core & mlx5_ib"); 1693