1 /*- 2 * BSD LICENSE 3 * 4 * Copyright 2015 6WIND S.A. 5 * Copyright 2015 Mellanox. 6 * 7 * Redistribution and use in source and binary forms, with or without 8 * modification, are permitted provided that the following conditions 9 * are met: 10 * 11 * * Redistributions of source code must retain the above copyright 12 * notice, this list of conditions and the following disclaimer. 13 * * Redistributions in binary form must reproduce the above copyright 14 * notice, this list of conditions and the following disclaimer in 15 * the documentation and/or other materials provided with the 16 * distribution. 17 * * Neither the name of 6WIND S.A. nor the names of its 18 * contributors may be used to endorse or promote products derived 19 * from this software without specific prior written permission. 20 * 21 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 22 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 23 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 24 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 25 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 26 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 27 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 28 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 29 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 30 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 31 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 32 */ 33 34 #include <stddef.h> 35 #include <unistd.h> 36 #include <string.h> 37 #include <assert.h> 38 #include <stdint.h> 39 #include <stdlib.h> 40 #include <errno.h> 41 #include <net/if.h> 42 43 /* Verbs header. */ 44 /* ISO C doesn't support unnamed structs/unions, disabling -pedantic. */ 45 #ifdef PEDANTIC 46 #pragma GCC diagnostic ignored "-Wpedantic" 47 #endif 48 #include <infiniband/verbs.h> 49 #ifdef PEDANTIC 50 #pragma GCC diagnostic error "-Wpedantic" 51 #endif 52 53 #include <rte_malloc.h> 54 #include <rte_ethdev.h> 55 #include <rte_ethdev_pci.h> 56 #include <rte_pci.h> 57 #include <rte_common.h> 58 #include <rte_kvargs.h> 59 60 #include "mlx5.h" 61 #include "mlx5_utils.h" 62 #include "mlx5_rxtx.h" 63 #include "mlx5_autoconf.h" 64 #include "mlx5_defs.h" 65 66 /* Device parameter to enable RX completion queue compression. */ 67 #define MLX5_RXQ_CQE_COMP_EN "rxq_cqe_comp_en" 68 69 /* Device parameter to configure inline send. */ 70 #define MLX5_TXQ_INLINE "txq_inline" 71 72 /* 73 * Device parameter to configure the number of TX queues threshold for 74 * enabling inline send. 75 */ 76 #define MLX5_TXQS_MIN_INLINE "txqs_min_inline" 77 78 /* Device parameter to enable multi-packet send WQEs. */ 79 #define MLX5_TXQ_MPW_EN "txq_mpw_en" 80 81 /* Device parameter to include 2 dsegs in the title WQEBB. */ 82 #define MLX5_TXQ_MPW_HDR_DSEG_EN "txq_mpw_hdr_dseg_en" 83 84 /* Device parameter to limit the size of inlining packet. */ 85 #define MLX5_TXQ_MAX_INLINE_LEN "txq_max_inline_len" 86 87 /* Device parameter to enable hardware TSO offload. */ 88 #define MLX5_TSO "tso" 89 90 /* Device parameter to enable hardware Tx vector. */ 91 #define MLX5_TX_VEC_EN "tx_vec_en" 92 93 /* Device parameter to enable hardware Rx vector. */ 94 #define MLX5_RX_VEC_EN "rx_vec_en" 95 96 /* Default PMD specific parameter value. */ 97 #define MLX5_ARG_UNSET (-1) 98 99 #ifndef HAVE_IBV_MLX5_MOD_MPW 100 #define MLX5DV_CONTEXT_FLAGS_MPW_ALLOWED (1 << 2) 101 #define MLX5DV_CONTEXT_FLAGS_ENHANCED_MPW (1 << 3) 102 #endif 103 104 #ifndef HAVE_IBV_MLX5_MOD_CQE_128B_COMP 105 #define MLX5DV_CONTEXT_FLAGS_CQE_128B_COMP (1 << 4) 106 #endif 107 108 struct mlx5_args { 109 int cqe_comp; 110 int txq_inline; 111 int txqs_inline; 112 int mps; 113 int mpw_hdr_dseg; 114 int inline_max_packet_sz; 115 int tso; 116 int tx_vec_en; 117 int rx_vec_en; 118 }; 119 /** 120 * Retrieve integer value from environment variable. 121 * 122 * @param[in] name 123 * Environment variable name. 124 * 125 * @return 126 * Integer value, 0 if the variable is not set. 127 */ 128 int 129 mlx5_getenv_int(const char *name) 130 { 131 const char *val = getenv(name); 132 133 if (val == NULL) 134 return 0; 135 return atoi(val); 136 } 137 138 /** 139 * Verbs callback to allocate a memory. This function should allocate the space 140 * according to the size provided residing inside a huge page. 141 * Please note that all allocation must respect the alignment from libmlx5 142 * (i.e. currently sysconf(_SC_PAGESIZE)). 143 * 144 * @param[in] size 145 * The size in bytes of the memory to allocate. 146 * @param[in] data 147 * A pointer to the callback data. 148 * 149 * @return 150 * a pointer to the allocate space. 151 */ 152 static void * 153 mlx5_alloc_verbs_buf(size_t size, void *data) 154 { 155 struct priv *priv = data; 156 void *ret; 157 size_t alignment = sysconf(_SC_PAGESIZE); 158 159 assert(data != NULL); 160 assert(!mlx5_is_secondary()); 161 ret = rte_malloc_socket(__func__, size, alignment, 162 priv->dev->device->numa_node); 163 DEBUG("Extern alloc size: %lu, align: %lu: %p", size, alignment, ret); 164 return ret; 165 } 166 167 /** 168 * Verbs callback to free a memory. 169 * 170 * @param[in] ptr 171 * A pointer to the memory to free. 172 * @param[in] data 173 * A pointer to the callback data. 174 */ 175 static void 176 mlx5_free_verbs_buf(void *ptr, void *data __rte_unused) 177 { 178 assert(data != NULL); 179 assert(!mlx5_is_secondary()); 180 DEBUG("Extern free request: %p", ptr); 181 rte_free(ptr); 182 } 183 184 /** 185 * DPDK callback to close the device. 186 * 187 * Destroy all queues and objects, free memory. 188 * 189 * @param dev 190 * Pointer to Ethernet device structure. 191 */ 192 static void 193 mlx5_dev_close(struct rte_eth_dev *dev) 194 { 195 struct priv *priv = mlx5_get_priv(dev); 196 unsigned int i; 197 int ret; 198 199 priv_lock(priv); 200 DEBUG("%p: closing device \"%s\"", 201 (void *)dev, 202 ((priv->ctx != NULL) ? priv->ctx->device->name : "")); 203 /* In case mlx5_dev_stop() has not been called. */ 204 priv_dev_interrupt_handler_uninstall(priv, dev); 205 priv_dev_traffic_disable(priv, dev); 206 /* Prevent crashes when queues are still in use. */ 207 dev->rx_pkt_burst = removed_rx_burst; 208 dev->tx_pkt_burst = removed_tx_burst; 209 if (priv->rxqs != NULL) { 210 /* XXX race condition if mlx5_rx_burst() is still running. */ 211 usleep(1000); 212 for (i = 0; (i != priv->rxqs_n); ++i) 213 mlx5_priv_rxq_release(priv, i); 214 priv->rxqs_n = 0; 215 priv->rxqs = NULL; 216 } 217 if (priv->txqs != NULL) { 218 /* XXX race condition if mlx5_tx_burst() is still running. */ 219 usleep(1000); 220 for (i = 0; (i != priv->txqs_n); ++i) 221 mlx5_priv_txq_release(priv, i); 222 priv->txqs_n = 0; 223 priv->txqs = NULL; 224 } 225 if (priv->pd != NULL) { 226 assert(priv->ctx != NULL); 227 claim_zero(ibv_dealloc_pd(priv->pd)); 228 claim_zero(ibv_close_device(priv->ctx)); 229 } else 230 assert(priv->ctx == NULL); 231 if (priv->rss_conf.rss_key != NULL) 232 rte_free(priv->rss_conf.rss_key); 233 if (priv->reta_idx != NULL) 234 rte_free(priv->reta_idx); 235 priv_socket_uninit(priv); 236 ret = mlx5_priv_hrxq_ibv_verify(priv); 237 if (ret) 238 WARN("%p: some Hash Rx queue still remain", (void *)priv); 239 ret = mlx5_priv_ind_table_ibv_verify(priv); 240 if (ret) 241 WARN("%p: some Indirection table still remain", (void *)priv); 242 ret = mlx5_priv_rxq_ibv_verify(priv); 243 if (ret) 244 WARN("%p: some Verbs Rx queue still remain", (void *)priv); 245 ret = mlx5_priv_rxq_verify(priv); 246 if (ret) 247 WARN("%p: some Rx Queues still remain", (void *)priv); 248 ret = mlx5_priv_txq_ibv_verify(priv); 249 if (ret) 250 WARN("%p: some Verbs Tx queue still remain", (void *)priv); 251 ret = mlx5_priv_txq_verify(priv); 252 if (ret) 253 WARN("%p: some Tx Queues still remain", (void *)priv); 254 ret = priv_flow_verify(priv); 255 if (ret) 256 WARN("%p: some flows still remain", (void *)priv); 257 ret = priv_mr_verify(priv); 258 if (ret) 259 WARN("%p: some Memory Region still remain", (void *)priv); 260 priv_unlock(priv); 261 memset(priv, 0, sizeof(*priv)); 262 } 263 264 const struct eth_dev_ops mlx5_dev_ops = { 265 .dev_configure = mlx5_dev_configure, 266 .dev_start = mlx5_dev_start, 267 .dev_stop = mlx5_dev_stop, 268 .dev_set_link_down = mlx5_set_link_down, 269 .dev_set_link_up = mlx5_set_link_up, 270 .dev_close = mlx5_dev_close, 271 .promiscuous_enable = mlx5_promiscuous_enable, 272 .promiscuous_disable = mlx5_promiscuous_disable, 273 .allmulticast_enable = mlx5_allmulticast_enable, 274 .allmulticast_disable = mlx5_allmulticast_disable, 275 .link_update = mlx5_link_update, 276 .stats_get = mlx5_stats_get, 277 .stats_reset = mlx5_stats_reset, 278 .xstats_get = mlx5_xstats_get, 279 .xstats_reset = mlx5_xstats_reset, 280 .xstats_get_names = mlx5_xstats_get_names, 281 .dev_infos_get = mlx5_dev_infos_get, 282 .dev_supported_ptypes_get = mlx5_dev_supported_ptypes_get, 283 .vlan_filter_set = mlx5_vlan_filter_set, 284 .rx_queue_setup = mlx5_rx_queue_setup, 285 .tx_queue_setup = mlx5_tx_queue_setup, 286 .rx_queue_release = mlx5_rx_queue_release, 287 .tx_queue_release = mlx5_tx_queue_release, 288 .flow_ctrl_get = mlx5_dev_get_flow_ctrl, 289 .flow_ctrl_set = mlx5_dev_set_flow_ctrl, 290 .mac_addr_remove = mlx5_mac_addr_remove, 291 .mac_addr_add = mlx5_mac_addr_add, 292 .mac_addr_set = mlx5_mac_addr_set, 293 .mtu_set = mlx5_dev_set_mtu, 294 .vlan_strip_queue_set = mlx5_vlan_strip_queue_set, 295 .vlan_offload_set = mlx5_vlan_offload_set, 296 .reta_update = mlx5_dev_rss_reta_update, 297 .reta_query = mlx5_dev_rss_reta_query, 298 .rss_hash_update = mlx5_rss_hash_update, 299 .rss_hash_conf_get = mlx5_rss_hash_conf_get, 300 .filter_ctrl = mlx5_dev_filter_ctrl, 301 .rx_descriptor_status = mlx5_rx_descriptor_status, 302 .tx_descriptor_status = mlx5_tx_descriptor_status, 303 .rx_queue_intr_enable = mlx5_rx_intr_enable, 304 .rx_queue_intr_disable = mlx5_rx_intr_disable, 305 }; 306 307 static const struct eth_dev_ops mlx5_dev_sec_ops = { 308 .stats_get = mlx5_stats_get, 309 .stats_reset = mlx5_stats_reset, 310 .xstats_get = mlx5_xstats_get, 311 .xstats_reset = mlx5_xstats_reset, 312 .xstats_get_names = mlx5_xstats_get_names, 313 .dev_infos_get = mlx5_dev_infos_get, 314 .rx_descriptor_status = mlx5_rx_descriptor_status, 315 .tx_descriptor_status = mlx5_tx_descriptor_status, 316 }; 317 318 /* Available operators in flow isolated mode. */ 319 const struct eth_dev_ops mlx5_dev_ops_isolate = { 320 .dev_configure = mlx5_dev_configure, 321 .dev_start = mlx5_dev_start, 322 .dev_stop = mlx5_dev_stop, 323 .dev_set_link_down = mlx5_set_link_down, 324 .dev_set_link_up = mlx5_set_link_up, 325 .dev_close = mlx5_dev_close, 326 .link_update = mlx5_link_update, 327 .stats_get = mlx5_stats_get, 328 .stats_reset = mlx5_stats_reset, 329 .xstats_get = mlx5_xstats_get, 330 .xstats_reset = mlx5_xstats_reset, 331 .xstats_get_names = mlx5_xstats_get_names, 332 .dev_infos_get = mlx5_dev_infos_get, 333 .dev_supported_ptypes_get = mlx5_dev_supported_ptypes_get, 334 .vlan_filter_set = mlx5_vlan_filter_set, 335 .rx_queue_setup = mlx5_rx_queue_setup, 336 .tx_queue_setup = mlx5_tx_queue_setup, 337 .rx_queue_release = mlx5_rx_queue_release, 338 .tx_queue_release = mlx5_tx_queue_release, 339 .flow_ctrl_get = mlx5_dev_get_flow_ctrl, 340 .flow_ctrl_set = mlx5_dev_set_flow_ctrl, 341 .mac_addr_remove = mlx5_mac_addr_remove, 342 .mac_addr_add = mlx5_mac_addr_add, 343 .mac_addr_set = mlx5_mac_addr_set, 344 .mtu_set = mlx5_dev_set_mtu, 345 .vlan_strip_queue_set = mlx5_vlan_strip_queue_set, 346 .vlan_offload_set = mlx5_vlan_offload_set, 347 .filter_ctrl = mlx5_dev_filter_ctrl, 348 .rx_descriptor_status = mlx5_rx_descriptor_status, 349 .tx_descriptor_status = mlx5_tx_descriptor_status, 350 .rx_queue_intr_enable = mlx5_rx_intr_enable, 351 .rx_queue_intr_disable = mlx5_rx_intr_disable, 352 }; 353 354 static struct { 355 struct rte_pci_addr pci_addr; /* associated PCI address */ 356 uint32_t ports; /* physical ports bitfield. */ 357 } mlx5_dev[32]; 358 359 /** 360 * Get device index in mlx5_dev[] from PCI bus address. 361 * 362 * @param[in] pci_addr 363 * PCI bus address to look for. 364 * 365 * @return 366 * mlx5_dev[] index on success, -1 on failure. 367 */ 368 static int 369 mlx5_dev_idx(struct rte_pci_addr *pci_addr) 370 { 371 unsigned int i; 372 int ret = -1; 373 374 assert(pci_addr != NULL); 375 for (i = 0; (i != RTE_DIM(mlx5_dev)); ++i) { 376 if ((mlx5_dev[i].pci_addr.domain == pci_addr->domain) && 377 (mlx5_dev[i].pci_addr.bus == pci_addr->bus) && 378 (mlx5_dev[i].pci_addr.devid == pci_addr->devid) && 379 (mlx5_dev[i].pci_addr.function == pci_addr->function)) 380 return i; 381 if ((mlx5_dev[i].ports == 0) && (ret == -1)) 382 ret = i; 383 } 384 return ret; 385 } 386 387 /** 388 * Verify and store value for device argument. 389 * 390 * @param[in] key 391 * Key argument to verify. 392 * @param[in] val 393 * Value associated with key. 394 * @param opaque 395 * User data. 396 * 397 * @return 398 * 0 on success, negative errno value on failure. 399 */ 400 static int 401 mlx5_args_check(const char *key, const char *val, void *opaque) 402 { 403 struct mlx5_args *args = opaque; 404 unsigned long tmp; 405 406 errno = 0; 407 tmp = strtoul(val, NULL, 0); 408 if (errno) { 409 WARN("%s: \"%s\" is not a valid integer", key, val); 410 return errno; 411 } 412 if (strcmp(MLX5_RXQ_CQE_COMP_EN, key) == 0) { 413 args->cqe_comp = !!tmp; 414 } else if (strcmp(MLX5_TXQ_INLINE, key) == 0) { 415 args->txq_inline = tmp; 416 } else if (strcmp(MLX5_TXQS_MIN_INLINE, key) == 0) { 417 args->txqs_inline = tmp; 418 } else if (strcmp(MLX5_TXQ_MPW_EN, key) == 0) { 419 args->mps = !!tmp; 420 } else if (strcmp(MLX5_TXQ_MPW_HDR_DSEG_EN, key) == 0) { 421 args->mpw_hdr_dseg = !!tmp; 422 } else if (strcmp(MLX5_TXQ_MAX_INLINE_LEN, key) == 0) { 423 args->inline_max_packet_sz = tmp; 424 } else if (strcmp(MLX5_TSO, key) == 0) { 425 args->tso = !!tmp; 426 } else if (strcmp(MLX5_TX_VEC_EN, key) == 0) { 427 args->tx_vec_en = !!tmp; 428 } else if (strcmp(MLX5_RX_VEC_EN, key) == 0) { 429 args->rx_vec_en = !!tmp; 430 } else { 431 WARN("%s: unknown parameter", key); 432 return -EINVAL; 433 } 434 return 0; 435 } 436 437 /** 438 * Parse device parameters. 439 * 440 * @param priv 441 * Pointer to private structure. 442 * @param devargs 443 * Device arguments structure. 444 * 445 * @return 446 * 0 on success, errno value on failure. 447 */ 448 static int 449 mlx5_args(struct mlx5_args *args, struct rte_devargs *devargs) 450 { 451 const char **params = (const char *[]){ 452 MLX5_RXQ_CQE_COMP_EN, 453 MLX5_TXQ_INLINE, 454 MLX5_TXQS_MIN_INLINE, 455 MLX5_TXQ_MPW_EN, 456 MLX5_TXQ_MPW_HDR_DSEG_EN, 457 MLX5_TXQ_MAX_INLINE_LEN, 458 MLX5_TSO, 459 MLX5_TX_VEC_EN, 460 MLX5_RX_VEC_EN, 461 NULL, 462 }; 463 struct rte_kvargs *kvlist; 464 int ret = 0; 465 int i; 466 467 if (devargs == NULL) 468 return 0; 469 /* Following UGLY cast is done to pass checkpatch. */ 470 kvlist = rte_kvargs_parse(devargs->args, params); 471 if (kvlist == NULL) 472 return 0; 473 /* Process parameters. */ 474 for (i = 0; (params[i] != NULL); ++i) { 475 if (rte_kvargs_count(kvlist, params[i])) { 476 ret = rte_kvargs_process(kvlist, params[i], 477 mlx5_args_check, args); 478 if (ret != 0) { 479 rte_kvargs_free(kvlist); 480 return ret; 481 } 482 } 483 } 484 rte_kvargs_free(kvlist); 485 return 0; 486 } 487 488 static struct rte_pci_driver mlx5_driver; 489 490 /** 491 * Assign parameters from args into priv, only non default 492 * values are considered. 493 * 494 * @param[out] priv 495 * Pointer to private structure. 496 * @param[in] args 497 * Pointer to args values. 498 */ 499 static void 500 mlx5_args_assign(struct priv *priv, struct mlx5_args *args) 501 { 502 if (args->cqe_comp != MLX5_ARG_UNSET) 503 priv->cqe_comp = args->cqe_comp; 504 if (args->txq_inline != MLX5_ARG_UNSET) 505 priv->txq_inline = args->txq_inline; 506 if (args->txqs_inline != MLX5_ARG_UNSET) 507 priv->txqs_inline = args->txqs_inline; 508 if (args->mps != MLX5_ARG_UNSET) 509 priv->mps = args->mps ? priv->mps : 0; 510 if (args->mpw_hdr_dseg != MLX5_ARG_UNSET) 511 priv->mpw_hdr_dseg = args->mpw_hdr_dseg; 512 if (args->inline_max_packet_sz != MLX5_ARG_UNSET) 513 priv->inline_max_packet_sz = args->inline_max_packet_sz; 514 if (args->tso != MLX5_ARG_UNSET) 515 priv->tso = args->tso; 516 if (args->tx_vec_en != MLX5_ARG_UNSET) 517 priv->tx_vec_en = args->tx_vec_en; 518 if (args->rx_vec_en != MLX5_ARG_UNSET) 519 priv->rx_vec_en = args->rx_vec_en; 520 } 521 522 /** 523 * DPDK callback to register a PCI device. 524 * 525 * This function creates an Ethernet device for each port of a given 526 * PCI device. 527 * 528 * @param[in] pci_drv 529 * PCI driver structure (mlx5_driver). 530 * @param[in] pci_dev 531 * PCI device information. 532 * 533 * @return 534 * 0 on success, negative errno value on failure. 535 */ 536 static int 537 mlx5_pci_probe(struct rte_pci_driver *pci_drv, struct rte_pci_device *pci_dev) 538 { 539 struct ibv_device **list; 540 struct ibv_device *ibv_dev; 541 int err = 0; 542 struct ibv_context *attr_ctx = NULL; 543 struct ibv_device_attr_ex device_attr; 544 unsigned int sriov; 545 unsigned int mps; 546 unsigned int cqe_comp; 547 unsigned int tunnel_en = 0; 548 int idx; 549 int i; 550 struct mlx5dv_context attrs_out; 551 #ifdef HAVE_IBV_DEVICE_COUNTERS_SET_SUPPORT 552 struct ibv_counter_set_description cs_desc; 553 #endif 554 555 (void)pci_drv; 556 assert(pci_drv == &mlx5_driver); 557 /* Get mlx5_dev[] index. */ 558 idx = mlx5_dev_idx(&pci_dev->addr); 559 if (idx == -1) { 560 ERROR("this driver cannot support any more adapters"); 561 return -ENOMEM; 562 } 563 DEBUG("using driver device index %d", idx); 564 565 /* Save PCI address. */ 566 mlx5_dev[idx].pci_addr = pci_dev->addr; 567 list = ibv_get_device_list(&i); 568 if (list == NULL) { 569 assert(errno); 570 if (errno == ENOSYS) 571 ERROR("cannot list devices, is ib_uverbs loaded?"); 572 return -errno; 573 } 574 assert(i >= 0); 575 /* 576 * For each listed device, check related sysfs entry against 577 * the provided PCI ID. 578 */ 579 while (i != 0) { 580 struct rte_pci_addr pci_addr; 581 582 --i; 583 DEBUG("checking device \"%s\"", list[i]->name); 584 if (mlx5_ibv_device_to_pci_addr(list[i], &pci_addr)) 585 continue; 586 if ((pci_dev->addr.domain != pci_addr.domain) || 587 (pci_dev->addr.bus != pci_addr.bus) || 588 (pci_dev->addr.devid != pci_addr.devid) || 589 (pci_dev->addr.function != pci_addr.function)) 590 continue; 591 sriov = ((pci_dev->id.device_id == 592 PCI_DEVICE_ID_MELLANOX_CONNECTX4VF) || 593 (pci_dev->id.device_id == 594 PCI_DEVICE_ID_MELLANOX_CONNECTX4LXVF) || 595 (pci_dev->id.device_id == 596 PCI_DEVICE_ID_MELLANOX_CONNECTX5VF) || 597 (pci_dev->id.device_id == 598 PCI_DEVICE_ID_MELLANOX_CONNECTX5EXVF)); 599 switch (pci_dev->id.device_id) { 600 case PCI_DEVICE_ID_MELLANOX_CONNECTX4: 601 tunnel_en = 1; 602 break; 603 case PCI_DEVICE_ID_MELLANOX_CONNECTX4LX: 604 case PCI_DEVICE_ID_MELLANOX_CONNECTX5: 605 case PCI_DEVICE_ID_MELLANOX_CONNECTX5VF: 606 case PCI_DEVICE_ID_MELLANOX_CONNECTX5EX: 607 case PCI_DEVICE_ID_MELLANOX_CONNECTX5EXVF: 608 tunnel_en = 1; 609 break; 610 default: 611 break; 612 } 613 INFO("PCI information matches, using device \"%s\"" 614 " (SR-IOV: %s)", 615 list[i]->name, 616 sriov ? "true" : "false"); 617 attr_ctx = ibv_open_device(list[i]); 618 err = errno; 619 break; 620 } 621 if (attr_ctx == NULL) { 622 ibv_free_device_list(list); 623 switch (err) { 624 case 0: 625 ERROR("cannot access device, is mlx5_ib loaded?"); 626 return -ENODEV; 627 case EINVAL: 628 ERROR("cannot use device, are drivers up to date?"); 629 return -EINVAL; 630 } 631 assert(err > 0); 632 return -err; 633 } 634 ibv_dev = list[i]; 635 636 DEBUG("device opened"); 637 /* 638 * Multi-packet send is supported by ConnectX-4 Lx PF as well 639 * as all ConnectX-5 devices. 640 */ 641 mlx5dv_query_device(attr_ctx, &attrs_out); 642 if (attrs_out.flags & (MLX5DV_CONTEXT_FLAGS_ENHANCED_MPW | 643 MLX5DV_CONTEXT_FLAGS_MPW_ALLOWED)) { 644 INFO("Enhanced MPW is detected\n"); 645 mps = MLX5_MPW_ENHANCED; 646 } else if (attrs_out.flags & MLX5DV_CONTEXT_FLAGS_MPW_ALLOWED) { 647 INFO("MPW is detected\n"); 648 mps = MLX5_MPW; 649 } else { 650 INFO("MPW is disabled\n"); 651 mps = MLX5_MPW_DISABLED; 652 } 653 if (RTE_CACHE_LINE_SIZE == 128 && 654 !(attrs_out.flags & MLX5DV_CONTEXT_FLAGS_CQE_128B_COMP)) 655 cqe_comp = 0; 656 else 657 cqe_comp = 1; 658 if (ibv_query_device_ex(attr_ctx, NULL, &device_attr)) 659 goto error; 660 INFO("%u port(s) detected", device_attr.orig_attr.phys_port_cnt); 661 662 for (i = 0; i < device_attr.orig_attr.phys_port_cnt; i++) { 663 uint32_t port = i + 1; /* ports are indexed from one */ 664 uint32_t test = (1 << i); 665 struct ibv_context *ctx = NULL; 666 struct ibv_port_attr port_attr; 667 struct ibv_pd *pd = NULL; 668 struct priv *priv = NULL; 669 struct rte_eth_dev *eth_dev; 670 struct ibv_device_attr_ex device_attr_ex; 671 struct ether_addr mac; 672 uint16_t num_vfs = 0; 673 struct ibv_device_attr_ex device_attr; 674 struct mlx5_args args = { 675 .cqe_comp = MLX5_ARG_UNSET, 676 .txq_inline = MLX5_ARG_UNSET, 677 .txqs_inline = MLX5_ARG_UNSET, 678 .mps = MLX5_ARG_UNSET, 679 .mpw_hdr_dseg = MLX5_ARG_UNSET, 680 .inline_max_packet_sz = MLX5_ARG_UNSET, 681 .tso = MLX5_ARG_UNSET, 682 .tx_vec_en = MLX5_ARG_UNSET, 683 .rx_vec_en = MLX5_ARG_UNSET, 684 }; 685 686 mlx5_dev[idx].ports |= test; 687 688 if (mlx5_is_secondary()) { 689 /* from rte_ethdev.c */ 690 char name[RTE_ETH_NAME_MAX_LEN]; 691 692 snprintf(name, sizeof(name), "%s port %u", 693 ibv_get_device_name(ibv_dev), port); 694 eth_dev = rte_eth_dev_attach_secondary(name); 695 if (eth_dev == NULL) { 696 ERROR("can not attach rte ethdev"); 697 err = ENOMEM; 698 goto error; 699 } 700 eth_dev->device = &pci_dev->device; 701 eth_dev->dev_ops = &mlx5_dev_sec_ops; 702 priv = eth_dev->data->dev_private; 703 /* Receive command fd from primary process */ 704 err = priv_socket_connect(priv); 705 if (err < 0) { 706 err = -err; 707 goto error; 708 } 709 /* Remap UAR for Tx queues. */ 710 err = priv_tx_uar_remap(priv, err); 711 if (err < 0) { 712 err = -err; 713 goto error; 714 } 715 priv_dev_select_rx_function(priv, eth_dev); 716 priv_dev_select_tx_function(priv, eth_dev); 717 continue; 718 } 719 720 DEBUG("using port %u (%08" PRIx32 ")", port, test); 721 722 ctx = ibv_open_device(ibv_dev); 723 if (ctx == NULL) { 724 err = ENODEV; 725 goto port_error; 726 } 727 728 ibv_query_device_ex(ctx, NULL, &device_attr); 729 /* Check port status. */ 730 err = ibv_query_port(ctx, port, &port_attr); 731 if (err) { 732 ERROR("port query failed: %s", strerror(err)); 733 goto port_error; 734 } 735 736 if (port_attr.link_layer != IBV_LINK_LAYER_ETHERNET) { 737 ERROR("port %d is not configured in Ethernet mode", 738 port); 739 err = EINVAL; 740 goto port_error; 741 } 742 743 if (port_attr.state != IBV_PORT_ACTIVE) 744 DEBUG("port %d is not active: \"%s\" (%d)", 745 port, ibv_port_state_str(port_attr.state), 746 port_attr.state); 747 748 /* Allocate protection domain. */ 749 pd = ibv_alloc_pd(ctx); 750 if (pd == NULL) { 751 ERROR("PD allocation failure"); 752 err = ENOMEM; 753 goto port_error; 754 } 755 756 mlx5_dev[idx].ports |= test; 757 758 /* from rte_ethdev.c */ 759 priv = rte_zmalloc("ethdev private structure", 760 sizeof(*priv), 761 RTE_CACHE_LINE_SIZE); 762 if (priv == NULL) { 763 ERROR("priv allocation failure"); 764 err = ENOMEM; 765 goto port_error; 766 } 767 768 priv->ctx = ctx; 769 strncpy(priv->ibdev_path, priv->ctx->device->ibdev_path, 770 sizeof(priv->ibdev_path)); 771 priv->device_attr = device_attr; 772 priv->port = port; 773 priv->pd = pd; 774 priv->mtu = ETHER_MTU; 775 priv->mps = mps; /* Enable MPW by default if supported. */ 776 priv->cqe_comp = cqe_comp; 777 priv->tunnel_en = tunnel_en; 778 /* Enable vector by default if supported. */ 779 priv->tx_vec_en = 1; 780 priv->rx_vec_en = 1; 781 err = mlx5_args(&args, pci_dev->device.devargs); 782 if (err) { 783 ERROR("failed to process device arguments: %s", 784 strerror(err)); 785 goto port_error; 786 } 787 mlx5_args_assign(priv, &args); 788 if (ibv_query_device_ex(ctx, NULL, &device_attr_ex)) { 789 ERROR("ibv_query_device_ex() failed"); 790 goto port_error; 791 } 792 793 priv->hw_csum = 794 !!(device_attr_ex.device_cap_flags_ex & 795 IBV_DEVICE_RAW_IP_CSUM); 796 DEBUG("checksum offloading is %ssupported", 797 (priv->hw_csum ? "" : "not ")); 798 799 #ifdef HAVE_IBV_DEVICE_VXLAN_SUPPORT 800 priv->hw_csum_l2tun = !!(exp_device_attr.exp_device_cap_flags & 801 IBV_DEVICE_VXLAN_SUPPORT); 802 #endif 803 DEBUG("L2 tunnel checksum offloads are %ssupported", 804 (priv->hw_csum_l2tun ? "" : "not ")); 805 806 #ifdef HAVE_IBV_DEVICE_COUNTERS_SET_SUPPORT 807 priv->counter_set_supported = !!(device_attr.max_counter_sets); 808 ibv_describe_counter_set(ctx, 0, &cs_desc); 809 DEBUG("counter type = %d, num of cs = %ld, attributes = %d", 810 cs_desc.counter_type, cs_desc.num_of_cs, 811 cs_desc.attributes); 812 #endif 813 priv->ind_table_max_size = 814 device_attr_ex.rss_caps.max_rwq_indirection_table_size; 815 /* Remove this check once DPDK supports larger/variable 816 * indirection tables. */ 817 if (priv->ind_table_max_size > 818 (unsigned int)ETH_RSS_RETA_SIZE_512) 819 priv->ind_table_max_size = ETH_RSS_RETA_SIZE_512; 820 DEBUG("maximum RX indirection table size is %u", 821 priv->ind_table_max_size); 822 priv->hw_vlan_strip = !!(device_attr_ex.raw_packet_caps & 823 IBV_RAW_PACKET_CAP_CVLAN_STRIPPING); 824 DEBUG("VLAN stripping is %ssupported", 825 (priv->hw_vlan_strip ? "" : "not ")); 826 827 priv->hw_fcs_strip = 828 !!(device_attr_ex.orig_attr.device_cap_flags & 829 IBV_WQ_FLAGS_SCATTER_FCS); 830 DEBUG("FCS stripping configuration is %ssupported", 831 (priv->hw_fcs_strip ? "" : "not ")); 832 833 #ifdef HAVE_IBV_WQ_FLAG_RX_END_PADDING 834 priv->hw_padding = !!device_attr_ex.rx_pad_end_addr_align; 835 #endif 836 DEBUG("hardware RX end alignment padding is %ssupported", 837 (priv->hw_padding ? "" : "not ")); 838 839 priv_get_num_vfs(priv, &num_vfs); 840 priv->sriov = (num_vfs || sriov); 841 priv->tso = ((priv->tso) && 842 (device_attr_ex.tso_caps.max_tso > 0) && 843 (device_attr_ex.tso_caps.supported_qpts & 844 (1 << IBV_QPT_RAW_PACKET))); 845 if (priv->tso) 846 priv->max_tso_payload_sz = 847 device_attr_ex.tso_caps.max_tso; 848 if (priv->mps && !mps) { 849 ERROR("multi-packet send not supported on this device" 850 " (" MLX5_TXQ_MPW_EN ")"); 851 err = ENOTSUP; 852 goto port_error; 853 } else if (priv->mps && priv->tso) { 854 WARN("multi-packet send not supported in conjunction " 855 "with TSO. MPS disabled"); 856 priv->mps = 0; 857 } 858 INFO("%sMPS is %s", 859 priv->mps == MLX5_MPW_ENHANCED ? "Enhanced " : "", 860 priv->mps != MLX5_MPW_DISABLED ? "enabled" : "disabled"); 861 /* Set default values for Enhanced MPW, a.k.a MPWv2. */ 862 if (priv->mps == MLX5_MPW_ENHANCED) { 863 if (args.txqs_inline == MLX5_ARG_UNSET) 864 priv->txqs_inline = MLX5_EMPW_MIN_TXQS; 865 if (args.inline_max_packet_sz == MLX5_ARG_UNSET) 866 priv->inline_max_packet_sz = 867 MLX5_EMPW_MAX_INLINE_LEN; 868 if (args.txq_inline == MLX5_ARG_UNSET) 869 priv->txq_inline = MLX5_WQE_SIZE_MAX - 870 MLX5_WQE_SIZE; 871 } 872 if (priv->cqe_comp && !cqe_comp) { 873 WARN("Rx CQE compression isn't supported"); 874 priv->cqe_comp = 0; 875 } 876 /* Configure the first MAC address by default. */ 877 if (priv_get_mac(priv, &mac.addr_bytes)) { 878 ERROR("cannot get MAC address, is mlx5_en loaded?" 879 " (errno: %s)", strerror(errno)); 880 err = ENODEV; 881 goto port_error; 882 } 883 INFO("port %u MAC address is %02x:%02x:%02x:%02x:%02x:%02x", 884 priv->port, 885 mac.addr_bytes[0], mac.addr_bytes[1], 886 mac.addr_bytes[2], mac.addr_bytes[3], 887 mac.addr_bytes[4], mac.addr_bytes[5]); 888 #ifndef NDEBUG 889 { 890 char ifname[IF_NAMESIZE]; 891 892 if (priv_get_ifname(priv, &ifname) == 0) 893 DEBUG("port %u ifname is \"%s\"", 894 priv->port, ifname); 895 else 896 DEBUG("port %u ifname is unknown", priv->port); 897 } 898 #endif 899 /* Get actual MTU if possible. */ 900 priv_get_mtu(priv, &priv->mtu); 901 DEBUG("port %u MTU is %u", priv->port, priv->mtu); 902 903 /* from rte_ethdev.c */ 904 { 905 char name[RTE_ETH_NAME_MAX_LEN]; 906 907 snprintf(name, sizeof(name), "%s port %u", 908 ibv_get_device_name(ibv_dev), port); 909 eth_dev = rte_eth_dev_allocate(name); 910 } 911 if (eth_dev == NULL) { 912 ERROR("can not allocate rte ethdev"); 913 err = ENOMEM; 914 goto port_error; 915 } 916 eth_dev->data->dev_private = priv; 917 eth_dev->data->mac_addrs = priv->mac; 918 eth_dev->device = &pci_dev->device; 919 rte_eth_copy_pci_info(eth_dev, pci_dev); 920 eth_dev->data->dev_flags |= RTE_ETH_DEV_DETACHABLE; 921 eth_dev->device->driver = &mlx5_driver.driver; 922 priv->dev = eth_dev; 923 eth_dev->dev_ops = &mlx5_dev_ops; 924 /* Register MAC address. */ 925 claim_zero(mlx5_mac_addr_add(eth_dev, &mac, 0, 0)); 926 TAILQ_INIT(&priv->flows); 927 TAILQ_INIT(&priv->ctrl_flows); 928 929 /* Hint libmlx5 to use PMD allocator for data plane resources */ 930 struct mlx5dv_ctx_allocators alctr = { 931 .alloc = &mlx5_alloc_verbs_buf, 932 .free = &mlx5_free_verbs_buf, 933 .data = priv, 934 }; 935 mlx5dv_set_context_attr(ctx, MLX5DV_CTX_ATTR_BUF_ALLOCATORS, 936 (void *)((uintptr_t)&alctr)); 937 938 /* Bring Ethernet device up. */ 939 DEBUG("forcing Ethernet interface up"); 940 priv_set_flags(priv, ~IFF_UP, IFF_UP); 941 mlx5_link_update(priv->dev, 1); 942 continue; 943 944 port_error: 945 if (priv) 946 rte_free(priv); 947 if (pd) 948 claim_zero(ibv_dealloc_pd(pd)); 949 if (ctx) 950 claim_zero(ibv_close_device(ctx)); 951 break; 952 } 953 954 /* 955 * XXX if something went wrong in the loop above, there is a resource 956 * leak (ctx, pd, priv, dpdk ethdev) but we can do nothing about it as 957 * long as the dpdk does not provide a way to deallocate a ethdev and a 958 * way to enumerate the registered ethdevs to free the previous ones. 959 */ 960 961 /* no port found, complain */ 962 if (!mlx5_dev[idx].ports) { 963 err = ENODEV; 964 goto error; 965 } 966 967 error: 968 if (attr_ctx) 969 claim_zero(ibv_close_device(attr_ctx)); 970 if (list) 971 ibv_free_device_list(list); 972 assert(err >= 0); 973 return -err; 974 } 975 976 static const struct rte_pci_id mlx5_pci_id_map[] = { 977 { 978 RTE_PCI_DEVICE(PCI_VENDOR_ID_MELLANOX, 979 PCI_DEVICE_ID_MELLANOX_CONNECTX4) 980 }, 981 { 982 RTE_PCI_DEVICE(PCI_VENDOR_ID_MELLANOX, 983 PCI_DEVICE_ID_MELLANOX_CONNECTX4VF) 984 }, 985 { 986 RTE_PCI_DEVICE(PCI_VENDOR_ID_MELLANOX, 987 PCI_DEVICE_ID_MELLANOX_CONNECTX4LX) 988 }, 989 { 990 RTE_PCI_DEVICE(PCI_VENDOR_ID_MELLANOX, 991 PCI_DEVICE_ID_MELLANOX_CONNECTX4LXVF) 992 }, 993 { 994 RTE_PCI_DEVICE(PCI_VENDOR_ID_MELLANOX, 995 PCI_DEVICE_ID_MELLANOX_CONNECTX5) 996 }, 997 { 998 RTE_PCI_DEVICE(PCI_VENDOR_ID_MELLANOX, 999 PCI_DEVICE_ID_MELLANOX_CONNECTX5VF) 1000 }, 1001 { 1002 RTE_PCI_DEVICE(PCI_VENDOR_ID_MELLANOX, 1003 PCI_DEVICE_ID_MELLANOX_CONNECTX5EX) 1004 }, 1005 { 1006 RTE_PCI_DEVICE(PCI_VENDOR_ID_MELLANOX, 1007 PCI_DEVICE_ID_MELLANOX_CONNECTX5EXVF) 1008 }, 1009 { 1010 .vendor_id = 0 1011 } 1012 }; 1013 1014 static struct rte_pci_driver mlx5_driver = { 1015 .driver = { 1016 .name = MLX5_DRIVER_NAME 1017 }, 1018 .id_table = mlx5_pci_id_map, 1019 .probe = mlx5_pci_probe, 1020 .drv_flags = RTE_PCI_DRV_INTR_LSC | RTE_PCI_DRV_INTR_RMV, 1021 }; 1022 1023 /** 1024 * Driver initialization routine. 1025 */ 1026 RTE_INIT(rte_mlx5_pmd_init); 1027 static void 1028 rte_mlx5_pmd_init(void) 1029 { 1030 /* Build the static table for ptype conversion. */ 1031 mlx5_set_ptype_table(); 1032 /* 1033 * RDMAV_HUGEPAGES_SAFE tells ibv_fork_init() we intend to use 1034 * huge pages. Calling ibv_fork_init() during init allows 1035 * applications to use fork() safely for purposes other than 1036 * using this PMD, which is not supported in forked processes. 1037 */ 1038 setenv("RDMAV_HUGEPAGES_SAFE", "1", 1); 1039 /* Don't map UAR to WC if BlueFlame is not used.*/ 1040 setenv("MLX5_SHUT_UP_BF", "1", 1); 1041 /* Match the size of Rx completion entry to the size of a cacheline. */ 1042 if (RTE_CACHE_LINE_SIZE == 128) 1043 setenv("MLX5_CQE_SIZE", "128", 0); 1044 ibv_fork_init(); 1045 rte_pci_register(&mlx5_driver); 1046 } 1047 1048 RTE_PMD_EXPORT_NAME(net_mlx5, __COUNTER__); 1049 RTE_PMD_REGISTER_PCI_TABLE(net_mlx5, mlx5_pci_id_map); 1050 RTE_PMD_REGISTER_KMOD_DEP(net_mlx5, "* ib_uverbs & mlx5_core & mlx5_ib"); 1051