1 /*- 2 * BSD LICENSE 3 * 4 * Copyright 2015 6WIND S.A. 5 * Copyright 2015 Mellanox. 6 * 7 * Redistribution and use in source and binary forms, with or without 8 * modification, are permitted provided that the following conditions 9 * are met: 10 * 11 * * Redistributions of source code must retain the above copyright 12 * notice, this list of conditions and the following disclaimer. 13 * * Redistributions in binary form must reproduce the above copyright 14 * notice, this list of conditions and the following disclaimer in 15 * the documentation and/or other materials provided with the 16 * distribution. 17 * * Neither the name of 6WIND S.A. nor the names of its 18 * contributors may be used to endorse or promote products derived 19 * from this software without specific prior written permission. 20 * 21 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 22 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 23 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 24 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 25 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 26 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 27 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 28 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 29 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 30 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 31 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 32 */ 33 34 #include <stddef.h> 35 #include <unistd.h> 36 #include <string.h> 37 #include <assert.h> 38 #include <stdint.h> 39 #include <stdlib.h> 40 #include <errno.h> 41 #include <net/if.h> 42 43 /* Verbs header. */ 44 /* ISO C doesn't support unnamed structs/unions, disabling -pedantic. */ 45 #ifdef PEDANTIC 46 #pragma GCC diagnostic ignored "-Wpedantic" 47 #endif 48 #include <infiniband/verbs.h> 49 #ifdef PEDANTIC 50 #pragma GCC diagnostic error "-Wpedantic" 51 #endif 52 53 #include <rte_malloc.h> 54 #include <rte_ethdev.h> 55 #include <rte_ethdev_pci.h> 56 #include <rte_pci.h> 57 #include <rte_bus_pci.h> 58 #include <rte_common.h> 59 #include <rte_kvargs.h> 60 61 #include "mlx5.h" 62 #include "mlx5_utils.h" 63 #include "mlx5_rxtx.h" 64 #include "mlx5_autoconf.h" 65 #include "mlx5_defs.h" 66 67 /* Device parameter to enable RX completion queue compression. */ 68 #define MLX5_RXQ_CQE_COMP_EN "rxq_cqe_comp_en" 69 70 /* Device parameter to configure inline send. */ 71 #define MLX5_TXQ_INLINE "txq_inline" 72 73 /* 74 * Device parameter to configure the number of TX queues threshold for 75 * enabling inline send. 76 */ 77 #define MLX5_TXQS_MIN_INLINE "txqs_min_inline" 78 79 /* Device parameter to enable multi-packet send WQEs. */ 80 #define MLX5_TXQ_MPW_EN "txq_mpw_en" 81 82 /* Device parameter to include 2 dsegs in the title WQEBB. */ 83 #define MLX5_TXQ_MPW_HDR_DSEG_EN "txq_mpw_hdr_dseg_en" 84 85 /* Device parameter to limit the size of inlining packet. */ 86 #define MLX5_TXQ_MAX_INLINE_LEN "txq_max_inline_len" 87 88 /* Device parameter to enable hardware Tx vector. */ 89 #define MLX5_TX_VEC_EN "tx_vec_en" 90 91 /* Device parameter to enable hardware Rx vector. */ 92 #define MLX5_RX_VEC_EN "rx_vec_en" 93 94 #ifndef HAVE_IBV_MLX5_MOD_MPW 95 #define MLX5DV_CONTEXT_FLAGS_MPW_ALLOWED (1 << 2) 96 #define MLX5DV_CONTEXT_FLAGS_ENHANCED_MPW (1 << 3) 97 #endif 98 99 #ifndef HAVE_IBV_MLX5_MOD_CQE_128B_COMP 100 #define MLX5DV_CONTEXT_FLAGS_CQE_128B_COMP (1 << 4) 101 #endif 102 103 /** 104 * Retrieve integer value from environment variable. 105 * 106 * @param[in] name 107 * Environment variable name. 108 * 109 * @return 110 * Integer value, 0 if the variable is not set. 111 */ 112 int 113 mlx5_getenv_int(const char *name) 114 { 115 const char *val = getenv(name); 116 117 if (val == NULL) 118 return 0; 119 return atoi(val); 120 } 121 122 /** 123 * Verbs callback to allocate a memory. This function should allocate the space 124 * according to the size provided residing inside a huge page. 125 * Please note that all allocation must respect the alignment from libmlx5 126 * (i.e. currently sysconf(_SC_PAGESIZE)). 127 * 128 * @param[in] size 129 * The size in bytes of the memory to allocate. 130 * @param[in] data 131 * A pointer to the callback data. 132 * 133 * @return 134 * a pointer to the allocate space. 135 */ 136 static void * 137 mlx5_alloc_verbs_buf(size_t size, void *data) 138 { 139 struct priv *priv = data; 140 void *ret; 141 size_t alignment = sysconf(_SC_PAGESIZE); 142 143 assert(data != NULL); 144 ret = rte_malloc_socket(__func__, size, alignment, 145 priv->dev->device->numa_node); 146 DEBUG("Extern alloc size: %lu, align: %lu: %p", size, alignment, ret); 147 return ret; 148 } 149 150 /** 151 * Verbs callback to free a memory. 152 * 153 * @param[in] ptr 154 * A pointer to the memory to free. 155 * @param[in] data 156 * A pointer to the callback data. 157 */ 158 static void 159 mlx5_free_verbs_buf(void *ptr, void *data __rte_unused) 160 { 161 assert(data != NULL); 162 DEBUG("Extern free request: %p", ptr); 163 rte_free(ptr); 164 } 165 166 /** 167 * DPDK callback to close the device. 168 * 169 * Destroy all queues and objects, free memory. 170 * 171 * @param dev 172 * Pointer to Ethernet device structure. 173 */ 174 static void 175 mlx5_dev_close(struct rte_eth_dev *dev) 176 { 177 struct priv *priv = dev->data->dev_private; 178 unsigned int i; 179 int ret; 180 181 priv_lock(priv); 182 DEBUG("%p: closing device \"%s\"", 183 (void *)dev, 184 ((priv->ctx != NULL) ? priv->ctx->device->name : "")); 185 /* In case mlx5_dev_stop() has not been called. */ 186 priv_dev_interrupt_handler_uninstall(priv, dev); 187 priv_dev_traffic_disable(priv, dev); 188 /* Prevent crashes when queues are still in use. */ 189 dev->rx_pkt_burst = removed_rx_burst; 190 dev->tx_pkt_burst = removed_tx_burst; 191 if (priv->rxqs != NULL) { 192 /* XXX race condition if mlx5_rx_burst() is still running. */ 193 usleep(1000); 194 for (i = 0; (i != priv->rxqs_n); ++i) 195 mlx5_priv_rxq_release(priv, i); 196 priv->rxqs_n = 0; 197 priv->rxqs = NULL; 198 } 199 if (priv->txqs != NULL) { 200 /* XXX race condition if mlx5_tx_burst() is still running. */ 201 usleep(1000); 202 for (i = 0; (i != priv->txqs_n); ++i) 203 mlx5_priv_txq_release(priv, i); 204 priv->txqs_n = 0; 205 priv->txqs = NULL; 206 } 207 if (priv->pd != NULL) { 208 assert(priv->ctx != NULL); 209 claim_zero(ibv_dealloc_pd(priv->pd)); 210 claim_zero(ibv_close_device(priv->ctx)); 211 } else 212 assert(priv->ctx == NULL); 213 if (priv->rss_conf.rss_key != NULL) 214 rte_free(priv->rss_conf.rss_key); 215 if (priv->reta_idx != NULL) 216 rte_free(priv->reta_idx); 217 priv_socket_uninit(priv); 218 ret = mlx5_priv_hrxq_ibv_verify(priv); 219 if (ret) 220 WARN("%p: some Hash Rx queue still remain", (void *)priv); 221 ret = mlx5_priv_ind_table_ibv_verify(priv); 222 if (ret) 223 WARN("%p: some Indirection table still remain", (void *)priv); 224 ret = mlx5_priv_rxq_ibv_verify(priv); 225 if (ret) 226 WARN("%p: some Verbs Rx queue still remain", (void *)priv); 227 ret = mlx5_priv_rxq_verify(priv); 228 if (ret) 229 WARN("%p: some Rx Queues still remain", (void *)priv); 230 ret = mlx5_priv_txq_ibv_verify(priv); 231 if (ret) 232 WARN("%p: some Verbs Tx queue still remain", (void *)priv); 233 ret = mlx5_priv_txq_verify(priv); 234 if (ret) 235 WARN("%p: some Tx Queues still remain", (void *)priv); 236 ret = priv_flow_verify(priv); 237 if (ret) 238 WARN("%p: some flows still remain", (void *)priv); 239 ret = priv_mr_verify(priv); 240 if (ret) 241 WARN("%p: some Memory Region still remain", (void *)priv); 242 priv_unlock(priv); 243 memset(priv, 0, sizeof(*priv)); 244 } 245 246 const struct eth_dev_ops mlx5_dev_ops = { 247 .dev_configure = mlx5_dev_configure, 248 .dev_start = mlx5_dev_start, 249 .dev_stop = mlx5_dev_stop, 250 .dev_set_link_down = mlx5_set_link_down, 251 .dev_set_link_up = mlx5_set_link_up, 252 .dev_close = mlx5_dev_close, 253 .promiscuous_enable = mlx5_promiscuous_enable, 254 .promiscuous_disable = mlx5_promiscuous_disable, 255 .allmulticast_enable = mlx5_allmulticast_enable, 256 .allmulticast_disable = mlx5_allmulticast_disable, 257 .link_update = mlx5_link_update, 258 .stats_get = mlx5_stats_get, 259 .stats_reset = mlx5_stats_reset, 260 .xstats_get = mlx5_xstats_get, 261 .xstats_reset = mlx5_xstats_reset, 262 .xstats_get_names = mlx5_xstats_get_names, 263 .dev_infos_get = mlx5_dev_infos_get, 264 .dev_supported_ptypes_get = mlx5_dev_supported_ptypes_get, 265 .vlan_filter_set = mlx5_vlan_filter_set, 266 .rx_queue_setup = mlx5_rx_queue_setup, 267 .tx_queue_setup = mlx5_tx_queue_setup, 268 .rx_queue_release = mlx5_rx_queue_release, 269 .tx_queue_release = mlx5_tx_queue_release, 270 .flow_ctrl_get = mlx5_dev_get_flow_ctrl, 271 .flow_ctrl_set = mlx5_dev_set_flow_ctrl, 272 .mac_addr_remove = mlx5_mac_addr_remove, 273 .mac_addr_add = mlx5_mac_addr_add, 274 .mac_addr_set = mlx5_mac_addr_set, 275 .mtu_set = mlx5_dev_set_mtu, 276 .vlan_strip_queue_set = mlx5_vlan_strip_queue_set, 277 .vlan_offload_set = mlx5_vlan_offload_set, 278 .reta_update = mlx5_dev_rss_reta_update, 279 .reta_query = mlx5_dev_rss_reta_query, 280 .rss_hash_update = mlx5_rss_hash_update, 281 .rss_hash_conf_get = mlx5_rss_hash_conf_get, 282 .filter_ctrl = mlx5_dev_filter_ctrl, 283 .rx_descriptor_status = mlx5_rx_descriptor_status, 284 .tx_descriptor_status = mlx5_tx_descriptor_status, 285 .rx_queue_intr_enable = mlx5_rx_intr_enable, 286 .rx_queue_intr_disable = mlx5_rx_intr_disable, 287 }; 288 289 static const struct eth_dev_ops mlx5_dev_sec_ops = { 290 .stats_get = mlx5_stats_get, 291 .stats_reset = mlx5_stats_reset, 292 .xstats_get = mlx5_xstats_get, 293 .xstats_reset = mlx5_xstats_reset, 294 .xstats_get_names = mlx5_xstats_get_names, 295 .dev_infos_get = mlx5_dev_infos_get, 296 .rx_descriptor_status = mlx5_rx_descriptor_status, 297 .tx_descriptor_status = mlx5_tx_descriptor_status, 298 }; 299 300 /* Available operators in flow isolated mode. */ 301 const struct eth_dev_ops mlx5_dev_ops_isolate = { 302 .dev_configure = mlx5_dev_configure, 303 .dev_start = mlx5_dev_start, 304 .dev_stop = mlx5_dev_stop, 305 .dev_set_link_down = mlx5_set_link_down, 306 .dev_set_link_up = mlx5_set_link_up, 307 .dev_close = mlx5_dev_close, 308 .link_update = mlx5_link_update, 309 .stats_get = mlx5_stats_get, 310 .stats_reset = mlx5_stats_reset, 311 .xstats_get = mlx5_xstats_get, 312 .xstats_reset = mlx5_xstats_reset, 313 .xstats_get_names = mlx5_xstats_get_names, 314 .dev_infos_get = mlx5_dev_infos_get, 315 .dev_supported_ptypes_get = mlx5_dev_supported_ptypes_get, 316 .vlan_filter_set = mlx5_vlan_filter_set, 317 .rx_queue_setup = mlx5_rx_queue_setup, 318 .tx_queue_setup = mlx5_tx_queue_setup, 319 .rx_queue_release = mlx5_rx_queue_release, 320 .tx_queue_release = mlx5_tx_queue_release, 321 .flow_ctrl_get = mlx5_dev_get_flow_ctrl, 322 .flow_ctrl_set = mlx5_dev_set_flow_ctrl, 323 .mac_addr_remove = mlx5_mac_addr_remove, 324 .mac_addr_add = mlx5_mac_addr_add, 325 .mac_addr_set = mlx5_mac_addr_set, 326 .mtu_set = mlx5_dev_set_mtu, 327 .vlan_strip_queue_set = mlx5_vlan_strip_queue_set, 328 .vlan_offload_set = mlx5_vlan_offload_set, 329 .filter_ctrl = mlx5_dev_filter_ctrl, 330 .rx_descriptor_status = mlx5_rx_descriptor_status, 331 .tx_descriptor_status = mlx5_tx_descriptor_status, 332 .rx_queue_intr_enable = mlx5_rx_intr_enable, 333 .rx_queue_intr_disable = mlx5_rx_intr_disable, 334 }; 335 336 static struct { 337 struct rte_pci_addr pci_addr; /* associated PCI address */ 338 uint32_t ports; /* physical ports bitfield. */ 339 } mlx5_dev[32]; 340 341 /** 342 * Get device index in mlx5_dev[] from PCI bus address. 343 * 344 * @param[in] pci_addr 345 * PCI bus address to look for. 346 * 347 * @return 348 * mlx5_dev[] index on success, -1 on failure. 349 */ 350 static int 351 mlx5_dev_idx(struct rte_pci_addr *pci_addr) 352 { 353 unsigned int i; 354 int ret = -1; 355 356 assert(pci_addr != NULL); 357 for (i = 0; (i != RTE_DIM(mlx5_dev)); ++i) { 358 if ((mlx5_dev[i].pci_addr.domain == pci_addr->domain) && 359 (mlx5_dev[i].pci_addr.bus == pci_addr->bus) && 360 (mlx5_dev[i].pci_addr.devid == pci_addr->devid) && 361 (mlx5_dev[i].pci_addr.function == pci_addr->function)) 362 return i; 363 if ((mlx5_dev[i].ports == 0) && (ret == -1)) 364 ret = i; 365 } 366 return ret; 367 } 368 369 /** 370 * Verify and store value for device argument. 371 * 372 * @param[in] key 373 * Key argument to verify. 374 * @param[in] val 375 * Value associated with key. 376 * @param opaque 377 * User data. 378 * 379 * @return 380 * 0 on success, negative errno value on failure. 381 */ 382 static int 383 mlx5_args_check(const char *key, const char *val, void *opaque) 384 { 385 struct mlx5_dev_config *config = opaque; 386 unsigned long tmp; 387 388 errno = 0; 389 tmp = strtoul(val, NULL, 0); 390 if (errno) { 391 WARN("%s: \"%s\" is not a valid integer", key, val); 392 return errno; 393 } 394 if (strcmp(MLX5_RXQ_CQE_COMP_EN, key) == 0) { 395 config->cqe_comp = !!tmp; 396 } else if (strcmp(MLX5_TXQ_INLINE, key) == 0) { 397 config->txq_inline = tmp; 398 } else if (strcmp(MLX5_TXQS_MIN_INLINE, key) == 0) { 399 config->txqs_inline = tmp; 400 } else if (strcmp(MLX5_TXQ_MPW_EN, key) == 0) { 401 config->mps = !!tmp ? config->mps : 0; 402 } else if (strcmp(MLX5_TXQ_MPW_HDR_DSEG_EN, key) == 0) { 403 config->mpw_hdr_dseg = !!tmp; 404 } else if (strcmp(MLX5_TXQ_MAX_INLINE_LEN, key) == 0) { 405 config->inline_max_packet_sz = tmp; 406 } else if (strcmp(MLX5_TX_VEC_EN, key) == 0) { 407 config->tx_vec_en = !!tmp; 408 } else if (strcmp(MLX5_RX_VEC_EN, key) == 0) { 409 config->rx_vec_en = !!tmp; 410 } else { 411 WARN("%s: unknown parameter", key); 412 return -EINVAL; 413 } 414 return 0; 415 } 416 417 /** 418 * Parse device parameters. 419 * 420 * @param config 421 * Pointer to device configuration structure. 422 * @param devargs 423 * Device arguments structure. 424 * 425 * @return 426 * 0 on success, errno value on failure. 427 */ 428 static int 429 mlx5_args(struct mlx5_dev_config *config, struct rte_devargs *devargs) 430 { 431 const char **params = (const char *[]){ 432 MLX5_RXQ_CQE_COMP_EN, 433 MLX5_TXQ_INLINE, 434 MLX5_TXQS_MIN_INLINE, 435 MLX5_TXQ_MPW_EN, 436 MLX5_TXQ_MPW_HDR_DSEG_EN, 437 MLX5_TXQ_MAX_INLINE_LEN, 438 MLX5_TX_VEC_EN, 439 MLX5_RX_VEC_EN, 440 NULL, 441 }; 442 struct rte_kvargs *kvlist; 443 int ret = 0; 444 int i; 445 446 if (devargs == NULL) 447 return 0; 448 /* Following UGLY cast is done to pass checkpatch. */ 449 kvlist = rte_kvargs_parse(devargs->args, params); 450 if (kvlist == NULL) 451 return 0; 452 /* Process parameters. */ 453 for (i = 0; (params[i] != NULL); ++i) { 454 if (rte_kvargs_count(kvlist, params[i])) { 455 ret = rte_kvargs_process(kvlist, params[i], 456 mlx5_args_check, config); 457 if (ret != 0) { 458 rte_kvargs_free(kvlist); 459 return ret; 460 } 461 } 462 } 463 rte_kvargs_free(kvlist); 464 return 0; 465 } 466 467 static struct rte_pci_driver mlx5_driver; 468 469 /** 470 * DPDK callback to register a PCI device. 471 * 472 * This function creates an Ethernet device for each port of a given 473 * PCI device. 474 * 475 * @param[in] pci_drv 476 * PCI driver structure (mlx5_driver). 477 * @param[in] pci_dev 478 * PCI device information. 479 * 480 * @return 481 * 0 on success, negative errno value on failure. 482 */ 483 static int 484 mlx5_pci_probe(struct rte_pci_driver *pci_drv, struct rte_pci_device *pci_dev) 485 { 486 struct ibv_device **list; 487 struct ibv_device *ibv_dev; 488 int err = 0; 489 struct ibv_context *attr_ctx = NULL; 490 struct ibv_device_attr_ex device_attr; 491 unsigned int sriov; 492 unsigned int mps; 493 unsigned int cqe_comp; 494 unsigned int tunnel_en = 0; 495 int idx; 496 int i; 497 struct mlx5dv_context attrs_out; 498 #ifdef HAVE_IBV_DEVICE_COUNTERS_SET_SUPPORT 499 struct ibv_counter_set_description cs_desc; 500 #endif 501 502 (void)pci_drv; 503 assert(pci_drv == &mlx5_driver); 504 /* Get mlx5_dev[] index. */ 505 idx = mlx5_dev_idx(&pci_dev->addr); 506 if (idx == -1) { 507 ERROR("this driver cannot support any more adapters"); 508 return -ENOMEM; 509 } 510 DEBUG("using driver device index %d", idx); 511 512 /* Save PCI address. */ 513 mlx5_dev[idx].pci_addr = pci_dev->addr; 514 list = ibv_get_device_list(&i); 515 if (list == NULL) { 516 assert(errno); 517 if (errno == ENOSYS) 518 ERROR("cannot list devices, is ib_uverbs loaded?"); 519 return -errno; 520 } 521 assert(i >= 0); 522 /* 523 * For each listed device, check related sysfs entry against 524 * the provided PCI ID. 525 */ 526 while (i != 0) { 527 struct rte_pci_addr pci_addr; 528 529 --i; 530 DEBUG("checking device \"%s\"", list[i]->name); 531 if (mlx5_ibv_device_to_pci_addr(list[i], &pci_addr)) 532 continue; 533 if ((pci_dev->addr.domain != pci_addr.domain) || 534 (pci_dev->addr.bus != pci_addr.bus) || 535 (pci_dev->addr.devid != pci_addr.devid) || 536 (pci_dev->addr.function != pci_addr.function)) 537 continue; 538 sriov = ((pci_dev->id.device_id == 539 PCI_DEVICE_ID_MELLANOX_CONNECTX4VF) || 540 (pci_dev->id.device_id == 541 PCI_DEVICE_ID_MELLANOX_CONNECTX4LXVF) || 542 (pci_dev->id.device_id == 543 PCI_DEVICE_ID_MELLANOX_CONNECTX5VF) || 544 (pci_dev->id.device_id == 545 PCI_DEVICE_ID_MELLANOX_CONNECTX5EXVF)); 546 switch (pci_dev->id.device_id) { 547 case PCI_DEVICE_ID_MELLANOX_CONNECTX4: 548 tunnel_en = 1; 549 break; 550 case PCI_DEVICE_ID_MELLANOX_CONNECTX4LX: 551 case PCI_DEVICE_ID_MELLANOX_CONNECTX5: 552 case PCI_DEVICE_ID_MELLANOX_CONNECTX5VF: 553 case PCI_DEVICE_ID_MELLANOX_CONNECTX5EX: 554 case PCI_DEVICE_ID_MELLANOX_CONNECTX5EXVF: 555 tunnel_en = 1; 556 break; 557 default: 558 break; 559 } 560 INFO("PCI information matches, using device \"%s\"" 561 " (SR-IOV: %s)", 562 list[i]->name, 563 sriov ? "true" : "false"); 564 attr_ctx = ibv_open_device(list[i]); 565 err = errno; 566 break; 567 } 568 if (attr_ctx == NULL) { 569 ibv_free_device_list(list); 570 switch (err) { 571 case 0: 572 ERROR("cannot access device, is mlx5_ib loaded?"); 573 return -ENODEV; 574 case EINVAL: 575 ERROR("cannot use device, are drivers up to date?"); 576 return -EINVAL; 577 } 578 assert(err > 0); 579 return -err; 580 } 581 ibv_dev = list[i]; 582 583 DEBUG("device opened"); 584 /* 585 * Multi-packet send is supported by ConnectX-4 Lx PF as well 586 * as all ConnectX-5 devices. 587 */ 588 mlx5dv_query_device(attr_ctx, &attrs_out); 589 if (attrs_out.flags & MLX5DV_CONTEXT_FLAGS_MPW_ALLOWED) { 590 if (attrs_out.flags & MLX5DV_CONTEXT_FLAGS_ENHANCED_MPW) { 591 DEBUG("Enhanced MPW is supported"); 592 mps = MLX5_MPW_ENHANCED; 593 } else { 594 DEBUG("MPW is supported"); 595 mps = MLX5_MPW; 596 } 597 } else { 598 DEBUG("MPW isn't supported"); 599 mps = MLX5_MPW_DISABLED; 600 } 601 if (RTE_CACHE_LINE_SIZE == 128 && 602 !(attrs_out.flags & MLX5DV_CONTEXT_FLAGS_CQE_128B_COMP)) 603 cqe_comp = 0; 604 else 605 cqe_comp = 1; 606 if (ibv_query_device_ex(attr_ctx, NULL, &device_attr)) 607 goto error; 608 INFO("%u port(s) detected", device_attr.orig_attr.phys_port_cnt); 609 610 for (i = 0; i < device_attr.orig_attr.phys_port_cnt; i++) { 611 uint32_t port = i + 1; /* ports are indexed from one */ 612 uint32_t test = (1 << i); 613 struct ibv_context *ctx = NULL; 614 struct ibv_port_attr port_attr; 615 struct ibv_pd *pd = NULL; 616 struct priv *priv = NULL; 617 struct rte_eth_dev *eth_dev; 618 struct ibv_device_attr_ex device_attr_ex; 619 struct ether_addr mac; 620 uint16_t num_vfs = 0; 621 struct ibv_device_attr_ex device_attr; 622 struct mlx5_dev_config config = { 623 .cqe_comp = cqe_comp, 624 .mps = mps, 625 .tunnel_en = tunnel_en, 626 .tx_vec_en = 1, 627 .rx_vec_en = 1, 628 .mpw_hdr_dseg = 0, 629 .txq_inline = MLX5_ARG_UNSET, 630 .txqs_inline = MLX5_ARG_UNSET, 631 .inline_max_packet_sz = MLX5_ARG_UNSET, 632 }; 633 634 mlx5_dev[idx].ports |= test; 635 636 if (rte_eal_process_type() == RTE_PROC_SECONDARY) { 637 /* from rte_ethdev.c */ 638 char name[RTE_ETH_NAME_MAX_LEN]; 639 640 snprintf(name, sizeof(name), "%s port %u", 641 ibv_get_device_name(ibv_dev), port); 642 eth_dev = rte_eth_dev_attach_secondary(name); 643 if (eth_dev == NULL) { 644 ERROR("can not attach rte ethdev"); 645 err = ENOMEM; 646 goto error; 647 } 648 eth_dev->device = &pci_dev->device; 649 eth_dev->dev_ops = &mlx5_dev_sec_ops; 650 priv = eth_dev->data->dev_private; 651 /* Receive command fd from primary process */ 652 err = priv_socket_connect(priv); 653 if (err < 0) { 654 err = -err; 655 goto error; 656 } 657 /* Remap UAR for Tx queues. */ 658 err = priv_tx_uar_remap(priv, err); 659 if (err < 0) { 660 err = -err; 661 goto error; 662 } 663 /* 664 * Ethdev pointer is still required as input since 665 * the primary device is not accessible from the 666 * secondary process. 667 */ 668 eth_dev->rx_pkt_burst = 669 priv_select_rx_function(priv, eth_dev); 670 eth_dev->tx_pkt_burst = 671 priv_select_tx_function(priv, eth_dev); 672 continue; 673 } 674 675 DEBUG("using port %u (%08" PRIx32 ")", port, test); 676 677 ctx = ibv_open_device(ibv_dev); 678 if (ctx == NULL) { 679 err = ENODEV; 680 goto port_error; 681 } 682 683 ibv_query_device_ex(ctx, NULL, &device_attr); 684 /* Check port status. */ 685 err = ibv_query_port(ctx, port, &port_attr); 686 if (err) { 687 ERROR("port query failed: %s", strerror(err)); 688 goto port_error; 689 } 690 691 if (port_attr.link_layer != IBV_LINK_LAYER_ETHERNET) { 692 ERROR("port %d is not configured in Ethernet mode", 693 port); 694 err = EINVAL; 695 goto port_error; 696 } 697 698 if (port_attr.state != IBV_PORT_ACTIVE) 699 DEBUG("port %d is not active: \"%s\" (%d)", 700 port, ibv_port_state_str(port_attr.state), 701 port_attr.state); 702 703 /* Allocate protection domain. */ 704 pd = ibv_alloc_pd(ctx); 705 if (pd == NULL) { 706 ERROR("PD allocation failure"); 707 err = ENOMEM; 708 goto port_error; 709 } 710 711 mlx5_dev[idx].ports |= test; 712 713 /* from rte_ethdev.c */ 714 priv = rte_zmalloc("ethdev private structure", 715 sizeof(*priv), 716 RTE_CACHE_LINE_SIZE); 717 if (priv == NULL) { 718 ERROR("priv allocation failure"); 719 err = ENOMEM; 720 goto port_error; 721 } 722 723 priv->ctx = ctx; 724 strncpy(priv->ibdev_path, priv->ctx->device->ibdev_path, 725 sizeof(priv->ibdev_path)); 726 priv->device_attr = device_attr; 727 priv->port = port; 728 priv->pd = pd; 729 priv->mtu = ETHER_MTU; 730 err = mlx5_args(&config, pci_dev->device.devargs); 731 if (err) { 732 ERROR("failed to process device arguments: %s", 733 strerror(err)); 734 goto port_error; 735 } 736 if (ibv_query_device_ex(ctx, NULL, &device_attr_ex)) { 737 ERROR("ibv_query_device_ex() failed"); 738 goto port_error; 739 } 740 741 config.hw_csum = !!(device_attr_ex.device_cap_flags_ex & 742 IBV_DEVICE_RAW_IP_CSUM); 743 DEBUG("checksum offloading is %ssupported", 744 (config.hw_csum ? "" : "not ")); 745 746 #ifdef HAVE_IBV_DEVICE_VXLAN_SUPPORT 747 config.hw_csum_l2tun = 748 !!(exp_device_attr.exp_device_cap_flags & 749 IBV_DEVICE_VXLAN_SUPPORT); 750 #endif 751 DEBUG("Rx L2 tunnel checksum offloads are %ssupported", 752 (config.hw_csum_l2tun ? "" : "not ")); 753 754 #ifdef HAVE_IBV_DEVICE_COUNTERS_SET_SUPPORT 755 config.flow_counter_en = !!(device_attr.max_counter_sets); 756 ibv_describe_counter_set(ctx, 0, &cs_desc); 757 DEBUG("counter type = %d, num of cs = %ld, attributes = %d", 758 cs_desc.counter_type, cs_desc.num_of_cs, 759 cs_desc.attributes); 760 #endif 761 config.ind_table_max_size = 762 device_attr_ex.rss_caps.max_rwq_indirection_table_size; 763 /* Remove this check once DPDK supports larger/variable 764 * indirection tables. */ 765 if (config.ind_table_max_size > 766 (unsigned int)ETH_RSS_RETA_SIZE_512) 767 config.ind_table_max_size = ETH_RSS_RETA_SIZE_512; 768 DEBUG("maximum RX indirection table size is %u", 769 config.ind_table_max_size); 770 config.hw_vlan_strip = !!(device_attr_ex.raw_packet_caps & 771 IBV_RAW_PACKET_CAP_CVLAN_STRIPPING); 772 DEBUG("VLAN stripping is %ssupported", 773 (config.hw_vlan_strip ? "" : "not ")); 774 775 config.hw_fcs_strip = 776 !!(device_attr_ex.orig_attr.device_cap_flags & 777 IBV_WQ_FLAGS_SCATTER_FCS); 778 DEBUG("FCS stripping configuration is %ssupported", 779 (config.hw_fcs_strip ? "" : "not ")); 780 781 #ifdef HAVE_IBV_WQ_FLAG_RX_END_PADDING 782 config.hw_padding = !!device_attr_ex.rx_pad_end_addr_align; 783 #endif 784 DEBUG("hardware RX end alignment padding is %ssupported", 785 (config.hw_padding ? "" : "not ")); 786 787 priv_get_num_vfs(priv, &num_vfs); 788 config.sriov = (num_vfs || sriov); 789 config.tso = ((device_attr_ex.tso_caps.max_tso > 0) && 790 (device_attr_ex.tso_caps.supported_qpts & 791 (1 << IBV_QPT_RAW_PACKET))); 792 if (config.tso) 793 config.tso_max_payload_sz = 794 device_attr_ex.tso_caps.max_tso; 795 if (config.mps && !mps) { 796 ERROR("multi-packet send not supported on this device" 797 " (" MLX5_TXQ_MPW_EN ")"); 798 err = ENOTSUP; 799 goto port_error; 800 } 801 INFO("%sMPS is %s", 802 config.mps == MLX5_MPW_ENHANCED ? "Enhanced " : "", 803 config.mps != MLX5_MPW_DISABLED ? "enabled" : "disabled"); 804 if (config.cqe_comp && !cqe_comp) { 805 WARN("Rx CQE compression isn't supported"); 806 config.cqe_comp = 0; 807 } 808 /* Configure the first MAC address by default. */ 809 if (priv_get_mac(priv, &mac.addr_bytes)) { 810 ERROR("cannot get MAC address, is mlx5_en loaded?" 811 " (errno: %s)", strerror(errno)); 812 err = ENODEV; 813 goto port_error; 814 } 815 INFO("port %u MAC address is %02x:%02x:%02x:%02x:%02x:%02x", 816 priv->port, 817 mac.addr_bytes[0], mac.addr_bytes[1], 818 mac.addr_bytes[2], mac.addr_bytes[3], 819 mac.addr_bytes[4], mac.addr_bytes[5]); 820 #ifndef NDEBUG 821 { 822 char ifname[IF_NAMESIZE]; 823 824 if (priv_get_ifname(priv, &ifname) == 0) 825 DEBUG("port %u ifname is \"%s\"", 826 priv->port, ifname); 827 else 828 DEBUG("port %u ifname is unknown", priv->port); 829 } 830 #endif 831 /* Get actual MTU if possible. */ 832 priv_get_mtu(priv, &priv->mtu); 833 DEBUG("port %u MTU is %u", priv->port, priv->mtu); 834 835 /* from rte_ethdev.c */ 836 { 837 char name[RTE_ETH_NAME_MAX_LEN]; 838 839 snprintf(name, sizeof(name), "%s port %u", 840 ibv_get_device_name(ibv_dev), port); 841 eth_dev = rte_eth_dev_allocate(name); 842 } 843 if (eth_dev == NULL) { 844 ERROR("can not allocate rte ethdev"); 845 err = ENOMEM; 846 goto port_error; 847 } 848 eth_dev->data->dev_private = priv; 849 eth_dev->data->mac_addrs = priv->mac; 850 eth_dev->device = &pci_dev->device; 851 rte_eth_copy_pci_info(eth_dev, pci_dev); 852 eth_dev->device->driver = &mlx5_driver.driver; 853 priv->dev = eth_dev; 854 eth_dev->dev_ops = &mlx5_dev_ops; 855 /* Register MAC address. */ 856 claim_zero(mlx5_mac_addr_add(eth_dev, &mac, 0, 0)); 857 TAILQ_INIT(&priv->flows); 858 TAILQ_INIT(&priv->ctrl_flows); 859 860 /* Hint libmlx5 to use PMD allocator for data plane resources */ 861 struct mlx5dv_ctx_allocators alctr = { 862 .alloc = &mlx5_alloc_verbs_buf, 863 .free = &mlx5_free_verbs_buf, 864 .data = priv, 865 }; 866 mlx5dv_set_context_attr(ctx, MLX5DV_CTX_ATTR_BUF_ALLOCATORS, 867 (void *)((uintptr_t)&alctr)); 868 869 /* Bring Ethernet device up. */ 870 DEBUG("forcing Ethernet interface up"); 871 priv_set_flags(priv, ~IFF_UP, IFF_UP); 872 mlx5_link_update(priv->dev, 1); 873 /* Store device configuration on private structure. */ 874 priv->config = config; 875 continue; 876 877 port_error: 878 if (priv) 879 rte_free(priv); 880 if (pd) 881 claim_zero(ibv_dealloc_pd(pd)); 882 if (ctx) 883 claim_zero(ibv_close_device(ctx)); 884 break; 885 } 886 887 /* 888 * XXX if something went wrong in the loop above, there is a resource 889 * leak (ctx, pd, priv, dpdk ethdev) but we can do nothing about it as 890 * long as the dpdk does not provide a way to deallocate a ethdev and a 891 * way to enumerate the registered ethdevs to free the previous ones. 892 */ 893 894 /* no port found, complain */ 895 if (!mlx5_dev[idx].ports) { 896 err = ENODEV; 897 goto error; 898 } 899 900 error: 901 if (attr_ctx) 902 claim_zero(ibv_close_device(attr_ctx)); 903 if (list) 904 ibv_free_device_list(list); 905 assert(err >= 0); 906 return -err; 907 } 908 909 static const struct rte_pci_id mlx5_pci_id_map[] = { 910 { 911 RTE_PCI_DEVICE(PCI_VENDOR_ID_MELLANOX, 912 PCI_DEVICE_ID_MELLANOX_CONNECTX4) 913 }, 914 { 915 RTE_PCI_DEVICE(PCI_VENDOR_ID_MELLANOX, 916 PCI_DEVICE_ID_MELLANOX_CONNECTX4VF) 917 }, 918 { 919 RTE_PCI_DEVICE(PCI_VENDOR_ID_MELLANOX, 920 PCI_DEVICE_ID_MELLANOX_CONNECTX4LX) 921 }, 922 { 923 RTE_PCI_DEVICE(PCI_VENDOR_ID_MELLANOX, 924 PCI_DEVICE_ID_MELLANOX_CONNECTX4LXVF) 925 }, 926 { 927 RTE_PCI_DEVICE(PCI_VENDOR_ID_MELLANOX, 928 PCI_DEVICE_ID_MELLANOX_CONNECTX5) 929 }, 930 { 931 RTE_PCI_DEVICE(PCI_VENDOR_ID_MELLANOX, 932 PCI_DEVICE_ID_MELLANOX_CONNECTX5VF) 933 }, 934 { 935 RTE_PCI_DEVICE(PCI_VENDOR_ID_MELLANOX, 936 PCI_DEVICE_ID_MELLANOX_CONNECTX5EX) 937 }, 938 { 939 RTE_PCI_DEVICE(PCI_VENDOR_ID_MELLANOX, 940 PCI_DEVICE_ID_MELLANOX_CONNECTX5EXVF) 941 }, 942 { 943 .vendor_id = 0 944 } 945 }; 946 947 static struct rte_pci_driver mlx5_driver = { 948 .driver = { 949 .name = MLX5_DRIVER_NAME 950 }, 951 .id_table = mlx5_pci_id_map, 952 .probe = mlx5_pci_probe, 953 .drv_flags = RTE_PCI_DRV_INTR_LSC | RTE_PCI_DRV_INTR_RMV, 954 }; 955 956 /** 957 * Driver initialization routine. 958 */ 959 RTE_INIT(rte_mlx5_pmd_init); 960 static void 961 rte_mlx5_pmd_init(void) 962 { 963 /* Build the static table for ptype conversion. */ 964 mlx5_set_ptype_table(); 965 /* 966 * RDMAV_HUGEPAGES_SAFE tells ibv_fork_init() we intend to use 967 * huge pages. Calling ibv_fork_init() during init allows 968 * applications to use fork() safely for purposes other than 969 * using this PMD, which is not supported in forked processes. 970 */ 971 setenv("RDMAV_HUGEPAGES_SAFE", "1", 1); 972 /* Match the size of Rx completion entry to the size of a cacheline. */ 973 if (RTE_CACHE_LINE_SIZE == 128) 974 setenv("MLX5_CQE_SIZE", "128", 0); 975 ibv_fork_init(); 976 rte_pci_register(&mlx5_driver); 977 } 978 979 RTE_PMD_EXPORT_NAME(net_mlx5, __COUNTER__); 980 RTE_PMD_REGISTER_PCI_TABLE(net_mlx5, mlx5_pci_id_map); 981 RTE_PMD_REGISTER_KMOD_DEP(net_mlx5, "* ib_uverbs & mlx5_core & mlx5_ib"); 982