1 /* SPDX-License-Identifier: BSD-3-Clause 2 * Copyright 2015 6WIND S.A. 3 * Copyright 2015 Mellanox Technologies, Ltd 4 */ 5 6 #include <stddef.h> 7 #include <unistd.h> 8 #include <string.h> 9 #include <assert.h> 10 #include <dlfcn.h> 11 #include <stdint.h> 12 #include <stdlib.h> 13 #include <errno.h> 14 #include <net/if.h> 15 #include <sys/mman.h> 16 #include <linux/rtnetlink.h> 17 18 /* Verbs header. */ 19 /* ISO C doesn't support unnamed structs/unions, disabling -pedantic. */ 20 #ifdef PEDANTIC 21 #pragma GCC diagnostic ignored "-Wpedantic" 22 #endif 23 #include <infiniband/verbs.h> 24 #ifdef PEDANTIC 25 #pragma GCC diagnostic error "-Wpedantic" 26 #endif 27 28 #include <rte_malloc.h> 29 #include <rte_ethdev_driver.h> 30 #include <rte_ethdev_pci.h> 31 #include <rte_pci.h> 32 #include <rte_bus_pci.h> 33 #include <rte_common.h> 34 #include <rte_config.h> 35 #include <rte_eal_memconfig.h> 36 #include <rte_kvargs.h> 37 #include <rte_rwlock.h> 38 #include <rte_spinlock.h> 39 #include <rte_string_fns.h> 40 41 #include "mlx5.h" 42 #include "mlx5_utils.h" 43 #include "mlx5_rxtx.h" 44 #include "mlx5_autoconf.h" 45 #include "mlx5_defs.h" 46 #include "mlx5_glue.h" 47 #include "mlx5_mr.h" 48 #include "mlx5_flow.h" 49 50 /* Device parameter to enable RX completion queue compression. */ 51 #define MLX5_RXQ_CQE_COMP_EN "rxq_cqe_comp_en" 52 53 /* Device parameter to enable RX completion entry padding to 128B. */ 54 #define MLX5_RXQ_CQE_PAD_EN "rxq_cqe_pad_en" 55 56 /* Device parameter to enable padding Rx packet to cacheline size. */ 57 #define MLX5_RXQ_PKT_PAD_EN "rxq_pkt_pad_en" 58 59 /* Device parameter to enable Multi-Packet Rx queue. */ 60 #define MLX5_RX_MPRQ_EN "mprq_en" 61 62 /* Device parameter to configure log 2 of the number of strides for MPRQ. */ 63 #define MLX5_RX_MPRQ_LOG_STRIDE_NUM "mprq_log_stride_num" 64 65 /* Device parameter to limit the size of memcpy'd packet for MPRQ. */ 66 #define MLX5_RX_MPRQ_MAX_MEMCPY_LEN "mprq_max_memcpy_len" 67 68 /* Device parameter to set the minimum number of Rx queues to enable MPRQ. */ 69 #define MLX5_RXQS_MIN_MPRQ "rxqs_min_mprq" 70 71 /* Device parameter to configure inline send. */ 72 #define MLX5_TXQ_INLINE "txq_inline" 73 74 /* 75 * Device parameter to configure the number of TX queues threshold for 76 * enabling inline send. 77 */ 78 #define MLX5_TXQS_MIN_INLINE "txqs_min_inline" 79 80 /* 81 * Device parameter to configure the number of TX queues threshold for 82 * enabling vectorized Tx. 83 */ 84 #define MLX5_TXQS_MAX_VEC "txqs_max_vec" 85 86 /* Device parameter to enable multi-packet send WQEs. */ 87 #define MLX5_TXQ_MPW_EN "txq_mpw_en" 88 89 /* Device parameter to include 2 dsegs in the title WQEBB. */ 90 #define MLX5_TXQ_MPW_HDR_DSEG_EN "txq_mpw_hdr_dseg_en" 91 92 /* Device parameter to limit the size of inlining packet. */ 93 #define MLX5_TXQ_MAX_INLINE_LEN "txq_max_inline_len" 94 95 /* Device parameter to enable hardware Tx vector. */ 96 #define MLX5_TX_VEC_EN "tx_vec_en" 97 98 /* Device parameter to enable hardware Rx vector. */ 99 #define MLX5_RX_VEC_EN "rx_vec_en" 100 101 /* Allow L3 VXLAN flow creation. */ 102 #define MLX5_L3_VXLAN_EN "l3_vxlan_en" 103 104 /* Activate DV E-Switch flow steering. */ 105 #define MLX5_DV_ESW_EN "dv_esw_en" 106 107 /* Activate DV flow steering. */ 108 #define MLX5_DV_FLOW_EN "dv_flow_en" 109 110 /* Activate Netlink support in VF mode. */ 111 #define MLX5_VF_NL_EN "vf_nl_en" 112 113 /* Enable extending memsegs when creating a MR. */ 114 #define MLX5_MR_EXT_MEMSEG_EN "mr_ext_memseg_en" 115 116 /* Select port representors to instantiate. */ 117 #define MLX5_REPRESENTOR "representor" 118 119 /* Device parameter to configure the maximum number of dump files per queue. */ 120 #define MLX5_MAX_DUMP_FILES_NUM "max_dump_files_num" 121 122 #ifndef HAVE_IBV_MLX5_MOD_MPW 123 #define MLX5DV_CONTEXT_FLAGS_MPW_ALLOWED (1 << 2) 124 #define MLX5DV_CONTEXT_FLAGS_ENHANCED_MPW (1 << 3) 125 #endif 126 127 #ifndef HAVE_IBV_MLX5_MOD_CQE_128B_COMP 128 #define MLX5DV_CONTEXT_FLAGS_CQE_128B_COMP (1 << 4) 129 #endif 130 131 static const char *MZ_MLX5_PMD_SHARED_DATA = "mlx5_pmd_shared_data"; 132 133 /* Shared memory between primary and secondary processes. */ 134 struct mlx5_shared_data *mlx5_shared_data; 135 136 /* Spinlock for mlx5_shared_data allocation. */ 137 static rte_spinlock_t mlx5_shared_data_lock = RTE_SPINLOCK_INITIALIZER; 138 139 /* Process local data for secondary processes. */ 140 static struct mlx5_local_data mlx5_local_data; 141 142 /** Driver-specific log messages type. */ 143 int mlx5_logtype; 144 145 /** Data associated with devices to spawn. */ 146 struct mlx5_dev_spawn_data { 147 uint32_t ifindex; /**< Network interface index. */ 148 uint32_t max_port; /**< IB device maximal port index. */ 149 uint32_t ibv_port; /**< IB device physical port index. */ 150 struct mlx5_switch_info info; /**< Switch information. */ 151 struct ibv_device *ibv_dev; /**< Associated IB device. */ 152 struct rte_eth_dev *eth_dev; /**< Associated Ethernet device. */ 153 struct rte_pci_device *pci_dev; /**< Backend PCI device. */ 154 }; 155 156 static LIST_HEAD(, mlx5_ibv_shared) mlx5_ibv_list = LIST_HEAD_INITIALIZER(); 157 static pthread_mutex_t mlx5_ibv_list_mutex = PTHREAD_MUTEX_INITIALIZER; 158 159 /** 160 * Allocate shared IB device context. If there is multiport device the 161 * master and representors will share this context, if there is single 162 * port dedicated IB device, the context will be used by only given 163 * port due to unification. 164 * 165 * Routine first searches the context for the specified IB device name, 166 * if found the shared context assumed and reference counter is incremented. 167 * If no context found the new one is created and initialized with specified 168 * IB device context and parameters. 169 * 170 * @param[in] spawn 171 * Pointer to the IB device attributes (name, port, etc). 172 * 173 * @return 174 * Pointer to mlx5_ibv_shared object on success, 175 * otherwise NULL and rte_errno is set. 176 */ 177 static struct mlx5_ibv_shared * 178 mlx5_alloc_shared_ibctx(const struct mlx5_dev_spawn_data *spawn) 179 { 180 struct mlx5_ibv_shared *sh; 181 int err = 0; 182 uint32_t i; 183 184 assert(spawn); 185 /* Secondary process should not create the shared context. */ 186 assert(rte_eal_process_type() == RTE_PROC_PRIMARY); 187 pthread_mutex_lock(&mlx5_ibv_list_mutex); 188 /* Search for IB context by device name. */ 189 LIST_FOREACH(sh, &mlx5_ibv_list, next) { 190 if (!strcmp(sh->ibdev_name, spawn->ibv_dev->name)) { 191 sh->refcnt++; 192 goto exit; 193 } 194 } 195 /* No device found, we have to create new shared context. */ 196 assert(spawn->max_port); 197 sh = rte_zmalloc("ethdev shared ib context", 198 sizeof(struct mlx5_ibv_shared) + 199 spawn->max_port * 200 sizeof(struct mlx5_ibv_shared_port), 201 RTE_CACHE_LINE_SIZE); 202 if (!sh) { 203 DRV_LOG(ERR, "shared context allocation failure"); 204 rte_errno = ENOMEM; 205 goto exit; 206 } 207 /* Try to open IB device with DV first, then usual Verbs. */ 208 errno = 0; 209 sh->ctx = mlx5_glue->dv_open_device(spawn->ibv_dev); 210 if (sh->ctx) { 211 sh->devx = 1; 212 DRV_LOG(DEBUG, "DevX is supported"); 213 } else { 214 sh->ctx = mlx5_glue->open_device(spawn->ibv_dev); 215 if (!sh->ctx) { 216 err = errno ? errno : ENODEV; 217 goto error; 218 } 219 DRV_LOG(DEBUG, "DevX is NOT supported"); 220 } 221 err = mlx5_glue->query_device_ex(sh->ctx, NULL, &sh->device_attr); 222 if (err) { 223 DRV_LOG(DEBUG, "ibv_query_device_ex() failed"); 224 goto error; 225 } 226 sh->refcnt = 1; 227 sh->max_port = spawn->max_port; 228 strncpy(sh->ibdev_name, sh->ctx->device->name, 229 sizeof(sh->ibdev_name)); 230 strncpy(sh->ibdev_path, sh->ctx->device->ibdev_path, 231 sizeof(sh->ibdev_path)); 232 sh->pci_dev = spawn->pci_dev; 233 pthread_mutex_init(&sh->intr_mutex, NULL); 234 /* 235 * Setting port_id to max unallowed value means 236 * there is no interrupt subhandler installed for 237 * the given port index i. 238 */ 239 for (i = 0; i < sh->max_port; i++) 240 sh->port[i].ih_port_id = RTE_MAX_ETHPORTS; 241 sh->pd = mlx5_glue->alloc_pd(sh->ctx); 242 if (sh->pd == NULL) { 243 DRV_LOG(ERR, "PD allocation failure"); 244 err = ENOMEM; 245 goto error; 246 } 247 /* 248 * Once the device is added to the list of memory event 249 * callback, its global MR cache table cannot be expanded 250 * on the fly because of deadlock. If it overflows, lookup 251 * should be done by searching MR list linearly, which is slow. 252 * 253 * At this point the device is not added to the memory 254 * event list yet, context is just being created. 255 */ 256 err = mlx5_mr_btree_init(&sh->mr.cache, 257 MLX5_MR_BTREE_CACHE_N * 2, 258 sh->pci_dev->device.numa_node); 259 if (err) { 260 err = rte_errno; 261 goto error; 262 } 263 LIST_INSERT_HEAD(&mlx5_ibv_list, sh, next); 264 exit: 265 pthread_mutex_unlock(&mlx5_ibv_list_mutex); 266 return sh; 267 error: 268 pthread_mutex_unlock(&mlx5_ibv_list_mutex); 269 assert(sh); 270 if (sh->pd) 271 claim_zero(mlx5_glue->dealloc_pd(sh->pd)); 272 if (sh->ctx) 273 claim_zero(mlx5_glue->close_device(sh->ctx)); 274 rte_free(sh); 275 assert(err > 0); 276 rte_errno = err; 277 return NULL; 278 } 279 280 /** 281 * Free shared IB device context. Decrement counter and if zero free 282 * all allocated resources and close handles. 283 * 284 * @param[in] sh 285 * Pointer to mlx5_ibv_shared object to free 286 */ 287 static void 288 mlx5_free_shared_ibctx(struct mlx5_ibv_shared *sh) 289 { 290 pthread_mutex_lock(&mlx5_ibv_list_mutex); 291 #ifndef NDEBUG 292 /* Check the object presence in the list. */ 293 struct mlx5_ibv_shared *lctx; 294 295 LIST_FOREACH(lctx, &mlx5_ibv_list, next) 296 if (lctx == sh) 297 break; 298 assert(lctx); 299 if (lctx != sh) { 300 DRV_LOG(ERR, "Freeing non-existing shared IB context"); 301 goto exit; 302 } 303 #endif 304 assert(sh); 305 assert(sh->refcnt); 306 /* Secondary process should not free the shared context. */ 307 assert(rte_eal_process_type() == RTE_PROC_PRIMARY); 308 if (--sh->refcnt) 309 goto exit; 310 /* Release created Memory Regions. */ 311 mlx5_mr_release(sh); 312 LIST_REMOVE(sh, next); 313 /* 314 * Ensure there is no async event handler installed. 315 * Only primary process handles async device events. 316 **/ 317 assert(!sh->intr_cnt); 318 if (sh->intr_cnt) 319 mlx5_intr_callback_unregister 320 (&sh->intr_handle, mlx5_dev_interrupt_handler, sh); 321 pthread_mutex_destroy(&sh->intr_mutex); 322 if (sh->pd) 323 claim_zero(mlx5_glue->dealloc_pd(sh->pd)); 324 if (sh->ctx) 325 claim_zero(mlx5_glue->close_device(sh->ctx)); 326 rte_free(sh); 327 exit: 328 pthread_mutex_unlock(&mlx5_ibv_list_mutex); 329 } 330 331 /** 332 * Initialize DR related data within private structure. 333 * Routine checks the reference counter and does actual 334 * resources creation/initialization only if counter is zero. 335 * 336 * @param[in] priv 337 * Pointer to the private device data structure. 338 * 339 * @return 340 * Zero on success, positive error code otherwise. 341 */ 342 static int 343 mlx5_alloc_shared_dr(struct mlx5_priv *priv) 344 { 345 #ifdef HAVE_MLX5DV_DR 346 struct mlx5_ibv_shared *sh = priv->sh; 347 int err = 0; 348 void *domain; 349 350 assert(sh); 351 if (sh->dv_refcnt) { 352 /* Shared DV/DR structures is already initialized. */ 353 sh->dv_refcnt++; 354 priv->dr_shared = 1; 355 return 0; 356 } 357 /* Reference counter is zero, we should initialize structures. */ 358 domain = mlx5_glue->dr_create_domain(sh->ctx, 359 MLX5DV_DR_DOMAIN_TYPE_NIC_RX); 360 if (!domain) { 361 DRV_LOG(ERR, "ingress mlx5dv_dr_create_domain failed"); 362 err = errno; 363 goto error; 364 } 365 sh->rx_domain = domain; 366 domain = mlx5_glue->dr_create_domain(sh->ctx, 367 MLX5DV_DR_DOMAIN_TYPE_NIC_TX); 368 if (!domain) { 369 DRV_LOG(ERR, "egress mlx5dv_dr_create_domain failed"); 370 err = errno; 371 goto error; 372 } 373 pthread_mutex_init(&sh->dv_mutex, NULL); 374 sh->tx_domain = domain; 375 #ifdef HAVE_MLX5DV_DR_ESWITCH 376 if (priv->config.dv_esw_en) { 377 domain = mlx5_glue->dr_create_domain 378 (sh->ctx, MLX5DV_DR_DOMAIN_TYPE_FDB); 379 if (!domain) { 380 DRV_LOG(ERR, "FDB mlx5dv_dr_create_domain failed"); 381 err = errno; 382 goto error; 383 } 384 sh->fdb_domain = domain; 385 sh->esw_drop_action = mlx5_glue->dr_create_flow_action_drop(); 386 } 387 #endif 388 sh->dv_refcnt++; 389 priv->dr_shared = 1; 390 return 0; 391 392 error: 393 /* Rollback the created objects. */ 394 if (sh->rx_domain) { 395 mlx5_glue->dr_destroy_domain(sh->rx_domain); 396 sh->rx_domain = NULL; 397 } 398 if (sh->tx_domain) { 399 mlx5_glue->dr_destroy_domain(sh->tx_domain); 400 sh->tx_domain = NULL; 401 } 402 if (sh->fdb_domain) { 403 mlx5_glue->dr_destroy_domain(sh->fdb_domain); 404 sh->fdb_domain = NULL; 405 } 406 if (sh->esw_drop_action) { 407 mlx5_glue->destroy_flow_action(sh->esw_drop_action); 408 sh->esw_drop_action = NULL; 409 } 410 return err; 411 #else 412 (void)priv; 413 return 0; 414 #endif 415 } 416 417 /** 418 * Destroy DR related data within private structure. 419 * 420 * @param[in] priv 421 * Pointer to the private device data structure. 422 */ 423 static void 424 mlx5_free_shared_dr(struct mlx5_priv *priv) 425 { 426 #ifdef HAVE_MLX5DV_DR 427 struct mlx5_ibv_shared *sh; 428 429 if (!priv->dr_shared) 430 return; 431 priv->dr_shared = 0; 432 sh = priv->sh; 433 assert(sh); 434 assert(sh->dv_refcnt); 435 if (sh->dv_refcnt && --sh->dv_refcnt) 436 return; 437 if (sh->rx_domain) { 438 mlx5_glue->dr_destroy_domain(sh->rx_domain); 439 sh->rx_domain = NULL; 440 } 441 if (sh->tx_domain) { 442 mlx5_glue->dr_destroy_domain(sh->tx_domain); 443 sh->tx_domain = NULL; 444 } 445 #ifdef HAVE_MLX5DV_DR_ESWITCH 446 if (sh->fdb_domain) { 447 mlx5_glue->dr_destroy_domain(sh->fdb_domain); 448 sh->fdb_domain = NULL; 449 } 450 if (sh->esw_drop_action) { 451 mlx5_glue->destroy_flow_action(sh->esw_drop_action); 452 sh->esw_drop_action = NULL; 453 } 454 #endif 455 pthread_mutex_destroy(&sh->dv_mutex); 456 #else 457 (void)priv; 458 #endif 459 } 460 461 /** 462 * Initialize shared data between primary and secondary process. 463 * 464 * A memzone is reserved by primary process and secondary processes attach to 465 * the memzone. 466 * 467 * @return 468 * 0 on success, a negative errno value otherwise and rte_errno is set. 469 */ 470 static int 471 mlx5_init_shared_data(void) 472 { 473 const struct rte_memzone *mz; 474 int ret = 0; 475 476 rte_spinlock_lock(&mlx5_shared_data_lock); 477 if (mlx5_shared_data == NULL) { 478 if (rte_eal_process_type() == RTE_PROC_PRIMARY) { 479 /* Allocate shared memory. */ 480 mz = rte_memzone_reserve(MZ_MLX5_PMD_SHARED_DATA, 481 sizeof(*mlx5_shared_data), 482 SOCKET_ID_ANY, 0); 483 if (mz == NULL) { 484 DRV_LOG(ERR, 485 "Cannot allocate mlx5 shared data\n"); 486 ret = -rte_errno; 487 goto error; 488 } 489 mlx5_shared_data = mz->addr; 490 memset(mlx5_shared_data, 0, sizeof(*mlx5_shared_data)); 491 rte_spinlock_init(&mlx5_shared_data->lock); 492 } else { 493 /* Lookup allocated shared memory. */ 494 mz = rte_memzone_lookup(MZ_MLX5_PMD_SHARED_DATA); 495 if (mz == NULL) { 496 DRV_LOG(ERR, 497 "Cannot attach mlx5 shared data\n"); 498 ret = -rte_errno; 499 goto error; 500 } 501 mlx5_shared_data = mz->addr; 502 memset(&mlx5_local_data, 0, sizeof(mlx5_local_data)); 503 } 504 } 505 error: 506 rte_spinlock_unlock(&mlx5_shared_data_lock); 507 return ret; 508 } 509 510 /** 511 * Retrieve integer value from environment variable. 512 * 513 * @param[in] name 514 * Environment variable name. 515 * 516 * @return 517 * Integer value, 0 if the variable is not set. 518 */ 519 int 520 mlx5_getenv_int(const char *name) 521 { 522 const char *val = getenv(name); 523 524 if (val == NULL) 525 return 0; 526 return atoi(val); 527 } 528 529 /** 530 * Verbs callback to allocate a memory. This function should allocate the space 531 * according to the size provided residing inside a huge page. 532 * Please note that all allocation must respect the alignment from libmlx5 533 * (i.e. currently sysconf(_SC_PAGESIZE)). 534 * 535 * @param[in] size 536 * The size in bytes of the memory to allocate. 537 * @param[in] data 538 * A pointer to the callback data. 539 * 540 * @return 541 * Allocated buffer, NULL otherwise and rte_errno is set. 542 */ 543 static void * 544 mlx5_alloc_verbs_buf(size_t size, void *data) 545 { 546 struct mlx5_priv *priv = data; 547 void *ret; 548 size_t alignment = sysconf(_SC_PAGESIZE); 549 unsigned int socket = SOCKET_ID_ANY; 550 551 if (priv->verbs_alloc_ctx.type == MLX5_VERBS_ALLOC_TYPE_TX_QUEUE) { 552 const struct mlx5_txq_ctrl *ctrl = priv->verbs_alloc_ctx.obj; 553 554 socket = ctrl->socket; 555 } else if (priv->verbs_alloc_ctx.type == 556 MLX5_VERBS_ALLOC_TYPE_RX_QUEUE) { 557 const struct mlx5_rxq_ctrl *ctrl = priv->verbs_alloc_ctx.obj; 558 559 socket = ctrl->socket; 560 } 561 assert(data != NULL); 562 ret = rte_malloc_socket(__func__, size, alignment, socket); 563 if (!ret && size) 564 rte_errno = ENOMEM; 565 return ret; 566 } 567 568 /** 569 * Verbs callback to free a memory. 570 * 571 * @param[in] ptr 572 * A pointer to the memory to free. 573 * @param[in] data 574 * A pointer to the callback data. 575 */ 576 static void 577 mlx5_free_verbs_buf(void *ptr, void *data __rte_unused) 578 { 579 assert(data != NULL); 580 rte_free(ptr); 581 } 582 583 /** 584 * Initialize process private data structure. 585 * 586 * @param dev 587 * Pointer to Ethernet device structure. 588 * 589 * @return 590 * 0 on success, a negative errno value otherwise and rte_errno is set. 591 */ 592 int 593 mlx5_proc_priv_init(struct rte_eth_dev *dev) 594 { 595 struct mlx5_priv *priv = dev->data->dev_private; 596 struct mlx5_proc_priv *ppriv; 597 size_t ppriv_size; 598 599 /* 600 * UAR register table follows the process private structure. BlueFlame 601 * registers for Tx queues are stored in the table. 602 */ 603 ppriv_size = 604 sizeof(struct mlx5_proc_priv) + priv->txqs_n * sizeof(void *); 605 ppriv = rte_malloc_socket("mlx5_proc_priv", ppriv_size, 606 RTE_CACHE_LINE_SIZE, dev->device->numa_node); 607 if (!ppriv) { 608 rte_errno = ENOMEM; 609 return -rte_errno; 610 } 611 ppriv->uar_table_sz = ppriv_size; 612 dev->process_private = ppriv; 613 return 0; 614 } 615 616 /** 617 * Un-initialize process private data structure. 618 * 619 * @param dev 620 * Pointer to Ethernet device structure. 621 */ 622 static void 623 mlx5_proc_priv_uninit(struct rte_eth_dev *dev) 624 { 625 if (!dev->process_private) 626 return; 627 rte_free(dev->process_private); 628 dev->process_private = NULL; 629 } 630 631 /** 632 * DPDK callback to close the device. 633 * 634 * Destroy all queues and objects, free memory. 635 * 636 * @param dev 637 * Pointer to Ethernet device structure. 638 */ 639 static void 640 mlx5_dev_close(struct rte_eth_dev *dev) 641 { 642 struct mlx5_priv *priv = dev->data->dev_private; 643 unsigned int i; 644 int ret; 645 646 DRV_LOG(DEBUG, "port %u closing device \"%s\"", 647 dev->data->port_id, 648 ((priv->sh->ctx != NULL) ? priv->sh->ctx->device->name : "")); 649 /* In case mlx5_dev_stop() has not been called. */ 650 mlx5_dev_interrupt_handler_uninstall(dev); 651 mlx5_traffic_disable(dev); 652 mlx5_flow_flush(dev, NULL); 653 /* Prevent crashes when queues are still in use. */ 654 dev->rx_pkt_burst = removed_rx_burst; 655 dev->tx_pkt_burst = removed_tx_burst; 656 rte_wmb(); 657 /* Disable datapath on secondary process. */ 658 mlx5_mp_req_stop_rxtx(dev); 659 if (priv->rxqs != NULL) { 660 /* XXX race condition if mlx5_rx_burst() is still running. */ 661 usleep(1000); 662 for (i = 0; (i != priv->rxqs_n); ++i) 663 mlx5_rxq_release(dev, i); 664 priv->rxqs_n = 0; 665 priv->rxqs = NULL; 666 } 667 if (priv->txqs != NULL) { 668 /* XXX race condition if mlx5_tx_burst() is still running. */ 669 usleep(1000); 670 for (i = 0; (i != priv->txqs_n); ++i) 671 mlx5_txq_release(dev, i); 672 priv->txqs_n = 0; 673 priv->txqs = NULL; 674 } 675 mlx5_proc_priv_uninit(dev); 676 mlx5_mprq_free_mp(dev); 677 /* Remove from memory callback device list. */ 678 rte_rwlock_write_lock(&mlx5_shared_data->mem_event_rwlock); 679 assert(priv->sh); 680 LIST_REMOVE(priv->sh, mem_event_cb); 681 rte_rwlock_write_unlock(&mlx5_shared_data->mem_event_rwlock); 682 mlx5_free_shared_dr(priv); 683 if (priv->rss_conf.rss_key != NULL) 684 rte_free(priv->rss_conf.rss_key); 685 if (priv->reta_idx != NULL) 686 rte_free(priv->reta_idx); 687 if (priv->config.vf) 688 mlx5_nl_mac_addr_flush(dev); 689 if (priv->nl_socket_route >= 0) 690 close(priv->nl_socket_route); 691 if (priv->nl_socket_rdma >= 0) 692 close(priv->nl_socket_rdma); 693 if (priv->sh) { 694 /* 695 * Free the shared context in last turn, because the cleanup 696 * routines above may use some shared fields, like 697 * mlx5_nl_mac_addr_flush() uses ibdev_path for retrieveing 698 * ifindex if Netlink fails. 699 */ 700 mlx5_free_shared_ibctx(priv->sh); 701 priv->sh = NULL; 702 } 703 ret = mlx5_hrxq_ibv_verify(dev); 704 if (ret) 705 DRV_LOG(WARNING, "port %u some hash Rx queue still remain", 706 dev->data->port_id); 707 ret = mlx5_ind_table_ibv_verify(dev); 708 if (ret) 709 DRV_LOG(WARNING, "port %u some indirection table still remain", 710 dev->data->port_id); 711 ret = mlx5_rxq_ibv_verify(dev); 712 if (ret) 713 DRV_LOG(WARNING, "port %u some Verbs Rx queue still remain", 714 dev->data->port_id); 715 ret = mlx5_rxq_verify(dev); 716 if (ret) 717 DRV_LOG(WARNING, "port %u some Rx queues still remain", 718 dev->data->port_id); 719 ret = mlx5_txq_ibv_verify(dev); 720 if (ret) 721 DRV_LOG(WARNING, "port %u some Verbs Tx queue still remain", 722 dev->data->port_id); 723 ret = mlx5_txq_verify(dev); 724 if (ret) 725 DRV_LOG(WARNING, "port %u some Tx queues still remain", 726 dev->data->port_id); 727 ret = mlx5_flow_verify(dev); 728 if (ret) 729 DRV_LOG(WARNING, "port %u some flows still remain", 730 dev->data->port_id); 731 if (priv->domain_id != RTE_ETH_DEV_SWITCH_DOMAIN_ID_INVALID) { 732 unsigned int c = 0; 733 uint16_t port_id; 734 735 RTE_ETH_FOREACH_DEV_OF(port_id, dev->device) { 736 struct mlx5_priv *opriv = 737 rte_eth_devices[port_id].data->dev_private; 738 739 if (!opriv || 740 opriv->domain_id != priv->domain_id || 741 &rte_eth_devices[port_id] == dev) 742 continue; 743 ++c; 744 } 745 if (!c) 746 claim_zero(rte_eth_switch_domain_free(priv->domain_id)); 747 } 748 memset(priv, 0, sizeof(*priv)); 749 priv->domain_id = RTE_ETH_DEV_SWITCH_DOMAIN_ID_INVALID; 750 /* 751 * Reset mac_addrs to NULL such that it is not freed as part of 752 * rte_eth_dev_release_port(). mac_addrs is part of dev_private so 753 * it is freed when dev_private is freed. 754 */ 755 dev->data->mac_addrs = NULL; 756 } 757 758 const struct eth_dev_ops mlx5_dev_ops = { 759 .dev_configure = mlx5_dev_configure, 760 .dev_start = mlx5_dev_start, 761 .dev_stop = mlx5_dev_stop, 762 .dev_set_link_down = mlx5_set_link_down, 763 .dev_set_link_up = mlx5_set_link_up, 764 .dev_close = mlx5_dev_close, 765 .promiscuous_enable = mlx5_promiscuous_enable, 766 .promiscuous_disable = mlx5_promiscuous_disable, 767 .allmulticast_enable = mlx5_allmulticast_enable, 768 .allmulticast_disable = mlx5_allmulticast_disable, 769 .link_update = mlx5_link_update, 770 .stats_get = mlx5_stats_get, 771 .stats_reset = mlx5_stats_reset, 772 .xstats_get = mlx5_xstats_get, 773 .xstats_reset = mlx5_xstats_reset, 774 .xstats_get_names = mlx5_xstats_get_names, 775 .fw_version_get = mlx5_fw_version_get, 776 .dev_infos_get = mlx5_dev_infos_get, 777 .read_clock = mlx5_read_clock, 778 .dev_supported_ptypes_get = mlx5_dev_supported_ptypes_get, 779 .vlan_filter_set = mlx5_vlan_filter_set, 780 .rx_queue_setup = mlx5_rx_queue_setup, 781 .tx_queue_setup = mlx5_tx_queue_setup, 782 .rx_queue_release = mlx5_rx_queue_release, 783 .tx_queue_release = mlx5_tx_queue_release, 784 .flow_ctrl_get = mlx5_dev_get_flow_ctrl, 785 .flow_ctrl_set = mlx5_dev_set_flow_ctrl, 786 .mac_addr_remove = mlx5_mac_addr_remove, 787 .mac_addr_add = mlx5_mac_addr_add, 788 .mac_addr_set = mlx5_mac_addr_set, 789 .set_mc_addr_list = mlx5_set_mc_addr_list, 790 .mtu_set = mlx5_dev_set_mtu, 791 .vlan_strip_queue_set = mlx5_vlan_strip_queue_set, 792 .vlan_offload_set = mlx5_vlan_offload_set, 793 .reta_update = mlx5_dev_rss_reta_update, 794 .reta_query = mlx5_dev_rss_reta_query, 795 .rss_hash_update = mlx5_rss_hash_update, 796 .rss_hash_conf_get = mlx5_rss_hash_conf_get, 797 .filter_ctrl = mlx5_dev_filter_ctrl, 798 .rx_descriptor_status = mlx5_rx_descriptor_status, 799 .tx_descriptor_status = mlx5_tx_descriptor_status, 800 .rx_queue_count = mlx5_rx_queue_count, 801 .rx_queue_intr_enable = mlx5_rx_intr_enable, 802 .rx_queue_intr_disable = mlx5_rx_intr_disable, 803 .is_removed = mlx5_is_removed, 804 }; 805 806 /* Available operations from secondary process. */ 807 static const struct eth_dev_ops mlx5_dev_sec_ops = { 808 .stats_get = mlx5_stats_get, 809 .stats_reset = mlx5_stats_reset, 810 .xstats_get = mlx5_xstats_get, 811 .xstats_reset = mlx5_xstats_reset, 812 .xstats_get_names = mlx5_xstats_get_names, 813 .fw_version_get = mlx5_fw_version_get, 814 .dev_infos_get = mlx5_dev_infos_get, 815 .rx_descriptor_status = mlx5_rx_descriptor_status, 816 .tx_descriptor_status = mlx5_tx_descriptor_status, 817 }; 818 819 /* Available operations in flow isolated mode. */ 820 const struct eth_dev_ops mlx5_dev_ops_isolate = { 821 .dev_configure = mlx5_dev_configure, 822 .dev_start = mlx5_dev_start, 823 .dev_stop = mlx5_dev_stop, 824 .dev_set_link_down = mlx5_set_link_down, 825 .dev_set_link_up = mlx5_set_link_up, 826 .dev_close = mlx5_dev_close, 827 .promiscuous_enable = mlx5_promiscuous_enable, 828 .promiscuous_disable = mlx5_promiscuous_disable, 829 .allmulticast_enable = mlx5_allmulticast_enable, 830 .allmulticast_disable = mlx5_allmulticast_disable, 831 .link_update = mlx5_link_update, 832 .stats_get = mlx5_stats_get, 833 .stats_reset = mlx5_stats_reset, 834 .xstats_get = mlx5_xstats_get, 835 .xstats_reset = mlx5_xstats_reset, 836 .xstats_get_names = mlx5_xstats_get_names, 837 .fw_version_get = mlx5_fw_version_get, 838 .dev_infos_get = mlx5_dev_infos_get, 839 .dev_supported_ptypes_get = mlx5_dev_supported_ptypes_get, 840 .vlan_filter_set = mlx5_vlan_filter_set, 841 .rx_queue_setup = mlx5_rx_queue_setup, 842 .tx_queue_setup = mlx5_tx_queue_setup, 843 .rx_queue_release = mlx5_rx_queue_release, 844 .tx_queue_release = mlx5_tx_queue_release, 845 .flow_ctrl_get = mlx5_dev_get_flow_ctrl, 846 .flow_ctrl_set = mlx5_dev_set_flow_ctrl, 847 .mac_addr_remove = mlx5_mac_addr_remove, 848 .mac_addr_add = mlx5_mac_addr_add, 849 .mac_addr_set = mlx5_mac_addr_set, 850 .set_mc_addr_list = mlx5_set_mc_addr_list, 851 .mtu_set = mlx5_dev_set_mtu, 852 .vlan_strip_queue_set = mlx5_vlan_strip_queue_set, 853 .vlan_offload_set = mlx5_vlan_offload_set, 854 .filter_ctrl = mlx5_dev_filter_ctrl, 855 .rx_descriptor_status = mlx5_rx_descriptor_status, 856 .tx_descriptor_status = mlx5_tx_descriptor_status, 857 .rx_queue_intr_enable = mlx5_rx_intr_enable, 858 .rx_queue_intr_disable = mlx5_rx_intr_disable, 859 .is_removed = mlx5_is_removed, 860 }; 861 862 /** 863 * Verify and store value for device argument. 864 * 865 * @param[in] key 866 * Key argument to verify. 867 * @param[in] val 868 * Value associated with key. 869 * @param opaque 870 * User data. 871 * 872 * @return 873 * 0 on success, a negative errno value otherwise and rte_errno is set. 874 */ 875 static int 876 mlx5_args_check(const char *key, const char *val, void *opaque) 877 { 878 struct mlx5_dev_config *config = opaque; 879 unsigned long tmp; 880 881 /* No-op, port representors are processed in mlx5_dev_spawn(). */ 882 if (!strcmp(MLX5_REPRESENTOR, key)) 883 return 0; 884 errno = 0; 885 tmp = strtoul(val, NULL, 0); 886 if (errno) { 887 rte_errno = errno; 888 DRV_LOG(WARNING, "%s: \"%s\" is not a valid integer", key, val); 889 return -rte_errno; 890 } 891 if (strcmp(MLX5_RXQ_CQE_COMP_EN, key) == 0) { 892 config->cqe_comp = !!tmp; 893 } else if (strcmp(MLX5_RXQ_CQE_PAD_EN, key) == 0) { 894 config->cqe_pad = !!tmp; 895 } else if (strcmp(MLX5_RXQ_PKT_PAD_EN, key) == 0) { 896 config->hw_padding = !!tmp; 897 } else if (strcmp(MLX5_RX_MPRQ_EN, key) == 0) { 898 config->mprq.enabled = !!tmp; 899 } else if (strcmp(MLX5_RX_MPRQ_LOG_STRIDE_NUM, key) == 0) { 900 config->mprq.stride_num_n = tmp; 901 } else if (strcmp(MLX5_RX_MPRQ_MAX_MEMCPY_LEN, key) == 0) { 902 config->mprq.max_memcpy_len = tmp; 903 } else if (strcmp(MLX5_RXQS_MIN_MPRQ, key) == 0) { 904 config->mprq.min_rxqs_num = tmp; 905 } else if (strcmp(MLX5_TXQ_INLINE, key) == 0) { 906 config->txq_inline = tmp; 907 } else if (strcmp(MLX5_TXQS_MIN_INLINE, key) == 0) { 908 config->txqs_inline = tmp; 909 } else if (strcmp(MLX5_TXQS_MAX_VEC, key) == 0) { 910 config->txqs_vec = tmp; 911 } else if (strcmp(MLX5_TXQ_MPW_EN, key) == 0) { 912 config->mps = !!tmp; 913 } else if (strcmp(MLX5_TXQ_MPW_HDR_DSEG_EN, key) == 0) { 914 config->mpw_hdr_dseg = !!tmp; 915 } else if (strcmp(MLX5_TXQ_MAX_INLINE_LEN, key) == 0) { 916 config->inline_max_packet_sz = tmp; 917 } else if (strcmp(MLX5_TX_VEC_EN, key) == 0) { 918 config->tx_vec_en = !!tmp; 919 } else if (strcmp(MLX5_RX_VEC_EN, key) == 0) { 920 config->rx_vec_en = !!tmp; 921 } else if (strcmp(MLX5_L3_VXLAN_EN, key) == 0) { 922 config->l3_vxlan_en = !!tmp; 923 } else if (strcmp(MLX5_VF_NL_EN, key) == 0) { 924 config->vf_nl_en = !!tmp; 925 } else if (strcmp(MLX5_DV_ESW_EN, key) == 0) { 926 config->dv_esw_en = !!tmp; 927 } else if (strcmp(MLX5_DV_FLOW_EN, key) == 0) { 928 config->dv_flow_en = !!tmp; 929 } else if (strcmp(MLX5_MR_EXT_MEMSEG_EN, key) == 0) { 930 config->mr_ext_memseg_en = !!tmp; 931 } else if (strcmp(MLX5_MAX_DUMP_FILES_NUM, key) == 0) { 932 config->max_dump_files_num = tmp; 933 } else { 934 DRV_LOG(WARNING, "%s: unknown parameter", key); 935 rte_errno = EINVAL; 936 return -rte_errno; 937 } 938 return 0; 939 } 940 941 /** 942 * Parse device parameters. 943 * 944 * @param config 945 * Pointer to device configuration structure. 946 * @param devargs 947 * Device arguments structure. 948 * 949 * @return 950 * 0 on success, a negative errno value otherwise and rte_errno is set. 951 */ 952 static int 953 mlx5_args(struct mlx5_dev_config *config, struct rte_devargs *devargs) 954 { 955 const char **params = (const char *[]){ 956 MLX5_RXQ_CQE_COMP_EN, 957 MLX5_RXQ_CQE_PAD_EN, 958 MLX5_RXQ_PKT_PAD_EN, 959 MLX5_RX_MPRQ_EN, 960 MLX5_RX_MPRQ_LOG_STRIDE_NUM, 961 MLX5_RX_MPRQ_MAX_MEMCPY_LEN, 962 MLX5_RXQS_MIN_MPRQ, 963 MLX5_TXQ_INLINE, 964 MLX5_TXQS_MIN_INLINE, 965 MLX5_TXQS_MAX_VEC, 966 MLX5_TXQ_MPW_EN, 967 MLX5_TXQ_MPW_HDR_DSEG_EN, 968 MLX5_TXQ_MAX_INLINE_LEN, 969 MLX5_TX_VEC_EN, 970 MLX5_RX_VEC_EN, 971 MLX5_L3_VXLAN_EN, 972 MLX5_VF_NL_EN, 973 MLX5_DV_ESW_EN, 974 MLX5_DV_FLOW_EN, 975 MLX5_MR_EXT_MEMSEG_EN, 976 MLX5_REPRESENTOR, 977 MLX5_MAX_DUMP_FILES_NUM, 978 NULL, 979 }; 980 struct rte_kvargs *kvlist; 981 int ret = 0; 982 int i; 983 984 if (devargs == NULL) 985 return 0; 986 /* Following UGLY cast is done to pass checkpatch. */ 987 kvlist = rte_kvargs_parse(devargs->args, params); 988 if (kvlist == NULL) { 989 rte_errno = EINVAL; 990 return -rte_errno; 991 } 992 /* Process parameters. */ 993 for (i = 0; (params[i] != NULL); ++i) { 994 if (rte_kvargs_count(kvlist, params[i])) { 995 ret = rte_kvargs_process(kvlist, params[i], 996 mlx5_args_check, config); 997 if (ret) { 998 rte_errno = EINVAL; 999 rte_kvargs_free(kvlist); 1000 return -rte_errno; 1001 } 1002 } 1003 } 1004 rte_kvargs_free(kvlist); 1005 return 0; 1006 } 1007 1008 static struct rte_pci_driver mlx5_driver; 1009 1010 /** 1011 * PMD global initialization. 1012 * 1013 * Independent from individual device, this function initializes global 1014 * per-PMD data structures distinguishing primary and secondary processes. 1015 * Hence, each initialization is called once per a process. 1016 * 1017 * @return 1018 * 0 on success, a negative errno value otherwise and rte_errno is set. 1019 */ 1020 static int 1021 mlx5_init_once(void) 1022 { 1023 struct mlx5_shared_data *sd; 1024 struct mlx5_local_data *ld = &mlx5_local_data; 1025 int ret = 0; 1026 1027 if (mlx5_init_shared_data()) 1028 return -rte_errno; 1029 sd = mlx5_shared_data; 1030 assert(sd); 1031 rte_spinlock_lock(&sd->lock); 1032 switch (rte_eal_process_type()) { 1033 case RTE_PROC_PRIMARY: 1034 if (sd->init_done) 1035 break; 1036 LIST_INIT(&sd->mem_event_cb_list); 1037 rte_rwlock_init(&sd->mem_event_rwlock); 1038 rte_mem_event_callback_register("MLX5_MEM_EVENT_CB", 1039 mlx5_mr_mem_event_cb, NULL); 1040 ret = mlx5_mp_init_primary(); 1041 if (ret) 1042 goto out; 1043 sd->init_done = true; 1044 break; 1045 case RTE_PROC_SECONDARY: 1046 if (ld->init_done) 1047 break; 1048 ret = mlx5_mp_init_secondary(); 1049 if (ret) 1050 goto out; 1051 ++sd->secondary_cnt; 1052 ld->init_done = true; 1053 break; 1054 default: 1055 break; 1056 } 1057 out: 1058 rte_spinlock_unlock(&sd->lock); 1059 return ret; 1060 } 1061 1062 /** 1063 * Spawn an Ethernet device from Verbs information. 1064 * 1065 * @param dpdk_dev 1066 * Backing DPDK device. 1067 * @param spawn 1068 * Verbs device parameters (name, port, switch_info) to spawn. 1069 * @param config 1070 * Device configuration parameters. 1071 * 1072 * @return 1073 * A valid Ethernet device object on success, NULL otherwise and rte_errno 1074 * is set. The following errors are defined: 1075 * 1076 * EBUSY: device is not supposed to be spawned. 1077 * EEXIST: device is already spawned 1078 */ 1079 static struct rte_eth_dev * 1080 mlx5_dev_spawn(struct rte_device *dpdk_dev, 1081 struct mlx5_dev_spawn_data *spawn, 1082 struct mlx5_dev_config config) 1083 { 1084 const struct mlx5_switch_info *switch_info = &spawn->info; 1085 struct mlx5_ibv_shared *sh = NULL; 1086 struct ibv_port_attr port_attr; 1087 struct mlx5dv_context dv_attr = { .comp_mask = 0 }; 1088 struct rte_eth_dev *eth_dev = NULL; 1089 struct mlx5_priv *priv = NULL; 1090 int err = 0; 1091 unsigned int hw_padding = 0; 1092 unsigned int mps; 1093 unsigned int cqe_comp; 1094 unsigned int cqe_pad = 0; 1095 unsigned int tunnel_en = 0; 1096 unsigned int mpls_en = 0; 1097 unsigned int swp = 0; 1098 unsigned int mprq = 0; 1099 unsigned int mprq_min_stride_size_n = 0; 1100 unsigned int mprq_max_stride_size_n = 0; 1101 unsigned int mprq_min_stride_num_n = 0; 1102 unsigned int mprq_max_stride_num_n = 0; 1103 struct rte_ether_addr mac; 1104 char name[RTE_ETH_NAME_MAX_LEN]; 1105 int own_domain_id = 0; 1106 uint16_t port_id; 1107 unsigned int i; 1108 1109 /* Determine if this port representor is supposed to be spawned. */ 1110 if (switch_info->representor && dpdk_dev->devargs) { 1111 struct rte_eth_devargs eth_da; 1112 1113 err = rte_eth_devargs_parse(dpdk_dev->devargs->args, ð_da); 1114 if (err) { 1115 rte_errno = -err; 1116 DRV_LOG(ERR, "failed to process device arguments: %s", 1117 strerror(rte_errno)); 1118 return NULL; 1119 } 1120 for (i = 0; i < eth_da.nb_representor_ports; ++i) 1121 if (eth_da.representor_ports[i] == 1122 (uint16_t)switch_info->port_name) 1123 break; 1124 if (i == eth_da.nb_representor_ports) { 1125 rte_errno = EBUSY; 1126 return NULL; 1127 } 1128 } 1129 /* Build device name. */ 1130 if (!switch_info->representor) 1131 strlcpy(name, dpdk_dev->name, sizeof(name)); 1132 else 1133 snprintf(name, sizeof(name), "%s_representor_%u", 1134 dpdk_dev->name, switch_info->port_name); 1135 /* check if the device is already spawned */ 1136 if (rte_eth_dev_get_port_by_name(name, &port_id) == 0) { 1137 rte_errno = EEXIST; 1138 return NULL; 1139 } 1140 DRV_LOG(DEBUG, "naming Ethernet device \"%s\"", name); 1141 if (rte_eal_process_type() == RTE_PROC_SECONDARY) { 1142 eth_dev = rte_eth_dev_attach_secondary(name); 1143 if (eth_dev == NULL) { 1144 DRV_LOG(ERR, "can not attach rte ethdev"); 1145 rte_errno = ENOMEM; 1146 return NULL; 1147 } 1148 eth_dev->device = dpdk_dev; 1149 eth_dev->dev_ops = &mlx5_dev_sec_ops; 1150 err = mlx5_proc_priv_init(eth_dev); 1151 if (err) 1152 return NULL; 1153 /* Receive command fd from primary process */ 1154 err = mlx5_mp_req_verbs_cmd_fd(eth_dev); 1155 if (err < 0) 1156 return NULL; 1157 /* Remap UAR for Tx queues. */ 1158 err = mlx5_tx_uar_init_secondary(eth_dev, err); 1159 if (err) 1160 return NULL; 1161 /* 1162 * Ethdev pointer is still required as input since 1163 * the primary device is not accessible from the 1164 * secondary process. 1165 */ 1166 eth_dev->rx_pkt_burst = mlx5_select_rx_function(eth_dev); 1167 eth_dev->tx_pkt_burst = mlx5_select_tx_function(eth_dev); 1168 return eth_dev; 1169 } 1170 sh = mlx5_alloc_shared_ibctx(spawn); 1171 if (!sh) 1172 return NULL; 1173 config.devx = sh->devx; 1174 #ifdef HAVE_IBV_MLX5_MOD_SWP 1175 dv_attr.comp_mask |= MLX5DV_CONTEXT_MASK_SWP; 1176 #endif 1177 /* 1178 * Multi-packet send is supported by ConnectX-4 Lx PF as well 1179 * as all ConnectX-5 devices. 1180 */ 1181 #ifdef HAVE_IBV_DEVICE_TUNNEL_SUPPORT 1182 dv_attr.comp_mask |= MLX5DV_CONTEXT_MASK_TUNNEL_OFFLOADS; 1183 #endif 1184 #ifdef HAVE_IBV_DEVICE_STRIDING_RQ_SUPPORT 1185 dv_attr.comp_mask |= MLX5DV_CONTEXT_MASK_STRIDING_RQ; 1186 #endif 1187 mlx5_glue->dv_query_device(sh->ctx, &dv_attr); 1188 if (dv_attr.flags & MLX5DV_CONTEXT_FLAGS_MPW_ALLOWED) { 1189 if (dv_attr.flags & MLX5DV_CONTEXT_FLAGS_ENHANCED_MPW) { 1190 DRV_LOG(DEBUG, "enhanced MPW is supported"); 1191 mps = MLX5_MPW_ENHANCED; 1192 } else { 1193 DRV_LOG(DEBUG, "MPW is supported"); 1194 mps = MLX5_MPW; 1195 } 1196 } else { 1197 DRV_LOG(DEBUG, "MPW isn't supported"); 1198 mps = MLX5_MPW_DISABLED; 1199 } 1200 #ifdef HAVE_IBV_MLX5_MOD_SWP 1201 if (dv_attr.comp_mask & MLX5DV_CONTEXT_MASK_SWP) 1202 swp = dv_attr.sw_parsing_caps.sw_parsing_offloads; 1203 DRV_LOG(DEBUG, "SWP support: %u", swp); 1204 #endif 1205 config.swp = !!swp; 1206 #ifdef HAVE_IBV_DEVICE_STRIDING_RQ_SUPPORT 1207 if (dv_attr.comp_mask & MLX5DV_CONTEXT_MASK_STRIDING_RQ) { 1208 struct mlx5dv_striding_rq_caps mprq_caps = 1209 dv_attr.striding_rq_caps; 1210 1211 DRV_LOG(DEBUG, "\tmin_single_stride_log_num_of_bytes: %d", 1212 mprq_caps.min_single_stride_log_num_of_bytes); 1213 DRV_LOG(DEBUG, "\tmax_single_stride_log_num_of_bytes: %d", 1214 mprq_caps.max_single_stride_log_num_of_bytes); 1215 DRV_LOG(DEBUG, "\tmin_single_wqe_log_num_of_strides: %d", 1216 mprq_caps.min_single_wqe_log_num_of_strides); 1217 DRV_LOG(DEBUG, "\tmax_single_wqe_log_num_of_strides: %d", 1218 mprq_caps.max_single_wqe_log_num_of_strides); 1219 DRV_LOG(DEBUG, "\tsupported_qpts: %d", 1220 mprq_caps.supported_qpts); 1221 DRV_LOG(DEBUG, "device supports Multi-Packet RQ"); 1222 mprq = 1; 1223 mprq_min_stride_size_n = 1224 mprq_caps.min_single_stride_log_num_of_bytes; 1225 mprq_max_stride_size_n = 1226 mprq_caps.max_single_stride_log_num_of_bytes; 1227 mprq_min_stride_num_n = 1228 mprq_caps.min_single_wqe_log_num_of_strides; 1229 mprq_max_stride_num_n = 1230 mprq_caps.max_single_wqe_log_num_of_strides; 1231 config.mprq.stride_num_n = RTE_MAX(MLX5_MPRQ_STRIDE_NUM_N, 1232 mprq_min_stride_num_n); 1233 } 1234 #endif 1235 if (RTE_CACHE_LINE_SIZE == 128 && 1236 !(dv_attr.flags & MLX5DV_CONTEXT_FLAGS_CQE_128B_COMP)) 1237 cqe_comp = 0; 1238 else 1239 cqe_comp = 1; 1240 config.cqe_comp = cqe_comp; 1241 #ifdef HAVE_IBV_MLX5_MOD_CQE_128B_PAD 1242 /* Whether device supports 128B Rx CQE padding. */ 1243 cqe_pad = RTE_CACHE_LINE_SIZE == 128 && 1244 (dv_attr.flags & MLX5DV_CONTEXT_FLAGS_CQE_128B_PAD); 1245 #endif 1246 #ifdef HAVE_IBV_DEVICE_TUNNEL_SUPPORT 1247 if (dv_attr.comp_mask & MLX5DV_CONTEXT_MASK_TUNNEL_OFFLOADS) { 1248 tunnel_en = ((dv_attr.tunnel_offloads_caps & 1249 MLX5DV_RAW_PACKET_CAP_TUNNELED_OFFLOAD_VXLAN) && 1250 (dv_attr.tunnel_offloads_caps & 1251 MLX5DV_RAW_PACKET_CAP_TUNNELED_OFFLOAD_GRE)); 1252 } 1253 DRV_LOG(DEBUG, "tunnel offloading is %ssupported", 1254 tunnel_en ? "" : "not "); 1255 #else 1256 DRV_LOG(WARNING, 1257 "tunnel offloading disabled due to old OFED/rdma-core version"); 1258 #endif 1259 config.tunnel_en = tunnel_en; 1260 #ifdef HAVE_IBV_DEVICE_MPLS_SUPPORT 1261 mpls_en = ((dv_attr.tunnel_offloads_caps & 1262 MLX5DV_RAW_PACKET_CAP_TUNNELED_OFFLOAD_CW_MPLS_OVER_GRE) && 1263 (dv_attr.tunnel_offloads_caps & 1264 MLX5DV_RAW_PACKET_CAP_TUNNELED_OFFLOAD_CW_MPLS_OVER_UDP)); 1265 DRV_LOG(DEBUG, "MPLS over GRE/UDP tunnel offloading is %ssupported", 1266 mpls_en ? "" : "not "); 1267 #else 1268 DRV_LOG(WARNING, "MPLS over GRE/UDP tunnel offloading disabled due to" 1269 " old OFED/rdma-core version or firmware configuration"); 1270 #endif 1271 config.mpls_en = mpls_en; 1272 /* Check port status. */ 1273 err = mlx5_glue->query_port(sh->ctx, spawn->ibv_port, &port_attr); 1274 if (err) { 1275 DRV_LOG(ERR, "port query failed: %s", strerror(err)); 1276 goto error; 1277 } 1278 if (port_attr.link_layer != IBV_LINK_LAYER_ETHERNET) { 1279 DRV_LOG(ERR, "port is not configured in Ethernet mode"); 1280 err = EINVAL; 1281 goto error; 1282 } 1283 if (port_attr.state != IBV_PORT_ACTIVE) 1284 DRV_LOG(DEBUG, "port is not active: \"%s\" (%d)", 1285 mlx5_glue->port_state_str(port_attr.state), 1286 port_attr.state); 1287 /* Allocate private eth device data. */ 1288 priv = rte_zmalloc("ethdev private structure", 1289 sizeof(*priv), 1290 RTE_CACHE_LINE_SIZE); 1291 if (priv == NULL) { 1292 DRV_LOG(ERR, "priv allocation failure"); 1293 err = ENOMEM; 1294 goto error; 1295 } 1296 priv->sh = sh; 1297 priv->ibv_port = spawn->ibv_port; 1298 priv->mtu = RTE_ETHER_MTU; 1299 #ifndef RTE_ARCH_64 1300 /* Initialize UAR access locks for 32bit implementations. */ 1301 rte_spinlock_init(&priv->uar_lock_cq); 1302 for (i = 0; i < MLX5_UAR_PAGE_NUM_MAX; i++) 1303 rte_spinlock_init(&priv->uar_lock[i]); 1304 #endif 1305 /* Some internal functions rely on Netlink sockets, open them now. */ 1306 priv->nl_socket_rdma = mlx5_nl_init(NETLINK_RDMA); 1307 priv->nl_socket_route = mlx5_nl_init(NETLINK_ROUTE); 1308 priv->nl_sn = 0; 1309 priv->representor = !!switch_info->representor; 1310 priv->master = !!switch_info->master; 1311 priv->domain_id = RTE_ETH_DEV_SWITCH_DOMAIN_ID_INVALID; 1312 /* 1313 * Currently we support single E-Switch per PF configurations 1314 * only and vport_id field contains the vport index for 1315 * associated VF, which is deduced from representor port name. 1316 * For example, let's have the IB device port 10, it has 1317 * attached network device eth0, which has port name attribute 1318 * pf0vf2, we can deduce the VF number as 2, and set vport index 1319 * as 3 (2+1). This assigning schema should be changed if the 1320 * multiple E-Switch instances per PF configurations or/and PCI 1321 * subfunctions are added. 1322 */ 1323 priv->vport_id = switch_info->representor ? 1324 switch_info->port_name + 1 : -1; 1325 /* representor_id field keeps the unmodified port/VF index. */ 1326 priv->representor_id = switch_info->representor ? 1327 switch_info->port_name : -1; 1328 /* 1329 * Look for sibling devices in order to reuse their switch domain 1330 * if any, otherwise allocate one. 1331 */ 1332 RTE_ETH_FOREACH_DEV_OF(port_id, dpdk_dev) { 1333 const struct mlx5_priv *opriv = 1334 rte_eth_devices[port_id].data->dev_private; 1335 1336 if (!opriv || 1337 opriv->domain_id == 1338 RTE_ETH_DEV_SWITCH_DOMAIN_ID_INVALID) 1339 continue; 1340 priv->domain_id = opriv->domain_id; 1341 break; 1342 } 1343 if (priv->domain_id == RTE_ETH_DEV_SWITCH_DOMAIN_ID_INVALID) { 1344 err = rte_eth_switch_domain_alloc(&priv->domain_id); 1345 if (err) { 1346 err = rte_errno; 1347 DRV_LOG(ERR, "unable to allocate switch domain: %s", 1348 strerror(rte_errno)); 1349 goto error; 1350 } 1351 own_domain_id = 1; 1352 } 1353 err = mlx5_args(&config, dpdk_dev->devargs); 1354 if (err) { 1355 err = rte_errno; 1356 DRV_LOG(ERR, "failed to process device arguments: %s", 1357 strerror(rte_errno)); 1358 goto error; 1359 } 1360 config.hw_csum = !!(sh->device_attr.device_cap_flags_ex & 1361 IBV_DEVICE_RAW_IP_CSUM); 1362 DRV_LOG(DEBUG, "checksum offloading is %ssupported", 1363 (config.hw_csum ? "" : "not ")); 1364 #if !defined(HAVE_IBV_DEVICE_COUNTERS_SET_V42) && \ 1365 !defined(HAVE_IBV_DEVICE_COUNTERS_SET_V45) 1366 DRV_LOG(DEBUG, "counters are not supported"); 1367 #endif 1368 #ifndef HAVE_IBV_FLOW_DV_SUPPORT 1369 if (config.dv_flow_en) { 1370 DRV_LOG(WARNING, "DV flow is not supported"); 1371 config.dv_flow_en = 0; 1372 } 1373 #endif 1374 config.ind_table_max_size = 1375 sh->device_attr.rss_caps.max_rwq_indirection_table_size; 1376 /* 1377 * Remove this check once DPDK supports larger/variable 1378 * indirection tables. 1379 */ 1380 if (config.ind_table_max_size > (unsigned int)ETH_RSS_RETA_SIZE_512) 1381 config.ind_table_max_size = ETH_RSS_RETA_SIZE_512; 1382 DRV_LOG(DEBUG, "maximum Rx indirection table size is %u", 1383 config.ind_table_max_size); 1384 config.hw_vlan_strip = !!(sh->device_attr.raw_packet_caps & 1385 IBV_RAW_PACKET_CAP_CVLAN_STRIPPING); 1386 DRV_LOG(DEBUG, "VLAN stripping is %ssupported", 1387 (config.hw_vlan_strip ? "" : "not ")); 1388 config.hw_fcs_strip = !!(sh->device_attr.raw_packet_caps & 1389 IBV_RAW_PACKET_CAP_SCATTER_FCS); 1390 DRV_LOG(DEBUG, "FCS stripping configuration is %ssupported", 1391 (config.hw_fcs_strip ? "" : "not ")); 1392 #if defined(HAVE_IBV_WQ_FLAG_RX_END_PADDING) 1393 hw_padding = !!sh->device_attr.rx_pad_end_addr_align; 1394 #elif defined(HAVE_IBV_WQ_FLAGS_PCI_WRITE_END_PADDING) 1395 hw_padding = !!(sh->device_attr.device_cap_flags_ex & 1396 IBV_DEVICE_PCI_WRITE_END_PADDING); 1397 #endif 1398 if (config.hw_padding && !hw_padding) { 1399 DRV_LOG(DEBUG, "Rx end alignment padding isn't supported"); 1400 config.hw_padding = 0; 1401 } else if (config.hw_padding) { 1402 DRV_LOG(DEBUG, "Rx end alignment padding is enabled"); 1403 } 1404 config.tso = (sh->device_attr.tso_caps.max_tso > 0 && 1405 (sh->device_attr.tso_caps.supported_qpts & 1406 (1 << IBV_QPT_RAW_PACKET))); 1407 if (config.tso) 1408 config.tso_max_payload_sz = sh->device_attr.tso_caps.max_tso; 1409 /* 1410 * MPW is disabled by default, while the Enhanced MPW is enabled 1411 * by default. 1412 */ 1413 if (config.mps == MLX5_ARG_UNSET) 1414 config.mps = (mps == MLX5_MPW_ENHANCED) ? MLX5_MPW_ENHANCED : 1415 MLX5_MPW_DISABLED; 1416 else 1417 config.mps = config.mps ? mps : MLX5_MPW_DISABLED; 1418 DRV_LOG(INFO, "%sMPS is %s", 1419 config.mps == MLX5_MPW_ENHANCED ? "enhanced " : "", 1420 config.mps != MLX5_MPW_DISABLED ? "enabled" : "disabled"); 1421 if (config.cqe_comp && !cqe_comp) { 1422 DRV_LOG(WARNING, "Rx CQE compression isn't supported"); 1423 config.cqe_comp = 0; 1424 } 1425 if (config.cqe_pad && !cqe_pad) { 1426 DRV_LOG(WARNING, "Rx CQE padding isn't supported"); 1427 config.cqe_pad = 0; 1428 } else if (config.cqe_pad) { 1429 DRV_LOG(INFO, "Rx CQE padding is enabled"); 1430 } 1431 if (config.mprq.enabled && mprq) { 1432 if (config.mprq.stride_num_n > mprq_max_stride_num_n || 1433 config.mprq.stride_num_n < mprq_min_stride_num_n) { 1434 config.mprq.stride_num_n = 1435 RTE_MAX(MLX5_MPRQ_STRIDE_NUM_N, 1436 mprq_min_stride_num_n); 1437 DRV_LOG(WARNING, 1438 "the number of strides" 1439 " for Multi-Packet RQ is out of range," 1440 " setting default value (%u)", 1441 1 << config.mprq.stride_num_n); 1442 } 1443 config.mprq.min_stride_size_n = mprq_min_stride_size_n; 1444 config.mprq.max_stride_size_n = mprq_max_stride_size_n; 1445 } else if (config.mprq.enabled && !mprq) { 1446 DRV_LOG(WARNING, "Multi-Packet RQ isn't supported"); 1447 config.mprq.enabled = 0; 1448 } 1449 if (config.max_dump_files_num == 0) 1450 config.max_dump_files_num = 128; 1451 eth_dev = rte_eth_dev_allocate(name); 1452 if (eth_dev == NULL) { 1453 DRV_LOG(ERR, "can not allocate rte ethdev"); 1454 err = ENOMEM; 1455 goto error; 1456 } 1457 /* Flag to call rte_eth_dev_release_port() in rte_eth_dev_close(). */ 1458 eth_dev->data->dev_flags |= RTE_ETH_DEV_CLOSE_REMOVE; 1459 if (priv->representor) { 1460 eth_dev->data->dev_flags |= RTE_ETH_DEV_REPRESENTOR; 1461 eth_dev->data->representor_id = priv->representor_id; 1462 } 1463 eth_dev->data->dev_private = priv; 1464 priv->dev_data = eth_dev->data; 1465 eth_dev->data->mac_addrs = priv->mac; 1466 eth_dev->device = dpdk_dev; 1467 /* Configure the first MAC address by default. */ 1468 if (mlx5_get_mac(eth_dev, &mac.addr_bytes)) { 1469 DRV_LOG(ERR, 1470 "port %u cannot get MAC address, is mlx5_en" 1471 " loaded? (errno: %s)", 1472 eth_dev->data->port_id, strerror(rte_errno)); 1473 err = ENODEV; 1474 goto error; 1475 } 1476 DRV_LOG(INFO, 1477 "port %u MAC address is %02x:%02x:%02x:%02x:%02x:%02x", 1478 eth_dev->data->port_id, 1479 mac.addr_bytes[0], mac.addr_bytes[1], 1480 mac.addr_bytes[2], mac.addr_bytes[3], 1481 mac.addr_bytes[4], mac.addr_bytes[5]); 1482 #ifndef NDEBUG 1483 { 1484 char ifname[IF_NAMESIZE]; 1485 1486 if (mlx5_get_ifname(eth_dev, &ifname) == 0) 1487 DRV_LOG(DEBUG, "port %u ifname is \"%s\"", 1488 eth_dev->data->port_id, ifname); 1489 else 1490 DRV_LOG(DEBUG, "port %u ifname is unknown", 1491 eth_dev->data->port_id); 1492 } 1493 #endif 1494 /* Get actual MTU if possible. */ 1495 err = mlx5_get_mtu(eth_dev, &priv->mtu); 1496 if (err) { 1497 err = rte_errno; 1498 goto error; 1499 } 1500 DRV_LOG(DEBUG, "port %u MTU is %u", eth_dev->data->port_id, 1501 priv->mtu); 1502 /* Initialize burst functions to prevent crashes before link-up. */ 1503 eth_dev->rx_pkt_burst = removed_rx_burst; 1504 eth_dev->tx_pkt_burst = removed_tx_burst; 1505 eth_dev->dev_ops = &mlx5_dev_ops; 1506 /* Register MAC address. */ 1507 claim_zero(mlx5_mac_addr_add(eth_dev, &mac, 0, 0)); 1508 if (config.vf && config.vf_nl_en) 1509 mlx5_nl_mac_addr_sync(eth_dev); 1510 TAILQ_INIT(&priv->flows); 1511 TAILQ_INIT(&priv->ctrl_flows); 1512 /* Hint libmlx5 to use PMD allocator for data plane resources */ 1513 struct mlx5dv_ctx_allocators alctr = { 1514 .alloc = &mlx5_alloc_verbs_buf, 1515 .free = &mlx5_free_verbs_buf, 1516 .data = priv, 1517 }; 1518 mlx5_glue->dv_set_context_attr(sh->ctx, 1519 MLX5DV_CTX_ATTR_BUF_ALLOCATORS, 1520 (void *)((uintptr_t)&alctr)); 1521 /* Bring Ethernet device up. */ 1522 DRV_LOG(DEBUG, "port %u forcing Ethernet interface up", 1523 eth_dev->data->port_id); 1524 mlx5_set_link_up(eth_dev); 1525 /* 1526 * Even though the interrupt handler is not installed yet, 1527 * interrupts will still trigger on the async_fd from 1528 * Verbs context returned by ibv_open_device(). 1529 */ 1530 mlx5_link_update(eth_dev, 0); 1531 #ifdef HAVE_IBV_DEVX_OBJ 1532 if (config.devx) { 1533 err = mlx5_devx_cmd_query_hca_attr(sh->ctx, &config.hca_attr); 1534 if (err) { 1535 err = -err; 1536 goto error; 1537 } 1538 } 1539 #endif 1540 #ifdef HAVE_MLX5DV_DR_ESWITCH 1541 if (!(config.hca_attr.eswitch_manager && config.dv_flow_en && 1542 (switch_info->representor || switch_info->master))) 1543 config.dv_esw_en = 0; 1544 #else 1545 config.dv_esw_en = 0; 1546 #endif 1547 /* Store device configuration on private structure. */ 1548 priv->config = config; 1549 if (config.dv_flow_en) { 1550 err = mlx5_alloc_shared_dr(priv); 1551 if (err) 1552 goto error; 1553 } 1554 /* Supported Verbs flow priority number detection. */ 1555 err = mlx5_flow_discover_priorities(eth_dev); 1556 if (err < 0) { 1557 err = -err; 1558 goto error; 1559 } 1560 priv->config.flow_prio = err; 1561 /* Add device to memory callback list. */ 1562 rte_rwlock_write_lock(&mlx5_shared_data->mem_event_rwlock); 1563 LIST_INSERT_HEAD(&mlx5_shared_data->mem_event_cb_list, 1564 sh, mem_event_cb); 1565 rte_rwlock_write_unlock(&mlx5_shared_data->mem_event_rwlock); 1566 return eth_dev; 1567 error: 1568 if (priv) { 1569 if (priv->sh) 1570 mlx5_free_shared_dr(priv); 1571 if (priv->nl_socket_route >= 0) 1572 close(priv->nl_socket_route); 1573 if (priv->nl_socket_rdma >= 0) 1574 close(priv->nl_socket_rdma); 1575 if (own_domain_id) 1576 claim_zero(rte_eth_switch_domain_free(priv->domain_id)); 1577 rte_free(priv); 1578 if (eth_dev != NULL) 1579 eth_dev->data->dev_private = NULL; 1580 } 1581 if (eth_dev != NULL) { 1582 /* mac_addrs must not be freed alone because part of dev_private */ 1583 eth_dev->data->mac_addrs = NULL; 1584 rte_eth_dev_release_port(eth_dev); 1585 } 1586 if (sh) 1587 mlx5_free_shared_ibctx(sh); 1588 assert(err > 0); 1589 rte_errno = err; 1590 return NULL; 1591 } 1592 1593 /** 1594 * Comparison callback to sort device data. 1595 * 1596 * This is meant to be used with qsort(). 1597 * 1598 * @param a[in] 1599 * Pointer to pointer to first data object. 1600 * @param b[in] 1601 * Pointer to pointer to second data object. 1602 * 1603 * @return 1604 * 0 if both objects are equal, less than 0 if the first argument is less 1605 * than the second, greater than 0 otherwise. 1606 */ 1607 static int 1608 mlx5_dev_spawn_data_cmp(const void *a, const void *b) 1609 { 1610 const struct mlx5_switch_info *si_a = 1611 &((const struct mlx5_dev_spawn_data *)a)->info; 1612 const struct mlx5_switch_info *si_b = 1613 &((const struct mlx5_dev_spawn_data *)b)->info; 1614 int ret; 1615 1616 /* Master device first. */ 1617 ret = si_b->master - si_a->master; 1618 if (ret) 1619 return ret; 1620 /* Then representor devices. */ 1621 ret = si_b->representor - si_a->representor; 1622 if (ret) 1623 return ret; 1624 /* Unidentified devices come last in no specific order. */ 1625 if (!si_a->representor) 1626 return 0; 1627 /* Order representors by name. */ 1628 return si_a->port_name - si_b->port_name; 1629 } 1630 1631 /** 1632 * DPDK callback to register a PCI device. 1633 * 1634 * This function spawns Ethernet devices out of a given PCI device. 1635 * 1636 * @param[in] pci_drv 1637 * PCI driver structure (mlx5_driver). 1638 * @param[in] pci_dev 1639 * PCI device information. 1640 * 1641 * @return 1642 * 0 on success, a negative errno value otherwise and rte_errno is set. 1643 */ 1644 static int 1645 mlx5_pci_probe(struct rte_pci_driver *pci_drv __rte_unused, 1646 struct rte_pci_device *pci_dev) 1647 { 1648 struct ibv_device **ibv_list; 1649 /* 1650 * Number of found IB Devices matching with requested PCI BDF. 1651 * nd != 1 means there are multiple IB devices over the same 1652 * PCI device and we have representors and master. 1653 */ 1654 unsigned int nd = 0; 1655 /* 1656 * Number of found IB device Ports. nd = 1 and np = 1..n means 1657 * we have the single multiport IB device, and there may be 1658 * representors attached to some of found ports. 1659 */ 1660 unsigned int np = 0; 1661 /* 1662 * Number of DPDK ethernet devices to Spawn - either over 1663 * multiple IB devices or multiple ports of single IB device. 1664 * Actually this is the number of iterations to spawn. 1665 */ 1666 unsigned int ns = 0; 1667 struct mlx5_dev_config dev_config; 1668 int ret; 1669 1670 ret = mlx5_init_once(); 1671 if (ret) { 1672 DRV_LOG(ERR, "unable to init PMD global data: %s", 1673 strerror(rte_errno)); 1674 return -rte_errno; 1675 } 1676 assert(pci_drv == &mlx5_driver); 1677 errno = 0; 1678 ibv_list = mlx5_glue->get_device_list(&ret); 1679 if (!ibv_list) { 1680 rte_errno = errno ? errno : ENOSYS; 1681 DRV_LOG(ERR, "cannot list devices, is ib_uverbs loaded?"); 1682 return -rte_errno; 1683 } 1684 /* 1685 * First scan the list of all Infiniband devices to find 1686 * matching ones, gathering into the list. 1687 */ 1688 struct ibv_device *ibv_match[ret + 1]; 1689 int nl_route = -1; 1690 int nl_rdma = -1; 1691 unsigned int i; 1692 1693 while (ret-- > 0) { 1694 struct rte_pci_addr pci_addr; 1695 1696 DRV_LOG(DEBUG, "checking device \"%s\"", ibv_list[ret]->name); 1697 if (mlx5_ibv_device_to_pci_addr(ibv_list[ret], &pci_addr)) 1698 continue; 1699 if (pci_dev->addr.domain != pci_addr.domain || 1700 pci_dev->addr.bus != pci_addr.bus || 1701 pci_dev->addr.devid != pci_addr.devid || 1702 pci_dev->addr.function != pci_addr.function) 1703 continue; 1704 DRV_LOG(INFO, "PCI information matches for device \"%s\"", 1705 ibv_list[ret]->name); 1706 ibv_match[nd++] = ibv_list[ret]; 1707 } 1708 ibv_match[nd] = NULL; 1709 if (!nd) { 1710 /* No device matches, just complain and bail out. */ 1711 mlx5_glue->free_device_list(ibv_list); 1712 DRV_LOG(WARNING, 1713 "no Verbs device matches PCI device " PCI_PRI_FMT "," 1714 " are kernel drivers loaded?", 1715 pci_dev->addr.domain, pci_dev->addr.bus, 1716 pci_dev->addr.devid, pci_dev->addr.function); 1717 rte_errno = ENOENT; 1718 ret = -rte_errno; 1719 return ret; 1720 } 1721 nl_route = mlx5_nl_init(NETLINK_ROUTE); 1722 nl_rdma = mlx5_nl_init(NETLINK_RDMA); 1723 if (nd == 1) { 1724 /* 1725 * Found single matching device may have multiple ports. 1726 * Each port may be representor, we have to check the port 1727 * number and check the representors existence. 1728 */ 1729 if (nl_rdma >= 0) 1730 np = mlx5_nl_portnum(nl_rdma, ibv_match[0]->name); 1731 if (!np) 1732 DRV_LOG(WARNING, "can not get IB device \"%s\"" 1733 " ports number", ibv_match[0]->name); 1734 } 1735 /* 1736 * Now we can determine the maximal 1737 * amount of devices to be spawned. 1738 */ 1739 struct mlx5_dev_spawn_data list[np ? np : nd]; 1740 1741 if (np > 1) { 1742 /* 1743 * Single IB device with multiple ports found, 1744 * it may be E-Switch master device and representors. 1745 * We have to perform identification trough the ports. 1746 */ 1747 assert(nl_rdma >= 0); 1748 assert(ns == 0); 1749 assert(nd == 1); 1750 for (i = 1; i <= np; ++i) { 1751 list[ns].max_port = np; 1752 list[ns].ibv_port = i; 1753 list[ns].ibv_dev = ibv_match[0]; 1754 list[ns].eth_dev = NULL; 1755 list[ns].pci_dev = pci_dev; 1756 list[ns].ifindex = mlx5_nl_ifindex 1757 (nl_rdma, list[ns].ibv_dev->name, i); 1758 if (!list[ns].ifindex) { 1759 /* 1760 * No network interface index found for the 1761 * specified port, it means there is no 1762 * representor on this port. It's OK, 1763 * there can be disabled ports, for example 1764 * if sriov_numvfs < sriov_totalvfs. 1765 */ 1766 continue; 1767 } 1768 ret = -1; 1769 if (nl_route >= 0) 1770 ret = mlx5_nl_switch_info 1771 (nl_route, 1772 list[ns].ifindex, 1773 &list[ns].info); 1774 if (ret || (!list[ns].info.representor && 1775 !list[ns].info.master)) { 1776 /* 1777 * We failed to recognize representors with 1778 * Netlink, let's try to perform the task 1779 * with sysfs. 1780 */ 1781 ret = mlx5_sysfs_switch_info 1782 (list[ns].ifindex, 1783 &list[ns].info); 1784 } 1785 if (!ret && (list[ns].info.representor ^ 1786 list[ns].info.master)) 1787 ns++; 1788 } 1789 if (!ns) { 1790 DRV_LOG(ERR, 1791 "unable to recognize master/representors" 1792 " on the IB device with multiple ports"); 1793 rte_errno = ENOENT; 1794 ret = -rte_errno; 1795 goto exit; 1796 } 1797 } else { 1798 /* 1799 * The existence of several matching entries (nd > 1) means 1800 * port representors have been instantiated. No existing Verbs 1801 * call nor sysfs entries can tell them apart, this can only 1802 * be done through Netlink calls assuming kernel drivers are 1803 * recent enough to support them. 1804 * 1805 * In the event of identification failure through Netlink, 1806 * try again through sysfs, then: 1807 * 1808 * 1. A single IB device matches (nd == 1) with single 1809 * port (np=0/1) and is not a representor, assume 1810 * no switch support. 1811 * 1812 * 2. Otherwise no safe assumptions can be made; 1813 * complain louder and bail out. 1814 */ 1815 np = 1; 1816 for (i = 0; i != nd; ++i) { 1817 memset(&list[ns].info, 0, sizeof(list[ns].info)); 1818 list[ns].max_port = 1; 1819 list[ns].ibv_port = 1; 1820 list[ns].ibv_dev = ibv_match[i]; 1821 list[ns].eth_dev = NULL; 1822 list[ns].pci_dev = pci_dev; 1823 list[ns].ifindex = 0; 1824 if (nl_rdma >= 0) 1825 list[ns].ifindex = mlx5_nl_ifindex 1826 (nl_rdma, list[ns].ibv_dev->name, 1); 1827 if (!list[ns].ifindex) { 1828 char ifname[IF_NAMESIZE]; 1829 1830 /* 1831 * Netlink failed, it may happen with old 1832 * ib_core kernel driver (before 4.16). 1833 * We can assume there is old driver because 1834 * here we are processing single ports IB 1835 * devices. Let's try sysfs to retrieve 1836 * the ifindex. The method works for 1837 * master device only. 1838 */ 1839 if (nd > 1) { 1840 /* 1841 * Multiple devices found, assume 1842 * representors, can not distinguish 1843 * master/representor and retrieve 1844 * ifindex via sysfs. 1845 */ 1846 continue; 1847 } 1848 ret = mlx5_get_master_ifname 1849 (ibv_match[i]->ibdev_path, &ifname); 1850 if (!ret) 1851 list[ns].ifindex = 1852 if_nametoindex(ifname); 1853 if (!list[ns].ifindex) { 1854 /* 1855 * No network interface index found 1856 * for the specified device, it means 1857 * there it is neither representor 1858 * nor master. 1859 */ 1860 continue; 1861 } 1862 } 1863 ret = -1; 1864 if (nl_route >= 0) 1865 ret = mlx5_nl_switch_info 1866 (nl_route, 1867 list[ns].ifindex, 1868 &list[ns].info); 1869 if (ret || (!list[ns].info.representor && 1870 !list[ns].info.master)) { 1871 /* 1872 * We failed to recognize representors with 1873 * Netlink, let's try to perform the task 1874 * with sysfs. 1875 */ 1876 ret = mlx5_sysfs_switch_info 1877 (list[ns].ifindex, 1878 &list[ns].info); 1879 } 1880 if (!ret && (list[ns].info.representor ^ 1881 list[ns].info.master)) { 1882 ns++; 1883 } else if ((nd == 1) && 1884 !list[ns].info.representor && 1885 !list[ns].info.master) { 1886 /* 1887 * Single IB device with 1888 * one physical port and 1889 * attached network device. 1890 * May be SRIOV is not enabled 1891 * or there is no representors. 1892 */ 1893 DRV_LOG(INFO, "no E-Switch support detected"); 1894 ns++; 1895 break; 1896 } 1897 } 1898 if (!ns) { 1899 DRV_LOG(ERR, 1900 "unable to recognize master/representors" 1901 " on the multiple IB devices"); 1902 rte_errno = ENOENT; 1903 ret = -rte_errno; 1904 goto exit; 1905 } 1906 } 1907 assert(ns); 1908 /* 1909 * Sort list to probe devices in natural order for users convenience 1910 * (i.e. master first, then representors from lowest to highest ID). 1911 */ 1912 qsort(list, ns, sizeof(*list), mlx5_dev_spawn_data_cmp); 1913 /* Default configuration. */ 1914 dev_config = (struct mlx5_dev_config){ 1915 .hw_padding = 0, 1916 .mps = MLX5_ARG_UNSET, 1917 .tx_vec_en = 1, 1918 .rx_vec_en = 1, 1919 .txq_inline = MLX5_ARG_UNSET, 1920 .txqs_inline = MLX5_ARG_UNSET, 1921 .txqs_vec = MLX5_ARG_UNSET, 1922 .inline_max_packet_sz = MLX5_ARG_UNSET, 1923 .vf_nl_en = 1, 1924 .mr_ext_memseg_en = 1, 1925 .mprq = { 1926 .enabled = 0, /* Disabled by default. */ 1927 .stride_num_n = MLX5_MPRQ_STRIDE_NUM_N, 1928 .max_memcpy_len = MLX5_MPRQ_MEMCPY_DEFAULT_LEN, 1929 .min_rxqs_num = MLX5_MPRQ_MIN_RXQS, 1930 }, 1931 .dv_esw_en = 1, 1932 }; 1933 /* Device specific configuration. */ 1934 switch (pci_dev->id.device_id) { 1935 case PCI_DEVICE_ID_MELLANOX_CONNECTX5BF: 1936 dev_config.txqs_vec = MLX5_VPMD_MAX_TXQS_BLUEFIELD; 1937 break; 1938 case PCI_DEVICE_ID_MELLANOX_CONNECTX4VF: 1939 case PCI_DEVICE_ID_MELLANOX_CONNECTX4LXVF: 1940 case PCI_DEVICE_ID_MELLANOX_CONNECTX5VF: 1941 case PCI_DEVICE_ID_MELLANOX_CONNECTX5EXVF: 1942 dev_config.vf = 1; 1943 break; 1944 default: 1945 break; 1946 } 1947 /* Set architecture-dependent default value if unset. */ 1948 if (dev_config.txqs_vec == MLX5_ARG_UNSET) 1949 dev_config.txqs_vec = MLX5_VPMD_MAX_TXQS; 1950 for (i = 0; i != ns; ++i) { 1951 uint32_t restore; 1952 1953 list[i].eth_dev = mlx5_dev_spawn(&pci_dev->device, 1954 &list[i], 1955 dev_config); 1956 if (!list[i].eth_dev) { 1957 if (rte_errno != EBUSY && rte_errno != EEXIST) 1958 break; 1959 /* Device is disabled or already spawned. Ignore it. */ 1960 continue; 1961 } 1962 restore = list[i].eth_dev->data->dev_flags; 1963 rte_eth_copy_pci_info(list[i].eth_dev, pci_dev); 1964 /* Restore non-PCI flags cleared by the above call. */ 1965 list[i].eth_dev->data->dev_flags |= restore; 1966 rte_eth_dev_probing_finish(list[i].eth_dev); 1967 } 1968 if (i != ns) { 1969 DRV_LOG(ERR, 1970 "probe of PCI device " PCI_PRI_FMT " aborted after" 1971 " encountering an error: %s", 1972 pci_dev->addr.domain, pci_dev->addr.bus, 1973 pci_dev->addr.devid, pci_dev->addr.function, 1974 strerror(rte_errno)); 1975 ret = -rte_errno; 1976 /* Roll back. */ 1977 while (i--) { 1978 if (!list[i].eth_dev) 1979 continue; 1980 mlx5_dev_close(list[i].eth_dev); 1981 /* mac_addrs must not be freed because in dev_private */ 1982 list[i].eth_dev->data->mac_addrs = NULL; 1983 claim_zero(rte_eth_dev_release_port(list[i].eth_dev)); 1984 } 1985 /* Restore original error. */ 1986 rte_errno = -ret; 1987 } else { 1988 ret = 0; 1989 } 1990 exit: 1991 /* 1992 * Do the routine cleanup: 1993 * - close opened Netlink sockets 1994 * - free the Infiniband device list 1995 */ 1996 if (nl_rdma >= 0) 1997 close(nl_rdma); 1998 if (nl_route >= 0) 1999 close(nl_route); 2000 assert(ibv_list); 2001 mlx5_glue->free_device_list(ibv_list); 2002 return ret; 2003 } 2004 2005 /** 2006 * DPDK callback to remove a PCI device. 2007 * 2008 * This function removes all Ethernet devices belong to a given PCI device. 2009 * 2010 * @param[in] pci_dev 2011 * Pointer to the PCI device. 2012 * 2013 * @return 2014 * 0 on success, the function cannot fail. 2015 */ 2016 static int 2017 mlx5_pci_remove(struct rte_pci_device *pci_dev) 2018 { 2019 uint16_t port_id; 2020 2021 RTE_ETH_FOREACH_DEV_OF(port_id, &pci_dev->device) 2022 rte_eth_dev_close(port_id); 2023 return 0; 2024 } 2025 2026 static const struct rte_pci_id mlx5_pci_id_map[] = { 2027 { 2028 RTE_PCI_DEVICE(PCI_VENDOR_ID_MELLANOX, 2029 PCI_DEVICE_ID_MELLANOX_CONNECTX4) 2030 }, 2031 { 2032 RTE_PCI_DEVICE(PCI_VENDOR_ID_MELLANOX, 2033 PCI_DEVICE_ID_MELLANOX_CONNECTX4VF) 2034 }, 2035 { 2036 RTE_PCI_DEVICE(PCI_VENDOR_ID_MELLANOX, 2037 PCI_DEVICE_ID_MELLANOX_CONNECTX4LX) 2038 }, 2039 { 2040 RTE_PCI_DEVICE(PCI_VENDOR_ID_MELLANOX, 2041 PCI_DEVICE_ID_MELLANOX_CONNECTX4LXVF) 2042 }, 2043 { 2044 RTE_PCI_DEVICE(PCI_VENDOR_ID_MELLANOX, 2045 PCI_DEVICE_ID_MELLANOX_CONNECTX5) 2046 }, 2047 { 2048 RTE_PCI_DEVICE(PCI_VENDOR_ID_MELLANOX, 2049 PCI_DEVICE_ID_MELLANOX_CONNECTX5VF) 2050 }, 2051 { 2052 RTE_PCI_DEVICE(PCI_VENDOR_ID_MELLANOX, 2053 PCI_DEVICE_ID_MELLANOX_CONNECTX5EX) 2054 }, 2055 { 2056 RTE_PCI_DEVICE(PCI_VENDOR_ID_MELLANOX, 2057 PCI_DEVICE_ID_MELLANOX_CONNECTX5EXVF) 2058 }, 2059 { 2060 RTE_PCI_DEVICE(PCI_VENDOR_ID_MELLANOX, 2061 PCI_DEVICE_ID_MELLANOX_CONNECTX5BF) 2062 }, 2063 { 2064 RTE_PCI_DEVICE(PCI_VENDOR_ID_MELLANOX, 2065 PCI_DEVICE_ID_MELLANOX_CONNECTX5BFVF) 2066 }, 2067 { 2068 RTE_PCI_DEVICE(PCI_VENDOR_ID_MELLANOX, 2069 PCI_DEVICE_ID_MELLANOX_CONNECTX6) 2070 }, 2071 { 2072 RTE_PCI_DEVICE(PCI_VENDOR_ID_MELLANOX, 2073 PCI_DEVICE_ID_MELLANOX_CONNECTX6VF) 2074 }, 2075 { 2076 .vendor_id = 0 2077 } 2078 }; 2079 2080 static struct rte_pci_driver mlx5_driver = { 2081 .driver = { 2082 .name = MLX5_DRIVER_NAME 2083 }, 2084 .id_table = mlx5_pci_id_map, 2085 .probe = mlx5_pci_probe, 2086 .remove = mlx5_pci_remove, 2087 .dma_map = mlx5_dma_map, 2088 .dma_unmap = mlx5_dma_unmap, 2089 .drv_flags = RTE_PCI_DRV_INTR_LSC | RTE_PCI_DRV_INTR_RMV | 2090 RTE_PCI_DRV_PROBE_AGAIN | RTE_PCI_DRV_IOVA_AS_VA, 2091 }; 2092 2093 #ifdef RTE_IBVERBS_LINK_DLOPEN 2094 2095 /** 2096 * Suffix RTE_EAL_PMD_PATH with "-glue". 2097 * 2098 * This function performs a sanity check on RTE_EAL_PMD_PATH before 2099 * suffixing its last component. 2100 * 2101 * @param buf[out] 2102 * Output buffer, should be large enough otherwise NULL is returned. 2103 * @param size 2104 * Size of @p out. 2105 * 2106 * @return 2107 * Pointer to @p buf or @p NULL in case suffix cannot be appended. 2108 */ 2109 static char * 2110 mlx5_glue_path(char *buf, size_t size) 2111 { 2112 static const char *const bad[] = { "/", ".", "..", NULL }; 2113 const char *path = RTE_EAL_PMD_PATH; 2114 size_t len = strlen(path); 2115 size_t off; 2116 int i; 2117 2118 while (len && path[len - 1] == '/') 2119 --len; 2120 for (off = len; off && path[off - 1] != '/'; --off) 2121 ; 2122 for (i = 0; bad[i]; ++i) 2123 if (!strncmp(path + off, bad[i], (int)(len - off))) 2124 goto error; 2125 i = snprintf(buf, size, "%.*s-glue", (int)len, path); 2126 if (i == -1 || (size_t)i >= size) 2127 goto error; 2128 return buf; 2129 error: 2130 DRV_LOG(ERR, 2131 "unable to append \"-glue\" to last component of" 2132 " RTE_EAL_PMD_PATH (\"" RTE_EAL_PMD_PATH "\")," 2133 " please re-configure DPDK"); 2134 return NULL; 2135 } 2136 2137 /** 2138 * Initialization routine for run-time dependency on rdma-core. 2139 */ 2140 static int 2141 mlx5_glue_init(void) 2142 { 2143 char glue_path[sizeof(RTE_EAL_PMD_PATH) - 1 + sizeof("-glue")]; 2144 const char *path[] = { 2145 /* 2146 * A basic security check is necessary before trusting 2147 * MLX5_GLUE_PATH, which may override RTE_EAL_PMD_PATH. 2148 */ 2149 (geteuid() == getuid() && getegid() == getgid() ? 2150 getenv("MLX5_GLUE_PATH") : NULL), 2151 /* 2152 * When RTE_EAL_PMD_PATH is set, use its glue-suffixed 2153 * variant, otherwise let dlopen() look up libraries on its 2154 * own. 2155 */ 2156 (*RTE_EAL_PMD_PATH ? 2157 mlx5_glue_path(glue_path, sizeof(glue_path)) : ""), 2158 }; 2159 unsigned int i = 0; 2160 void *handle = NULL; 2161 void **sym; 2162 const char *dlmsg; 2163 2164 while (!handle && i != RTE_DIM(path)) { 2165 const char *end; 2166 size_t len; 2167 int ret; 2168 2169 if (!path[i]) { 2170 ++i; 2171 continue; 2172 } 2173 end = strpbrk(path[i], ":;"); 2174 if (!end) 2175 end = path[i] + strlen(path[i]); 2176 len = end - path[i]; 2177 ret = 0; 2178 do { 2179 char name[ret + 1]; 2180 2181 ret = snprintf(name, sizeof(name), "%.*s%s" MLX5_GLUE, 2182 (int)len, path[i], 2183 (!len || *(end - 1) == '/') ? "" : "/"); 2184 if (ret == -1) 2185 break; 2186 if (sizeof(name) != (size_t)ret + 1) 2187 continue; 2188 DRV_LOG(DEBUG, "looking for rdma-core glue as \"%s\"", 2189 name); 2190 handle = dlopen(name, RTLD_LAZY); 2191 break; 2192 } while (1); 2193 path[i] = end + 1; 2194 if (!*end) 2195 ++i; 2196 } 2197 if (!handle) { 2198 rte_errno = EINVAL; 2199 dlmsg = dlerror(); 2200 if (dlmsg) 2201 DRV_LOG(WARNING, "cannot load glue library: %s", dlmsg); 2202 goto glue_error; 2203 } 2204 sym = dlsym(handle, "mlx5_glue"); 2205 if (!sym || !*sym) { 2206 rte_errno = EINVAL; 2207 dlmsg = dlerror(); 2208 if (dlmsg) 2209 DRV_LOG(ERR, "cannot resolve glue symbol: %s", dlmsg); 2210 goto glue_error; 2211 } 2212 mlx5_glue = *sym; 2213 return 0; 2214 glue_error: 2215 if (handle) 2216 dlclose(handle); 2217 DRV_LOG(WARNING, 2218 "cannot initialize PMD due to missing run-time dependency on" 2219 " rdma-core libraries (libibverbs, libmlx5)"); 2220 return -rte_errno; 2221 } 2222 2223 #endif 2224 2225 /** 2226 * Driver initialization routine. 2227 */ 2228 RTE_INIT(rte_mlx5_pmd_init) 2229 { 2230 /* Initialize driver log type. */ 2231 mlx5_logtype = rte_log_register("pmd.net.mlx5"); 2232 if (mlx5_logtype >= 0) 2233 rte_log_set_level(mlx5_logtype, RTE_LOG_NOTICE); 2234 2235 /* Build the static tables for Verbs conversion. */ 2236 mlx5_set_ptype_table(); 2237 mlx5_set_cksum_table(); 2238 mlx5_set_swp_types_table(); 2239 /* 2240 * RDMAV_HUGEPAGES_SAFE tells ibv_fork_init() we intend to use 2241 * huge pages. Calling ibv_fork_init() during init allows 2242 * applications to use fork() safely for purposes other than 2243 * using this PMD, which is not supported in forked processes. 2244 */ 2245 setenv("RDMAV_HUGEPAGES_SAFE", "1", 1); 2246 /* Match the size of Rx completion entry to the size of a cacheline. */ 2247 if (RTE_CACHE_LINE_SIZE == 128) 2248 setenv("MLX5_CQE_SIZE", "128", 0); 2249 /* 2250 * MLX5_DEVICE_FATAL_CLEANUP tells ibv_destroy functions to 2251 * cleanup all the Verbs resources even when the device was removed. 2252 */ 2253 setenv("MLX5_DEVICE_FATAL_CLEANUP", "1", 1); 2254 #ifdef RTE_IBVERBS_LINK_DLOPEN 2255 if (mlx5_glue_init()) 2256 return; 2257 assert(mlx5_glue); 2258 #endif 2259 #ifndef NDEBUG 2260 /* Glue structure must not contain any NULL pointers. */ 2261 { 2262 unsigned int i; 2263 2264 for (i = 0; i != sizeof(*mlx5_glue) / sizeof(void *); ++i) 2265 assert(((const void *const *)mlx5_glue)[i]); 2266 } 2267 #endif 2268 if (strcmp(mlx5_glue->version, MLX5_GLUE_VERSION)) { 2269 DRV_LOG(ERR, 2270 "rdma-core glue \"%s\" mismatch: \"%s\" is required", 2271 mlx5_glue->version, MLX5_GLUE_VERSION); 2272 return; 2273 } 2274 mlx5_glue->fork_init(); 2275 rte_pci_register(&mlx5_driver); 2276 } 2277 2278 RTE_PMD_EXPORT_NAME(net_mlx5, __COUNTER__); 2279 RTE_PMD_REGISTER_PCI_TABLE(net_mlx5, mlx5_pci_id_map); 2280 RTE_PMD_REGISTER_KMOD_DEP(net_mlx5, "* ib_uverbs & mlx5_core & mlx5_ib"); 2281