1 /* SPDX-License-Identifier: BSD-3-Clause 2 * Copyright 2015 6WIND S.A. 3 * Copyright 2015 Mellanox Technologies, Ltd 4 */ 5 6 #include <stddef.h> 7 #include <unistd.h> 8 #include <string.h> 9 #include <stdint.h> 10 #include <stdlib.h> 11 #include <errno.h> 12 #include <net/if.h> 13 #include <sys/mman.h> 14 #include <linux/rtnetlink.h> 15 16 /* Verbs header. */ 17 /* ISO C doesn't support unnamed structs/unions, disabling -pedantic. */ 18 #ifdef PEDANTIC 19 #pragma GCC diagnostic ignored "-Wpedantic" 20 #endif 21 #include <infiniband/verbs.h> 22 #ifdef PEDANTIC 23 #pragma GCC diagnostic error "-Wpedantic" 24 #endif 25 26 #include <rte_malloc.h> 27 #include <rte_ethdev_driver.h> 28 #include <rte_ethdev_pci.h> 29 #include <rte_pci.h> 30 #include <rte_bus_pci.h> 31 #include <rte_common.h> 32 #include <rte_config.h> 33 #include <rte_kvargs.h> 34 #include <rte_rwlock.h> 35 #include <rte_spinlock.h> 36 #include <rte_string_fns.h> 37 #include <rte_alarm.h> 38 39 #include <mlx5_glue.h> 40 #include <mlx5_devx_cmds.h> 41 #include <mlx5_common.h> 42 43 #include "mlx5_defs.h" 44 #include "mlx5.h" 45 #include "mlx5_utils.h" 46 #include "mlx5_rxtx.h" 47 #include "mlx5_autoconf.h" 48 #include "mlx5_mr.h" 49 #include "mlx5_flow.h" 50 #include "rte_pmd_mlx5.h" 51 52 /* Device parameter to enable RX completion queue compression. */ 53 #define MLX5_RXQ_CQE_COMP_EN "rxq_cqe_comp_en" 54 55 /* Device parameter to enable RX completion entry padding to 128B. */ 56 #define MLX5_RXQ_CQE_PAD_EN "rxq_cqe_pad_en" 57 58 /* Device parameter to enable padding Rx packet to cacheline size. */ 59 #define MLX5_RXQ_PKT_PAD_EN "rxq_pkt_pad_en" 60 61 /* Device parameter to enable Multi-Packet Rx queue. */ 62 #define MLX5_RX_MPRQ_EN "mprq_en" 63 64 /* Device parameter to configure log 2 of the number of strides for MPRQ. */ 65 #define MLX5_RX_MPRQ_LOG_STRIDE_NUM "mprq_log_stride_num" 66 67 /* Device parameter to limit the size of memcpy'd packet for MPRQ. */ 68 #define MLX5_RX_MPRQ_MAX_MEMCPY_LEN "mprq_max_memcpy_len" 69 70 /* Device parameter to set the minimum number of Rx queues to enable MPRQ. */ 71 #define MLX5_RXQS_MIN_MPRQ "rxqs_min_mprq" 72 73 /* Device parameter to configure inline send. Deprecated, ignored.*/ 74 #define MLX5_TXQ_INLINE "txq_inline" 75 76 /* Device parameter to limit packet size to inline with ordinary SEND. */ 77 #define MLX5_TXQ_INLINE_MAX "txq_inline_max" 78 79 /* Device parameter to configure minimal data size to inline. */ 80 #define MLX5_TXQ_INLINE_MIN "txq_inline_min" 81 82 /* Device parameter to limit packet size to inline with Enhanced MPW. */ 83 #define MLX5_TXQ_INLINE_MPW "txq_inline_mpw" 84 85 /* 86 * Device parameter to configure the number of TX queues threshold for 87 * enabling inline send. 88 */ 89 #define MLX5_TXQS_MIN_INLINE "txqs_min_inline" 90 91 /* 92 * Device parameter to configure the number of TX queues threshold for 93 * enabling vectorized Tx, deprecated, ignored (no vectorized Tx routines). 94 */ 95 #define MLX5_TXQS_MAX_VEC "txqs_max_vec" 96 97 /* Device parameter to enable multi-packet send WQEs. */ 98 #define MLX5_TXQ_MPW_EN "txq_mpw_en" 99 100 /* 101 * Device parameter to force doorbell register mapping 102 * to non-cahed region eliminating the extra write memory barrier. 103 */ 104 #define MLX5_TX_DB_NC "tx_db_nc" 105 106 /* 107 * Device parameter to include 2 dsegs in the title WQEBB. 108 * Deprecated, ignored. 109 */ 110 #define MLX5_TXQ_MPW_HDR_DSEG_EN "txq_mpw_hdr_dseg_en" 111 112 /* 113 * Device parameter to limit the size of inlining packet. 114 * Deprecated, ignored. 115 */ 116 #define MLX5_TXQ_MAX_INLINE_LEN "txq_max_inline_len" 117 118 /* 119 * Device parameter to enable hardware Tx vector. 120 * Deprecated, ignored (no vectorized Tx routines anymore). 121 */ 122 #define MLX5_TX_VEC_EN "tx_vec_en" 123 124 /* Device parameter to enable hardware Rx vector. */ 125 #define MLX5_RX_VEC_EN "rx_vec_en" 126 127 /* Allow L3 VXLAN flow creation. */ 128 #define MLX5_L3_VXLAN_EN "l3_vxlan_en" 129 130 /* Activate DV E-Switch flow steering. */ 131 #define MLX5_DV_ESW_EN "dv_esw_en" 132 133 /* Activate DV flow steering. */ 134 #define MLX5_DV_FLOW_EN "dv_flow_en" 135 136 /* Enable extensive flow metadata support. */ 137 #define MLX5_DV_XMETA_EN "dv_xmeta_en" 138 139 /* Activate Netlink support in VF mode. */ 140 #define MLX5_VF_NL_EN "vf_nl_en" 141 142 /* Enable extending memsegs when creating a MR. */ 143 #define MLX5_MR_EXT_MEMSEG_EN "mr_ext_memseg_en" 144 145 /* Select port representors to instantiate. */ 146 #define MLX5_REPRESENTOR "representor" 147 148 /* Device parameter to configure the maximum number of dump files per queue. */ 149 #define MLX5_MAX_DUMP_FILES_NUM "max_dump_files_num" 150 151 /* Configure timeout of LRO session (in microseconds). */ 152 #define MLX5_LRO_TIMEOUT_USEC "lro_timeout_usec" 153 154 #ifndef HAVE_IBV_MLX5_MOD_MPW 155 #define MLX5DV_CONTEXT_FLAGS_MPW_ALLOWED (1 << 2) 156 #define MLX5DV_CONTEXT_FLAGS_ENHANCED_MPW (1 << 3) 157 #endif 158 159 #ifndef HAVE_IBV_MLX5_MOD_CQE_128B_COMP 160 #define MLX5DV_CONTEXT_FLAGS_CQE_128B_COMP (1 << 4) 161 #endif 162 163 static const char *MZ_MLX5_PMD_SHARED_DATA = "mlx5_pmd_shared_data"; 164 165 /* Shared memory between primary and secondary processes. */ 166 struct mlx5_shared_data *mlx5_shared_data; 167 168 /* Spinlock for mlx5_shared_data allocation. */ 169 static rte_spinlock_t mlx5_shared_data_lock = RTE_SPINLOCK_INITIALIZER; 170 171 /* Process local data for secondary processes. */ 172 static struct mlx5_local_data mlx5_local_data; 173 174 /** Driver-specific log messages type. */ 175 int mlx5_logtype; 176 177 /** Data associated with devices to spawn. */ 178 struct mlx5_dev_spawn_data { 179 uint32_t ifindex; /**< Network interface index. */ 180 uint32_t max_port; /**< IB device maximal port index. */ 181 uint32_t ibv_port; /**< IB device physical port index. */ 182 int pf_bond; /**< bonding device PF index. < 0 - no bonding */ 183 struct mlx5_switch_info info; /**< Switch information. */ 184 struct ibv_device *ibv_dev; /**< Associated IB device. */ 185 struct rte_eth_dev *eth_dev; /**< Associated Ethernet device. */ 186 struct rte_pci_device *pci_dev; /**< Backend PCI device. */ 187 }; 188 189 static LIST_HEAD(, mlx5_ibv_shared) mlx5_ibv_list = LIST_HEAD_INITIALIZER(); 190 static pthread_mutex_t mlx5_ibv_list_mutex = PTHREAD_MUTEX_INITIALIZER; 191 192 #define MLX5_FLOW_MIN_ID_POOL_SIZE 512 193 #define MLX5_ID_GENERATION_ARRAY_FACTOR 16 194 195 #define MLX5_FLOW_TABLE_HLIST_ARRAY_SIZE 4096 196 #define MLX5_TAGS_HLIST_ARRAY_SIZE 8192 197 198 /** 199 * Allocate ID pool structure. 200 * 201 * @param[in] max_id 202 * The maximum id can be allocated from the pool. 203 * 204 * @return 205 * Pointer to pool object, NULL value otherwise. 206 */ 207 struct mlx5_flow_id_pool * 208 mlx5_flow_id_pool_alloc(uint32_t max_id) 209 { 210 struct mlx5_flow_id_pool *pool; 211 void *mem; 212 213 pool = rte_zmalloc("id pool allocation", sizeof(*pool), 214 RTE_CACHE_LINE_SIZE); 215 if (!pool) { 216 DRV_LOG(ERR, "can't allocate id pool"); 217 rte_errno = ENOMEM; 218 return NULL; 219 } 220 mem = rte_zmalloc("", MLX5_FLOW_MIN_ID_POOL_SIZE * sizeof(uint32_t), 221 RTE_CACHE_LINE_SIZE); 222 if (!mem) { 223 DRV_LOG(ERR, "can't allocate mem for id pool"); 224 rte_errno = ENOMEM; 225 goto error; 226 } 227 pool->free_arr = mem; 228 pool->curr = pool->free_arr; 229 pool->last = pool->free_arr + MLX5_FLOW_MIN_ID_POOL_SIZE; 230 pool->base_index = 0; 231 pool->max_id = max_id; 232 return pool; 233 error: 234 rte_free(pool); 235 return NULL; 236 } 237 238 /** 239 * Release ID pool structure. 240 * 241 * @param[in] pool 242 * Pointer to flow id pool object to free. 243 */ 244 void 245 mlx5_flow_id_pool_release(struct mlx5_flow_id_pool *pool) 246 { 247 rte_free(pool->free_arr); 248 rte_free(pool); 249 } 250 251 /** 252 * Generate ID. 253 * 254 * @param[in] pool 255 * Pointer to flow id pool. 256 * @param[out] id 257 * The generated ID. 258 * 259 * @return 260 * 0 on success, error value otherwise. 261 */ 262 uint32_t 263 mlx5_flow_id_get(struct mlx5_flow_id_pool *pool, uint32_t *id) 264 { 265 if (pool->curr == pool->free_arr) { 266 if (pool->base_index == pool->max_id) { 267 rte_errno = ENOMEM; 268 DRV_LOG(ERR, "no free id"); 269 return -rte_errno; 270 } 271 *id = ++pool->base_index; 272 return 0; 273 } 274 *id = *(--pool->curr); 275 return 0; 276 } 277 278 /** 279 * Release ID. 280 * 281 * @param[in] pool 282 * Pointer to flow id pool. 283 * @param[out] id 284 * The generated ID. 285 * 286 * @return 287 * 0 on success, error value otherwise. 288 */ 289 uint32_t 290 mlx5_flow_id_release(struct mlx5_flow_id_pool *pool, uint32_t id) 291 { 292 uint32_t size; 293 uint32_t size2; 294 void *mem; 295 296 if (pool->curr == pool->last) { 297 size = pool->curr - pool->free_arr; 298 size2 = size * MLX5_ID_GENERATION_ARRAY_FACTOR; 299 MLX5_ASSERT(size2 > size); 300 mem = rte_malloc("", size2 * sizeof(uint32_t), 0); 301 if (!mem) { 302 DRV_LOG(ERR, "can't allocate mem for id pool"); 303 rte_errno = ENOMEM; 304 return -rte_errno; 305 } 306 memcpy(mem, pool->free_arr, size * sizeof(uint32_t)); 307 rte_free(pool->free_arr); 308 pool->free_arr = mem; 309 pool->curr = pool->free_arr + size; 310 pool->last = pool->free_arr + size2; 311 } 312 *pool->curr = id; 313 pool->curr++; 314 return 0; 315 } 316 317 /** 318 * Initialize the counters management structure. 319 * 320 * @param[in] sh 321 * Pointer to mlx5_ibv_shared object to free 322 */ 323 static void 324 mlx5_flow_counters_mng_init(struct mlx5_ibv_shared *sh) 325 { 326 uint8_t i; 327 328 TAILQ_INIT(&sh->cmng.flow_counters); 329 for (i = 0; i < RTE_DIM(sh->cmng.ccont); ++i) 330 TAILQ_INIT(&sh->cmng.ccont[i].pool_list); 331 } 332 333 /** 334 * Destroy all the resources allocated for a counter memory management. 335 * 336 * @param[in] mng 337 * Pointer to the memory management structure. 338 */ 339 static void 340 mlx5_flow_destroy_counter_stat_mem_mng(struct mlx5_counter_stats_mem_mng *mng) 341 { 342 uint8_t *mem = (uint8_t *)(uintptr_t)mng->raws[0].data; 343 344 LIST_REMOVE(mng, next); 345 claim_zero(mlx5_devx_cmd_destroy(mng->dm)); 346 claim_zero(mlx5_glue->devx_umem_dereg(mng->umem)); 347 rte_free(mem); 348 } 349 350 /** 351 * Close and release all the resources of the counters management. 352 * 353 * @param[in] sh 354 * Pointer to mlx5_ibv_shared object to free. 355 */ 356 static void 357 mlx5_flow_counters_mng_close(struct mlx5_ibv_shared *sh) 358 { 359 struct mlx5_counter_stats_mem_mng *mng; 360 uint8_t i; 361 int j; 362 int retries = 1024; 363 364 rte_errno = 0; 365 while (--retries) { 366 rte_eal_alarm_cancel(mlx5_flow_query_alarm, sh); 367 if (rte_errno != EINPROGRESS) 368 break; 369 rte_pause(); 370 } 371 for (i = 0; i < RTE_DIM(sh->cmng.ccont); ++i) { 372 struct mlx5_flow_counter_pool *pool; 373 uint32_t batch = !!(i % 2); 374 375 if (!sh->cmng.ccont[i].pools) 376 continue; 377 pool = TAILQ_FIRST(&sh->cmng.ccont[i].pool_list); 378 while (pool) { 379 if (batch) { 380 if (pool->min_dcs) 381 claim_zero 382 (mlx5_devx_cmd_destroy(pool->min_dcs)); 383 } 384 for (j = 0; j < MLX5_COUNTERS_PER_POOL; ++j) { 385 if (pool->counters_raw[j].action) 386 claim_zero 387 (mlx5_glue->destroy_flow_action 388 (pool->counters_raw[j].action)); 389 if (!batch && pool->counters_raw[j].dcs) 390 claim_zero(mlx5_devx_cmd_destroy 391 (pool->counters_raw[j].dcs)); 392 } 393 TAILQ_REMOVE(&sh->cmng.ccont[i].pool_list, pool, 394 next); 395 rte_free(pool); 396 pool = TAILQ_FIRST(&sh->cmng.ccont[i].pool_list); 397 } 398 rte_free(sh->cmng.ccont[i].pools); 399 } 400 mng = LIST_FIRST(&sh->cmng.mem_mngs); 401 while (mng) { 402 mlx5_flow_destroy_counter_stat_mem_mng(mng); 403 mng = LIST_FIRST(&sh->cmng.mem_mngs); 404 } 405 memset(&sh->cmng, 0, sizeof(sh->cmng)); 406 } 407 408 /** 409 * Extract pdn of PD object using DV API. 410 * 411 * @param[in] pd 412 * Pointer to the verbs PD object. 413 * @param[out] pdn 414 * Pointer to the PD object number variable. 415 * 416 * @return 417 * 0 on success, error value otherwise. 418 */ 419 #ifdef HAVE_IBV_FLOW_DV_SUPPORT 420 static int 421 mlx5_get_pdn(struct ibv_pd *pd __rte_unused, uint32_t *pdn __rte_unused) 422 { 423 struct mlx5dv_obj obj; 424 struct mlx5dv_pd pd_info; 425 int ret = 0; 426 427 obj.pd.in = pd; 428 obj.pd.out = &pd_info; 429 ret = mlx5_glue->dv_init_obj(&obj, MLX5DV_OBJ_PD); 430 if (ret) { 431 DRV_LOG(DEBUG, "Fail to get PD object info"); 432 return ret; 433 } 434 *pdn = pd_info.pdn; 435 return 0; 436 } 437 #endif /* HAVE_IBV_FLOW_DV_SUPPORT */ 438 439 static int 440 mlx5_config_doorbell_mapping_env(const struct mlx5_dev_config *config) 441 { 442 char *env; 443 int value; 444 445 MLX5_ASSERT(rte_eal_process_type() == RTE_PROC_PRIMARY); 446 /* Get environment variable to store. */ 447 env = getenv(MLX5_SHUT_UP_BF); 448 value = env ? !!strcmp(env, "0") : MLX5_ARG_UNSET; 449 if (config->dbnc == MLX5_ARG_UNSET) 450 setenv(MLX5_SHUT_UP_BF, MLX5_SHUT_UP_BF_DEFAULT, 1); 451 else 452 setenv(MLX5_SHUT_UP_BF, 453 config->dbnc == MLX5_TXDB_NCACHED ? "1" : "0", 1); 454 return value; 455 } 456 457 static void 458 mlx5_restore_doorbell_mapping_env(int value) 459 { 460 MLX5_ASSERT(rte_eal_process_type() == RTE_PROC_PRIMARY); 461 /* Restore the original environment variable state. */ 462 if (value == MLX5_ARG_UNSET) 463 unsetenv(MLX5_SHUT_UP_BF); 464 else 465 setenv(MLX5_SHUT_UP_BF, value ? "1" : "0", 1); 466 } 467 468 /** 469 * Allocate shared IB device context. If there is multiport device the 470 * master and representors will share this context, if there is single 471 * port dedicated IB device, the context will be used by only given 472 * port due to unification. 473 * 474 * Routine first searches the context for the specified IB device name, 475 * if found the shared context assumed and reference counter is incremented. 476 * If no context found the new one is created and initialized with specified 477 * IB device context and parameters. 478 * 479 * @param[in] spawn 480 * Pointer to the IB device attributes (name, port, etc). 481 * @param[in] config 482 * Pointer to device configuration structure. 483 * 484 * @return 485 * Pointer to mlx5_ibv_shared object on success, 486 * otherwise NULL and rte_errno is set. 487 */ 488 static struct mlx5_ibv_shared * 489 mlx5_alloc_shared_ibctx(const struct mlx5_dev_spawn_data *spawn, 490 const struct mlx5_dev_config *config) 491 { 492 struct mlx5_ibv_shared *sh; 493 int dbmap_env; 494 int err = 0; 495 uint32_t i; 496 #ifdef HAVE_IBV_FLOW_DV_SUPPORT 497 struct mlx5_devx_tis_attr tis_attr = { 0 }; 498 #endif 499 500 MLX5_ASSERT(spawn); 501 /* Secondary process should not create the shared context. */ 502 MLX5_ASSERT(rte_eal_process_type() == RTE_PROC_PRIMARY); 503 pthread_mutex_lock(&mlx5_ibv_list_mutex); 504 /* Search for IB context by device name. */ 505 LIST_FOREACH(sh, &mlx5_ibv_list, next) { 506 if (!strcmp(sh->ibdev_name, spawn->ibv_dev->name)) { 507 sh->refcnt++; 508 goto exit; 509 } 510 } 511 /* No device found, we have to create new shared context. */ 512 MLX5_ASSERT(spawn->max_port); 513 sh = rte_zmalloc("ethdev shared ib context", 514 sizeof(struct mlx5_ibv_shared) + 515 spawn->max_port * 516 sizeof(struct mlx5_ibv_shared_port), 517 RTE_CACHE_LINE_SIZE); 518 if (!sh) { 519 DRV_LOG(ERR, "shared context allocation failure"); 520 rte_errno = ENOMEM; 521 goto exit; 522 } 523 /* 524 * Configure environment variable "MLX5_BF_SHUT_UP" 525 * before the device creation. The rdma_core library 526 * checks the variable at device creation and 527 * stores the result internally. 528 */ 529 dbmap_env = mlx5_config_doorbell_mapping_env(config); 530 /* Try to open IB device with DV first, then usual Verbs. */ 531 errno = 0; 532 sh->ctx = mlx5_glue->dv_open_device(spawn->ibv_dev); 533 if (sh->ctx) { 534 sh->devx = 1; 535 DRV_LOG(DEBUG, "DevX is supported"); 536 /* The device is created, no need for environment. */ 537 mlx5_restore_doorbell_mapping_env(dbmap_env); 538 } else { 539 /* The environment variable is still configured. */ 540 sh->ctx = mlx5_glue->open_device(spawn->ibv_dev); 541 err = errno ? errno : ENODEV; 542 /* 543 * The environment variable is not needed anymore, 544 * all device creation attempts are completed. 545 */ 546 mlx5_restore_doorbell_mapping_env(dbmap_env); 547 if (!sh->ctx) 548 goto error; 549 DRV_LOG(DEBUG, "DevX is NOT supported"); 550 } 551 err = mlx5_glue->query_device_ex(sh->ctx, NULL, &sh->device_attr); 552 if (err) { 553 DRV_LOG(DEBUG, "ibv_query_device_ex() failed"); 554 goto error; 555 } 556 sh->refcnt = 1; 557 sh->max_port = spawn->max_port; 558 strncpy(sh->ibdev_name, sh->ctx->device->name, 559 sizeof(sh->ibdev_name)); 560 strncpy(sh->ibdev_path, sh->ctx->device->ibdev_path, 561 sizeof(sh->ibdev_path)); 562 pthread_mutex_init(&sh->intr_mutex, NULL); 563 /* 564 * Setting port_id to max unallowed value means 565 * there is no interrupt subhandler installed for 566 * the given port index i. 567 */ 568 for (i = 0; i < sh->max_port; i++) { 569 sh->port[i].ih_port_id = RTE_MAX_ETHPORTS; 570 sh->port[i].devx_ih_port_id = RTE_MAX_ETHPORTS; 571 } 572 sh->pd = mlx5_glue->alloc_pd(sh->ctx); 573 if (sh->pd == NULL) { 574 DRV_LOG(ERR, "PD allocation failure"); 575 err = ENOMEM; 576 goto error; 577 } 578 #ifdef HAVE_IBV_FLOW_DV_SUPPORT 579 if (sh->devx) { 580 err = mlx5_get_pdn(sh->pd, &sh->pdn); 581 if (err) { 582 DRV_LOG(ERR, "Fail to extract pdn from PD"); 583 goto error; 584 } 585 sh->td = mlx5_devx_cmd_create_td(sh->ctx); 586 if (!sh->td) { 587 DRV_LOG(ERR, "TD allocation failure"); 588 err = ENOMEM; 589 goto error; 590 } 591 tis_attr.transport_domain = sh->td->id; 592 sh->tis = mlx5_devx_cmd_create_tis(sh->ctx, &tis_attr); 593 if (!sh->tis) { 594 DRV_LOG(ERR, "TIS allocation failure"); 595 err = ENOMEM; 596 goto error; 597 } 598 } 599 sh->flow_id_pool = mlx5_flow_id_pool_alloc(UINT32_MAX); 600 if (!sh->flow_id_pool) { 601 DRV_LOG(ERR, "can't create flow id pool"); 602 err = ENOMEM; 603 goto error; 604 } 605 #endif /* HAVE_IBV_FLOW_DV_SUPPORT */ 606 /* 607 * Once the device is added to the list of memory event 608 * callback, its global MR cache table cannot be expanded 609 * on the fly because of deadlock. If it overflows, lookup 610 * should be done by searching MR list linearly, which is slow. 611 * 612 * At this point the device is not added to the memory 613 * event list yet, context is just being created. 614 */ 615 err = mlx5_mr_btree_init(&sh->mr.cache, 616 MLX5_MR_BTREE_CACHE_N * 2, 617 spawn->pci_dev->device.numa_node); 618 if (err) { 619 err = rte_errno; 620 goto error; 621 } 622 mlx5_flow_counters_mng_init(sh); 623 /* Add device to memory callback list. */ 624 rte_rwlock_write_lock(&mlx5_shared_data->mem_event_rwlock); 625 LIST_INSERT_HEAD(&mlx5_shared_data->mem_event_cb_list, 626 sh, mem_event_cb); 627 rte_rwlock_write_unlock(&mlx5_shared_data->mem_event_rwlock); 628 /* Add context to the global device list. */ 629 LIST_INSERT_HEAD(&mlx5_ibv_list, sh, next); 630 exit: 631 pthread_mutex_unlock(&mlx5_ibv_list_mutex); 632 return sh; 633 error: 634 pthread_mutex_unlock(&mlx5_ibv_list_mutex); 635 MLX5_ASSERT(sh); 636 if (sh->tis) 637 claim_zero(mlx5_devx_cmd_destroy(sh->tis)); 638 if (sh->td) 639 claim_zero(mlx5_devx_cmd_destroy(sh->td)); 640 if (sh->pd) 641 claim_zero(mlx5_glue->dealloc_pd(sh->pd)); 642 if (sh->ctx) 643 claim_zero(mlx5_glue->close_device(sh->ctx)); 644 if (sh->flow_id_pool) 645 mlx5_flow_id_pool_release(sh->flow_id_pool); 646 rte_free(sh); 647 MLX5_ASSERT(err > 0); 648 rte_errno = err; 649 return NULL; 650 } 651 652 /** 653 * Free shared IB device context. Decrement counter and if zero free 654 * all allocated resources and close handles. 655 * 656 * @param[in] sh 657 * Pointer to mlx5_ibv_shared object to free 658 */ 659 static void 660 mlx5_free_shared_ibctx(struct mlx5_ibv_shared *sh) 661 { 662 pthread_mutex_lock(&mlx5_ibv_list_mutex); 663 #ifdef RTE_LIBRTE_MLX5_DEBUG 664 /* Check the object presence in the list. */ 665 struct mlx5_ibv_shared *lctx; 666 667 LIST_FOREACH(lctx, &mlx5_ibv_list, next) 668 if (lctx == sh) 669 break; 670 MLX5_ASSERT(lctx); 671 if (lctx != sh) { 672 DRV_LOG(ERR, "Freeing non-existing shared IB context"); 673 goto exit; 674 } 675 #endif 676 MLX5_ASSERT(sh); 677 MLX5_ASSERT(sh->refcnt); 678 /* Secondary process should not free the shared context. */ 679 MLX5_ASSERT(rte_eal_process_type() == RTE_PROC_PRIMARY); 680 if (--sh->refcnt) 681 goto exit; 682 /* Remove from memory callback device list. */ 683 rte_rwlock_write_lock(&mlx5_shared_data->mem_event_rwlock); 684 LIST_REMOVE(sh, mem_event_cb); 685 rte_rwlock_write_unlock(&mlx5_shared_data->mem_event_rwlock); 686 /* Release created Memory Regions. */ 687 mlx5_mr_release(sh); 688 /* Remove context from the global device list. */ 689 LIST_REMOVE(sh, next); 690 /* 691 * Ensure there is no async event handler installed. 692 * Only primary process handles async device events. 693 **/ 694 mlx5_flow_counters_mng_close(sh); 695 MLX5_ASSERT(!sh->intr_cnt); 696 if (sh->intr_cnt) 697 mlx5_intr_callback_unregister 698 (&sh->intr_handle, mlx5_dev_interrupt_handler, sh); 699 #ifdef HAVE_MLX5_DEVX_ASYNC_SUPPORT 700 if (sh->devx_intr_cnt) { 701 if (sh->intr_handle_devx.fd) 702 rte_intr_callback_unregister(&sh->intr_handle_devx, 703 mlx5_dev_interrupt_handler_devx, sh); 704 if (sh->devx_comp) 705 mlx5dv_devx_destroy_cmd_comp(sh->devx_comp); 706 } 707 #endif 708 pthread_mutex_destroy(&sh->intr_mutex); 709 if (sh->pd) 710 claim_zero(mlx5_glue->dealloc_pd(sh->pd)); 711 if (sh->tis) 712 claim_zero(mlx5_devx_cmd_destroy(sh->tis)); 713 if (sh->td) 714 claim_zero(mlx5_devx_cmd_destroy(sh->td)); 715 if (sh->ctx) 716 claim_zero(mlx5_glue->close_device(sh->ctx)); 717 if (sh->flow_id_pool) 718 mlx5_flow_id_pool_release(sh->flow_id_pool); 719 rte_free(sh); 720 exit: 721 pthread_mutex_unlock(&mlx5_ibv_list_mutex); 722 } 723 724 /** 725 * Destroy table hash list and all the root entries per domain. 726 * 727 * @param[in] priv 728 * Pointer to the private device data structure. 729 */ 730 static void 731 mlx5_free_table_hash_list(struct mlx5_priv *priv) 732 { 733 struct mlx5_ibv_shared *sh = priv->sh; 734 struct mlx5_flow_tbl_data_entry *tbl_data; 735 union mlx5_flow_tbl_key table_key = { 736 { 737 .table_id = 0, 738 .reserved = 0, 739 .domain = 0, 740 .direction = 0, 741 } 742 }; 743 struct mlx5_hlist_entry *pos; 744 745 if (!sh->flow_tbls) 746 return; 747 pos = mlx5_hlist_lookup(sh->flow_tbls, table_key.v64); 748 if (pos) { 749 tbl_data = container_of(pos, struct mlx5_flow_tbl_data_entry, 750 entry); 751 MLX5_ASSERT(tbl_data); 752 mlx5_hlist_remove(sh->flow_tbls, pos); 753 rte_free(tbl_data); 754 } 755 table_key.direction = 1; 756 pos = mlx5_hlist_lookup(sh->flow_tbls, table_key.v64); 757 if (pos) { 758 tbl_data = container_of(pos, struct mlx5_flow_tbl_data_entry, 759 entry); 760 MLX5_ASSERT(tbl_data); 761 mlx5_hlist_remove(sh->flow_tbls, pos); 762 rte_free(tbl_data); 763 } 764 table_key.direction = 0; 765 table_key.domain = 1; 766 pos = mlx5_hlist_lookup(sh->flow_tbls, table_key.v64); 767 if (pos) { 768 tbl_data = container_of(pos, struct mlx5_flow_tbl_data_entry, 769 entry); 770 MLX5_ASSERT(tbl_data); 771 mlx5_hlist_remove(sh->flow_tbls, pos); 772 rte_free(tbl_data); 773 } 774 mlx5_hlist_destroy(sh->flow_tbls, NULL, NULL); 775 } 776 777 /** 778 * Initialize flow table hash list and create the root tables entry 779 * for each domain. 780 * 781 * @param[in] priv 782 * Pointer to the private device data structure. 783 * 784 * @return 785 * Zero on success, positive error code otherwise. 786 */ 787 static int 788 mlx5_alloc_table_hash_list(struct mlx5_priv *priv) 789 { 790 struct mlx5_ibv_shared *sh = priv->sh; 791 char s[MLX5_HLIST_NAMESIZE]; 792 int err = 0; 793 794 MLX5_ASSERT(sh); 795 snprintf(s, sizeof(s), "%s_flow_table", priv->sh->ibdev_name); 796 sh->flow_tbls = mlx5_hlist_create(s, MLX5_FLOW_TABLE_HLIST_ARRAY_SIZE); 797 if (!sh->flow_tbls) { 798 DRV_LOG(ERR, "flow tables with hash creation failed.\n"); 799 err = ENOMEM; 800 return err; 801 } 802 #ifndef HAVE_MLX5DV_DR 803 /* 804 * In case we have not DR support, the zero tables should be created 805 * because DV expect to see them even if they cannot be created by 806 * RDMA-CORE. 807 */ 808 union mlx5_flow_tbl_key table_key = { 809 { 810 .table_id = 0, 811 .reserved = 0, 812 .domain = 0, 813 .direction = 0, 814 } 815 }; 816 struct mlx5_flow_tbl_data_entry *tbl_data = rte_zmalloc(NULL, 817 sizeof(*tbl_data), 0); 818 819 if (!tbl_data) { 820 err = ENOMEM; 821 goto error; 822 } 823 tbl_data->entry.key = table_key.v64; 824 err = mlx5_hlist_insert(sh->flow_tbls, &tbl_data->entry); 825 if (err) 826 goto error; 827 rte_atomic32_init(&tbl_data->tbl.refcnt); 828 rte_atomic32_inc(&tbl_data->tbl.refcnt); 829 table_key.direction = 1; 830 tbl_data = rte_zmalloc(NULL, sizeof(*tbl_data), 0); 831 if (!tbl_data) { 832 err = ENOMEM; 833 goto error; 834 } 835 tbl_data->entry.key = table_key.v64; 836 err = mlx5_hlist_insert(sh->flow_tbls, &tbl_data->entry); 837 if (err) 838 goto error; 839 rte_atomic32_init(&tbl_data->tbl.refcnt); 840 rte_atomic32_inc(&tbl_data->tbl.refcnt); 841 table_key.direction = 0; 842 table_key.domain = 1; 843 tbl_data = rte_zmalloc(NULL, sizeof(*tbl_data), 0); 844 if (!tbl_data) { 845 err = ENOMEM; 846 goto error; 847 } 848 tbl_data->entry.key = table_key.v64; 849 err = mlx5_hlist_insert(sh->flow_tbls, &tbl_data->entry); 850 if (err) 851 goto error; 852 rte_atomic32_init(&tbl_data->tbl.refcnt); 853 rte_atomic32_inc(&tbl_data->tbl.refcnt); 854 return err; 855 error: 856 mlx5_free_table_hash_list(priv); 857 #endif /* HAVE_MLX5DV_DR */ 858 return err; 859 } 860 861 /** 862 * Initialize DR related data within private structure. 863 * Routine checks the reference counter and does actual 864 * resources creation/initialization only if counter is zero. 865 * 866 * @param[in] priv 867 * Pointer to the private device data structure. 868 * 869 * @return 870 * Zero on success, positive error code otherwise. 871 */ 872 static int 873 mlx5_alloc_shared_dr(struct mlx5_priv *priv) 874 { 875 struct mlx5_ibv_shared *sh = priv->sh; 876 char s[MLX5_HLIST_NAMESIZE]; 877 int err = 0; 878 879 if (!sh->flow_tbls) 880 err = mlx5_alloc_table_hash_list(priv); 881 else 882 DRV_LOG(DEBUG, "sh->flow_tbls[%p] already created, reuse\n", 883 (void *)sh->flow_tbls); 884 if (err) 885 return err; 886 /* Create tags hash list table. */ 887 snprintf(s, sizeof(s), "%s_tags", sh->ibdev_name); 888 sh->tag_table = mlx5_hlist_create(s, MLX5_TAGS_HLIST_ARRAY_SIZE); 889 if (!sh->tag_table) { 890 DRV_LOG(ERR, "tags with hash creation failed.\n"); 891 err = ENOMEM; 892 goto error; 893 } 894 #ifdef HAVE_MLX5DV_DR 895 void *domain; 896 897 if (sh->dv_refcnt) { 898 /* Shared DV/DR structures is already initialized. */ 899 sh->dv_refcnt++; 900 priv->dr_shared = 1; 901 return 0; 902 } 903 /* Reference counter is zero, we should initialize structures. */ 904 domain = mlx5_glue->dr_create_domain(sh->ctx, 905 MLX5DV_DR_DOMAIN_TYPE_NIC_RX); 906 if (!domain) { 907 DRV_LOG(ERR, "ingress mlx5dv_dr_create_domain failed"); 908 err = errno; 909 goto error; 910 } 911 sh->rx_domain = domain; 912 domain = mlx5_glue->dr_create_domain(sh->ctx, 913 MLX5DV_DR_DOMAIN_TYPE_NIC_TX); 914 if (!domain) { 915 DRV_LOG(ERR, "egress mlx5dv_dr_create_domain failed"); 916 err = errno; 917 goto error; 918 } 919 pthread_mutex_init(&sh->dv_mutex, NULL); 920 sh->tx_domain = domain; 921 #ifdef HAVE_MLX5DV_DR_ESWITCH 922 if (priv->config.dv_esw_en) { 923 domain = mlx5_glue->dr_create_domain 924 (sh->ctx, MLX5DV_DR_DOMAIN_TYPE_FDB); 925 if (!domain) { 926 DRV_LOG(ERR, "FDB mlx5dv_dr_create_domain failed"); 927 err = errno; 928 goto error; 929 } 930 sh->fdb_domain = domain; 931 sh->esw_drop_action = mlx5_glue->dr_create_flow_action_drop(); 932 } 933 #endif 934 sh->pop_vlan_action = mlx5_glue->dr_create_flow_action_pop_vlan(); 935 #endif /* HAVE_MLX5DV_DR */ 936 sh->dv_refcnt++; 937 priv->dr_shared = 1; 938 return 0; 939 error: 940 /* Rollback the created objects. */ 941 if (sh->rx_domain) { 942 mlx5_glue->dr_destroy_domain(sh->rx_domain); 943 sh->rx_domain = NULL; 944 } 945 if (sh->tx_domain) { 946 mlx5_glue->dr_destroy_domain(sh->tx_domain); 947 sh->tx_domain = NULL; 948 } 949 if (sh->fdb_domain) { 950 mlx5_glue->dr_destroy_domain(sh->fdb_domain); 951 sh->fdb_domain = NULL; 952 } 953 if (sh->esw_drop_action) { 954 mlx5_glue->destroy_flow_action(sh->esw_drop_action); 955 sh->esw_drop_action = NULL; 956 } 957 if (sh->pop_vlan_action) { 958 mlx5_glue->destroy_flow_action(sh->pop_vlan_action); 959 sh->pop_vlan_action = NULL; 960 } 961 if (sh->tag_table) { 962 /* tags should be destroyed with flow before. */ 963 mlx5_hlist_destroy(sh->tag_table, NULL, NULL); 964 sh->tag_table = NULL; 965 } 966 mlx5_free_table_hash_list(priv); 967 return err; 968 } 969 970 /** 971 * Destroy DR related data within private structure. 972 * 973 * @param[in] priv 974 * Pointer to the private device data structure. 975 */ 976 static void 977 mlx5_free_shared_dr(struct mlx5_priv *priv) 978 { 979 struct mlx5_ibv_shared *sh; 980 981 if (!priv->dr_shared) 982 return; 983 priv->dr_shared = 0; 984 sh = priv->sh; 985 MLX5_ASSERT(sh); 986 #ifdef HAVE_MLX5DV_DR 987 MLX5_ASSERT(sh->dv_refcnt); 988 if (sh->dv_refcnt && --sh->dv_refcnt) 989 return; 990 if (sh->rx_domain) { 991 mlx5_glue->dr_destroy_domain(sh->rx_domain); 992 sh->rx_domain = NULL; 993 } 994 if (sh->tx_domain) { 995 mlx5_glue->dr_destroy_domain(sh->tx_domain); 996 sh->tx_domain = NULL; 997 } 998 #ifdef HAVE_MLX5DV_DR_ESWITCH 999 if (sh->fdb_domain) { 1000 mlx5_glue->dr_destroy_domain(sh->fdb_domain); 1001 sh->fdb_domain = NULL; 1002 } 1003 if (sh->esw_drop_action) { 1004 mlx5_glue->destroy_flow_action(sh->esw_drop_action); 1005 sh->esw_drop_action = NULL; 1006 } 1007 #endif 1008 if (sh->pop_vlan_action) { 1009 mlx5_glue->destroy_flow_action(sh->pop_vlan_action); 1010 sh->pop_vlan_action = NULL; 1011 } 1012 pthread_mutex_destroy(&sh->dv_mutex); 1013 #endif /* HAVE_MLX5DV_DR */ 1014 if (sh->tag_table) { 1015 /* tags should be destroyed with flow before. */ 1016 mlx5_hlist_destroy(sh->tag_table, NULL, NULL); 1017 sh->tag_table = NULL; 1018 } 1019 mlx5_free_table_hash_list(priv); 1020 } 1021 1022 /** 1023 * Initialize shared data between primary and secondary process. 1024 * 1025 * A memzone is reserved by primary process and secondary processes attach to 1026 * the memzone. 1027 * 1028 * @return 1029 * 0 on success, a negative errno value otherwise and rte_errno is set. 1030 */ 1031 static int 1032 mlx5_init_shared_data(void) 1033 { 1034 const struct rte_memzone *mz; 1035 int ret = 0; 1036 1037 rte_spinlock_lock(&mlx5_shared_data_lock); 1038 if (mlx5_shared_data == NULL) { 1039 if (rte_eal_process_type() == RTE_PROC_PRIMARY) { 1040 /* Allocate shared memory. */ 1041 mz = rte_memzone_reserve(MZ_MLX5_PMD_SHARED_DATA, 1042 sizeof(*mlx5_shared_data), 1043 SOCKET_ID_ANY, 0); 1044 if (mz == NULL) { 1045 DRV_LOG(ERR, 1046 "Cannot allocate mlx5 shared data"); 1047 ret = -rte_errno; 1048 goto error; 1049 } 1050 mlx5_shared_data = mz->addr; 1051 memset(mlx5_shared_data, 0, sizeof(*mlx5_shared_data)); 1052 rte_spinlock_init(&mlx5_shared_data->lock); 1053 } else { 1054 /* Lookup allocated shared memory. */ 1055 mz = rte_memzone_lookup(MZ_MLX5_PMD_SHARED_DATA); 1056 if (mz == NULL) { 1057 DRV_LOG(ERR, 1058 "Cannot attach mlx5 shared data"); 1059 ret = -rte_errno; 1060 goto error; 1061 } 1062 mlx5_shared_data = mz->addr; 1063 memset(&mlx5_local_data, 0, sizeof(mlx5_local_data)); 1064 } 1065 } 1066 error: 1067 rte_spinlock_unlock(&mlx5_shared_data_lock); 1068 return ret; 1069 } 1070 1071 /** 1072 * Retrieve integer value from environment variable. 1073 * 1074 * @param[in] name 1075 * Environment variable name. 1076 * 1077 * @return 1078 * Integer value, 0 if the variable is not set. 1079 */ 1080 int 1081 mlx5_getenv_int(const char *name) 1082 { 1083 const char *val = getenv(name); 1084 1085 if (val == NULL) 1086 return 0; 1087 return atoi(val); 1088 } 1089 1090 /** 1091 * Verbs callback to allocate a memory. This function should allocate the space 1092 * according to the size provided residing inside a huge page. 1093 * Please note that all allocation must respect the alignment from libmlx5 1094 * (i.e. currently sysconf(_SC_PAGESIZE)). 1095 * 1096 * @param[in] size 1097 * The size in bytes of the memory to allocate. 1098 * @param[in] data 1099 * A pointer to the callback data. 1100 * 1101 * @return 1102 * Allocated buffer, NULL otherwise and rte_errno is set. 1103 */ 1104 static void * 1105 mlx5_alloc_verbs_buf(size_t size, void *data) 1106 { 1107 struct mlx5_priv *priv = data; 1108 void *ret; 1109 size_t alignment = sysconf(_SC_PAGESIZE); 1110 unsigned int socket = SOCKET_ID_ANY; 1111 1112 if (priv->verbs_alloc_ctx.type == MLX5_VERBS_ALLOC_TYPE_TX_QUEUE) { 1113 const struct mlx5_txq_ctrl *ctrl = priv->verbs_alloc_ctx.obj; 1114 1115 socket = ctrl->socket; 1116 } else if (priv->verbs_alloc_ctx.type == 1117 MLX5_VERBS_ALLOC_TYPE_RX_QUEUE) { 1118 const struct mlx5_rxq_ctrl *ctrl = priv->verbs_alloc_ctx.obj; 1119 1120 socket = ctrl->socket; 1121 } 1122 MLX5_ASSERT(data != NULL); 1123 ret = rte_malloc_socket(__func__, size, alignment, socket); 1124 if (!ret && size) 1125 rte_errno = ENOMEM; 1126 return ret; 1127 } 1128 1129 /** 1130 * Verbs callback to free a memory. 1131 * 1132 * @param[in] ptr 1133 * A pointer to the memory to free. 1134 * @param[in] data 1135 * A pointer to the callback data. 1136 */ 1137 static void 1138 mlx5_free_verbs_buf(void *ptr, void *data __rte_unused) 1139 { 1140 MLX5_ASSERT(data != NULL); 1141 rte_free(ptr); 1142 } 1143 1144 /** 1145 * DPDK callback to add udp tunnel port 1146 * 1147 * @param[in] dev 1148 * A pointer to eth_dev 1149 * @param[in] udp_tunnel 1150 * A pointer to udp tunnel 1151 * 1152 * @return 1153 * 0 on valid udp ports and tunnels, -ENOTSUP otherwise. 1154 */ 1155 int 1156 mlx5_udp_tunnel_port_add(struct rte_eth_dev *dev __rte_unused, 1157 struct rte_eth_udp_tunnel *udp_tunnel) 1158 { 1159 MLX5_ASSERT(udp_tunnel != NULL); 1160 if (udp_tunnel->prot_type == RTE_TUNNEL_TYPE_VXLAN && 1161 udp_tunnel->udp_port == 4789) 1162 return 0; 1163 if (udp_tunnel->prot_type == RTE_TUNNEL_TYPE_VXLAN_GPE && 1164 udp_tunnel->udp_port == 4790) 1165 return 0; 1166 return -ENOTSUP; 1167 } 1168 1169 /** 1170 * Initialize process private data structure. 1171 * 1172 * @param dev 1173 * Pointer to Ethernet device structure. 1174 * 1175 * @return 1176 * 0 on success, a negative errno value otherwise and rte_errno is set. 1177 */ 1178 int 1179 mlx5_proc_priv_init(struct rte_eth_dev *dev) 1180 { 1181 struct mlx5_priv *priv = dev->data->dev_private; 1182 struct mlx5_proc_priv *ppriv; 1183 size_t ppriv_size; 1184 1185 /* 1186 * UAR register table follows the process private structure. BlueFlame 1187 * registers for Tx queues are stored in the table. 1188 */ 1189 ppriv_size = 1190 sizeof(struct mlx5_proc_priv) + priv->txqs_n * sizeof(void *); 1191 ppriv = rte_malloc_socket("mlx5_proc_priv", ppriv_size, 1192 RTE_CACHE_LINE_SIZE, dev->device->numa_node); 1193 if (!ppriv) { 1194 rte_errno = ENOMEM; 1195 return -rte_errno; 1196 } 1197 ppriv->uar_table_sz = ppriv_size; 1198 dev->process_private = ppriv; 1199 return 0; 1200 } 1201 1202 /** 1203 * Un-initialize process private data structure. 1204 * 1205 * @param dev 1206 * Pointer to Ethernet device structure. 1207 */ 1208 static void 1209 mlx5_proc_priv_uninit(struct rte_eth_dev *dev) 1210 { 1211 if (!dev->process_private) 1212 return; 1213 rte_free(dev->process_private); 1214 dev->process_private = NULL; 1215 } 1216 1217 /** 1218 * DPDK callback to close the device. 1219 * 1220 * Destroy all queues and objects, free memory. 1221 * 1222 * @param dev 1223 * Pointer to Ethernet device structure. 1224 */ 1225 static void 1226 mlx5_dev_close(struct rte_eth_dev *dev) 1227 { 1228 struct mlx5_priv *priv = dev->data->dev_private; 1229 unsigned int i; 1230 int ret; 1231 1232 DRV_LOG(DEBUG, "port %u closing device \"%s\"", 1233 dev->data->port_id, 1234 ((priv->sh->ctx != NULL) ? priv->sh->ctx->device->name : "")); 1235 /* In case mlx5_dev_stop() has not been called. */ 1236 mlx5_dev_interrupt_handler_uninstall(dev); 1237 mlx5_dev_interrupt_handler_devx_uninstall(dev); 1238 mlx5_traffic_disable(dev); 1239 mlx5_flow_flush(dev, NULL); 1240 mlx5_flow_meter_flush(dev, NULL); 1241 /* Prevent crashes when queues are still in use. */ 1242 dev->rx_pkt_burst = removed_rx_burst; 1243 dev->tx_pkt_burst = removed_tx_burst; 1244 rte_wmb(); 1245 /* Disable datapath on secondary process. */ 1246 mlx5_mp_req_stop_rxtx(dev); 1247 if (priv->rxqs != NULL) { 1248 /* XXX race condition if mlx5_rx_burst() is still running. */ 1249 usleep(1000); 1250 for (i = 0; (i != priv->rxqs_n); ++i) 1251 mlx5_rxq_release(dev, i); 1252 priv->rxqs_n = 0; 1253 priv->rxqs = NULL; 1254 } 1255 if (priv->txqs != NULL) { 1256 /* XXX race condition if mlx5_tx_burst() is still running. */ 1257 usleep(1000); 1258 for (i = 0; (i != priv->txqs_n); ++i) 1259 mlx5_txq_release(dev, i); 1260 priv->txqs_n = 0; 1261 priv->txqs = NULL; 1262 } 1263 mlx5_proc_priv_uninit(dev); 1264 if (priv->mreg_cp_tbl) 1265 mlx5_hlist_destroy(priv->mreg_cp_tbl, NULL, NULL); 1266 mlx5_mprq_free_mp(dev); 1267 mlx5_free_shared_dr(priv); 1268 if (priv->rss_conf.rss_key != NULL) 1269 rte_free(priv->rss_conf.rss_key); 1270 if (priv->reta_idx != NULL) 1271 rte_free(priv->reta_idx); 1272 if (priv->config.vf) 1273 mlx5_nl_mac_addr_flush(priv->nl_socket_route, mlx5_ifindex(dev), 1274 dev->data->mac_addrs, 1275 MLX5_MAX_MAC_ADDRESSES, priv->mac_own); 1276 if (priv->nl_socket_route >= 0) 1277 close(priv->nl_socket_route); 1278 if (priv->nl_socket_rdma >= 0) 1279 close(priv->nl_socket_rdma); 1280 if (priv->vmwa_context) 1281 mlx5_vlan_vmwa_exit(priv->vmwa_context); 1282 if (priv->sh) { 1283 /* 1284 * Free the shared context in last turn, because the cleanup 1285 * routines above may use some shared fields, like 1286 * mlx5_nl_mac_addr_flush() uses ibdev_path for retrieveing 1287 * ifindex if Netlink fails. 1288 */ 1289 mlx5_free_shared_ibctx(priv->sh); 1290 priv->sh = NULL; 1291 } 1292 ret = mlx5_hrxq_verify(dev); 1293 if (ret) 1294 DRV_LOG(WARNING, "port %u some hash Rx queue still remain", 1295 dev->data->port_id); 1296 ret = mlx5_ind_table_obj_verify(dev); 1297 if (ret) 1298 DRV_LOG(WARNING, "port %u some indirection table still remain", 1299 dev->data->port_id); 1300 ret = mlx5_rxq_obj_verify(dev); 1301 if (ret) 1302 DRV_LOG(WARNING, "port %u some Rx queue objects still remain", 1303 dev->data->port_id); 1304 ret = mlx5_rxq_verify(dev); 1305 if (ret) 1306 DRV_LOG(WARNING, "port %u some Rx queues still remain", 1307 dev->data->port_id); 1308 ret = mlx5_txq_obj_verify(dev); 1309 if (ret) 1310 DRV_LOG(WARNING, "port %u some Verbs Tx queue still remain", 1311 dev->data->port_id); 1312 ret = mlx5_txq_verify(dev); 1313 if (ret) 1314 DRV_LOG(WARNING, "port %u some Tx queues still remain", 1315 dev->data->port_id); 1316 ret = mlx5_flow_verify(dev); 1317 if (ret) 1318 DRV_LOG(WARNING, "port %u some flows still remain", 1319 dev->data->port_id); 1320 if (priv->domain_id != RTE_ETH_DEV_SWITCH_DOMAIN_ID_INVALID) { 1321 unsigned int c = 0; 1322 uint16_t port_id; 1323 1324 MLX5_ETH_FOREACH_DEV(port_id, priv->pci_dev) { 1325 struct mlx5_priv *opriv = 1326 rte_eth_devices[port_id].data->dev_private; 1327 1328 if (!opriv || 1329 opriv->domain_id != priv->domain_id || 1330 &rte_eth_devices[port_id] == dev) 1331 continue; 1332 ++c; 1333 break; 1334 } 1335 if (!c) 1336 claim_zero(rte_eth_switch_domain_free(priv->domain_id)); 1337 } 1338 memset(priv, 0, sizeof(*priv)); 1339 priv->domain_id = RTE_ETH_DEV_SWITCH_DOMAIN_ID_INVALID; 1340 /* 1341 * Reset mac_addrs to NULL such that it is not freed as part of 1342 * rte_eth_dev_release_port(). mac_addrs is part of dev_private so 1343 * it is freed when dev_private is freed. 1344 */ 1345 dev->data->mac_addrs = NULL; 1346 } 1347 1348 const struct eth_dev_ops mlx5_dev_ops = { 1349 .dev_configure = mlx5_dev_configure, 1350 .dev_start = mlx5_dev_start, 1351 .dev_stop = mlx5_dev_stop, 1352 .dev_set_link_down = mlx5_set_link_down, 1353 .dev_set_link_up = mlx5_set_link_up, 1354 .dev_close = mlx5_dev_close, 1355 .promiscuous_enable = mlx5_promiscuous_enable, 1356 .promiscuous_disable = mlx5_promiscuous_disable, 1357 .allmulticast_enable = mlx5_allmulticast_enable, 1358 .allmulticast_disable = mlx5_allmulticast_disable, 1359 .link_update = mlx5_link_update, 1360 .stats_get = mlx5_stats_get, 1361 .stats_reset = mlx5_stats_reset, 1362 .xstats_get = mlx5_xstats_get, 1363 .xstats_reset = mlx5_xstats_reset, 1364 .xstats_get_names = mlx5_xstats_get_names, 1365 .fw_version_get = mlx5_fw_version_get, 1366 .dev_infos_get = mlx5_dev_infos_get, 1367 .read_clock = mlx5_read_clock, 1368 .dev_supported_ptypes_get = mlx5_dev_supported_ptypes_get, 1369 .vlan_filter_set = mlx5_vlan_filter_set, 1370 .rx_queue_setup = mlx5_rx_queue_setup, 1371 .rx_hairpin_queue_setup = mlx5_rx_hairpin_queue_setup, 1372 .tx_queue_setup = mlx5_tx_queue_setup, 1373 .tx_hairpin_queue_setup = mlx5_tx_hairpin_queue_setup, 1374 .rx_queue_release = mlx5_rx_queue_release, 1375 .tx_queue_release = mlx5_tx_queue_release, 1376 .flow_ctrl_get = mlx5_dev_get_flow_ctrl, 1377 .flow_ctrl_set = mlx5_dev_set_flow_ctrl, 1378 .mac_addr_remove = mlx5_mac_addr_remove, 1379 .mac_addr_add = mlx5_mac_addr_add, 1380 .mac_addr_set = mlx5_mac_addr_set, 1381 .set_mc_addr_list = mlx5_set_mc_addr_list, 1382 .mtu_set = mlx5_dev_set_mtu, 1383 .vlan_strip_queue_set = mlx5_vlan_strip_queue_set, 1384 .vlan_offload_set = mlx5_vlan_offload_set, 1385 .reta_update = mlx5_dev_rss_reta_update, 1386 .reta_query = mlx5_dev_rss_reta_query, 1387 .rss_hash_update = mlx5_rss_hash_update, 1388 .rss_hash_conf_get = mlx5_rss_hash_conf_get, 1389 .filter_ctrl = mlx5_dev_filter_ctrl, 1390 .rx_descriptor_status = mlx5_rx_descriptor_status, 1391 .tx_descriptor_status = mlx5_tx_descriptor_status, 1392 .rxq_info_get = mlx5_rxq_info_get, 1393 .txq_info_get = mlx5_txq_info_get, 1394 .rx_burst_mode_get = mlx5_rx_burst_mode_get, 1395 .tx_burst_mode_get = mlx5_tx_burst_mode_get, 1396 .rx_queue_count = mlx5_rx_queue_count, 1397 .rx_queue_intr_enable = mlx5_rx_intr_enable, 1398 .rx_queue_intr_disable = mlx5_rx_intr_disable, 1399 .is_removed = mlx5_is_removed, 1400 .udp_tunnel_port_add = mlx5_udp_tunnel_port_add, 1401 .get_module_info = mlx5_get_module_info, 1402 .get_module_eeprom = mlx5_get_module_eeprom, 1403 .hairpin_cap_get = mlx5_hairpin_cap_get, 1404 .mtr_ops_get = mlx5_flow_meter_ops_get, 1405 }; 1406 1407 /* Available operations from secondary process. */ 1408 static const struct eth_dev_ops mlx5_dev_sec_ops = { 1409 .stats_get = mlx5_stats_get, 1410 .stats_reset = mlx5_stats_reset, 1411 .xstats_get = mlx5_xstats_get, 1412 .xstats_reset = mlx5_xstats_reset, 1413 .xstats_get_names = mlx5_xstats_get_names, 1414 .fw_version_get = mlx5_fw_version_get, 1415 .dev_infos_get = mlx5_dev_infos_get, 1416 .rx_descriptor_status = mlx5_rx_descriptor_status, 1417 .tx_descriptor_status = mlx5_tx_descriptor_status, 1418 .rxq_info_get = mlx5_rxq_info_get, 1419 .txq_info_get = mlx5_txq_info_get, 1420 .rx_burst_mode_get = mlx5_rx_burst_mode_get, 1421 .tx_burst_mode_get = mlx5_tx_burst_mode_get, 1422 .get_module_info = mlx5_get_module_info, 1423 .get_module_eeprom = mlx5_get_module_eeprom, 1424 }; 1425 1426 /* Available operations in flow isolated mode. */ 1427 const struct eth_dev_ops mlx5_dev_ops_isolate = { 1428 .dev_configure = mlx5_dev_configure, 1429 .dev_start = mlx5_dev_start, 1430 .dev_stop = mlx5_dev_stop, 1431 .dev_set_link_down = mlx5_set_link_down, 1432 .dev_set_link_up = mlx5_set_link_up, 1433 .dev_close = mlx5_dev_close, 1434 .promiscuous_enable = mlx5_promiscuous_enable, 1435 .promiscuous_disable = mlx5_promiscuous_disable, 1436 .allmulticast_enable = mlx5_allmulticast_enable, 1437 .allmulticast_disable = mlx5_allmulticast_disable, 1438 .link_update = mlx5_link_update, 1439 .stats_get = mlx5_stats_get, 1440 .stats_reset = mlx5_stats_reset, 1441 .xstats_get = mlx5_xstats_get, 1442 .xstats_reset = mlx5_xstats_reset, 1443 .xstats_get_names = mlx5_xstats_get_names, 1444 .fw_version_get = mlx5_fw_version_get, 1445 .dev_infos_get = mlx5_dev_infos_get, 1446 .dev_supported_ptypes_get = mlx5_dev_supported_ptypes_get, 1447 .vlan_filter_set = mlx5_vlan_filter_set, 1448 .rx_queue_setup = mlx5_rx_queue_setup, 1449 .rx_hairpin_queue_setup = mlx5_rx_hairpin_queue_setup, 1450 .tx_queue_setup = mlx5_tx_queue_setup, 1451 .tx_hairpin_queue_setup = mlx5_tx_hairpin_queue_setup, 1452 .rx_queue_release = mlx5_rx_queue_release, 1453 .tx_queue_release = mlx5_tx_queue_release, 1454 .flow_ctrl_get = mlx5_dev_get_flow_ctrl, 1455 .flow_ctrl_set = mlx5_dev_set_flow_ctrl, 1456 .mac_addr_remove = mlx5_mac_addr_remove, 1457 .mac_addr_add = mlx5_mac_addr_add, 1458 .mac_addr_set = mlx5_mac_addr_set, 1459 .set_mc_addr_list = mlx5_set_mc_addr_list, 1460 .mtu_set = mlx5_dev_set_mtu, 1461 .vlan_strip_queue_set = mlx5_vlan_strip_queue_set, 1462 .vlan_offload_set = mlx5_vlan_offload_set, 1463 .filter_ctrl = mlx5_dev_filter_ctrl, 1464 .rx_descriptor_status = mlx5_rx_descriptor_status, 1465 .tx_descriptor_status = mlx5_tx_descriptor_status, 1466 .rxq_info_get = mlx5_rxq_info_get, 1467 .txq_info_get = mlx5_txq_info_get, 1468 .rx_burst_mode_get = mlx5_rx_burst_mode_get, 1469 .tx_burst_mode_get = mlx5_tx_burst_mode_get, 1470 .rx_queue_intr_enable = mlx5_rx_intr_enable, 1471 .rx_queue_intr_disable = mlx5_rx_intr_disable, 1472 .is_removed = mlx5_is_removed, 1473 .get_module_info = mlx5_get_module_info, 1474 .get_module_eeprom = mlx5_get_module_eeprom, 1475 .hairpin_cap_get = mlx5_hairpin_cap_get, 1476 .mtr_ops_get = mlx5_flow_meter_ops_get, 1477 }; 1478 1479 /** 1480 * Verify and store value for device argument. 1481 * 1482 * @param[in] key 1483 * Key argument to verify. 1484 * @param[in] val 1485 * Value associated with key. 1486 * @param opaque 1487 * User data. 1488 * 1489 * @return 1490 * 0 on success, a negative errno value otherwise and rte_errno is set. 1491 */ 1492 static int 1493 mlx5_args_check(const char *key, const char *val, void *opaque) 1494 { 1495 struct mlx5_dev_config *config = opaque; 1496 unsigned long tmp; 1497 1498 /* No-op, port representors are processed in mlx5_dev_spawn(). */ 1499 if (!strcmp(MLX5_REPRESENTOR, key)) 1500 return 0; 1501 errno = 0; 1502 tmp = strtoul(val, NULL, 0); 1503 if (errno) { 1504 rte_errno = errno; 1505 DRV_LOG(WARNING, "%s: \"%s\" is not a valid integer", key, val); 1506 return -rte_errno; 1507 } 1508 if (strcmp(MLX5_RXQ_CQE_COMP_EN, key) == 0) { 1509 config->cqe_comp = !!tmp; 1510 } else if (strcmp(MLX5_RXQ_CQE_PAD_EN, key) == 0) { 1511 config->cqe_pad = !!tmp; 1512 } else if (strcmp(MLX5_RXQ_PKT_PAD_EN, key) == 0) { 1513 config->hw_padding = !!tmp; 1514 } else if (strcmp(MLX5_RX_MPRQ_EN, key) == 0) { 1515 config->mprq.enabled = !!tmp; 1516 } else if (strcmp(MLX5_RX_MPRQ_LOG_STRIDE_NUM, key) == 0) { 1517 config->mprq.stride_num_n = tmp; 1518 } else if (strcmp(MLX5_RX_MPRQ_MAX_MEMCPY_LEN, key) == 0) { 1519 config->mprq.max_memcpy_len = tmp; 1520 } else if (strcmp(MLX5_RXQS_MIN_MPRQ, key) == 0) { 1521 config->mprq.min_rxqs_num = tmp; 1522 } else if (strcmp(MLX5_TXQ_INLINE, key) == 0) { 1523 DRV_LOG(WARNING, "%s: deprecated parameter," 1524 " converted to txq_inline_max", key); 1525 config->txq_inline_max = tmp; 1526 } else if (strcmp(MLX5_TXQ_INLINE_MAX, key) == 0) { 1527 config->txq_inline_max = tmp; 1528 } else if (strcmp(MLX5_TXQ_INLINE_MIN, key) == 0) { 1529 config->txq_inline_min = tmp; 1530 } else if (strcmp(MLX5_TXQ_INLINE_MPW, key) == 0) { 1531 config->txq_inline_mpw = tmp; 1532 } else if (strcmp(MLX5_TXQS_MIN_INLINE, key) == 0) { 1533 config->txqs_inline = tmp; 1534 } else if (strcmp(MLX5_TXQS_MAX_VEC, key) == 0) { 1535 DRV_LOG(WARNING, "%s: deprecated parameter, ignored", key); 1536 } else if (strcmp(MLX5_TXQ_MPW_EN, key) == 0) { 1537 config->mps = !!tmp; 1538 } else if (strcmp(MLX5_TX_DB_NC, key) == 0) { 1539 if (tmp != MLX5_TXDB_CACHED && 1540 tmp != MLX5_TXDB_NCACHED && 1541 tmp != MLX5_TXDB_HEURISTIC) { 1542 DRV_LOG(ERR, "invalid Tx doorbell " 1543 "mapping parameter"); 1544 rte_errno = EINVAL; 1545 return -rte_errno; 1546 } 1547 config->dbnc = tmp; 1548 } else if (strcmp(MLX5_TXQ_MPW_HDR_DSEG_EN, key) == 0) { 1549 DRV_LOG(WARNING, "%s: deprecated parameter, ignored", key); 1550 } else if (strcmp(MLX5_TXQ_MAX_INLINE_LEN, key) == 0) { 1551 DRV_LOG(WARNING, "%s: deprecated parameter," 1552 " converted to txq_inline_mpw", key); 1553 config->txq_inline_mpw = tmp; 1554 } else if (strcmp(MLX5_TX_VEC_EN, key) == 0) { 1555 DRV_LOG(WARNING, "%s: deprecated parameter, ignored", key); 1556 } else if (strcmp(MLX5_RX_VEC_EN, key) == 0) { 1557 config->rx_vec_en = !!tmp; 1558 } else if (strcmp(MLX5_L3_VXLAN_EN, key) == 0) { 1559 config->l3_vxlan_en = !!tmp; 1560 } else if (strcmp(MLX5_VF_NL_EN, key) == 0) { 1561 config->vf_nl_en = !!tmp; 1562 } else if (strcmp(MLX5_DV_ESW_EN, key) == 0) { 1563 config->dv_esw_en = !!tmp; 1564 } else if (strcmp(MLX5_DV_FLOW_EN, key) == 0) { 1565 config->dv_flow_en = !!tmp; 1566 } else if (strcmp(MLX5_DV_XMETA_EN, key) == 0) { 1567 if (tmp != MLX5_XMETA_MODE_LEGACY && 1568 tmp != MLX5_XMETA_MODE_META16 && 1569 tmp != MLX5_XMETA_MODE_META32) { 1570 DRV_LOG(ERR, "invalid extensive " 1571 "metadata parameter"); 1572 rte_errno = EINVAL; 1573 return -rte_errno; 1574 } 1575 config->dv_xmeta_en = tmp; 1576 } else if (strcmp(MLX5_MR_EXT_MEMSEG_EN, key) == 0) { 1577 config->mr_ext_memseg_en = !!tmp; 1578 } else if (strcmp(MLX5_MAX_DUMP_FILES_NUM, key) == 0) { 1579 config->max_dump_files_num = tmp; 1580 } else if (strcmp(MLX5_LRO_TIMEOUT_USEC, key) == 0) { 1581 config->lro.timeout = tmp; 1582 } else if (strcmp(MLX5_CLASS_ARG_NAME, key) == 0) { 1583 DRV_LOG(DEBUG, "class argument is %s.", val); 1584 } else { 1585 DRV_LOG(WARNING, "%s: unknown parameter", key); 1586 rte_errno = EINVAL; 1587 return -rte_errno; 1588 } 1589 return 0; 1590 } 1591 1592 /** 1593 * Parse device parameters. 1594 * 1595 * @param config 1596 * Pointer to device configuration structure. 1597 * @param devargs 1598 * Device arguments structure. 1599 * 1600 * @return 1601 * 0 on success, a negative errno value otherwise and rte_errno is set. 1602 */ 1603 static int 1604 mlx5_args(struct mlx5_dev_config *config, struct rte_devargs *devargs) 1605 { 1606 const char **params = (const char *[]){ 1607 MLX5_RXQ_CQE_COMP_EN, 1608 MLX5_RXQ_CQE_PAD_EN, 1609 MLX5_RXQ_PKT_PAD_EN, 1610 MLX5_RX_MPRQ_EN, 1611 MLX5_RX_MPRQ_LOG_STRIDE_NUM, 1612 MLX5_RX_MPRQ_MAX_MEMCPY_LEN, 1613 MLX5_RXQS_MIN_MPRQ, 1614 MLX5_TXQ_INLINE, 1615 MLX5_TXQ_INLINE_MIN, 1616 MLX5_TXQ_INLINE_MAX, 1617 MLX5_TXQ_INLINE_MPW, 1618 MLX5_TXQS_MIN_INLINE, 1619 MLX5_TXQS_MAX_VEC, 1620 MLX5_TXQ_MPW_EN, 1621 MLX5_TXQ_MPW_HDR_DSEG_EN, 1622 MLX5_TXQ_MAX_INLINE_LEN, 1623 MLX5_TX_DB_NC, 1624 MLX5_TX_VEC_EN, 1625 MLX5_RX_VEC_EN, 1626 MLX5_L3_VXLAN_EN, 1627 MLX5_VF_NL_EN, 1628 MLX5_DV_ESW_EN, 1629 MLX5_DV_FLOW_EN, 1630 MLX5_DV_XMETA_EN, 1631 MLX5_MR_EXT_MEMSEG_EN, 1632 MLX5_REPRESENTOR, 1633 MLX5_MAX_DUMP_FILES_NUM, 1634 MLX5_LRO_TIMEOUT_USEC, 1635 MLX5_CLASS_ARG_NAME, 1636 NULL, 1637 }; 1638 struct rte_kvargs *kvlist; 1639 int ret = 0; 1640 int i; 1641 1642 if (devargs == NULL) 1643 return 0; 1644 /* Following UGLY cast is done to pass checkpatch. */ 1645 kvlist = rte_kvargs_parse(devargs->args, params); 1646 if (kvlist == NULL) { 1647 rte_errno = EINVAL; 1648 return -rte_errno; 1649 } 1650 /* Process parameters. */ 1651 for (i = 0; (params[i] != NULL); ++i) { 1652 if (rte_kvargs_count(kvlist, params[i])) { 1653 ret = rte_kvargs_process(kvlist, params[i], 1654 mlx5_args_check, config); 1655 if (ret) { 1656 rte_errno = EINVAL; 1657 rte_kvargs_free(kvlist); 1658 return -rte_errno; 1659 } 1660 } 1661 } 1662 rte_kvargs_free(kvlist); 1663 return 0; 1664 } 1665 1666 static struct rte_pci_driver mlx5_driver; 1667 1668 /** 1669 * PMD global initialization. 1670 * 1671 * Independent from individual device, this function initializes global 1672 * per-PMD data structures distinguishing primary and secondary processes. 1673 * Hence, each initialization is called once per a process. 1674 * 1675 * @return 1676 * 0 on success, a negative errno value otherwise and rte_errno is set. 1677 */ 1678 static int 1679 mlx5_init_once(void) 1680 { 1681 struct mlx5_shared_data *sd; 1682 struct mlx5_local_data *ld = &mlx5_local_data; 1683 int ret = 0; 1684 1685 if (mlx5_init_shared_data()) 1686 return -rte_errno; 1687 sd = mlx5_shared_data; 1688 MLX5_ASSERT(sd); 1689 rte_spinlock_lock(&sd->lock); 1690 switch (rte_eal_process_type()) { 1691 case RTE_PROC_PRIMARY: 1692 if (sd->init_done) 1693 break; 1694 LIST_INIT(&sd->mem_event_cb_list); 1695 rte_rwlock_init(&sd->mem_event_rwlock); 1696 rte_mem_event_callback_register("MLX5_MEM_EVENT_CB", 1697 mlx5_mr_mem_event_cb, NULL); 1698 ret = mlx5_mp_init_primary(); 1699 if (ret) 1700 goto out; 1701 sd->init_done = true; 1702 break; 1703 case RTE_PROC_SECONDARY: 1704 if (ld->init_done) 1705 break; 1706 ret = mlx5_mp_init_secondary(); 1707 if (ret) 1708 goto out; 1709 ++sd->secondary_cnt; 1710 ld->init_done = true; 1711 break; 1712 default: 1713 break; 1714 } 1715 out: 1716 rte_spinlock_unlock(&sd->lock); 1717 return ret; 1718 } 1719 1720 /** 1721 * Configures the minimal amount of data to inline into WQE 1722 * while sending packets. 1723 * 1724 * - the txq_inline_min has the maximal priority, if this 1725 * key is specified in devargs 1726 * - if DevX is enabled the inline mode is queried from the 1727 * device (HCA attributes and NIC vport context if needed). 1728 * - otherwise L2 mode (18 bytes) is assumed for ConnectX-4/4LX 1729 * and none (0 bytes) for other NICs 1730 * 1731 * @param spawn 1732 * Verbs device parameters (name, port, switch_info) to spawn. 1733 * @param config 1734 * Device configuration parameters. 1735 */ 1736 static void 1737 mlx5_set_min_inline(struct mlx5_dev_spawn_data *spawn, 1738 struct mlx5_dev_config *config) 1739 { 1740 if (config->txq_inline_min != MLX5_ARG_UNSET) { 1741 /* Application defines size of inlined data explicitly. */ 1742 switch (spawn->pci_dev->id.device_id) { 1743 case PCI_DEVICE_ID_MELLANOX_CONNECTX4: 1744 case PCI_DEVICE_ID_MELLANOX_CONNECTX4VF: 1745 if (config->txq_inline_min < 1746 (int)MLX5_INLINE_HSIZE_L2) { 1747 DRV_LOG(DEBUG, 1748 "txq_inline_mix aligned to minimal" 1749 " ConnectX-4 required value %d", 1750 (int)MLX5_INLINE_HSIZE_L2); 1751 config->txq_inline_min = MLX5_INLINE_HSIZE_L2; 1752 } 1753 break; 1754 } 1755 goto exit; 1756 } 1757 if (config->hca_attr.eth_net_offloads) { 1758 /* We have DevX enabled, inline mode queried successfully. */ 1759 switch (config->hca_attr.wqe_inline_mode) { 1760 case MLX5_CAP_INLINE_MODE_L2: 1761 /* outer L2 header must be inlined. */ 1762 config->txq_inline_min = MLX5_INLINE_HSIZE_L2; 1763 goto exit; 1764 case MLX5_CAP_INLINE_MODE_NOT_REQUIRED: 1765 /* No inline data are required by NIC. */ 1766 config->txq_inline_min = MLX5_INLINE_HSIZE_NONE; 1767 config->hw_vlan_insert = 1768 config->hca_attr.wqe_vlan_insert; 1769 DRV_LOG(DEBUG, "Tx VLAN insertion is supported"); 1770 goto exit; 1771 case MLX5_CAP_INLINE_MODE_VPORT_CONTEXT: 1772 /* inline mode is defined by NIC vport context. */ 1773 if (!config->hca_attr.eth_virt) 1774 break; 1775 switch (config->hca_attr.vport_inline_mode) { 1776 case MLX5_INLINE_MODE_NONE: 1777 config->txq_inline_min = 1778 MLX5_INLINE_HSIZE_NONE; 1779 goto exit; 1780 case MLX5_INLINE_MODE_L2: 1781 config->txq_inline_min = 1782 MLX5_INLINE_HSIZE_L2; 1783 goto exit; 1784 case MLX5_INLINE_MODE_IP: 1785 config->txq_inline_min = 1786 MLX5_INLINE_HSIZE_L3; 1787 goto exit; 1788 case MLX5_INLINE_MODE_TCP_UDP: 1789 config->txq_inline_min = 1790 MLX5_INLINE_HSIZE_L4; 1791 goto exit; 1792 case MLX5_INLINE_MODE_INNER_L2: 1793 config->txq_inline_min = 1794 MLX5_INLINE_HSIZE_INNER_L2; 1795 goto exit; 1796 case MLX5_INLINE_MODE_INNER_IP: 1797 config->txq_inline_min = 1798 MLX5_INLINE_HSIZE_INNER_L3; 1799 goto exit; 1800 case MLX5_INLINE_MODE_INNER_TCP_UDP: 1801 config->txq_inline_min = 1802 MLX5_INLINE_HSIZE_INNER_L4; 1803 goto exit; 1804 } 1805 } 1806 } 1807 /* 1808 * We get here if we are unable to deduce 1809 * inline data size with DevX. Try PCI ID 1810 * to determine old NICs. 1811 */ 1812 switch (spawn->pci_dev->id.device_id) { 1813 case PCI_DEVICE_ID_MELLANOX_CONNECTX4: 1814 case PCI_DEVICE_ID_MELLANOX_CONNECTX4VF: 1815 case PCI_DEVICE_ID_MELLANOX_CONNECTX4LX: 1816 case PCI_DEVICE_ID_MELLANOX_CONNECTX4LXVF: 1817 config->txq_inline_min = MLX5_INLINE_HSIZE_L2; 1818 config->hw_vlan_insert = 0; 1819 break; 1820 case PCI_DEVICE_ID_MELLANOX_CONNECTX5: 1821 case PCI_DEVICE_ID_MELLANOX_CONNECTX5VF: 1822 case PCI_DEVICE_ID_MELLANOX_CONNECTX5EX: 1823 case PCI_DEVICE_ID_MELLANOX_CONNECTX5EXVF: 1824 /* 1825 * These NICs support VLAN insertion from WQE and 1826 * report the wqe_vlan_insert flag. But there is the bug 1827 * and PFC control may be broken, so disable feature. 1828 */ 1829 config->hw_vlan_insert = 0; 1830 config->txq_inline_min = MLX5_INLINE_HSIZE_NONE; 1831 break; 1832 default: 1833 config->txq_inline_min = MLX5_INLINE_HSIZE_NONE; 1834 break; 1835 } 1836 exit: 1837 DRV_LOG(DEBUG, "min tx inline configured: %d", config->txq_inline_min); 1838 } 1839 1840 /** 1841 * Configures the metadata mask fields in the shared context. 1842 * 1843 * @param [in] dev 1844 * Pointer to Ethernet device. 1845 */ 1846 static void 1847 mlx5_set_metadata_mask(struct rte_eth_dev *dev) 1848 { 1849 struct mlx5_priv *priv = dev->data->dev_private; 1850 struct mlx5_ibv_shared *sh = priv->sh; 1851 uint32_t meta, mark, reg_c0; 1852 1853 reg_c0 = ~priv->vport_meta_mask; 1854 switch (priv->config.dv_xmeta_en) { 1855 case MLX5_XMETA_MODE_LEGACY: 1856 meta = UINT32_MAX; 1857 mark = MLX5_FLOW_MARK_MASK; 1858 break; 1859 case MLX5_XMETA_MODE_META16: 1860 meta = reg_c0 >> rte_bsf32(reg_c0); 1861 mark = MLX5_FLOW_MARK_MASK; 1862 break; 1863 case MLX5_XMETA_MODE_META32: 1864 meta = UINT32_MAX; 1865 mark = (reg_c0 >> rte_bsf32(reg_c0)) & MLX5_FLOW_MARK_MASK; 1866 break; 1867 default: 1868 meta = 0; 1869 mark = 0; 1870 MLX5_ASSERT(false); 1871 break; 1872 } 1873 if (sh->dv_mark_mask && sh->dv_mark_mask != mark) 1874 DRV_LOG(WARNING, "metadata MARK mask mismatche %08X:%08X", 1875 sh->dv_mark_mask, mark); 1876 else 1877 sh->dv_mark_mask = mark; 1878 if (sh->dv_meta_mask && sh->dv_meta_mask != meta) 1879 DRV_LOG(WARNING, "metadata META mask mismatche %08X:%08X", 1880 sh->dv_meta_mask, meta); 1881 else 1882 sh->dv_meta_mask = meta; 1883 if (sh->dv_regc0_mask && sh->dv_regc0_mask != reg_c0) 1884 DRV_LOG(WARNING, "metadata reg_c0 mask mismatche %08X:%08X", 1885 sh->dv_meta_mask, reg_c0); 1886 else 1887 sh->dv_regc0_mask = reg_c0; 1888 DRV_LOG(DEBUG, "metadata mode %u", priv->config.dv_xmeta_en); 1889 DRV_LOG(DEBUG, "metadata MARK mask %08X", sh->dv_mark_mask); 1890 DRV_LOG(DEBUG, "metadata META mask %08X", sh->dv_meta_mask); 1891 DRV_LOG(DEBUG, "metadata reg_c0 mask %08X", sh->dv_regc0_mask); 1892 } 1893 1894 /** 1895 * Allocate page of door-bells and register it using DevX API. 1896 * 1897 * @param [in] dev 1898 * Pointer to Ethernet device. 1899 * 1900 * @return 1901 * Pointer to new page on success, NULL otherwise. 1902 */ 1903 static struct mlx5_devx_dbr_page * 1904 mlx5_alloc_dbr_page(struct rte_eth_dev *dev) 1905 { 1906 struct mlx5_priv *priv = dev->data->dev_private; 1907 struct mlx5_devx_dbr_page *page; 1908 1909 /* Allocate space for door-bell page and management data. */ 1910 page = rte_calloc_socket(__func__, 1, sizeof(struct mlx5_devx_dbr_page), 1911 RTE_CACHE_LINE_SIZE, dev->device->numa_node); 1912 if (!page) { 1913 DRV_LOG(ERR, "port %u cannot allocate dbr page", 1914 dev->data->port_id); 1915 return NULL; 1916 } 1917 /* Register allocated memory. */ 1918 page->umem = mlx5_glue->devx_umem_reg(priv->sh->ctx, page->dbrs, 1919 MLX5_DBR_PAGE_SIZE, 0); 1920 if (!page->umem) { 1921 DRV_LOG(ERR, "port %u cannot umem reg dbr page", 1922 dev->data->port_id); 1923 rte_free(page); 1924 return NULL; 1925 } 1926 return page; 1927 } 1928 1929 /** 1930 * Find the next available door-bell, allocate new page if needed. 1931 * 1932 * @param [in] dev 1933 * Pointer to Ethernet device. 1934 * @param [out] dbr_page 1935 * Door-bell page containing the page data. 1936 * 1937 * @return 1938 * Door-bell address offset on success, a negative error value otherwise. 1939 */ 1940 int64_t 1941 mlx5_get_dbr(struct rte_eth_dev *dev, struct mlx5_devx_dbr_page **dbr_page) 1942 { 1943 struct mlx5_priv *priv = dev->data->dev_private; 1944 struct mlx5_devx_dbr_page *page = NULL; 1945 uint32_t i, j; 1946 1947 LIST_FOREACH(page, &priv->dbrpgs, next) 1948 if (page->dbr_count < MLX5_DBR_PER_PAGE) 1949 break; 1950 if (!page) { /* No page with free door-bell exists. */ 1951 page = mlx5_alloc_dbr_page(dev); 1952 if (!page) /* Failed to allocate new page. */ 1953 return (-1); 1954 LIST_INSERT_HEAD(&priv->dbrpgs, page, next); 1955 } 1956 /* Loop to find bitmap part with clear bit. */ 1957 for (i = 0; 1958 i < MLX5_DBR_BITMAP_SIZE && page->dbr_bitmap[i] == UINT64_MAX; 1959 i++) 1960 ; /* Empty. */ 1961 /* Find the first clear bit. */ 1962 j = rte_bsf64(~page->dbr_bitmap[i]); 1963 MLX5_ASSERT(i < (MLX5_DBR_PER_PAGE / 64)); 1964 page->dbr_bitmap[i] |= (1 << j); 1965 page->dbr_count++; 1966 *dbr_page = page; 1967 return (((i * 64) + j) * sizeof(uint64_t)); 1968 } 1969 1970 /** 1971 * Release a door-bell record. 1972 * 1973 * @param [in] dev 1974 * Pointer to Ethernet device. 1975 * @param [in] umem_id 1976 * UMEM ID of page containing the door-bell record to release. 1977 * @param [in] offset 1978 * Offset of door-bell record in page. 1979 * 1980 * @return 1981 * 0 on success, a negative error value otherwise. 1982 */ 1983 int32_t 1984 mlx5_release_dbr(struct rte_eth_dev *dev, uint32_t umem_id, uint64_t offset) 1985 { 1986 struct mlx5_priv *priv = dev->data->dev_private; 1987 struct mlx5_devx_dbr_page *page = NULL; 1988 int ret = 0; 1989 1990 LIST_FOREACH(page, &priv->dbrpgs, next) 1991 /* Find the page this address belongs to. */ 1992 if (page->umem->umem_id == umem_id) 1993 break; 1994 if (!page) 1995 return -EINVAL; 1996 page->dbr_count--; 1997 if (!page->dbr_count) { 1998 /* Page not used, free it and remove from list. */ 1999 LIST_REMOVE(page, next); 2000 if (page->umem) 2001 ret = -mlx5_glue->devx_umem_dereg(page->umem); 2002 rte_free(page); 2003 } else { 2004 /* Mark in bitmap that this door-bell is not in use. */ 2005 offset /= MLX5_DBR_SIZE; 2006 int i = offset / 64; 2007 int j = offset % 64; 2008 2009 page->dbr_bitmap[i] &= ~(1 << j); 2010 } 2011 return ret; 2012 } 2013 2014 int 2015 rte_pmd_mlx5_get_dyn_flag_names(char *names[], unsigned int n) 2016 { 2017 static const char *const dynf_names[] = { 2018 RTE_PMD_MLX5_FINE_GRANULARITY_INLINE, 2019 RTE_MBUF_DYNFLAG_METADATA_NAME 2020 }; 2021 unsigned int i; 2022 2023 if (n < RTE_DIM(dynf_names)) 2024 return -ENOMEM; 2025 for (i = 0; i < RTE_DIM(dynf_names); i++) { 2026 if (names[i] == NULL) 2027 return -EINVAL; 2028 strcpy(names[i], dynf_names[i]); 2029 } 2030 return RTE_DIM(dynf_names); 2031 } 2032 2033 /** 2034 * Check sibling device configurations. 2035 * 2036 * Sibling devices sharing the Infiniband device context 2037 * should have compatible configurations. This regards 2038 * representors and bonding slaves. 2039 * 2040 * @param priv 2041 * Private device descriptor. 2042 * @param config 2043 * Configuration of the device is going to be created. 2044 * 2045 * @return 2046 * 0 on success, EINVAL otherwise 2047 */ 2048 static int 2049 mlx5_dev_check_sibling_config(struct mlx5_priv *priv, 2050 struct mlx5_dev_config *config) 2051 { 2052 struct mlx5_ibv_shared *sh = priv->sh; 2053 struct mlx5_dev_config *sh_conf = NULL; 2054 uint16_t port_id; 2055 2056 MLX5_ASSERT(sh); 2057 /* Nothing to compare for the single/first device. */ 2058 if (sh->refcnt == 1) 2059 return 0; 2060 /* Find the device with shared context. */ 2061 MLX5_ETH_FOREACH_DEV(port_id, priv->pci_dev) { 2062 struct mlx5_priv *opriv = 2063 rte_eth_devices[port_id].data->dev_private; 2064 2065 if (opriv && opriv != priv && opriv->sh == sh) { 2066 sh_conf = &opriv->config; 2067 break; 2068 } 2069 } 2070 if (!sh_conf) 2071 return 0; 2072 if (sh_conf->dv_flow_en ^ config->dv_flow_en) { 2073 DRV_LOG(ERR, "\"dv_flow_en\" configuration mismatch" 2074 " for shared %s context", sh->ibdev_name); 2075 rte_errno = EINVAL; 2076 return rte_errno; 2077 } 2078 if (sh_conf->dv_xmeta_en ^ config->dv_xmeta_en) { 2079 DRV_LOG(ERR, "\"dv_xmeta_en\" configuration mismatch" 2080 " for shared %s context", sh->ibdev_name); 2081 rte_errno = EINVAL; 2082 return rte_errno; 2083 } 2084 return 0; 2085 } 2086 /** 2087 * Spawn an Ethernet device from Verbs information. 2088 * 2089 * @param dpdk_dev 2090 * Backing DPDK device. 2091 * @param spawn 2092 * Verbs device parameters (name, port, switch_info) to spawn. 2093 * @param config 2094 * Device configuration parameters. 2095 * 2096 * @return 2097 * A valid Ethernet device object on success, NULL otherwise and rte_errno 2098 * is set. The following errors are defined: 2099 * 2100 * EBUSY: device is not supposed to be spawned. 2101 * EEXIST: device is already spawned 2102 */ 2103 static struct rte_eth_dev * 2104 mlx5_dev_spawn(struct rte_device *dpdk_dev, 2105 struct mlx5_dev_spawn_data *spawn, 2106 struct mlx5_dev_config config) 2107 { 2108 const struct mlx5_switch_info *switch_info = &spawn->info; 2109 struct mlx5_ibv_shared *sh = NULL; 2110 struct ibv_port_attr port_attr; 2111 struct mlx5dv_context dv_attr = { .comp_mask = 0 }; 2112 struct rte_eth_dev *eth_dev = NULL; 2113 struct mlx5_priv *priv = NULL; 2114 int err = 0; 2115 unsigned int hw_padding = 0; 2116 unsigned int mps; 2117 unsigned int cqe_comp; 2118 unsigned int cqe_pad = 0; 2119 unsigned int tunnel_en = 0; 2120 unsigned int mpls_en = 0; 2121 unsigned int swp = 0; 2122 unsigned int mprq = 0; 2123 unsigned int mprq_min_stride_size_n = 0; 2124 unsigned int mprq_max_stride_size_n = 0; 2125 unsigned int mprq_min_stride_num_n = 0; 2126 unsigned int mprq_max_stride_num_n = 0; 2127 struct rte_ether_addr mac; 2128 char name[RTE_ETH_NAME_MAX_LEN]; 2129 int own_domain_id = 0; 2130 uint16_t port_id; 2131 unsigned int i; 2132 #ifdef HAVE_MLX5DV_DR_DEVX_PORT 2133 struct mlx5dv_devx_port devx_port = { .comp_mask = 0 }; 2134 #endif 2135 2136 /* Determine if this port representor is supposed to be spawned. */ 2137 if (switch_info->representor && dpdk_dev->devargs) { 2138 struct rte_eth_devargs eth_da; 2139 2140 err = rte_eth_devargs_parse(dpdk_dev->devargs->args, ð_da); 2141 if (err) { 2142 rte_errno = -err; 2143 DRV_LOG(ERR, "failed to process device arguments: %s", 2144 strerror(rte_errno)); 2145 return NULL; 2146 } 2147 for (i = 0; i < eth_da.nb_representor_ports; ++i) 2148 if (eth_da.representor_ports[i] == 2149 (uint16_t)switch_info->port_name) 2150 break; 2151 if (i == eth_da.nb_representor_ports) { 2152 rte_errno = EBUSY; 2153 return NULL; 2154 } 2155 } 2156 /* Build device name. */ 2157 if (spawn->pf_bond < 0) { 2158 /* Single device. */ 2159 if (!switch_info->representor) 2160 strlcpy(name, dpdk_dev->name, sizeof(name)); 2161 else 2162 snprintf(name, sizeof(name), "%s_representor_%u", 2163 dpdk_dev->name, switch_info->port_name); 2164 } else { 2165 /* Bonding device. */ 2166 if (!switch_info->representor) 2167 snprintf(name, sizeof(name), "%s_%s", 2168 dpdk_dev->name, spawn->ibv_dev->name); 2169 else 2170 snprintf(name, sizeof(name), "%s_%s_representor_%u", 2171 dpdk_dev->name, spawn->ibv_dev->name, 2172 switch_info->port_name); 2173 } 2174 /* check if the device is already spawned */ 2175 if (rte_eth_dev_get_port_by_name(name, &port_id) == 0) { 2176 rte_errno = EEXIST; 2177 return NULL; 2178 } 2179 DRV_LOG(DEBUG, "naming Ethernet device \"%s\"", name); 2180 if (rte_eal_process_type() == RTE_PROC_SECONDARY) { 2181 eth_dev = rte_eth_dev_attach_secondary(name); 2182 if (eth_dev == NULL) { 2183 DRV_LOG(ERR, "can not attach rte ethdev"); 2184 rte_errno = ENOMEM; 2185 return NULL; 2186 } 2187 eth_dev->device = dpdk_dev; 2188 eth_dev->dev_ops = &mlx5_dev_sec_ops; 2189 err = mlx5_proc_priv_init(eth_dev); 2190 if (err) 2191 return NULL; 2192 /* Receive command fd from primary process */ 2193 err = mlx5_mp_req_verbs_cmd_fd(eth_dev); 2194 if (err < 0) 2195 return NULL; 2196 /* Remap UAR for Tx queues. */ 2197 err = mlx5_tx_uar_init_secondary(eth_dev, err); 2198 if (err) 2199 return NULL; 2200 /* 2201 * Ethdev pointer is still required as input since 2202 * the primary device is not accessible from the 2203 * secondary process. 2204 */ 2205 eth_dev->rx_pkt_burst = mlx5_select_rx_function(eth_dev); 2206 eth_dev->tx_pkt_burst = mlx5_select_tx_function(eth_dev); 2207 return eth_dev; 2208 } 2209 /* 2210 * Some parameters ("tx_db_nc" in particularly) are needed in 2211 * advance to create dv/verbs device context. We proceed the 2212 * devargs here to get ones, and later proceed devargs again 2213 * to override some hardware settings. 2214 */ 2215 err = mlx5_args(&config, dpdk_dev->devargs); 2216 if (err) { 2217 err = rte_errno; 2218 DRV_LOG(ERR, "failed to process device arguments: %s", 2219 strerror(rte_errno)); 2220 goto error; 2221 } 2222 sh = mlx5_alloc_shared_ibctx(spawn, &config); 2223 if (!sh) 2224 return NULL; 2225 config.devx = sh->devx; 2226 #ifdef HAVE_MLX5DV_DR_ACTION_DEST_DEVX_TIR 2227 config.dest_tir = 1; 2228 #endif 2229 #ifdef HAVE_IBV_MLX5_MOD_SWP 2230 dv_attr.comp_mask |= MLX5DV_CONTEXT_MASK_SWP; 2231 #endif 2232 /* 2233 * Multi-packet send is supported by ConnectX-4 Lx PF as well 2234 * as all ConnectX-5 devices. 2235 */ 2236 #ifdef HAVE_IBV_DEVICE_TUNNEL_SUPPORT 2237 dv_attr.comp_mask |= MLX5DV_CONTEXT_MASK_TUNNEL_OFFLOADS; 2238 #endif 2239 #ifdef HAVE_IBV_DEVICE_STRIDING_RQ_SUPPORT 2240 dv_attr.comp_mask |= MLX5DV_CONTEXT_MASK_STRIDING_RQ; 2241 #endif 2242 mlx5_glue->dv_query_device(sh->ctx, &dv_attr); 2243 if (dv_attr.flags & MLX5DV_CONTEXT_FLAGS_MPW_ALLOWED) { 2244 if (dv_attr.flags & MLX5DV_CONTEXT_FLAGS_ENHANCED_MPW) { 2245 DRV_LOG(DEBUG, "enhanced MPW is supported"); 2246 mps = MLX5_MPW_ENHANCED; 2247 } else { 2248 DRV_LOG(DEBUG, "MPW is supported"); 2249 mps = MLX5_MPW; 2250 } 2251 } else { 2252 DRV_LOG(DEBUG, "MPW isn't supported"); 2253 mps = MLX5_MPW_DISABLED; 2254 } 2255 #ifdef HAVE_IBV_MLX5_MOD_SWP 2256 if (dv_attr.comp_mask & MLX5DV_CONTEXT_MASK_SWP) 2257 swp = dv_attr.sw_parsing_caps.sw_parsing_offloads; 2258 DRV_LOG(DEBUG, "SWP support: %u", swp); 2259 #endif 2260 config.swp = !!swp; 2261 #ifdef HAVE_IBV_DEVICE_STRIDING_RQ_SUPPORT 2262 if (dv_attr.comp_mask & MLX5DV_CONTEXT_MASK_STRIDING_RQ) { 2263 struct mlx5dv_striding_rq_caps mprq_caps = 2264 dv_attr.striding_rq_caps; 2265 2266 DRV_LOG(DEBUG, "\tmin_single_stride_log_num_of_bytes: %d", 2267 mprq_caps.min_single_stride_log_num_of_bytes); 2268 DRV_LOG(DEBUG, "\tmax_single_stride_log_num_of_bytes: %d", 2269 mprq_caps.max_single_stride_log_num_of_bytes); 2270 DRV_LOG(DEBUG, "\tmin_single_wqe_log_num_of_strides: %d", 2271 mprq_caps.min_single_wqe_log_num_of_strides); 2272 DRV_LOG(DEBUG, "\tmax_single_wqe_log_num_of_strides: %d", 2273 mprq_caps.max_single_wqe_log_num_of_strides); 2274 DRV_LOG(DEBUG, "\tsupported_qpts: %d", 2275 mprq_caps.supported_qpts); 2276 DRV_LOG(DEBUG, "device supports Multi-Packet RQ"); 2277 mprq = 1; 2278 mprq_min_stride_size_n = 2279 mprq_caps.min_single_stride_log_num_of_bytes; 2280 mprq_max_stride_size_n = 2281 mprq_caps.max_single_stride_log_num_of_bytes; 2282 mprq_min_stride_num_n = 2283 mprq_caps.min_single_wqe_log_num_of_strides; 2284 mprq_max_stride_num_n = 2285 mprq_caps.max_single_wqe_log_num_of_strides; 2286 config.mprq.stride_num_n = RTE_MAX(MLX5_MPRQ_STRIDE_NUM_N, 2287 mprq_min_stride_num_n); 2288 } 2289 #endif 2290 if (RTE_CACHE_LINE_SIZE == 128 && 2291 !(dv_attr.flags & MLX5DV_CONTEXT_FLAGS_CQE_128B_COMP)) 2292 cqe_comp = 0; 2293 else 2294 cqe_comp = 1; 2295 config.cqe_comp = cqe_comp; 2296 #ifdef HAVE_IBV_MLX5_MOD_CQE_128B_PAD 2297 /* Whether device supports 128B Rx CQE padding. */ 2298 cqe_pad = RTE_CACHE_LINE_SIZE == 128 && 2299 (dv_attr.flags & MLX5DV_CONTEXT_FLAGS_CQE_128B_PAD); 2300 #endif 2301 #ifdef HAVE_IBV_DEVICE_TUNNEL_SUPPORT 2302 if (dv_attr.comp_mask & MLX5DV_CONTEXT_MASK_TUNNEL_OFFLOADS) { 2303 tunnel_en = ((dv_attr.tunnel_offloads_caps & 2304 MLX5DV_RAW_PACKET_CAP_TUNNELED_OFFLOAD_VXLAN) && 2305 (dv_attr.tunnel_offloads_caps & 2306 MLX5DV_RAW_PACKET_CAP_TUNNELED_OFFLOAD_GRE) && 2307 (dv_attr.tunnel_offloads_caps & 2308 MLX5DV_RAW_PACKET_CAP_TUNNELED_OFFLOAD_GENEVE)); 2309 } 2310 DRV_LOG(DEBUG, "tunnel offloading is %ssupported", 2311 tunnel_en ? "" : "not "); 2312 #else 2313 DRV_LOG(WARNING, 2314 "tunnel offloading disabled due to old OFED/rdma-core version"); 2315 #endif 2316 config.tunnel_en = tunnel_en; 2317 #ifdef HAVE_IBV_DEVICE_MPLS_SUPPORT 2318 mpls_en = ((dv_attr.tunnel_offloads_caps & 2319 MLX5DV_RAW_PACKET_CAP_TUNNELED_OFFLOAD_CW_MPLS_OVER_GRE) && 2320 (dv_attr.tunnel_offloads_caps & 2321 MLX5DV_RAW_PACKET_CAP_TUNNELED_OFFLOAD_CW_MPLS_OVER_UDP)); 2322 DRV_LOG(DEBUG, "MPLS over GRE/UDP tunnel offloading is %ssupported", 2323 mpls_en ? "" : "not "); 2324 #else 2325 DRV_LOG(WARNING, "MPLS over GRE/UDP tunnel offloading disabled due to" 2326 " old OFED/rdma-core version or firmware configuration"); 2327 #endif 2328 config.mpls_en = mpls_en; 2329 /* Check port status. */ 2330 err = mlx5_glue->query_port(sh->ctx, spawn->ibv_port, &port_attr); 2331 if (err) { 2332 DRV_LOG(ERR, "port query failed: %s", strerror(err)); 2333 goto error; 2334 } 2335 if (port_attr.link_layer != IBV_LINK_LAYER_ETHERNET) { 2336 DRV_LOG(ERR, "port is not configured in Ethernet mode"); 2337 err = EINVAL; 2338 goto error; 2339 } 2340 if (port_attr.state != IBV_PORT_ACTIVE) 2341 DRV_LOG(DEBUG, "port is not active: \"%s\" (%d)", 2342 mlx5_glue->port_state_str(port_attr.state), 2343 port_attr.state); 2344 /* Allocate private eth device data. */ 2345 priv = rte_zmalloc("ethdev private structure", 2346 sizeof(*priv), 2347 RTE_CACHE_LINE_SIZE); 2348 if (priv == NULL) { 2349 DRV_LOG(ERR, "priv allocation failure"); 2350 err = ENOMEM; 2351 goto error; 2352 } 2353 priv->sh = sh; 2354 priv->ibv_port = spawn->ibv_port; 2355 priv->pci_dev = spawn->pci_dev; 2356 priv->mtu = RTE_ETHER_MTU; 2357 #ifndef RTE_ARCH_64 2358 /* Initialize UAR access locks for 32bit implementations. */ 2359 rte_spinlock_init(&priv->uar_lock_cq); 2360 for (i = 0; i < MLX5_UAR_PAGE_NUM_MAX; i++) 2361 rte_spinlock_init(&priv->uar_lock[i]); 2362 #endif 2363 /* Some internal functions rely on Netlink sockets, open them now. */ 2364 priv->nl_socket_rdma = mlx5_nl_init(NETLINK_RDMA); 2365 priv->nl_socket_route = mlx5_nl_init(NETLINK_ROUTE); 2366 priv->representor = !!switch_info->representor; 2367 priv->master = !!switch_info->master; 2368 priv->domain_id = RTE_ETH_DEV_SWITCH_DOMAIN_ID_INVALID; 2369 priv->vport_meta_tag = 0; 2370 priv->vport_meta_mask = 0; 2371 priv->pf_bond = spawn->pf_bond; 2372 #ifdef HAVE_MLX5DV_DR_DEVX_PORT 2373 /* 2374 * The DevX port query API is implemented. E-Switch may use 2375 * either vport or reg_c[0] metadata register to match on 2376 * vport index. The engaged part of metadata register is 2377 * defined by mask. 2378 */ 2379 if (switch_info->representor || switch_info->master) { 2380 devx_port.comp_mask = MLX5DV_DEVX_PORT_VPORT | 2381 MLX5DV_DEVX_PORT_MATCH_REG_C_0; 2382 err = mlx5_glue->devx_port_query(sh->ctx, spawn->ibv_port, 2383 &devx_port); 2384 if (err) { 2385 DRV_LOG(WARNING, 2386 "can't query devx port %d on device %s", 2387 spawn->ibv_port, spawn->ibv_dev->name); 2388 devx_port.comp_mask = 0; 2389 } 2390 } 2391 if (devx_port.comp_mask & MLX5DV_DEVX_PORT_MATCH_REG_C_0) { 2392 priv->vport_meta_tag = devx_port.reg_c_0.value; 2393 priv->vport_meta_mask = devx_port.reg_c_0.mask; 2394 if (!priv->vport_meta_mask) { 2395 DRV_LOG(ERR, "vport zero mask for port %d" 2396 " on bonding device %s", 2397 spawn->ibv_port, spawn->ibv_dev->name); 2398 err = ENOTSUP; 2399 goto error; 2400 } 2401 if (priv->vport_meta_tag & ~priv->vport_meta_mask) { 2402 DRV_LOG(ERR, "invalid vport tag for port %d" 2403 " on bonding device %s", 2404 spawn->ibv_port, spawn->ibv_dev->name); 2405 err = ENOTSUP; 2406 goto error; 2407 } 2408 } 2409 if (devx_port.comp_mask & MLX5DV_DEVX_PORT_VPORT) { 2410 priv->vport_id = devx_port.vport_num; 2411 } else if (spawn->pf_bond >= 0) { 2412 DRV_LOG(ERR, "can't deduce vport index for port %d" 2413 " on bonding device %s", 2414 spawn->ibv_port, spawn->ibv_dev->name); 2415 err = ENOTSUP; 2416 goto error; 2417 } else { 2418 /* Suppose vport index in compatible way. */ 2419 priv->vport_id = switch_info->representor ? 2420 switch_info->port_name + 1 : -1; 2421 } 2422 #else 2423 /* 2424 * Kernel/rdma_core support single E-Switch per PF configurations 2425 * only and vport_id field contains the vport index for 2426 * associated VF, which is deduced from representor port name. 2427 * For example, let's have the IB device port 10, it has 2428 * attached network device eth0, which has port name attribute 2429 * pf0vf2, we can deduce the VF number as 2, and set vport index 2430 * as 3 (2+1). This assigning schema should be changed if the 2431 * multiple E-Switch instances per PF configurations or/and PCI 2432 * subfunctions are added. 2433 */ 2434 priv->vport_id = switch_info->representor ? 2435 switch_info->port_name + 1 : -1; 2436 #endif 2437 /* representor_id field keeps the unmodified VF index. */ 2438 priv->representor_id = switch_info->representor ? 2439 switch_info->port_name : -1; 2440 /* 2441 * Look for sibling devices in order to reuse their switch domain 2442 * if any, otherwise allocate one. 2443 */ 2444 MLX5_ETH_FOREACH_DEV(port_id, priv->pci_dev) { 2445 const struct mlx5_priv *opriv = 2446 rte_eth_devices[port_id].data->dev_private; 2447 2448 if (!opriv || 2449 opriv->sh != priv->sh || 2450 opriv->domain_id == 2451 RTE_ETH_DEV_SWITCH_DOMAIN_ID_INVALID) 2452 continue; 2453 priv->domain_id = opriv->domain_id; 2454 break; 2455 } 2456 if (priv->domain_id == RTE_ETH_DEV_SWITCH_DOMAIN_ID_INVALID) { 2457 err = rte_eth_switch_domain_alloc(&priv->domain_id); 2458 if (err) { 2459 err = rte_errno; 2460 DRV_LOG(ERR, "unable to allocate switch domain: %s", 2461 strerror(rte_errno)); 2462 goto error; 2463 } 2464 own_domain_id = 1; 2465 } 2466 /* Override some values set by hardware configuration. */ 2467 mlx5_args(&config, dpdk_dev->devargs); 2468 err = mlx5_dev_check_sibling_config(priv, &config); 2469 if (err) 2470 goto error; 2471 config.hw_csum = !!(sh->device_attr.device_cap_flags_ex & 2472 IBV_DEVICE_RAW_IP_CSUM); 2473 DRV_LOG(DEBUG, "checksum offloading is %ssupported", 2474 (config.hw_csum ? "" : "not ")); 2475 #if !defined(HAVE_IBV_DEVICE_COUNTERS_SET_V42) && \ 2476 !defined(HAVE_IBV_DEVICE_COUNTERS_SET_V45) 2477 DRV_LOG(DEBUG, "counters are not supported"); 2478 #endif 2479 #if !defined(HAVE_IBV_FLOW_DV_SUPPORT) || !defined(HAVE_MLX5DV_DR) 2480 if (config.dv_flow_en) { 2481 DRV_LOG(WARNING, "DV flow is not supported"); 2482 config.dv_flow_en = 0; 2483 } 2484 #endif 2485 config.ind_table_max_size = 2486 sh->device_attr.rss_caps.max_rwq_indirection_table_size; 2487 /* 2488 * Remove this check once DPDK supports larger/variable 2489 * indirection tables. 2490 */ 2491 if (config.ind_table_max_size > (unsigned int)ETH_RSS_RETA_SIZE_512) 2492 config.ind_table_max_size = ETH_RSS_RETA_SIZE_512; 2493 DRV_LOG(DEBUG, "maximum Rx indirection table size is %u", 2494 config.ind_table_max_size); 2495 config.hw_vlan_strip = !!(sh->device_attr.raw_packet_caps & 2496 IBV_RAW_PACKET_CAP_CVLAN_STRIPPING); 2497 DRV_LOG(DEBUG, "VLAN stripping is %ssupported", 2498 (config.hw_vlan_strip ? "" : "not ")); 2499 config.hw_fcs_strip = !!(sh->device_attr.raw_packet_caps & 2500 IBV_RAW_PACKET_CAP_SCATTER_FCS); 2501 DRV_LOG(DEBUG, "FCS stripping configuration is %ssupported", 2502 (config.hw_fcs_strip ? "" : "not ")); 2503 #if defined(HAVE_IBV_WQ_FLAG_RX_END_PADDING) 2504 hw_padding = !!sh->device_attr.rx_pad_end_addr_align; 2505 #elif defined(HAVE_IBV_WQ_FLAGS_PCI_WRITE_END_PADDING) 2506 hw_padding = !!(sh->device_attr.device_cap_flags_ex & 2507 IBV_DEVICE_PCI_WRITE_END_PADDING); 2508 #endif 2509 if (config.hw_padding && !hw_padding) { 2510 DRV_LOG(DEBUG, "Rx end alignment padding isn't supported"); 2511 config.hw_padding = 0; 2512 } else if (config.hw_padding) { 2513 DRV_LOG(DEBUG, "Rx end alignment padding is enabled"); 2514 } 2515 config.tso = (sh->device_attr.tso_caps.max_tso > 0 && 2516 (sh->device_attr.tso_caps.supported_qpts & 2517 (1 << IBV_QPT_RAW_PACKET))); 2518 if (config.tso) 2519 config.tso_max_payload_sz = sh->device_attr.tso_caps.max_tso; 2520 /* 2521 * MPW is disabled by default, while the Enhanced MPW is enabled 2522 * by default. 2523 */ 2524 if (config.mps == MLX5_ARG_UNSET) 2525 config.mps = (mps == MLX5_MPW_ENHANCED) ? MLX5_MPW_ENHANCED : 2526 MLX5_MPW_DISABLED; 2527 else 2528 config.mps = config.mps ? mps : MLX5_MPW_DISABLED; 2529 DRV_LOG(INFO, "%sMPS is %s", 2530 config.mps == MLX5_MPW_ENHANCED ? "enhanced " : 2531 config.mps == MLX5_MPW ? "legacy " : "", 2532 config.mps != MLX5_MPW_DISABLED ? "enabled" : "disabled"); 2533 if (config.cqe_comp && !cqe_comp) { 2534 DRV_LOG(WARNING, "Rx CQE compression isn't supported"); 2535 config.cqe_comp = 0; 2536 } 2537 if (config.cqe_pad && !cqe_pad) { 2538 DRV_LOG(WARNING, "Rx CQE padding isn't supported"); 2539 config.cqe_pad = 0; 2540 } else if (config.cqe_pad) { 2541 DRV_LOG(INFO, "Rx CQE padding is enabled"); 2542 } 2543 if (config.devx) { 2544 priv->counter_fallback = 0; 2545 err = mlx5_devx_cmd_query_hca_attr(sh->ctx, &config.hca_attr); 2546 if (err) { 2547 err = -err; 2548 goto error; 2549 } 2550 if (!config.hca_attr.flow_counters_dump) 2551 priv->counter_fallback = 1; 2552 #ifndef HAVE_IBV_DEVX_ASYNC 2553 priv->counter_fallback = 1; 2554 #endif 2555 if (priv->counter_fallback) 2556 DRV_LOG(INFO, "Use fall-back DV counter management"); 2557 /* Check for LRO support. */ 2558 if (config.dest_tir && config.hca_attr.lro_cap && 2559 config.dv_flow_en) { 2560 /* TBD check tunnel lro caps. */ 2561 config.lro.supported = config.hca_attr.lro_cap; 2562 DRV_LOG(DEBUG, "Device supports LRO"); 2563 /* 2564 * If LRO timeout is not configured by application, 2565 * use the minimal supported value. 2566 */ 2567 if (!config.lro.timeout) 2568 config.lro.timeout = 2569 config.hca_attr.lro_timer_supported_periods[0]; 2570 DRV_LOG(DEBUG, "LRO session timeout set to %d usec", 2571 config.lro.timeout); 2572 } 2573 #if defined(HAVE_MLX5DV_DR) && defined(HAVE_MLX5_DR_CREATE_ACTION_FLOW_METER) 2574 if (config.hca_attr.qos.sup && config.hca_attr.qos.srtcm_sup && 2575 config.dv_flow_en) { 2576 uint8_t reg_c_mask = 2577 config.hca_attr.qos.flow_meter_reg_c_ids; 2578 /* 2579 * Meter needs two REG_C's for color match and pre-sfx 2580 * flow match. Here get the REG_C for color match. 2581 * REG_C_0 and REG_C_1 is reserved for metadata feature. 2582 */ 2583 reg_c_mask &= 0xfc; 2584 if (__builtin_popcount(reg_c_mask) < 1) { 2585 priv->mtr_en = 0; 2586 DRV_LOG(WARNING, "No available register for" 2587 " meter."); 2588 } else { 2589 priv->mtr_color_reg = ffs(reg_c_mask) - 1 + 2590 REG_C_0; 2591 priv->mtr_en = 1; 2592 priv->mtr_reg_share = 2593 config.hca_attr.qos.flow_meter_reg_share; 2594 DRV_LOG(DEBUG, "The REG_C meter uses is %d", 2595 priv->mtr_color_reg); 2596 } 2597 } 2598 #endif 2599 } 2600 if (config.mprq.enabled && mprq) { 2601 if (config.mprq.stride_num_n > mprq_max_stride_num_n || 2602 config.mprq.stride_num_n < mprq_min_stride_num_n) { 2603 config.mprq.stride_num_n = 2604 RTE_MAX(MLX5_MPRQ_STRIDE_NUM_N, 2605 mprq_min_stride_num_n); 2606 DRV_LOG(WARNING, 2607 "the number of strides" 2608 " for Multi-Packet RQ is out of range," 2609 " setting default value (%u)", 2610 1 << config.mprq.stride_num_n); 2611 } 2612 config.mprq.min_stride_size_n = mprq_min_stride_size_n; 2613 config.mprq.max_stride_size_n = mprq_max_stride_size_n; 2614 } else if (config.mprq.enabled && !mprq) { 2615 DRV_LOG(WARNING, "Multi-Packet RQ isn't supported"); 2616 config.mprq.enabled = 0; 2617 } 2618 if (config.max_dump_files_num == 0) 2619 config.max_dump_files_num = 128; 2620 eth_dev = rte_eth_dev_allocate(name); 2621 if (eth_dev == NULL) { 2622 DRV_LOG(ERR, "can not allocate rte ethdev"); 2623 err = ENOMEM; 2624 goto error; 2625 } 2626 /* Flag to call rte_eth_dev_release_port() in rte_eth_dev_close(). */ 2627 eth_dev->data->dev_flags |= RTE_ETH_DEV_CLOSE_REMOVE; 2628 if (priv->representor) { 2629 eth_dev->data->dev_flags |= RTE_ETH_DEV_REPRESENTOR; 2630 eth_dev->data->representor_id = priv->representor_id; 2631 } 2632 /* 2633 * Store associated network device interface index. This index 2634 * is permanent throughout the lifetime of device. So, we may store 2635 * the ifindex here and use the cached value further. 2636 */ 2637 MLX5_ASSERT(spawn->ifindex); 2638 priv->if_index = spawn->ifindex; 2639 eth_dev->data->dev_private = priv; 2640 priv->dev_data = eth_dev->data; 2641 eth_dev->data->mac_addrs = priv->mac; 2642 eth_dev->device = dpdk_dev; 2643 /* Configure the first MAC address by default. */ 2644 if (mlx5_get_mac(eth_dev, &mac.addr_bytes)) { 2645 DRV_LOG(ERR, 2646 "port %u cannot get MAC address, is mlx5_en" 2647 " loaded? (errno: %s)", 2648 eth_dev->data->port_id, strerror(rte_errno)); 2649 err = ENODEV; 2650 goto error; 2651 } 2652 DRV_LOG(INFO, 2653 "port %u MAC address is %02x:%02x:%02x:%02x:%02x:%02x", 2654 eth_dev->data->port_id, 2655 mac.addr_bytes[0], mac.addr_bytes[1], 2656 mac.addr_bytes[2], mac.addr_bytes[3], 2657 mac.addr_bytes[4], mac.addr_bytes[5]); 2658 #ifdef RTE_LIBRTE_MLX5_DEBUG 2659 { 2660 char ifname[IF_NAMESIZE]; 2661 2662 if (mlx5_get_ifname(eth_dev, &ifname) == 0) 2663 DRV_LOG(DEBUG, "port %u ifname is \"%s\"", 2664 eth_dev->data->port_id, ifname); 2665 else 2666 DRV_LOG(DEBUG, "port %u ifname is unknown", 2667 eth_dev->data->port_id); 2668 } 2669 #endif 2670 /* Get actual MTU if possible. */ 2671 err = mlx5_get_mtu(eth_dev, &priv->mtu); 2672 if (err) { 2673 err = rte_errno; 2674 goto error; 2675 } 2676 DRV_LOG(DEBUG, "port %u MTU is %u", eth_dev->data->port_id, 2677 priv->mtu); 2678 /* Initialize burst functions to prevent crashes before link-up. */ 2679 eth_dev->rx_pkt_burst = removed_rx_burst; 2680 eth_dev->tx_pkt_burst = removed_tx_burst; 2681 eth_dev->dev_ops = &mlx5_dev_ops; 2682 /* Register MAC address. */ 2683 claim_zero(mlx5_mac_addr_add(eth_dev, &mac, 0, 0)); 2684 if (config.vf && config.vf_nl_en) 2685 mlx5_nl_mac_addr_sync(priv->nl_socket_route, 2686 mlx5_ifindex(eth_dev), 2687 eth_dev->data->mac_addrs, 2688 MLX5_MAX_MAC_ADDRESSES); 2689 TAILQ_INIT(&priv->flows); 2690 TAILQ_INIT(&priv->ctrl_flows); 2691 TAILQ_INIT(&priv->flow_meters); 2692 TAILQ_INIT(&priv->flow_meter_profiles); 2693 /* Hint libmlx5 to use PMD allocator for data plane resources */ 2694 struct mlx5dv_ctx_allocators alctr = { 2695 .alloc = &mlx5_alloc_verbs_buf, 2696 .free = &mlx5_free_verbs_buf, 2697 .data = priv, 2698 }; 2699 mlx5_glue->dv_set_context_attr(sh->ctx, 2700 MLX5DV_CTX_ATTR_BUF_ALLOCATORS, 2701 (void *)((uintptr_t)&alctr)); 2702 /* Bring Ethernet device up. */ 2703 DRV_LOG(DEBUG, "port %u forcing Ethernet interface up", 2704 eth_dev->data->port_id); 2705 mlx5_set_link_up(eth_dev); 2706 /* 2707 * Even though the interrupt handler is not installed yet, 2708 * interrupts will still trigger on the async_fd from 2709 * Verbs context returned by ibv_open_device(). 2710 */ 2711 mlx5_link_update(eth_dev, 0); 2712 #ifdef HAVE_MLX5DV_DR_ESWITCH 2713 if (!(config.hca_attr.eswitch_manager && config.dv_flow_en && 2714 (switch_info->representor || switch_info->master))) 2715 config.dv_esw_en = 0; 2716 #else 2717 config.dv_esw_en = 0; 2718 #endif 2719 /* Detect minimal data bytes to inline. */ 2720 mlx5_set_min_inline(spawn, &config); 2721 /* Store device configuration on private structure. */ 2722 priv->config = config; 2723 /* Create context for virtual machine VLAN workaround. */ 2724 priv->vmwa_context = mlx5_vlan_vmwa_init(eth_dev, spawn->ifindex); 2725 if (config.dv_flow_en) { 2726 err = mlx5_alloc_shared_dr(priv); 2727 if (err) 2728 goto error; 2729 /* 2730 * RSS id is shared with meter flow id. Meter flow id can only 2731 * use the 24 MSB of the register. 2732 */ 2733 priv->qrss_id_pool = mlx5_flow_id_pool_alloc(UINT32_MAX >> 2734 MLX5_MTR_COLOR_BITS); 2735 if (!priv->qrss_id_pool) { 2736 DRV_LOG(ERR, "can't create flow id pool"); 2737 err = ENOMEM; 2738 goto error; 2739 } 2740 } 2741 /* Supported Verbs flow priority number detection. */ 2742 err = mlx5_flow_discover_priorities(eth_dev); 2743 if (err < 0) { 2744 err = -err; 2745 goto error; 2746 } 2747 priv->config.flow_prio = err; 2748 if (!priv->config.dv_esw_en && 2749 priv->config.dv_xmeta_en != MLX5_XMETA_MODE_LEGACY) { 2750 DRV_LOG(WARNING, "metadata mode %u is not supported " 2751 "(no E-Switch)", priv->config.dv_xmeta_en); 2752 priv->config.dv_xmeta_en = MLX5_XMETA_MODE_LEGACY; 2753 } 2754 mlx5_set_metadata_mask(eth_dev); 2755 if (priv->config.dv_xmeta_en != MLX5_XMETA_MODE_LEGACY && 2756 !priv->sh->dv_regc0_mask) { 2757 DRV_LOG(ERR, "metadata mode %u is not supported " 2758 "(no metadata reg_c[0] is available)", 2759 priv->config.dv_xmeta_en); 2760 err = ENOTSUP; 2761 goto error; 2762 } 2763 /* Query availibility of metadata reg_c's. */ 2764 err = mlx5_flow_discover_mreg_c(eth_dev); 2765 if (err < 0) { 2766 err = -err; 2767 goto error; 2768 } 2769 if (!mlx5_flow_ext_mreg_supported(eth_dev)) { 2770 DRV_LOG(DEBUG, 2771 "port %u extensive metadata register is not supported", 2772 eth_dev->data->port_id); 2773 if (priv->config.dv_xmeta_en != MLX5_XMETA_MODE_LEGACY) { 2774 DRV_LOG(ERR, "metadata mode %u is not supported " 2775 "(no metadata registers available)", 2776 priv->config.dv_xmeta_en); 2777 err = ENOTSUP; 2778 goto error; 2779 } 2780 } 2781 if (priv->config.dv_flow_en && 2782 priv->config.dv_xmeta_en != MLX5_XMETA_MODE_LEGACY && 2783 mlx5_flow_ext_mreg_supported(eth_dev) && 2784 priv->sh->dv_regc0_mask) { 2785 priv->mreg_cp_tbl = mlx5_hlist_create(MLX5_FLOW_MREG_HNAME, 2786 MLX5_FLOW_MREG_HTABLE_SZ); 2787 if (!priv->mreg_cp_tbl) { 2788 err = ENOMEM; 2789 goto error; 2790 } 2791 } 2792 return eth_dev; 2793 error: 2794 if (priv) { 2795 if (priv->mreg_cp_tbl) 2796 mlx5_hlist_destroy(priv->mreg_cp_tbl, NULL, NULL); 2797 if (priv->sh) 2798 mlx5_free_shared_dr(priv); 2799 if (priv->nl_socket_route >= 0) 2800 close(priv->nl_socket_route); 2801 if (priv->nl_socket_rdma >= 0) 2802 close(priv->nl_socket_rdma); 2803 if (priv->vmwa_context) 2804 mlx5_vlan_vmwa_exit(priv->vmwa_context); 2805 if (priv->qrss_id_pool) 2806 mlx5_flow_id_pool_release(priv->qrss_id_pool); 2807 if (own_domain_id) 2808 claim_zero(rte_eth_switch_domain_free(priv->domain_id)); 2809 rte_free(priv); 2810 if (eth_dev != NULL) 2811 eth_dev->data->dev_private = NULL; 2812 } 2813 if (eth_dev != NULL) { 2814 /* mac_addrs must not be freed alone because part of dev_private */ 2815 eth_dev->data->mac_addrs = NULL; 2816 rte_eth_dev_release_port(eth_dev); 2817 } 2818 if (sh) 2819 mlx5_free_shared_ibctx(sh); 2820 MLX5_ASSERT(err > 0); 2821 rte_errno = err; 2822 return NULL; 2823 } 2824 2825 /** 2826 * Comparison callback to sort device data. 2827 * 2828 * This is meant to be used with qsort(). 2829 * 2830 * @param a[in] 2831 * Pointer to pointer to first data object. 2832 * @param b[in] 2833 * Pointer to pointer to second data object. 2834 * 2835 * @return 2836 * 0 if both objects are equal, less than 0 if the first argument is less 2837 * than the second, greater than 0 otherwise. 2838 */ 2839 static int 2840 mlx5_dev_spawn_data_cmp(const void *a, const void *b) 2841 { 2842 const struct mlx5_switch_info *si_a = 2843 &((const struct mlx5_dev_spawn_data *)a)->info; 2844 const struct mlx5_switch_info *si_b = 2845 &((const struct mlx5_dev_spawn_data *)b)->info; 2846 int ret; 2847 2848 /* Master device first. */ 2849 ret = si_b->master - si_a->master; 2850 if (ret) 2851 return ret; 2852 /* Then representor devices. */ 2853 ret = si_b->representor - si_a->representor; 2854 if (ret) 2855 return ret; 2856 /* Unidentified devices come last in no specific order. */ 2857 if (!si_a->representor) 2858 return 0; 2859 /* Order representors by name. */ 2860 return si_a->port_name - si_b->port_name; 2861 } 2862 2863 /** 2864 * Match PCI information for possible slaves of bonding device. 2865 * 2866 * @param[in] ibv_dev 2867 * Pointer to Infiniband device structure. 2868 * @param[in] pci_dev 2869 * Pointer to PCI device structure to match PCI address. 2870 * @param[in] nl_rdma 2871 * Netlink RDMA group socket handle. 2872 * 2873 * @return 2874 * negative value if no bonding device found, otherwise 2875 * positive index of slave PF in bonding. 2876 */ 2877 static int 2878 mlx5_device_bond_pci_match(const struct ibv_device *ibv_dev, 2879 const struct rte_pci_device *pci_dev, 2880 int nl_rdma) 2881 { 2882 char ifname[IF_NAMESIZE + 1]; 2883 unsigned int ifindex; 2884 unsigned int np, i; 2885 FILE *file = NULL; 2886 int pf = -1; 2887 2888 /* 2889 * Try to get master device name. If something goes 2890 * wrong suppose the lack of kernel support and no 2891 * bonding devices. 2892 */ 2893 if (nl_rdma < 0) 2894 return -1; 2895 if (!strstr(ibv_dev->name, "bond")) 2896 return -1; 2897 np = mlx5_nl_portnum(nl_rdma, ibv_dev->name); 2898 if (!np) 2899 return -1; 2900 /* 2901 * The Master device might not be on the predefined 2902 * port (not on port index 1, it is not garanted), 2903 * we have to scan all Infiniband device port and 2904 * find master. 2905 */ 2906 for (i = 1; i <= np; ++i) { 2907 /* Check whether Infiniband port is populated. */ 2908 ifindex = mlx5_nl_ifindex(nl_rdma, ibv_dev->name, i); 2909 if (!ifindex) 2910 continue; 2911 if (!if_indextoname(ifindex, ifname)) 2912 continue; 2913 /* Try to read bonding slave names from sysfs. */ 2914 MKSTR(slaves, 2915 "/sys/class/net/%s/master/bonding/slaves", ifname); 2916 file = fopen(slaves, "r"); 2917 if (file) 2918 break; 2919 } 2920 if (!file) 2921 return -1; 2922 /* Use safe format to check maximal buffer length. */ 2923 MLX5_ASSERT(atol(RTE_STR(IF_NAMESIZE)) == IF_NAMESIZE); 2924 while (fscanf(file, "%" RTE_STR(IF_NAMESIZE) "s", ifname) == 1) { 2925 char tmp_str[IF_NAMESIZE + 32]; 2926 struct rte_pci_addr pci_addr; 2927 struct mlx5_switch_info info; 2928 2929 /* Process slave interface names in the loop. */ 2930 snprintf(tmp_str, sizeof(tmp_str), 2931 "/sys/class/net/%s", ifname); 2932 if (mlx5_dev_to_pci_addr(tmp_str, &pci_addr)) { 2933 DRV_LOG(WARNING, "can not get PCI address" 2934 " for netdev \"%s\"", ifname); 2935 continue; 2936 } 2937 if (pci_dev->addr.domain != pci_addr.domain || 2938 pci_dev->addr.bus != pci_addr.bus || 2939 pci_dev->addr.devid != pci_addr.devid || 2940 pci_dev->addr.function != pci_addr.function) 2941 continue; 2942 /* Slave interface PCI address match found. */ 2943 fclose(file); 2944 snprintf(tmp_str, sizeof(tmp_str), 2945 "/sys/class/net/%s/phys_port_name", ifname); 2946 file = fopen(tmp_str, "rb"); 2947 if (!file) 2948 break; 2949 info.name_type = MLX5_PHYS_PORT_NAME_TYPE_NOTSET; 2950 if (fscanf(file, "%32s", tmp_str) == 1) 2951 mlx5_translate_port_name(tmp_str, &info); 2952 if (info.name_type == MLX5_PHYS_PORT_NAME_TYPE_LEGACY || 2953 info.name_type == MLX5_PHYS_PORT_NAME_TYPE_UPLINK) 2954 pf = info.port_name; 2955 break; 2956 } 2957 if (file) 2958 fclose(file); 2959 return pf; 2960 } 2961 2962 /** 2963 * DPDK callback to register a PCI device. 2964 * 2965 * This function spawns Ethernet devices out of a given PCI device. 2966 * 2967 * @param[in] pci_drv 2968 * PCI driver structure (mlx5_driver). 2969 * @param[in] pci_dev 2970 * PCI device information. 2971 * 2972 * @return 2973 * 0 on success, a negative errno value otherwise and rte_errno is set. 2974 */ 2975 static int 2976 mlx5_pci_probe(struct rte_pci_driver *pci_drv __rte_unused, 2977 struct rte_pci_device *pci_dev) 2978 { 2979 struct ibv_device **ibv_list; 2980 /* 2981 * Number of found IB Devices matching with requested PCI BDF. 2982 * nd != 1 means there are multiple IB devices over the same 2983 * PCI device and we have representors and master. 2984 */ 2985 unsigned int nd = 0; 2986 /* 2987 * Number of found IB device Ports. nd = 1 and np = 1..n means 2988 * we have the single multiport IB device, and there may be 2989 * representors attached to some of found ports. 2990 */ 2991 unsigned int np = 0; 2992 /* 2993 * Number of DPDK ethernet devices to Spawn - either over 2994 * multiple IB devices or multiple ports of single IB device. 2995 * Actually this is the number of iterations to spawn. 2996 */ 2997 unsigned int ns = 0; 2998 /* 2999 * Bonding device 3000 * < 0 - no bonding device (single one) 3001 * >= 0 - bonding device (value is slave PF index) 3002 */ 3003 int bd = -1; 3004 struct mlx5_dev_spawn_data *list = NULL; 3005 struct mlx5_dev_config dev_config; 3006 int ret; 3007 3008 if (mlx5_class_get(pci_dev->device.devargs) != MLX5_CLASS_NET) { 3009 DRV_LOG(DEBUG, "Skip probing - should be probed by other mlx5" 3010 " driver."); 3011 return 1; 3012 } 3013 if (rte_eal_process_type() == RTE_PROC_PRIMARY) 3014 mlx5_pmd_socket_init(); 3015 ret = mlx5_init_once(); 3016 if (ret) { 3017 DRV_LOG(ERR, "unable to init PMD global data: %s", 3018 strerror(rte_errno)); 3019 return -rte_errno; 3020 } 3021 MLX5_ASSERT(pci_drv == &mlx5_driver); 3022 errno = 0; 3023 ibv_list = mlx5_glue->get_device_list(&ret); 3024 if (!ibv_list) { 3025 rte_errno = errno ? errno : ENOSYS; 3026 DRV_LOG(ERR, "cannot list devices, is ib_uverbs loaded?"); 3027 return -rte_errno; 3028 } 3029 /* 3030 * First scan the list of all Infiniband devices to find 3031 * matching ones, gathering into the list. 3032 */ 3033 struct ibv_device *ibv_match[ret + 1]; 3034 int nl_route = mlx5_nl_init(NETLINK_ROUTE); 3035 int nl_rdma = mlx5_nl_init(NETLINK_RDMA); 3036 unsigned int i; 3037 3038 while (ret-- > 0) { 3039 struct rte_pci_addr pci_addr; 3040 3041 DRV_LOG(DEBUG, "checking device \"%s\"", ibv_list[ret]->name); 3042 bd = mlx5_device_bond_pci_match 3043 (ibv_list[ret], pci_dev, nl_rdma); 3044 if (bd >= 0) { 3045 /* 3046 * Bonding device detected. Only one match is allowed, 3047 * the bonding is supported over multi-port IB device, 3048 * there should be no matches on representor PCI 3049 * functions or non VF LAG bonding devices with 3050 * specified address. 3051 */ 3052 if (nd) { 3053 DRV_LOG(ERR, 3054 "multiple PCI match on bonding device" 3055 "\"%s\" found", ibv_list[ret]->name); 3056 rte_errno = ENOENT; 3057 ret = -rte_errno; 3058 goto exit; 3059 } 3060 DRV_LOG(INFO, "PCI information matches for" 3061 " slave %d bonding device \"%s\"", 3062 bd, ibv_list[ret]->name); 3063 ibv_match[nd++] = ibv_list[ret]; 3064 break; 3065 } 3066 if (mlx5_dev_to_pci_addr 3067 (ibv_list[ret]->ibdev_path, &pci_addr)) 3068 continue; 3069 if (pci_dev->addr.domain != pci_addr.domain || 3070 pci_dev->addr.bus != pci_addr.bus || 3071 pci_dev->addr.devid != pci_addr.devid || 3072 pci_dev->addr.function != pci_addr.function) 3073 continue; 3074 DRV_LOG(INFO, "PCI information matches for device \"%s\"", 3075 ibv_list[ret]->name); 3076 ibv_match[nd++] = ibv_list[ret]; 3077 } 3078 ibv_match[nd] = NULL; 3079 if (!nd) { 3080 /* No device matches, just complain and bail out. */ 3081 DRV_LOG(WARNING, 3082 "no Verbs device matches PCI device " PCI_PRI_FMT "," 3083 " are kernel drivers loaded?", 3084 pci_dev->addr.domain, pci_dev->addr.bus, 3085 pci_dev->addr.devid, pci_dev->addr.function); 3086 rte_errno = ENOENT; 3087 ret = -rte_errno; 3088 goto exit; 3089 } 3090 if (nd == 1) { 3091 /* 3092 * Found single matching device may have multiple ports. 3093 * Each port may be representor, we have to check the port 3094 * number and check the representors existence. 3095 */ 3096 if (nl_rdma >= 0) 3097 np = mlx5_nl_portnum(nl_rdma, ibv_match[0]->name); 3098 if (!np) 3099 DRV_LOG(WARNING, "can not get IB device \"%s\"" 3100 " ports number", ibv_match[0]->name); 3101 if (bd >= 0 && !np) { 3102 DRV_LOG(ERR, "can not get ports" 3103 " for bonding device"); 3104 rte_errno = ENOENT; 3105 ret = -rte_errno; 3106 goto exit; 3107 } 3108 } 3109 #ifndef HAVE_MLX5DV_DR_DEVX_PORT 3110 if (bd >= 0) { 3111 /* 3112 * This may happen if there is VF LAG kernel support and 3113 * application is compiled with older rdma_core library. 3114 */ 3115 DRV_LOG(ERR, 3116 "No kernel/verbs support for VF LAG bonding found."); 3117 rte_errno = ENOTSUP; 3118 ret = -rte_errno; 3119 goto exit; 3120 } 3121 #endif 3122 /* 3123 * Now we can determine the maximal 3124 * amount of devices to be spawned. 3125 */ 3126 list = rte_zmalloc("device spawn data", 3127 sizeof(struct mlx5_dev_spawn_data) * 3128 (np ? np : nd), 3129 RTE_CACHE_LINE_SIZE); 3130 if (!list) { 3131 DRV_LOG(ERR, "spawn data array allocation failure"); 3132 rte_errno = ENOMEM; 3133 ret = -rte_errno; 3134 goto exit; 3135 } 3136 if (bd >= 0 || np > 1) { 3137 /* 3138 * Single IB device with multiple ports found, 3139 * it may be E-Switch master device and representors. 3140 * We have to perform identification trough the ports. 3141 */ 3142 MLX5_ASSERT(nl_rdma >= 0); 3143 MLX5_ASSERT(ns == 0); 3144 MLX5_ASSERT(nd == 1); 3145 MLX5_ASSERT(np); 3146 for (i = 1; i <= np; ++i) { 3147 list[ns].max_port = np; 3148 list[ns].ibv_port = i; 3149 list[ns].ibv_dev = ibv_match[0]; 3150 list[ns].eth_dev = NULL; 3151 list[ns].pci_dev = pci_dev; 3152 list[ns].pf_bond = bd; 3153 list[ns].ifindex = mlx5_nl_ifindex 3154 (nl_rdma, list[ns].ibv_dev->name, i); 3155 if (!list[ns].ifindex) { 3156 /* 3157 * No network interface index found for the 3158 * specified port, it means there is no 3159 * representor on this port. It's OK, 3160 * there can be disabled ports, for example 3161 * if sriov_numvfs < sriov_totalvfs. 3162 */ 3163 continue; 3164 } 3165 ret = -1; 3166 if (nl_route >= 0) 3167 ret = mlx5_nl_switch_info 3168 (nl_route, 3169 list[ns].ifindex, 3170 &list[ns].info); 3171 if (ret || (!list[ns].info.representor && 3172 !list[ns].info.master)) { 3173 /* 3174 * We failed to recognize representors with 3175 * Netlink, let's try to perform the task 3176 * with sysfs. 3177 */ 3178 ret = mlx5_sysfs_switch_info 3179 (list[ns].ifindex, 3180 &list[ns].info); 3181 } 3182 if (!ret && bd >= 0) { 3183 switch (list[ns].info.name_type) { 3184 case MLX5_PHYS_PORT_NAME_TYPE_UPLINK: 3185 if (list[ns].info.port_name == bd) 3186 ns++; 3187 break; 3188 case MLX5_PHYS_PORT_NAME_TYPE_PFVF: 3189 if (list[ns].info.pf_num == bd) 3190 ns++; 3191 break; 3192 default: 3193 break; 3194 } 3195 continue; 3196 } 3197 if (!ret && (list[ns].info.representor ^ 3198 list[ns].info.master)) 3199 ns++; 3200 } 3201 if (!ns) { 3202 DRV_LOG(ERR, 3203 "unable to recognize master/representors" 3204 " on the IB device with multiple ports"); 3205 rte_errno = ENOENT; 3206 ret = -rte_errno; 3207 goto exit; 3208 } 3209 } else { 3210 /* 3211 * The existence of several matching entries (nd > 1) means 3212 * port representors have been instantiated. No existing Verbs 3213 * call nor sysfs entries can tell them apart, this can only 3214 * be done through Netlink calls assuming kernel drivers are 3215 * recent enough to support them. 3216 * 3217 * In the event of identification failure through Netlink, 3218 * try again through sysfs, then: 3219 * 3220 * 1. A single IB device matches (nd == 1) with single 3221 * port (np=0/1) and is not a representor, assume 3222 * no switch support. 3223 * 3224 * 2. Otherwise no safe assumptions can be made; 3225 * complain louder and bail out. 3226 */ 3227 np = 1; 3228 for (i = 0; i != nd; ++i) { 3229 memset(&list[ns].info, 0, sizeof(list[ns].info)); 3230 list[ns].max_port = 1; 3231 list[ns].ibv_port = 1; 3232 list[ns].ibv_dev = ibv_match[i]; 3233 list[ns].eth_dev = NULL; 3234 list[ns].pci_dev = pci_dev; 3235 list[ns].pf_bond = -1; 3236 list[ns].ifindex = 0; 3237 if (nl_rdma >= 0) 3238 list[ns].ifindex = mlx5_nl_ifindex 3239 (nl_rdma, list[ns].ibv_dev->name, 1); 3240 if (!list[ns].ifindex) { 3241 char ifname[IF_NAMESIZE]; 3242 3243 /* 3244 * Netlink failed, it may happen with old 3245 * ib_core kernel driver (before 4.16). 3246 * We can assume there is old driver because 3247 * here we are processing single ports IB 3248 * devices. Let's try sysfs to retrieve 3249 * the ifindex. The method works for 3250 * master device only. 3251 */ 3252 if (nd > 1) { 3253 /* 3254 * Multiple devices found, assume 3255 * representors, can not distinguish 3256 * master/representor and retrieve 3257 * ifindex via sysfs. 3258 */ 3259 continue; 3260 } 3261 ret = mlx5_get_master_ifname 3262 (ibv_match[i]->ibdev_path, &ifname); 3263 if (!ret) 3264 list[ns].ifindex = 3265 if_nametoindex(ifname); 3266 if (!list[ns].ifindex) { 3267 /* 3268 * No network interface index found 3269 * for the specified device, it means 3270 * there it is neither representor 3271 * nor master. 3272 */ 3273 continue; 3274 } 3275 } 3276 ret = -1; 3277 if (nl_route >= 0) 3278 ret = mlx5_nl_switch_info 3279 (nl_route, 3280 list[ns].ifindex, 3281 &list[ns].info); 3282 if (ret || (!list[ns].info.representor && 3283 !list[ns].info.master)) { 3284 /* 3285 * We failed to recognize representors with 3286 * Netlink, let's try to perform the task 3287 * with sysfs. 3288 */ 3289 ret = mlx5_sysfs_switch_info 3290 (list[ns].ifindex, 3291 &list[ns].info); 3292 } 3293 if (!ret && (list[ns].info.representor ^ 3294 list[ns].info.master)) { 3295 ns++; 3296 } else if ((nd == 1) && 3297 !list[ns].info.representor && 3298 !list[ns].info.master) { 3299 /* 3300 * Single IB device with 3301 * one physical port and 3302 * attached network device. 3303 * May be SRIOV is not enabled 3304 * or there is no representors. 3305 */ 3306 DRV_LOG(INFO, "no E-Switch support detected"); 3307 ns++; 3308 break; 3309 } 3310 } 3311 if (!ns) { 3312 DRV_LOG(ERR, 3313 "unable to recognize master/representors" 3314 " on the multiple IB devices"); 3315 rte_errno = ENOENT; 3316 ret = -rte_errno; 3317 goto exit; 3318 } 3319 } 3320 MLX5_ASSERT(ns); 3321 /* 3322 * Sort list to probe devices in natural order for users convenience 3323 * (i.e. master first, then representors from lowest to highest ID). 3324 */ 3325 qsort(list, ns, sizeof(*list), mlx5_dev_spawn_data_cmp); 3326 /* Default configuration. */ 3327 dev_config = (struct mlx5_dev_config){ 3328 .hw_padding = 0, 3329 .mps = MLX5_ARG_UNSET, 3330 .dbnc = MLX5_ARG_UNSET, 3331 .rx_vec_en = 1, 3332 .txq_inline_max = MLX5_ARG_UNSET, 3333 .txq_inline_min = MLX5_ARG_UNSET, 3334 .txq_inline_mpw = MLX5_ARG_UNSET, 3335 .txqs_inline = MLX5_ARG_UNSET, 3336 .vf_nl_en = 1, 3337 .mr_ext_memseg_en = 1, 3338 .mprq = { 3339 .enabled = 0, /* Disabled by default. */ 3340 .stride_num_n = MLX5_MPRQ_STRIDE_NUM_N, 3341 .max_memcpy_len = MLX5_MPRQ_MEMCPY_DEFAULT_LEN, 3342 .min_rxqs_num = MLX5_MPRQ_MIN_RXQS, 3343 }, 3344 .dv_esw_en = 1, 3345 .dv_flow_en = 1, 3346 }; 3347 /* Device specific configuration. */ 3348 switch (pci_dev->id.device_id) { 3349 case PCI_DEVICE_ID_MELLANOX_CONNECTX4VF: 3350 case PCI_DEVICE_ID_MELLANOX_CONNECTX4LXVF: 3351 case PCI_DEVICE_ID_MELLANOX_CONNECTX5VF: 3352 case PCI_DEVICE_ID_MELLANOX_CONNECTX5EXVF: 3353 case PCI_DEVICE_ID_MELLANOX_CONNECTX5BFVF: 3354 case PCI_DEVICE_ID_MELLANOX_CONNECTX6VF: 3355 case PCI_DEVICE_ID_MELLANOX_CONNECTX6DXVF: 3356 dev_config.vf = 1; 3357 break; 3358 default: 3359 break; 3360 } 3361 for (i = 0; i != ns; ++i) { 3362 uint32_t restore; 3363 3364 list[i].eth_dev = mlx5_dev_spawn(&pci_dev->device, 3365 &list[i], 3366 dev_config); 3367 if (!list[i].eth_dev) { 3368 if (rte_errno != EBUSY && rte_errno != EEXIST) 3369 break; 3370 /* Device is disabled or already spawned. Ignore it. */ 3371 continue; 3372 } 3373 restore = list[i].eth_dev->data->dev_flags; 3374 rte_eth_copy_pci_info(list[i].eth_dev, pci_dev); 3375 /* Restore non-PCI flags cleared by the above call. */ 3376 list[i].eth_dev->data->dev_flags |= restore; 3377 mlx5_dev_interrupt_handler_devx_install(list[i].eth_dev); 3378 rte_eth_dev_probing_finish(list[i].eth_dev); 3379 } 3380 if (i != ns) { 3381 DRV_LOG(ERR, 3382 "probe of PCI device " PCI_PRI_FMT " aborted after" 3383 " encountering an error: %s", 3384 pci_dev->addr.domain, pci_dev->addr.bus, 3385 pci_dev->addr.devid, pci_dev->addr.function, 3386 strerror(rte_errno)); 3387 ret = -rte_errno; 3388 /* Roll back. */ 3389 while (i--) { 3390 if (!list[i].eth_dev) 3391 continue; 3392 mlx5_dev_close(list[i].eth_dev); 3393 /* mac_addrs must not be freed because in dev_private */ 3394 list[i].eth_dev->data->mac_addrs = NULL; 3395 claim_zero(rte_eth_dev_release_port(list[i].eth_dev)); 3396 } 3397 /* Restore original error. */ 3398 rte_errno = -ret; 3399 } else { 3400 ret = 0; 3401 } 3402 exit: 3403 /* 3404 * Do the routine cleanup: 3405 * - close opened Netlink sockets 3406 * - free allocated spawn data array 3407 * - free the Infiniband device list 3408 */ 3409 if (nl_rdma >= 0) 3410 close(nl_rdma); 3411 if (nl_route >= 0) 3412 close(nl_route); 3413 if (list) 3414 rte_free(list); 3415 MLX5_ASSERT(ibv_list); 3416 mlx5_glue->free_device_list(ibv_list); 3417 return ret; 3418 } 3419 3420 /** 3421 * Look for the ethernet device belonging to mlx5 driver. 3422 * 3423 * @param[in] port_id 3424 * port_id to start looking for device. 3425 * @param[in] pci_dev 3426 * Pointer to the hint PCI device. When device is being probed 3427 * the its siblings (master and preceding representors might 3428 * not have assigned driver yet (because the mlx5_pci_probe() 3429 * is not completed yet, for this case match on hint PCI 3430 * device may be used to detect sibling device. 3431 * 3432 * @return 3433 * port_id of found device, RTE_MAX_ETHPORT if not found. 3434 */ 3435 uint16_t 3436 mlx5_eth_find_next(uint16_t port_id, struct rte_pci_device *pci_dev) 3437 { 3438 while (port_id < RTE_MAX_ETHPORTS) { 3439 struct rte_eth_dev *dev = &rte_eth_devices[port_id]; 3440 3441 if (dev->state != RTE_ETH_DEV_UNUSED && 3442 dev->device && 3443 (dev->device == &pci_dev->device || 3444 (dev->device->driver && 3445 dev->device->driver->name && 3446 !strcmp(dev->device->driver->name, MLX5_DRIVER_NAME)))) 3447 break; 3448 port_id++; 3449 } 3450 if (port_id >= RTE_MAX_ETHPORTS) 3451 return RTE_MAX_ETHPORTS; 3452 return port_id; 3453 } 3454 3455 /** 3456 * DPDK callback to remove a PCI device. 3457 * 3458 * This function removes all Ethernet devices belong to a given PCI device. 3459 * 3460 * @param[in] pci_dev 3461 * Pointer to the PCI device. 3462 * 3463 * @return 3464 * 0 on success, the function cannot fail. 3465 */ 3466 static int 3467 mlx5_pci_remove(struct rte_pci_device *pci_dev) 3468 { 3469 uint16_t port_id; 3470 3471 RTE_ETH_FOREACH_DEV_OF(port_id, &pci_dev->device) 3472 rte_eth_dev_close(port_id); 3473 return 0; 3474 } 3475 3476 static const struct rte_pci_id mlx5_pci_id_map[] = { 3477 { 3478 RTE_PCI_DEVICE(PCI_VENDOR_ID_MELLANOX, 3479 PCI_DEVICE_ID_MELLANOX_CONNECTX4) 3480 }, 3481 { 3482 RTE_PCI_DEVICE(PCI_VENDOR_ID_MELLANOX, 3483 PCI_DEVICE_ID_MELLANOX_CONNECTX4VF) 3484 }, 3485 { 3486 RTE_PCI_DEVICE(PCI_VENDOR_ID_MELLANOX, 3487 PCI_DEVICE_ID_MELLANOX_CONNECTX4LX) 3488 }, 3489 { 3490 RTE_PCI_DEVICE(PCI_VENDOR_ID_MELLANOX, 3491 PCI_DEVICE_ID_MELLANOX_CONNECTX4LXVF) 3492 }, 3493 { 3494 RTE_PCI_DEVICE(PCI_VENDOR_ID_MELLANOX, 3495 PCI_DEVICE_ID_MELLANOX_CONNECTX5) 3496 }, 3497 { 3498 RTE_PCI_DEVICE(PCI_VENDOR_ID_MELLANOX, 3499 PCI_DEVICE_ID_MELLANOX_CONNECTX5VF) 3500 }, 3501 { 3502 RTE_PCI_DEVICE(PCI_VENDOR_ID_MELLANOX, 3503 PCI_DEVICE_ID_MELLANOX_CONNECTX5EX) 3504 }, 3505 { 3506 RTE_PCI_DEVICE(PCI_VENDOR_ID_MELLANOX, 3507 PCI_DEVICE_ID_MELLANOX_CONNECTX5EXVF) 3508 }, 3509 { 3510 RTE_PCI_DEVICE(PCI_VENDOR_ID_MELLANOX, 3511 PCI_DEVICE_ID_MELLANOX_CONNECTX5BF) 3512 }, 3513 { 3514 RTE_PCI_DEVICE(PCI_VENDOR_ID_MELLANOX, 3515 PCI_DEVICE_ID_MELLANOX_CONNECTX5BFVF) 3516 }, 3517 { 3518 RTE_PCI_DEVICE(PCI_VENDOR_ID_MELLANOX, 3519 PCI_DEVICE_ID_MELLANOX_CONNECTX6) 3520 }, 3521 { 3522 RTE_PCI_DEVICE(PCI_VENDOR_ID_MELLANOX, 3523 PCI_DEVICE_ID_MELLANOX_CONNECTX6VF) 3524 }, 3525 { 3526 RTE_PCI_DEVICE(PCI_VENDOR_ID_MELLANOX, 3527 PCI_DEVICE_ID_MELLANOX_CONNECTX6DX) 3528 }, 3529 { 3530 RTE_PCI_DEVICE(PCI_VENDOR_ID_MELLANOX, 3531 PCI_DEVICE_ID_MELLANOX_CONNECTX6DXVF) 3532 }, 3533 { 3534 .vendor_id = 0 3535 } 3536 }; 3537 3538 static struct rte_pci_driver mlx5_driver = { 3539 .driver = { 3540 .name = MLX5_DRIVER_NAME 3541 }, 3542 .id_table = mlx5_pci_id_map, 3543 .probe = mlx5_pci_probe, 3544 .remove = mlx5_pci_remove, 3545 .dma_map = mlx5_dma_map, 3546 .dma_unmap = mlx5_dma_unmap, 3547 .drv_flags = RTE_PCI_DRV_INTR_LSC | RTE_PCI_DRV_INTR_RMV | 3548 RTE_PCI_DRV_PROBE_AGAIN, 3549 }; 3550 3551 /** 3552 * Driver initialization routine. 3553 */ 3554 RTE_INIT(rte_mlx5_pmd_init) 3555 { 3556 /* Initialize driver log type. */ 3557 mlx5_logtype = rte_log_register("pmd.net.mlx5"); 3558 if (mlx5_logtype >= 0) 3559 rte_log_set_level(mlx5_logtype, RTE_LOG_NOTICE); 3560 3561 /* Build the static tables for Verbs conversion. */ 3562 mlx5_set_ptype_table(); 3563 mlx5_set_cksum_table(); 3564 mlx5_set_swp_types_table(); 3565 if (mlx5_glue) 3566 rte_pci_register(&mlx5_driver); 3567 } 3568 3569 RTE_PMD_EXPORT_NAME(net_mlx5, __COUNTER__); 3570 RTE_PMD_REGISTER_PCI_TABLE(net_mlx5, mlx5_pci_id_map); 3571 RTE_PMD_REGISTER_KMOD_DEP(net_mlx5, "* ib_uverbs & mlx5_core & mlx5_ib"); 3572