1 /* SPDX-License-Identifier: BSD-3-Clause 2 * Copyright 2015 6WIND S.A. 3 * Copyright 2015 Mellanox Technologies, Ltd 4 */ 5 6 #include <stddef.h> 7 #include <unistd.h> 8 #include <string.h> 9 #include <stdint.h> 10 #include <stdlib.h> 11 #include <errno.h> 12 #include <fcntl.h> 13 14 #include <rte_malloc.h> 15 #include <ethdev_driver.h> 16 #include <rte_pci.h> 17 #include <bus_pci_driver.h> 18 #include <rte_common.h> 19 #include <rte_kvargs.h> 20 #include <rte_rwlock.h> 21 #include <rte_spinlock.h> 22 #include <rte_string_fns.h> 23 #include <rte_eal_paging.h> 24 #include <rte_alarm.h> 25 #include <rte_cycles.h> 26 #include <rte_interrupts.h> 27 28 #include <mlx5_glue.h> 29 #include <mlx5_devx_cmds.h> 30 #include <mlx5_common.h> 31 #include <mlx5_common_os.h> 32 #include <mlx5_common_mp.h> 33 #include <mlx5_malloc.h> 34 35 #include "mlx5_defs.h" 36 #include "mlx5.h" 37 #include "mlx5_utils.h" 38 #include "mlx5_rxtx.h" 39 #include "mlx5_rx.h" 40 #include "mlx5_tx.h" 41 #include "mlx5_autoconf.h" 42 #include "mlx5_flow.h" 43 #include "mlx5_flow_os.h" 44 #include "rte_pmd_mlx5.h" 45 46 #define MLX5_ETH_DRIVER_NAME mlx5_eth 47 48 /* Device parameter to enable RX completion queue compression. */ 49 #define MLX5_RXQ_CQE_COMP_EN "rxq_cqe_comp_en" 50 51 /* Device parameter to enable padding Rx packet to cacheline size. */ 52 #define MLX5_RXQ_PKT_PAD_EN "rxq_pkt_pad_en" 53 54 /* Device parameter to enable Multi-Packet Rx queue. */ 55 #define MLX5_RX_MPRQ_EN "mprq_en" 56 57 /* Device parameter to configure log 2 of the number of strides for MPRQ. */ 58 #define MLX5_RX_MPRQ_LOG_STRIDE_NUM "mprq_log_stride_num" 59 60 /* Device parameter to configure log 2 of the stride size for MPRQ. */ 61 #define MLX5_RX_MPRQ_LOG_STRIDE_SIZE "mprq_log_stride_size" 62 63 /* Device parameter to limit the size of memcpy'd packet for MPRQ. */ 64 #define MLX5_RX_MPRQ_MAX_MEMCPY_LEN "mprq_max_memcpy_len" 65 66 /* Device parameter to set the minimum number of Rx queues to enable MPRQ. */ 67 #define MLX5_RXQS_MIN_MPRQ "rxqs_min_mprq" 68 69 /* Device parameter to configure inline send. Deprecated, ignored.*/ 70 #define MLX5_TXQ_INLINE "txq_inline" 71 72 /* Device parameter to limit packet size to inline with ordinary SEND. */ 73 #define MLX5_TXQ_INLINE_MAX "txq_inline_max" 74 75 /* Device parameter to configure minimal data size to inline. */ 76 #define MLX5_TXQ_INLINE_MIN "txq_inline_min" 77 78 /* Device parameter to limit packet size to inline with Enhanced MPW. */ 79 #define MLX5_TXQ_INLINE_MPW "txq_inline_mpw" 80 81 /* 82 * Device parameter to configure the number of TX queues threshold for 83 * enabling inline send. 84 */ 85 #define MLX5_TXQS_MIN_INLINE "txqs_min_inline" 86 87 /* 88 * Device parameter to configure the number of TX queues threshold for 89 * enabling vectorized Tx, deprecated, ignored (no vectorized Tx routines). 90 */ 91 #define MLX5_TXQS_MAX_VEC "txqs_max_vec" 92 93 /* Device parameter to enable multi-packet send WQEs. */ 94 #define MLX5_TXQ_MPW_EN "txq_mpw_en" 95 96 /* 97 * Device parameter to include 2 dsegs in the title WQEBB. 98 * Deprecated, ignored. 99 */ 100 #define MLX5_TXQ_MPW_HDR_DSEG_EN "txq_mpw_hdr_dseg_en" 101 102 /* 103 * Device parameter to limit the size of inlining packet. 104 * Deprecated, ignored. 105 */ 106 #define MLX5_TXQ_MAX_INLINE_LEN "txq_max_inline_len" 107 108 /* 109 * Device parameter to enable Tx scheduling on timestamps 110 * and specify the packet pacing granularity in nanoseconds. 111 */ 112 #define MLX5_TX_PP "tx_pp" 113 114 /* 115 * Device parameter to specify skew in nanoseconds on Tx datapath, 116 * it represents the time between SQ start WQE processing and 117 * appearing actual packet data on the wire. 118 */ 119 #define MLX5_TX_SKEW "tx_skew" 120 121 /* 122 * Device parameter to enable hardware Tx vector. 123 * Deprecated, ignored (no vectorized Tx routines anymore). 124 */ 125 #define MLX5_TX_VEC_EN "tx_vec_en" 126 127 /* Device parameter to enable hardware Rx vector. */ 128 #define MLX5_RX_VEC_EN "rx_vec_en" 129 130 /* Allow L3 VXLAN flow creation. */ 131 #define MLX5_L3_VXLAN_EN "l3_vxlan_en" 132 133 /* Activate DV E-Switch flow steering. */ 134 #define MLX5_DV_ESW_EN "dv_esw_en" 135 136 /* Activate DV flow steering. */ 137 #define MLX5_DV_FLOW_EN "dv_flow_en" 138 139 /* Enable extensive flow metadata support. */ 140 #define MLX5_DV_XMETA_EN "dv_xmeta_en" 141 142 /* Device parameter to let the user manage the lacp traffic of bonded device */ 143 #define MLX5_LACP_BY_USER "lacp_by_user" 144 145 /* Activate Netlink support in VF mode. */ 146 #define MLX5_VF_NL_EN "vf_nl_en" 147 148 /* Select port representors to instantiate. */ 149 #define MLX5_REPRESENTOR "representor" 150 151 /* Device parameter to configure the maximum number of dump files per queue. */ 152 #define MLX5_MAX_DUMP_FILES_NUM "max_dump_files_num" 153 154 /* Configure timeout of LRO session (in microseconds). */ 155 #define MLX5_LRO_TIMEOUT_USEC "lro_timeout_usec" 156 157 /* 158 * Device parameter to configure the total data buffer size for a single 159 * hairpin queue (logarithm value). 160 */ 161 #define MLX5_HP_BUF_SIZE "hp_buf_log_sz" 162 163 /* Flow memory reclaim mode. */ 164 #define MLX5_RECLAIM_MEM "reclaim_mem_mode" 165 166 /* Decap will be used or not. */ 167 #define MLX5_DECAP_EN "decap_en" 168 169 /* Device parameter to configure allow or prevent duplicate rules pattern. */ 170 #define MLX5_ALLOW_DUPLICATE_PATTERN "allow_duplicate_pattern" 171 172 /* Device parameter to configure the delay drop when creating Rxqs. */ 173 #define MLX5_DELAY_DROP "delay_drop" 174 175 /* Device parameter to create the fdb default rule in PMD */ 176 #define MLX5_FDB_DEFAULT_RULE_EN "fdb_def_rule_en" 177 178 /* HW steering counter configuration. */ 179 #define MLX5_HWS_CNT_SERVICE_CORE "service_core" 180 181 /* HW steering counter's query interval. */ 182 #define MLX5_HWS_CNT_CYCLE_TIME "svc_cycle_time" 183 184 /* Device parameter to control representor matching in ingress/egress flows with HWS. */ 185 #define MLX5_REPR_MATCHING_EN "repr_matching_en" 186 187 /* Shared memory between primary and secondary processes. */ 188 struct mlx5_shared_data *mlx5_shared_data; 189 190 /** Driver-specific log messages type. */ 191 int mlx5_logtype; 192 193 static LIST_HEAD(, mlx5_dev_ctx_shared) mlx5_dev_ctx_list = 194 LIST_HEAD_INITIALIZER(); 195 static pthread_mutex_t mlx5_dev_ctx_list_mutex; 196 static const struct mlx5_indexed_pool_config mlx5_ipool_cfg[] = { 197 #if defined(HAVE_IBV_FLOW_DV_SUPPORT) || !defined(HAVE_INFINIBAND_VERBS_H) 198 [MLX5_IPOOL_DECAP_ENCAP] = { 199 .size = sizeof(struct mlx5_flow_dv_encap_decap_resource), 200 .trunk_size = 64, 201 .grow_trunk = 3, 202 .grow_shift = 2, 203 .need_lock = 1, 204 .release_mem_en = 1, 205 .malloc = mlx5_malloc, 206 .free = mlx5_free, 207 .type = "mlx5_encap_decap_ipool", 208 }, 209 [MLX5_IPOOL_PUSH_VLAN] = { 210 .size = sizeof(struct mlx5_flow_dv_push_vlan_action_resource), 211 .trunk_size = 64, 212 .grow_trunk = 3, 213 .grow_shift = 2, 214 .need_lock = 1, 215 .release_mem_en = 1, 216 .malloc = mlx5_malloc, 217 .free = mlx5_free, 218 .type = "mlx5_push_vlan_ipool", 219 }, 220 [MLX5_IPOOL_TAG] = { 221 .size = sizeof(struct mlx5_flow_dv_tag_resource), 222 .trunk_size = 64, 223 .grow_trunk = 3, 224 .grow_shift = 2, 225 .need_lock = 1, 226 .release_mem_en = 0, 227 .per_core_cache = (1 << 16), 228 .malloc = mlx5_malloc, 229 .free = mlx5_free, 230 .type = "mlx5_tag_ipool", 231 }, 232 [MLX5_IPOOL_PORT_ID] = { 233 .size = sizeof(struct mlx5_flow_dv_port_id_action_resource), 234 .trunk_size = 64, 235 .grow_trunk = 3, 236 .grow_shift = 2, 237 .need_lock = 1, 238 .release_mem_en = 1, 239 .malloc = mlx5_malloc, 240 .free = mlx5_free, 241 .type = "mlx5_port_id_ipool", 242 }, 243 [MLX5_IPOOL_JUMP] = { 244 .size = sizeof(struct mlx5_flow_tbl_data_entry), 245 .trunk_size = 64, 246 .grow_trunk = 3, 247 .grow_shift = 2, 248 .need_lock = 1, 249 .release_mem_en = 1, 250 .malloc = mlx5_malloc, 251 .free = mlx5_free, 252 .type = "mlx5_jump_ipool", 253 }, 254 [MLX5_IPOOL_SAMPLE] = { 255 .size = sizeof(struct mlx5_flow_dv_sample_resource), 256 .trunk_size = 64, 257 .grow_trunk = 3, 258 .grow_shift = 2, 259 .need_lock = 1, 260 .release_mem_en = 1, 261 .malloc = mlx5_malloc, 262 .free = mlx5_free, 263 .type = "mlx5_sample_ipool", 264 }, 265 [MLX5_IPOOL_DEST_ARRAY] = { 266 .size = sizeof(struct mlx5_flow_dv_dest_array_resource), 267 .trunk_size = 64, 268 .grow_trunk = 3, 269 .grow_shift = 2, 270 .need_lock = 1, 271 .release_mem_en = 1, 272 .malloc = mlx5_malloc, 273 .free = mlx5_free, 274 .type = "mlx5_dest_array_ipool", 275 }, 276 [MLX5_IPOOL_TUNNEL_ID] = { 277 .size = sizeof(struct mlx5_flow_tunnel), 278 .trunk_size = MLX5_MAX_TUNNELS, 279 .need_lock = 1, 280 .release_mem_en = 1, 281 .type = "mlx5_tunnel_offload", 282 }, 283 [MLX5_IPOOL_TNL_TBL_ID] = { 284 .size = 0, 285 .need_lock = 1, 286 .type = "mlx5_flow_tnl_tbl_ipool", 287 }, 288 #endif 289 [MLX5_IPOOL_MTR] = { 290 /** 291 * The ipool index should grow continually from small to big, 292 * for meter idx, so not set grow_trunk to avoid meter index 293 * not jump continually. 294 */ 295 .size = sizeof(struct mlx5_legacy_flow_meter), 296 .trunk_size = 64, 297 .need_lock = 1, 298 .release_mem_en = 1, 299 .malloc = mlx5_malloc, 300 .free = mlx5_free, 301 .type = "mlx5_meter_ipool", 302 }, 303 [MLX5_IPOOL_MCP] = { 304 .size = sizeof(struct mlx5_flow_mreg_copy_resource), 305 .trunk_size = 64, 306 .grow_trunk = 3, 307 .grow_shift = 2, 308 .need_lock = 1, 309 .release_mem_en = 1, 310 .malloc = mlx5_malloc, 311 .free = mlx5_free, 312 .type = "mlx5_mcp_ipool", 313 }, 314 [MLX5_IPOOL_HRXQ] = { 315 .size = (sizeof(struct mlx5_hrxq) + MLX5_RSS_HASH_KEY_LEN), 316 .trunk_size = 64, 317 .grow_trunk = 3, 318 .grow_shift = 2, 319 .need_lock = 1, 320 .release_mem_en = 1, 321 .malloc = mlx5_malloc, 322 .free = mlx5_free, 323 .type = "mlx5_hrxq_ipool", 324 }, 325 [MLX5_IPOOL_MLX5_FLOW] = { 326 /* 327 * MLX5_IPOOL_MLX5_FLOW size varies for DV and VERBS flows. 328 * It set in run time according to PCI function configuration. 329 */ 330 .size = 0, 331 .trunk_size = 64, 332 .grow_trunk = 3, 333 .grow_shift = 2, 334 .need_lock = 1, 335 .release_mem_en = 0, 336 .per_core_cache = 1 << 19, 337 .malloc = mlx5_malloc, 338 .free = mlx5_free, 339 .type = "mlx5_flow_handle_ipool", 340 }, 341 [MLX5_IPOOL_RTE_FLOW] = { 342 .size = sizeof(struct rte_flow), 343 .trunk_size = 4096, 344 .need_lock = 1, 345 .release_mem_en = 1, 346 .malloc = mlx5_malloc, 347 .free = mlx5_free, 348 .type = "rte_flow_ipool", 349 }, 350 [MLX5_IPOOL_RSS_EXPANTION_FLOW_ID] = { 351 .size = 0, 352 .need_lock = 1, 353 .type = "mlx5_flow_rss_id_ipool", 354 }, 355 [MLX5_IPOOL_RSS_SHARED_ACTIONS] = { 356 .size = sizeof(struct mlx5_shared_action_rss), 357 .trunk_size = 64, 358 .grow_trunk = 3, 359 .grow_shift = 2, 360 .need_lock = 1, 361 .release_mem_en = 1, 362 .malloc = mlx5_malloc, 363 .free = mlx5_free, 364 .type = "mlx5_shared_action_rss", 365 }, 366 [MLX5_IPOOL_MTR_POLICY] = { 367 /** 368 * The ipool index should grow continually from small to big, 369 * for policy idx, so not set grow_trunk to avoid policy index 370 * not jump continually. 371 */ 372 .size = sizeof(struct mlx5_flow_meter_sub_policy), 373 .trunk_size = 64, 374 .need_lock = 1, 375 .release_mem_en = 1, 376 .malloc = mlx5_malloc, 377 .free = mlx5_free, 378 .type = "mlx5_meter_policy_ipool", 379 }, 380 }; 381 382 #define MLX5_FLOW_MIN_ID_POOL_SIZE 512 383 #define MLX5_ID_GENERATION_ARRAY_FACTOR 16 384 385 #define MLX5_FLOW_TABLE_HLIST_ARRAY_SIZE 1024 386 387 /** 388 * Decide whether representor ID is a HPF(host PF) port on BF2. 389 * 390 * @param dev 391 * Pointer to Ethernet device structure. 392 * 393 * @return 394 * Non-zero if HPF, otherwise 0. 395 */ 396 bool 397 mlx5_is_hpf(struct rte_eth_dev *dev) 398 { 399 struct mlx5_priv *priv = dev->data->dev_private; 400 uint16_t repr = MLX5_REPRESENTOR_REPR(priv->representor_id); 401 int type = MLX5_REPRESENTOR_TYPE(priv->representor_id); 402 403 return priv->representor != 0 && type == RTE_ETH_REPRESENTOR_VF && 404 MLX5_REPRESENTOR_REPR(-1) == repr; 405 } 406 407 /** 408 * Decide whether representor ID is a SF port representor. 409 * 410 * @param dev 411 * Pointer to Ethernet device structure. 412 * 413 * @return 414 * Non-zero if HPF, otherwise 0. 415 */ 416 bool 417 mlx5_is_sf_repr(struct rte_eth_dev *dev) 418 { 419 struct mlx5_priv *priv = dev->data->dev_private; 420 int type = MLX5_REPRESENTOR_TYPE(priv->representor_id); 421 422 return priv->representor != 0 && type == RTE_ETH_REPRESENTOR_SF; 423 } 424 425 /** 426 * Initialize the ASO aging management structure. 427 * 428 * @param[in] sh 429 * Pointer to mlx5_dev_ctx_shared object to free 430 * 431 * @return 432 * 0 on success, a negative errno value otherwise and rte_errno is set. 433 */ 434 int 435 mlx5_flow_aso_age_mng_init(struct mlx5_dev_ctx_shared *sh) 436 { 437 int err; 438 439 if (sh->aso_age_mng) 440 return 0; 441 sh->aso_age_mng = mlx5_malloc(MLX5_MEM_ZERO, sizeof(*sh->aso_age_mng), 442 RTE_CACHE_LINE_SIZE, SOCKET_ID_ANY); 443 if (!sh->aso_age_mng) { 444 DRV_LOG(ERR, "aso_age_mng allocation was failed."); 445 rte_errno = ENOMEM; 446 return -ENOMEM; 447 } 448 err = mlx5_aso_queue_init(sh, ASO_OPC_MOD_FLOW_HIT, 1); 449 if (err) { 450 mlx5_free(sh->aso_age_mng); 451 return -1; 452 } 453 rte_rwlock_init(&sh->aso_age_mng->resize_rwl); 454 rte_spinlock_init(&sh->aso_age_mng->free_sl); 455 LIST_INIT(&sh->aso_age_mng->free); 456 return 0; 457 } 458 459 /** 460 * Close and release all the resources of the ASO aging management structure. 461 * 462 * @param[in] sh 463 * Pointer to mlx5_dev_ctx_shared object to free. 464 */ 465 static void 466 mlx5_flow_aso_age_mng_close(struct mlx5_dev_ctx_shared *sh) 467 { 468 int i, j; 469 470 mlx5_aso_flow_hit_queue_poll_stop(sh); 471 mlx5_aso_queue_uninit(sh, ASO_OPC_MOD_FLOW_HIT); 472 if (sh->aso_age_mng->pools) { 473 struct mlx5_aso_age_pool *pool; 474 475 for (i = 0; i < sh->aso_age_mng->next; ++i) { 476 pool = sh->aso_age_mng->pools[i]; 477 claim_zero(mlx5_devx_cmd_destroy 478 (pool->flow_hit_aso_obj)); 479 for (j = 0; j < MLX5_COUNTERS_PER_POOL; ++j) 480 if (pool->actions[j].dr_action) 481 claim_zero 482 (mlx5_flow_os_destroy_flow_action 483 (pool->actions[j].dr_action)); 484 mlx5_free(pool); 485 } 486 mlx5_free(sh->aso_age_mng->pools); 487 } 488 mlx5_free(sh->aso_age_mng); 489 } 490 491 /** 492 * Initialize the shared aging list information per port. 493 * 494 * @param[in] sh 495 * Pointer to mlx5_dev_ctx_shared object. 496 */ 497 static void 498 mlx5_flow_aging_init(struct mlx5_dev_ctx_shared *sh) 499 { 500 uint32_t i; 501 struct mlx5_age_info *age_info; 502 503 /* 504 * In HW steering, aging information structure is initialized later 505 * during configure function. 506 */ 507 if (sh->config.dv_flow_en == 2) 508 return; 509 for (i = 0; i < sh->max_port; i++) { 510 age_info = &sh->port[i].age_info; 511 age_info->flags = 0; 512 TAILQ_INIT(&age_info->aged_counters); 513 LIST_INIT(&age_info->aged_aso); 514 rte_spinlock_init(&age_info->aged_sl); 515 MLX5_AGE_SET(age_info, MLX5_AGE_TRIGGER); 516 } 517 } 518 519 /** 520 * DV flow counter mode detect and config. 521 * 522 * @param dev 523 * Pointer to rte_eth_dev structure. 524 * 525 */ 526 void 527 mlx5_flow_counter_mode_config(struct rte_eth_dev *dev __rte_unused) 528 { 529 #ifdef HAVE_IBV_FLOW_DV_SUPPORT 530 struct mlx5_priv *priv = dev->data->dev_private; 531 struct mlx5_dev_ctx_shared *sh = priv->sh; 532 struct mlx5_hca_attr *hca_attr = &sh->cdev->config.hca_attr; 533 bool fallback; 534 535 #ifndef HAVE_IBV_DEVX_ASYNC 536 fallback = true; 537 #else 538 fallback = false; 539 if (!sh->cdev->config.devx || !sh->config.dv_flow_en || 540 !hca_attr->flow_counters_dump || 541 !(hca_attr->flow_counter_bulk_alloc_bitmap & 0x4) || 542 (mlx5_flow_dv_discover_counter_offset_support(dev) == -ENOTSUP)) 543 fallback = true; 544 #endif 545 if (fallback) 546 DRV_LOG(INFO, "Use fall-back DV counter management. Flow " 547 "counter dump:%d, bulk_alloc_bitmap:0x%hhx.", 548 hca_attr->flow_counters_dump, 549 hca_attr->flow_counter_bulk_alloc_bitmap); 550 /* Initialize fallback mode only on the port initializes sh. */ 551 if (sh->refcnt == 1) 552 sh->sws_cmng.counter_fallback = fallback; 553 else if (fallback != sh->sws_cmng.counter_fallback) 554 DRV_LOG(WARNING, "Port %d in sh has different fallback mode " 555 "with others:%d.", PORT_ID(priv), fallback); 556 #endif 557 } 558 559 /** 560 * Initialize the counters management structure. 561 * 562 * @param[in] sh 563 * Pointer to mlx5_dev_ctx_shared object to free 564 * 565 * @return 566 * 0 on success, otherwise negative errno value and rte_errno is set. 567 */ 568 static int 569 mlx5_flow_counters_mng_init(struct mlx5_dev_ctx_shared *sh) 570 { 571 int i, j; 572 573 if (sh->config.dv_flow_en < 2) { 574 void *pools; 575 576 pools = mlx5_malloc(MLX5_MEM_ZERO, 577 sizeof(struct mlx5_flow_counter_pool *) * 578 MLX5_COUNTER_POOLS_MAX_NUM, 579 0, SOCKET_ID_ANY); 580 if (!pools) { 581 DRV_LOG(ERR, 582 "Counter management allocation was failed."); 583 rte_errno = ENOMEM; 584 return -rte_errno; 585 } 586 memset(&sh->sws_cmng, 0, sizeof(sh->sws_cmng)); 587 TAILQ_INIT(&sh->sws_cmng.flow_counters); 588 sh->sws_cmng.min_id = MLX5_CNT_BATCH_OFFSET; 589 sh->sws_cmng.max_id = -1; 590 sh->sws_cmng.last_pool_idx = POOL_IDX_INVALID; 591 sh->sws_cmng.pools = pools; 592 rte_spinlock_init(&sh->sws_cmng.pool_update_sl); 593 for (i = 0; i < MLX5_COUNTER_TYPE_MAX; i++) { 594 TAILQ_INIT(&sh->sws_cmng.counters[i]); 595 rte_spinlock_init(&sh->sws_cmng.csl[i]); 596 } 597 } else { 598 struct mlx5_hca_attr *attr = &sh->cdev->config.hca_attr; 599 uint32_t fw_max_nb_cnts = attr->max_flow_counter; 600 uint8_t log_dcs = log2above(fw_max_nb_cnts) - 1; 601 uint32_t max_nb_cnts = 0; 602 603 for (i = 0, j = 0; j < MLX5_HWS_CNT_DCS_NUM; ++i) { 604 int log_dcs_i = log_dcs - i; 605 606 if (log_dcs_i < 0) 607 break; 608 if ((max_nb_cnts | RTE_BIT32(log_dcs_i)) > 609 fw_max_nb_cnts) 610 continue; 611 max_nb_cnts |= RTE_BIT32(log_dcs_i); 612 j++; 613 } 614 sh->hws_max_log_bulk_sz = log_dcs; 615 sh->hws_max_nb_counters = max_nb_cnts; 616 } 617 return 0; 618 } 619 620 /** 621 * Destroy all the resources allocated for a counter memory management. 622 * 623 * @param[in] mng 624 * Pointer to the memory management structure. 625 */ 626 static void 627 mlx5_flow_destroy_counter_stat_mem_mng(struct mlx5_counter_stats_mem_mng *mng) 628 { 629 uint8_t *mem = (uint8_t *)(uintptr_t)mng->raws[0].data; 630 631 LIST_REMOVE(mng, next); 632 mlx5_os_wrapped_mkey_destroy(&mng->wm); 633 mlx5_free(mem); 634 } 635 636 /** 637 * Close and release all the resources of the counters management. 638 * 639 * @param[in] sh 640 * Pointer to mlx5_dev_ctx_shared object to free. 641 */ 642 static void 643 mlx5_flow_counters_mng_close(struct mlx5_dev_ctx_shared *sh) 644 { 645 struct mlx5_counter_stats_mem_mng *mng; 646 int i, j; 647 int retries = 1024; 648 649 rte_errno = 0; 650 while (--retries) { 651 rte_eal_alarm_cancel(mlx5_flow_query_alarm, sh); 652 if (rte_errno != EINPROGRESS) 653 break; 654 rte_pause(); 655 } 656 657 if (sh->sws_cmng.pools) { 658 struct mlx5_flow_counter_pool *pool; 659 uint16_t n_valid = sh->sws_cmng.n_valid; 660 bool fallback = sh->sws_cmng.counter_fallback; 661 662 for (i = 0; i < n_valid; ++i) { 663 pool = sh->sws_cmng.pools[i]; 664 if (!fallback && pool->min_dcs) 665 claim_zero(mlx5_devx_cmd_destroy 666 (pool->min_dcs)); 667 for (j = 0; j < MLX5_COUNTERS_PER_POOL; ++j) { 668 struct mlx5_flow_counter *cnt = 669 MLX5_POOL_GET_CNT(pool, j); 670 671 if (cnt->action) 672 claim_zero 673 (mlx5_flow_os_destroy_flow_action 674 (cnt->action)); 675 if (fallback && cnt->dcs_when_free) 676 claim_zero(mlx5_devx_cmd_destroy 677 (cnt->dcs_when_free)); 678 } 679 mlx5_free(pool); 680 } 681 mlx5_free(sh->sws_cmng.pools); 682 } 683 mng = LIST_FIRST(&sh->sws_cmng.mem_mngs); 684 while (mng) { 685 mlx5_flow_destroy_counter_stat_mem_mng(mng); 686 mng = LIST_FIRST(&sh->sws_cmng.mem_mngs); 687 } 688 memset(&sh->sws_cmng, 0, sizeof(sh->sws_cmng)); 689 } 690 691 /** 692 * Initialize the aso flow meters management structure. 693 * 694 * @param[in] sh 695 * Pointer to mlx5_dev_ctx_shared object to free 696 */ 697 int 698 mlx5_aso_flow_mtrs_mng_init(struct mlx5_dev_ctx_shared *sh) 699 { 700 if (!sh->mtrmng) { 701 sh->mtrmng = mlx5_malloc(MLX5_MEM_ZERO, 702 sizeof(*sh->mtrmng), 703 RTE_CACHE_LINE_SIZE, SOCKET_ID_ANY); 704 if (!sh->mtrmng) { 705 DRV_LOG(ERR, 706 "meter management allocation was failed."); 707 rte_errno = ENOMEM; 708 return -ENOMEM; 709 } 710 if (sh->meter_aso_en) { 711 rte_spinlock_init(&sh->mtrmng->pools_mng.mtrsl); 712 rte_rwlock_init(&sh->mtrmng->pools_mng.resize_mtrwl); 713 LIST_INIT(&sh->mtrmng->pools_mng.meters); 714 } 715 sh->mtrmng->def_policy_id = MLX5_INVALID_POLICY_ID; 716 } 717 return 0; 718 } 719 720 /** 721 * Close and release all the resources of 722 * the ASO flow meter management structure. 723 * 724 * @param[in] sh 725 * Pointer to mlx5_dev_ctx_shared object to free. 726 */ 727 static void 728 mlx5_aso_flow_mtrs_mng_close(struct mlx5_dev_ctx_shared *sh) 729 { 730 struct mlx5_aso_mtr_pool *mtr_pool; 731 struct mlx5_flow_mtr_mng *mtrmng = sh->mtrmng; 732 uint32_t idx; 733 #ifdef HAVE_MLX5_DR_CREATE_ACTION_ASO 734 struct mlx5_aso_mtr *aso_mtr; 735 int i; 736 #endif /* HAVE_MLX5_DR_CREATE_ACTION_ASO */ 737 738 if (sh->meter_aso_en) { 739 mlx5_aso_queue_uninit(sh, ASO_OPC_MOD_POLICER); 740 idx = mtrmng->pools_mng.n_valid; 741 while (idx--) { 742 mtr_pool = mtrmng->pools_mng.pools[idx]; 743 #ifdef HAVE_MLX5_DR_CREATE_ACTION_ASO 744 for (i = 0; i < MLX5_ASO_MTRS_PER_POOL; i++) { 745 aso_mtr = &mtr_pool->mtrs[i]; 746 if (aso_mtr->fm.meter_action_g) 747 claim_zero 748 (mlx5_glue->destroy_flow_action 749 (aso_mtr->fm.meter_action_g)); 750 if (aso_mtr->fm.meter_action_y) 751 claim_zero 752 (mlx5_glue->destroy_flow_action 753 (aso_mtr->fm.meter_action_y)); 754 } 755 #endif /* HAVE_MLX5_DR_CREATE_ACTION_ASO */ 756 claim_zero(mlx5_devx_cmd_destroy 757 (mtr_pool->devx_obj)); 758 mtrmng->pools_mng.n_valid--; 759 mlx5_free(mtr_pool); 760 } 761 mlx5_free(sh->mtrmng->pools_mng.pools); 762 } 763 mlx5_free(sh->mtrmng); 764 sh->mtrmng = NULL; 765 } 766 767 /* Send FLOW_AGED event if needed. */ 768 void 769 mlx5_age_event_prepare(struct mlx5_dev_ctx_shared *sh) 770 { 771 struct mlx5_age_info *age_info; 772 uint32_t i; 773 774 for (i = 0; i < sh->max_port; i++) { 775 age_info = &sh->port[i].age_info; 776 if (!MLX5_AGE_GET(age_info, MLX5_AGE_EVENT_NEW)) 777 continue; 778 MLX5_AGE_UNSET(age_info, MLX5_AGE_EVENT_NEW); 779 if (MLX5_AGE_GET(age_info, MLX5_AGE_TRIGGER)) { 780 MLX5_AGE_UNSET(age_info, MLX5_AGE_TRIGGER); 781 rte_eth_dev_callback_process 782 (&rte_eth_devices[sh->port[i].devx_ih_port_id], 783 RTE_ETH_EVENT_FLOW_AGED, NULL); 784 } 785 } 786 } 787 788 /* 789 * Initialize the ASO connection tracking structure. 790 * 791 * @param[in] sh 792 * Pointer to mlx5_dev_ctx_shared object. 793 * 794 * @return 795 * 0 on success, a negative errno value otherwise and rte_errno is set. 796 */ 797 int 798 mlx5_flow_aso_ct_mng_init(struct mlx5_dev_ctx_shared *sh) 799 { 800 int err; 801 802 if (sh->ct_mng) 803 return 0; 804 sh->ct_mng = mlx5_malloc(MLX5_MEM_ZERO, sizeof(*sh->ct_mng) + 805 sizeof(struct mlx5_aso_sq) * MLX5_ASO_CT_SQ_NUM, 806 RTE_CACHE_LINE_SIZE, SOCKET_ID_ANY); 807 if (!sh->ct_mng) { 808 DRV_LOG(ERR, "ASO CT management allocation failed."); 809 rte_errno = ENOMEM; 810 return -rte_errno; 811 } 812 err = mlx5_aso_queue_init(sh, ASO_OPC_MOD_CONNECTION_TRACKING, MLX5_ASO_CT_SQ_NUM); 813 if (err) { 814 mlx5_free(sh->ct_mng); 815 /* rte_errno should be extracted from the failure. */ 816 rte_errno = EINVAL; 817 return -rte_errno; 818 } 819 rte_spinlock_init(&sh->ct_mng->ct_sl); 820 rte_rwlock_init(&sh->ct_mng->resize_rwl); 821 LIST_INIT(&sh->ct_mng->free_cts); 822 return 0; 823 } 824 825 /* 826 * Close and release all the resources of the 827 * ASO connection tracking management structure. 828 * 829 * @param[in] sh 830 * Pointer to mlx5_dev_ctx_shared object to free. 831 */ 832 static void 833 mlx5_flow_aso_ct_mng_close(struct mlx5_dev_ctx_shared *sh) 834 { 835 struct mlx5_aso_ct_pools_mng *mng = sh->ct_mng; 836 struct mlx5_aso_ct_pool *ct_pool; 837 struct mlx5_aso_ct_action *ct; 838 uint32_t idx; 839 uint32_t val; 840 uint32_t cnt; 841 int i; 842 843 mlx5_aso_queue_uninit(sh, ASO_OPC_MOD_CONNECTION_TRACKING); 844 idx = mng->next; 845 while (idx--) { 846 cnt = 0; 847 ct_pool = mng->pools[idx]; 848 for (i = 0; i < MLX5_ASO_CT_ACTIONS_PER_POOL; i++) { 849 ct = &ct_pool->actions[i]; 850 val = __atomic_fetch_sub(&ct->refcnt, 1, 851 __ATOMIC_RELAXED); 852 MLX5_ASSERT(val == 1); 853 if (val > 1) 854 cnt++; 855 #ifdef HAVE_MLX5_DR_ACTION_ASO_CT 856 if (ct->dr_action_orig) 857 claim_zero(mlx5_glue->destroy_flow_action 858 (ct->dr_action_orig)); 859 if (ct->dr_action_rply) 860 claim_zero(mlx5_glue->destroy_flow_action 861 (ct->dr_action_rply)); 862 #endif 863 } 864 claim_zero(mlx5_devx_cmd_destroy(ct_pool->devx_obj)); 865 if (cnt) { 866 DRV_LOG(DEBUG, "%u ASO CT objects are being used in the pool %u", 867 cnt, i); 868 } 869 mlx5_free(ct_pool); 870 /* in case of failure. */ 871 mng->next--; 872 } 873 mlx5_free(mng->pools); 874 mlx5_free(mng); 875 /* Management structure must be cleared to 0s during allocation. */ 876 sh->ct_mng = NULL; 877 } 878 879 /** 880 * Initialize the flow resources' indexed mempool. 881 * 882 * @param[in] sh 883 * Pointer to mlx5_dev_ctx_shared object. 884 */ 885 static void 886 mlx5_flow_ipool_create(struct mlx5_dev_ctx_shared *sh) 887 { 888 uint8_t i; 889 struct mlx5_indexed_pool_config cfg; 890 891 for (i = 0; i < MLX5_IPOOL_MAX; ++i) { 892 cfg = mlx5_ipool_cfg[i]; 893 switch (i) { 894 default: 895 break; 896 /* 897 * Set MLX5_IPOOL_MLX5_FLOW ipool size 898 * according to PCI function flow configuration. 899 */ 900 case MLX5_IPOOL_MLX5_FLOW: 901 cfg.size = sh->config.dv_flow_en ? 902 sizeof(struct mlx5_flow_handle) : 903 MLX5_FLOW_HANDLE_VERBS_SIZE; 904 break; 905 } 906 if (sh->config.reclaim_mode) { 907 cfg.release_mem_en = 1; 908 cfg.per_core_cache = 0; 909 } else { 910 cfg.release_mem_en = 0; 911 } 912 sh->ipool[i] = mlx5_ipool_create(&cfg); 913 } 914 } 915 916 917 /** 918 * Release the flow resources' indexed mempool. 919 * 920 * @param[in] sh 921 * Pointer to mlx5_dev_ctx_shared object. 922 */ 923 static void 924 mlx5_flow_ipool_destroy(struct mlx5_dev_ctx_shared *sh) 925 { 926 uint8_t i; 927 928 for (i = 0; i < MLX5_IPOOL_MAX; ++i) 929 mlx5_ipool_destroy(sh->ipool[i]); 930 for (i = 0; i < MLX5_MAX_MODIFY_NUM; ++i) 931 if (sh->mdh_ipools[i]) 932 mlx5_ipool_destroy(sh->mdh_ipools[i]); 933 } 934 935 /* 936 * Check if dynamic flex parser for eCPRI already exists. 937 * 938 * @param dev 939 * Pointer to Ethernet device structure. 940 * 941 * @return 942 * true on exists, false on not. 943 */ 944 bool 945 mlx5_flex_parser_ecpri_exist(struct rte_eth_dev *dev) 946 { 947 struct mlx5_priv *priv = dev->data->dev_private; 948 struct mlx5_ecpri_parser_profile *prf = &priv->sh->ecpri_parser; 949 950 return !!prf->obj; 951 } 952 953 /* 954 * Allocation of a flex parser for eCPRI. Once created, this parser related 955 * resources will be held until the device is closed. 956 * 957 * @param dev 958 * Pointer to Ethernet device structure. 959 * 960 * @return 961 * 0 on success, a negative errno value otherwise and rte_errno is set. 962 */ 963 int 964 mlx5_flex_parser_ecpri_alloc(struct rte_eth_dev *dev) 965 { 966 struct mlx5_priv *priv = dev->data->dev_private; 967 struct mlx5_hca_flex_attr *attr = &priv->sh->cdev->config.hca_attr.flex; 968 struct mlx5_ecpri_parser_profile *prf = &priv->sh->ecpri_parser; 969 struct mlx5_devx_graph_node_attr node = { 970 .modify_field_select = 0, 971 }; 972 struct mlx5_ext_sample_id ids[8]; 973 int ret; 974 975 if (!priv->sh->cdev->config.hca_attr.parse_graph_flex_node) { 976 DRV_LOG(ERR, "Dynamic flex parser is not supported " 977 "for device %s.", priv->dev_data->name); 978 return -ENOTSUP; 979 } 980 node.header_length_mode = MLX5_GRAPH_NODE_LEN_FIXED; 981 /* 8 bytes now: 4B common header + 4B message body header. */ 982 node.header_length_base_value = 0x8; 983 /* After MAC layer: Ether / VLAN. */ 984 node.in[0].arc_parse_graph_node = MLX5_GRAPH_ARC_NODE_MAC; 985 /* Type of compared condition should be 0xAEFE in the L2 layer. */ 986 node.in[0].compare_condition_value = RTE_ETHER_TYPE_ECPRI; 987 /* Sample #0: type in common header. */ 988 node.sample[0].flow_match_sample_en = 1; 989 /* Fixed offset. */ 990 node.sample[0].flow_match_sample_offset_mode = 0x0; 991 /* Only the 2nd byte will be used. */ 992 node.sample[0].flow_match_sample_field_base_offset = 0x0; 993 /* Sample #1: message payload. */ 994 node.sample[1].flow_match_sample_en = 1; 995 /* Fixed offset. */ 996 node.sample[1].flow_match_sample_offset_mode = 0x0; 997 /* 998 * Only the first two bytes will be used right now, and its offset will 999 * start after the common header that with the length of a DW(u32). 1000 */ 1001 node.sample[1].flow_match_sample_field_base_offset = sizeof(uint32_t); 1002 prf->obj = mlx5_devx_cmd_create_flex_parser(priv->sh->cdev->ctx, &node); 1003 if (!prf->obj) { 1004 DRV_LOG(ERR, "Failed to create flex parser node object."); 1005 return (rte_errno == 0) ? -ENODEV : -rte_errno; 1006 } 1007 prf->num = 2; 1008 ret = mlx5_devx_cmd_query_parse_samples(prf->obj, ids, prf->num, NULL); 1009 if (ret) { 1010 DRV_LOG(ERR, "Failed to query sample IDs."); 1011 return (rte_errno == 0) ? -ENODEV : -rte_errno; 1012 } 1013 prf->offset[0] = 0x0; 1014 prf->offset[1] = sizeof(uint32_t); 1015 if (attr->ext_sample_id) { 1016 prf->ids[0] = ids[0].sample_id; 1017 prf->ids[1] = ids[1].sample_id; 1018 } else { 1019 prf->ids[0] = ids[0].id; 1020 prf->ids[1] = ids[1].id; 1021 } 1022 return 0; 1023 } 1024 1025 /* 1026 * Destroy the flex parser node, including the parser itself, input / output 1027 * arcs and DW samples. Resources could be reused then. 1028 * 1029 * @param dev 1030 * Pointer to Ethernet device structure. 1031 */ 1032 static void 1033 mlx5_flex_parser_ecpri_release(struct rte_eth_dev *dev) 1034 { 1035 struct mlx5_priv *priv = dev->data->dev_private; 1036 struct mlx5_ecpri_parser_profile *prf = &priv->sh->ecpri_parser; 1037 1038 if (prf->obj) 1039 mlx5_devx_cmd_destroy(prf->obj); 1040 prf->obj = NULL; 1041 } 1042 1043 /* 1044 * Allocation of a flex parser for srh. Once refcnt is zero, the resources held 1045 * by this parser will be freed. 1046 * @param dev 1047 * Pointer to Ethernet device structure. 1048 * 1049 * @return 1050 * 0 on success, a negative errno value otherwise and rte_errno is set. 1051 */ 1052 int 1053 mlx5_alloc_srh_flex_parser(struct rte_eth_dev *dev) 1054 { 1055 struct mlx5_devx_graph_node_attr node = { 1056 .modify_field_select = 0, 1057 }; 1058 struct mlx5_ext_sample_id ids[MLX5_GRAPH_NODE_SAMPLE_NUM]; 1059 struct mlx5_priv *priv = dev->data->dev_private; 1060 struct mlx5_common_dev_config *config = &priv->sh->cdev->config; 1061 void *ibv_ctx = priv->sh->cdev->ctx; 1062 int ret; 1063 1064 memset(ids, 0xff, sizeof(ids)); 1065 if (!config->hca_attr.parse_graph_flex_node) { 1066 DRV_LOG(ERR, "Dynamic flex parser is not supported"); 1067 return -ENOTSUP; 1068 } 1069 if (__atomic_add_fetch(&priv->sh->srh_flex_parser.refcnt, 1, __ATOMIC_RELAXED) > 1) 1070 return 0; 1071 1072 node.header_length_mode = MLX5_GRAPH_NODE_LEN_FIELD; 1073 /* Srv6 first two DW are not counted in. */ 1074 node.header_length_base_value = 0x8; 1075 /* The unit is uint64_t. */ 1076 node.header_length_field_shift = 0x3; 1077 /* Header length is the 2nd byte. */ 1078 node.header_length_field_offset = 0x8; 1079 node.header_length_field_mask = 0xF; 1080 /* One byte next header protocol. */ 1081 node.next_header_field_size = 0x8; 1082 node.in[0].arc_parse_graph_node = MLX5_GRAPH_ARC_NODE_IP; 1083 node.in[0].compare_condition_value = IPPROTO_ROUTING; 1084 node.sample[0].flow_match_sample_en = 1; 1085 /* First come first serve no matter inner or outer. */ 1086 node.sample[0].flow_match_sample_tunnel_mode = MLX5_GRAPH_SAMPLE_TUNNEL_FIRST; 1087 node.out[0].arc_parse_graph_node = MLX5_GRAPH_ARC_NODE_TCP; 1088 node.out[0].compare_condition_value = IPPROTO_TCP; 1089 node.out[1].arc_parse_graph_node = MLX5_GRAPH_ARC_NODE_UDP; 1090 node.out[1].compare_condition_value = IPPROTO_UDP; 1091 node.out[2].arc_parse_graph_node = MLX5_GRAPH_ARC_NODE_IPV6; 1092 node.out[2].compare_condition_value = IPPROTO_IPV6; 1093 priv->sh->srh_flex_parser.fp = mlx5_devx_cmd_create_flex_parser(ibv_ctx, &node); 1094 if (!priv->sh->srh_flex_parser.fp) { 1095 DRV_LOG(ERR, "Failed to create flex parser node object."); 1096 return (rte_errno == 0) ? -ENODEV : -rte_errno; 1097 } 1098 priv->sh->srh_flex_parser.num = 1; 1099 ret = mlx5_devx_cmd_query_parse_samples(priv->sh->srh_flex_parser.fp, ids, 1100 priv->sh->srh_flex_parser.num, 1101 &priv->sh->srh_flex_parser.anchor_id); 1102 if (ret) { 1103 DRV_LOG(ERR, "Failed to query sample IDs."); 1104 return (rte_errno == 0) ? -ENODEV : -rte_errno; 1105 } 1106 priv->sh->srh_flex_parser.offset[0] = 0x0; 1107 priv->sh->srh_flex_parser.ids[0].id = ids[0].id; 1108 return 0; 1109 } 1110 1111 /* 1112 * Destroy the flex parser node, including the parser itself, input / output 1113 * arcs and DW samples. Resources could be reused then. 1114 * 1115 * @param dev 1116 * Pointer to Ethernet device structure 1117 */ 1118 void 1119 mlx5_free_srh_flex_parser(struct rte_eth_dev *dev) 1120 { 1121 struct mlx5_priv *priv = dev->data->dev_private; 1122 struct mlx5_internal_flex_parser_profile *fp = &priv->sh->srh_flex_parser; 1123 1124 if (__atomic_sub_fetch(&fp->refcnt, 1, __ATOMIC_RELAXED)) 1125 return; 1126 if (fp->fp) 1127 mlx5_devx_cmd_destroy(fp->fp); 1128 fp->fp = NULL; 1129 fp->num = 0; 1130 } 1131 1132 uint32_t 1133 mlx5_get_supported_sw_parsing_offloads(const struct mlx5_hca_attr *attr) 1134 { 1135 uint32_t sw_parsing_offloads = 0; 1136 1137 if (attr->swp) { 1138 sw_parsing_offloads |= MLX5_SW_PARSING_CAP; 1139 if (attr->swp_csum) 1140 sw_parsing_offloads |= MLX5_SW_PARSING_CSUM_CAP; 1141 1142 if (attr->swp_lso) 1143 sw_parsing_offloads |= MLX5_SW_PARSING_TSO_CAP; 1144 } 1145 return sw_parsing_offloads; 1146 } 1147 1148 uint32_t 1149 mlx5_get_supported_tunneling_offloads(const struct mlx5_hca_attr *attr) 1150 { 1151 uint32_t tn_offloads = 0; 1152 1153 if (attr->tunnel_stateless_vxlan) 1154 tn_offloads |= MLX5_TUNNELED_OFFLOADS_VXLAN_CAP; 1155 if (attr->tunnel_stateless_gre) 1156 tn_offloads |= MLX5_TUNNELED_OFFLOADS_GRE_CAP; 1157 if (attr->tunnel_stateless_geneve_rx) 1158 tn_offloads |= MLX5_TUNNELED_OFFLOADS_GENEVE_CAP; 1159 return tn_offloads; 1160 } 1161 1162 /* Fill all fields of UAR structure. */ 1163 static int 1164 mlx5_rxtx_uars_prepare(struct mlx5_dev_ctx_shared *sh) 1165 { 1166 int ret; 1167 1168 ret = mlx5_devx_uar_prepare(sh->cdev, &sh->tx_uar); 1169 if (ret) { 1170 DRV_LOG(ERR, "Failed to prepare Tx DevX UAR."); 1171 return -rte_errno; 1172 } 1173 MLX5_ASSERT(sh->tx_uar.obj); 1174 MLX5_ASSERT(mlx5_os_get_devx_uar_base_addr(sh->tx_uar.obj)); 1175 ret = mlx5_devx_uar_prepare(sh->cdev, &sh->rx_uar); 1176 if (ret) { 1177 DRV_LOG(ERR, "Failed to prepare Rx DevX UAR."); 1178 mlx5_devx_uar_release(&sh->tx_uar); 1179 return -rte_errno; 1180 } 1181 MLX5_ASSERT(sh->rx_uar.obj); 1182 MLX5_ASSERT(mlx5_os_get_devx_uar_base_addr(sh->rx_uar.obj)); 1183 return 0; 1184 } 1185 1186 static void 1187 mlx5_rxtx_uars_release(struct mlx5_dev_ctx_shared *sh) 1188 { 1189 mlx5_devx_uar_release(&sh->rx_uar); 1190 mlx5_devx_uar_release(&sh->tx_uar); 1191 } 1192 1193 /** 1194 * rte_mempool_walk() callback to unregister Rx mempools. 1195 * It used when implicit mempool registration is disabled. 1196 * 1197 * @param mp 1198 * The mempool being walked. 1199 * @param arg 1200 * Pointer to the device shared context. 1201 */ 1202 static void 1203 mlx5_dev_ctx_shared_rx_mempool_unregister_cb(struct rte_mempool *mp, void *arg) 1204 { 1205 struct mlx5_dev_ctx_shared *sh = arg; 1206 1207 mlx5_dev_mempool_unregister(sh->cdev, mp); 1208 } 1209 1210 /** 1211 * Callback used when implicit mempool registration is disabled 1212 * in order to track Rx mempool destruction. 1213 * 1214 * @param event 1215 * Mempool life cycle event. 1216 * @param mp 1217 * An Rx mempool registered explicitly when the port is started. 1218 * @param arg 1219 * Pointer to a device shared context. 1220 */ 1221 static void 1222 mlx5_dev_ctx_shared_rx_mempool_event_cb(enum rte_mempool_event event, 1223 struct rte_mempool *mp, void *arg) 1224 { 1225 struct mlx5_dev_ctx_shared *sh = arg; 1226 1227 if (event == RTE_MEMPOOL_EVENT_DESTROY) 1228 mlx5_dev_mempool_unregister(sh->cdev, mp); 1229 } 1230 1231 int 1232 mlx5_dev_ctx_shared_mempool_subscribe(struct rte_eth_dev *dev) 1233 { 1234 struct mlx5_priv *priv = dev->data->dev_private; 1235 struct mlx5_dev_ctx_shared *sh = priv->sh; 1236 int ret; 1237 1238 /* Check if we only need to track Rx mempool destruction. */ 1239 if (!sh->cdev->config.mr_mempool_reg_en) { 1240 ret = rte_mempool_event_callback_register 1241 (mlx5_dev_ctx_shared_rx_mempool_event_cb, sh); 1242 return ret == 0 || rte_errno == EEXIST ? 0 : ret; 1243 } 1244 return mlx5_dev_mempool_subscribe(sh->cdev); 1245 } 1246 1247 /** 1248 * Set up multiple TISs with different affinities according to 1249 * number of bonding ports 1250 * 1251 * @param priv 1252 * Pointer of shared context. 1253 * 1254 * @return 1255 * Zero on success, -1 otherwise. 1256 */ 1257 static int 1258 mlx5_setup_tis(struct mlx5_dev_ctx_shared *sh) 1259 { 1260 int i; 1261 struct mlx5_devx_lag_context lag_ctx = { 0 }; 1262 struct mlx5_devx_tis_attr tis_attr = { 0 }; 1263 1264 tis_attr.transport_domain = sh->td->id; 1265 if (sh->bond.n_port) { 1266 if (!mlx5_devx_cmd_query_lag(sh->cdev->ctx, &lag_ctx)) { 1267 sh->lag.tx_remap_affinity[0] = 1268 lag_ctx.tx_remap_affinity_1; 1269 sh->lag.tx_remap_affinity[1] = 1270 lag_ctx.tx_remap_affinity_2; 1271 sh->lag.affinity_mode = lag_ctx.port_select_mode; 1272 } else { 1273 DRV_LOG(ERR, "Failed to query lag affinity."); 1274 return -1; 1275 } 1276 if (sh->lag.affinity_mode == MLX5_LAG_MODE_TIS) { 1277 for (i = 0; i < sh->bond.n_port; i++) { 1278 tis_attr.lag_tx_port_affinity = 1279 MLX5_IFC_LAG_MAP_TIS_AFFINITY(i, 1280 sh->bond.n_port); 1281 sh->tis[i] = mlx5_devx_cmd_create_tis(sh->cdev->ctx, 1282 &tis_attr); 1283 if (!sh->tis[i]) { 1284 DRV_LOG(ERR, "Failed to TIS %d/%d for bonding device" 1285 " %s.", i, sh->bond.n_port, 1286 sh->ibdev_name); 1287 return -1; 1288 } 1289 } 1290 DRV_LOG(DEBUG, "LAG number of ports : %d, affinity_1 & 2 : pf%d & %d.\n", 1291 sh->bond.n_port, lag_ctx.tx_remap_affinity_1, 1292 lag_ctx.tx_remap_affinity_2); 1293 return 0; 1294 } 1295 if (sh->lag.affinity_mode == MLX5_LAG_MODE_HASH) 1296 DRV_LOG(INFO, "Device %s enabled HW hash based LAG.", 1297 sh->ibdev_name); 1298 } 1299 tis_attr.lag_tx_port_affinity = 0; 1300 sh->tis[0] = mlx5_devx_cmd_create_tis(sh->cdev->ctx, &tis_attr); 1301 if (!sh->tis[0]) { 1302 DRV_LOG(ERR, "Failed to TIS 0 for bonding device" 1303 " %s.", sh->ibdev_name); 1304 return -1; 1305 } 1306 return 0; 1307 } 1308 1309 /** 1310 * Verify and store value for share device argument. 1311 * 1312 * @param[in] key 1313 * Key argument to verify. 1314 * @param[in] val 1315 * Value associated with key. 1316 * @param opaque 1317 * User data. 1318 * 1319 * @return 1320 * 0 on success, a negative errno value otherwise and rte_errno is set. 1321 */ 1322 static int 1323 mlx5_dev_args_check_handler(const char *key, const char *val, void *opaque) 1324 { 1325 struct mlx5_sh_config *config = opaque; 1326 signed long tmp; 1327 1328 errno = 0; 1329 tmp = strtol(val, NULL, 0); 1330 if (errno) { 1331 rte_errno = errno; 1332 DRV_LOG(WARNING, "%s: \"%s\" is not a valid integer", key, val); 1333 return -rte_errno; 1334 } 1335 if (tmp < 0 && strcmp(MLX5_TX_PP, key) && strcmp(MLX5_TX_SKEW, key)) { 1336 /* Negative values are acceptable for some keys only. */ 1337 rte_errno = EINVAL; 1338 DRV_LOG(WARNING, "%s: invalid negative value \"%s\"", key, val); 1339 return -rte_errno; 1340 } 1341 if (strcmp(MLX5_TX_PP, key) == 0) { 1342 unsigned long mod = tmp >= 0 ? tmp : -tmp; 1343 1344 if (!mod) { 1345 DRV_LOG(ERR, "Zero Tx packet pacing parameter."); 1346 rte_errno = EINVAL; 1347 return -rte_errno; 1348 } 1349 config->tx_pp = tmp; 1350 } else if (strcmp(MLX5_TX_SKEW, key) == 0) { 1351 config->tx_skew = tmp; 1352 } else if (strcmp(MLX5_L3_VXLAN_EN, key) == 0) { 1353 config->l3_vxlan_en = !!tmp; 1354 } else if (strcmp(MLX5_VF_NL_EN, key) == 0) { 1355 config->vf_nl_en = !!tmp; 1356 } else if (strcmp(MLX5_DV_ESW_EN, key) == 0) { 1357 config->dv_esw_en = !!tmp; 1358 } else if (strcmp(MLX5_DV_FLOW_EN, key) == 0) { 1359 if (tmp > 2) { 1360 DRV_LOG(ERR, "Invalid %s parameter.", key); 1361 rte_errno = EINVAL; 1362 return -rte_errno; 1363 } 1364 config->dv_flow_en = tmp; 1365 } else if (strcmp(MLX5_DV_XMETA_EN, key) == 0) { 1366 if (tmp != MLX5_XMETA_MODE_LEGACY && 1367 tmp != MLX5_XMETA_MODE_META16 && 1368 tmp != MLX5_XMETA_MODE_META32 && 1369 tmp != MLX5_XMETA_MODE_MISS_INFO && 1370 tmp != MLX5_XMETA_MODE_META32_HWS) { 1371 DRV_LOG(ERR, "Invalid extensive metadata parameter."); 1372 rte_errno = EINVAL; 1373 return -rte_errno; 1374 } 1375 if (tmp != MLX5_XMETA_MODE_MISS_INFO) 1376 config->dv_xmeta_en = tmp; 1377 else 1378 config->dv_miss_info = 1; 1379 } else if (strcmp(MLX5_LACP_BY_USER, key) == 0) { 1380 config->lacp_by_user = !!tmp; 1381 } else if (strcmp(MLX5_RECLAIM_MEM, key) == 0) { 1382 if (tmp != MLX5_RCM_NONE && 1383 tmp != MLX5_RCM_LIGHT && 1384 tmp != MLX5_RCM_AGGR) { 1385 DRV_LOG(ERR, "Unrecognize %s: \"%s\"", key, val); 1386 rte_errno = EINVAL; 1387 return -rte_errno; 1388 } 1389 config->reclaim_mode = tmp; 1390 } else if (strcmp(MLX5_DECAP_EN, key) == 0) { 1391 config->decap_en = !!tmp; 1392 } else if (strcmp(MLX5_ALLOW_DUPLICATE_PATTERN, key) == 0) { 1393 config->allow_duplicate_pattern = !!tmp; 1394 } else if (strcmp(MLX5_FDB_DEFAULT_RULE_EN, key) == 0) { 1395 config->fdb_def_rule = !!tmp; 1396 } else if (strcmp(MLX5_HWS_CNT_SERVICE_CORE, key) == 0) { 1397 config->cnt_svc.service_core = tmp; 1398 } else if (strcmp(MLX5_HWS_CNT_CYCLE_TIME, key) == 0) { 1399 config->cnt_svc.cycle_time = tmp; 1400 } else if (strcmp(MLX5_REPR_MATCHING_EN, key) == 0) { 1401 config->repr_matching = !!tmp; 1402 } 1403 return 0; 1404 } 1405 1406 /** 1407 * Parse user device parameters and adjust them according to device 1408 * capabilities. 1409 * 1410 * @param sh 1411 * Pointer to shared device context. 1412 * @param mkvlist 1413 * Pointer to mlx5 kvargs control, can be NULL if there is no devargs. 1414 * @param config 1415 * Pointer to shared device configuration structure. 1416 * 1417 * @return 1418 * 0 on success, a negative errno value otherwise and rte_errno is set. 1419 */ 1420 static int 1421 mlx5_shared_dev_ctx_args_config(struct mlx5_dev_ctx_shared *sh, 1422 struct mlx5_kvargs_ctrl *mkvlist, 1423 struct mlx5_sh_config *config) 1424 { 1425 const char **params = (const char *[]){ 1426 MLX5_TX_PP, 1427 MLX5_TX_SKEW, 1428 MLX5_L3_VXLAN_EN, 1429 MLX5_VF_NL_EN, 1430 MLX5_DV_ESW_EN, 1431 MLX5_DV_FLOW_EN, 1432 MLX5_DV_XMETA_EN, 1433 MLX5_LACP_BY_USER, 1434 MLX5_RECLAIM_MEM, 1435 MLX5_DECAP_EN, 1436 MLX5_ALLOW_DUPLICATE_PATTERN, 1437 MLX5_FDB_DEFAULT_RULE_EN, 1438 MLX5_HWS_CNT_SERVICE_CORE, 1439 MLX5_HWS_CNT_CYCLE_TIME, 1440 MLX5_REPR_MATCHING_EN, 1441 NULL, 1442 }; 1443 int ret = 0; 1444 1445 /* Default configuration. */ 1446 memset(config, 0, sizeof(*config)); 1447 config->vf_nl_en = 1; 1448 config->dv_esw_en = 1; 1449 config->dv_flow_en = 1; 1450 config->decap_en = 1; 1451 config->allow_duplicate_pattern = 1; 1452 config->fdb_def_rule = 1; 1453 config->cnt_svc.cycle_time = MLX5_CNT_SVC_CYCLE_TIME_DEFAULT; 1454 config->cnt_svc.service_core = rte_get_main_lcore(); 1455 config->repr_matching = 1; 1456 if (mkvlist != NULL) { 1457 /* Process parameters. */ 1458 ret = mlx5_kvargs_process(mkvlist, params, 1459 mlx5_dev_args_check_handler, config); 1460 if (ret) { 1461 DRV_LOG(ERR, "Failed to process device arguments: %s", 1462 strerror(rte_errno)); 1463 return -rte_errno; 1464 } 1465 } 1466 /* Adjust parameters according to device capabilities. */ 1467 if (config->dv_flow_en && !sh->dev_cap.dv_flow_en) { 1468 DRV_LOG(WARNING, "DV flow is not supported."); 1469 config->dv_flow_en = 0; 1470 } 1471 if (config->dv_esw_en && !sh->dev_cap.dv_esw_en) { 1472 DRV_LOG(DEBUG, "E-Switch DV flow is not supported."); 1473 config->dv_esw_en = 0; 1474 } 1475 if (config->dv_esw_en && !config->dv_flow_en) { 1476 DRV_LOG(DEBUG, 1477 "E-Switch DV flow is supported only when DV flow is enabled."); 1478 config->dv_esw_en = 0; 1479 } 1480 if (config->dv_miss_info && config->dv_esw_en) 1481 config->dv_xmeta_en = MLX5_XMETA_MODE_META16; 1482 if (!config->dv_esw_en && 1483 config->dv_xmeta_en != MLX5_XMETA_MODE_LEGACY) { 1484 DRV_LOG(WARNING, 1485 "Metadata mode %u is not supported (no E-Switch).", 1486 config->dv_xmeta_en); 1487 config->dv_xmeta_en = MLX5_XMETA_MODE_LEGACY; 1488 } 1489 if (config->dv_flow_en != 2 && !config->repr_matching) { 1490 DRV_LOG(DEBUG, "Disabling representor matching is valid only " 1491 "when HW Steering is enabled."); 1492 config->repr_matching = 1; 1493 } 1494 if (config->tx_pp && !sh->dev_cap.txpp_en) { 1495 DRV_LOG(ERR, "Packet pacing is not supported."); 1496 rte_errno = ENODEV; 1497 return -rte_errno; 1498 } 1499 if (!config->tx_pp && config->tx_skew && 1500 !sh->cdev->config.hca_attr.wait_on_time) { 1501 DRV_LOG(WARNING, 1502 "\"tx_skew\" doesn't affect without \"tx_pp\"."); 1503 } 1504 /* Check for LRO support. */ 1505 if (mlx5_devx_obj_ops_en(sh) && sh->cdev->config.hca_attr.lro_cap) { 1506 /* TBD check tunnel lro caps. */ 1507 config->lro_allowed = 1; 1508 DRV_LOG(DEBUG, "LRO is allowed."); 1509 DRV_LOG(DEBUG, 1510 "LRO minimal size of TCP segment required for coalescing is %d bytes.", 1511 sh->cdev->config.hca_attr.lro_min_mss_size); 1512 } 1513 /* 1514 * If HW has bug working with tunnel packet decapsulation and scatter 1515 * FCS, and decapsulation is needed, clear the hw_fcs_strip bit. 1516 * Then RTE_ETH_RX_OFFLOAD_KEEP_CRC bit will not be set anymore. 1517 */ 1518 if (sh->dev_cap.scatter_fcs_w_decap_disable && sh->config.decap_en) 1519 config->hw_fcs_strip = 0; 1520 else 1521 config->hw_fcs_strip = sh->dev_cap.hw_fcs_strip; 1522 DRV_LOG(DEBUG, "FCS stripping configuration is %ssupported", 1523 (config->hw_fcs_strip ? "" : "not ")); 1524 DRV_LOG(DEBUG, "\"tx_pp\" is %d.", config->tx_pp); 1525 DRV_LOG(DEBUG, "\"tx_skew\" is %d.", config->tx_skew); 1526 DRV_LOG(DEBUG, "\"reclaim_mode\" is %u.", config->reclaim_mode); 1527 DRV_LOG(DEBUG, "\"dv_esw_en\" is %u.", config->dv_esw_en); 1528 DRV_LOG(DEBUG, "\"dv_flow_en\" is %u.", config->dv_flow_en); 1529 DRV_LOG(DEBUG, "\"dv_xmeta_en\" is %u.", config->dv_xmeta_en); 1530 DRV_LOG(DEBUG, "\"dv_miss_info\" is %u.", config->dv_miss_info); 1531 DRV_LOG(DEBUG, "\"l3_vxlan_en\" is %u.", config->l3_vxlan_en); 1532 DRV_LOG(DEBUG, "\"vf_nl_en\" is %u.", config->vf_nl_en); 1533 DRV_LOG(DEBUG, "\"lacp_by_user\" is %u.", config->lacp_by_user); 1534 DRV_LOG(DEBUG, "\"decap_en\" is %u.", config->decap_en); 1535 DRV_LOG(DEBUG, "\"allow_duplicate_pattern\" is %u.", 1536 config->allow_duplicate_pattern); 1537 DRV_LOG(DEBUG, "\"fdb_def_rule_en\" is %u.", config->fdb_def_rule); 1538 DRV_LOG(DEBUG, "\"repr_matching_en\" is %u.", config->repr_matching); 1539 return 0; 1540 } 1541 1542 /** 1543 * Configure realtime timestamp format. 1544 * 1545 * @param sh 1546 * Pointer to mlx5_dev_ctx_shared object. 1547 * @param hca_attr 1548 * Pointer to DevX HCA capabilities structure. 1549 */ 1550 void 1551 mlx5_rt_timestamp_config(struct mlx5_dev_ctx_shared *sh, 1552 struct mlx5_hca_attr *hca_attr) 1553 { 1554 uint32_t dw_cnt = MLX5_ST_SZ_DW(register_mtutc); 1555 uint32_t reg[dw_cnt]; 1556 int ret = ENOTSUP; 1557 1558 if (hca_attr->access_register_user) 1559 ret = mlx5_devx_cmd_register_read(sh->cdev->ctx, 1560 MLX5_REGISTER_ID_MTUTC, 0, 1561 reg, dw_cnt); 1562 if (!ret) { 1563 uint32_t ts_mode; 1564 1565 /* MTUTC register is read successfully. */ 1566 ts_mode = MLX5_GET(register_mtutc, reg, time_stamp_mode); 1567 if (ts_mode == MLX5_MTUTC_TIMESTAMP_MODE_REAL_TIME) 1568 sh->dev_cap.rt_timestamp = 1; 1569 } else { 1570 /* Kernel does not support register reading. */ 1571 if (hca_attr->dev_freq_khz == (NS_PER_S / MS_PER_S)) 1572 sh->dev_cap.rt_timestamp = 1; 1573 } 1574 } 1575 1576 /** 1577 * Allocate shared device context. If there is multiport device the 1578 * master and representors will share this context, if there is single 1579 * port dedicated device, the context will be used by only given 1580 * port due to unification. 1581 * 1582 * Routine first searches the context for the specified device name, 1583 * if found the shared context assumed and reference counter is incremented. 1584 * If no context found the new one is created and initialized with specified 1585 * device context and parameters. 1586 * 1587 * @param[in] spawn 1588 * Pointer to the device attributes (name, port, etc). 1589 * @param mkvlist 1590 * Pointer to mlx5 kvargs control, can be NULL if there is no devargs. 1591 * 1592 * @return 1593 * Pointer to mlx5_dev_ctx_shared object on success, 1594 * otherwise NULL and rte_errno is set. 1595 */ 1596 struct mlx5_dev_ctx_shared * 1597 mlx5_alloc_shared_dev_ctx(const struct mlx5_dev_spawn_data *spawn, 1598 struct mlx5_kvargs_ctrl *mkvlist) 1599 { 1600 struct mlx5_dev_ctx_shared *sh; 1601 int err = 0; 1602 uint32_t i; 1603 1604 MLX5_ASSERT(spawn); 1605 /* Secondary process should not create the shared context. */ 1606 MLX5_ASSERT(rte_eal_process_type() == RTE_PROC_PRIMARY); 1607 pthread_mutex_lock(&mlx5_dev_ctx_list_mutex); 1608 /* Search for IB context by device name. */ 1609 LIST_FOREACH(sh, &mlx5_dev_ctx_list, next) { 1610 if (!strcmp(sh->ibdev_name, spawn->phys_dev_name)) { 1611 sh->refcnt++; 1612 goto exit; 1613 } 1614 } 1615 /* No device found, we have to create new shared context. */ 1616 MLX5_ASSERT(spawn->max_port); 1617 sh = mlx5_malloc(MLX5_MEM_ZERO | MLX5_MEM_RTE, 1618 sizeof(struct mlx5_dev_ctx_shared) + 1619 spawn->max_port * sizeof(struct mlx5_dev_shared_port), 1620 RTE_CACHE_LINE_SIZE, SOCKET_ID_ANY); 1621 if (!sh) { 1622 DRV_LOG(ERR, "Shared context allocation failure."); 1623 rte_errno = ENOMEM; 1624 goto exit; 1625 } 1626 pthread_mutex_init(&sh->txpp.mutex, NULL); 1627 sh->numa_node = spawn->cdev->dev->numa_node; 1628 sh->cdev = spawn->cdev; 1629 sh->esw_mode = !!(spawn->info.master || spawn->info.representor); 1630 if (spawn->bond_info) 1631 sh->bond = *spawn->bond_info; 1632 err = mlx5_os_capabilities_prepare(sh); 1633 if (err) { 1634 DRV_LOG(ERR, "Fail to configure device capabilities."); 1635 goto error; 1636 } 1637 err = mlx5_shared_dev_ctx_args_config(sh, mkvlist, &sh->config); 1638 if (err) { 1639 DRV_LOG(ERR, "Failed to process device configure: %s", 1640 strerror(rte_errno)); 1641 goto error; 1642 } 1643 sh->refcnt = 1; 1644 sh->max_port = spawn->max_port; 1645 strncpy(sh->ibdev_name, mlx5_os_get_ctx_device_name(sh->cdev->ctx), 1646 sizeof(sh->ibdev_name) - 1); 1647 strncpy(sh->ibdev_path, mlx5_os_get_ctx_device_path(sh->cdev->ctx), 1648 sizeof(sh->ibdev_path) - 1); 1649 /* 1650 * Setting port_id to max unallowed value means there is no interrupt 1651 * subhandler installed for the given port index i. 1652 */ 1653 for (i = 0; i < sh->max_port; i++) { 1654 sh->port[i].ih_port_id = RTE_MAX_ETHPORTS; 1655 sh->port[i].devx_ih_port_id = RTE_MAX_ETHPORTS; 1656 sh->port[i].nl_ih_port_id = RTE_MAX_ETHPORTS; 1657 } 1658 if (sh->cdev->config.devx) { 1659 sh->td = mlx5_devx_cmd_create_td(sh->cdev->ctx); 1660 if (!sh->td) { 1661 DRV_LOG(ERR, "TD allocation failure"); 1662 rte_errno = ENOMEM; 1663 goto error; 1664 } 1665 if (mlx5_setup_tis(sh)) { 1666 DRV_LOG(ERR, "TIS allocation failure"); 1667 rte_errno = ENOMEM; 1668 goto error; 1669 } 1670 err = mlx5_rxtx_uars_prepare(sh); 1671 if (err) 1672 goto error; 1673 #ifndef RTE_ARCH_64 1674 } else { 1675 /* Initialize UAR access locks for 32bit implementations. */ 1676 rte_spinlock_init(&sh->uar_lock_cq); 1677 for (i = 0; i < MLX5_UAR_PAGE_NUM_MAX; i++) 1678 rte_spinlock_init(&sh->uar_lock[i]); 1679 #endif 1680 } 1681 mlx5_os_dev_shared_handler_install(sh); 1682 if (LIST_EMPTY(&mlx5_dev_ctx_list)) { 1683 err = mlx5_flow_os_init_workspace_once(); 1684 if (err) 1685 goto error; 1686 } 1687 err = mlx5_flow_counters_mng_init(sh); 1688 if (err) { 1689 DRV_LOG(ERR, "Fail to initialize counters manage."); 1690 goto error; 1691 } 1692 mlx5_flow_aging_init(sh); 1693 mlx5_flow_ipool_create(sh); 1694 /* Add context to the global device list. */ 1695 LIST_INSERT_HEAD(&mlx5_dev_ctx_list, sh, next); 1696 rte_spinlock_init(&sh->geneve_tlv_opt_sl); 1697 exit: 1698 pthread_mutex_unlock(&mlx5_dev_ctx_list_mutex); 1699 return sh; 1700 error: 1701 err = rte_errno; 1702 pthread_mutex_destroy(&sh->txpp.mutex); 1703 pthread_mutex_unlock(&mlx5_dev_ctx_list_mutex); 1704 MLX5_ASSERT(sh); 1705 mlx5_rxtx_uars_release(sh); 1706 i = 0; 1707 do { 1708 if (sh->tis[i]) 1709 claim_zero(mlx5_devx_cmd_destroy(sh->tis[i])); 1710 } while (++i < (uint32_t)sh->bond.n_port); 1711 if (sh->td) 1712 claim_zero(mlx5_devx_cmd_destroy(sh->td)); 1713 mlx5_free(sh); 1714 rte_errno = err; 1715 return NULL; 1716 } 1717 1718 /** 1719 * Create LWM event_channel and interrupt handle for shared device 1720 * context. All rxqs sharing the device context share the event_channel. 1721 * A callback is registered in interrupt thread to receive the LWM event. 1722 * 1723 * @param[in] priv 1724 * Pointer to mlx5_priv instance. 1725 * 1726 * @return 1727 * 0 on success, negative with rte_errno set. 1728 */ 1729 int 1730 mlx5_lwm_setup(struct mlx5_priv *priv) 1731 { 1732 int fd_lwm; 1733 1734 pthread_mutex_init(&priv->sh->lwm_config_lock, NULL); 1735 priv->sh->devx_channel_lwm = mlx5_os_devx_create_event_channel 1736 (priv->sh->cdev->ctx, 1737 MLX5DV_DEVX_CREATE_EVENT_CHANNEL_FLAGS_OMIT_EV_DATA); 1738 if (!priv->sh->devx_channel_lwm) 1739 goto err; 1740 fd_lwm = mlx5_os_get_devx_channel_fd(priv->sh->devx_channel_lwm); 1741 priv->sh->intr_handle_lwm = mlx5_os_interrupt_handler_create 1742 (RTE_INTR_INSTANCE_F_SHARED, true, 1743 fd_lwm, mlx5_dev_interrupt_handler_lwm, priv); 1744 if (!priv->sh->intr_handle_lwm) 1745 goto err; 1746 return 0; 1747 err: 1748 if (priv->sh->devx_channel_lwm) { 1749 mlx5_os_devx_destroy_event_channel 1750 (priv->sh->devx_channel_lwm); 1751 priv->sh->devx_channel_lwm = NULL; 1752 } 1753 pthread_mutex_destroy(&priv->sh->lwm_config_lock); 1754 return -rte_errno; 1755 } 1756 1757 /** 1758 * Destroy LWM event_channel and interrupt handle for shared device 1759 * context before free this context. The interrupt handler is also 1760 * unregistered. 1761 * 1762 * @param[in] sh 1763 * Pointer to shared device context. 1764 */ 1765 void 1766 mlx5_lwm_unset(struct mlx5_dev_ctx_shared *sh) 1767 { 1768 if (sh->intr_handle_lwm) { 1769 mlx5_os_interrupt_handler_destroy(sh->intr_handle_lwm, 1770 mlx5_dev_interrupt_handler_lwm, (void *)-1); 1771 sh->intr_handle_lwm = NULL; 1772 } 1773 if (sh->devx_channel_lwm) { 1774 mlx5_os_devx_destroy_event_channel 1775 (sh->devx_channel_lwm); 1776 sh->devx_channel_lwm = NULL; 1777 } 1778 pthread_mutex_destroy(&sh->lwm_config_lock); 1779 } 1780 1781 /** 1782 * Free shared IB device context. Decrement counter and if zero free 1783 * all allocated resources and close handles. 1784 * 1785 * @param[in] sh 1786 * Pointer to mlx5_dev_ctx_shared object to free 1787 */ 1788 void 1789 mlx5_free_shared_dev_ctx(struct mlx5_dev_ctx_shared *sh) 1790 { 1791 int ret; 1792 int i = 0; 1793 1794 pthread_mutex_lock(&mlx5_dev_ctx_list_mutex); 1795 #ifdef RTE_LIBRTE_MLX5_DEBUG 1796 /* Check the object presence in the list. */ 1797 struct mlx5_dev_ctx_shared *lctx; 1798 1799 LIST_FOREACH(lctx, &mlx5_dev_ctx_list, next) 1800 if (lctx == sh) 1801 break; 1802 MLX5_ASSERT(lctx); 1803 if (lctx != sh) { 1804 DRV_LOG(ERR, "Freeing non-existing shared IB context"); 1805 goto exit; 1806 } 1807 #endif 1808 MLX5_ASSERT(sh); 1809 MLX5_ASSERT(sh->refcnt); 1810 /* Secondary process should not free the shared context. */ 1811 MLX5_ASSERT(rte_eal_process_type() == RTE_PROC_PRIMARY); 1812 if (--sh->refcnt) 1813 goto exit; 1814 /* Stop watching for mempool events and unregister all mempools. */ 1815 if (!sh->cdev->config.mr_mempool_reg_en) { 1816 ret = rte_mempool_event_callback_unregister 1817 (mlx5_dev_ctx_shared_rx_mempool_event_cb, sh); 1818 if (ret == 0) 1819 rte_mempool_walk 1820 (mlx5_dev_ctx_shared_rx_mempool_unregister_cb, sh); 1821 } 1822 /* Remove context from the global device list. */ 1823 LIST_REMOVE(sh, next); 1824 /* Release resources on the last device removal. */ 1825 if (LIST_EMPTY(&mlx5_dev_ctx_list)) { 1826 mlx5_os_net_cleanup(); 1827 mlx5_flow_os_release_workspace(); 1828 } 1829 pthread_mutex_unlock(&mlx5_dev_ctx_list_mutex); 1830 if (sh->flex_parsers_dv) { 1831 mlx5_list_destroy(sh->flex_parsers_dv); 1832 sh->flex_parsers_dv = NULL; 1833 } 1834 /* 1835 * Ensure there is no async event handler installed. 1836 * Only primary process handles async device events. 1837 **/ 1838 mlx5_flow_counters_mng_close(sh); 1839 if (sh->ct_mng) 1840 mlx5_flow_aso_ct_mng_close(sh); 1841 if (sh->aso_age_mng) { 1842 mlx5_flow_aso_age_mng_close(sh); 1843 sh->aso_age_mng = NULL; 1844 } 1845 if (sh->mtrmng) 1846 mlx5_aso_flow_mtrs_mng_close(sh); 1847 mlx5_flow_ipool_destroy(sh); 1848 mlx5_os_dev_shared_handler_uninstall(sh); 1849 mlx5_rxtx_uars_release(sh); 1850 do { 1851 if (sh->tis[i]) 1852 claim_zero(mlx5_devx_cmd_destroy(sh->tis[i])); 1853 } while (++i < sh->bond.n_port); 1854 if (sh->td) 1855 claim_zero(mlx5_devx_cmd_destroy(sh->td)); 1856 #ifdef HAVE_MLX5_HWS_SUPPORT 1857 /* HWS manages geneve_tlv_option resource as global. */ 1858 if (sh->config.dv_flow_en == 2) 1859 flow_dev_geneve_tlv_option_resource_release(sh); 1860 else 1861 #endif 1862 MLX5_ASSERT(sh->geneve_tlv_option_resource == NULL); 1863 pthread_mutex_destroy(&sh->txpp.mutex); 1864 mlx5_lwm_unset(sh); 1865 mlx5_free(sh); 1866 return; 1867 exit: 1868 pthread_mutex_unlock(&mlx5_dev_ctx_list_mutex); 1869 } 1870 1871 /** 1872 * Destroy table hash list. 1873 * 1874 * @param[in] priv 1875 * Pointer to the private device data structure. 1876 */ 1877 void 1878 mlx5_free_table_hash_list(struct mlx5_priv *priv) 1879 { 1880 struct mlx5_dev_ctx_shared *sh = priv->sh; 1881 struct mlx5_hlist **tbls = (priv->sh->config.dv_flow_en == 2) ? 1882 &sh->groups : &sh->flow_tbls; 1883 if (*tbls == NULL) 1884 return; 1885 mlx5_hlist_destroy(*tbls); 1886 *tbls = NULL; 1887 } 1888 1889 #ifdef HAVE_MLX5_HWS_SUPPORT 1890 /** 1891 * Allocate HW steering group hash list. 1892 * 1893 * @param[in] priv 1894 * Pointer to the private device data structure. 1895 */ 1896 static int 1897 mlx5_alloc_hw_group_hash_list(struct mlx5_priv *priv) 1898 { 1899 int err = 0; 1900 struct mlx5_dev_ctx_shared *sh = priv->sh; 1901 char s[MLX5_NAME_SIZE]; 1902 1903 MLX5_ASSERT(sh); 1904 snprintf(s, sizeof(s), "%s_flow_groups", priv->sh->ibdev_name); 1905 sh->groups = mlx5_hlist_create 1906 (s, MLX5_FLOW_TABLE_HLIST_ARRAY_SIZE, 1907 false, true, sh, 1908 flow_hw_grp_create_cb, 1909 flow_hw_grp_match_cb, 1910 flow_hw_grp_remove_cb, 1911 flow_hw_grp_clone_cb, 1912 flow_hw_grp_clone_free_cb); 1913 if (!sh->groups) { 1914 DRV_LOG(ERR, "flow groups with hash creation failed."); 1915 err = ENOMEM; 1916 } 1917 return err; 1918 } 1919 #endif 1920 1921 1922 /** 1923 * Initialize flow table hash list and create the root tables entry 1924 * for each domain. 1925 * 1926 * @param[in] priv 1927 * Pointer to the private device data structure. 1928 * 1929 * @return 1930 * Zero on success, positive error code otherwise. 1931 */ 1932 int 1933 mlx5_alloc_table_hash_list(struct mlx5_priv *priv __rte_unused) 1934 { 1935 int err = 0; 1936 1937 /* Tables are only used in DV and DR modes. */ 1938 #if defined(HAVE_IBV_FLOW_DV_SUPPORT) || !defined(HAVE_INFINIBAND_VERBS_H) 1939 struct mlx5_dev_ctx_shared *sh = priv->sh; 1940 char s[MLX5_NAME_SIZE]; 1941 1942 #ifdef HAVE_MLX5_HWS_SUPPORT 1943 if (priv->sh->config.dv_flow_en == 2) 1944 return mlx5_alloc_hw_group_hash_list(priv); 1945 #endif 1946 MLX5_ASSERT(sh); 1947 snprintf(s, sizeof(s), "%s_flow_table", priv->sh->ibdev_name); 1948 sh->flow_tbls = mlx5_hlist_create(s, MLX5_FLOW_TABLE_HLIST_ARRAY_SIZE, 1949 false, true, sh, 1950 flow_dv_tbl_create_cb, 1951 flow_dv_tbl_match_cb, 1952 flow_dv_tbl_remove_cb, 1953 flow_dv_tbl_clone_cb, 1954 flow_dv_tbl_clone_free_cb); 1955 if (!sh->flow_tbls) { 1956 DRV_LOG(ERR, "flow tables with hash creation failed."); 1957 err = ENOMEM; 1958 return err; 1959 } 1960 #ifndef HAVE_MLX5DV_DR 1961 struct rte_flow_error error; 1962 struct rte_eth_dev *dev = &rte_eth_devices[priv->dev_data->port_id]; 1963 1964 /* 1965 * In case we have not DR support, the zero tables should be created 1966 * because DV expect to see them even if they cannot be created by 1967 * RDMA-CORE. 1968 */ 1969 if (!flow_dv_tbl_resource_get(dev, 0, 0, 0, 0, 1970 NULL, 0, 1, 0, &error) || 1971 !flow_dv_tbl_resource_get(dev, 0, 1, 0, 0, 1972 NULL, 0, 1, 0, &error) || 1973 !flow_dv_tbl_resource_get(dev, 0, 0, 1, 0, 1974 NULL, 0, 1, 0, &error)) { 1975 err = ENOMEM; 1976 goto error; 1977 } 1978 return err; 1979 error: 1980 mlx5_free_table_hash_list(priv); 1981 #endif /* HAVE_MLX5DV_DR */ 1982 #endif 1983 return err; 1984 } 1985 1986 /** 1987 * Retrieve integer value from environment variable. 1988 * 1989 * @param[in] name 1990 * Environment variable name. 1991 * 1992 * @return 1993 * Integer value, 0 if the variable is not set. 1994 */ 1995 int 1996 mlx5_getenv_int(const char *name) 1997 { 1998 const char *val = getenv(name); 1999 2000 if (val == NULL) 2001 return 0; 2002 return atoi(val); 2003 } 2004 2005 /** 2006 * DPDK callback to add udp tunnel port 2007 * 2008 * @param[in] dev 2009 * A pointer to eth_dev 2010 * @param[in] udp_tunnel 2011 * A pointer to udp tunnel 2012 * 2013 * @return 2014 * 0 on valid udp ports and tunnels, -ENOTSUP otherwise. 2015 */ 2016 int 2017 mlx5_udp_tunnel_port_add(struct rte_eth_dev *dev __rte_unused, 2018 struct rte_eth_udp_tunnel *udp_tunnel) 2019 { 2020 MLX5_ASSERT(udp_tunnel != NULL); 2021 if (udp_tunnel->prot_type == RTE_ETH_TUNNEL_TYPE_VXLAN && 2022 udp_tunnel->udp_port == 4789) 2023 return 0; 2024 if (udp_tunnel->prot_type == RTE_ETH_TUNNEL_TYPE_VXLAN_GPE && 2025 udp_tunnel->udp_port == 4790) 2026 return 0; 2027 return -ENOTSUP; 2028 } 2029 2030 /** 2031 * Initialize process private data structure. 2032 * 2033 * @param dev 2034 * Pointer to Ethernet device structure. 2035 * 2036 * @return 2037 * 0 on success, a negative errno value otherwise and rte_errno is set. 2038 */ 2039 int 2040 mlx5_proc_priv_init(struct rte_eth_dev *dev) 2041 { 2042 struct mlx5_priv *priv = dev->data->dev_private; 2043 struct mlx5_proc_priv *ppriv; 2044 size_t ppriv_size; 2045 2046 mlx5_proc_priv_uninit(dev); 2047 /* 2048 * UAR register table follows the process private structure. BlueFlame 2049 * registers for Tx queues are stored in the table. 2050 */ 2051 ppriv_size = sizeof(struct mlx5_proc_priv) + 2052 priv->txqs_n * sizeof(struct mlx5_uar_data); 2053 ppriv = mlx5_malloc(MLX5_MEM_RTE | MLX5_MEM_ZERO, ppriv_size, 2054 RTE_CACHE_LINE_SIZE, dev->device->numa_node); 2055 if (!ppriv) { 2056 rte_errno = ENOMEM; 2057 return -rte_errno; 2058 } 2059 ppriv->uar_table_sz = priv->txqs_n; 2060 dev->process_private = ppriv; 2061 if (rte_eal_process_type() == RTE_PROC_PRIMARY) 2062 priv->sh->pppriv = ppriv; 2063 return 0; 2064 } 2065 2066 /** 2067 * Un-initialize process private data structure. 2068 * 2069 * @param dev 2070 * Pointer to Ethernet device structure. 2071 */ 2072 void 2073 mlx5_proc_priv_uninit(struct rte_eth_dev *dev) 2074 { 2075 struct mlx5_proc_priv *ppriv = dev->process_private; 2076 2077 if (!ppriv) 2078 return; 2079 if (ppriv->hca_bar) 2080 mlx5_txpp_unmap_hca_bar(dev); 2081 mlx5_free(dev->process_private); 2082 dev->process_private = NULL; 2083 } 2084 2085 /** 2086 * DPDK callback to close the device. 2087 * 2088 * Destroy all queues and objects, free memory. 2089 * 2090 * @param dev 2091 * Pointer to Ethernet device structure. 2092 */ 2093 int 2094 mlx5_dev_close(struct rte_eth_dev *dev) 2095 { 2096 struct mlx5_priv *priv = dev->data->dev_private; 2097 unsigned int i; 2098 int ret; 2099 2100 if (rte_eal_process_type() == RTE_PROC_SECONDARY) { 2101 /* Check if process_private released. */ 2102 if (!dev->process_private) 2103 return 0; 2104 mlx5_tx_uar_uninit_secondary(dev); 2105 mlx5_proc_priv_uninit(dev); 2106 rte_eth_dev_release_port(dev); 2107 return 0; 2108 } 2109 if (!priv->sh) 2110 return 0; 2111 if (priv->shared_refcnt) { 2112 DRV_LOG(ERR, "port %u is shared host in use (%u)", 2113 dev->data->port_id, priv->shared_refcnt); 2114 rte_errno = EBUSY; 2115 return -EBUSY; 2116 } 2117 DRV_LOG(DEBUG, "port %u closing device \"%s\"", 2118 dev->data->port_id, 2119 ((priv->sh->cdev->ctx != NULL) ? 2120 mlx5_os_get_ctx_device_name(priv->sh->cdev->ctx) : "")); 2121 /* 2122 * If default mreg copy action is removed at the stop stage, 2123 * the search will return none and nothing will be done anymore. 2124 */ 2125 if (priv->sh->config.dv_flow_en != 2) 2126 mlx5_flow_stop_default(dev); 2127 mlx5_traffic_disable(dev); 2128 /* 2129 * If all the flows are already flushed in the device stop stage, 2130 * then this will return directly without any action. 2131 */ 2132 mlx5_flow_list_flush(dev, MLX5_FLOW_TYPE_GEN, true); 2133 mlx5_action_handle_flush(dev); 2134 mlx5_flow_meter_flush(dev, NULL); 2135 /* Prevent crashes when queues are still in use. */ 2136 dev->rx_pkt_burst = rte_eth_pkt_burst_dummy; 2137 dev->tx_pkt_burst = rte_eth_pkt_burst_dummy; 2138 rte_wmb(); 2139 /* Disable datapath on secondary process. */ 2140 mlx5_mp_os_req_stop_rxtx(dev); 2141 /* Free the eCPRI flex parser resource. */ 2142 mlx5_flex_parser_ecpri_release(dev); 2143 mlx5_flex_item_port_cleanup(dev); 2144 #ifdef HAVE_MLX5_HWS_SUPPORT 2145 flow_hw_destroy_vport_action(dev); 2146 flow_hw_resource_release(dev); 2147 flow_hw_clear_port_info(dev); 2148 if (priv->sh->config.dv_flow_en == 2) { 2149 flow_hw_clear_flow_metadata_config(); 2150 flow_hw_clear_tags_set(dev); 2151 } 2152 #endif 2153 if (priv->rxq_privs != NULL) { 2154 /* XXX race condition if mlx5_rx_burst() is still running. */ 2155 rte_delay_us_sleep(1000); 2156 for (i = 0; (i != priv->rxqs_n); ++i) 2157 mlx5_rxq_release(dev, i); 2158 priv->rxqs_n = 0; 2159 mlx5_free(priv->rxq_privs); 2160 priv->rxq_privs = NULL; 2161 } 2162 if (priv->txqs != NULL) { 2163 /* XXX race condition if mlx5_tx_burst() is still running. */ 2164 rte_delay_us_sleep(1000); 2165 for (i = 0; (i != priv->txqs_n); ++i) 2166 mlx5_txq_release(dev, i); 2167 priv->txqs_n = 0; 2168 priv->txqs = NULL; 2169 } 2170 mlx5_proc_priv_uninit(dev); 2171 if (priv->q_counters) { 2172 mlx5_devx_cmd_destroy(priv->q_counters); 2173 priv->q_counters = NULL; 2174 } 2175 if (priv->drop_queue.hrxq) 2176 mlx5_drop_action_destroy(dev); 2177 if (priv->mreg_cp_tbl) 2178 mlx5_hlist_destroy(priv->mreg_cp_tbl); 2179 mlx5_mprq_free_mp(dev); 2180 mlx5_os_free_shared_dr(priv); 2181 if (priv->rss_conf.rss_key != NULL) 2182 mlx5_free(priv->rss_conf.rss_key); 2183 if (priv->reta_idx != NULL) 2184 mlx5_free(priv->reta_idx); 2185 if (priv->sh->dev_cap.vf) 2186 mlx5_os_mac_addr_flush(dev); 2187 if (priv->nl_socket_route >= 0) 2188 close(priv->nl_socket_route); 2189 if (priv->nl_socket_rdma >= 0) 2190 close(priv->nl_socket_rdma); 2191 if (priv->vmwa_context) 2192 mlx5_vlan_vmwa_exit(priv->vmwa_context); 2193 ret = mlx5_hrxq_verify(dev); 2194 if (ret) 2195 DRV_LOG(WARNING, "port %u some hash Rx queue still remain", 2196 dev->data->port_id); 2197 ret = mlx5_ind_table_obj_verify(dev); 2198 if (ret) 2199 DRV_LOG(WARNING, "port %u some indirection table still remain", 2200 dev->data->port_id); 2201 ret = mlx5_rxq_obj_verify(dev); 2202 if (ret) 2203 DRV_LOG(WARNING, "port %u some Rx queue objects still remain", 2204 dev->data->port_id); 2205 ret = mlx5_ext_rxq_verify(dev); 2206 if (ret) 2207 DRV_LOG(WARNING, "Port %u some external RxQ still remain.", 2208 dev->data->port_id); 2209 ret = mlx5_rxq_verify(dev); 2210 if (ret) 2211 DRV_LOG(WARNING, "port %u some Rx queues still remain", 2212 dev->data->port_id); 2213 ret = mlx5_txq_obj_verify(dev); 2214 if (ret) 2215 DRV_LOG(WARNING, "port %u some Verbs Tx queue still remain", 2216 dev->data->port_id); 2217 ret = mlx5_txq_verify(dev); 2218 if (ret) 2219 DRV_LOG(WARNING, "port %u some Tx queues still remain", 2220 dev->data->port_id); 2221 ret = mlx5_flow_verify(dev); 2222 if (ret) 2223 DRV_LOG(WARNING, "port %u some flows still remain", 2224 dev->data->port_id); 2225 if (priv->hrxqs) 2226 mlx5_list_destroy(priv->hrxqs); 2227 mlx5_free(priv->ext_rxqs); 2228 priv->sh->port[priv->dev_port - 1].nl_ih_port_id = RTE_MAX_ETHPORTS; 2229 /* 2230 * The interrupt handler port id must be reset before priv is reset 2231 * since 'mlx5_dev_interrupt_nl_cb' uses priv. 2232 */ 2233 rte_io_wmb(); 2234 /* 2235 * Free the shared context in last turn, because the cleanup 2236 * routines above may use some shared fields, like 2237 * mlx5_os_mac_addr_flush() uses ibdev_path for retrieving 2238 * ifindex if Netlink fails. 2239 */ 2240 mlx5_free_shared_dev_ctx(priv->sh); 2241 if (priv->domain_id != RTE_ETH_DEV_SWITCH_DOMAIN_ID_INVALID) { 2242 unsigned int c = 0; 2243 uint16_t port_id; 2244 2245 MLX5_ETH_FOREACH_DEV(port_id, dev->device) { 2246 struct mlx5_priv *opriv = 2247 rte_eth_devices[port_id].data->dev_private; 2248 2249 if (!opriv || 2250 opriv->domain_id != priv->domain_id || 2251 &rte_eth_devices[port_id] == dev) 2252 continue; 2253 ++c; 2254 break; 2255 } 2256 if (!c) 2257 claim_zero(rte_eth_switch_domain_free(priv->domain_id)); 2258 } 2259 memset(priv, 0, sizeof(*priv)); 2260 priv->domain_id = RTE_ETH_DEV_SWITCH_DOMAIN_ID_INVALID; 2261 /* 2262 * Reset mac_addrs to NULL such that it is not freed as part of 2263 * rte_eth_dev_release_port(). mac_addrs is part of dev_private so 2264 * it is freed when dev_private is freed. 2265 */ 2266 dev->data->mac_addrs = NULL; 2267 return 0; 2268 } 2269 2270 const struct eth_dev_ops mlx5_dev_ops = { 2271 .dev_configure = mlx5_dev_configure, 2272 .dev_start = mlx5_dev_start, 2273 .dev_stop = mlx5_dev_stop, 2274 .dev_set_link_down = mlx5_set_link_down, 2275 .dev_set_link_up = mlx5_set_link_up, 2276 .dev_close = mlx5_dev_close, 2277 .promiscuous_enable = mlx5_promiscuous_enable, 2278 .promiscuous_disable = mlx5_promiscuous_disable, 2279 .allmulticast_enable = mlx5_allmulticast_enable, 2280 .allmulticast_disable = mlx5_allmulticast_disable, 2281 .link_update = mlx5_link_update, 2282 .stats_get = mlx5_stats_get, 2283 .stats_reset = mlx5_stats_reset, 2284 .xstats_get = mlx5_xstats_get, 2285 .xstats_reset = mlx5_xstats_reset, 2286 .xstats_get_names = mlx5_xstats_get_names, 2287 .fw_version_get = mlx5_fw_version_get, 2288 .dev_infos_get = mlx5_dev_infos_get, 2289 .representor_info_get = mlx5_representor_info_get, 2290 .read_clock = mlx5_txpp_read_clock, 2291 .dev_supported_ptypes_get = mlx5_dev_supported_ptypes_get, 2292 .vlan_filter_set = mlx5_vlan_filter_set, 2293 .rx_queue_setup = mlx5_rx_queue_setup, 2294 .rx_queue_avail_thresh_set = mlx5_rx_queue_lwm_set, 2295 .rx_queue_avail_thresh_query = mlx5_rx_queue_lwm_query, 2296 .rx_hairpin_queue_setup = mlx5_rx_hairpin_queue_setup, 2297 .tx_queue_setup = mlx5_tx_queue_setup, 2298 .tx_hairpin_queue_setup = mlx5_tx_hairpin_queue_setup, 2299 .rx_queue_release = mlx5_rx_queue_release, 2300 .tx_queue_release = mlx5_tx_queue_release, 2301 .rx_queue_start = mlx5_rx_queue_start, 2302 .rx_queue_stop = mlx5_rx_queue_stop, 2303 .tx_queue_start = mlx5_tx_queue_start, 2304 .tx_queue_stop = mlx5_tx_queue_stop, 2305 .flow_ctrl_get = mlx5_dev_get_flow_ctrl, 2306 .flow_ctrl_set = mlx5_dev_set_flow_ctrl, 2307 .mac_addr_remove = mlx5_mac_addr_remove, 2308 .mac_addr_add = mlx5_mac_addr_add, 2309 .mac_addr_set = mlx5_mac_addr_set, 2310 .set_mc_addr_list = mlx5_set_mc_addr_list, 2311 .mtu_set = mlx5_dev_set_mtu, 2312 .vlan_strip_queue_set = mlx5_vlan_strip_queue_set, 2313 .vlan_offload_set = mlx5_vlan_offload_set, 2314 .reta_update = mlx5_dev_rss_reta_update, 2315 .reta_query = mlx5_dev_rss_reta_query, 2316 .rss_hash_update = mlx5_rss_hash_update, 2317 .rss_hash_conf_get = mlx5_rss_hash_conf_get, 2318 .flow_ops_get = mlx5_flow_ops_get, 2319 .rxq_info_get = mlx5_rxq_info_get, 2320 .txq_info_get = mlx5_txq_info_get, 2321 .rx_burst_mode_get = mlx5_rx_burst_mode_get, 2322 .tx_burst_mode_get = mlx5_tx_burst_mode_get, 2323 .rx_queue_intr_enable = mlx5_rx_intr_enable, 2324 .rx_queue_intr_disable = mlx5_rx_intr_disable, 2325 .is_removed = mlx5_is_removed, 2326 .udp_tunnel_port_add = mlx5_udp_tunnel_port_add, 2327 .get_module_info = mlx5_get_module_info, 2328 .get_module_eeprom = mlx5_get_module_eeprom, 2329 .hairpin_cap_get = mlx5_hairpin_cap_get, 2330 .mtr_ops_get = mlx5_flow_meter_ops_get, 2331 .hairpin_bind = mlx5_hairpin_bind, 2332 .hairpin_unbind = mlx5_hairpin_unbind, 2333 .hairpin_get_peer_ports = mlx5_hairpin_get_peer_ports, 2334 .hairpin_queue_peer_update = mlx5_hairpin_queue_peer_update, 2335 .hairpin_queue_peer_bind = mlx5_hairpin_queue_peer_bind, 2336 .hairpin_queue_peer_unbind = mlx5_hairpin_queue_peer_unbind, 2337 .get_monitor_addr = mlx5_get_monitor_addr, 2338 }; 2339 2340 /* Available operations from secondary process. */ 2341 const struct eth_dev_ops mlx5_dev_sec_ops = { 2342 .stats_get = mlx5_stats_get, 2343 .stats_reset = mlx5_stats_reset, 2344 .xstats_get = mlx5_xstats_get, 2345 .xstats_reset = mlx5_xstats_reset, 2346 .xstats_get_names = mlx5_xstats_get_names, 2347 .fw_version_get = mlx5_fw_version_get, 2348 .dev_infos_get = mlx5_dev_infos_get, 2349 .representor_info_get = mlx5_representor_info_get, 2350 .read_clock = mlx5_txpp_read_clock, 2351 .rx_queue_start = mlx5_rx_queue_start, 2352 .rx_queue_stop = mlx5_rx_queue_stop, 2353 .tx_queue_start = mlx5_tx_queue_start, 2354 .tx_queue_stop = mlx5_tx_queue_stop, 2355 .rxq_info_get = mlx5_rxq_info_get, 2356 .txq_info_get = mlx5_txq_info_get, 2357 .rx_burst_mode_get = mlx5_rx_burst_mode_get, 2358 .tx_burst_mode_get = mlx5_tx_burst_mode_get, 2359 .get_module_info = mlx5_get_module_info, 2360 .get_module_eeprom = mlx5_get_module_eeprom, 2361 }; 2362 2363 /* Available operations in flow isolated mode. */ 2364 const struct eth_dev_ops mlx5_dev_ops_isolate = { 2365 .dev_configure = mlx5_dev_configure, 2366 .dev_start = mlx5_dev_start, 2367 .dev_stop = mlx5_dev_stop, 2368 .dev_set_link_down = mlx5_set_link_down, 2369 .dev_set_link_up = mlx5_set_link_up, 2370 .dev_close = mlx5_dev_close, 2371 .promiscuous_enable = mlx5_promiscuous_enable, 2372 .promiscuous_disable = mlx5_promiscuous_disable, 2373 .allmulticast_enable = mlx5_allmulticast_enable, 2374 .allmulticast_disable = mlx5_allmulticast_disable, 2375 .link_update = mlx5_link_update, 2376 .stats_get = mlx5_stats_get, 2377 .stats_reset = mlx5_stats_reset, 2378 .xstats_get = mlx5_xstats_get, 2379 .xstats_reset = mlx5_xstats_reset, 2380 .xstats_get_names = mlx5_xstats_get_names, 2381 .fw_version_get = mlx5_fw_version_get, 2382 .dev_infos_get = mlx5_dev_infos_get, 2383 .representor_info_get = mlx5_representor_info_get, 2384 .read_clock = mlx5_txpp_read_clock, 2385 .dev_supported_ptypes_get = mlx5_dev_supported_ptypes_get, 2386 .vlan_filter_set = mlx5_vlan_filter_set, 2387 .rx_queue_setup = mlx5_rx_queue_setup, 2388 .rx_hairpin_queue_setup = mlx5_rx_hairpin_queue_setup, 2389 .tx_queue_setup = mlx5_tx_queue_setup, 2390 .tx_hairpin_queue_setup = mlx5_tx_hairpin_queue_setup, 2391 .rx_queue_release = mlx5_rx_queue_release, 2392 .tx_queue_release = mlx5_tx_queue_release, 2393 .rx_queue_start = mlx5_rx_queue_start, 2394 .rx_queue_stop = mlx5_rx_queue_stop, 2395 .tx_queue_start = mlx5_tx_queue_start, 2396 .tx_queue_stop = mlx5_tx_queue_stop, 2397 .flow_ctrl_get = mlx5_dev_get_flow_ctrl, 2398 .flow_ctrl_set = mlx5_dev_set_flow_ctrl, 2399 .mac_addr_remove = mlx5_mac_addr_remove, 2400 .mac_addr_add = mlx5_mac_addr_add, 2401 .mac_addr_set = mlx5_mac_addr_set, 2402 .set_mc_addr_list = mlx5_set_mc_addr_list, 2403 .mtu_set = mlx5_dev_set_mtu, 2404 .vlan_strip_queue_set = mlx5_vlan_strip_queue_set, 2405 .vlan_offload_set = mlx5_vlan_offload_set, 2406 .flow_ops_get = mlx5_flow_ops_get, 2407 .rxq_info_get = mlx5_rxq_info_get, 2408 .txq_info_get = mlx5_txq_info_get, 2409 .rx_burst_mode_get = mlx5_rx_burst_mode_get, 2410 .tx_burst_mode_get = mlx5_tx_burst_mode_get, 2411 .rx_queue_intr_enable = mlx5_rx_intr_enable, 2412 .rx_queue_intr_disable = mlx5_rx_intr_disable, 2413 .is_removed = mlx5_is_removed, 2414 .get_module_info = mlx5_get_module_info, 2415 .get_module_eeprom = mlx5_get_module_eeprom, 2416 .hairpin_cap_get = mlx5_hairpin_cap_get, 2417 .mtr_ops_get = mlx5_flow_meter_ops_get, 2418 .hairpin_bind = mlx5_hairpin_bind, 2419 .hairpin_unbind = mlx5_hairpin_unbind, 2420 .hairpin_get_peer_ports = mlx5_hairpin_get_peer_ports, 2421 .hairpin_queue_peer_update = mlx5_hairpin_queue_peer_update, 2422 .hairpin_queue_peer_bind = mlx5_hairpin_queue_peer_bind, 2423 .hairpin_queue_peer_unbind = mlx5_hairpin_queue_peer_unbind, 2424 .get_monitor_addr = mlx5_get_monitor_addr, 2425 }; 2426 2427 /** 2428 * Verify and store value for device argument. 2429 * 2430 * @param[in] key 2431 * Key argument to verify. 2432 * @param[in] val 2433 * Value associated with key. 2434 * @param opaque 2435 * User data. 2436 * 2437 * @return 2438 * 0 on success, a negative errno value otherwise and rte_errno is set. 2439 */ 2440 static int 2441 mlx5_port_args_check_handler(const char *key, const char *val, void *opaque) 2442 { 2443 struct mlx5_port_config *config = opaque; 2444 signed long tmp; 2445 2446 /* No-op, port representors are processed in mlx5_dev_spawn(). */ 2447 if (!strcmp(MLX5_REPRESENTOR, key)) 2448 return 0; 2449 errno = 0; 2450 tmp = strtol(val, NULL, 0); 2451 if (errno) { 2452 rte_errno = errno; 2453 DRV_LOG(WARNING, "%s: \"%s\" is not a valid integer", key, val); 2454 return -rte_errno; 2455 } 2456 if (tmp < 0) { 2457 /* Negative values are acceptable for some keys only. */ 2458 rte_errno = EINVAL; 2459 DRV_LOG(WARNING, "%s: invalid negative value \"%s\"", key, val); 2460 return -rte_errno; 2461 } 2462 if (strcmp(MLX5_RXQ_CQE_COMP_EN, key) == 0) { 2463 if (tmp > MLX5_CQE_RESP_FORMAT_L34H_STRIDX) { 2464 DRV_LOG(ERR, "invalid CQE compression " 2465 "format parameter"); 2466 rte_errno = EINVAL; 2467 return -rte_errno; 2468 } 2469 config->cqe_comp = !!tmp; 2470 config->cqe_comp_fmt = tmp; 2471 } else if (strcmp(MLX5_RXQ_PKT_PAD_EN, key) == 0) { 2472 config->hw_padding = !!tmp; 2473 } else if (strcmp(MLX5_RX_MPRQ_EN, key) == 0) { 2474 config->mprq.enabled = !!tmp; 2475 } else if (strcmp(MLX5_RX_MPRQ_LOG_STRIDE_NUM, key) == 0) { 2476 config->mprq.log_stride_num = tmp; 2477 } else if (strcmp(MLX5_RX_MPRQ_LOG_STRIDE_SIZE, key) == 0) { 2478 config->mprq.log_stride_size = tmp; 2479 } else if (strcmp(MLX5_RX_MPRQ_MAX_MEMCPY_LEN, key) == 0) { 2480 config->mprq.max_memcpy_len = tmp; 2481 } else if (strcmp(MLX5_RXQS_MIN_MPRQ, key) == 0) { 2482 config->mprq.min_rxqs_num = tmp; 2483 } else if (strcmp(MLX5_TXQ_INLINE, key) == 0) { 2484 DRV_LOG(WARNING, "%s: deprecated parameter," 2485 " converted to txq_inline_max", key); 2486 config->txq_inline_max = tmp; 2487 } else if (strcmp(MLX5_TXQ_INLINE_MAX, key) == 0) { 2488 config->txq_inline_max = tmp; 2489 } else if (strcmp(MLX5_TXQ_INLINE_MIN, key) == 0) { 2490 config->txq_inline_min = tmp; 2491 } else if (strcmp(MLX5_TXQ_INLINE_MPW, key) == 0) { 2492 config->txq_inline_mpw = tmp; 2493 } else if (strcmp(MLX5_TXQS_MIN_INLINE, key) == 0) { 2494 config->txqs_inline = tmp; 2495 } else if (strcmp(MLX5_TXQS_MAX_VEC, key) == 0) { 2496 DRV_LOG(WARNING, "%s: deprecated parameter, ignored", key); 2497 } else if (strcmp(MLX5_TXQ_MPW_EN, key) == 0) { 2498 config->mps = !!tmp; 2499 } else if (strcmp(MLX5_TXQ_MPW_HDR_DSEG_EN, key) == 0) { 2500 DRV_LOG(WARNING, "%s: deprecated parameter, ignored", key); 2501 } else if (strcmp(MLX5_TXQ_MAX_INLINE_LEN, key) == 0) { 2502 DRV_LOG(WARNING, "%s: deprecated parameter," 2503 " converted to txq_inline_mpw", key); 2504 config->txq_inline_mpw = tmp; 2505 } else if (strcmp(MLX5_TX_VEC_EN, key) == 0) { 2506 DRV_LOG(WARNING, "%s: deprecated parameter, ignored", key); 2507 } else if (strcmp(MLX5_RX_VEC_EN, key) == 0) { 2508 config->rx_vec_en = !!tmp; 2509 } else if (strcmp(MLX5_MAX_DUMP_FILES_NUM, key) == 0) { 2510 config->max_dump_files_num = tmp; 2511 } else if (strcmp(MLX5_LRO_TIMEOUT_USEC, key) == 0) { 2512 config->lro_timeout = tmp; 2513 } else if (strcmp(MLX5_HP_BUF_SIZE, key) == 0) { 2514 config->log_hp_size = tmp; 2515 } else if (strcmp(MLX5_DELAY_DROP, key) == 0) { 2516 config->std_delay_drop = !!(tmp & MLX5_DELAY_DROP_STANDARD); 2517 config->hp_delay_drop = !!(tmp & MLX5_DELAY_DROP_HAIRPIN); 2518 } 2519 return 0; 2520 } 2521 2522 /** 2523 * Parse user port parameters and adjust them according to device capabilities. 2524 * 2525 * @param priv 2526 * Pointer to shared device context. 2527 * @param mkvlist 2528 * Pointer to mlx5 kvargs control, can be NULL if there is no devargs. 2529 * @param config 2530 * Pointer to port configuration structure. 2531 * 2532 * @return 2533 * 0 on success, a negative errno value otherwise and rte_errno is set. 2534 */ 2535 int 2536 mlx5_port_args_config(struct mlx5_priv *priv, struct mlx5_kvargs_ctrl *mkvlist, 2537 struct mlx5_port_config *config) 2538 { 2539 struct mlx5_hca_attr *hca_attr = &priv->sh->cdev->config.hca_attr; 2540 struct mlx5_dev_cap *dev_cap = &priv->sh->dev_cap; 2541 bool devx = priv->sh->cdev->config.devx; 2542 const char **params = (const char *[]){ 2543 MLX5_RXQ_CQE_COMP_EN, 2544 MLX5_RXQ_PKT_PAD_EN, 2545 MLX5_RX_MPRQ_EN, 2546 MLX5_RX_MPRQ_LOG_STRIDE_NUM, 2547 MLX5_RX_MPRQ_LOG_STRIDE_SIZE, 2548 MLX5_RX_MPRQ_MAX_MEMCPY_LEN, 2549 MLX5_RXQS_MIN_MPRQ, 2550 MLX5_TXQ_INLINE, 2551 MLX5_TXQ_INLINE_MIN, 2552 MLX5_TXQ_INLINE_MAX, 2553 MLX5_TXQ_INLINE_MPW, 2554 MLX5_TXQS_MIN_INLINE, 2555 MLX5_TXQS_MAX_VEC, 2556 MLX5_TXQ_MPW_EN, 2557 MLX5_TXQ_MPW_HDR_DSEG_EN, 2558 MLX5_TXQ_MAX_INLINE_LEN, 2559 MLX5_TX_VEC_EN, 2560 MLX5_RX_VEC_EN, 2561 MLX5_REPRESENTOR, 2562 MLX5_MAX_DUMP_FILES_NUM, 2563 MLX5_LRO_TIMEOUT_USEC, 2564 MLX5_HP_BUF_SIZE, 2565 MLX5_DELAY_DROP, 2566 NULL, 2567 }; 2568 int ret = 0; 2569 2570 /* Default configuration. */ 2571 memset(config, 0, sizeof(*config)); 2572 config->mps = MLX5_ARG_UNSET; 2573 config->cqe_comp = 1; 2574 config->rx_vec_en = 1; 2575 config->txq_inline_max = MLX5_ARG_UNSET; 2576 config->txq_inline_min = MLX5_ARG_UNSET; 2577 config->txq_inline_mpw = MLX5_ARG_UNSET; 2578 config->txqs_inline = MLX5_ARG_UNSET; 2579 config->mprq.max_memcpy_len = MLX5_MPRQ_MEMCPY_DEFAULT_LEN; 2580 config->mprq.min_rxqs_num = MLX5_MPRQ_MIN_RXQS; 2581 config->mprq.log_stride_num = MLX5_MPRQ_DEFAULT_LOG_STRIDE_NUM; 2582 config->log_hp_size = MLX5_ARG_UNSET; 2583 config->std_delay_drop = 0; 2584 config->hp_delay_drop = 0; 2585 if (mkvlist != NULL) { 2586 /* Process parameters. */ 2587 ret = mlx5_kvargs_process(mkvlist, params, 2588 mlx5_port_args_check_handler, config); 2589 if (ret) { 2590 DRV_LOG(ERR, "Failed to process port arguments: %s", 2591 strerror(rte_errno)); 2592 return -rte_errno; 2593 } 2594 } 2595 /* Adjust parameters according to device capabilities. */ 2596 if (config->hw_padding && !dev_cap->hw_padding) { 2597 DRV_LOG(DEBUG, "Rx end alignment padding isn't supported."); 2598 config->hw_padding = 0; 2599 } else if (config->hw_padding) { 2600 DRV_LOG(DEBUG, "Rx end alignment padding is enabled."); 2601 } 2602 /* 2603 * MPW is disabled by default, while the Enhanced MPW is enabled 2604 * by default. 2605 */ 2606 if (config->mps == MLX5_ARG_UNSET) 2607 config->mps = (dev_cap->mps == MLX5_MPW_ENHANCED) ? 2608 MLX5_MPW_ENHANCED : MLX5_MPW_DISABLED; 2609 else 2610 config->mps = config->mps ? dev_cap->mps : MLX5_MPW_DISABLED; 2611 DRV_LOG(INFO, "%sMPS is %s", 2612 config->mps == MLX5_MPW_ENHANCED ? "enhanced " : 2613 config->mps == MLX5_MPW ? "legacy " : "", 2614 config->mps != MLX5_MPW_DISABLED ? "enabled" : "disabled"); 2615 if (priv->sh->config.lro_allowed) { 2616 /* 2617 * If LRO timeout is not configured by application, 2618 * use the minimal supported value. 2619 */ 2620 if (!config->lro_timeout) 2621 config->lro_timeout = 2622 hca_attr->lro_timer_supported_periods[0]; 2623 DRV_LOG(DEBUG, "LRO session timeout set to %d usec.", 2624 config->lro_timeout); 2625 } 2626 if (config->cqe_comp && !dev_cap->cqe_comp) { 2627 DRV_LOG(WARNING, "Rx CQE 128B compression is not supported."); 2628 config->cqe_comp = 0; 2629 } 2630 if (config->cqe_comp_fmt == MLX5_CQE_RESP_FORMAT_FTAG_STRIDX && 2631 (!devx || !hca_attr->mini_cqe_resp_flow_tag)) { 2632 DRV_LOG(WARNING, 2633 "Flow Tag CQE compression format isn't supported."); 2634 config->cqe_comp = 0; 2635 } 2636 if (config->cqe_comp_fmt == MLX5_CQE_RESP_FORMAT_L34H_STRIDX && 2637 (!devx || !hca_attr->mini_cqe_resp_l3_l4_tag)) { 2638 DRV_LOG(WARNING, 2639 "L3/L4 Header CQE compression format isn't supported."); 2640 config->cqe_comp = 0; 2641 } 2642 DRV_LOG(DEBUG, "Rx CQE compression is %ssupported.", 2643 config->cqe_comp ? "" : "not "); 2644 if ((config->std_delay_drop || config->hp_delay_drop) && 2645 !dev_cap->rq_delay_drop_en) { 2646 config->std_delay_drop = 0; 2647 config->hp_delay_drop = 0; 2648 DRV_LOG(WARNING, "dev_port-%u: Rxq delay drop isn't supported.", 2649 priv->dev_port); 2650 } 2651 if (config->mprq.enabled && !priv->sh->dev_cap.mprq.enabled) { 2652 DRV_LOG(WARNING, "Multi-Packet RQ isn't supported."); 2653 config->mprq.enabled = 0; 2654 } 2655 if (config->max_dump_files_num == 0) 2656 config->max_dump_files_num = 128; 2657 /* Detect minimal data bytes to inline. */ 2658 mlx5_set_min_inline(priv); 2659 DRV_LOG(DEBUG, "VLAN insertion in WQE is %ssupported.", 2660 config->hw_vlan_insert ? "" : "not "); 2661 DRV_LOG(DEBUG, "\"rxq_pkt_pad_en\" is %u.", config->hw_padding); 2662 DRV_LOG(DEBUG, "\"rxq_cqe_comp_en\" is %u.", config->cqe_comp); 2663 DRV_LOG(DEBUG, "\"cqe_comp_fmt\" is %u.", config->cqe_comp_fmt); 2664 DRV_LOG(DEBUG, "\"rx_vec_en\" is %u.", config->rx_vec_en); 2665 DRV_LOG(DEBUG, "Standard \"delay_drop\" is %u.", 2666 config->std_delay_drop); 2667 DRV_LOG(DEBUG, "Hairpin \"delay_drop\" is %u.", config->hp_delay_drop); 2668 DRV_LOG(DEBUG, "\"max_dump_files_num\" is %u.", 2669 config->max_dump_files_num); 2670 DRV_LOG(DEBUG, "\"log_hp_size\" is %u.", config->log_hp_size); 2671 DRV_LOG(DEBUG, "\"mprq_en\" is %u.", config->mprq.enabled); 2672 DRV_LOG(DEBUG, "\"mprq_log_stride_num\" is %u.", 2673 config->mprq.log_stride_num); 2674 DRV_LOG(DEBUG, "\"mprq_log_stride_size\" is %u.", 2675 config->mprq.log_stride_size); 2676 DRV_LOG(DEBUG, "\"mprq_max_memcpy_len\" is %u.", 2677 config->mprq.max_memcpy_len); 2678 DRV_LOG(DEBUG, "\"rxqs_min_mprq\" is %u.", config->mprq.min_rxqs_num); 2679 DRV_LOG(DEBUG, "\"lro_timeout_usec\" is %u.", config->lro_timeout); 2680 DRV_LOG(DEBUG, "\"txq_mpw_en\" is %d.", config->mps); 2681 DRV_LOG(DEBUG, "\"txqs_min_inline\" is %d.", config->txqs_inline); 2682 DRV_LOG(DEBUG, "\"txq_inline_min\" is %d.", config->txq_inline_min); 2683 DRV_LOG(DEBUG, "\"txq_inline_max\" is %d.", config->txq_inline_max); 2684 DRV_LOG(DEBUG, "\"txq_inline_mpw\" is %d.", config->txq_inline_mpw); 2685 return 0; 2686 } 2687 2688 /** 2689 * Print the key for device argument. 2690 * 2691 * It is "dummy" handler whose whole purpose is to enable using 2692 * mlx5_kvargs_process() function which set devargs as used. 2693 * 2694 * @param key 2695 * Key argument. 2696 * @param val 2697 * Value associated with key, unused. 2698 * @param opaque 2699 * Unused, can be NULL. 2700 * 2701 * @return 2702 * 0 on success, function cannot fail. 2703 */ 2704 static int 2705 mlx5_dummy_handler(const char *key, const char *val, void *opaque) 2706 { 2707 DRV_LOG(DEBUG, "\tKey: \"%s\" is set as used.", key); 2708 RTE_SET_USED(opaque); 2709 RTE_SET_USED(val); 2710 return 0; 2711 } 2712 2713 /** 2714 * Set requested devargs as used when device is already spawned. 2715 * 2716 * It is necessary since it is valid to ask probe again for existing device, 2717 * if its devargs don't assign as used, mlx5_kvargs_validate() will fail. 2718 * 2719 * @param name 2720 * Name of the existing device. 2721 * @param port_id 2722 * Port identifier of the device. 2723 * @param mkvlist 2724 * Pointer to mlx5 kvargs control to sign as used. 2725 */ 2726 void 2727 mlx5_port_args_set_used(const char *name, uint16_t port_id, 2728 struct mlx5_kvargs_ctrl *mkvlist) 2729 { 2730 const char **params = (const char *[]){ 2731 MLX5_RXQ_CQE_COMP_EN, 2732 MLX5_RXQ_PKT_PAD_EN, 2733 MLX5_RX_MPRQ_EN, 2734 MLX5_RX_MPRQ_LOG_STRIDE_NUM, 2735 MLX5_RX_MPRQ_LOG_STRIDE_SIZE, 2736 MLX5_RX_MPRQ_MAX_MEMCPY_LEN, 2737 MLX5_RXQS_MIN_MPRQ, 2738 MLX5_TXQ_INLINE, 2739 MLX5_TXQ_INLINE_MIN, 2740 MLX5_TXQ_INLINE_MAX, 2741 MLX5_TXQ_INLINE_MPW, 2742 MLX5_TXQS_MIN_INLINE, 2743 MLX5_TXQS_MAX_VEC, 2744 MLX5_TXQ_MPW_EN, 2745 MLX5_TXQ_MPW_HDR_DSEG_EN, 2746 MLX5_TXQ_MAX_INLINE_LEN, 2747 MLX5_TX_VEC_EN, 2748 MLX5_RX_VEC_EN, 2749 MLX5_REPRESENTOR, 2750 MLX5_MAX_DUMP_FILES_NUM, 2751 MLX5_LRO_TIMEOUT_USEC, 2752 MLX5_HP_BUF_SIZE, 2753 MLX5_DELAY_DROP, 2754 NULL, 2755 }; 2756 2757 /* Secondary process should not handle devargs. */ 2758 if (rte_eal_process_type() != RTE_PROC_PRIMARY) 2759 return; 2760 MLX5_ASSERT(mkvlist != NULL); 2761 DRV_LOG(DEBUG, "Ethernet device \"%s\" for port %u " 2762 "already exists, set devargs as used:", name, port_id); 2763 /* This function cannot fail with this handler. */ 2764 mlx5_kvargs_process(mkvlist, params, mlx5_dummy_handler, NULL); 2765 } 2766 2767 /** 2768 * Check sibling device configurations when probing again. 2769 * 2770 * Sibling devices sharing infiniband device context should have compatible 2771 * configurations. This regards representors and bonding device. 2772 * 2773 * @param cdev 2774 * Pointer to mlx5 device structure. 2775 * @param mkvlist 2776 * Pointer to mlx5 kvargs control, can be NULL if there is no devargs. 2777 * 2778 * @return 2779 * 0 on success, a negative errno value otherwise and rte_errno is set. 2780 */ 2781 int 2782 mlx5_probe_again_args_validate(struct mlx5_common_device *cdev, 2783 struct mlx5_kvargs_ctrl *mkvlist) 2784 { 2785 struct mlx5_dev_ctx_shared *sh = NULL; 2786 struct mlx5_sh_config *config; 2787 int ret; 2788 2789 /* Secondary process should not handle devargs. */ 2790 if (rte_eal_process_type() != RTE_PROC_PRIMARY) 2791 return 0; 2792 pthread_mutex_lock(&mlx5_dev_ctx_list_mutex); 2793 /* Search for IB context by common device pointer. */ 2794 LIST_FOREACH(sh, &mlx5_dev_ctx_list, next) 2795 if (sh->cdev == cdev) 2796 break; 2797 pthread_mutex_unlock(&mlx5_dev_ctx_list_mutex); 2798 /* There is sh for this device -> it isn't probe again. */ 2799 if (sh == NULL) 2800 return 0; 2801 config = mlx5_malloc(MLX5_MEM_ZERO | MLX5_MEM_RTE, 2802 sizeof(struct mlx5_sh_config), 2803 RTE_CACHE_LINE_SIZE, SOCKET_ID_ANY); 2804 if (config == NULL) { 2805 rte_errno = -ENOMEM; 2806 return -rte_errno; 2807 } 2808 /* 2809 * Creates a temporary IB context configure structure according to new 2810 * devargs attached in probing again. 2811 */ 2812 ret = mlx5_shared_dev_ctx_args_config(sh, mkvlist, config); 2813 if (ret) { 2814 DRV_LOG(ERR, "Failed to process device configure: %s", 2815 strerror(rte_errno)); 2816 mlx5_free(config); 2817 return ret; 2818 } 2819 /* 2820 * Checks the match between the temporary structure and the existing 2821 * IB context structure. 2822 */ 2823 if (sh->config.dv_flow_en ^ config->dv_flow_en) { 2824 DRV_LOG(ERR, "\"dv_flow_en\" " 2825 "configuration mismatch for shared %s context.", 2826 sh->ibdev_name); 2827 goto error; 2828 } 2829 if ((sh->config.dv_xmeta_en ^ config->dv_xmeta_en) || 2830 (sh->config.dv_miss_info ^ config->dv_miss_info)) { 2831 DRV_LOG(ERR, "\"dv_xmeta_en\" " 2832 "configuration mismatch for shared %s context.", 2833 sh->ibdev_name); 2834 goto error; 2835 } 2836 if (sh->config.dv_esw_en ^ config->dv_esw_en) { 2837 DRV_LOG(ERR, "\"dv_esw_en\" " 2838 "configuration mismatch for shared %s context.", 2839 sh->ibdev_name); 2840 goto error; 2841 } 2842 if (sh->config.reclaim_mode ^ config->reclaim_mode) { 2843 DRV_LOG(ERR, "\"reclaim_mode\" " 2844 "configuration mismatch for shared %s context.", 2845 sh->ibdev_name); 2846 goto error; 2847 } 2848 if (sh->config.allow_duplicate_pattern ^ 2849 config->allow_duplicate_pattern) { 2850 DRV_LOG(ERR, "\"allow_duplicate_pattern\" " 2851 "configuration mismatch for shared %s context.", 2852 sh->ibdev_name); 2853 goto error; 2854 } 2855 if (sh->config.fdb_def_rule ^ config->fdb_def_rule) { 2856 DRV_LOG(ERR, "\"fdb_def_rule_en\" configuration mismatch for shared %s context.", 2857 sh->ibdev_name); 2858 goto error; 2859 } 2860 if (sh->config.l3_vxlan_en ^ config->l3_vxlan_en) { 2861 DRV_LOG(ERR, "\"l3_vxlan_en\" " 2862 "configuration mismatch for shared %s context.", 2863 sh->ibdev_name); 2864 goto error; 2865 } 2866 if (sh->config.decap_en ^ config->decap_en) { 2867 DRV_LOG(ERR, "\"decap_en\" " 2868 "configuration mismatch for shared %s context.", 2869 sh->ibdev_name); 2870 goto error; 2871 } 2872 if (sh->config.lacp_by_user ^ config->lacp_by_user) { 2873 DRV_LOG(ERR, "\"lacp_by_user\" " 2874 "configuration mismatch for shared %s context.", 2875 sh->ibdev_name); 2876 goto error; 2877 } 2878 if (sh->config.tx_pp ^ config->tx_pp) { 2879 DRV_LOG(ERR, "\"tx_pp\" " 2880 "configuration mismatch for shared %s context.", 2881 sh->ibdev_name); 2882 goto error; 2883 } 2884 if (sh->config.tx_skew ^ config->tx_skew) { 2885 DRV_LOG(ERR, "\"tx_skew\" " 2886 "configuration mismatch for shared %s context.", 2887 sh->ibdev_name); 2888 goto error; 2889 } 2890 mlx5_free(config); 2891 return 0; 2892 error: 2893 mlx5_free(config); 2894 rte_errno = EINVAL; 2895 return -rte_errno; 2896 } 2897 2898 /** 2899 * Configures the minimal amount of data to inline into WQE 2900 * while sending packets. 2901 * 2902 * - the txq_inline_min has the maximal priority, if this 2903 * key is specified in devargs 2904 * - if DevX is enabled the inline mode is queried from the 2905 * device (HCA attributes and NIC vport context if needed). 2906 * - otherwise L2 mode (18 bytes) is assumed for ConnectX-4/4 Lx 2907 * and none (0 bytes) for other NICs 2908 * 2909 * @param priv 2910 * Pointer to the private device data structure. 2911 */ 2912 void 2913 mlx5_set_min_inline(struct mlx5_priv *priv) 2914 { 2915 struct mlx5_hca_attr *hca_attr = &priv->sh->cdev->config.hca_attr; 2916 struct mlx5_port_config *config = &priv->config; 2917 2918 if (config->txq_inline_min != MLX5_ARG_UNSET) { 2919 /* Application defines size of inlined data explicitly. */ 2920 if (priv->pci_dev != NULL) { 2921 switch (priv->pci_dev->id.device_id) { 2922 case PCI_DEVICE_ID_MELLANOX_CONNECTX4: 2923 case PCI_DEVICE_ID_MELLANOX_CONNECTX4VF: 2924 if (config->txq_inline_min < 2925 (int)MLX5_INLINE_HSIZE_L2) { 2926 DRV_LOG(DEBUG, 2927 "txq_inline_mix aligned to minimal ConnectX-4 required value %d", 2928 (int)MLX5_INLINE_HSIZE_L2); 2929 config->txq_inline_min = 2930 MLX5_INLINE_HSIZE_L2; 2931 } 2932 break; 2933 } 2934 } 2935 goto exit; 2936 } 2937 if (hca_attr->eth_net_offloads) { 2938 /* We have DevX enabled, inline mode queried successfully. */ 2939 switch (hca_attr->wqe_inline_mode) { 2940 case MLX5_CAP_INLINE_MODE_L2: 2941 /* outer L2 header must be inlined. */ 2942 config->txq_inline_min = MLX5_INLINE_HSIZE_L2; 2943 goto exit; 2944 case MLX5_CAP_INLINE_MODE_NOT_REQUIRED: 2945 /* No inline data are required by NIC. */ 2946 config->txq_inline_min = MLX5_INLINE_HSIZE_NONE; 2947 config->hw_vlan_insert = 2948 hca_attr->wqe_vlan_insert; 2949 DRV_LOG(DEBUG, "Tx VLAN insertion is supported"); 2950 goto exit; 2951 case MLX5_CAP_INLINE_MODE_VPORT_CONTEXT: 2952 /* inline mode is defined by NIC vport context. */ 2953 if (!hca_attr->eth_virt) 2954 break; 2955 switch (hca_attr->vport_inline_mode) { 2956 case MLX5_INLINE_MODE_NONE: 2957 config->txq_inline_min = 2958 MLX5_INLINE_HSIZE_NONE; 2959 goto exit; 2960 case MLX5_INLINE_MODE_L2: 2961 config->txq_inline_min = 2962 MLX5_INLINE_HSIZE_L2; 2963 goto exit; 2964 case MLX5_INLINE_MODE_IP: 2965 config->txq_inline_min = 2966 MLX5_INLINE_HSIZE_L3; 2967 goto exit; 2968 case MLX5_INLINE_MODE_TCP_UDP: 2969 config->txq_inline_min = 2970 MLX5_INLINE_HSIZE_L4; 2971 goto exit; 2972 case MLX5_INLINE_MODE_INNER_L2: 2973 config->txq_inline_min = 2974 MLX5_INLINE_HSIZE_INNER_L2; 2975 goto exit; 2976 case MLX5_INLINE_MODE_INNER_IP: 2977 config->txq_inline_min = 2978 MLX5_INLINE_HSIZE_INNER_L3; 2979 goto exit; 2980 case MLX5_INLINE_MODE_INNER_TCP_UDP: 2981 config->txq_inline_min = 2982 MLX5_INLINE_HSIZE_INNER_L4; 2983 goto exit; 2984 } 2985 } 2986 } 2987 if (priv->pci_dev == NULL) { 2988 config->txq_inline_min = MLX5_INLINE_HSIZE_NONE; 2989 goto exit; 2990 } 2991 /* 2992 * We get here if we are unable to deduce 2993 * inline data size with DevX. Try PCI ID 2994 * to determine old NICs. 2995 */ 2996 switch (priv->pci_dev->id.device_id) { 2997 case PCI_DEVICE_ID_MELLANOX_CONNECTX4: 2998 case PCI_DEVICE_ID_MELLANOX_CONNECTX4VF: 2999 case PCI_DEVICE_ID_MELLANOX_CONNECTX4LX: 3000 case PCI_DEVICE_ID_MELLANOX_CONNECTX4LXVF: 3001 config->txq_inline_min = MLX5_INLINE_HSIZE_L2; 3002 config->hw_vlan_insert = 0; 3003 break; 3004 case PCI_DEVICE_ID_MELLANOX_CONNECTX5: 3005 case PCI_DEVICE_ID_MELLANOX_CONNECTX5VF: 3006 case PCI_DEVICE_ID_MELLANOX_CONNECTX5EX: 3007 case PCI_DEVICE_ID_MELLANOX_CONNECTX5EXVF: 3008 /* 3009 * These NICs support VLAN insertion from WQE and 3010 * report the wqe_vlan_insert flag. But there is the bug 3011 * and PFC control may be broken, so disable feature. 3012 */ 3013 config->hw_vlan_insert = 0; 3014 config->txq_inline_min = MLX5_INLINE_HSIZE_NONE; 3015 break; 3016 default: 3017 config->txq_inline_min = MLX5_INLINE_HSIZE_NONE; 3018 break; 3019 } 3020 exit: 3021 DRV_LOG(DEBUG, "min tx inline configured: %d", config->txq_inline_min); 3022 } 3023 3024 /** 3025 * Configures the metadata mask fields in the shared context. 3026 * 3027 * @param [in] dev 3028 * Pointer to Ethernet device. 3029 */ 3030 void 3031 mlx5_set_metadata_mask(struct rte_eth_dev *dev) 3032 { 3033 struct mlx5_priv *priv = dev->data->dev_private; 3034 struct mlx5_dev_ctx_shared *sh = priv->sh; 3035 uint32_t meta, mark, reg_c0; 3036 3037 reg_c0 = ~priv->vport_meta_mask; 3038 switch (sh->config.dv_xmeta_en) { 3039 case MLX5_XMETA_MODE_LEGACY: 3040 meta = UINT32_MAX; 3041 mark = MLX5_FLOW_MARK_MASK; 3042 break; 3043 case MLX5_XMETA_MODE_META16: 3044 meta = reg_c0 >> rte_bsf32(reg_c0); 3045 mark = MLX5_FLOW_MARK_MASK; 3046 break; 3047 case MLX5_XMETA_MODE_META32: 3048 meta = UINT32_MAX; 3049 mark = (reg_c0 >> rte_bsf32(reg_c0)) & MLX5_FLOW_MARK_MASK; 3050 break; 3051 case MLX5_XMETA_MODE_META32_HWS: 3052 meta = UINT32_MAX; 3053 mark = MLX5_FLOW_MARK_MASK; 3054 break; 3055 default: 3056 meta = 0; 3057 mark = 0; 3058 MLX5_ASSERT(false); 3059 break; 3060 } 3061 if (sh->dv_mark_mask && sh->dv_mark_mask != mark) 3062 DRV_LOG(WARNING, "metadata MARK mask mismatch %08X:%08X", 3063 sh->dv_mark_mask, mark); 3064 else 3065 sh->dv_mark_mask = mark; 3066 if (sh->dv_meta_mask && sh->dv_meta_mask != meta) 3067 DRV_LOG(WARNING, "metadata META mask mismatch %08X:%08X", 3068 sh->dv_meta_mask, meta); 3069 else 3070 sh->dv_meta_mask = meta; 3071 if (sh->dv_regc0_mask && sh->dv_regc0_mask != reg_c0) 3072 DRV_LOG(WARNING, "metadata reg_c0 mask mismatch %08X:%08X", 3073 sh->dv_meta_mask, reg_c0); 3074 else 3075 sh->dv_regc0_mask = reg_c0; 3076 DRV_LOG(DEBUG, "metadata mode %u", sh->config.dv_xmeta_en); 3077 DRV_LOG(DEBUG, "metadata MARK mask %08X", sh->dv_mark_mask); 3078 DRV_LOG(DEBUG, "metadata META mask %08X", sh->dv_meta_mask); 3079 DRV_LOG(DEBUG, "metadata reg_c0 mask %08X", sh->dv_regc0_mask); 3080 } 3081 3082 int 3083 rte_pmd_mlx5_get_dyn_flag_names(char *names[], unsigned int n) 3084 { 3085 static const char *const dynf_names[] = { 3086 RTE_PMD_MLX5_FINE_GRANULARITY_INLINE, 3087 RTE_MBUF_DYNFLAG_METADATA_NAME, 3088 RTE_MBUF_DYNFLAG_TX_TIMESTAMP_NAME 3089 }; 3090 unsigned int i; 3091 3092 if (n < RTE_DIM(dynf_names)) 3093 return -ENOMEM; 3094 for (i = 0; i < RTE_DIM(dynf_names); i++) { 3095 if (names[i] == NULL) 3096 return -EINVAL; 3097 strcpy(names[i], dynf_names[i]); 3098 } 3099 return RTE_DIM(dynf_names); 3100 } 3101 3102 /** 3103 * Look for the ethernet device belonging to mlx5 driver. 3104 * 3105 * @param[in] port_id 3106 * port_id to start looking for device. 3107 * @param[in] odev 3108 * Pointer to the hint device. When device is being probed 3109 * the its siblings (master and preceding representors might 3110 * not have assigned driver yet (because the mlx5_os_pci_probe() 3111 * is not completed yet, for this case match on hint 3112 * device may be used to detect sibling device. 3113 * 3114 * @return 3115 * port_id of found device, RTE_MAX_ETHPORT if not found. 3116 */ 3117 uint16_t 3118 mlx5_eth_find_next(uint16_t port_id, struct rte_device *odev) 3119 { 3120 while (port_id < RTE_MAX_ETHPORTS) { 3121 struct rte_eth_dev *dev = &rte_eth_devices[port_id]; 3122 3123 if (dev->state != RTE_ETH_DEV_UNUSED && 3124 dev->device && 3125 (dev->device == odev || 3126 (dev->device->driver && 3127 dev->device->driver->name && 3128 ((strcmp(dev->device->driver->name, 3129 MLX5_PCI_DRIVER_NAME) == 0) || 3130 (strcmp(dev->device->driver->name, 3131 MLX5_AUXILIARY_DRIVER_NAME) == 0))))) 3132 break; 3133 port_id++; 3134 } 3135 if (port_id >= RTE_MAX_ETHPORTS) 3136 return RTE_MAX_ETHPORTS; 3137 return port_id; 3138 } 3139 3140 /** 3141 * Callback to remove a device. 3142 * 3143 * This function removes all Ethernet devices belong to a given device. 3144 * 3145 * @param[in] cdev 3146 * Pointer to the generic device. 3147 * 3148 * @return 3149 * 0 on success, the function cannot fail. 3150 */ 3151 int 3152 mlx5_net_remove(struct mlx5_common_device *cdev) 3153 { 3154 uint16_t port_id; 3155 int ret = 0; 3156 3157 RTE_ETH_FOREACH_DEV_OF(port_id, cdev->dev) { 3158 /* 3159 * mlx5_dev_close() is not registered to secondary process, 3160 * call the close function explicitly for secondary process. 3161 */ 3162 if (rte_eal_process_type() == RTE_PROC_SECONDARY) 3163 ret |= mlx5_dev_close(&rte_eth_devices[port_id]); 3164 else 3165 ret |= rte_eth_dev_close(port_id); 3166 } 3167 return ret == 0 ? 0 : -EIO; 3168 } 3169 3170 static const struct rte_pci_id mlx5_pci_id_map[] = { 3171 { 3172 RTE_PCI_DEVICE(PCI_VENDOR_ID_MELLANOX, 3173 PCI_DEVICE_ID_MELLANOX_CONNECTX4) 3174 }, 3175 { 3176 RTE_PCI_DEVICE(PCI_VENDOR_ID_MELLANOX, 3177 PCI_DEVICE_ID_MELLANOX_CONNECTX4VF) 3178 }, 3179 { 3180 RTE_PCI_DEVICE(PCI_VENDOR_ID_MELLANOX, 3181 PCI_DEVICE_ID_MELLANOX_CONNECTX4LX) 3182 }, 3183 { 3184 RTE_PCI_DEVICE(PCI_VENDOR_ID_MELLANOX, 3185 PCI_DEVICE_ID_MELLANOX_CONNECTX4LXVF) 3186 }, 3187 { 3188 RTE_PCI_DEVICE(PCI_VENDOR_ID_MELLANOX, 3189 PCI_DEVICE_ID_MELLANOX_CONNECTX5) 3190 }, 3191 { 3192 RTE_PCI_DEVICE(PCI_VENDOR_ID_MELLANOX, 3193 PCI_DEVICE_ID_MELLANOX_CONNECTX5VF) 3194 }, 3195 { 3196 RTE_PCI_DEVICE(PCI_VENDOR_ID_MELLANOX, 3197 PCI_DEVICE_ID_MELLANOX_CONNECTX5EX) 3198 }, 3199 { 3200 RTE_PCI_DEVICE(PCI_VENDOR_ID_MELLANOX, 3201 PCI_DEVICE_ID_MELLANOX_CONNECTX5EXVF) 3202 }, 3203 { 3204 RTE_PCI_DEVICE(PCI_VENDOR_ID_MELLANOX, 3205 PCI_DEVICE_ID_MELLANOX_BLUEFIELD) 3206 }, 3207 { 3208 RTE_PCI_DEVICE(PCI_VENDOR_ID_MELLANOX, 3209 PCI_DEVICE_ID_MELLANOX_BLUEFIELDVF) 3210 }, 3211 { 3212 RTE_PCI_DEVICE(PCI_VENDOR_ID_MELLANOX, 3213 PCI_DEVICE_ID_MELLANOX_CONNECTX6) 3214 }, 3215 { 3216 RTE_PCI_DEVICE(PCI_VENDOR_ID_MELLANOX, 3217 PCI_DEVICE_ID_MELLANOX_CONNECTX6VF) 3218 }, 3219 { 3220 RTE_PCI_DEVICE(PCI_VENDOR_ID_MELLANOX, 3221 PCI_DEVICE_ID_MELLANOX_CONNECTX6DX) 3222 }, 3223 { 3224 RTE_PCI_DEVICE(PCI_VENDOR_ID_MELLANOX, 3225 PCI_DEVICE_ID_MELLANOX_CONNECTXVF) 3226 }, 3227 { 3228 RTE_PCI_DEVICE(PCI_VENDOR_ID_MELLANOX, 3229 PCI_DEVICE_ID_MELLANOX_BLUEFIELD2) 3230 }, 3231 { 3232 RTE_PCI_DEVICE(PCI_VENDOR_ID_MELLANOX, 3233 PCI_DEVICE_ID_MELLANOX_CONNECTX6LX) 3234 }, 3235 { 3236 RTE_PCI_DEVICE(PCI_VENDOR_ID_MELLANOX, 3237 PCI_DEVICE_ID_MELLANOX_CONNECTX7) 3238 }, 3239 { 3240 RTE_PCI_DEVICE(PCI_VENDOR_ID_MELLANOX, 3241 PCI_DEVICE_ID_MELLANOX_BLUEFIELD3) 3242 }, 3243 { 3244 .vendor_id = 0 3245 } 3246 }; 3247 3248 static struct mlx5_class_driver mlx5_net_driver = { 3249 .drv_class = MLX5_CLASS_ETH, 3250 .name = RTE_STR(MLX5_ETH_DRIVER_NAME), 3251 .id_table = mlx5_pci_id_map, 3252 .probe = mlx5_os_net_probe, 3253 .remove = mlx5_net_remove, 3254 .probe_again = 1, 3255 .intr_lsc = 1, 3256 .intr_rmv = 1, 3257 }; 3258 3259 /* Initialize driver log type. */ 3260 RTE_LOG_REGISTER_DEFAULT(mlx5_logtype, NOTICE) 3261 3262 /** 3263 * Driver initialization routine. 3264 */ 3265 RTE_INIT(rte_mlx5_pmd_init) 3266 { 3267 pthread_mutex_init(&mlx5_dev_ctx_list_mutex, NULL); 3268 mlx5_common_init(); 3269 /* Build the static tables for Verbs conversion. */ 3270 mlx5_set_ptype_table(); 3271 mlx5_set_cksum_table(); 3272 mlx5_set_swp_types_table(); 3273 if (mlx5_glue) 3274 mlx5_class_driver_register(&mlx5_net_driver); 3275 } 3276 3277 RTE_PMD_EXPORT_NAME(MLX5_ETH_DRIVER_NAME, __COUNTER__); 3278 RTE_PMD_REGISTER_PCI_TABLE(MLX5_ETH_DRIVER_NAME, mlx5_pci_id_map); 3279 RTE_PMD_REGISTER_KMOD_DEP(MLX5_ETH_DRIVER_NAME, "* ib_uverbs & mlx5_core & mlx5_ib"); 3280