1 /*- 2 * BSD LICENSE 3 * 4 * Copyright 2015 6WIND S.A. 5 * Copyright 2015 Mellanox. 6 * 7 * Redistribution and use in source and binary forms, with or without 8 * modification, are permitted provided that the following conditions 9 * are met: 10 * 11 * * Redistributions of source code must retain the above copyright 12 * notice, this list of conditions and the following disclaimer. 13 * * Redistributions in binary form must reproduce the above copyright 14 * notice, this list of conditions and the following disclaimer in 15 * the documentation and/or other materials provided with the 16 * distribution. 17 * * Neither the name of 6WIND S.A. nor the names of its 18 * contributors may be used to endorse or promote products derived 19 * from this software without specific prior written permission. 20 * 21 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 22 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 23 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 24 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 25 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 26 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 27 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 28 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 29 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 30 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 31 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 32 */ 33 34 #include <stddef.h> 35 #include <unistd.h> 36 #include <string.h> 37 #include <assert.h> 38 #include <stdint.h> 39 #include <stdlib.h> 40 #include <errno.h> 41 #include <net/if.h> 42 43 /* Verbs header. */ 44 /* ISO C doesn't support unnamed structs/unions, disabling -pedantic. */ 45 #ifdef PEDANTIC 46 #pragma GCC diagnostic ignored "-Wpedantic" 47 #endif 48 #include <infiniband/verbs.h> 49 #ifdef PEDANTIC 50 #pragma GCC diagnostic error "-Wpedantic" 51 #endif 52 53 /* DPDK headers don't like -pedantic. */ 54 #ifdef PEDANTIC 55 #pragma GCC diagnostic ignored "-Wpedantic" 56 #endif 57 #include <rte_malloc.h> 58 #include <rte_ethdev.h> 59 #include <rte_ethdev_pci.h> 60 #include <rte_pci.h> 61 #include <rte_common.h> 62 #include <rte_kvargs.h> 63 #ifdef PEDANTIC 64 #pragma GCC diagnostic error "-Wpedantic" 65 #endif 66 67 #include "mlx5.h" 68 #include "mlx5_utils.h" 69 #include "mlx5_rxtx.h" 70 #include "mlx5_autoconf.h" 71 #include "mlx5_defs.h" 72 73 /* Device parameter to enable RX completion queue compression. */ 74 #define MLX5_RXQ_CQE_COMP_EN "rxq_cqe_comp_en" 75 76 /* Device parameter to configure inline send. */ 77 #define MLX5_TXQ_INLINE "txq_inline" 78 79 /* 80 * Device parameter to configure the number of TX queues threshold for 81 * enabling inline send. 82 */ 83 #define MLX5_TXQS_MIN_INLINE "txqs_min_inline" 84 85 /* Device parameter to enable multi-packet send WQEs. */ 86 #define MLX5_TXQ_MPW_EN "txq_mpw_en" 87 88 /* Device parameter to include 2 dsegs in the title WQEBB. */ 89 #define MLX5_TXQ_MPW_HDR_DSEG_EN "txq_mpw_hdr_dseg_en" 90 91 /* Device parameter to limit the size of inlining packet. */ 92 #define MLX5_TXQ_MAX_INLINE_LEN "txq_max_inline_len" 93 94 /* Device parameter to enable hardware TSO offload. */ 95 #define MLX5_TSO "tso" 96 97 /* Device parameter to enable hardware Tx vector. */ 98 #define MLX5_TX_VEC_EN "tx_vec_en" 99 100 /* Device parameter to enable hardware Rx vector. */ 101 #define MLX5_RX_VEC_EN "rx_vec_en" 102 103 /* Default PMD specific parameter value. */ 104 #define MLX5_ARG_UNSET (-1) 105 106 struct mlx5_args { 107 int cqe_comp; 108 int txq_inline; 109 int txqs_inline; 110 int mps; 111 int mpw_hdr_dseg; 112 int inline_max_packet_sz; 113 int tso; 114 int tx_vec_en; 115 int rx_vec_en; 116 }; 117 /** 118 * Retrieve integer value from environment variable. 119 * 120 * @param[in] name 121 * Environment variable name. 122 * 123 * @return 124 * Integer value, 0 if the variable is not set. 125 */ 126 int 127 mlx5_getenv_int(const char *name) 128 { 129 const char *val = getenv(name); 130 131 if (val == NULL) 132 return 0; 133 return atoi(val); 134 } 135 136 /** 137 * DPDK callback to close the device. 138 * 139 * Destroy all queues and objects, free memory. 140 * 141 * @param dev 142 * Pointer to Ethernet device structure. 143 */ 144 static void 145 mlx5_dev_close(struct rte_eth_dev *dev) 146 { 147 struct priv *priv = mlx5_get_priv(dev); 148 unsigned int i; 149 150 priv_lock(priv); 151 DEBUG("%p: closing device \"%s\"", 152 (void *)dev, 153 ((priv->ctx != NULL) ? priv->ctx->device->name : "")); 154 /* In case mlx5_dev_stop() has not been called. */ 155 priv_dev_interrupt_handler_uninstall(priv, dev); 156 priv_special_flow_disable_all(priv); 157 priv_mac_addrs_disable(priv); 158 priv_destroy_hash_rxqs(priv); 159 160 /* Remove flow director elements. */ 161 priv_fdir_disable(priv); 162 priv_fdir_delete_filters_list(priv); 163 164 /* Prevent crashes when queues are still in use. */ 165 dev->rx_pkt_burst = removed_rx_burst; 166 dev->tx_pkt_burst = removed_tx_burst; 167 if (priv->rxqs != NULL) { 168 /* XXX race condition if mlx5_rx_burst() is still running. */ 169 usleep(1000); 170 for (i = 0; (i != priv->rxqs_n); ++i) { 171 struct rxq *rxq = (*priv->rxqs)[i]; 172 struct rxq_ctrl *rxq_ctrl; 173 174 if (rxq == NULL) 175 continue; 176 rxq_ctrl = container_of(rxq, struct rxq_ctrl, rxq); 177 (*priv->rxqs)[i] = NULL; 178 rxq_cleanup(rxq_ctrl); 179 rte_free(rxq_ctrl); 180 } 181 priv->rxqs_n = 0; 182 priv->rxqs = NULL; 183 } 184 if (priv->txqs != NULL) { 185 /* XXX race condition if mlx5_tx_burst() is still running. */ 186 usleep(1000); 187 for (i = 0; (i != priv->txqs_n); ++i) { 188 struct txq *txq = (*priv->txqs)[i]; 189 struct txq_ctrl *txq_ctrl; 190 191 if (txq == NULL) 192 continue; 193 txq_ctrl = container_of(txq, struct txq_ctrl, txq); 194 (*priv->txqs)[i] = NULL; 195 txq_cleanup(txq_ctrl); 196 rte_free(txq_ctrl); 197 } 198 priv->txqs_n = 0; 199 priv->txqs = NULL; 200 } 201 if (priv->pd != NULL) { 202 assert(priv->ctx != NULL); 203 claim_zero(ibv_dealloc_pd(priv->pd)); 204 claim_zero(ibv_close_device(priv->ctx)); 205 } else 206 assert(priv->ctx == NULL); 207 if (priv->rss_conf != NULL) { 208 for (i = 0; (i != hash_rxq_init_n); ++i) 209 rte_free((*priv->rss_conf)[i]); 210 rte_free(priv->rss_conf); 211 } 212 if (priv->reta_idx != NULL) 213 rte_free(priv->reta_idx); 214 priv_unlock(priv); 215 memset(priv, 0, sizeof(*priv)); 216 } 217 218 static const struct eth_dev_ops mlx5_dev_ops = { 219 .dev_configure = mlx5_dev_configure, 220 .dev_start = mlx5_dev_start, 221 .dev_stop = mlx5_dev_stop, 222 .dev_set_link_down = mlx5_set_link_down, 223 .dev_set_link_up = mlx5_set_link_up, 224 .dev_close = mlx5_dev_close, 225 .promiscuous_enable = mlx5_promiscuous_enable, 226 .promiscuous_disable = mlx5_promiscuous_disable, 227 .allmulticast_enable = mlx5_allmulticast_enable, 228 .allmulticast_disable = mlx5_allmulticast_disable, 229 .link_update = mlx5_link_update, 230 .stats_get = mlx5_stats_get, 231 .stats_reset = mlx5_stats_reset, 232 .xstats_get = mlx5_xstats_get, 233 .xstats_reset = mlx5_xstats_reset, 234 .xstats_get_names = mlx5_xstats_get_names, 235 .dev_infos_get = mlx5_dev_infos_get, 236 .dev_supported_ptypes_get = mlx5_dev_supported_ptypes_get, 237 .vlan_filter_set = mlx5_vlan_filter_set, 238 .rx_queue_setup = mlx5_rx_queue_setup, 239 .tx_queue_setup = mlx5_tx_queue_setup, 240 .rx_queue_release = mlx5_rx_queue_release, 241 .tx_queue_release = mlx5_tx_queue_release, 242 .flow_ctrl_get = mlx5_dev_get_flow_ctrl, 243 .flow_ctrl_set = mlx5_dev_set_flow_ctrl, 244 .mac_addr_remove = mlx5_mac_addr_remove, 245 .mac_addr_add = mlx5_mac_addr_add, 246 .mac_addr_set = mlx5_mac_addr_set, 247 .mtu_set = mlx5_dev_set_mtu, 248 .vlan_strip_queue_set = mlx5_vlan_strip_queue_set, 249 .vlan_offload_set = mlx5_vlan_offload_set, 250 .reta_update = mlx5_dev_rss_reta_update, 251 .reta_query = mlx5_dev_rss_reta_query, 252 .rss_hash_update = mlx5_rss_hash_update, 253 .rss_hash_conf_get = mlx5_rss_hash_conf_get, 254 .filter_ctrl = mlx5_dev_filter_ctrl, 255 .rx_descriptor_status = mlx5_rx_descriptor_status, 256 .tx_descriptor_status = mlx5_tx_descriptor_status, 257 #ifdef HAVE_UPDATE_CQ_CI 258 .rx_queue_intr_enable = mlx5_rx_intr_enable, 259 .rx_queue_intr_disable = mlx5_rx_intr_disable, 260 #endif 261 }; 262 263 static struct { 264 struct rte_pci_addr pci_addr; /* associated PCI address */ 265 uint32_t ports; /* physical ports bitfield. */ 266 } mlx5_dev[32]; 267 268 /** 269 * Get device index in mlx5_dev[] from PCI bus address. 270 * 271 * @param[in] pci_addr 272 * PCI bus address to look for. 273 * 274 * @return 275 * mlx5_dev[] index on success, -1 on failure. 276 */ 277 static int 278 mlx5_dev_idx(struct rte_pci_addr *pci_addr) 279 { 280 unsigned int i; 281 int ret = -1; 282 283 assert(pci_addr != NULL); 284 for (i = 0; (i != RTE_DIM(mlx5_dev)); ++i) { 285 if ((mlx5_dev[i].pci_addr.domain == pci_addr->domain) && 286 (mlx5_dev[i].pci_addr.bus == pci_addr->bus) && 287 (mlx5_dev[i].pci_addr.devid == pci_addr->devid) && 288 (mlx5_dev[i].pci_addr.function == pci_addr->function)) 289 return i; 290 if ((mlx5_dev[i].ports == 0) && (ret == -1)) 291 ret = i; 292 } 293 return ret; 294 } 295 296 /** 297 * Verify and store value for device argument. 298 * 299 * @param[in] key 300 * Key argument to verify. 301 * @param[in] val 302 * Value associated with key. 303 * @param opaque 304 * User data. 305 * 306 * @return 307 * 0 on success, negative errno value on failure. 308 */ 309 static int 310 mlx5_args_check(const char *key, const char *val, void *opaque) 311 { 312 struct mlx5_args *args = opaque; 313 unsigned long tmp; 314 315 errno = 0; 316 tmp = strtoul(val, NULL, 0); 317 if (errno) { 318 WARN("%s: \"%s\" is not a valid integer", key, val); 319 return errno; 320 } 321 if (strcmp(MLX5_RXQ_CQE_COMP_EN, key) == 0) { 322 args->cqe_comp = !!tmp; 323 } else if (strcmp(MLX5_TXQ_INLINE, key) == 0) { 324 args->txq_inline = tmp; 325 } else if (strcmp(MLX5_TXQS_MIN_INLINE, key) == 0) { 326 args->txqs_inline = tmp; 327 } else if (strcmp(MLX5_TXQ_MPW_EN, key) == 0) { 328 args->mps = !!tmp; 329 } else if (strcmp(MLX5_TXQ_MPW_HDR_DSEG_EN, key) == 0) { 330 args->mpw_hdr_dseg = !!tmp; 331 } else if (strcmp(MLX5_TXQ_MAX_INLINE_LEN, key) == 0) { 332 args->inline_max_packet_sz = tmp; 333 } else if (strcmp(MLX5_TSO, key) == 0) { 334 args->tso = !!tmp; 335 } else if (strcmp(MLX5_TX_VEC_EN, key) == 0) { 336 args->tx_vec_en = !!tmp; 337 } else if (strcmp(MLX5_RX_VEC_EN, key) == 0) { 338 args->rx_vec_en = !!tmp; 339 } else { 340 WARN("%s: unknown parameter", key); 341 return -EINVAL; 342 } 343 return 0; 344 } 345 346 /** 347 * Parse device parameters. 348 * 349 * @param priv 350 * Pointer to private structure. 351 * @param devargs 352 * Device arguments structure. 353 * 354 * @return 355 * 0 on success, errno value on failure. 356 */ 357 static int 358 mlx5_args(struct mlx5_args *args, struct rte_devargs *devargs) 359 { 360 const char **params = (const char *[]){ 361 MLX5_RXQ_CQE_COMP_EN, 362 MLX5_TXQ_INLINE, 363 MLX5_TXQS_MIN_INLINE, 364 MLX5_TXQ_MPW_EN, 365 MLX5_TXQ_MPW_HDR_DSEG_EN, 366 MLX5_TXQ_MAX_INLINE_LEN, 367 MLX5_TSO, 368 MLX5_TX_VEC_EN, 369 MLX5_RX_VEC_EN, 370 NULL, 371 }; 372 struct rte_kvargs *kvlist; 373 int ret = 0; 374 int i; 375 376 if (devargs == NULL) 377 return 0; 378 /* Following UGLY cast is done to pass checkpatch. */ 379 kvlist = rte_kvargs_parse(devargs->args, params); 380 if (kvlist == NULL) 381 return 0; 382 /* Process parameters. */ 383 for (i = 0; (params[i] != NULL); ++i) { 384 if (rte_kvargs_count(kvlist, params[i])) { 385 ret = rte_kvargs_process(kvlist, params[i], 386 mlx5_args_check, args); 387 if (ret != 0) { 388 rte_kvargs_free(kvlist); 389 return ret; 390 } 391 } 392 } 393 rte_kvargs_free(kvlist); 394 return 0; 395 } 396 397 static struct rte_pci_driver mlx5_driver; 398 399 /** 400 * Assign parameters from args into priv, only non default 401 * values are considered. 402 * 403 * @param[out] priv 404 * Pointer to private structure. 405 * @param[in] args 406 * Pointer to args values. 407 */ 408 static void 409 mlx5_args_assign(struct priv *priv, struct mlx5_args *args) 410 { 411 if (args->cqe_comp != MLX5_ARG_UNSET) 412 priv->cqe_comp = args->cqe_comp; 413 if (args->txq_inline != MLX5_ARG_UNSET) 414 priv->txq_inline = args->txq_inline; 415 if (args->txqs_inline != MLX5_ARG_UNSET) 416 priv->txqs_inline = args->txqs_inline; 417 if (args->mps != MLX5_ARG_UNSET) 418 priv->mps = args->mps ? priv->mps : 0; 419 if (args->mpw_hdr_dseg != MLX5_ARG_UNSET) 420 priv->mpw_hdr_dseg = args->mpw_hdr_dseg; 421 if (args->inline_max_packet_sz != MLX5_ARG_UNSET) 422 priv->inline_max_packet_sz = args->inline_max_packet_sz; 423 if (args->tso != MLX5_ARG_UNSET) 424 priv->tso = args->tso; 425 if (args->tx_vec_en != MLX5_ARG_UNSET) 426 priv->tx_vec_en = args->tx_vec_en; 427 if (args->rx_vec_en != MLX5_ARG_UNSET) 428 priv->rx_vec_en = args->rx_vec_en; 429 } 430 431 /** 432 * DPDK callback to register a PCI device. 433 * 434 * This function creates an Ethernet device for each port of a given 435 * PCI device. 436 * 437 * @param[in] pci_drv 438 * PCI driver structure (mlx5_driver). 439 * @param[in] pci_dev 440 * PCI device information. 441 * 442 * @return 443 * 0 on success, negative errno value on failure. 444 */ 445 static int 446 mlx5_pci_probe(struct rte_pci_driver *pci_drv, struct rte_pci_device *pci_dev) 447 { 448 struct ibv_device **list; 449 struct ibv_device *ibv_dev; 450 int err = 0; 451 struct ibv_context *attr_ctx = NULL; 452 struct ibv_device_attr device_attr; 453 unsigned int sriov; 454 unsigned int mps; 455 unsigned int tunnel_en; 456 int idx; 457 int i; 458 459 (void)pci_drv; 460 assert(pci_drv == &mlx5_driver); 461 /* Get mlx5_dev[] index. */ 462 idx = mlx5_dev_idx(&pci_dev->addr); 463 if (idx == -1) { 464 ERROR("this driver cannot support any more adapters"); 465 return -ENOMEM; 466 } 467 DEBUG("using driver device index %d", idx); 468 469 /* Save PCI address. */ 470 mlx5_dev[idx].pci_addr = pci_dev->addr; 471 list = ibv_get_device_list(&i); 472 if (list == NULL) { 473 assert(errno); 474 if (errno == ENOSYS) 475 ERROR("cannot list devices, is ib_uverbs loaded?"); 476 return -errno; 477 } 478 assert(i >= 0); 479 /* 480 * For each listed device, check related sysfs entry against 481 * the provided PCI ID. 482 */ 483 while (i != 0) { 484 struct rte_pci_addr pci_addr; 485 486 --i; 487 DEBUG("checking device \"%s\"", list[i]->name); 488 if (mlx5_ibv_device_to_pci_addr(list[i], &pci_addr)) 489 continue; 490 if ((pci_dev->addr.domain != pci_addr.domain) || 491 (pci_dev->addr.bus != pci_addr.bus) || 492 (pci_dev->addr.devid != pci_addr.devid) || 493 (pci_dev->addr.function != pci_addr.function)) 494 continue; 495 sriov = ((pci_dev->id.device_id == 496 PCI_DEVICE_ID_MELLANOX_CONNECTX4VF) || 497 (pci_dev->id.device_id == 498 PCI_DEVICE_ID_MELLANOX_CONNECTX4LXVF) || 499 (pci_dev->id.device_id == 500 PCI_DEVICE_ID_MELLANOX_CONNECTX5VF) || 501 (pci_dev->id.device_id == 502 PCI_DEVICE_ID_MELLANOX_CONNECTX5EXVF)); 503 /* 504 * Multi-packet send is supported by ConnectX-4 Lx PF as well 505 * as all ConnectX-5 devices. 506 */ 507 switch (pci_dev->id.device_id) { 508 case PCI_DEVICE_ID_MELLANOX_CONNECTX4: 509 tunnel_en = 1; 510 mps = MLX5_MPW_DISABLED; 511 break; 512 case PCI_DEVICE_ID_MELLANOX_CONNECTX4LX: 513 mps = MLX5_MPW; 514 break; 515 case PCI_DEVICE_ID_MELLANOX_CONNECTX5: 516 case PCI_DEVICE_ID_MELLANOX_CONNECTX5VF: 517 case PCI_DEVICE_ID_MELLANOX_CONNECTX5EX: 518 case PCI_DEVICE_ID_MELLANOX_CONNECTX5EXVF: 519 tunnel_en = 1; 520 mps = MLX5_MPW_ENHANCED; 521 break; 522 default: 523 mps = MLX5_MPW_DISABLED; 524 } 525 INFO("PCI information matches, using device \"%s\"" 526 " (SR-IOV: %s, %sMPS: %s)", 527 list[i]->name, 528 sriov ? "true" : "false", 529 mps == MLX5_MPW_ENHANCED ? "Enhanced " : "", 530 mps != MLX5_MPW_DISABLED ? "true" : "false"); 531 attr_ctx = ibv_open_device(list[i]); 532 err = errno; 533 break; 534 } 535 if (attr_ctx == NULL) { 536 ibv_free_device_list(list); 537 switch (err) { 538 case 0: 539 ERROR("cannot access device, is mlx5_ib loaded?"); 540 return -ENODEV; 541 case EINVAL: 542 ERROR("cannot use device, are drivers up to date?"); 543 return -EINVAL; 544 } 545 assert(err > 0); 546 return -err; 547 } 548 ibv_dev = list[i]; 549 550 DEBUG("device opened"); 551 if (ibv_query_device(attr_ctx, &device_attr)) 552 goto error; 553 INFO("%u port(s) detected", device_attr.phys_port_cnt); 554 555 for (i = 0; i < device_attr.phys_port_cnt; i++) { 556 uint32_t port = i + 1; /* ports are indexed from one */ 557 uint32_t test = (1 << i); 558 struct ibv_context *ctx = NULL; 559 struct ibv_port_attr port_attr; 560 struct ibv_pd *pd = NULL; 561 struct priv *priv = NULL; 562 struct rte_eth_dev *eth_dev; 563 struct ibv_exp_device_attr exp_device_attr; 564 struct ether_addr mac; 565 uint16_t num_vfs = 0; 566 struct mlx5_args args = { 567 .cqe_comp = MLX5_ARG_UNSET, 568 .txq_inline = MLX5_ARG_UNSET, 569 .txqs_inline = MLX5_ARG_UNSET, 570 .mps = MLX5_ARG_UNSET, 571 .mpw_hdr_dseg = MLX5_ARG_UNSET, 572 .inline_max_packet_sz = MLX5_ARG_UNSET, 573 .tso = MLX5_ARG_UNSET, 574 .tx_vec_en = MLX5_ARG_UNSET, 575 .rx_vec_en = MLX5_ARG_UNSET, 576 }; 577 578 exp_device_attr.comp_mask = 579 IBV_EXP_DEVICE_ATTR_EXP_CAP_FLAGS | 580 IBV_EXP_DEVICE_ATTR_RX_HASH | 581 IBV_EXP_DEVICE_ATTR_VLAN_OFFLOADS | 582 IBV_EXP_DEVICE_ATTR_RX_PAD_END_ALIGN | 583 IBV_EXP_DEVICE_ATTR_TSO_CAPS | 584 0; 585 586 DEBUG("using port %u (%08" PRIx32 ")", port, test); 587 588 ctx = ibv_open_device(ibv_dev); 589 if (ctx == NULL) 590 goto port_error; 591 592 /* Check port status. */ 593 err = ibv_query_port(ctx, port, &port_attr); 594 if (err) { 595 ERROR("port query failed: %s", strerror(err)); 596 goto port_error; 597 } 598 599 if (port_attr.link_layer != IBV_LINK_LAYER_ETHERNET) { 600 ERROR("port %d is not configured in Ethernet mode", 601 port); 602 goto port_error; 603 } 604 605 if (port_attr.state != IBV_PORT_ACTIVE) 606 DEBUG("port %d is not active: \"%s\" (%d)", 607 port, ibv_port_state_str(port_attr.state), 608 port_attr.state); 609 610 /* Allocate protection domain. */ 611 pd = ibv_alloc_pd(ctx); 612 if (pd == NULL) { 613 ERROR("PD allocation failure"); 614 err = ENOMEM; 615 goto port_error; 616 } 617 618 mlx5_dev[idx].ports |= test; 619 620 /* from rte_ethdev.c */ 621 priv = rte_zmalloc("ethdev private structure", 622 sizeof(*priv), 623 RTE_CACHE_LINE_SIZE); 624 if (priv == NULL) { 625 ERROR("priv allocation failure"); 626 err = ENOMEM; 627 goto port_error; 628 } 629 630 priv->ctx = ctx; 631 priv->device_attr = device_attr; 632 priv->port = port; 633 priv->pd = pd; 634 priv->mtu = ETHER_MTU; 635 priv->mps = mps; /* Enable MPW by default if supported. */ 636 priv->cqe_comp = 1; /* Enable compression by default. */ 637 priv->tunnel_en = tunnel_en; 638 /* Enable vector by default if supported. */ 639 priv->tx_vec_en = 1; 640 priv->rx_vec_en = 1; 641 err = mlx5_args(&args, pci_dev->device.devargs); 642 if (err) { 643 ERROR("failed to process device arguments: %s", 644 strerror(err)); 645 goto port_error; 646 } 647 mlx5_args_assign(priv, &args); 648 if (ibv_exp_query_device(ctx, &exp_device_attr)) { 649 ERROR("ibv_exp_query_device() failed"); 650 goto port_error; 651 } 652 653 priv->hw_csum = 654 ((exp_device_attr.exp_device_cap_flags & 655 IBV_EXP_DEVICE_RX_CSUM_TCP_UDP_PKT) && 656 (exp_device_attr.exp_device_cap_flags & 657 IBV_EXP_DEVICE_RX_CSUM_IP_PKT)); 658 DEBUG("checksum offloading is %ssupported", 659 (priv->hw_csum ? "" : "not ")); 660 661 priv->hw_csum_l2tun = !!(exp_device_attr.exp_device_cap_flags & 662 IBV_EXP_DEVICE_VXLAN_SUPPORT); 663 DEBUG("L2 tunnel checksum offloads are %ssupported", 664 (priv->hw_csum_l2tun ? "" : "not ")); 665 666 priv->ind_table_max_size = exp_device_attr.rx_hash_caps.max_rwq_indirection_table_size; 667 /* Remove this check once DPDK supports larger/variable 668 * indirection tables. */ 669 if (priv->ind_table_max_size > 670 (unsigned int)ETH_RSS_RETA_SIZE_512) 671 priv->ind_table_max_size = ETH_RSS_RETA_SIZE_512; 672 DEBUG("maximum RX indirection table size is %u", 673 priv->ind_table_max_size); 674 priv->hw_vlan_strip = !!(exp_device_attr.wq_vlan_offloads_cap & 675 IBV_EXP_RECEIVE_WQ_CVLAN_STRIP); 676 DEBUG("VLAN stripping is %ssupported", 677 (priv->hw_vlan_strip ? "" : "not ")); 678 679 priv->hw_fcs_strip = !!(exp_device_attr.exp_device_cap_flags & 680 IBV_EXP_DEVICE_SCATTER_FCS); 681 DEBUG("FCS stripping configuration is %ssupported", 682 (priv->hw_fcs_strip ? "" : "not ")); 683 684 priv->hw_padding = !!exp_device_attr.rx_pad_end_addr_align; 685 DEBUG("hardware RX end alignment padding is %ssupported", 686 (priv->hw_padding ? "" : "not ")); 687 688 priv_get_num_vfs(priv, &num_vfs); 689 priv->sriov = (num_vfs || sriov); 690 priv->tso = ((priv->tso) && 691 (exp_device_attr.tso_caps.max_tso > 0) && 692 (exp_device_attr.tso_caps.supported_qpts & 693 (1 << IBV_QPT_RAW_ETH))); 694 if (priv->tso) 695 priv->max_tso_payload_sz = 696 exp_device_attr.tso_caps.max_tso; 697 if (priv->mps && !mps) { 698 ERROR("multi-packet send not supported on this device" 699 " (" MLX5_TXQ_MPW_EN ")"); 700 err = ENOTSUP; 701 goto port_error; 702 } else if (priv->mps && priv->tso) { 703 WARN("multi-packet send not supported in conjunction " 704 "with TSO. MPS disabled"); 705 priv->mps = 0; 706 } 707 INFO("%sMPS is %s", 708 priv->mps == MLX5_MPW_ENHANCED ? "Enhanced " : "", 709 priv->mps != MLX5_MPW_DISABLED ? "enabled" : "disabled"); 710 /* Set default values for Enhanced MPW, a.k.a MPWv2. */ 711 if (priv->mps == MLX5_MPW_ENHANCED) { 712 if (args.txqs_inline == MLX5_ARG_UNSET) 713 priv->txqs_inline = MLX5_EMPW_MIN_TXQS; 714 if (args.inline_max_packet_sz == MLX5_ARG_UNSET) 715 priv->inline_max_packet_sz = 716 MLX5_EMPW_MAX_INLINE_LEN; 717 if (args.txq_inline == MLX5_ARG_UNSET) 718 priv->txq_inline = MLX5_WQE_SIZE_MAX - 719 MLX5_WQE_SIZE; 720 } 721 /* Allocate and register default RSS hash keys. */ 722 priv->rss_conf = rte_calloc(__func__, hash_rxq_init_n, 723 sizeof((*priv->rss_conf)[0]), 0); 724 if (priv->rss_conf == NULL) { 725 err = ENOMEM; 726 goto port_error; 727 } 728 err = rss_hash_rss_conf_new_key(priv, 729 rss_hash_default_key, 730 rss_hash_default_key_len, 731 ETH_RSS_PROTO_MASK); 732 if (err) 733 goto port_error; 734 /* Configure the first MAC address by default. */ 735 if (priv_get_mac(priv, &mac.addr_bytes)) { 736 ERROR("cannot get MAC address, is mlx5_en loaded?" 737 " (errno: %s)", strerror(errno)); 738 goto port_error; 739 } 740 INFO("port %u MAC address is %02x:%02x:%02x:%02x:%02x:%02x", 741 priv->port, 742 mac.addr_bytes[0], mac.addr_bytes[1], 743 mac.addr_bytes[2], mac.addr_bytes[3], 744 mac.addr_bytes[4], mac.addr_bytes[5]); 745 /* Register MAC address. */ 746 claim_zero(priv_mac_addr_add(priv, 0, 747 (const uint8_t (*)[ETHER_ADDR_LEN]) 748 mac.addr_bytes)); 749 /* Initialize FD filters list. */ 750 err = fdir_init_filters_list(priv); 751 if (err) 752 goto port_error; 753 #ifndef NDEBUG 754 { 755 char ifname[IF_NAMESIZE]; 756 757 if (priv_get_ifname(priv, &ifname) == 0) 758 DEBUG("port %u ifname is \"%s\"", 759 priv->port, ifname); 760 else 761 DEBUG("port %u ifname is unknown", priv->port); 762 } 763 #endif 764 /* Get actual MTU if possible. */ 765 priv_get_mtu(priv, &priv->mtu); 766 DEBUG("port %u MTU is %u", priv->port, priv->mtu); 767 768 /* from rte_ethdev.c */ 769 { 770 char name[RTE_ETH_NAME_MAX_LEN]; 771 772 snprintf(name, sizeof(name), "%s port %u", 773 ibv_get_device_name(ibv_dev), port); 774 eth_dev = rte_eth_dev_allocate(name); 775 } 776 if (eth_dev == NULL) { 777 ERROR("can not allocate rte ethdev"); 778 err = ENOMEM; 779 goto port_error; 780 } 781 782 /* Secondary processes have to use local storage for their 783 * private data as well as a copy of eth_dev->data, but this 784 * pointer must not be modified before burst functions are 785 * actually called. */ 786 if (mlx5_is_secondary()) { 787 struct mlx5_secondary_data *sd = 788 &mlx5_secondary_data[eth_dev->data->port_id]; 789 sd->primary_priv = eth_dev->data->dev_private; 790 if (sd->primary_priv == NULL) { 791 ERROR("no private data for port %u", 792 eth_dev->data->port_id); 793 err = EINVAL; 794 goto port_error; 795 } 796 sd->shared_dev_data = eth_dev->data; 797 rte_spinlock_init(&sd->lock); 798 memcpy(sd->data.name, sd->shared_dev_data->name, 799 sizeof(sd->data.name)); 800 sd->data.dev_private = priv; 801 sd->data.rx_mbuf_alloc_failed = 0; 802 sd->data.mtu = ETHER_MTU; 803 sd->data.port_id = sd->shared_dev_data->port_id; 804 sd->data.mac_addrs = priv->mac; 805 eth_dev->tx_pkt_burst = mlx5_tx_burst_secondary_setup; 806 eth_dev->rx_pkt_burst = mlx5_rx_burst_secondary_setup; 807 } else { 808 eth_dev->data->dev_private = priv; 809 eth_dev->data->mac_addrs = priv->mac; 810 } 811 812 eth_dev->device = &pci_dev->device; 813 rte_eth_copy_pci_info(eth_dev, pci_dev); 814 eth_dev->data->dev_flags |= RTE_ETH_DEV_DETACHABLE; 815 eth_dev->device->driver = &mlx5_driver.driver; 816 priv->dev = eth_dev; 817 eth_dev->dev_ops = &mlx5_dev_ops; 818 TAILQ_INIT(&priv->flows); 819 820 /* Bring Ethernet device up. */ 821 DEBUG("forcing Ethernet interface up"); 822 priv_set_flags(priv, ~IFF_UP, IFF_UP); 823 mlx5_link_update(priv->dev, 1); 824 continue; 825 826 port_error: 827 if (priv) { 828 rte_free(priv->rss_conf); 829 rte_free(priv); 830 } 831 if (pd) 832 claim_zero(ibv_dealloc_pd(pd)); 833 if (ctx) 834 claim_zero(ibv_close_device(ctx)); 835 break; 836 } 837 838 /* 839 * XXX if something went wrong in the loop above, there is a resource 840 * leak (ctx, pd, priv, dpdk ethdev) but we can do nothing about it as 841 * long as the dpdk does not provide a way to deallocate a ethdev and a 842 * way to enumerate the registered ethdevs to free the previous ones. 843 */ 844 845 /* no port found, complain */ 846 if (!mlx5_dev[idx].ports) { 847 err = ENODEV; 848 goto error; 849 } 850 851 error: 852 if (attr_ctx) 853 claim_zero(ibv_close_device(attr_ctx)); 854 if (list) 855 ibv_free_device_list(list); 856 assert(err >= 0); 857 return -err; 858 } 859 860 static const struct rte_pci_id mlx5_pci_id_map[] = { 861 { 862 RTE_PCI_DEVICE(PCI_VENDOR_ID_MELLANOX, 863 PCI_DEVICE_ID_MELLANOX_CONNECTX4) 864 }, 865 { 866 RTE_PCI_DEVICE(PCI_VENDOR_ID_MELLANOX, 867 PCI_DEVICE_ID_MELLANOX_CONNECTX4VF) 868 }, 869 { 870 RTE_PCI_DEVICE(PCI_VENDOR_ID_MELLANOX, 871 PCI_DEVICE_ID_MELLANOX_CONNECTX4LX) 872 }, 873 { 874 RTE_PCI_DEVICE(PCI_VENDOR_ID_MELLANOX, 875 PCI_DEVICE_ID_MELLANOX_CONNECTX4LXVF) 876 }, 877 { 878 RTE_PCI_DEVICE(PCI_VENDOR_ID_MELLANOX, 879 PCI_DEVICE_ID_MELLANOX_CONNECTX5) 880 }, 881 { 882 RTE_PCI_DEVICE(PCI_VENDOR_ID_MELLANOX, 883 PCI_DEVICE_ID_MELLANOX_CONNECTX5VF) 884 }, 885 { 886 RTE_PCI_DEVICE(PCI_VENDOR_ID_MELLANOX, 887 PCI_DEVICE_ID_MELLANOX_CONNECTX5EX) 888 }, 889 { 890 RTE_PCI_DEVICE(PCI_VENDOR_ID_MELLANOX, 891 PCI_DEVICE_ID_MELLANOX_CONNECTX5EXVF) 892 }, 893 { 894 .vendor_id = 0 895 } 896 }; 897 898 static struct rte_pci_driver mlx5_driver = { 899 .driver = { 900 .name = MLX5_DRIVER_NAME 901 }, 902 .id_table = mlx5_pci_id_map, 903 .probe = mlx5_pci_probe, 904 .drv_flags = RTE_PCI_DRV_INTR_LSC, 905 }; 906 907 /** 908 * Driver initialization routine. 909 */ 910 RTE_INIT(rte_mlx5_pmd_init); 911 static void 912 rte_mlx5_pmd_init(void) 913 { 914 /* Build the static table for ptype conversion. */ 915 mlx5_set_ptype_table(); 916 /* 917 * RDMAV_HUGEPAGES_SAFE tells ibv_fork_init() we intend to use 918 * huge pages. Calling ibv_fork_init() during init allows 919 * applications to use fork() safely for purposes other than 920 * using this PMD, which is not supported in forked processes. 921 */ 922 setenv("RDMAV_HUGEPAGES_SAFE", "1", 1); 923 ibv_fork_init(); 924 rte_pci_register(&mlx5_driver); 925 } 926 927 RTE_PMD_EXPORT_NAME(net_mlx5, __COUNTER__); 928 RTE_PMD_REGISTER_PCI_TABLE(net_mlx5, mlx5_pci_id_map); 929 RTE_PMD_REGISTER_KMOD_DEP(net_mlx5, "* ib_uverbs & mlx5_core & mlx5_ib"); 930