1 /* SPDX-License-Identifier: BSD-3-Clause 2 * Copyright 2015 6WIND S.A. 3 * Copyright 2015 Mellanox Technologies, Ltd 4 */ 5 6 #include <stddef.h> 7 #include <unistd.h> 8 #include <string.h> 9 #include <assert.h> 10 #include <dlfcn.h> 11 #include <stdint.h> 12 #include <stdlib.h> 13 #include <errno.h> 14 #include <net/if.h> 15 #include <sys/mman.h> 16 #include <linux/rtnetlink.h> 17 18 /* Verbs header. */ 19 /* ISO C doesn't support unnamed structs/unions, disabling -pedantic. */ 20 #ifdef PEDANTIC 21 #pragma GCC diagnostic ignored "-Wpedantic" 22 #endif 23 #include <infiniband/verbs.h> 24 #ifdef PEDANTIC 25 #pragma GCC diagnostic error "-Wpedantic" 26 #endif 27 28 #include <rte_malloc.h> 29 #include <rte_ethdev_driver.h> 30 #include <rte_ethdev_pci.h> 31 #include <rte_pci.h> 32 #include <rte_bus_pci.h> 33 #include <rte_common.h> 34 #include <rte_config.h> 35 #include <rte_eal_memconfig.h> 36 #include <rte_kvargs.h> 37 #include <rte_rwlock.h> 38 #include <rte_spinlock.h> 39 #include <rte_string_fns.h> 40 #include <rte_alarm.h> 41 42 #include "mlx5.h" 43 #include "mlx5_utils.h" 44 #include "mlx5_rxtx.h" 45 #include "mlx5_autoconf.h" 46 #include "mlx5_defs.h" 47 #include "mlx5_glue.h" 48 #include "mlx5_mr.h" 49 #include "mlx5_flow.h" 50 51 /* Device parameter to enable RX completion queue compression. */ 52 #define MLX5_RXQ_CQE_COMP_EN "rxq_cqe_comp_en" 53 54 /* Device parameter to enable RX completion entry padding to 128B. */ 55 #define MLX5_RXQ_CQE_PAD_EN "rxq_cqe_pad_en" 56 57 /* Device parameter to enable padding Rx packet to cacheline size. */ 58 #define MLX5_RXQ_PKT_PAD_EN "rxq_pkt_pad_en" 59 60 /* Device parameter to enable Multi-Packet Rx queue. */ 61 #define MLX5_RX_MPRQ_EN "mprq_en" 62 63 /* Device parameter to configure log 2 of the number of strides for MPRQ. */ 64 #define MLX5_RX_MPRQ_LOG_STRIDE_NUM "mprq_log_stride_num" 65 66 /* Device parameter to limit the size of memcpy'd packet for MPRQ. */ 67 #define MLX5_RX_MPRQ_MAX_MEMCPY_LEN "mprq_max_memcpy_len" 68 69 /* Device parameter to set the minimum number of Rx queues to enable MPRQ. */ 70 #define MLX5_RXQS_MIN_MPRQ "rxqs_min_mprq" 71 72 /* Device parameter to configure inline send. Deprecated, ignored.*/ 73 #define MLX5_TXQ_INLINE "txq_inline" 74 75 /* Device parameter to limit packet size to inline with ordinary SEND. */ 76 #define MLX5_TXQ_INLINE_MAX "txq_inline_max" 77 78 /* Device parameter to configure minimal data size to inline. */ 79 #define MLX5_TXQ_INLINE_MIN "txq_inline_min" 80 81 /* Device parameter to limit packet size to inline with Enhanced MPW. */ 82 #define MLX5_TXQ_INLINE_MPW "txq_inline_mpw" 83 84 /* 85 * Device parameter to configure the number of TX queues threshold for 86 * enabling inline send. 87 */ 88 #define MLX5_TXQS_MIN_INLINE "txqs_min_inline" 89 90 /* 91 * Device parameter to configure the number of TX queues threshold for 92 * enabling vectorized Tx, deprecated, ignored (no vectorized Tx routines). 93 */ 94 #define MLX5_TXQS_MAX_VEC "txqs_max_vec" 95 96 /* Device parameter to enable multi-packet send WQEs. */ 97 #define MLX5_TXQ_MPW_EN "txq_mpw_en" 98 99 /* 100 * Device parameter to include 2 dsegs in the title WQEBB. 101 * Deprecated, ignored. 102 */ 103 #define MLX5_TXQ_MPW_HDR_DSEG_EN "txq_mpw_hdr_dseg_en" 104 105 /* 106 * Device parameter to limit the size of inlining packet. 107 * Deprecated, ignored. 108 */ 109 #define MLX5_TXQ_MAX_INLINE_LEN "txq_max_inline_len" 110 111 /* 112 * Device parameter to enable hardware Tx vector. 113 * Deprecated, ignored (no vectorized Tx routines anymore). 114 */ 115 #define MLX5_TX_VEC_EN "tx_vec_en" 116 117 /* Device parameter to enable hardware Rx vector. */ 118 #define MLX5_RX_VEC_EN "rx_vec_en" 119 120 /* Allow L3 VXLAN flow creation. */ 121 #define MLX5_L3_VXLAN_EN "l3_vxlan_en" 122 123 /* Activate DV E-Switch flow steering. */ 124 #define MLX5_DV_ESW_EN "dv_esw_en" 125 126 /* Activate DV flow steering. */ 127 #define MLX5_DV_FLOW_EN "dv_flow_en" 128 129 /* Activate Netlink support in VF mode. */ 130 #define MLX5_VF_NL_EN "vf_nl_en" 131 132 /* Enable extending memsegs when creating a MR. */ 133 #define MLX5_MR_EXT_MEMSEG_EN "mr_ext_memseg_en" 134 135 /* Select port representors to instantiate. */ 136 #define MLX5_REPRESENTOR "representor" 137 138 /* Device parameter to configure the maximum number of dump files per queue. */ 139 #define MLX5_MAX_DUMP_FILES_NUM "max_dump_files_num" 140 141 /* Configure timeout of LRO session (in microseconds). */ 142 #define MLX5_LRO_TIMEOUT_USEC "lro_timeout_usec" 143 144 #ifndef HAVE_IBV_MLX5_MOD_MPW 145 #define MLX5DV_CONTEXT_FLAGS_MPW_ALLOWED (1 << 2) 146 #define MLX5DV_CONTEXT_FLAGS_ENHANCED_MPW (1 << 3) 147 #endif 148 149 #ifndef HAVE_IBV_MLX5_MOD_CQE_128B_COMP 150 #define MLX5DV_CONTEXT_FLAGS_CQE_128B_COMP (1 << 4) 151 #endif 152 153 static const char *MZ_MLX5_PMD_SHARED_DATA = "mlx5_pmd_shared_data"; 154 155 /* Shared memory between primary and secondary processes. */ 156 struct mlx5_shared_data *mlx5_shared_data; 157 158 /* Spinlock for mlx5_shared_data allocation. */ 159 static rte_spinlock_t mlx5_shared_data_lock = RTE_SPINLOCK_INITIALIZER; 160 161 /* Process local data for secondary processes. */ 162 static struct mlx5_local_data mlx5_local_data; 163 164 /** Driver-specific log messages type. */ 165 int mlx5_logtype; 166 167 /** Data associated with devices to spawn. */ 168 struct mlx5_dev_spawn_data { 169 uint32_t ifindex; /**< Network interface index. */ 170 uint32_t max_port; /**< IB device maximal port index. */ 171 uint32_t ibv_port; /**< IB device physical port index. */ 172 struct mlx5_switch_info info; /**< Switch information. */ 173 struct ibv_device *ibv_dev; /**< Associated IB device. */ 174 struct rte_eth_dev *eth_dev; /**< Associated Ethernet device. */ 175 struct rte_pci_device *pci_dev; /**< Backend PCI device. */ 176 }; 177 178 static LIST_HEAD(, mlx5_ibv_shared) mlx5_ibv_list = LIST_HEAD_INITIALIZER(); 179 static pthread_mutex_t mlx5_ibv_list_mutex = PTHREAD_MUTEX_INITIALIZER; 180 181 /** 182 * Initialize the counters management structure. 183 * 184 * @param[in] sh 185 * Pointer to mlx5_ibv_shared object to free 186 */ 187 static void 188 mlx5_flow_counters_mng_init(struct mlx5_ibv_shared *sh) 189 { 190 uint8_t i; 191 192 TAILQ_INIT(&sh->cmng.flow_counters); 193 for (i = 0; i < RTE_DIM(sh->cmng.ccont); ++i) 194 TAILQ_INIT(&sh->cmng.ccont[i].pool_list); 195 } 196 197 /** 198 * Destroy all the resources allocated for a counter memory management. 199 * 200 * @param[in] mng 201 * Pointer to the memory management structure. 202 */ 203 static void 204 mlx5_flow_destroy_counter_stat_mem_mng(struct mlx5_counter_stats_mem_mng *mng) 205 { 206 uint8_t *mem = (uint8_t *)(uintptr_t)mng->raws[0].data; 207 208 LIST_REMOVE(mng, next); 209 claim_zero(mlx5_devx_cmd_destroy(mng->dm)); 210 claim_zero(mlx5_glue->devx_umem_dereg(mng->umem)); 211 rte_free(mem); 212 } 213 214 /** 215 * Close and release all the resources of the counters management. 216 * 217 * @param[in] sh 218 * Pointer to mlx5_ibv_shared object to free. 219 */ 220 static void 221 mlx5_flow_counters_mng_close(struct mlx5_ibv_shared *sh) 222 { 223 struct mlx5_counter_stats_mem_mng *mng; 224 uint8_t i; 225 int j; 226 int retries = 1024; 227 228 rte_errno = 0; 229 while (--retries) { 230 rte_eal_alarm_cancel(mlx5_flow_query_alarm, sh); 231 if (rte_errno != EINPROGRESS) 232 break; 233 rte_pause(); 234 } 235 for (i = 0; i < RTE_DIM(sh->cmng.ccont); ++i) { 236 struct mlx5_flow_counter_pool *pool; 237 uint32_t batch = !!(i % 2); 238 239 if (!sh->cmng.ccont[i].pools) 240 continue; 241 pool = TAILQ_FIRST(&sh->cmng.ccont[i].pool_list); 242 while (pool) { 243 if (batch) { 244 if (pool->min_dcs) 245 claim_zero 246 (mlx5_devx_cmd_destroy(pool->min_dcs)); 247 } 248 for (j = 0; j < MLX5_COUNTERS_PER_POOL; ++j) { 249 if (pool->counters_raw[j].action) 250 claim_zero 251 (mlx5_glue->destroy_flow_action 252 (pool->counters_raw[j].action)); 253 if (!batch && pool->counters_raw[j].dcs) 254 claim_zero(mlx5_devx_cmd_destroy 255 (pool->counters_raw[j].dcs)); 256 } 257 TAILQ_REMOVE(&sh->cmng.ccont[i].pool_list, pool, 258 next); 259 rte_free(pool); 260 pool = TAILQ_FIRST(&sh->cmng.ccont[i].pool_list); 261 } 262 rte_free(sh->cmng.ccont[i].pools); 263 } 264 mng = LIST_FIRST(&sh->cmng.mem_mngs); 265 while (mng) { 266 mlx5_flow_destroy_counter_stat_mem_mng(mng); 267 mng = LIST_FIRST(&sh->cmng.mem_mngs); 268 } 269 memset(&sh->cmng, 0, sizeof(sh->cmng)); 270 } 271 272 /** 273 * Extract pdn of PD object using DV API. 274 * 275 * @param[in] pd 276 * Pointer to the verbs PD object. 277 * @param[out] pdn 278 * Pointer to the PD object number variable. 279 * 280 * @return 281 * 0 on success, error value otherwise. 282 */ 283 #ifdef HAVE_IBV_FLOW_DV_SUPPORT 284 static int 285 mlx5_get_pdn(struct ibv_pd *pd __rte_unused, uint32_t *pdn __rte_unused) 286 { 287 struct mlx5dv_obj obj; 288 struct mlx5dv_pd pd_info; 289 int ret = 0; 290 291 obj.pd.in = pd; 292 obj.pd.out = &pd_info; 293 ret = mlx5_glue->dv_init_obj(&obj, MLX5DV_OBJ_PD); 294 if (ret) { 295 DRV_LOG(DEBUG, "Fail to get PD object info"); 296 return ret; 297 } 298 *pdn = pd_info.pdn; 299 return 0; 300 } 301 #endif /* HAVE_IBV_FLOW_DV_SUPPORT */ 302 303 /** 304 * Allocate shared IB device context. If there is multiport device the 305 * master and representors will share this context, if there is single 306 * port dedicated IB device, the context will be used by only given 307 * port due to unification. 308 * 309 * Routine first searches the context for the specified IB device name, 310 * if found the shared context assumed and reference counter is incremented. 311 * If no context found the new one is created and initialized with specified 312 * IB device context and parameters. 313 * 314 * @param[in] spawn 315 * Pointer to the IB device attributes (name, port, etc). 316 * 317 * @return 318 * Pointer to mlx5_ibv_shared object on success, 319 * otherwise NULL and rte_errno is set. 320 */ 321 static struct mlx5_ibv_shared * 322 mlx5_alloc_shared_ibctx(const struct mlx5_dev_spawn_data *spawn) 323 { 324 struct mlx5_ibv_shared *sh; 325 int err = 0; 326 uint32_t i; 327 328 assert(spawn); 329 /* Secondary process should not create the shared context. */ 330 assert(rte_eal_process_type() == RTE_PROC_PRIMARY); 331 pthread_mutex_lock(&mlx5_ibv_list_mutex); 332 /* Search for IB context by device name. */ 333 LIST_FOREACH(sh, &mlx5_ibv_list, next) { 334 if (!strcmp(sh->ibdev_name, spawn->ibv_dev->name)) { 335 sh->refcnt++; 336 goto exit; 337 } 338 } 339 /* No device found, we have to create new shared context. */ 340 assert(spawn->max_port); 341 sh = rte_zmalloc("ethdev shared ib context", 342 sizeof(struct mlx5_ibv_shared) + 343 spawn->max_port * 344 sizeof(struct mlx5_ibv_shared_port), 345 RTE_CACHE_LINE_SIZE); 346 if (!sh) { 347 DRV_LOG(ERR, "shared context allocation failure"); 348 rte_errno = ENOMEM; 349 goto exit; 350 } 351 /* Try to open IB device with DV first, then usual Verbs. */ 352 errno = 0; 353 sh->ctx = mlx5_glue->dv_open_device(spawn->ibv_dev); 354 if (sh->ctx) { 355 sh->devx = 1; 356 DRV_LOG(DEBUG, "DevX is supported"); 357 } else { 358 sh->ctx = mlx5_glue->open_device(spawn->ibv_dev); 359 if (!sh->ctx) { 360 err = errno ? errno : ENODEV; 361 goto error; 362 } 363 DRV_LOG(DEBUG, "DevX is NOT supported"); 364 } 365 err = mlx5_glue->query_device_ex(sh->ctx, NULL, &sh->device_attr); 366 if (err) { 367 DRV_LOG(DEBUG, "ibv_query_device_ex() failed"); 368 goto error; 369 } 370 sh->refcnt = 1; 371 sh->max_port = spawn->max_port; 372 strncpy(sh->ibdev_name, sh->ctx->device->name, 373 sizeof(sh->ibdev_name)); 374 strncpy(sh->ibdev_path, sh->ctx->device->ibdev_path, 375 sizeof(sh->ibdev_path)); 376 sh->pci_dev = spawn->pci_dev; 377 pthread_mutex_init(&sh->intr_mutex, NULL); 378 /* 379 * Setting port_id to max unallowed value means 380 * there is no interrupt subhandler installed for 381 * the given port index i. 382 */ 383 for (i = 0; i < sh->max_port; i++) 384 sh->port[i].ih_port_id = RTE_MAX_ETHPORTS; 385 sh->pd = mlx5_glue->alloc_pd(sh->ctx); 386 if (sh->pd == NULL) { 387 DRV_LOG(ERR, "PD allocation failure"); 388 err = ENOMEM; 389 goto error; 390 } 391 #ifdef HAVE_IBV_FLOW_DV_SUPPORT 392 err = mlx5_get_pdn(sh->pd, &sh->pdn); 393 if (err) { 394 DRV_LOG(ERR, "Fail to extract pdn from PD"); 395 goto error; 396 } 397 #endif /* HAVE_IBV_FLOW_DV_SUPPORT */ 398 /* 399 * Once the device is added to the list of memory event 400 * callback, its global MR cache table cannot be expanded 401 * on the fly because of deadlock. If it overflows, lookup 402 * should be done by searching MR list linearly, which is slow. 403 * 404 * At this point the device is not added to the memory 405 * event list yet, context is just being created. 406 */ 407 err = mlx5_mr_btree_init(&sh->mr.cache, 408 MLX5_MR_BTREE_CACHE_N * 2, 409 sh->pci_dev->device.numa_node); 410 if (err) { 411 err = rte_errno; 412 goto error; 413 } 414 mlx5_flow_counters_mng_init(sh); 415 LIST_INSERT_HEAD(&mlx5_ibv_list, sh, next); 416 exit: 417 pthread_mutex_unlock(&mlx5_ibv_list_mutex); 418 return sh; 419 error: 420 pthread_mutex_unlock(&mlx5_ibv_list_mutex); 421 assert(sh); 422 if (sh->pd) 423 claim_zero(mlx5_glue->dealloc_pd(sh->pd)); 424 if (sh->ctx) 425 claim_zero(mlx5_glue->close_device(sh->ctx)); 426 rte_free(sh); 427 assert(err > 0); 428 rte_errno = err; 429 return NULL; 430 } 431 432 /** 433 * Free shared IB device context. Decrement counter and if zero free 434 * all allocated resources and close handles. 435 * 436 * @param[in] sh 437 * Pointer to mlx5_ibv_shared object to free 438 */ 439 static void 440 mlx5_free_shared_ibctx(struct mlx5_ibv_shared *sh) 441 { 442 pthread_mutex_lock(&mlx5_ibv_list_mutex); 443 #ifndef NDEBUG 444 /* Check the object presence in the list. */ 445 struct mlx5_ibv_shared *lctx; 446 447 LIST_FOREACH(lctx, &mlx5_ibv_list, next) 448 if (lctx == sh) 449 break; 450 assert(lctx); 451 if (lctx != sh) { 452 DRV_LOG(ERR, "Freeing non-existing shared IB context"); 453 goto exit; 454 } 455 #endif 456 assert(sh); 457 assert(sh->refcnt); 458 /* Secondary process should not free the shared context. */ 459 assert(rte_eal_process_type() == RTE_PROC_PRIMARY); 460 if (--sh->refcnt) 461 goto exit; 462 /* Release created Memory Regions. */ 463 mlx5_mr_release(sh); 464 LIST_REMOVE(sh, next); 465 /* 466 * Ensure there is no async event handler installed. 467 * Only primary process handles async device events. 468 **/ 469 mlx5_flow_counters_mng_close(sh); 470 assert(!sh->intr_cnt); 471 if (sh->intr_cnt) 472 mlx5_intr_callback_unregister 473 (&sh->intr_handle, mlx5_dev_interrupt_handler, sh); 474 pthread_mutex_destroy(&sh->intr_mutex); 475 if (sh->pd) 476 claim_zero(mlx5_glue->dealloc_pd(sh->pd)); 477 if (sh->ctx) 478 claim_zero(mlx5_glue->close_device(sh->ctx)); 479 rte_free(sh); 480 exit: 481 pthread_mutex_unlock(&mlx5_ibv_list_mutex); 482 } 483 484 /** 485 * Initialize DR related data within private structure. 486 * Routine checks the reference counter and does actual 487 * resources creation/initialization only if counter is zero. 488 * 489 * @param[in] priv 490 * Pointer to the private device data structure. 491 * 492 * @return 493 * Zero on success, positive error code otherwise. 494 */ 495 static int 496 mlx5_alloc_shared_dr(struct mlx5_priv *priv) 497 { 498 #ifdef HAVE_MLX5DV_DR 499 struct mlx5_ibv_shared *sh = priv->sh; 500 int err = 0; 501 void *domain; 502 503 assert(sh); 504 if (sh->dv_refcnt) { 505 /* Shared DV/DR structures is already initialized. */ 506 sh->dv_refcnt++; 507 priv->dr_shared = 1; 508 return 0; 509 } 510 /* Reference counter is zero, we should initialize structures. */ 511 domain = mlx5_glue->dr_create_domain(sh->ctx, 512 MLX5DV_DR_DOMAIN_TYPE_NIC_RX); 513 if (!domain) { 514 DRV_LOG(ERR, "ingress mlx5dv_dr_create_domain failed"); 515 err = errno; 516 goto error; 517 } 518 sh->rx_domain = domain; 519 domain = mlx5_glue->dr_create_domain(sh->ctx, 520 MLX5DV_DR_DOMAIN_TYPE_NIC_TX); 521 if (!domain) { 522 DRV_LOG(ERR, "egress mlx5dv_dr_create_domain failed"); 523 err = errno; 524 goto error; 525 } 526 pthread_mutex_init(&sh->dv_mutex, NULL); 527 sh->tx_domain = domain; 528 #ifdef HAVE_MLX5DV_DR_ESWITCH 529 if (priv->config.dv_esw_en) { 530 domain = mlx5_glue->dr_create_domain 531 (sh->ctx, MLX5DV_DR_DOMAIN_TYPE_FDB); 532 if (!domain) { 533 DRV_LOG(ERR, "FDB mlx5dv_dr_create_domain failed"); 534 err = errno; 535 goto error; 536 } 537 sh->fdb_domain = domain; 538 sh->esw_drop_action = mlx5_glue->dr_create_flow_action_drop(); 539 } 540 #endif 541 sh->dv_refcnt++; 542 priv->dr_shared = 1; 543 return 0; 544 545 error: 546 /* Rollback the created objects. */ 547 if (sh->rx_domain) { 548 mlx5_glue->dr_destroy_domain(sh->rx_domain); 549 sh->rx_domain = NULL; 550 } 551 if (sh->tx_domain) { 552 mlx5_glue->dr_destroy_domain(sh->tx_domain); 553 sh->tx_domain = NULL; 554 } 555 if (sh->fdb_domain) { 556 mlx5_glue->dr_destroy_domain(sh->fdb_domain); 557 sh->fdb_domain = NULL; 558 } 559 if (sh->esw_drop_action) { 560 mlx5_glue->destroy_flow_action(sh->esw_drop_action); 561 sh->esw_drop_action = NULL; 562 } 563 return err; 564 #else 565 (void)priv; 566 return 0; 567 #endif 568 } 569 570 /** 571 * Destroy DR related data within private structure. 572 * 573 * @param[in] priv 574 * Pointer to the private device data structure. 575 */ 576 static void 577 mlx5_free_shared_dr(struct mlx5_priv *priv) 578 { 579 #ifdef HAVE_MLX5DV_DR 580 struct mlx5_ibv_shared *sh; 581 582 if (!priv->dr_shared) 583 return; 584 priv->dr_shared = 0; 585 sh = priv->sh; 586 assert(sh); 587 assert(sh->dv_refcnt); 588 if (sh->dv_refcnt && --sh->dv_refcnt) 589 return; 590 if (sh->rx_domain) { 591 mlx5_glue->dr_destroy_domain(sh->rx_domain); 592 sh->rx_domain = NULL; 593 } 594 if (sh->tx_domain) { 595 mlx5_glue->dr_destroy_domain(sh->tx_domain); 596 sh->tx_domain = NULL; 597 } 598 #ifdef HAVE_MLX5DV_DR_ESWITCH 599 if (sh->fdb_domain) { 600 mlx5_glue->dr_destroy_domain(sh->fdb_domain); 601 sh->fdb_domain = NULL; 602 } 603 if (sh->esw_drop_action) { 604 mlx5_glue->destroy_flow_action(sh->esw_drop_action); 605 sh->esw_drop_action = NULL; 606 } 607 #endif 608 pthread_mutex_destroy(&sh->dv_mutex); 609 #else 610 (void)priv; 611 #endif 612 } 613 614 /** 615 * Initialize shared data between primary and secondary process. 616 * 617 * A memzone is reserved by primary process and secondary processes attach to 618 * the memzone. 619 * 620 * @return 621 * 0 on success, a negative errno value otherwise and rte_errno is set. 622 */ 623 static int 624 mlx5_init_shared_data(void) 625 { 626 const struct rte_memzone *mz; 627 int ret = 0; 628 629 rte_spinlock_lock(&mlx5_shared_data_lock); 630 if (mlx5_shared_data == NULL) { 631 if (rte_eal_process_type() == RTE_PROC_PRIMARY) { 632 /* Allocate shared memory. */ 633 mz = rte_memzone_reserve(MZ_MLX5_PMD_SHARED_DATA, 634 sizeof(*mlx5_shared_data), 635 SOCKET_ID_ANY, 0); 636 if (mz == NULL) { 637 DRV_LOG(ERR, 638 "Cannot allocate mlx5 shared data\n"); 639 ret = -rte_errno; 640 goto error; 641 } 642 mlx5_shared_data = mz->addr; 643 memset(mlx5_shared_data, 0, sizeof(*mlx5_shared_data)); 644 rte_spinlock_init(&mlx5_shared_data->lock); 645 } else { 646 /* Lookup allocated shared memory. */ 647 mz = rte_memzone_lookup(MZ_MLX5_PMD_SHARED_DATA); 648 if (mz == NULL) { 649 DRV_LOG(ERR, 650 "Cannot attach mlx5 shared data\n"); 651 ret = -rte_errno; 652 goto error; 653 } 654 mlx5_shared_data = mz->addr; 655 memset(&mlx5_local_data, 0, sizeof(mlx5_local_data)); 656 } 657 } 658 error: 659 rte_spinlock_unlock(&mlx5_shared_data_lock); 660 return ret; 661 } 662 663 /** 664 * Retrieve integer value from environment variable. 665 * 666 * @param[in] name 667 * Environment variable name. 668 * 669 * @return 670 * Integer value, 0 if the variable is not set. 671 */ 672 int 673 mlx5_getenv_int(const char *name) 674 { 675 const char *val = getenv(name); 676 677 if (val == NULL) 678 return 0; 679 return atoi(val); 680 } 681 682 /** 683 * Verbs callback to allocate a memory. This function should allocate the space 684 * according to the size provided residing inside a huge page. 685 * Please note that all allocation must respect the alignment from libmlx5 686 * (i.e. currently sysconf(_SC_PAGESIZE)). 687 * 688 * @param[in] size 689 * The size in bytes of the memory to allocate. 690 * @param[in] data 691 * A pointer to the callback data. 692 * 693 * @return 694 * Allocated buffer, NULL otherwise and rte_errno is set. 695 */ 696 static void * 697 mlx5_alloc_verbs_buf(size_t size, void *data) 698 { 699 struct mlx5_priv *priv = data; 700 void *ret; 701 size_t alignment = sysconf(_SC_PAGESIZE); 702 unsigned int socket = SOCKET_ID_ANY; 703 704 if (priv->verbs_alloc_ctx.type == MLX5_VERBS_ALLOC_TYPE_TX_QUEUE) { 705 const struct mlx5_txq_ctrl *ctrl = priv->verbs_alloc_ctx.obj; 706 707 socket = ctrl->socket; 708 } else if (priv->verbs_alloc_ctx.type == 709 MLX5_VERBS_ALLOC_TYPE_RX_QUEUE) { 710 const struct mlx5_rxq_ctrl *ctrl = priv->verbs_alloc_ctx.obj; 711 712 socket = ctrl->socket; 713 } 714 assert(data != NULL); 715 ret = rte_malloc_socket(__func__, size, alignment, socket); 716 if (!ret && size) 717 rte_errno = ENOMEM; 718 return ret; 719 } 720 721 /** 722 * Verbs callback to free a memory. 723 * 724 * @param[in] ptr 725 * A pointer to the memory to free. 726 * @param[in] data 727 * A pointer to the callback data. 728 */ 729 static void 730 mlx5_free_verbs_buf(void *ptr, void *data __rte_unused) 731 { 732 assert(data != NULL); 733 rte_free(ptr); 734 } 735 736 /** 737 * Initialize process private data structure. 738 * 739 * @param dev 740 * Pointer to Ethernet device structure. 741 * 742 * @return 743 * 0 on success, a negative errno value otherwise and rte_errno is set. 744 */ 745 int 746 mlx5_proc_priv_init(struct rte_eth_dev *dev) 747 { 748 struct mlx5_priv *priv = dev->data->dev_private; 749 struct mlx5_proc_priv *ppriv; 750 size_t ppriv_size; 751 752 /* 753 * UAR register table follows the process private structure. BlueFlame 754 * registers for Tx queues are stored in the table. 755 */ 756 ppriv_size = 757 sizeof(struct mlx5_proc_priv) + priv->txqs_n * sizeof(void *); 758 ppriv = rte_malloc_socket("mlx5_proc_priv", ppriv_size, 759 RTE_CACHE_LINE_SIZE, dev->device->numa_node); 760 if (!ppriv) { 761 rte_errno = ENOMEM; 762 return -rte_errno; 763 } 764 ppriv->uar_table_sz = ppriv_size; 765 dev->process_private = ppriv; 766 return 0; 767 } 768 769 /** 770 * Un-initialize process private data structure. 771 * 772 * @param dev 773 * Pointer to Ethernet device structure. 774 */ 775 static void 776 mlx5_proc_priv_uninit(struct rte_eth_dev *dev) 777 { 778 if (!dev->process_private) 779 return; 780 rte_free(dev->process_private); 781 dev->process_private = NULL; 782 } 783 784 /** 785 * DPDK callback to close the device. 786 * 787 * Destroy all queues and objects, free memory. 788 * 789 * @param dev 790 * Pointer to Ethernet device structure. 791 */ 792 static void 793 mlx5_dev_close(struct rte_eth_dev *dev) 794 { 795 struct mlx5_priv *priv = dev->data->dev_private; 796 unsigned int i; 797 int ret; 798 799 DRV_LOG(DEBUG, "port %u closing device \"%s\"", 800 dev->data->port_id, 801 ((priv->sh->ctx != NULL) ? priv->sh->ctx->device->name : "")); 802 /* In case mlx5_dev_stop() has not been called. */ 803 mlx5_dev_interrupt_handler_uninstall(dev); 804 mlx5_traffic_disable(dev); 805 mlx5_flow_flush(dev, NULL); 806 /* Prevent crashes when queues are still in use. */ 807 dev->rx_pkt_burst = removed_rx_burst; 808 dev->tx_pkt_burst = removed_tx_burst; 809 rte_wmb(); 810 /* Disable datapath on secondary process. */ 811 mlx5_mp_req_stop_rxtx(dev); 812 if (priv->rxqs != NULL) { 813 /* XXX race condition if mlx5_rx_burst() is still running. */ 814 usleep(1000); 815 for (i = 0; (i != priv->rxqs_n); ++i) 816 mlx5_rxq_release(dev, i); 817 priv->rxqs_n = 0; 818 priv->rxqs = NULL; 819 } 820 if (priv->txqs != NULL) { 821 /* XXX race condition if mlx5_tx_burst() is still running. */ 822 usleep(1000); 823 for (i = 0; (i != priv->txqs_n); ++i) 824 mlx5_txq_release(dev, i); 825 priv->txqs_n = 0; 826 priv->txqs = NULL; 827 } 828 mlx5_proc_priv_uninit(dev); 829 mlx5_mprq_free_mp(dev); 830 /* Remove from memory callback device list. */ 831 rte_rwlock_write_lock(&mlx5_shared_data->mem_event_rwlock); 832 assert(priv->sh); 833 LIST_REMOVE(priv->sh, mem_event_cb); 834 rte_rwlock_write_unlock(&mlx5_shared_data->mem_event_rwlock); 835 mlx5_free_shared_dr(priv); 836 if (priv->rss_conf.rss_key != NULL) 837 rte_free(priv->rss_conf.rss_key); 838 if (priv->reta_idx != NULL) 839 rte_free(priv->reta_idx); 840 if (priv->config.vf) 841 mlx5_nl_mac_addr_flush(dev); 842 if (priv->nl_socket_route >= 0) 843 close(priv->nl_socket_route); 844 if (priv->nl_socket_rdma >= 0) 845 close(priv->nl_socket_rdma); 846 if (priv->sh) { 847 /* 848 * Free the shared context in last turn, because the cleanup 849 * routines above may use some shared fields, like 850 * mlx5_nl_mac_addr_flush() uses ibdev_path for retrieveing 851 * ifindex if Netlink fails. 852 */ 853 mlx5_free_shared_ibctx(priv->sh); 854 priv->sh = NULL; 855 } 856 ret = mlx5_hrxq_verify(dev); 857 if (ret) 858 DRV_LOG(WARNING, "port %u some hash Rx queue still remain", 859 dev->data->port_id); 860 ret = mlx5_ind_table_obj_verify(dev); 861 if (ret) 862 DRV_LOG(WARNING, "port %u some indirection table still remain", 863 dev->data->port_id); 864 ret = mlx5_rxq_obj_verify(dev); 865 if (ret) 866 DRV_LOG(WARNING, "port %u some Rx queue objects still remain", 867 dev->data->port_id); 868 ret = mlx5_rxq_verify(dev); 869 if (ret) 870 DRV_LOG(WARNING, "port %u some Rx queues still remain", 871 dev->data->port_id); 872 ret = mlx5_txq_ibv_verify(dev); 873 if (ret) 874 DRV_LOG(WARNING, "port %u some Verbs Tx queue still remain", 875 dev->data->port_id); 876 ret = mlx5_txq_verify(dev); 877 if (ret) 878 DRV_LOG(WARNING, "port %u some Tx queues still remain", 879 dev->data->port_id); 880 ret = mlx5_flow_verify(dev); 881 if (ret) 882 DRV_LOG(WARNING, "port %u some flows still remain", 883 dev->data->port_id); 884 if (priv->domain_id != RTE_ETH_DEV_SWITCH_DOMAIN_ID_INVALID) { 885 unsigned int c = 0; 886 uint16_t port_id; 887 888 RTE_ETH_FOREACH_DEV_OF(port_id, dev->device) { 889 struct mlx5_priv *opriv = 890 rte_eth_devices[port_id].data->dev_private; 891 892 if (!opriv || 893 opriv->domain_id != priv->domain_id || 894 &rte_eth_devices[port_id] == dev) 895 continue; 896 ++c; 897 } 898 if (!c) 899 claim_zero(rte_eth_switch_domain_free(priv->domain_id)); 900 } 901 memset(priv, 0, sizeof(*priv)); 902 priv->domain_id = RTE_ETH_DEV_SWITCH_DOMAIN_ID_INVALID; 903 /* 904 * Reset mac_addrs to NULL such that it is not freed as part of 905 * rte_eth_dev_release_port(). mac_addrs is part of dev_private so 906 * it is freed when dev_private is freed. 907 */ 908 dev->data->mac_addrs = NULL; 909 } 910 911 const struct eth_dev_ops mlx5_dev_ops = { 912 .dev_configure = mlx5_dev_configure, 913 .dev_start = mlx5_dev_start, 914 .dev_stop = mlx5_dev_stop, 915 .dev_set_link_down = mlx5_set_link_down, 916 .dev_set_link_up = mlx5_set_link_up, 917 .dev_close = mlx5_dev_close, 918 .promiscuous_enable = mlx5_promiscuous_enable, 919 .promiscuous_disable = mlx5_promiscuous_disable, 920 .allmulticast_enable = mlx5_allmulticast_enable, 921 .allmulticast_disable = mlx5_allmulticast_disable, 922 .link_update = mlx5_link_update, 923 .stats_get = mlx5_stats_get, 924 .stats_reset = mlx5_stats_reset, 925 .xstats_get = mlx5_xstats_get, 926 .xstats_reset = mlx5_xstats_reset, 927 .xstats_get_names = mlx5_xstats_get_names, 928 .fw_version_get = mlx5_fw_version_get, 929 .dev_infos_get = mlx5_dev_infos_get, 930 .read_clock = mlx5_read_clock, 931 .dev_supported_ptypes_get = mlx5_dev_supported_ptypes_get, 932 .vlan_filter_set = mlx5_vlan_filter_set, 933 .rx_queue_setup = mlx5_rx_queue_setup, 934 .tx_queue_setup = mlx5_tx_queue_setup, 935 .rx_queue_release = mlx5_rx_queue_release, 936 .tx_queue_release = mlx5_tx_queue_release, 937 .flow_ctrl_get = mlx5_dev_get_flow_ctrl, 938 .flow_ctrl_set = mlx5_dev_set_flow_ctrl, 939 .mac_addr_remove = mlx5_mac_addr_remove, 940 .mac_addr_add = mlx5_mac_addr_add, 941 .mac_addr_set = mlx5_mac_addr_set, 942 .set_mc_addr_list = mlx5_set_mc_addr_list, 943 .mtu_set = mlx5_dev_set_mtu, 944 .vlan_strip_queue_set = mlx5_vlan_strip_queue_set, 945 .vlan_offload_set = mlx5_vlan_offload_set, 946 .reta_update = mlx5_dev_rss_reta_update, 947 .reta_query = mlx5_dev_rss_reta_query, 948 .rss_hash_update = mlx5_rss_hash_update, 949 .rss_hash_conf_get = mlx5_rss_hash_conf_get, 950 .filter_ctrl = mlx5_dev_filter_ctrl, 951 .rx_descriptor_status = mlx5_rx_descriptor_status, 952 .tx_descriptor_status = mlx5_tx_descriptor_status, 953 .rx_queue_count = mlx5_rx_queue_count, 954 .rx_queue_intr_enable = mlx5_rx_intr_enable, 955 .rx_queue_intr_disable = mlx5_rx_intr_disable, 956 .is_removed = mlx5_is_removed, 957 }; 958 959 /* Available operations from secondary process. */ 960 static const struct eth_dev_ops mlx5_dev_sec_ops = { 961 .stats_get = mlx5_stats_get, 962 .stats_reset = mlx5_stats_reset, 963 .xstats_get = mlx5_xstats_get, 964 .xstats_reset = mlx5_xstats_reset, 965 .xstats_get_names = mlx5_xstats_get_names, 966 .fw_version_get = mlx5_fw_version_get, 967 .dev_infos_get = mlx5_dev_infos_get, 968 .rx_descriptor_status = mlx5_rx_descriptor_status, 969 .tx_descriptor_status = mlx5_tx_descriptor_status, 970 }; 971 972 /* Available operations in flow isolated mode. */ 973 const struct eth_dev_ops mlx5_dev_ops_isolate = { 974 .dev_configure = mlx5_dev_configure, 975 .dev_start = mlx5_dev_start, 976 .dev_stop = mlx5_dev_stop, 977 .dev_set_link_down = mlx5_set_link_down, 978 .dev_set_link_up = mlx5_set_link_up, 979 .dev_close = mlx5_dev_close, 980 .promiscuous_enable = mlx5_promiscuous_enable, 981 .promiscuous_disable = mlx5_promiscuous_disable, 982 .allmulticast_enable = mlx5_allmulticast_enable, 983 .allmulticast_disable = mlx5_allmulticast_disable, 984 .link_update = mlx5_link_update, 985 .stats_get = mlx5_stats_get, 986 .stats_reset = mlx5_stats_reset, 987 .xstats_get = mlx5_xstats_get, 988 .xstats_reset = mlx5_xstats_reset, 989 .xstats_get_names = mlx5_xstats_get_names, 990 .fw_version_get = mlx5_fw_version_get, 991 .dev_infos_get = mlx5_dev_infos_get, 992 .dev_supported_ptypes_get = mlx5_dev_supported_ptypes_get, 993 .vlan_filter_set = mlx5_vlan_filter_set, 994 .rx_queue_setup = mlx5_rx_queue_setup, 995 .tx_queue_setup = mlx5_tx_queue_setup, 996 .rx_queue_release = mlx5_rx_queue_release, 997 .tx_queue_release = mlx5_tx_queue_release, 998 .flow_ctrl_get = mlx5_dev_get_flow_ctrl, 999 .flow_ctrl_set = mlx5_dev_set_flow_ctrl, 1000 .mac_addr_remove = mlx5_mac_addr_remove, 1001 .mac_addr_add = mlx5_mac_addr_add, 1002 .mac_addr_set = mlx5_mac_addr_set, 1003 .set_mc_addr_list = mlx5_set_mc_addr_list, 1004 .mtu_set = mlx5_dev_set_mtu, 1005 .vlan_strip_queue_set = mlx5_vlan_strip_queue_set, 1006 .vlan_offload_set = mlx5_vlan_offload_set, 1007 .filter_ctrl = mlx5_dev_filter_ctrl, 1008 .rx_descriptor_status = mlx5_rx_descriptor_status, 1009 .tx_descriptor_status = mlx5_tx_descriptor_status, 1010 .rx_queue_intr_enable = mlx5_rx_intr_enable, 1011 .rx_queue_intr_disable = mlx5_rx_intr_disable, 1012 .is_removed = mlx5_is_removed, 1013 }; 1014 1015 /** 1016 * Verify and store value for device argument. 1017 * 1018 * @param[in] key 1019 * Key argument to verify. 1020 * @param[in] val 1021 * Value associated with key. 1022 * @param opaque 1023 * User data. 1024 * 1025 * @return 1026 * 0 on success, a negative errno value otherwise and rte_errno is set. 1027 */ 1028 static int 1029 mlx5_args_check(const char *key, const char *val, void *opaque) 1030 { 1031 struct mlx5_dev_config *config = opaque; 1032 unsigned long tmp; 1033 1034 /* No-op, port representors are processed in mlx5_dev_spawn(). */ 1035 if (!strcmp(MLX5_REPRESENTOR, key)) 1036 return 0; 1037 errno = 0; 1038 tmp = strtoul(val, NULL, 0); 1039 if (errno) { 1040 rte_errno = errno; 1041 DRV_LOG(WARNING, "%s: \"%s\" is not a valid integer", key, val); 1042 return -rte_errno; 1043 } 1044 if (strcmp(MLX5_RXQ_CQE_COMP_EN, key) == 0) { 1045 config->cqe_comp = !!tmp; 1046 } else if (strcmp(MLX5_RXQ_CQE_PAD_EN, key) == 0) { 1047 config->cqe_pad = !!tmp; 1048 } else if (strcmp(MLX5_RXQ_PKT_PAD_EN, key) == 0) { 1049 config->hw_padding = !!tmp; 1050 } else if (strcmp(MLX5_RX_MPRQ_EN, key) == 0) { 1051 config->mprq.enabled = !!tmp; 1052 } else if (strcmp(MLX5_RX_MPRQ_LOG_STRIDE_NUM, key) == 0) { 1053 config->mprq.stride_num_n = tmp; 1054 } else if (strcmp(MLX5_RX_MPRQ_MAX_MEMCPY_LEN, key) == 0) { 1055 config->mprq.max_memcpy_len = tmp; 1056 } else if (strcmp(MLX5_RXQS_MIN_MPRQ, key) == 0) { 1057 config->mprq.min_rxqs_num = tmp; 1058 } else if (strcmp(MLX5_TXQ_INLINE, key) == 0) { 1059 DRV_LOG(WARNING, "%s: deprecated parameter," 1060 " converted to txq_inline_max", key); 1061 config->txq_inline_max = tmp; 1062 } else if (strcmp(MLX5_TXQ_INLINE_MAX, key) == 0) { 1063 config->txq_inline_max = tmp; 1064 } else if (strcmp(MLX5_TXQ_INLINE_MIN, key) == 0) { 1065 config->txq_inline_min = tmp; 1066 } else if (strcmp(MLX5_TXQ_INLINE_MPW, key) == 0) { 1067 config->txq_inline_mpw = tmp; 1068 } else if (strcmp(MLX5_TXQS_MIN_INLINE, key) == 0) { 1069 config->txqs_inline = tmp; 1070 } else if (strcmp(MLX5_TXQS_MAX_VEC, key) == 0) { 1071 DRV_LOG(WARNING, "%s: deprecated parameter, ignored", key); 1072 } else if (strcmp(MLX5_TXQ_MPW_EN, key) == 0) { 1073 config->mps = !!tmp; 1074 } else if (strcmp(MLX5_TXQ_MPW_HDR_DSEG_EN, key) == 0) { 1075 DRV_LOG(WARNING, "%s: deprecated parameter, ignored", key); 1076 } else if (strcmp(MLX5_TXQ_MAX_INLINE_LEN, key) == 0) { 1077 DRV_LOG(WARNING, "%s: deprecated parameter," 1078 " converted to txq_inline_mpw", key); 1079 config->txq_inline_mpw = tmp; 1080 } else if (strcmp(MLX5_TX_VEC_EN, key) == 0) { 1081 DRV_LOG(WARNING, "%s: deprecated parameter, ignored", key); 1082 } else if (strcmp(MLX5_RX_VEC_EN, key) == 0) { 1083 config->rx_vec_en = !!tmp; 1084 } else if (strcmp(MLX5_L3_VXLAN_EN, key) == 0) { 1085 config->l3_vxlan_en = !!tmp; 1086 } else if (strcmp(MLX5_VF_NL_EN, key) == 0) { 1087 config->vf_nl_en = !!tmp; 1088 } else if (strcmp(MLX5_DV_ESW_EN, key) == 0) { 1089 config->dv_esw_en = !!tmp; 1090 } else if (strcmp(MLX5_DV_FLOW_EN, key) == 0) { 1091 config->dv_flow_en = !!tmp; 1092 } else if (strcmp(MLX5_MR_EXT_MEMSEG_EN, key) == 0) { 1093 config->mr_ext_memseg_en = !!tmp; 1094 } else if (strcmp(MLX5_MAX_DUMP_FILES_NUM, key) == 0) { 1095 config->max_dump_files_num = tmp; 1096 } else if (strcmp(MLX5_LRO_TIMEOUT_USEC, key) == 0) { 1097 config->lro.timeout = tmp; 1098 } else { 1099 DRV_LOG(WARNING, "%s: unknown parameter", key); 1100 rte_errno = EINVAL; 1101 return -rte_errno; 1102 } 1103 return 0; 1104 } 1105 1106 /** 1107 * Parse device parameters. 1108 * 1109 * @param config 1110 * Pointer to device configuration structure. 1111 * @param devargs 1112 * Device arguments structure. 1113 * 1114 * @return 1115 * 0 on success, a negative errno value otherwise and rte_errno is set. 1116 */ 1117 static int 1118 mlx5_args(struct mlx5_dev_config *config, struct rte_devargs *devargs) 1119 { 1120 const char **params = (const char *[]){ 1121 MLX5_RXQ_CQE_COMP_EN, 1122 MLX5_RXQ_CQE_PAD_EN, 1123 MLX5_RXQ_PKT_PAD_EN, 1124 MLX5_RX_MPRQ_EN, 1125 MLX5_RX_MPRQ_LOG_STRIDE_NUM, 1126 MLX5_RX_MPRQ_MAX_MEMCPY_LEN, 1127 MLX5_RXQS_MIN_MPRQ, 1128 MLX5_TXQ_INLINE, 1129 MLX5_TXQ_INLINE_MIN, 1130 MLX5_TXQ_INLINE_MAX, 1131 MLX5_TXQ_INLINE_MPW, 1132 MLX5_TXQS_MIN_INLINE, 1133 MLX5_TXQS_MAX_VEC, 1134 MLX5_TXQ_MPW_EN, 1135 MLX5_TXQ_MPW_HDR_DSEG_EN, 1136 MLX5_TXQ_MAX_INLINE_LEN, 1137 MLX5_TX_VEC_EN, 1138 MLX5_RX_VEC_EN, 1139 MLX5_L3_VXLAN_EN, 1140 MLX5_VF_NL_EN, 1141 MLX5_DV_ESW_EN, 1142 MLX5_DV_FLOW_EN, 1143 MLX5_MR_EXT_MEMSEG_EN, 1144 MLX5_REPRESENTOR, 1145 MLX5_MAX_DUMP_FILES_NUM, 1146 MLX5_LRO_TIMEOUT_USEC, 1147 NULL, 1148 }; 1149 struct rte_kvargs *kvlist; 1150 int ret = 0; 1151 int i; 1152 1153 if (devargs == NULL) 1154 return 0; 1155 /* Following UGLY cast is done to pass checkpatch. */ 1156 kvlist = rte_kvargs_parse(devargs->args, params); 1157 if (kvlist == NULL) { 1158 rte_errno = EINVAL; 1159 return -rte_errno; 1160 } 1161 /* Process parameters. */ 1162 for (i = 0; (params[i] != NULL); ++i) { 1163 if (rte_kvargs_count(kvlist, params[i])) { 1164 ret = rte_kvargs_process(kvlist, params[i], 1165 mlx5_args_check, config); 1166 if (ret) { 1167 rte_errno = EINVAL; 1168 rte_kvargs_free(kvlist); 1169 return -rte_errno; 1170 } 1171 } 1172 } 1173 rte_kvargs_free(kvlist); 1174 return 0; 1175 } 1176 1177 static struct rte_pci_driver mlx5_driver; 1178 1179 /** 1180 * PMD global initialization. 1181 * 1182 * Independent from individual device, this function initializes global 1183 * per-PMD data structures distinguishing primary and secondary processes. 1184 * Hence, each initialization is called once per a process. 1185 * 1186 * @return 1187 * 0 on success, a negative errno value otherwise and rte_errno is set. 1188 */ 1189 static int 1190 mlx5_init_once(void) 1191 { 1192 struct mlx5_shared_data *sd; 1193 struct mlx5_local_data *ld = &mlx5_local_data; 1194 int ret = 0; 1195 1196 if (mlx5_init_shared_data()) 1197 return -rte_errno; 1198 sd = mlx5_shared_data; 1199 assert(sd); 1200 rte_spinlock_lock(&sd->lock); 1201 switch (rte_eal_process_type()) { 1202 case RTE_PROC_PRIMARY: 1203 if (sd->init_done) 1204 break; 1205 LIST_INIT(&sd->mem_event_cb_list); 1206 rte_rwlock_init(&sd->mem_event_rwlock); 1207 rte_mem_event_callback_register("MLX5_MEM_EVENT_CB", 1208 mlx5_mr_mem_event_cb, NULL); 1209 ret = mlx5_mp_init_primary(); 1210 if (ret) 1211 goto out; 1212 sd->init_done = true; 1213 break; 1214 case RTE_PROC_SECONDARY: 1215 if (ld->init_done) 1216 break; 1217 ret = mlx5_mp_init_secondary(); 1218 if (ret) 1219 goto out; 1220 ++sd->secondary_cnt; 1221 ld->init_done = true; 1222 break; 1223 default: 1224 break; 1225 } 1226 out: 1227 rte_spinlock_unlock(&sd->lock); 1228 return ret; 1229 } 1230 1231 /** 1232 * Configures the minimal amount of data to inline into WQE 1233 * while sending packets. 1234 * 1235 * - the txq_inline_min has the maximal priority, if this 1236 * key is specified in devargs 1237 * - if DevX is enabled the inline mode is queried from the 1238 * device (HCA attributes and NIC vport context if needed). 1239 * - otherwise L2 mode (18 bytes) is assumed for ConnectX-4/4LX 1240 * and none (0 bytes) for other NICs 1241 * 1242 * @param spawn 1243 * Verbs device parameters (name, port, switch_info) to spawn. 1244 * @param config 1245 * Device configuration parameters. 1246 */ 1247 static void 1248 mlx5_set_min_inline(struct mlx5_dev_spawn_data *spawn, 1249 struct mlx5_dev_config *config) 1250 { 1251 if (config->txq_inline_min != MLX5_ARG_UNSET) { 1252 /* Application defines size of inlined data explicitly. */ 1253 switch (spawn->pci_dev->id.device_id) { 1254 case PCI_DEVICE_ID_MELLANOX_CONNECTX4: 1255 case PCI_DEVICE_ID_MELLANOX_CONNECTX4VF: 1256 if (config->txq_inline_min < 1257 (int)MLX5_INLINE_HSIZE_L2) { 1258 DRV_LOG(DEBUG, 1259 "txq_inline_mix aligned to minimal" 1260 " ConnectX-4 required value %d", 1261 (int)MLX5_INLINE_HSIZE_L2); 1262 config->txq_inline_min = MLX5_INLINE_HSIZE_L2; 1263 } 1264 break; 1265 } 1266 goto exit; 1267 } 1268 if (config->hca_attr.eth_net_offloads) { 1269 /* We have DevX enabled, inline mode queried successfully. */ 1270 switch (config->hca_attr.wqe_inline_mode) { 1271 case MLX5_CAP_INLINE_MODE_L2: 1272 /* outer L2 header must be inlined. */ 1273 config->txq_inline_min = MLX5_INLINE_HSIZE_L2; 1274 goto exit; 1275 case MLX5_CAP_INLINE_MODE_NOT_REQUIRED: 1276 /* No inline data are required by NIC. */ 1277 config->txq_inline_min = MLX5_INLINE_HSIZE_NONE; 1278 config->hw_vlan_insert = 1279 config->hca_attr.wqe_vlan_insert; 1280 DRV_LOG(DEBUG, "Tx VLAN insertion is supported"); 1281 goto exit; 1282 case MLX5_CAP_INLINE_MODE_VPORT_CONTEXT: 1283 /* inline mode is defined by NIC vport context. */ 1284 if (!config->hca_attr.eth_virt) 1285 break; 1286 switch (config->hca_attr.vport_inline_mode) { 1287 case MLX5_INLINE_MODE_NONE: 1288 config->txq_inline_min = 1289 MLX5_INLINE_HSIZE_NONE; 1290 goto exit; 1291 case MLX5_INLINE_MODE_L2: 1292 config->txq_inline_min = 1293 MLX5_INLINE_HSIZE_L2; 1294 goto exit; 1295 case MLX5_INLINE_MODE_IP: 1296 config->txq_inline_min = 1297 MLX5_INLINE_HSIZE_L3; 1298 goto exit; 1299 case MLX5_INLINE_MODE_TCP_UDP: 1300 config->txq_inline_min = 1301 MLX5_INLINE_HSIZE_L4; 1302 goto exit; 1303 case MLX5_INLINE_MODE_INNER_L2: 1304 config->txq_inline_min = 1305 MLX5_INLINE_HSIZE_INNER_L2; 1306 goto exit; 1307 case MLX5_INLINE_MODE_INNER_IP: 1308 config->txq_inline_min = 1309 MLX5_INLINE_HSIZE_INNER_L3; 1310 goto exit; 1311 case MLX5_INLINE_MODE_INNER_TCP_UDP: 1312 config->txq_inline_min = 1313 MLX5_INLINE_HSIZE_INNER_L4; 1314 goto exit; 1315 } 1316 } 1317 } 1318 /* 1319 * We get here if we are unable to deduce 1320 * inline data size with DevX. Try PCI ID 1321 * to determine old NICs. 1322 */ 1323 switch (spawn->pci_dev->id.device_id) { 1324 case PCI_DEVICE_ID_MELLANOX_CONNECTX4: 1325 case PCI_DEVICE_ID_MELLANOX_CONNECTX4VF: 1326 config->txq_inline_min = MLX5_INLINE_HSIZE_L2; 1327 config->hw_vlan_insert = 0; 1328 break; 1329 case PCI_DEVICE_ID_MELLANOX_CONNECTX4LX: 1330 case PCI_DEVICE_ID_MELLANOX_CONNECTX4LXVF: 1331 config->txq_inline_min = MLX5_INLINE_HSIZE_NONE; 1332 config->hw_vlan_insert = 0; 1333 break; 1334 case PCI_DEVICE_ID_MELLANOX_CONNECTX5: 1335 case PCI_DEVICE_ID_MELLANOX_CONNECTX5VF: 1336 case PCI_DEVICE_ID_MELLANOX_CONNECTX5EX: 1337 case PCI_DEVICE_ID_MELLANOX_CONNECTX5EXVF: 1338 /* 1339 * These NICs support VLAN insertion from WQE and 1340 * report the wqe_vlan_insert flag. But there is the bug 1341 * and PFC control may be broken, so disable feature. 1342 */ 1343 config->hw_vlan_insert = 0; 1344 break; 1345 default: 1346 config->txq_inline_min = MLX5_INLINE_HSIZE_NONE; 1347 break; 1348 } 1349 exit: 1350 DRV_LOG(DEBUG, "min tx inline configured: %d", config->txq_inline_min); 1351 } 1352 1353 /** 1354 * Allocate page of door-bells and register it using DevX API. 1355 * 1356 * @param [in] dev 1357 * Pointer to Ethernet device. 1358 * 1359 * @return 1360 * Pointer to new page on success, NULL otherwise. 1361 */ 1362 static struct mlx5_devx_dbr_page * 1363 mlx5_alloc_dbr_page(struct rte_eth_dev *dev) 1364 { 1365 struct mlx5_priv *priv = dev->data->dev_private; 1366 struct mlx5_devx_dbr_page *page; 1367 1368 /* Allocate space for door-bell page and management data. */ 1369 page = rte_calloc_socket(__func__, 1, sizeof(struct mlx5_devx_dbr_page), 1370 RTE_CACHE_LINE_SIZE, dev->device->numa_node); 1371 if (!page) { 1372 DRV_LOG(ERR, "port %u cannot allocate dbr page", 1373 dev->data->port_id); 1374 return NULL; 1375 } 1376 /* Register allocated memory. */ 1377 page->umem = mlx5_glue->devx_umem_reg(priv->sh->ctx, page->dbrs, 1378 MLX5_DBR_PAGE_SIZE, 0); 1379 if (!page->umem) { 1380 DRV_LOG(ERR, "port %u cannot umem reg dbr page", 1381 dev->data->port_id); 1382 rte_free(page); 1383 return NULL; 1384 } 1385 return page; 1386 } 1387 1388 /** 1389 * Find the next available door-bell, allocate new page if needed. 1390 * 1391 * @param [in] dev 1392 * Pointer to Ethernet device. 1393 * @param [out] dbr_page 1394 * Door-bell page containing the page data. 1395 * 1396 * @return 1397 * Door-bell address offset on success, a negative error value otherwise. 1398 */ 1399 int64_t 1400 mlx5_get_dbr(struct rte_eth_dev *dev, struct mlx5_devx_dbr_page **dbr_page) 1401 { 1402 struct mlx5_priv *priv = dev->data->dev_private; 1403 struct mlx5_devx_dbr_page *page = NULL; 1404 uint32_t i, j; 1405 1406 LIST_FOREACH(page, &priv->dbrpgs, next) 1407 if (page->dbr_count < MLX5_DBR_PER_PAGE) 1408 break; 1409 if (!page) { /* No page with free door-bell exists. */ 1410 page = mlx5_alloc_dbr_page(dev); 1411 if (!page) /* Failed to allocate new page. */ 1412 return (-1); 1413 LIST_INSERT_HEAD(&priv->dbrpgs, page, next); 1414 } 1415 /* Loop to find bitmap part with clear bit. */ 1416 for (i = 0; 1417 i < MLX5_DBR_BITMAP_SIZE && page->dbr_bitmap[i] == UINT64_MAX; 1418 i++) 1419 ; /* Empty. */ 1420 /* Find the first clear bit. */ 1421 j = rte_bsf64(~page->dbr_bitmap[i]); 1422 assert(i < (MLX5_DBR_PER_PAGE / 64)); 1423 page->dbr_bitmap[i] |= (1 << j); 1424 page->dbr_count++; 1425 *dbr_page = page; 1426 return (((i * 64) + j) * sizeof(uint64_t)); 1427 } 1428 1429 /** 1430 * Release a door-bell record. 1431 * 1432 * @param [in] dev 1433 * Pointer to Ethernet device. 1434 * @param [in] umem_id 1435 * UMEM ID of page containing the door-bell record to release. 1436 * @param [in] offset 1437 * Offset of door-bell record in page. 1438 * 1439 * @return 1440 * 0 on success, a negative error value otherwise. 1441 */ 1442 int32_t 1443 mlx5_release_dbr(struct rte_eth_dev *dev, uint32_t umem_id, uint64_t offset) 1444 { 1445 struct mlx5_priv *priv = dev->data->dev_private; 1446 struct mlx5_devx_dbr_page *page = NULL; 1447 int ret = 0; 1448 1449 LIST_FOREACH(page, &priv->dbrpgs, next) 1450 /* Find the page this address belongs to. */ 1451 if (page->umem->umem_id == umem_id) 1452 break; 1453 if (!page) 1454 return -EINVAL; 1455 page->dbr_count--; 1456 if (!page->dbr_count) { 1457 /* Page not used, free it and remove from list. */ 1458 LIST_REMOVE(page, next); 1459 if (page->umem) 1460 ret = -mlx5_glue->devx_umem_dereg(page->umem); 1461 rte_free(page); 1462 } else { 1463 /* Mark in bitmap that this door-bell is not in use. */ 1464 offset /= MLX5_DBR_SIZE; 1465 int i = offset / 64; 1466 int j = offset % 64; 1467 1468 page->dbr_bitmap[i] &= ~(1 << j); 1469 } 1470 return ret; 1471 } 1472 1473 /** 1474 * Spawn an Ethernet device from Verbs information. 1475 * 1476 * @param dpdk_dev 1477 * Backing DPDK device. 1478 * @param spawn 1479 * Verbs device parameters (name, port, switch_info) to spawn. 1480 * @param config 1481 * Device configuration parameters. 1482 * 1483 * @return 1484 * A valid Ethernet device object on success, NULL otherwise and rte_errno 1485 * is set. The following errors are defined: 1486 * 1487 * EBUSY: device is not supposed to be spawned. 1488 * EEXIST: device is already spawned 1489 */ 1490 static struct rte_eth_dev * 1491 mlx5_dev_spawn(struct rte_device *dpdk_dev, 1492 struct mlx5_dev_spawn_data *spawn, 1493 struct mlx5_dev_config config) 1494 { 1495 const struct mlx5_switch_info *switch_info = &spawn->info; 1496 struct mlx5_ibv_shared *sh = NULL; 1497 struct ibv_port_attr port_attr; 1498 struct mlx5dv_context dv_attr = { .comp_mask = 0 }; 1499 struct rte_eth_dev *eth_dev = NULL; 1500 struct mlx5_priv *priv = NULL; 1501 int err = 0; 1502 unsigned int hw_padding = 0; 1503 unsigned int mps; 1504 unsigned int cqe_comp; 1505 unsigned int cqe_pad = 0; 1506 unsigned int tunnel_en = 0; 1507 unsigned int mpls_en = 0; 1508 unsigned int swp = 0; 1509 unsigned int mprq = 0; 1510 unsigned int mprq_min_stride_size_n = 0; 1511 unsigned int mprq_max_stride_size_n = 0; 1512 unsigned int mprq_min_stride_num_n = 0; 1513 unsigned int mprq_max_stride_num_n = 0; 1514 struct rte_ether_addr mac; 1515 char name[RTE_ETH_NAME_MAX_LEN]; 1516 int own_domain_id = 0; 1517 uint16_t port_id; 1518 unsigned int i; 1519 1520 /* Determine if this port representor is supposed to be spawned. */ 1521 if (switch_info->representor && dpdk_dev->devargs) { 1522 struct rte_eth_devargs eth_da; 1523 1524 err = rte_eth_devargs_parse(dpdk_dev->devargs->args, ð_da); 1525 if (err) { 1526 rte_errno = -err; 1527 DRV_LOG(ERR, "failed to process device arguments: %s", 1528 strerror(rte_errno)); 1529 return NULL; 1530 } 1531 for (i = 0; i < eth_da.nb_representor_ports; ++i) 1532 if (eth_da.representor_ports[i] == 1533 (uint16_t)switch_info->port_name) 1534 break; 1535 if (i == eth_da.nb_representor_ports) { 1536 rte_errno = EBUSY; 1537 return NULL; 1538 } 1539 } 1540 /* Build device name. */ 1541 if (!switch_info->representor) 1542 strlcpy(name, dpdk_dev->name, sizeof(name)); 1543 else 1544 snprintf(name, sizeof(name), "%s_representor_%u", 1545 dpdk_dev->name, switch_info->port_name); 1546 /* check if the device is already spawned */ 1547 if (rte_eth_dev_get_port_by_name(name, &port_id) == 0) { 1548 rte_errno = EEXIST; 1549 return NULL; 1550 } 1551 DRV_LOG(DEBUG, "naming Ethernet device \"%s\"", name); 1552 if (rte_eal_process_type() == RTE_PROC_SECONDARY) { 1553 eth_dev = rte_eth_dev_attach_secondary(name); 1554 if (eth_dev == NULL) { 1555 DRV_LOG(ERR, "can not attach rte ethdev"); 1556 rte_errno = ENOMEM; 1557 return NULL; 1558 } 1559 eth_dev->device = dpdk_dev; 1560 eth_dev->dev_ops = &mlx5_dev_sec_ops; 1561 err = mlx5_proc_priv_init(eth_dev); 1562 if (err) 1563 return NULL; 1564 /* Receive command fd from primary process */ 1565 err = mlx5_mp_req_verbs_cmd_fd(eth_dev); 1566 if (err < 0) 1567 return NULL; 1568 /* Remap UAR for Tx queues. */ 1569 err = mlx5_tx_uar_init_secondary(eth_dev, err); 1570 if (err) 1571 return NULL; 1572 /* 1573 * Ethdev pointer is still required as input since 1574 * the primary device is not accessible from the 1575 * secondary process. 1576 */ 1577 eth_dev->rx_pkt_burst = mlx5_select_rx_function(eth_dev); 1578 eth_dev->tx_pkt_burst = mlx5_select_tx_function(eth_dev); 1579 return eth_dev; 1580 } 1581 sh = mlx5_alloc_shared_ibctx(spawn); 1582 if (!sh) 1583 return NULL; 1584 config.devx = sh->devx; 1585 #ifdef HAVE_MLX5DV_DR_ACTION_DEST_DEVX_TIR 1586 config.dest_tir = 1; 1587 #endif 1588 #ifdef HAVE_IBV_MLX5_MOD_SWP 1589 dv_attr.comp_mask |= MLX5DV_CONTEXT_MASK_SWP; 1590 #endif 1591 /* 1592 * Multi-packet send is supported by ConnectX-4 Lx PF as well 1593 * as all ConnectX-5 devices. 1594 */ 1595 #ifdef HAVE_IBV_DEVICE_TUNNEL_SUPPORT 1596 dv_attr.comp_mask |= MLX5DV_CONTEXT_MASK_TUNNEL_OFFLOADS; 1597 #endif 1598 #ifdef HAVE_IBV_DEVICE_STRIDING_RQ_SUPPORT 1599 dv_attr.comp_mask |= MLX5DV_CONTEXT_MASK_STRIDING_RQ; 1600 #endif 1601 mlx5_glue->dv_query_device(sh->ctx, &dv_attr); 1602 if (dv_attr.flags & MLX5DV_CONTEXT_FLAGS_MPW_ALLOWED) { 1603 if (dv_attr.flags & MLX5DV_CONTEXT_FLAGS_ENHANCED_MPW) { 1604 DRV_LOG(DEBUG, "enhanced MPW is supported"); 1605 mps = MLX5_MPW_ENHANCED; 1606 } else { 1607 DRV_LOG(DEBUG, "MPW is supported"); 1608 mps = MLX5_MPW; 1609 } 1610 } else { 1611 DRV_LOG(DEBUG, "MPW isn't supported"); 1612 mps = MLX5_MPW_DISABLED; 1613 } 1614 #ifdef HAVE_IBV_MLX5_MOD_SWP 1615 if (dv_attr.comp_mask & MLX5DV_CONTEXT_MASK_SWP) 1616 swp = dv_attr.sw_parsing_caps.sw_parsing_offloads; 1617 DRV_LOG(DEBUG, "SWP support: %u", swp); 1618 #endif 1619 config.swp = !!swp; 1620 #ifdef HAVE_IBV_DEVICE_STRIDING_RQ_SUPPORT 1621 if (dv_attr.comp_mask & MLX5DV_CONTEXT_MASK_STRIDING_RQ) { 1622 struct mlx5dv_striding_rq_caps mprq_caps = 1623 dv_attr.striding_rq_caps; 1624 1625 DRV_LOG(DEBUG, "\tmin_single_stride_log_num_of_bytes: %d", 1626 mprq_caps.min_single_stride_log_num_of_bytes); 1627 DRV_LOG(DEBUG, "\tmax_single_stride_log_num_of_bytes: %d", 1628 mprq_caps.max_single_stride_log_num_of_bytes); 1629 DRV_LOG(DEBUG, "\tmin_single_wqe_log_num_of_strides: %d", 1630 mprq_caps.min_single_wqe_log_num_of_strides); 1631 DRV_LOG(DEBUG, "\tmax_single_wqe_log_num_of_strides: %d", 1632 mprq_caps.max_single_wqe_log_num_of_strides); 1633 DRV_LOG(DEBUG, "\tsupported_qpts: %d", 1634 mprq_caps.supported_qpts); 1635 DRV_LOG(DEBUG, "device supports Multi-Packet RQ"); 1636 mprq = 1; 1637 mprq_min_stride_size_n = 1638 mprq_caps.min_single_stride_log_num_of_bytes; 1639 mprq_max_stride_size_n = 1640 mprq_caps.max_single_stride_log_num_of_bytes; 1641 mprq_min_stride_num_n = 1642 mprq_caps.min_single_wqe_log_num_of_strides; 1643 mprq_max_stride_num_n = 1644 mprq_caps.max_single_wqe_log_num_of_strides; 1645 config.mprq.stride_num_n = RTE_MAX(MLX5_MPRQ_STRIDE_NUM_N, 1646 mprq_min_stride_num_n); 1647 } 1648 #endif 1649 if (RTE_CACHE_LINE_SIZE == 128 && 1650 !(dv_attr.flags & MLX5DV_CONTEXT_FLAGS_CQE_128B_COMP)) 1651 cqe_comp = 0; 1652 else 1653 cqe_comp = 1; 1654 config.cqe_comp = cqe_comp; 1655 #ifdef HAVE_IBV_MLX5_MOD_CQE_128B_PAD 1656 /* Whether device supports 128B Rx CQE padding. */ 1657 cqe_pad = RTE_CACHE_LINE_SIZE == 128 && 1658 (dv_attr.flags & MLX5DV_CONTEXT_FLAGS_CQE_128B_PAD); 1659 #endif 1660 #ifdef HAVE_IBV_DEVICE_TUNNEL_SUPPORT 1661 if (dv_attr.comp_mask & MLX5DV_CONTEXT_MASK_TUNNEL_OFFLOADS) { 1662 tunnel_en = ((dv_attr.tunnel_offloads_caps & 1663 MLX5DV_RAW_PACKET_CAP_TUNNELED_OFFLOAD_VXLAN) && 1664 (dv_attr.tunnel_offloads_caps & 1665 MLX5DV_RAW_PACKET_CAP_TUNNELED_OFFLOAD_GRE)); 1666 } 1667 DRV_LOG(DEBUG, "tunnel offloading is %ssupported", 1668 tunnel_en ? "" : "not "); 1669 #else 1670 DRV_LOG(WARNING, 1671 "tunnel offloading disabled due to old OFED/rdma-core version"); 1672 #endif 1673 config.tunnel_en = tunnel_en; 1674 #ifdef HAVE_IBV_DEVICE_MPLS_SUPPORT 1675 mpls_en = ((dv_attr.tunnel_offloads_caps & 1676 MLX5DV_RAW_PACKET_CAP_TUNNELED_OFFLOAD_CW_MPLS_OVER_GRE) && 1677 (dv_attr.tunnel_offloads_caps & 1678 MLX5DV_RAW_PACKET_CAP_TUNNELED_OFFLOAD_CW_MPLS_OVER_UDP)); 1679 DRV_LOG(DEBUG, "MPLS over GRE/UDP tunnel offloading is %ssupported", 1680 mpls_en ? "" : "not "); 1681 #else 1682 DRV_LOG(WARNING, "MPLS over GRE/UDP tunnel offloading disabled due to" 1683 " old OFED/rdma-core version or firmware configuration"); 1684 #endif 1685 config.mpls_en = mpls_en; 1686 /* Check port status. */ 1687 err = mlx5_glue->query_port(sh->ctx, spawn->ibv_port, &port_attr); 1688 if (err) { 1689 DRV_LOG(ERR, "port query failed: %s", strerror(err)); 1690 goto error; 1691 } 1692 if (port_attr.link_layer != IBV_LINK_LAYER_ETHERNET) { 1693 DRV_LOG(ERR, "port is not configured in Ethernet mode"); 1694 err = EINVAL; 1695 goto error; 1696 } 1697 if (port_attr.state != IBV_PORT_ACTIVE) 1698 DRV_LOG(DEBUG, "port is not active: \"%s\" (%d)", 1699 mlx5_glue->port_state_str(port_attr.state), 1700 port_attr.state); 1701 /* Allocate private eth device data. */ 1702 priv = rte_zmalloc("ethdev private structure", 1703 sizeof(*priv), 1704 RTE_CACHE_LINE_SIZE); 1705 if (priv == NULL) { 1706 DRV_LOG(ERR, "priv allocation failure"); 1707 err = ENOMEM; 1708 goto error; 1709 } 1710 priv->sh = sh; 1711 priv->ibv_port = spawn->ibv_port; 1712 priv->mtu = RTE_ETHER_MTU; 1713 #ifndef RTE_ARCH_64 1714 /* Initialize UAR access locks for 32bit implementations. */ 1715 rte_spinlock_init(&priv->uar_lock_cq); 1716 for (i = 0; i < MLX5_UAR_PAGE_NUM_MAX; i++) 1717 rte_spinlock_init(&priv->uar_lock[i]); 1718 #endif 1719 /* Some internal functions rely on Netlink sockets, open them now. */ 1720 priv->nl_socket_rdma = mlx5_nl_init(NETLINK_RDMA); 1721 priv->nl_socket_route = mlx5_nl_init(NETLINK_ROUTE); 1722 priv->nl_sn = 0; 1723 priv->representor = !!switch_info->representor; 1724 priv->master = !!switch_info->master; 1725 priv->domain_id = RTE_ETH_DEV_SWITCH_DOMAIN_ID_INVALID; 1726 /* 1727 * Currently we support single E-Switch per PF configurations 1728 * only and vport_id field contains the vport index for 1729 * associated VF, which is deduced from representor port name. 1730 * For example, let's have the IB device port 10, it has 1731 * attached network device eth0, which has port name attribute 1732 * pf0vf2, we can deduce the VF number as 2, and set vport index 1733 * as 3 (2+1). This assigning schema should be changed if the 1734 * multiple E-Switch instances per PF configurations or/and PCI 1735 * subfunctions are added. 1736 */ 1737 priv->vport_id = switch_info->representor ? 1738 switch_info->port_name + 1 : -1; 1739 /* representor_id field keeps the unmodified port/VF index. */ 1740 priv->representor_id = switch_info->representor ? 1741 switch_info->port_name : -1; 1742 /* 1743 * Look for sibling devices in order to reuse their switch domain 1744 * if any, otherwise allocate one. 1745 */ 1746 RTE_ETH_FOREACH_DEV_OF(port_id, dpdk_dev) { 1747 const struct mlx5_priv *opriv = 1748 rte_eth_devices[port_id].data->dev_private; 1749 1750 if (!opriv || 1751 opriv->domain_id == 1752 RTE_ETH_DEV_SWITCH_DOMAIN_ID_INVALID) 1753 continue; 1754 priv->domain_id = opriv->domain_id; 1755 break; 1756 } 1757 if (priv->domain_id == RTE_ETH_DEV_SWITCH_DOMAIN_ID_INVALID) { 1758 err = rte_eth_switch_domain_alloc(&priv->domain_id); 1759 if (err) { 1760 err = rte_errno; 1761 DRV_LOG(ERR, "unable to allocate switch domain: %s", 1762 strerror(rte_errno)); 1763 goto error; 1764 } 1765 own_domain_id = 1; 1766 } 1767 err = mlx5_args(&config, dpdk_dev->devargs); 1768 if (err) { 1769 err = rte_errno; 1770 DRV_LOG(ERR, "failed to process device arguments: %s", 1771 strerror(rte_errno)); 1772 goto error; 1773 } 1774 config.hw_csum = !!(sh->device_attr.device_cap_flags_ex & 1775 IBV_DEVICE_RAW_IP_CSUM); 1776 DRV_LOG(DEBUG, "checksum offloading is %ssupported", 1777 (config.hw_csum ? "" : "not ")); 1778 #if !defined(HAVE_IBV_DEVICE_COUNTERS_SET_V42) && \ 1779 !defined(HAVE_IBV_DEVICE_COUNTERS_SET_V45) 1780 DRV_LOG(DEBUG, "counters are not supported"); 1781 #endif 1782 #ifndef HAVE_IBV_FLOW_DV_SUPPORT 1783 if (config.dv_flow_en) { 1784 DRV_LOG(WARNING, "DV flow is not supported"); 1785 config.dv_flow_en = 0; 1786 } 1787 #endif 1788 config.ind_table_max_size = 1789 sh->device_attr.rss_caps.max_rwq_indirection_table_size; 1790 /* 1791 * Remove this check once DPDK supports larger/variable 1792 * indirection tables. 1793 */ 1794 if (config.ind_table_max_size > (unsigned int)ETH_RSS_RETA_SIZE_512) 1795 config.ind_table_max_size = ETH_RSS_RETA_SIZE_512; 1796 DRV_LOG(DEBUG, "maximum Rx indirection table size is %u", 1797 config.ind_table_max_size); 1798 config.hw_vlan_strip = !!(sh->device_attr.raw_packet_caps & 1799 IBV_RAW_PACKET_CAP_CVLAN_STRIPPING); 1800 DRV_LOG(DEBUG, "VLAN stripping is %ssupported", 1801 (config.hw_vlan_strip ? "" : "not ")); 1802 config.hw_fcs_strip = !!(sh->device_attr.raw_packet_caps & 1803 IBV_RAW_PACKET_CAP_SCATTER_FCS); 1804 DRV_LOG(DEBUG, "FCS stripping configuration is %ssupported", 1805 (config.hw_fcs_strip ? "" : "not ")); 1806 #if defined(HAVE_IBV_WQ_FLAG_RX_END_PADDING) 1807 hw_padding = !!sh->device_attr.rx_pad_end_addr_align; 1808 #elif defined(HAVE_IBV_WQ_FLAGS_PCI_WRITE_END_PADDING) 1809 hw_padding = !!(sh->device_attr.device_cap_flags_ex & 1810 IBV_DEVICE_PCI_WRITE_END_PADDING); 1811 #endif 1812 if (config.hw_padding && !hw_padding) { 1813 DRV_LOG(DEBUG, "Rx end alignment padding isn't supported"); 1814 config.hw_padding = 0; 1815 } else if (config.hw_padding) { 1816 DRV_LOG(DEBUG, "Rx end alignment padding is enabled"); 1817 } 1818 config.tso = (sh->device_attr.tso_caps.max_tso > 0 && 1819 (sh->device_attr.tso_caps.supported_qpts & 1820 (1 << IBV_QPT_RAW_PACKET))); 1821 if (config.tso) 1822 config.tso_max_payload_sz = sh->device_attr.tso_caps.max_tso; 1823 /* 1824 * MPW is disabled by default, while the Enhanced MPW is enabled 1825 * by default. 1826 */ 1827 if (config.mps == MLX5_ARG_UNSET) 1828 config.mps = (mps == MLX5_MPW_ENHANCED) ? MLX5_MPW_ENHANCED : 1829 MLX5_MPW_DISABLED; 1830 else 1831 config.mps = config.mps ? mps : MLX5_MPW_DISABLED; 1832 DRV_LOG(INFO, "%sMPS is %s", 1833 config.mps == MLX5_MPW_ENHANCED ? "enhanced " : "", 1834 config.mps != MLX5_MPW_DISABLED ? "enabled" : "disabled"); 1835 if (config.cqe_comp && !cqe_comp) { 1836 DRV_LOG(WARNING, "Rx CQE compression isn't supported"); 1837 config.cqe_comp = 0; 1838 } 1839 if (config.cqe_pad && !cqe_pad) { 1840 DRV_LOG(WARNING, "Rx CQE padding isn't supported"); 1841 config.cqe_pad = 0; 1842 } else if (config.cqe_pad) { 1843 DRV_LOG(INFO, "Rx CQE padding is enabled"); 1844 } 1845 if (config.devx) { 1846 priv->counter_fallback = 0; 1847 err = mlx5_devx_cmd_query_hca_attr(sh->ctx, &config.hca_attr); 1848 if (err) { 1849 err = -err; 1850 goto error; 1851 } 1852 if (!config.hca_attr.flow_counters_dump) 1853 priv->counter_fallback = 1; 1854 #ifndef HAVE_IBV_DEVX_ASYNC 1855 priv->counter_fallback = 1; 1856 #endif 1857 if (priv->counter_fallback) 1858 DRV_LOG(INFO, "Use fall-back DV counter management\n"); 1859 /* Check for LRO support. */ 1860 if (config.dest_tir && config.hca_attr.lro_cap) { 1861 /* TBD check tunnel lro caps. */ 1862 config.lro.supported = config.hca_attr.lro_cap; 1863 DRV_LOG(DEBUG, "Device supports LRO"); 1864 /* 1865 * If LRO timeout is not configured by application, 1866 * use the minimal supported value. 1867 */ 1868 if (!config.lro.timeout) 1869 config.lro.timeout = 1870 config.hca_attr.lro_timer_supported_periods[0]; 1871 DRV_LOG(DEBUG, "LRO session timeout set to %d usec", 1872 config.lro.timeout); 1873 } 1874 } 1875 if (config.mprq.enabled && mprq) { 1876 if (config.mprq.stride_num_n > mprq_max_stride_num_n || 1877 config.mprq.stride_num_n < mprq_min_stride_num_n) { 1878 config.mprq.stride_num_n = 1879 RTE_MAX(MLX5_MPRQ_STRIDE_NUM_N, 1880 mprq_min_stride_num_n); 1881 DRV_LOG(WARNING, 1882 "the number of strides" 1883 " for Multi-Packet RQ is out of range," 1884 " setting default value (%u)", 1885 1 << config.mprq.stride_num_n); 1886 } 1887 config.mprq.min_stride_size_n = mprq_min_stride_size_n; 1888 config.mprq.max_stride_size_n = mprq_max_stride_size_n; 1889 } else if (config.mprq.enabled && !mprq) { 1890 DRV_LOG(WARNING, "Multi-Packet RQ isn't supported"); 1891 config.mprq.enabled = 0; 1892 } 1893 if (config.max_dump_files_num == 0) 1894 config.max_dump_files_num = 128; 1895 eth_dev = rte_eth_dev_allocate(name); 1896 if (eth_dev == NULL) { 1897 DRV_LOG(ERR, "can not allocate rte ethdev"); 1898 err = ENOMEM; 1899 goto error; 1900 } 1901 /* Flag to call rte_eth_dev_release_port() in rte_eth_dev_close(). */ 1902 eth_dev->data->dev_flags |= RTE_ETH_DEV_CLOSE_REMOVE; 1903 if (priv->representor) { 1904 eth_dev->data->dev_flags |= RTE_ETH_DEV_REPRESENTOR; 1905 eth_dev->data->representor_id = priv->representor_id; 1906 } 1907 /* 1908 * Store associated network device interface index. This index 1909 * is permanent throughout the lifetime of device. So, we may store 1910 * the ifindex here and use the cached value further. 1911 */ 1912 assert(spawn->ifindex); 1913 priv->if_index = spawn->ifindex; 1914 eth_dev->data->dev_private = priv; 1915 priv->dev_data = eth_dev->data; 1916 eth_dev->data->mac_addrs = priv->mac; 1917 eth_dev->device = dpdk_dev; 1918 /* Configure the first MAC address by default. */ 1919 if (mlx5_get_mac(eth_dev, &mac.addr_bytes)) { 1920 DRV_LOG(ERR, 1921 "port %u cannot get MAC address, is mlx5_en" 1922 " loaded? (errno: %s)", 1923 eth_dev->data->port_id, strerror(rte_errno)); 1924 err = ENODEV; 1925 goto error; 1926 } 1927 DRV_LOG(INFO, 1928 "port %u MAC address is %02x:%02x:%02x:%02x:%02x:%02x", 1929 eth_dev->data->port_id, 1930 mac.addr_bytes[0], mac.addr_bytes[1], 1931 mac.addr_bytes[2], mac.addr_bytes[3], 1932 mac.addr_bytes[4], mac.addr_bytes[5]); 1933 #ifndef NDEBUG 1934 { 1935 char ifname[IF_NAMESIZE]; 1936 1937 if (mlx5_get_ifname(eth_dev, &ifname) == 0) 1938 DRV_LOG(DEBUG, "port %u ifname is \"%s\"", 1939 eth_dev->data->port_id, ifname); 1940 else 1941 DRV_LOG(DEBUG, "port %u ifname is unknown", 1942 eth_dev->data->port_id); 1943 } 1944 #endif 1945 /* Get actual MTU if possible. */ 1946 err = mlx5_get_mtu(eth_dev, &priv->mtu); 1947 if (err) { 1948 err = rte_errno; 1949 goto error; 1950 } 1951 DRV_LOG(DEBUG, "port %u MTU is %u", eth_dev->data->port_id, 1952 priv->mtu); 1953 /* Initialize burst functions to prevent crashes before link-up. */ 1954 eth_dev->rx_pkt_burst = removed_rx_burst; 1955 eth_dev->tx_pkt_burst = removed_tx_burst; 1956 eth_dev->dev_ops = &mlx5_dev_ops; 1957 /* Register MAC address. */ 1958 claim_zero(mlx5_mac_addr_add(eth_dev, &mac, 0, 0)); 1959 if (config.vf && config.vf_nl_en) 1960 mlx5_nl_mac_addr_sync(eth_dev); 1961 TAILQ_INIT(&priv->flows); 1962 TAILQ_INIT(&priv->ctrl_flows); 1963 /* Hint libmlx5 to use PMD allocator for data plane resources */ 1964 struct mlx5dv_ctx_allocators alctr = { 1965 .alloc = &mlx5_alloc_verbs_buf, 1966 .free = &mlx5_free_verbs_buf, 1967 .data = priv, 1968 }; 1969 mlx5_glue->dv_set_context_attr(sh->ctx, 1970 MLX5DV_CTX_ATTR_BUF_ALLOCATORS, 1971 (void *)((uintptr_t)&alctr)); 1972 /* Bring Ethernet device up. */ 1973 DRV_LOG(DEBUG, "port %u forcing Ethernet interface up", 1974 eth_dev->data->port_id); 1975 mlx5_set_link_up(eth_dev); 1976 /* 1977 * Even though the interrupt handler is not installed yet, 1978 * interrupts will still trigger on the async_fd from 1979 * Verbs context returned by ibv_open_device(). 1980 */ 1981 mlx5_link_update(eth_dev, 0); 1982 #ifdef HAVE_MLX5DV_DR_ESWITCH 1983 if (!(config.hca_attr.eswitch_manager && config.dv_flow_en && 1984 (switch_info->representor || switch_info->master))) 1985 config.dv_esw_en = 0; 1986 #else 1987 config.dv_esw_en = 0; 1988 #endif 1989 /* Detect minimal data bytes to inline. */ 1990 mlx5_set_min_inline(spawn, &config); 1991 /* Store device configuration on private structure. */ 1992 priv->config = config; 1993 if (config.dv_flow_en) { 1994 err = mlx5_alloc_shared_dr(priv); 1995 if (err) 1996 goto error; 1997 } 1998 /* Supported Verbs flow priority number detection. */ 1999 err = mlx5_flow_discover_priorities(eth_dev); 2000 if (err < 0) { 2001 err = -err; 2002 goto error; 2003 } 2004 priv->config.flow_prio = err; 2005 /* Add device to memory callback list. */ 2006 rte_rwlock_write_lock(&mlx5_shared_data->mem_event_rwlock); 2007 LIST_INSERT_HEAD(&mlx5_shared_data->mem_event_cb_list, 2008 sh, mem_event_cb); 2009 rte_rwlock_write_unlock(&mlx5_shared_data->mem_event_rwlock); 2010 return eth_dev; 2011 error: 2012 if (priv) { 2013 if (priv->sh) 2014 mlx5_free_shared_dr(priv); 2015 if (priv->nl_socket_route >= 0) 2016 close(priv->nl_socket_route); 2017 if (priv->nl_socket_rdma >= 0) 2018 close(priv->nl_socket_rdma); 2019 if (own_domain_id) 2020 claim_zero(rte_eth_switch_domain_free(priv->domain_id)); 2021 rte_free(priv); 2022 if (eth_dev != NULL) 2023 eth_dev->data->dev_private = NULL; 2024 } 2025 if (eth_dev != NULL) { 2026 /* mac_addrs must not be freed alone because part of dev_private */ 2027 eth_dev->data->mac_addrs = NULL; 2028 rte_eth_dev_release_port(eth_dev); 2029 } 2030 if (sh) 2031 mlx5_free_shared_ibctx(sh); 2032 assert(err > 0); 2033 rte_errno = err; 2034 return NULL; 2035 } 2036 2037 /** 2038 * Comparison callback to sort device data. 2039 * 2040 * This is meant to be used with qsort(). 2041 * 2042 * @param a[in] 2043 * Pointer to pointer to first data object. 2044 * @param b[in] 2045 * Pointer to pointer to second data object. 2046 * 2047 * @return 2048 * 0 if both objects are equal, less than 0 if the first argument is less 2049 * than the second, greater than 0 otherwise. 2050 */ 2051 static int 2052 mlx5_dev_spawn_data_cmp(const void *a, const void *b) 2053 { 2054 const struct mlx5_switch_info *si_a = 2055 &((const struct mlx5_dev_spawn_data *)a)->info; 2056 const struct mlx5_switch_info *si_b = 2057 &((const struct mlx5_dev_spawn_data *)b)->info; 2058 int ret; 2059 2060 /* Master device first. */ 2061 ret = si_b->master - si_a->master; 2062 if (ret) 2063 return ret; 2064 /* Then representor devices. */ 2065 ret = si_b->representor - si_a->representor; 2066 if (ret) 2067 return ret; 2068 /* Unidentified devices come last in no specific order. */ 2069 if (!si_a->representor) 2070 return 0; 2071 /* Order representors by name. */ 2072 return si_a->port_name - si_b->port_name; 2073 } 2074 2075 /** 2076 * DPDK callback to register a PCI device. 2077 * 2078 * This function spawns Ethernet devices out of a given PCI device. 2079 * 2080 * @param[in] pci_drv 2081 * PCI driver structure (mlx5_driver). 2082 * @param[in] pci_dev 2083 * PCI device information. 2084 * 2085 * @return 2086 * 0 on success, a negative errno value otherwise and rte_errno is set. 2087 */ 2088 static int 2089 mlx5_pci_probe(struct rte_pci_driver *pci_drv __rte_unused, 2090 struct rte_pci_device *pci_dev) 2091 { 2092 struct ibv_device **ibv_list; 2093 /* 2094 * Number of found IB Devices matching with requested PCI BDF. 2095 * nd != 1 means there are multiple IB devices over the same 2096 * PCI device and we have representors and master. 2097 */ 2098 unsigned int nd = 0; 2099 /* 2100 * Number of found IB device Ports. nd = 1 and np = 1..n means 2101 * we have the single multiport IB device, and there may be 2102 * representors attached to some of found ports. 2103 */ 2104 unsigned int np = 0; 2105 /* 2106 * Number of DPDK ethernet devices to Spawn - either over 2107 * multiple IB devices or multiple ports of single IB device. 2108 * Actually this is the number of iterations to spawn. 2109 */ 2110 unsigned int ns = 0; 2111 struct mlx5_dev_config dev_config; 2112 int ret; 2113 2114 ret = mlx5_init_once(); 2115 if (ret) { 2116 DRV_LOG(ERR, "unable to init PMD global data: %s", 2117 strerror(rte_errno)); 2118 return -rte_errno; 2119 } 2120 assert(pci_drv == &mlx5_driver); 2121 errno = 0; 2122 ibv_list = mlx5_glue->get_device_list(&ret); 2123 if (!ibv_list) { 2124 rte_errno = errno ? errno : ENOSYS; 2125 DRV_LOG(ERR, "cannot list devices, is ib_uverbs loaded?"); 2126 return -rte_errno; 2127 } 2128 /* 2129 * First scan the list of all Infiniband devices to find 2130 * matching ones, gathering into the list. 2131 */ 2132 struct ibv_device *ibv_match[ret + 1]; 2133 int nl_route = -1; 2134 int nl_rdma = -1; 2135 unsigned int i; 2136 2137 while (ret-- > 0) { 2138 struct rte_pci_addr pci_addr; 2139 2140 DRV_LOG(DEBUG, "checking device \"%s\"", ibv_list[ret]->name); 2141 if (mlx5_ibv_device_to_pci_addr(ibv_list[ret], &pci_addr)) 2142 continue; 2143 if (pci_dev->addr.domain != pci_addr.domain || 2144 pci_dev->addr.bus != pci_addr.bus || 2145 pci_dev->addr.devid != pci_addr.devid || 2146 pci_dev->addr.function != pci_addr.function) 2147 continue; 2148 DRV_LOG(INFO, "PCI information matches for device \"%s\"", 2149 ibv_list[ret]->name); 2150 ibv_match[nd++] = ibv_list[ret]; 2151 } 2152 ibv_match[nd] = NULL; 2153 if (!nd) { 2154 /* No device matches, just complain and bail out. */ 2155 mlx5_glue->free_device_list(ibv_list); 2156 DRV_LOG(WARNING, 2157 "no Verbs device matches PCI device " PCI_PRI_FMT "," 2158 " are kernel drivers loaded?", 2159 pci_dev->addr.domain, pci_dev->addr.bus, 2160 pci_dev->addr.devid, pci_dev->addr.function); 2161 rte_errno = ENOENT; 2162 ret = -rte_errno; 2163 return ret; 2164 } 2165 nl_route = mlx5_nl_init(NETLINK_ROUTE); 2166 nl_rdma = mlx5_nl_init(NETLINK_RDMA); 2167 if (nd == 1) { 2168 /* 2169 * Found single matching device may have multiple ports. 2170 * Each port may be representor, we have to check the port 2171 * number and check the representors existence. 2172 */ 2173 if (nl_rdma >= 0) 2174 np = mlx5_nl_portnum(nl_rdma, ibv_match[0]->name); 2175 if (!np) 2176 DRV_LOG(WARNING, "can not get IB device \"%s\"" 2177 " ports number", ibv_match[0]->name); 2178 } 2179 /* 2180 * Now we can determine the maximal 2181 * amount of devices to be spawned. 2182 */ 2183 struct mlx5_dev_spawn_data list[np ? np : nd]; 2184 2185 if (np > 1) { 2186 /* 2187 * Single IB device with multiple ports found, 2188 * it may be E-Switch master device and representors. 2189 * We have to perform identification trough the ports. 2190 */ 2191 assert(nl_rdma >= 0); 2192 assert(ns == 0); 2193 assert(nd == 1); 2194 for (i = 1; i <= np; ++i) { 2195 list[ns].max_port = np; 2196 list[ns].ibv_port = i; 2197 list[ns].ibv_dev = ibv_match[0]; 2198 list[ns].eth_dev = NULL; 2199 list[ns].pci_dev = pci_dev; 2200 list[ns].ifindex = mlx5_nl_ifindex 2201 (nl_rdma, list[ns].ibv_dev->name, i); 2202 if (!list[ns].ifindex) { 2203 /* 2204 * No network interface index found for the 2205 * specified port, it means there is no 2206 * representor on this port. It's OK, 2207 * there can be disabled ports, for example 2208 * if sriov_numvfs < sriov_totalvfs. 2209 */ 2210 continue; 2211 } 2212 ret = -1; 2213 if (nl_route >= 0) 2214 ret = mlx5_nl_switch_info 2215 (nl_route, 2216 list[ns].ifindex, 2217 &list[ns].info); 2218 if (ret || (!list[ns].info.representor && 2219 !list[ns].info.master)) { 2220 /* 2221 * We failed to recognize representors with 2222 * Netlink, let's try to perform the task 2223 * with sysfs. 2224 */ 2225 ret = mlx5_sysfs_switch_info 2226 (list[ns].ifindex, 2227 &list[ns].info); 2228 } 2229 if (!ret && (list[ns].info.representor ^ 2230 list[ns].info.master)) 2231 ns++; 2232 } 2233 if (!ns) { 2234 DRV_LOG(ERR, 2235 "unable to recognize master/representors" 2236 " on the IB device with multiple ports"); 2237 rte_errno = ENOENT; 2238 ret = -rte_errno; 2239 goto exit; 2240 } 2241 } else { 2242 /* 2243 * The existence of several matching entries (nd > 1) means 2244 * port representors have been instantiated. No existing Verbs 2245 * call nor sysfs entries can tell them apart, this can only 2246 * be done through Netlink calls assuming kernel drivers are 2247 * recent enough to support them. 2248 * 2249 * In the event of identification failure through Netlink, 2250 * try again through sysfs, then: 2251 * 2252 * 1. A single IB device matches (nd == 1) with single 2253 * port (np=0/1) and is not a representor, assume 2254 * no switch support. 2255 * 2256 * 2. Otherwise no safe assumptions can be made; 2257 * complain louder and bail out. 2258 */ 2259 np = 1; 2260 for (i = 0; i != nd; ++i) { 2261 memset(&list[ns].info, 0, sizeof(list[ns].info)); 2262 list[ns].max_port = 1; 2263 list[ns].ibv_port = 1; 2264 list[ns].ibv_dev = ibv_match[i]; 2265 list[ns].eth_dev = NULL; 2266 list[ns].pci_dev = pci_dev; 2267 list[ns].ifindex = 0; 2268 if (nl_rdma >= 0) 2269 list[ns].ifindex = mlx5_nl_ifindex 2270 (nl_rdma, list[ns].ibv_dev->name, 1); 2271 if (!list[ns].ifindex) { 2272 char ifname[IF_NAMESIZE]; 2273 2274 /* 2275 * Netlink failed, it may happen with old 2276 * ib_core kernel driver (before 4.16). 2277 * We can assume there is old driver because 2278 * here we are processing single ports IB 2279 * devices. Let's try sysfs to retrieve 2280 * the ifindex. The method works for 2281 * master device only. 2282 */ 2283 if (nd > 1) { 2284 /* 2285 * Multiple devices found, assume 2286 * representors, can not distinguish 2287 * master/representor and retrieve 2288 * ifindex via sysfs. 2289 */ 2290 continue; 2291 } 2292 ret = mlx5_get_master_ifname 2293 (ibv_match[i]->ibdev_path, &ifname); 2294 if (!ret) 2295 list[ns].ifindex = 2296 if_nametoindex(ifname); 2297 if (!list[ns].ifindex) { 2298 /* 2299 * No network interface index found 2300 * for the specified device, it means 2301 * there it is neither representor 2302 * nor master. 2303 */ 2304 continue; 2305 } 2306 } 2307 ret = -1; 2308 if (nl_route >= 0) 2309 ret = mlx5_nl_switch_info 2310 (nl_route, 2311 list[ns].ifindex, 2312 &list[ns].info); 2313 if (ret || (!list[ns].info.representor && 2314 !list[ns].info.master)) { 2315 /* 2316 * We failed to recognize representors with 2317 * Netlink, let's try to perform the task 2318 * with sysfs. 2319 */ 2320 ret = mlx5_sysfs_switch_info 2321 (list[ns].ifindex, 2322 &list[ns].info); 2323 } 2324 if (!ret && (list[ns].info.representor ^ 2325 list[ns].info.master)) { 2326 ns++; 2327 } else if ((nd == 1) && 2328 !list[ns].info.representor && 2329 !list[ns].info.master) { 2330 /* 2331 * Single IB device with 2332 * one physical port and 2333 * attached network device. 2334 * May be SRIOV is not enabled 2335 * or there is no representors. 2336 */ 2337 DRV_LOG(INFO, "no E-Switch support detected"); 2338 ns++; 2339 break; 2340 } 2341 } 2342 if (!ns) { 2343 DRV_LOG(ERR, 2344 "unable to recognize master/representors" 2345 " on the multiple IB devices"); 2346 rte_errno = ENOENT; 2347 ret = -rte_errno; 2348 goto exit; 2349 } 2350 } 2351 assert(ns); 2352 /* 2353 * Sort list to probe devices in natural order for users convenience 2354 * (i.e. master first, then representors from lowest to highest ID). 2355 */ 2356 qsort(list, ns, sizeof(*list), mlx5_dev_spawn_data_cmp); 2357 /* Default configuration. */ 2358 dev_config = (struct mlx5_dev_config){ 2359 .hw_padding = 0, 2360 .mps = MLX5_ARG_UNSET, 2361 .rx_vec_en = 1, 2362 .txq_inline_max = MLX5_ARG_UNSET, 2363 .txq_inline_min = MLX5_ARG_UNSET, 2364 .txq_inline_mpw = MLX5_ARG_UNSET, 2365 .txqs_inline = MLX5_ARG_UNSET, 2366 .vf_nl_en = 1, 2367 .mr_ext_memseg_en = 1, 2368 .mprq = { 2369 .enabled = 0, /* Disabled by default. */ 2370 .stride_num_n = MLX5_MPRQ_STRIDE_NUM_N, 2371 .max_memcpy_len = MLX5_MPRQ_MEMCPY_DEFAULT_LEN, 2372 .min_rxqs_num = MLX5_MPRQ_MIN_RXQS, 2373 }, 2374 .dv_esw_en = 1, 2375 }; 2376 /* Device specific configuration. */ 2377 switch (pci_dev->id.device_id) { 2378 case PCI_DEVICE_ID_MELLANOX_CONNECTX4VF: 2379 case PCI_DEVICE_ID_MELLANOX_CONNECTX4LXVF: 2380 case PCI_DEVICE_ID_MELLANOX_CONNECTX5VF: 2381 case PCI_DEVICE_ID_MELLANOX_CONNECTX5EXVF: 2382 dev_config.vf = 1; 2383 break; 2384 default: 2385 break; 2386 } 2387 for (i = 0; i != ns; ++i) { 2388 uint32_t restore; 2389 2390 list[i].eth_dev = mlx5_dev_spawn(&pci_dev->device, 2391 &list[i], 2392 dev_config); 2393 if (!list[i].eth_dev) { 2394 if (rte_errno != EBUSY && rte_errno != EEXIST) 2395 break; 2396 /* Device is disabled or already spawned. Ignore it. */ 2397 continue; 2398 } 2399 restore = list[i].eth_dev->data->dev_flags; 2400 rte_eth_copy_pci_info(list[i].eth_dev, pci_dev); 2401 /* Restore non-PCI flags cleared by the above call. */ 2402 list[i].eth_dev->data->dev_flags |= restore; 2403 rte_eth_dev_probing_finish(list[i].eth_dev); 2404 } 2405 if (i != ns) { 2406 DRV_LOG(ERR, 2407 "probe of PCI device " PCI_PRI_FMT " aborted after" 2408 " encountering an error: %s", 2409 pci_dev->addr.domain, pci_dev->addr.bus, 2410 pci_dev->addr.devid, pci_dev->addr.function, 2411 strerror(rte_errno)); 2412 ret = -rte_errno; 2413 /* Roll back. */ 2414 while (i--) { 2415 if (!list[i].eth_dev) 2416 continue; 2417 mlx5_dev_close(list[i].eth_dev); 2418 /* mac_addrs must not be freed because in dev_private */ 2419 list[i].eth_dev->data->mac_addrs = NULL; 2420 claim_zero(rte_eth_dev_release_port(list[i].eth_dev)); 2421 } 2422 /* Restore original error. */ 2423 rte_errno = -ret; 2424 } else { 2425 ret = 0; 2426 } 2427 exit: 2428 /* 2429 * Do the routine cleanup: 2430 * - close opened Netlink sockets 2431 * - free the Infiniband device list 2432 */ 2433 if (nl_rdma >= 0) 2434 close(nl_rdma); 2435 if (nl_route >= 0) 2436 close(nl_route); 2437 assert(ibv_list); 2438 mlx5_glue->free_device_list(ibv_list); 2439 return ret; 2440 } 2441 2442 /** 2443 * DPDK callback to remove a PCI device. 2444 * 2445 * This function removes all Ethernet devices belong to a given PCI device. 2446 * 2447 * @param[in] pci_dev 2448 * Pointer to the PCI device. 2449 * 2450 * @return 2451 * 0 on success, the function cannot fail. 2452 */ 2453 static int 2454 mlx5_pci_remove(struct rte_pci_device *pci_dev) 2455 { 2456 uint16_t port_id; 2457 2458 RTE_ETH_FOREACH_DEV_OF(port_id, &pci_dev->device) 2459 rte_eth_dev_close(port_id); 2460 return 0; 2461 } 2462 2463 static const struct rte_pci_id mlx5_pci_id_map[] = { 2464 { 2465 RTE_PCI_DEVICE(PCI_VENDOR_ID_MELLANOX, 2466 PCI_DEVICE_ID_MELLANOX_CONNECTX4) 2467 }, 2468 { 2469 RTE_PCI_DEVICE(PCI_VENDOR_ID_MELLANOX, 2470 PCI_DEVICE_ID_MELLANOX_CONNECTX4VF) 2471 }, 2472 { 2473 RTE_PCI_DEVICE(PCI_VENDOR_ID_MELLANOX, 2474 PCI_DEVICE_ID_MELLANOX_CONNECTX4LX) 2475 }, 2476 { 2477 RTE_PCI_DEVICE(PCI_VENDOR_ID_MELLANOX, 2478 PCI_DEVICE_ID_MELLANOX_CONNECTX4LXVF) 2479 }, 2480 { 2481 RTE_PCI_DEVICE(PCI_VENDOR_ID_MELLANOX, 2482 PCI_DEVICE_ID_MELLANOX_CONNECTX5) 2483 }, 2484 { 2485 RTE_PCI_DEVICE(PCI_VENDOR_ID_MELLANOX, 2486 PCI_DEVICE_ID_MELLANOX_CONNECTX5VF) 2487 }, 2488 { 2489 RTE_PCI_DEVICE(PCI_VENDOR_ID_MELLANOX, 2490 PCI_DEVICE_ID_MELLANOX_CONNECTX5EX) 2491 }, 2492 { 2493 RTE_PCI_DEVICE(PCI_VENDOR_ID_MELLANOX, 2494 PCI_DEVICE_ID_MELLANOX_CONNECTX5EXVF) 2495 }, 2496 { 2497 RTE_PCI_DEVICE(PCI_VENDOR_ID_MELLANOX, 2498 PCI_DEVICE_ID_MELLANOX_CONNECTX5BF) 2499 }, 2500 { 2501 RTE_PCI_DEVICE(PCI_VENDOR_ID_MELLANOX, 2502 PCI_DEVICE_ID_MELLANOX_CONNECTX5BFVF) 2503 }, 2504 { 2505 RTE_PCI_DEVICE(PCI_VENDOR_ID_MELLANOX, 2506 PCI_DEVICE_ID_MELLANOX_CONNECTX6) 2507 }, 2508 { 2509 RTE_PCI_DEVICE(PCI_VENDOR_ID_MELLANOX, 2510 PCI_DEVICE_ID_MELLANOX_CONNECTX6VF) 2511 }, 2512 { 2513 .vendor_id = 0 2514 } 2515 }; 2516 2517 static struct rte_pci_driver mlx5_driver = { 2518 .driver = { 2519 .name = MLX5_DRIVER_NAME 2520 }, 2521 .id_table = mlx5_pci_id_map, 2522 .probe = mlx5_pci_probe, 2523 .remove = mlx5_pci_remove, 2524 .dma_map = mlx5_dma_map, 2525 .dma_unmap = mlx5_dma_unmap, 2526 .drv_flags = RTE_PCI_DRV_INTR_LSC | RTE_PCI_DRV_INTR_RMV | 2527 RTE_PCI_DRV_PROBE_AGAIN, 2528 }; 2529 2530 #ifdef RTE_IBVERBS_LINK_DLOPEN 2531 2532 /** 2533 * Suffix RTE_EAL_PMD_PATH with "-glue". 2534 * 2535 * This function performs a sanity check on RTE_EAL_PMD_PATH before 2536 * suffixing its last component. 2537 * 2538 * @param buf[out] 2539 * Output buffer, should be large enough otherwise NULL is returned. 2540 * @param size 2541 * Size of @p out. 2542 * 2543 * @return 2544 * Pointer to @p buf or @p NULL in case suffix cannot be appended. 2545 */ 2546 static char * 2547 mlx5_glue_path(char *buf, size_t size) 2548 { 2549 static const char *const bad[] = { "/", ".", "..", NULL }; 2550 const char *path = RTE_EAL_PMD_PATH; 2551 size_t len = strlen(path); 2552 size_t off; 2553 int i; 2554 2555 while (len && path[len - 1] == '/') 2556 --len; 2557 for (off = len; off && path[off - 1] != '/'; --off) 2558 ; 2559 for (i = 0; bad[i]; ++i) 2560 if (!strncmp(path + off, bad[i], (int)(len - off))) 2561 goto error; 2562 i = snprintf(buf, size, "%.*s-glue", (int)len, path); 2563 if (i == -1 || (size_t)i >= size) 2564 goto error; 2565 return buf; 2566 error: 2567 DRV_LOG(ERR, 2568 "unable to append \"-glue\" to last component of" 2569 " RTE_EAL_PMD_PATH (\"" RTE_EAL_PMD_PATH "\")," 2570 " please re-configure DPDK"); 2571 return NULL; 2572 } 2573 2574 /** 2575 * Initialization routine for run-time dependency on rdma-core. 2576 */ 2577 static int 2578 mlx5_glue_init(void) 2579 { 2580 char glue_path[sizeof(RTE_EAL_PMD_PATH) - 1 + sizeof("-glue")]; 2581 const char *path[] = { 2582 /* 2583 * A basic security check is necessary before trusting 2584 * MLX5_GLUE_PATH, which may override RTE_EAL_PMD_PATH. 2585 */ 2586 (geteuid() == getuid() && getegid() == getgid() ? 2587 getenv("MLX5_GLUE_PATH") : NULL), 2588 /* 2589 * When RTE_EAL_PMD_PATH is set, use its glue-suffixed 2590 * variant, otherwise let dlopen() look up libraries on its 2591 * own. 2592 */ 2593 (*RTE_EAL_PMD_PATH ? 2594 mlx5_glue_path(glue_path, sizeof(glue_path)) : ""), 2595 }; 2596 unsigned int i = 0; 2597 void *handle = NULL; 2598 void **sym; 2599 const char *dlmsg; 2600 2601 while (!handle && i != RTE_DIM(path)) { 2602 const char *end; 2603 size_t len; 2604 int ret; 2605 2606 if (!path[i]) { 2607 ++i; 2608 continue; 2609 } 2610 end = strpbrk(path[i], ":;"); 2611 if (!end) 2612 end = path[i] + strlen(path[i]); 2613 len = end - path[i]; 2614 ret = 0; 2615 do { 2616 char name[ret + 1]; 2617 2618 ret = snprintf(name, sizeof(name), "%.*s%s" MLX5_GLUE, 2619 (int)len, path[i], 2620 (!len || *(end - 1) == '/') ? "" : "/"); 2621 if (ret == -1) 2622 break; 2623 if (sizeof(name) != (size_t)ret + 1) 2624 continue; 2625 DRV_LOG(DEBUG, "looking for rdma-core glue as \"%s\"", 2626 name); 2627 handle = dlopen(name, RTLD_LAZY); 2628 break; 2629 } while (1); 2630 path[i] = end + 1; 2631 if (!*end) 2632 ++i; 2633 } 2634 if (!handle) { 2635 rte_errno = EINVAL; 2636 dlmsg = dlerror(); 2637 if (dlmsg) 2638 DRV_LOG(WARNING, "cannot load glue library: %s", dlmsg); 2639 goto glue_error; 2640 } 2641 sym = dlsym(handle, "mlx5_glue"); 2642 if (!sym || !*sym) { 2643 rte_errno = EINVAL; 2644 dlmsg = dlerror(); 2645 if (dlmsg) 2646 DRV_LOG(ERR, "cannot resolve glue symbol: %s", dlmsg); 2647 goto glue_error; 2648 } 2649 mlx5_glue = *sym; 2650 return 0; 2651 glue_error: 2652 if (handle) 2653 dlclose(handle); 2654 DRV_LOG(WARNING, 2655 "cannot initialize PMD due to missing run-time dependency on" 2656 " rdma-core libraries (libibverbs, libmlx5)"); 2657 return -rte_errno; 2658 } 2659 2660 #endif 2661 2662 /** 2663 * Driver initialization routine. 2664 */ 2665 RTE_INIT(rte_mlx5_pmd_init) 2666 { 2667 /* Initialize driver log type. */ 2668 mlx5_logtype = rte_log_register("pmd.net.mlx5"); 2669 if (mlx5_logtype >= 0) 2670 rte_log_set_level(mlx5_logtype, RTE_LOG_NOTICE); 2671 2672 /* Build the static tables for Verbs conversion. */ 2673 mlx5_set_ptype_table(); 2674 mlx5_set_cksum_table(); 2675 mlx5_set_swp_types_table(); 2676 /* 2677 * RDMAV_HUGEPAGES_SAFE tells ibv_fork_init() we intend to use 2678 * huge pages. Calling ibv_fork_init() during init allows 2679 * applications to use fork() safely for purposes other than 2680 * using this PMD, which is not supported in forked processes. 2681 */ 2682 setenv("RDMAV_HUGEPAGES_SAFE", "1", 1); 2683 /* Match the size of Rx completion entry to the size of a cacheline. */ 2684 if (RTE_CACHE_LINE_SIZE == 128) 2685 setenv("MLX5_CQE_SIZE", "128", 0); 2686 /* 2687 * MLX5_DEVICE_FATAL_CLEANUP tells ibv_destroy functions to 2688 * cleanup all the Verbs resources even when the device was removed. 2689 */ 2690 setenv("MLX5_DEVICE_FATAL_CLEANUP", "1", 1); 2691 #ifdef RTE_IBVERBS_LINK_DLOPEN 2692 if (mlx5_glue_init()) 2693 return; 2694 assert(mlx5_glue); 2695 #endif 2696 #ifndef NDEBUG 2697 /* Glue structure must not contain any NULL pointers. */ 2698 { 2699 unsigned int i; 2700 2701 for (i = 0; i != sizeof(*mlx5_glue) / sizeof(void *); ++i) 2702 assert(((const void *const *)mlx5_glue)[i]); 2703 } 2704 #endif 2705 if (strcmp(mlx5_glue->version, MLX5_GLUE_VERSION)) { 2706 DRV_LOG(ERR, 2707 "rdma-core glue \"%s\" mismatch: \"%s\" is required", 2708 mlx5_glue->version, MLX5_GLUE_VERSION); 2709 return; 2710 } 2711 mlx5_glue->fork_init(); 2712 rte_pci_register(&mlx5_driver); 2713 } 2714 2715 RTE_PMD_EXPORT_NAME(net_mlx5, __COUNTER__); 2716 RTE_PMD_REGISTER_PCI_TABLE(net_mlx5, mlx5_pci_id_map); 2717 RTE_PMD_REGISTER_KMOD_DEP(net_mlx5, "* ib_uverbs & mlx5_core & mlx5_ib"); 2718