1 /* SPDX-License-Identifier: BSD-3-Clause 2 * Copyright 2015 6WIND S.A. 3 * Copyright 2015 Mellanox Technologies, Ltd 4 */ 5 6 #include <stddef.h> 7 #include <unistd.h> 8 #include <string.h> 9 #include <stdint.h> 10 #include <stdlib.h> 11 #include <errno.h> 12 #include <fcntl.h> 13 14 #include <rte_malloc.h> 15 #include <ethdev_driver.h> 16 #include <rte_pci.h> 17 #include <bus_pci_driver.h> 18 #include <rte_common.h> 19 #include <rte_kvargs.h> 20 #include <rte_rwlock.h> 21 #include <rte_spinlock.h> 22 #include <rte_string_fns.h> 23 #include <rte_eal_paging.h> 24 #include <rte_alarm.h> 25 #include <rte_cycles.h> 26 #include <rte_interrupts.h> 27 28 #include <mlx5_glue.h> 29 #include <mlx5_devx_cmds.h> 30 #include <mlx5_common.h> 31 #include <mlx5_common_os.h> 32 #include <mlx5_common_mp.h> 33 #include <mlx5_malloc.h> 34 35 #include "mlx5_defs.h" 36 #include "mlx5.h" 37 #include "mlx5_utils.h" 38 #include "mlx5_rxtx.h" 39 #include "mlx5_rx.h" 40 #include "mlx5_tx.h" 41 #include "mlx5_autoconf.h" 42 #include "mlx5_flow.h" 43 #include "mlx5_flow_os.h" 44 #include "rte_pmd_mlx5.h" 45 46 #define MLX5_ETH_DRIVER_NAME mlx5_eth 47 48 /* Device parameter to enable RX completion queue compression. */ 49 #define MLX5_RXQ_CQE_COMP_EN "rxq_cqe_comp_en" 50 51 /* Device parameter to enable padding Rx packet to cacheline size. */ 52 #define MLX5_RXQ_PKT_PAD_EN "rxq_pkt_pad_en" 53 54 /* Device parameter to enable Multi-Packet Rx queue. */ 55 #define MLX5_RX_MPRQ_EN "mprq_en" 56 57 /* Device parameter to configure log 2 of the number of strides for MPRQ. */ 58 #define MLX5_RX_MPRQ_LOG_STRIDE_NUM "mprq_log_stride_num" 59 60 /* Device parameter to configure log 2 of the stride size for MPRQ. */ 61 #define MLX5_RX_MPRQ_LOG_STRIDE_SIZE "mprq_log_stride_size" 62 63 /* Device parameter to limit the size of memcpy'd packet for MPRQ. */ 64 #define MLX5_RX_MPRQ_MAX_MEMCPY_LEN "mprq_max_memcpy_len" 65 66 /* Device parameter to set the minimum number of Rx queues to enable MPRQ. */ 67 #define MLX5_RXQS_MIN_MPRQ "rxqs_min_mprq" 68 69 /* Device parameter to configure inline send. Deprecated, ignored.*/ 70 #define MLX5_TXQ_INLINE "txq_inline" 71 72 /* Device parameter to limit packet size to inline with ordinary SEND. */ 73 #define MLX5_TXQ_INLINE_MAX "txq_inline_max" 74 75 /* Device parameter to configure minimal data size to inline. */ 76 #define MLX5_TXQ_INLINE_MIN "txq_inline_min" 77 78 /* Device parameter to limit packet size to inline with Enhanced MPW. */ 79 #define MLX5_TXQ_INLINE_MPW "txq_inline_mpw" 80 81 /* 82 * Device parameter to configure the number of TX queues threshold for 83 * enabling inline send. 84 */ 85 #define MLX5_TXQS_MIN_INLINE "txqs_min_inline" 86 87 /* 88 * Device parameter to configure the number of TX queues threshold for 89 * enabling vectorized Tx, deprecated, ignored (no vectorized Tx routines). 90 */ 91 #define MLX5_TXQS_MAX_VEC "txqs_max_vec" 92 93 /* Device parameter to enable multi-packet send WQEs. */ 94 #define MLX5_TXQ_MPW_EN "txq_mpw_en" 95 96 /* 97 * Device parameter to include 2 dsegs in the title WQEBB. 98 * Deprecated, ignored. 99 */ 100 #define MLX5_TXQ_MPW_HDR_DSEG_EN "txq_mpw_hdr_dseg_en" 101 102 /* 103 * Device parameter to limit the size of inlining packet. 104 * Deprecated, ignored. 105 */ 106 #define MLX5_TXQ_MAX_INLINE_LEN "txq_max_inline_len" 107 108 /* 109 * Device parameter to enable Tx scheduling on timestamps 110 * and specify the packet pacing granularity in nanoseconds. 111 */ 112 #define MLX5_TX_PP "tx_pp" 113 114 /* 115 * Device parameter to specify skew in nanoseconds on Tx datapath, 116 * it represents the time between SQ start WQE processing and 117 * appearing actual packet data on the wire. 118 */ 119 #define MLX5_TX_SKEW "tx_skew" 120 121 /* 122 * Device parameter to enable hardware Tx vector. 123 * Deprecated, ignored (no vectorized Tx routines anymore). 124 */ 125 #define MLX5_TX_VEC_EN "tx_vec_en" 126 127 /* Device parameter to enable hardware Rx vector. */ 128 #define MLX5_RX_VEC_EN "rx_vec_en" 129 130 /* Allow L3 VXLAN flow creation. */ 131 #define MLX5_L3_VXLAN_EN "l3_vxlan_en" 132 133 /* Activate DV E-Switch flow steering. */ 134 #define MLX5_DV_ESW_EN "dv_esw_en" 135 136 /* Activate DV flow steering. */ 137 #define MLX5_DV_FLOW_EN "dv_flow_en" 138 139 /* Enable extensive flow metadata support. */ 140 #define MLX5_DV_XMETA_EN "dv_xmeta_en" 141 142 /* Device parameter to let the user manage the lacp traffic of bonded device */ 143 #define MLX5_LACP_BY_USER "lacp_by_user" 144 145 /* Activate Netlink support in VF mode. */ 146 #define MLX5_VF_NL_EN "vf_nl_en" 147 148 /* Select port representors to instantiate. */ 149 #define MLX5_REPRESENTOR "representor" 150 151 /* Device parameter to configure the maximum number of dump files per queue. */ 152 #define MLX5_MAX_DUMP_FILES_NUM "max_dump_files_num" 153 154 /* Configure timeout of LRO session (in microseconds). */ 155 #define MLX5_LRO_TIMEOUT_USEC "lro_timeout_usec" 156 157 /* 158 * Device parameter to configure the total data buffer size for a single 159 * hairpin queue (logarithm value). 160 */ 161 #define MLX5_HP_BUF_SIZE "hp_buf_log_sz" 162 163 /* Flow memory reclaim mode. */ 164 #define MLX5_RECLAIM_MEM "reclaim_mem_mode" 165 166 /* Decap will be used or not. */ 167 #define MLX5_DECAP_EN "decap_en" 168 169 /* Device parameter to configure allow or prevent duplicate rules pattern. */ 170 #define MLX5_ALLOW_DUPLICATE_PATTERN "allow_duplicate_pattern" 171 172 /* Device parameter to configure the delay drop when creating Rxqs. */ 173 #define MLX5_DELAY_DROP "delay_drop" 174 175 /* Shared memory between primary and secondary processes. */ 176 struct mlx5_shared_data *mlx5_shared_data; 177 178 /** Driver-specific log messages type. */ 179 int mlx5_logtype; 180 181 static LIST_HEAD(, mlx5_dev_ctx_shared) mlx5_dev_ctx_list = 182 LIST_HEAD_INITIALIZER(); 183 static pthread_mutex_t mlx5_dev_ctx_list_mutex; 184 static const struct mlx5_indexed_pool_config mlx5_ipool_cfg[] = { 185 #if defined(HAVE_IBV_FLOW_DV_SUPPORT) || !defined(HAVE_INFINIBAND_VERBS_H) 186 [MLX5_IPOOL_DECAP_ENCAP] = { 187 .size = sizeof(struct mlx5_flow_dv_encap_decap_resource), 188 .trunk_size = 64, 189 .grow_trunk = 3, 190 .grow_shift = 2, 191 .need_lock = 1, 192 .release_mem_en = 1, 193 .malloc = mlx5_malloc, 194 .free = mlx5_free, 195 .type = "mlx5_encap_decap_ipool", 196 }, 197 [MLX5_IPOOL_PUSH_VLAN] = { 198 .size = sizeof(struct mlx5_flow_dv_push_vlan_action_resource), 199 .trunk_size = 64, 200 .grow_trunk = 3, 201 .grow_shift = 2, 202 .need_lock = 1, 203 .release_mem_en = 1, 204 .malloc = mlx5_malloc, 205 .free = mlx5_free, 206 .type = "mlx5_push_vlan_ipool", 207 }, 208 [MLX5_IPOOL_TAG] = { 209 .size = sizeof(struct mlx5_flow_dv_tag_resource), 210 .trunk_size = 64, 211 .grow_trunk = 3, 212 .grow_shift = 2, 213 .need_lock = 1, 214 .release_mem_en = 0, 215 .per_core_cache = (1 << 16), 216 .malloc = mlx5_malloc, 217 .free = mlx5_free, 218 .type = "mlx5_tag_ipool", 219 }, 220 [MLX5_IPOOL_PORT_ID] = { 221 .size = sizeof(struct mlx5_flow_dv_port_id_action_resource), 222 .trunk_size = 64, 223 .grow_trunk = 3, 224 .grow_shift = 2, 225 .need_lock = 1, 226 .release_mem_en = 1, 227 .malloc = mlx5_malloc, 228 .free = mlx5_free, 229 .type = "mlx5_port_id_ipool", 230 }, 231 [MLX5_IPOOL_JUMP] = { 232 .size = sizeof(struct mlx5_flow_tbl_data_entry), 233 .trunk_size = 64, 234 .grow_trunk = 3, 235 .grow_shift = 2, 236 .need_lock = 1, 237 .release_mem_en = 1, 238 .malloc = mlx5_malloc, 239 .free = mlx5_free, 240 .type = "mlx5_jump_ipool", 241 }, 242 [MLX5_IPOOL_SAMPLE] = { 243 .size = sizeof(struct mlx5_flow_dv_sample_resource), 244 .trunk_size = 64, 245 .grow_trunk = 3, 246 .grow_shift = 2, 247 .need_lock = 1, 248 .release_mem_en = 1, 249 .malloc = mlx5_malloc, 250 .free = mlx5_free, 251 .type = "mlx5_sample_ipool", 252 }, 253 [MLX5_IPOOL_DEST_ARRAY] = { 254 .size = sizeof(struct mlx5_flow_dv_dest_array_resource), 255 .trunk_size = 64, 256 .grow_trunk = 3, 257 .grow_shift = 2, 258 .need_lock = 1, 259 .release_mem_en = 1, 260 .malloc = mlx5_malloc, 261 .free = mlx5_free, 262 .type = "mlx5_dest_array_ipool", 263 }, 264 [MLX5_IPOOL_TUNNEL_ID] = { 265 .size = sizeof(struct mlx5_flow_tunnel), 266 .trunk_size = MLX5_MAX_TUNNELS, 267 .need_lock = 1, 268 .release_mem_en = 1, 269 .type = "mlx5_tunnel_offload", 270 }, 271 [MLX5_IPOOL_TNL_TBL_ID] = { 272 .size = 0, 273 .need_lock = 1, 274 .type = "mlx5_flow_tnl_tbl_ipool", 275 }, 276 #endif 277 [MLX5_IPOOL_MTR] = { 278 /** 279 * The ipool index should grow continually from small to big, 280 * for meter idx, so not set grow_trunk to avoid meter index 281 * not jump continually. 282 */ 283 .size = sizeof(struct mlx5_legacy_flow_meter), 284 .trunk_size = 64, 285 .need_lock = 1, 286 .release_mem_en = 1, 287 .malloc = mlx5_malloc, 288 .free = mlx5_free, 289 .type = "mlx5_meter_ipool", 290 }, 291 [MLX5_IPOOL_MCP] = { 292 .size = sizeof(struct mlx5_flow_mreg_copy_resource), 293 .trunk_size = 64, 294 .grow_trunk = 3, 295 .grow_shift = 2, 296 .need_lock = 1, 297 .release_mem_en = 1, 298 .malloc = mlx5_malloc, 299 .free = mlx5_free, 300 .type = "mlx5_mcp_ipool", 301 }, 302 [MLX5_IPOOL_HRXQ] = { 303 .size = (sizeof(struct mlx5_hrxq) + MLX5_RSS_HASH_KEY_LEN), 304 .trunk_size = 64, 305 .grow_trunk = 3, 306 .grow_shift = 2, 307 .need_lock = 1, 308 .release_mem_en = 1, 309 .malloc = mlx5_malloc, 310 .free = mlx5_free, 311 .type = "mlx5_hrxq_ipool", 312 }, 313 [MLX5_IPOOL_MLX5_FLOW] = { 314 /* 315 * MLX5_IPOOL_MLX5_FLOW size varies for DV and VERBS flows. 316 * It set in run time according to PCI function configuration. 317 */ 318 .size = 0, 319 .trunk_size = 64, 320 .grow_trunk = 3, 321 .grow_shift = 2, 322 .need_lock = 1, 323 .release_mem_en = 0, 324 .per_core_cache = 1 << 19, 325 .malloc = mlx5_malloc, 326 .free = mlx5_free, 327 .type = "mlx5_flow_handle_ipool", 328 }, 329 [MLX5_IPOOL_RTE_FLOW] = { 330 .size = sizeof(struct rte_flow), 331 .trunk_size = 4096, 332 .need_lock = 1, 333 .release_mem_en = 1, 334 .malloc = mlx5_malloc, 335 .free = mlx5_free, 336 .type = "rte_flow_ipool", 337 }, 338 [MLX5_IPOOL_RSS_EXPANTION_FLOW_ID] = { 339 .size = 0, 340 .need_lock = 1, 341 .type = "mlx5_flow_rss_id_ipool", 342 }, 343 [MLX5_IPOOL_RSS_SHARED_ACTIONS] = { 344 .size = sizeof(struct mlx5_shared_action_rss), 345 .trunk_size = 64, 346 .grow_trunk = 3, 347 .grow_shift = 2, 348 .need_lock = 1, 349 .release_mem_en = 1, 350 .malloc = mlx5_malloc, 351 .free = mlx5_free, 352 .type = "mlx5_shared_action_rss", 353 }, 354 [MLX5_IPOOL_MTR_POLICY] = { 355 /** 356 * The ipool index should grow continually from small to big, 357 * for policy idx, so not set grow_trunk to avoid policy index 358 * not jump continually. 359 */ 360 .size = sizeof(struct mlx5_flow_meter_sub_policy), 361 .trunk_size = 64, 362 .need_lock = 1, 363 .release_mem_en = 1, 364 .malloc = mlx5_malloc, 365 .free = mlx5_free, 366 .type = "mlx5_meter_policy_ipool", 367 }, 368 }; 369 370 #define MLX5_FLOW_MIN_ID_POOL_SIZE 512 371 #define MLX5_ID_GENERATION_ARRAY_FACTOR 16 372 373 #define MLX5_FLOW_TABLE_HLIST_ARRAY_SIZE 1024 374 375 /** 376 * Decide whether representor ID is a HPF(host PF) port on BF2. 377 * 378 * @param dev 379 * Pointer to Ethernet device structure. 380 * 381 * @return 382 * Non-zero if HPF, otherwise 0. 383 */ 384 bool 385 mlx5_is_hpf(struct rte_eth_dev *dev) 386 { 387 struct mlx5_priv *priv = dev->data->dev_private; 388 uint16_t repr = MLX5_REPRESENTOR_REPR(priv->representor_id); 389 int type = MLX5_REPRESENTOR_TYPE(priv->representor_id); 390 391 return priv->representor != 0 && type == RTE_ETH_REPRESENTOR_VF && 392 MLX5_REPRESENTOR_REPR(-1) == repr; 393 } 394 395 /** 396 * Decide whether representor ID is a SF port representor. 397 * 398 * @param dev 399 * Pointer to Ethernet device structure. 400 * 401 * @return 402 * Non-zero if HPF, otherwise 0. 403 */ 404 bool 405 mlx5_is_sf_repr(struct rte_eth_dev *dev) 406 { 407 struct mlx5_priv *priv = dev->data->dev_private; 408 int type = MLX5_REPRESENTOR_TYPE(priv->representor_id); 409 410 return priv->representor != 0 && type == RTE_ETH_REPRESENTOR_SF; 411 } 412 413 /** 414 * Initialize the ASO aging management structure. 415 * 416 * @param[in] sh 417 * Pointer to mlx5_dev_ctx_shared object to free 418 * 419 * @return 420 * 0 on success, a negative errno value otherwise and rte_errno is set. 421 */ 422 int 423 mlx5_flow_aso_age_mng_init(struct mlx5_dev_ctx_shared *sh) 424 { 425 int err; 426 427 if (sh->aso_age_mng) 428 return 0; 429 sh->aso_age_mng = mlx5_malloc(MLX5_MEM_ZERO, sizeof(*sh->aso_age_mng), 430 RTE_CACHE_LINE_SIZE, SOCKET_ID_ANY); 431 if (!sh->aso_age_mng) { 432 DRV_LOG(ERR, "aso_age_mng allocation was failed."); 433 rte_errno = ENOMEM; 434 return -ENOMEM; 435 } 436 err = mlx5_aso_queue_init(sh, ASO_OPC_MOD_FLOW_HIT); 437 if (err) { 438 mlx5_free(sh->aso_age_mng); 439 return -1; 440 } 441 rte_rwlock_init(&sh->aso_age_mng->resize_rwl); 442 rte_spinlock_init(&sh->aso_age_mng->free_sl); 443 LIST_INIT(&sh->aso_age_mng->free); 444 return 0; 445 } 446 447 /** 448 * Close and release all the resources of the ASO aging management structure. 449 * 450 * @param[in] sh 451 * Pointer to mlx5_dev_ctx_shared object to free. 452 */ 453 static void 454 mlx5_flow_aso_age_mng_close(struct mlx5_dev_ctx_shared *sh) 455 { 456 int i, j; 457 458 mlx5_aso_flow_hit_queue_poll_stop(sh); 459 mlx5_aso_queue_uninit(sh, ASO_OPC_MOD_FLOW_HIT); 460 if (sh->aso_age_mng->pools) { 461 struct mlx5_aso_age_pool *pool; 462 463 for (i = 0; i < sh->aso_age_mng->next; ++i) { 464 pool = sh->aso_age_mng->pools[i]; 465 claim_zero(mlx5_devx_cmd_destroy 466 (pool->flow_hit_aso_obj)); 467 for (j = 0; j < MLX5_COUNTERS_PER_POOL; ++j) 468 if (pool->actions[j].dr_action) 469 claim_zero 470 (mlx5_flow_os_destroy_flow_action 471 (pool->actions[j].dr_action)); 472 mlx5_free(pool); 473 } 474 mlx5_free(sh->aso_age_mng->pools); 475 } 476 mlx5_free(sh->aso_age_mng); 477 } 478 479 /** 480 * Initialize the shared aging list information per port. 481 * 482 * @param[in] sh 483 * Pointer to mlx5_dev_ctx_shared object. 484 */ 485 static void 486 mlx5_flow_aging_init(struct mlx5_dev_ctx_shared *sh) 487 { 488 uint32_t i; 489 struct mlx5_age_info *age_info; 490 491 for (i = 0; i < sh->max_port; i++) { 492 age_info = &sh->port[i].age_info; 493 age_info->flags = 0; 494 TAILQ_INIT(&age_info->aged_counters); 495 LIST_INIT(&age_info->aged_aso); 496 rte_spinlock_init(&age_info->aged_sl); 497 MLX5_AGE_SET(age_info, MLX5_AGE_TRIGGER); 498 } 499 } 500 501 /** 502 * DV flow counter mode detect and config. 503 * 504 * @param dev 505 * Pointer to rte_eth_dev structure. 506 * 507 */ 508 void 509 mlx5_flow_counter_mode_config(struct rte_eth_dev *dev __rte_unused) 510 { 511 #ifdef HAVE_IBV_FLOW_DV_SUPPORT 512 struct mlx5_priv *priv = dev->data->dev_private; 513 struct mlx5_dev_ctx_shared *sh = priv->sh; 514 struct mlx5_hca_attr *hca_attr = &sh->cdev->config.hca_attr; 515 bool fallback; 516 517 #ifndef HAVE_IBV_DEVX_ASYNC 518 fallback = true; 519 #else 520 fallback = false; 521 if (!sh->cdev->config.devx || !sh->config.dv_flow_en || 522 !hca_attr->flow_counters_dump || 523 !(hca_attr->flow_counter_bulk_alloc_bitmap & 0x4) || 524 (mlx5_flow_dv_discover_counter_offset_support(dev) == -ENOTSUP)) 525 fallback = true; 526 #endif 527 if (fallback) 528 DRV_LOG(INFO, "Use fall-back DV counter management. Flow " 529 "counter dump:%d, bulk_alloc_bitmap:0x%hhx.", 530 hca_attr->flow_counters_dump, 531 hca_attr->flow_counter_bulk_alloc_bitmap); 532 /* Initialize fallback mode only on the port initializes sh. */ 533 if (sh->refcnt == 1) 534 sh->cmng.counter_fallback = fallback; 535 else if (fallback != sh->cmng.counter_fallback) 536 DRV_LOG(WARNING, "Port %d in sh has different fallback mode " 537 "with others:%d.", PORT_ID(priv), fallback); 538 #endif 539 } 540 541 /** 542 * Initialize the counters management structure. 543 * 544 * @param[in] sh 545 * Pointer to mlx5_dev_ctx_shared object to free 546 */ 547 static void 548 mlx5_flow_counters_mng_init(struct mlx5_dev_ctx_shared *sh) 549 { 550 int i; 551 552 memset(&sh->cmng, 0, sizeof(sh->cmng)); 553 TAILQ_INIT(&sh->cmng.flow_counters); 554 sh->cmng.min_id = MLX5_CNT_BATCH_OFFSET; 555 sh->cmng.max_id = -1; 556 sh->cmng.last_pool_idx = POOL_IDX_INVALID; 557 rte_spinlock_init(&sh->cmng.pool_update_sl); 558 for (i = 0; i < MLX5_COUNTER_TYPE_MAX; i++) { 559 TAILQ_INIT(&sh->cmng.counters[i]); 560 rte_spinlock_init(&sh->cmng.csl[i]); 561 } 562 } 563 564 /** 565 * Destroy all the resources allocated for a counter memory management. 566 * 567 * @param[in] mng 568 * Pointer to the memory management structure. 569 */ 570 static void 571 mlx5_flow_destroy_counter_stat_mem_mng(struct mlx5_counter_stats_mem_mng *mng) 572 { 573 uint8_t *mem = (uint8_t *)(uintptr_t)mng->raws[0].data; 574 575 LIST_REMOVE(mng, next); 576 mlx5_os_wrapped_mkey_destroy(&mng->wm); 577 mlx5_free(mem); 578 } 579 580 /** 581 * Close and release all the resources of the counters management. 582 * 583 * @param[in] sh 584 * Pointer to mlx5_dev_ctx_shared object to free. 585 */ 586 static void 587 mlx5_flow_counters_mng_close(struct mlx5_dev_ctx_shared *sh) 588 { 589 struct mlx5_counter_stats_mem_mng *mng; 590 int i, j; 591 int retries = 1024; 592 593 rte_errno = 0; 594 while (--retries) { 595 rte_eal_alarm_cancel(mlx5_flow_query_alarm, sh); 596 if (rte_errno != EINPROGRESS) 597 break; 598 rte_pause(); 599 } 600 601 if (sh->cmng.pools) { 602 struct mlx5_flow_counter_pool *pool; 603 uint16_t n_valid = sh->cmng.n_valid; 604 bool fallback = sh->cmng.counter_fallback; 605 606 for (i = 0; i < n_valid; ++i) { 607 pool = sh->cmng.pools[i]; 608 if (!fallback && pool->min_dcs) 609 claim_zero(mlx5_devx_cmd_destroy 610 (pool->min_dcs)); 611 for (j = 0; j < MLX5_COUNTERS_PER_POOL; ++j) { 612 struct mlx5_flow_counter *cnt = 613 MLX5_POOL_GET_CNT(pool, j); 614 615 if (cnt->action) 616 claim_zero 617 (mlx5_flow_os_destroy_flow_action 618 (cnt->action)); 619 if (fallback && MLX5_POOL_GET_CNT 620 (pool, j)->dcs_when_free) 621 claim_zero(mlx5_devx_cmd_destroy 622 (cnt->dcs_when_free)); 623 } 624 mlx5_free(pool); 625 } 626 mlx5_free(sh->cmng.pools); 627 } 628 mng = LIST_FIRST(&sh->cmng.mem_mngs); 629 while (mng) { 630 mlx5_flow_destroy_counter_stat_mem_mng(mng); 631 mng = LIST_FIRST(&sh->cmng.mem_mngs); 632 } 633 memset(&sh->cmng, 0, sizeof(sh->cmng)); 634 } 635 636 /** 637 * Initialize the aso flow meters management structure. 638 * 639 * @param[in] sh 640 * Pointer to mlx5_dev_ctx_shared object to free 641 */ 642 int 643 mlx5_aso_flow_mtrs_mng_init(struct mlx5_dev_ctx_shared *sh) 644 { 645 if (!sh->mtrmng) { 646 sh->mtrmng = mlx5_malloc(MLX5_MEM_ZERO, 647 sizeof(*sh->mtrmng), 648 RTE_CACHE_LINE_SIZE, SOCKET_ID_ANY); 649 if (!sh->mtrmng) { 650 DRV_LOG(ERR, 651 "meter management allocation was failed."); 652 rte_errno = ENOMEM; 653 return -ENOMEM; 654 } 655 if (sh->meter_aso_en) { 656 rte_spinlock_init(&sh->mtrmng->pools_mng.mtrsl); 657 rte_rwlock_init(&sh->mtrmng->pools_mng.resize_mtrwl); 658 LIST_INIT(&sh->mtrmng->pools_mng.meters); 659 } 660 sh->mtrmng->def_policy_id = MLX5_INVALID_POLICY_ID; 661 } 662 return 0; 663 } 664 665 /** 666 * Close and release all the resources of 667 * the ASO flow meter management structure. 668 * 669 * @param[in] sh 670 * Pointer to mlx5_dev_ctx_shared object to free. 671 */ 672 static void 673 mlx5_aso_flow_mtrs_mng_close(struct mlx5_dev_ctx_shared *sh) 674 { 675 struct mlx5_aso_mtr_pool *mtr_pool; 676 struct mlx5_flow_mtr_mng *mtrmng = sh->mtrmng; 677 uint32_t idx; 678 #ifdef HAVE_MLX5_DR_CREATE_ACTION_ASO 679 struct mlx5_aso_mtr *aso_mtr; 680 int i; 681 #endif /* HAVE_MLX5_DR_CREATE_ACTION_ASO */ 682 683 if (sh->meter_aso_en) { 684 mlx5_aso_queue_uninit(sh, ASO_OPC_MOD_POLICER); 685 idx = mtrmng->pools_mng.n_valid; 686 while (idx--) { 687 mtr_pool = mtrmng->pools_mng.pools[idx]; 688 #ifdef HAVE_MLX5_DR_CREATE_ACTION_ASO 689 for (i = 0; i < MLX5_ASO_MTRS_PER_POOL; i++) { 690 aso_mtr = &mtr_pool->mtrs[i]; 691 if (aso_mtr->fm.meter_action_g) 692 claim_zero 693 (mlx5_glue->destroy_flow_action 694 (aso_mtr->fm.meter_action_g)); 695 if (aso_mtr->fm.meter_action_y) 696 claim_zero 697 (mlx5_glue->destroy_flow_action 698 (aso_mtr->fm.meter_action_y)); 699 } 700 #endif /* HAVE_MLX5_DR_CREATE_ACTION_ASO */ 701 claim_zero(mlx5_devx_cmd_destroy 702 (mtr_pool->devx_obj)); 703 mtrmng->pools_mng.n_valid--; 704 mlx5_free(mtr_pool); 705 } 706 mlx5_free(sh->mtrmng->pools_mng.pools); 707 } 708 mlx5_free(sh->mtrmng); 709 sh->mtrmng = NULL; 710 } 711 712 /* Send FLOW_AGED event if needed. */ 713 void 714 mlx5_age_event_prepare(struct mlx5_dev_ctx_shared *sh) 715 { 716 struct mlx5_age_info *age_info; 717 uint32_t i; 718 719 for (i = 0; i < sh->max_port; i++) { 720 age_info = &sh->port[i].age_info; 721 if (!MLX5_AGE_GET(age_info, MLX5_AGE_EVENT_NEW)) 722 continue; 723 MLX5_AGE_UNSET(age_info, MLX5_AGE_EVENT_NEW); 724 if (MLX5_AGE_GET(age_info, MLX5_AGE_TRIGGER)) { 725 MLX5_AGE_UNSET(age_info, MLX5_AGE_TRIGGER); 726 rte_eth_dev_callback_process 727 (&rte_eth_devices[sh->port[i].devx_ih_port_id], 728 RTE_ETH_EVENT_FLOW_AGED, NULL); 729 } 730 } 731 } 732 733 /* 734 * Initialize the ASO connection tracking structure. 735 * 736 * @param[in] sh 737 * Pointer to mlx5_dev_ctx_shared object. 738 * 739 * @return 740 * 0 on success, a negative errno value otherwise and rte_errno is set. 741 */ 742 int 743 mlx5_flow_aso_ct_mng_init(struct mlx5_dev_ctx_shared *sh) 744 { 745 int err; 746 747 if (sh->ct_mng) 748 return 0; 749 sh->ct_mng = mlx5_malloc(MLX5_MEM_ZERO, sizeof(*sh->ct_mng), 750 RTE_CACHE_LINE_SIZE, SOCKET_ID_ANY); 751 if (!sh->ct_mng) { 752 DRV_LOG(ERR, "ASO CT management allocation failed."); 753 rte_errno = ENOMEM; 754 return -rte_errno; 755 } 756 err = mlx5_aso_queue_init(sh, ASO_OPC_MOD_CONNECTION_TRACKING); 757 if (err) { 758 mlx5_free(sh->ct_mng); 759 /* rte_errno should be extracted from the failure. */ 760 rte_errno = EINVAL; 761 return -rte_errno; 762 } 763 rte_spinlock_init(&sh->ct_mng->ct_sl); 764 rte_rwlock_init(&sh->ct_mng->resize_rwl); 765 LIST_INIT(&sh->ct_mng->free_cts); 766 return 0; 767 } 768 769 /* 770 * Close and release all the resources of the 771 * ASO connection tracking management structure. 772 * 773 * @param[in] sh 774 * Pointer to mlx5_dev_ctx_shared object to free. 775 */ 776 static void 777 mlx5_flow_aso_ct_mng_close(struct mlx5_dev_ctx_shared *sh) 778 { 779 struct mlx5_aso_ct_pools_mng *mng = sh->ct_mng; 780 struct mlx5_aso_ct_pool *ct_pool; 781 struct mlx5_aso_ct_action *ct; 782 uint32_t idx; 783 uint32_t val; 784 uint32_t cnt; 785 int i; 786 787 mlx5_aso_queue_uninit(sh, ASO_OPC_MOD_CONNECTION_TRACKING); 788 idx = mng->next; 789 while (idx--) { 790 cnt = 0; 791 ct_pool = mng->pools[idx]; 792 for (i = 0; i < MLX5_ASO_CT_ACTIONS_PER_POOL; i++) { 793 ct = &ct_pool->actions[i]; 794 val = __atomic_fetch_sub(&ct->refcnt, 1, 795 __ATOMIC_RELAXED); 796 MLX5_ASSERT(val == 1); 797 if (val > 1) 798 cnt++; 799 #ifdef HAVE_MLX5_DR_ACTION_ASO_CT 800 if (ct->dr_action_orig) 801 claim_zero(mlx5_glue->destroy_flow_action 802 (ct->dr_action_orig)); 803 if (ct->dr_action_rply) 804 claim_zero(mlx5_glue->destroy_flow_action 805 (ct->dr_action_rply)); 806 #endif 807 } 808 claim_zero(mlx5_devx_cmd_destroy(ct_pool->devx_obj)); 809 if (cnt) { 810 DRV_LOG(DEBUG, "%u ASO CT objects are being used in the pool %u", 811 cnt, i); 812 } 813 mlx5_free(ct_pool); 814 /* in case of failure. */ 815 mng->next--; 816 } 817 mlx5_free(mng->pools); 818 mlx5_free(mng); 819 /* Management structure must be cleared to 0s during allocation. */ 820 sh->ct_mng = NULL; 821 } 822 823 /** 824 * Initialize the flow resources' indexed mempool. 825 * 826 * @param[in] sh 827 * Pointer to mlx5_dev_ctx_shared object. 828 */ 829 static void 830 mlx5_flow_ipool_create(struct mlx5_dev_ctx_shared *sh) 831 { 832 uint8_t i; 833 struct mlx5_indexed_pool_config cfg; 834 835 for (i = 0; i < MLX5_IPOOL_MAX; ++i) { 836 cfg = mlx5_ipool_cfg[i]; 837 switch (i) { 838 default: 839 break; 840 /* 841 * Set MLX5_IPOOL_MLX5_FLOW ipool size 842 * according to PCI function flow configuration. 843 */ 844 case MLX5_IPOOL_MLX5_FLOW: 845 cfg.size = sh->config.dv_flow_en ? 846 sizeof(struct mlx5_flow_handle) : 847 MLX5_FLOW_HANDLE_VERBS_SIZE; 848 break; 849 } 850 if (sh->config.reclaim_mode) { 851 cfg.release_mem_en = 1; 852 cfg.per_core_cache = 0; 853 } else { 854 cfg.release_mem_en = 0; 855 } 856 sh->ipool[i] = mlx5_ipool_create(&cfg); 857 } 858 } 859 860 861 /** 862 * Release the flow resources' indexed mempool. 863 * 864 * @param[in] sh 865 * Pointer to mlx5_dev_ctx_shared object. 866 */ 867 static void 868 mlx5_flow_ipool_destroy(struct mlx5_dev_ctx_shared *sh) 869 { 870 uint8_t i; 871 872 for (i = 0; i < MLX5_IPOOL_MAX; ++i) 873 mlx5_ipool_destroy(sh->ipool[i]); 874 for (i = 0; i < MLX5_MAX_MODIFY_NUM; ++i) 875 if (sh->mdh_ipools[i]) 876 mlx5_ipool_destroy(sh->mdh_ipools[i]); 877 } 878 879 /* 880 * Check if dynamic flex parser for eCPRI already exists. 881 * 882 * @param dev 883 * Pointer to Ethernet device structure. 884 * 885 * @return 886 * true on exists, false on not. 887 */ 888 bool 889 mlx5_flex_parser_ecpri_exist(struct rte_eth_dev *dev) 890 { 891 struct mlx5_priv *priv = dev->data->dev_private; 892 struct mlx5_ecpri_parser_profile *prf = &priv->sh->ecpri_parser; 893 894 return !!prf->obj; 895 } 896 897 /* 898 * Allocation of a flex parser for eCPRI. Once created, this parser related 899 * resources will be held until the device is closed. 900 * 901 * @param dev 902 * Pointer to Ethernet device structure. 903 * 904 * @return 905 * 0 on success, a negative errno value otherwise and rte_errno is set. 906 */ 907 int 908 mlx5_flex_parser_ecpri_alloc(struct rte_eth_dev *dev) 909 { 910 struct mlx5_priv *priv = dev->data->dev_private; 911 struct mlx5_ecpri_parser_profile *prf = &priv->sh->ecpri_parser; 912 struct mlx5_devx_graph_node_attr node = { 913 .modify_field_select = 0, 914 }; 915 uint32_t ids[8]; 916 int ret; 917 918 if (!priv->sh->cdev->config.hca_attr.parse_graph_flex_node) { 919 DRV_LOG(ERR, "Dynamic flex parser is not supported " 920 "for device %s.", priv->dev_data->name); 921 return -ENOTSUP; 922 } 923 node.header_length_mode = MLX5_GRAPH_NODE_LEN_FIXED; 924 /* 8 bytes now: 4B common header + 4B message body header. */ 925 node.header_length_base_value = 0x8; 926 /* After MAC layer: Ether / VLAN. */ 927 node.in[0].arc_parse_graph_node = MLX5_GRAPH_ARC_NODE_MAC; 928 /* Type of compared condition should be 0xAEFE in the L2 layer. */ 929 node.in[0].compare_condition_value = RTE_ETHER_TYPE_ECPRI; 930 /* Sample #0: type in common header. */ 931 node.sample[0].flow_match_sample_en = 1; 932 /* Fixed offset. */ 933 node.sample[0].flow_match_sample_offset_mode = 0x0; 934 /* Only the 2nd byte will be used. */ 935 node.sample[0].flow_match_sample_field_base_offset = 0x0; 936 /* Sample #1: message payload. */ 937 node.sample[1].flow_match_sample_en = 1; 938 /* Fixed offset. */ 939 node.sample[1].flow_match_sample_offset_mode = 0x0; 940 /* 941 * Only the first two bytes will be used right now, and its offset will 942 * start after the common header that with the length of a DW(u32). 943 */ 944 node.sample[1].flow_match_sample_field_base_offset = sizeof(uint32_t); 945 prf->obj = mlx5_devx_cmd_create_flex_parser(priv->sh->cdev->ctx, &node); 946 if (!prf->obj) { 947 DRV_LOG(ERR, "Failed to create flex parser node object."); 948 return (rte_errno == 0) ? -ENODEV : -rte_errno; 949 } 950 prf->num = 2; 951 ret = mlx5_devx_cmd_query_parse_samples(prf->obj, ids, prf->num); 952 if (ret) { 953 DRV_LOG(ERR, "Failed to query sample IDs."); 954 return (rte_errno == 0) ? -ENODEV : -rte_errno; 955 } 956 prf->offset[0] = 0x0; 957 prf->offset[1] = sizeof(uint32_t); 958 prf->ids[0] = ids[0]; 959 prf->ids[1] = ids[1]; 960 return 0; 961 } 962 963 /* 964 * Destroy the flex parser node, including the parser itself, input / output 965 * arcs and DW samples. Resources could be reused then. 966 * 967 * @param dev 968 * Pointer to Ethernet device structure. 969 */ 970 static void 971 mlx5_flex_parser_ecpri_release(struct rte_eth_dev *dev) 972 { 973 struct mlx5_priv *priv = dev->data->dev_private; 974 struct mlx5_ecpri_parser_profile *prf = &priv->sh->ecpri_parser; 975 976 if (prf->obj) 977 mlx5_devx_cmd_destroy(prf->obj); 978 prf->obj = NULL; 979 } 980 981 uint32_t 982 mlx5_get_supported_sw_parsing_offloads(const struct mlx5_hca_attr *attr) 983 { 984 uint32_t sw_parsing_offloads = 0; 985 986 if (attr->swp) { 987 sw_parsing_offloads |= MLX5_SW_PARSING_CAP; 988 if (attr->swp_csum) 989 sw_parsing_offloads |= MLX5_SW_PARSING_CSUM_CAP; 990 991 if (attr->swp_lso) 992 sw_parsing_offloads |= MLX5_SW_PARSING_TSO_CAP; 993 } 994 return sw_parsing_offloads; 995 } 996 997 uint32_t 998 mlx5_get_supported_tunneling_offloads(const struct mlx5_hca_attr *attr) 999 { 1000 uint32_t tn_offloads = 0; 1001 1002 if (attr->tunnel_stateless_vxlan) 1003 tn_offloads |= MLX5_TUNNELED_OFFLOADS_VXLAN_CAP; 1004 if (attr->tunnel_stateless_gre) 1005 tn_offloads |= MLX5_TUNNELED_OFFLOADS_GRE_CAP; 1006 if (attr->tunnel_stateless_geneve_rx) 1007 tn_offloads |= MLX5_TUNNELED_OFFLOADS_GENEVE_CAP; 1008 return tn_offloads; 1009 } 1010 1011 /* Fill all fields of UAR structure. */ 1012 static int 1013 mlx5_rxtx_uars_prepare(struct mlx5_dev_ctx_shared *sh) 1014 { 1015 int ret; 1016 1017 ret = mlx5_devx_uar_prepare(sh->cdev, &sh->tx_uar); 1018 if (ret) { 1019 DRV_LOG(ERR, "Failed to prepare Tx DevX UAR."); 1020 return -rte_errno; 1021 } 1022 MLX5_ASSERT(sh->tx_uar.obj); 1023 MLX5_ASSERT(mlx5_os_get_devx_uar_base_addr(sh->tx_uar.obj)); 1024 ret = mlx5_devx_uar_prepare(sh->cdev, &sh->rx_uar); 1025 if (ret) { 1026 DRV_LOG(ERR, "Failed to prepare Rx DevX UAR."); 1027 mlx5_devx_uar_release(&sh->tx_uar); 1028 return -rte_errno; 1029 } 1030 MLX5_ASSERT(sh->rx_uar.obj); 1031 MLX5_ASSERT(mlx5_os_get_devx_uar_base_addr(sh->rx_uar.obj)); 1032 return 0; 1033 } 1034 1035 static void 1036 mlx5_rxtx_uars_release(struct mlx5_dev_ctx_shared *sh) 1037 { 1038 mlx5_devx_uar_release(&sh->rx_uar); 1039 mlx5_devx_uar_release(&sh->tx_uar); 1040 } 1041 1042 /** 1043 * rte_mempool_walk() callback to unregister Rx mempools. 1044 * It used when implicit mempool registration is disabled. 1045 * 1046 * @param mp 1047 * The mempool being walked. 1048 * @param arg 1049 * Pointer to the device shared context. 1050 */ 1051 static void 1052 mlx5_dev_ctx_shared_rx_mempool_unregister_cb(struct rte_mempool *mp, void *arg) 1053 { 1054 struct mlx5_dev_ctx_shared *sh = arg; 1055 1056 mlx5_dev_mempool_unregister(sh->cdev, mp); 1057 } 1058 1059 /** 1060 * Callback used when implicit mempool registration is disabled 1061 * in order to track Rx mempool destruction. 1062 * 1063 * @param event 1064 * Mempool life cycle event. 1065 * @param mp 1066 * An Rx mempool registered explicitly when the port is started. 1067 * @param arg 1068 * Pointer to a device shared context. 1069 */ 1070 static void 1071 mlx5_dev_ctx_shared_rx_mempool_event_cb(enum rte_mempool_event event, 1072 struct rte_mempool *mp, void *arg) 1073 { 1074 struct mlx5_dev_ctx_shared *sh = arg; 1075 1076 if (event == RTE_MEMPOOL_EVENT_DESTROY) 1077 mlx5_dev_mempool_unregister(sh->cdev, mp); 1078 } 1079 1080 int 1081 mlx5_dev_ctx_shared_mempool_subscribe(struct rte_eth_dev *dev) 1082 { 1083 struct mlx5_priv *priv = dev->data->dev_private; 1084 struct mlx5_dev_ctx_shared *sh = priv->sh; 1085 int ret; 1086 1087 /* Check if we only need to track Rx mempool destruction. */ 1088 if (!sh->cdev->config.mr_mempool_reg_en) { 1089 ret = rte_mempool_event_callback_register 1090 (mlx5_dev_ctx_shared_rx_mempool_event_cb, sh); 1091 return ret == 0 || rte_errno == EEXIST ? 0 : ret; 1092 } 1093 return mlx5_dev_mempool_subscribe(sh->cdev); 1094 } 1095 1096 /** 1097 * Set up multiple TISs with different affinities according to 1098 * number of bonding ports 1099 * 1100 * @param priv 1101 * Pointer of shared context. 1102 * 1103 * @return 1104 * Zero on success, -1 otherwise. 1105 */ 1106 static int 1107 mlx5_setup_tis(struct mlx5_dev_ctx_shared *sh) 1108 { 1109 int i; 1110 struct mlx5_devx_lag_context lag_ctx = { 0 }; 1111 struct mlx5_devx_tis_attr tis_attr = { 0 }; 1112 1113 tis_attr.transport_domain = sh->td->id; 1114 if (sh->bond.n_port) { 1115 if (!mlx5_devx_cmd_query_lag(sh->cdev->ctx, &lag_ctx)) { 1116 sh->lag.tx_remap_affinity[0] = 1117 lag_ctx.tx_remap_affinity_1; 1118 sh->lag.tx_remap_affinity[1] = 1119 lag_ctx.tx_remap_affinity_2; 1120 sh->lag.affinity_mode = lag_ctx.port_select_mode; 1121 } else { 1122 DRV_LOG(ERR, "Failed to query lag affinity."); 1123 return -1; 1124 } 1125 if (sh->lag.affinity_mode == MLX5_LAG_MODE_TIS) { 1126 for (i = 0; i < sh->bond.n_port; i++) { 1127 tis_attr.lag_tx_port_affinity = 1128 MLX5_IFC_LAG_MAP_TIS_AFFINITY(i, 1129 sh->bond.n_port); 1130 sh->tis[i] = mlx5_devx_cmd_create_tis(sh->cdev->ctx, 1131 &tis_attr); 1132 if (!sh->tis[i]) { 1133 DRV_LOG(ERR, "Failed to TIS %d/%d for bonding device" 1134 " %s.", i, sh->bond.n_port, 1135 sh->ibdev_name); 1136 return -1; 1137 } 1138 } 1139 DRV_LOG(DEBUG, "LAG number of ports : %d, affinity_1 & 2 : pf%d & %d.\n", 1140 sh->bond.n_port, lag_ctx.tx_remap_affinity_1, 1141 lag_ctx.tx_remap_affinity_2); 1142 return 0; 1143 } 1144 if (sh->lag.affinity_mode == MLX5_LAG_MODE_HASH) 1145 DRV_LOG(INFO, "Device %s enabled HW hash based LAG.", 1146 sh->ibdev_name); 1147 } 1148 tis_attr.lag_tx_port_affinity = 0; 1149 sh->tis[0] = mlx5_devx_cmd_create_tis(sh->cdev->ctx, &tis_attr); 1150 if (!sh->tis[0]) { 1151 DRV_LOG(ERR, "Failed to TIS 0 for bonding device" 1152 " %s.", sh->ibdev_name); 1153 return -1; 1154 } 1155 return 0; 1156 } 1157 1158 /** 1159 * Verify and store value for share device argument. 1160 * 1161 * @param[in] key 1162 * Key argument to verify. 1163 * @param[in] val 1164 * Value associated with key. 1165 * @param opaque 1166 * User data. 1167 * 1168 * @return 1169 * 0 on success, a negative errno value otherwise and rte_errno is set. 1170 */ 1171 static int 1172 mlx5_dev_args_check_handler(const char *key, const char *val, void *opaque) 1173 { 1174 struct mlx5_sh_config *config = opaque; 1175 signed long tmp; 1176 1177 errno = 0; 1178 tmp = strtol(val, NULL, 0); 1179 if (errno) { 1180 rte_errno = errno; 1181 DRV_LOG(WARNING, "%s: \"%s\" is not a valid integer", key, val); 1182 return -rte_errno; 1183 } 1184 if (tmp < 0 && strcmp(MLX5_TX_PP, key) && strcmp(MLX5_TX_SKEW, key)) { 1185 /* Negative values are acceptable for some keys only. */ 1186 rte_errno = EINVAL; 1187 DRV_LOG(WARNING, "%s: invalid negative value \"%s\"", key, val); 1188 return -rte_errno; 1189 } 1190 if (strcmp(MLX5_TX_PP, key) == 0) { 1191 unsigned long mod = tmp >= 0 ? tmp : -tmp; 1192 1193 if (!mod) { 1194 DRV_LOG(ERR, "Zero Tx packet pacing parameter."); 1195 rte_errno = EINVAL; 1196 return -rte_errno; 1197 } 1198 config->tx_pp = tmp; 1199 } else if (strcmp(MLX5_TX_SKEW, key) == 0) { 1200 config->tx_skew = tmp; 1201 } else if (strcmp(MLX5_L3_VXLAN_EN, key) == 0) { 1202 config->l3_vxlan_en = !!tmp; 1203 } else if (strcmp(MLX5_VF_NL_EN, key) == 0) { 1204 config->vf_nl_en = !!tmp; 1205 } else if (strcmp(MLX5_DV_ESW_EN, key) == 0) { 1206 config->dv_esw_en = !!tmp; 1207 } else if (strcmp(MLX5_DV_FLOW_EN, key) == 0) { 1208 if (tmp > 2) { 1209 DRV_LOG(ERR, "Invalid %s parameter.", key); 1210 rte_errno = EINVAL; 1211 return -rte_errno; 1212 } 1213 config->dv_flow_en = tmp; 1214 } else if (strcmp(MLX5_DV_XMETA_EN, key) == 0) { 1215 if (tmp != MLX5_XMETA_MODE_LEGACY && 1216 tmp != MLX5_XMETA_MODE_META16 && 1217 tmp != MLX5_XMETA_MODE_META32 && 1218 tmp != MLX5_XMETA_MODE_MISS_INFO) { 1219 DRV_LOG(ERR, "Invalid extensive metadata parameter."); 1220 rte_errno = EINVAL; 1221 return -rte_errno; 1222 } 1223 if (tmp != MLX5_XMETA_MODE_MISS_INFO) 1224 config->dv_xmeta_en = tmp; 1225 else 1226 config->dv_miss_info = 1; 1227 } else if (strcmp(MLX5_LACP_BY_USER, key) == 0) { 1228 config->lacp_by_user = !!tmp; 1229 } else if (strcmp(MLX5_RECLAIM_MEM, key) == 0) { 1230 if (tmp != MLX5_RCM_NONE && 1231 tmp != MLX5_RCM_LIGHT && 1232 tmp != MLX5_RCM_AGGR) { 1233 DRV_LOG(ERR, "Unrecognize %s: \"%s\"", key, val); 1234 rte_errno = EINVAL; 1235 return -rte_errno; 1236 } 1237 config->reclaim_mode = tmp; 1238 } else if (strcmp(MLX5_DECAP_EN, key) == 0) { 1239 config->decap_en = !!tmp; 1240 } else if (strcmp(MLX5_ALLOW_DUPLICATE_PATTERN, key) == 0) { 1241 config->allow_duplicate_pattern = !!tmp; 1242 } 1243 return 0; 1244 } 1245 1246 /** 1247 * Parse user device parameters and adjust them according to device 1248 * capabilities. 1249 * 1250 * @param sh 1251 * Pointer to shared device context. 1252 * @param mkvlist 1253 * Pointer to mlx5 kvargs control, can be NULL if there is no devargs. 1254 * @param config 1255 * Pointer to shared device configuration structure. 1256 * 1257 * @return 1258 * 0 on success, a negative errno value otherwise and rte_errno is set. 1259 */ 1260 static int 1261 mlx5_shared_dev_ctx_args_config(struct mlx5_dev_ctx_shared *sh, 1262 struct mlx5_kvargs_ctrl *mkvlist, 1263 struct mlx5_sh_config *config) 1264 { 1265 const char **params = (const char *[]){ 1266 MLX5_TX_PP, 1267 MLX5_TX_SKEW, 1268 MLX5_L3_VXLAN_EN, 1269 MLX5_VF_NL_EN, 1270 MLX5_DV_ESW_EN, 1271 MLX5_DV_FLOW_EN, 1272 MLX5_DV_XMETA_EN, 1273 MLX5_LACP_BY_USER, 1274 MLX5_RECLAIM_MEM, 1275 MLX5_DECAP_EN, 1276 MLX5_ALLOW_DUPLICATE_PATTERN, 1277 NULL, 1278 }; 1279 int ret = 0; 1280 1281 /* Default configuration. */ 1282 memset(config, 0, sizeof(*config)); 1283 config->vf_nl_en = 1; 1284 config->dv_esw_en = 1; 1285 config->dv_flow_en = 1; 1286 config->decap_en = 1; 1287 config->allow_duplicate_pattern = 1; 1288 if (mkvlist != NULL) { 1289 /* Process parameters. */ 1290 ret = mlx5_kvargs_process(mkvlist, params, 1291 mlx5_dev_args_check_handler, config); 1292 if (ret) { 1293 DRV_LOG(ERR, "Failed to process device arguments: %s", 1294 strerror(rte_errno)); 1295 return -rte_errno; 1296 } 1297 } 1298 /* Adjust parameters according to device capabilities. */ 1299 if (config->dv_flow_en && !sh->dev_cap.dv_flow_en) { 1300 DRV_LOG(WARNING, "DV flow is not supported."); 1301 config->dv_flow_en = 0; 1302 } 1303 if (config->dv_esw_en && !sh->dev_cap.dv_esw_en) { 1304 DRV_LOG(DEBUG, "E-Switch DV flow is not supported."); 1305 config->dv_esw_en = 0; 1306 } 1307 if (config->dv_esw_en && !config->dv_flow_en) { 1308 DRV_LOG(DEBUG, 1309 "E-Switch DV flow is supported only when DV flow is enabled."); 1310 config->dv_esw_en = 0; 1311 } 1312 if (config->dv_miss_info && config->dv_esw_en) 1313 config->dv_xmeta_en = MLX5_XMETA_MODE_META16; 1314 if (!config->dv_esw_en && 1315 config->dv_xmeta_en != MLX5_XMETA_MODE_LEGACY) { 1316 DRV_LOG(WARNING, 1317 "Metadata mode %u is not supported (no E-Switch).", 1318 config->dv_xmeta_en); 1319 config->dv_xmeta_en = MLX5_XMETA_MODE_LEGACY; 1320 } 1321 if (config->tx_pp && !sh->dev_cap.txpp_en) { 1322 DRV_LOG(ERR, "Packet pacing is not supported."); 1323 rte_errno = ENODEV; 1324 return -rte_errno; 1325 } 1326 if (!config->tx_pp && config->tx_skew) { 1327 DRV_LOG(WARNING, 1328 "\"tx_skew\" doesn't affect without \"tx_pp\"."); 1329 } 1330 /* Check for LRO support. */ 1331 if (mlx5_devx_obj_ops_en(sh) && sh->cdev->config.hca_attr.lro_cap) { 1332 /* TBD check tunnel lro caps. */ 1333 config->lro_allowed = 1; 1334 DRV_LOG(DEBUG, "LRO is allowed."); 1335 DRV_LOG(DEBUG, 1336 "LRO minimal size of TCP segment required for coalescing is %d bytes.", 1337 sh->cdev->config.hca_attr.lro_min_mss_size); 1338 } 1339 /* 1340 * If HW has bug working with tunnel packet decapsulation and scatter 1341 * FCS, and decapsulation is needed, clear the hw_fcs_strip bit. 1342 * Then RTE_ETH_RX_OFFLOAD_KEEP_CRC bit will not be set anymore. 1343 */ 1344 if (sh->dev_cap.scatter_fcs_w_decap_disable && sh->config.decap_en) 1345 config->hw_fcs_strip = 0; 1346 else 1347 config->hw_fcs_strip = sh->dev_cap.hw_fcs_strip; 1348 DRV_LOG(DEBUG, "FCS stripping configuration is %ssupported", 1349 (config->hw_fcs_strip ? "" : "not ")); 1350 DRV_LOG(DEBUG, "\"tx_pp\" is %d.", config->tx_pp); 1351 DRV_LOG(DEBUG, "\"tx_skew\" is %d.", config->tx_skew); 1352 DRV_LOG(DEBUG, "\"reclaim_mode\" is %u.", config->reclaim_mode); 1353 DRV_LOG(DEBUG, "\"dv_esw_en\" is %u.", config->dv_esw_en); 1354 DRV_LOG(DEBUG, "\"dv_flow_en\" is %u.", config->dv_flow_en); 1355 DRV_LOG(DEBUG, "\"dv_xmeta_en\" is %u.", config->dv_xmeta_en); 1356 DRV_LOG(DEBUG, "\"dv_miss_info\" is %u.", config->dv_miss_info); 1357 DRV_LOG(DEBUG, "\"l3_vxlan_en\" is %u.", config->l3_vxlan_en); 1358 DRV_LOG(DEBUG, "\"vf_nl_en\" is %u.", config->vf_nl_en); 1359 DRV_LOG(DEBUG, "\"lacp_by_user\" is %u.", config->lacp_by_user); 1360 DRV_LOG(DEBUG, "\"decap_en\" is %u.", config->decap_en); 1361 DRV_LOG(DEBUG, "\"allow_duplicate_pattern\" is %u.", 1362 config->allow_duplicate_pattern); 1363 return 0; 1364 } 1365 1366 /** 1367 * Configure realtime timestamp format. 1368 * 1369 * @param sh 1370 * Pointer to mlx5_dev_ctx_shared object. 1371 * @param hca_attr 1372 * Pointer to DevX HCA capabilities structure. 1373 */ 1374 void 1375 mlx5_rt_timestamp_config(struct mlx5_dev_ctx_shared *sh, 1376 struct mlx5_hca_attr *hca_attr) 1377 { 1378 uint32_t dw_cnt = MLX5_ST_SZ_DW(register_mtutc); 1379 uint32_t reg[dw_cnt]; 1380 int ret = ENOTSUP; 1381 1382 if (hca_attr->access_register_user) 1383 ret = mlx5_devx_cmd_register_read(sh->cdev->ctx, 1384 MLX5_REGISTER_ID_MTUTC, 0, 1385 reg, dw_cnt); 1386 if (!ret) { 1387 uint32_t ts_mode; 1388 1389 /* MTUTC register is read successfully. */ 1390 ts_mode = MLX5_GET(register_mtutc, reg, time_stamp_mode); 1391 if (ts_mode == MLX5_MTUTC_TIMESTAMP_MODE_REAL_TIME) 1392 sh->dev_cap.rt_timestamp = 1; 1393 } else { 1394 /* Kernel does not support register reading. */ 1395 if (hca_attr->dev_freq_khz == (NS_PER_S / MS_PER_S)) 1396 sh->dev_cap.rt_timestamp = 1; 1397 } 1398 } 1399 1400 /** 1401 * Allocate shared device context. If there is multiport device the 1402 * master and representors will share this context, if there is single 1403 * port dedicated device, the context will be used by only given 1404 * port due to unification. 1405 * 1406 * Routine first searches the context for the specified device name, 1407 * if found the shared context assumed and reference counter is incremented. 1408 * If no context found the new one is created and initialized with specified 1409 * device context and parameters. 1410 * 1411 * @param[in] spawn 1412 * Pointer to the device attributes (name, port, etc). 1413 * @param mkvlist 1414 * Pointer to mlx5 kvargs control, can be NULL if there is no devargs. 1415 * 1416 * @return 1417 * Pointer to mlx5_dev_ctx_shared object on success, 1418 * otherwise NULL and rte_errno is set. 1419 */ 1420 struct mlx5_dev_ctx_shared * 1421 mlx5_alloc_shared_dev_ctx(const struct mlx5_dev_spawn_data *spawn, 1422 struct mlx5_kvargs_ctrl *mkvlist) 1423 { 1424 struct mlx5_dev_ctx_shared *sh; 1425 int err = 0; 1426 uint32_t i; 1427 1428 MLX5_ASSERT(spawn); 1429 /* Secondary process should not create the shared context. */ 1430 MLX5_ASSERT(rte_eal_process_type() == RTE_PROC_PRIMARY); 1431 pthread_mutex_lock(&mlx5_dev_ctx_list_mutex); 1432 /* Search for IB context by device name. */ 1433 LIST_FOREACH(sh, &mlx5_dev_ctx_list, next) { 1434 if (!strcmp(sh->ibdev_name, spawn->phys_dev_name)) { 1435 sh->refcnt++; 1436 goto exit; 1437 } 1438 } 1439 /* No device found, we have to create new shared context. */ 1440 MLX5_ASSERT(spawn->max_port); 1441 sh = mlx5_malloc(MLX5_MEM_ZERO | MLX5_MEM_RTE, 1442 sizeof(struct mlx5_dev_ctx_shared) + 1443 spawn->max_port * sizeof(struct mlx5_dev_shared_port), 1444 RTE_CACHE_LINE_SIZE, SOCKET_ID_ANY); 1445 if (!sh) { 1446 DRV_LOG(ERR, "Shared context allocation failure."); 1447 rte_errno = ENOMEM; 1448 goto exit; 1449 } 1450 pthread_mutex_init(&sh->txpp.mutex, NULL); 1451 sh->numa_node = spawn->cdev->dev->numa_node; 1452 sh->cdev = spawn->cdev; 1453 sh->esw_mode = !!(spawn->info.master || spawn->info.representor); 1454 if (spawn->bond_info) 1455 sh->bond = *spawn->bond_info; 1456 err = mlx5_os_capabilities_prepare(sh); 1457 if (err) { 1458 DRV_LOG(ERR, "Fail to configure device capabilities."); 1459 goto error; 1460 } 1461 err = mlx5_shared_dev_ctx_args_config(sh, mkvlist, &sh->config); 1462 if (err) { 1463 DRV_LOG(ERR, "Failed to process device configure: %s", 1464 strerror(rte_errno)); 1465 goto error; 1466 } 1467 sh->refcnt = 1; 1468 sh->max_port = spawn->max_port; 1469 strncpy(sh->ibdev_name, mlx5_os_get_ctx_device_name(sh->cdev->ctx), 1470 sizeof(sh->ibdev_name) - 1); 1471 strncpy(sh->ibdev_path, mlx5_os_get_ctx_device_path(sh->cdev->ctx), 1472 sizeof(sh->ibdev_path) - 1); 1473 /* 1474 * Setting port_id to max unallowed value means there is no interrupt 1475 * subhandler installed for the given port index i. 1476 */ 1477 for (i = 0; i < sh->max_port; i++) { 1478 sh->port[i].ih_port_id = RTE_MAX_ETHPORTS; 1479 sh->port[i].devx_ih_port_id = RTE_MAX_ETHPORTS; 1480 sh->port[i].nl_ih_port_id = RTE_MAX_ETHPORTS; 1481 } 1482 if (sh->cdev->config.devx) { 1483 sh->td = mlx5_devx_cmd_create_td(sh->cdev->ctx); 1484 if (!sh->td) { 1485 DRV_LOG(ERR, "TD allocation failure"); 1486 rte_errno = ENOMEM; 1487 goto error; 1488 } 1489 if (mlx5_setup_tis(sh)) { 1490 DRV_LOG(ERR, "TIS allocation failure"); 1491 rte_errno = ENOMEM; 1492 goto error; 1493 } 1494 err = mlx5_rxtx_uars_prepare(sh); 1495 if (err) 1496 goto error; 1497 #ifndef RTE_ARCH_64 1498 } else { 1499 /* Initialize UAR access locks for 32bit implementations. */ 1500 rte_spinlock_init(&sh->uar_lock_cq); 1501 for (i = 0; i < MLX5_UAR_PAGE_NUM_MAX; i++) 1502 rte_spinlock_init(&sh->uar_lock[i]); 1503 #endif 1504 } 1505 mlx5_os_dev_shared_handler_install(sh); 1506 if (LIST_EMPTY(&mlx5_dev_ctx_list)) { 1507 err = mlx5_flow_os_init_workspace_once(); 1508 if (err) 1509 goto error; 1510 } 1511 mlx5_flow_aging_init(sh); 1512 mlx5_flow_counters_mng_init(sh); 1513 mlx5_flow_ipool_create(sh); 1514 /* Add context to the global device list. */ 1515 LIST_INSERT_HEAD(&mlx5_dev_ctx_list, sh, next); 1516 rte_spinlock_init(&sh->geneve_tlv_opt_sl); 1517 exit: 1518 pthread_mutex_unlock(&mlx5_dev_ctx_list_mutex); 1519 return sh; 1520 error: 1521 err = rte_errno; 1522 pthread_mutex_destroy(&sh->txpp.mutex); 1523 pthread_mutex_unlock(&mlx5_dev_ctx_list_mutex); 1524 MLX5_ASSERT(sh); 1525 mlx5_rxtx_uars_release(sh); 1526 i = 0; 1527 do { 1528 if (sh->tis[i]) 1529 claim_zero(mlx5_devx_cmd_destroy(sh->tis[i])); 1530 } while (++i < (uint32_t)sh->bond.n_port); 1531 if (sh->td) 1532 claim_zero(mlx5_devx_cmd_destroy(sh->td)); 1533 mlx5_free(sh); 1534 rte_errno = err; 1535 return NULL; 1536 } 1537 1538 /** 1539 * Create LWM event_channel and interrupt handle for shared device 1540 * context. All rxqs sharing the device context share the event_channel. 1541 * A callback is registered in interrupt thread to receive the LWM event. 1542 * 1543 * @param[in] priv 1544 * Pointer to mlx5_priv instance. 1545 * 1546 * @return 1547 * 0 on success, negative with rte_errno set. 1548 */ 1549 int 1550 mlx5_lwm_setup(struct mlx5_priv *priv) 1551 { 1552 int fd_lwm; 1553 1554 pthread_mutex_init(&priv->sh->lwm_config_lock, NULL); 1555 priv->sh->devx_channel_lwm = mlx5_os_devx_create_event_channel 1556 (priv->sh->cdev->ctx, 1557 MLX5DV_DEVX_CREATE_EVENT_CHANNEL_FLAGS_OMIT_EV_DATA); 1558 if (!priv->sh->devx_channel_lwm) 1559 goto err; 1560 fd_lwm = mlx5_os_get_devx_channel_fd(priv->sh->devx_channel_lwm); 1561 priv->sh->intr_handle_lwm = mlx5_os_interrupt_handler_create 1562 (RTE_INTR_INSTANCE_F_SHARED, true, 1563 fd_lwm, mlx5_dev_interrupt_handler_lwm, priv); 1564 if (!priv->sh->intr_handle_lwm) 1565 goto err; 1566 return 0; 1567 err: 1568 if (priv->sh->devx_channel_lwm) { 1569 mlx5_os_devx_destroy_event_channel 1570 (priv->sh->devx_channel_lwm); 1571 priv->sh->devx_channel_lwm = NULL; 1572 } 1573 pthread_mutex_destroy(&priv->sh->lwm_config_lock); 1574 return -rte_errno; 1575 } 1576 1577 /** 1578 * Destroy LWM event_channel and interrupt handle for shared device 1579 * context before free this context. The interrupt handler is also 1580 * unregistered. 1581 * 1582 * @param[in] sh 1583 * Pointer to shared device context. 1584 */ 1585 void 1586 mlx5_lwm_unset(struct mlx5_dev_ctx_shared *sh) 1587 { 1588 if (sh->intr_handle_lwm) { 1589 mlx5_os_interrupt_handler_destroy(sh->intr_handle_lwm, 1590 mlx5_dev_interrupt_handler_lwm, (void *)-1); 1591 sh->intr_handle_lwm = NULL; 1592 } 1593 if (sh->devx_channel_lwm) { 1594 mlx5_os_devx_destroy_event_channel 1595 (sh->devx_channel_lwm); 1596 sh->devx_channel_lwm = NULL; 1597 } 1598 pthread_mutex_destroy(&sh->lwm_config_lock); 1599 } 1600 1601 /** 1602 * Free shared IB device context. Decrement counter and if zero free 1603 * all allocated resources and close handles. 1604 * 1605 * @param[in] sh 1606 * Pointer to mlx5_dev_ctx_shared object to free 1607 */ 1608 void 1609 mlx5_free_shared_dev_ctx(struct mlx5_dev_ctx_shared *sh) 1610 { 1611 int ret; 1612 int i = 0; 1613 1614 pthread_mutex_lock(&mlx5_dev_ctx_list_mutex); 1615 #ifdef RTE_LIBRTE_MLX5_DEBUG 1616 /* Check the object presence in the list. */ 1617 struct mlx5_dev_ctx_shared *lctx; 1618 1619 LIST_FOREACH(lctx, &mlx5_dev_ctx_list, next) 1620 if (lctx == sh) 1621 break; 1622 MLX5_ASSERT(lctx); 1623 if (lctx != sh) { 1624 DRV_LOG(ERR, "Freeing non-existing shared IB context"); 1625 goto exit; 1626 } 1627 #endif 1628 MLX5_ASSERT(sh); 1629 MLX5_ASSERT(sh->refcnt); 1630 /* Secondary process should not free the shared context. */ 1631 MLX5_ASSERT(rte_eal_process_type() == RTE_PROC_PRIMARY); 1632 if (--sh->refcnt) 1633 goto exit; 1634 /* Stop watching for mempool events and unregister all mempools. */ 1635 if (!sh->cdev->config.mr_mempool_reg_en) { 1636 ret = rte_mempool_event_callback_unregister 1637 (mlx5_dev_ctx_shared_rx_mempool_event_cb, sh); 1638 if (ret == 0) 1639 rte_mempool_walk 1640 (mlx5_dev_ctx_shared_rx_mempool_unregister_cb, sh); 1641 } 1642 /* Remove context from the global device list. */ 1643 LIST_REMOVE(sh, next); 1644 /* Release resources on the last device removal. */ 1645 if (LIST_EMPTY(&mlx5_dev_ctx_list)) { 1646 mlx5_os_net_cleanup(); 1647 mlx5_flow_os_release_workspace(); 1648 } 1649 pthread_mutex_unlock(&mlx5_dev_ctx_list_mutex); 1650 if (sh->flex_parsers_dv) { 1651 mlx5_list_destroy(sh->flex_parsers_dv); 1652 sh->flex_parsers_dv = NULL; 1653 } 1654 /* 1655 * Ensure there is no async event handler installed. 1656 * Only primary process handles async device events. 1657 **/ 1658 mlx5_flow_counters_mng_close(sh); 1659 if (sh->ct_mng) 1660 mlx5_flow_aso_ct_mng_close(sh); 1661 if (sh->aso_age_mng) { 1662 mlx5_flow_aso_age_mng_close(sh); 1663 sh->aso_age_mng = NULL; 1664 } 1665 if (sh->mtrmng) 1666 mlx5_aso_flow_mtrs_mng_close(sh); 1667 mlx5_flow_ipool_destroy(sh); 1668 mlx5_os_dev_shared_handler_uninstall(sh); 1669 mlx5_rxtx_uars_release(sh); 1670 do { 1671 if (sh->tis[i]) 1672 claim_zero(mlx5_devx_cmd_destroy(sh->tis[i])); 1673 } while (++i < sh->bond.n_port); 1674 if (sh->td) 1675 claim_zero(mlx5_devx_cmd_destroy(sh->td)); 1676 MLX5_ASSERT(sh->geneve_tlv_option_resource == NULL); 1677 pthread_mutex_destroy(&sh->txpp.mutex); 1678 mlx5_lwm_unset(sh); 1679 mlx5_free(sh); 1680 return; 1681 exit: 1682 pthread_mutex_unlock(&mlx5_dev_ctx_list_mutex); 1683 } 1684 1685 /** 1686 * Destroy table hash list. 1687 * 1688 * @param[in] priv 1689 * Pointer to the private device data structure. 1690 */ 1691 void 1692 mlx5_free_table_hash_list(struct mlx5_priv *priv) 1693 { 1694 struct mlx5_dev_ctx_shared *sh = priv->sh; 1695 struct mlx5_hlist **tbls = (priv->sh->config.dv_flow_en == 2) ? 1696 &sh->groups : &sh->flow_tbls; 1697 if (*tbls == NULL) 1698 return; 1699 mlx5_hlist_destroy(*tbls); 1700 *tbls = NULL; 1701 } 1702 1703 #if defined(HAVE_IBV_FLOW_DV_SUPPORT) || !defined(HAVE_INFINIBAND_VERBS_H) 1704 /** 1705 * Allocate HW steering group hash list. 1706 * 1707 * @param[in] priv 1708 * Pointer to the private device data structure. 1709 */ 1710 static int 1711 mlx5_alloc_hw_group_hash_list(struct mlx5_priv *priv) 1712 { 1713 int err = 0; 1714 struct mlx5_dev_ctx_shared *sh = priv->sh; 1715 char s[MLX5_NAME_SIZE]; 1716 1717 MLX5_ASSERT(sh); 1718 snprintf(s, sizeof(s), "%s_flow_groups", priv->sh->ibdev_name); 1719 sh->groups = mlx5_hlist_create 1720 (s, MLX5_FLOW_TABLE_HLIST_ARRAY_SIZE, 1721 false, true, sh, 1722 flow_hw_grp_create_cb, 1723 flow_hw_grp_match_cb, 1724 flow_hw_grp_remove_cb, 1725 flow_hw_grp_clone_cb, 1726 flow_hw_grp_clone_free_cb); 1727 if (!sh->groups) { 1728 DRV_LOG(ERR, "flow groups with hash creation failed."); 1729 err = ENOMEM; 1730 } 1731 return err; 1732 } 1733 #endif 1734 1735 1736 /** 1737 * Initialize flow table hash list and create the root tables entry 1738 * for each domain. 1739 * 1740 * @param[in] priv 1741 * Pointer to the private device data structure. 1742 * 1743 * @return 1744 * Zero on success, positive error code otherwise. 1745 */ 1746 int 1747 mlx5_alloc_table_hash_list(struct mlx5_priv *priv __rte_unused) 1748 { 1749 int err = 0; 1750 1751 /* Tables are only used in DV and DR modes. */ 1752 #if defined(HAVE_IBV_FLOW_DV_SUPPORT) || !defined(HAVE_INFINIBAND_VERBS_H) 1753 struct mlx5_dev_ctx_shared *sh = priv->sh; 1754 char s[MLX5_NAME_SIZE]; 1755 1756 if (priv->sh->config.dv_flow_en == 2) 1757 return mlx5_alloc_hw_group_hash_list(priv); 1758 MLX5_ASSERT(sh); 1759 snprintf(s, sizeof(s), "%s_flow_table", priv->sh->ibdev_name); 1760 sh->flow_tbls = mlx5_hlist_create(s, MLX5_FLOW_TABLE_HLIST_ARRAY_SIZE, 1761 false, true, sh, 1762 flow_dv_tbl_create_cb, 1763 flow_dv_tbl_match_cb, 1764 flow_dv_tbl_remove_cb, 1765 flow_dv_tbl_clone_cb, 1766 flow_dv_tbl_clone_free_cb); 1767 if (!sh->flow_tbls) { 1768 DRV_LOG(ERR, "flow tables with hash creation failed."); 1769 err = ENOMEM; 1770 return err; 1771 } 1772 #ifndef HAVE_MLX5DV_DR 1773 struct rte_flow_error error; 1774 struct rte_eth_dev *dev = &rte_eth_devices[priv->dev_data->port_id]; 1775 1776 /* 1777 * In case we have not DR support, the zero tables should be created 1778 * because DV expect to see them even if they cannot be created by 1779 * RDMA-CORE. 1780 */ 1781 if (!flow_dv_tbl_resource_get(dev, 0, 0, 0, 0, 1782 NULL, 0, 1, 0, &error) || 1783 !flow_dv_tbl_resource_get(dev, 0, 1, 0, 0, 1784 NULL, 0, 1, 0, &error) || 1785 !flow_dv_tbl_resource_get(dev, 0, 0, 1, 0, 1786 NULL, 0, 1, 0, &error)) { 1787 err = ENOMEM; 1788 goto error; 1789 } 1790 return err; 1791 error: 1792 mlx5_free_table_hash_list(priv); 1793 #endif /* HAVE_MLX5DV_DR */ 1794 #endif 1795 return err; 1796 } 1797 1798 /** 1799 * Retrieve integer value from environment variable. 1800 * 1801 * @param[in] name 1802 * Environment variable name. 1803 * 1804 * @return 1805 * Integer value, 0 if the variable is not set. 1806 */ 1807 int 1808 mlx5_getenv_int(const char *name) 1809 { 1810 const char *val = getenv(name); 1811 1812 if (val == NULL) 1813 return 0; 1814 return atoi(val); 1815 } 1816 1817 /** 1818 * DPDK callback to add udp tunnel port 1819 * 1820 * @param[in] dev 1821 * A pointer to eth_dev 1822 * @param[in] udp_tunnel 1823 * A pointer to udp tunnel 1824 * 1825 * @return 1826 * 0 on valid udp ports and tunnels, -ENOTSUP otherwise. 1827 */ 1828 int 1829 mlx5_udp_tunnel_port_add(struct rte_eth_dev *dev __rte_unused, 1830 struct rte_eth_udp_tunnel *udp_tunnel) 1831 { 1832 MLX5_ASSERT(udp_tunnel != NULL); 1833 if (udp_tunnel->prot_type == RTE_ETH_TUNNEL_TYPE_VXLAN && 1834 udp_tunnel->udp_port == 4789) 1835 return 0; 1836 if (udp_tunnel->prot_type == RTE_ETH_TUNNEL_TYPE_VXLAN_GPE && 1837 udp_tunnel->udp_port == 4790) 1838 return 0; 1839 return -ENOTSUP; 1840 } 1841 1842 /** 1843 * Initialize process private data structure. 1844 * 1845 * @param dev 1846 * Pointer to Ethernet device structure. 1847 * 1848 * @return 1849 * 0 on success, a negative errno value otherwise and rte_errno is set. 1850 */ 1851 int 1852 mlx5_proc_priv_init(struct rte_eth_dev *dev) 1853 { 1854 struct mlx5_priv *priv = dev->data->dev_private; 1855 struct mlx5_proc_priv *ppriv; 1856 size_t ppriv_size; 1857 1858 mlx5_proc_priv_uninit(dev); 1859 /* 1860 * UAR register table follows the process private structure. BlueFlame 1861 * registers for Tx queues are stored in the table. 1862 */ 1863 ppriv_size = sizeof(struct mlx5_proc_priv) + 1864 priv->txqs_n * sizeof(struct mlx5_uar_data); 1865 ppriv = mlx5_malloc(MLX5_MEM_RTE | MLX5_MEM_ZERO, ppriv_size, 1866 RTE_CACHE_LINE_SIZE, dev->device->numa_node); 1867 if (!ppriv) { 1868 rte_errno = ENOMEM; 1869 return -rte_errno; 1870 } 1871 ppriv->uar_table_sz = priv->txqs_n; 1872 dev->process_private = ppriv; 1873 if (rte_eal_process_type() == RTE_PROC_PRIMARY) 1874 priv->sh->pppriv = ppriv; 1875 return 0; 1876 } 1877 1878 /** 1879 * Un-initialize process private data structure. 1880 * 1881 * @param dev 1882 * Pointer to Ethernet device structure. 1883 */ 1884 void 1885 mlx5_proc_priv_uninit(struct rte_eth_dev *dev) 1886 { 1887 if (!dev->process_private) 1888 return; 1889 mlx5_free(dev->process_private); 1890 dev->process_private = NULL; 1891 } 1892 1893 /** 1894 * DPDK callback to close the device. 1895 * 1896 * Destroy all queues and objects, free memory. 1897 * 1898 * @param dev 1899 * Pointer to Ethernet device structure. 1900 */ 1901 int 1902 mlx5_dev_close(struct rte_eth_dev *dev) 1903 { 1904 struct mlx5_priv *priv = dev->data->dev_private; 1905 unsigned int i; 1906 int ret; 1907 1908 if (rte_eal_process_type() == RTE_PROC_SECONDARY) { 1909 /* Check if process_private released. */ 1910 if (!dev->process_private) 1911 return 0; 1912 mlx5_tx_uar_uninit_secondary(dev); 1913 mlx5_proc_priv_uninit(dev); 1914 rte_eth_dev_release_port(dev); 1915 return 0; 1916 } 1917 if (!priv->sh) 1918 return 0; 1919 DRV_LOG(DEBUG, "port %u closing device \"%s\"", 1920 dev->data->port_id, 1921 ((priv->sh->cdev->ctx != NULL) ? 1922 mlx5_os_get_ctx_device_name(priv->sh->cdev->ctx) : "")); 1923 /* 1924 * If default mreg copy action is removed at the stop stage, 1925 * the search will return none and nothing will be done anymore. 1926 */ 1927 mlx5_flow_stop_default(dev); 1928 mlx5_traffic_disable(dev); 1929 /* 1930 * If all the flows are already flushed in the device stop stage, 1931 * then this will return directly without any action. 1932 */ 1933 mlx5_flow_list_flush(dev, MLX5_FLOW_TYPE_GEN, true); 1934 mlx5_action_handle_flush(dev); 1935 mlx5_flow_meter_flush(dev, NULL); 1936 /* Prevent crashes when queues are still in use. */ 1937 dev->rx_pkt_burst = rte_eth_pkt_burst_dummy; 1938 dev->tx_pkt_burst = rte_eth_pkt_burst_dummy; 1939 rte_wmb(); 1940 /* Disable datapath on secondary process. */ 1941 mlx5_mp_os_req_stop_rxtx(dev); 1942 /* Free the eCPRI flex parser resource. */ 1943 mlx5_flex_parser_ecpri_release(dev); 1944 mlx5_flex_item_port_cleanup(dev); 1945 #if defined(HAVE_IBV_FLOW_DV_SUPPORT) || !defined(HAVE_INFINIBAND_VERBS_H) 1946 flow_hw_resource_release(dev); 1947 #endif 1948 if (priv->rxq_privs != NULL) { 1949 /* XXX race condition if mlx5_rx_burst() is still running. */ 1950 rte_delay_us_sleep(1000); 1951 for (i = 0; (i != priv->rxqs_n); ++i) 1952 mlx5_rxq_release(dev, i); 1953 priv->rxqs_n = 0; 1954 mlx5_free(priv->rxq_privs); 1955 priv->rxq_privs = NULL; 1956 } 1957 if (priv->txqs != NULL) { 1958 /* XXX race condition if mlx5_tx_burst() is still running. */ 1959 rte_delay_us_sleep(1000); 1960 for (i = 0; (i != priv->txqs_n); ++i) 1961 mlx5_txq_release(dev, i); 1962 priv->txqs_n = 0; 1963 priv->txqs = NULL; 1964 } 1965 mlx5_proc_priv_uninit(dev); 1966 if (priv->q_counters) { 1967 mlx5_devx_cmd_destroy(priv->q_counters); 1968 priv->q_counters = NULL; 1969 } 1970 if (priv->drop_queue.hrxq) 1971 mlx5_drop_action_destroy(dev); 1972 if (priv->mreg_cp_tbl) 1973 mlx5_hlist_destroy(priv->mreg_cp_tbl); 1974 mlx5_mprq_free_mp(dev); 1975 mlx5_os_free_shared_dr(priv); 1976 if (priv->rss_conf.rss_key != NULL) 1977 mlx5_free(priv->rss_conf.rss_key); 1978 if (priv->reta_idx != NULL) 1979 mlx5_free(priv->reta_idx); 1980 if (priv->sh->dev_cap.vf) 1981 mlx5_os_mac_addr_flush(dev); 1982 if (priv->nl_socket_route >= 0) 1983 close(priv->nl_socket_route); 1984 if (priv->nl_socket_rdma >= 0) 1985 close(priv->nl_socket_rdma); 1986 if (priv->vmwa_context) 1987 mlx5_vlan_vmwa_exit(priv->vmwa_context); 1988 ret = mlx5_hrxq_verify(dev); 1989 if (ret) 1990 DRV_LOG(WARNING, "port %u some hash Rx queue still remain", 1991 dev->data->port_id); 1992 ret = mlx5_ind_table_obj_verify(dev); 1993 if (ret) 1994 DRV_LOG(WARNING, "port %u some indirection table still remain", 1995 dev->data->port_id); 1996 ret = mlx5_rxq_obj_verify(dev); 1997 if (ret) 1998 DRV_LOG(WARNING, "port %u some Rx queue objects still remain", 1999 dev->data->port_id); 2000 ret = mlx5_ext_rxq_verify(dev); 2001 if (ret) 2002 DRV_LOG(WARNING, "Port %u some external RxQ still remain.", 2003 dev->data->port_id); 2004 ret = mlx5_rxq_verify(dev); 2005 if (ret) 2006 DRV_LOG(WARNING, "port %u some Rx queues still remain", 2007 dev->data->port_id); 2008 ret = mlx5_txq_obj_verify(dev); 2009 if (ret) 2010 DRV_LOG(WARNING, "port %u some Verbs Tx queue still remain", 2011 dev->data->port_id); 2012 ret = mlx5_txq_verify(dev); 2013 if (ret) 2014 DRV_LOG(WARNING, "port %u some Tx queues still remain", 2015 dev->data->port_id); 2016 ret = mlx5_flow_verify(dev); 2017 if (ret) 2018 DRV_LOG(WARNING, "port %u some flows still remain", 2019 dev->data->port_id); 2020 if (priv->hrxqs) 2021 mlx5_list_destroy(priv->hrxqs); 2022 mlx5_free(priv->ext_rxqs); 2023 /* 2024 * Free the shared context in last turn, because the cleanup 2025 * routines above may use some shared fields, like 2026 * mlx5_os_mac_addr_flush() uses ibdev_path for retrieving 2027 * ifindex if Netlink fails. 2028 */ 2029 mlx5_free_shared_dev_ctx(priv->sh); 2030 if (priv->domain_id != RTE_ETH_DEV_SWITCH_DOMAIN_ID_INVALID) { 2031 unsigned int c = 0; 2032 uint16_t port_id; 2033 2034 MLX5_ETH_FOREACH_DEV(port_id, dev->device) { 2035 struct mlx5_priv *opriv = 2036 rte_eth_devices[port_id].data->dev_private; 2037 2038 if (!opriv || 2039 opriv->domain_id != priv->domain_id || 2040 &rte_eth_devices[port_id] == dev) 2041 continue; 2042 ++c; 2043 break; 2044 } 2045 if (!c) 2046 claim_zero(rte_eth_switch_domain_free(priv->domain_id)); 2047 } 2048 memset(priv, 0, sizeof(*priv)); 2049 priv->domain_id = RTE_ETH_DEV_SWITCH_DOMAIN_ID_INVALID; 2050 /* 2051 * Reset mac_addrs to NULL such that it is not freed as part of 2052 * rte_eth_dev_release_port(). mac_addrs is part of dev_private so 2053 * it is freed when dev_private is freed. 2054 */ 2055 dev->data->mac_addrs = NULL; 2056 return 0; 2057 } 2058 2059 const struct eth_dev_ops mlx5_dev_ops = { 2060 .dev_configure = mlx5_dev_configure, 2061 .dev_start = mlx5_dev_start, 2062 .dev_stop = mlx5_dev_stop, 2063 .dev_set_link_down = mlx5_set_link_down, 2064 .dev_set_link_up = mlx5_set_link_up, 2065 .dev_close = mlx5_dev_close, 2066 .promiscuous_enable = mlx5_promiscuous_enable, 2067 .promiscuous_disable = mlx5_promiscuous_disable, 2068 .allmulticast_enable = mlx5_allmulticast_enable, 2069 .allmulticast_disable = mlx5_allmulticast_disable, 2070 .link_update = mlx5_link_update, 2071 .stats_get = mlx5_stats_get, 2072 .stats_reset = mlx5_stats_reset, 2073 .xstats_get = mlx5_xstats_get, 2074 .xstats_reset = mlx5_xstats_reset, 2075 .xstats_get_names = mlx5_xstats_get_names, 2076 .fw_version_get = mlx5_fw_version_get, 2077 .dev_infos_get = mlx5_dev_infos_get, 2078 .representor_info_get = mlx5_representor_info_get, 2079 .read_clock = mlx5_txpp_read_clock, 2080 .dev_supported_ptypes_get = mlx5_dev_supported_ptypes_get, 2081 .vlan_filter_set = mlx5_vlan_filter_set, 2082 .rx_queue_setup = mlx5_rx_queue_setup, 2083 .rx_queue_avail_thresh_set = mlx5_rx_queue_lwm_set, 2084 .rx_queue_avail_thresh_query = mlx5_rx_queue_lwm_query, 2085 .rx_hairpin_queue_setup = mlx5_rx_hairpin_queue_setup, 2086 .tx_queue_setup = mlx5_tx_queue_setup, 2087 .tx_hairpin_queue_setup = mlx5_tx_hairpin_queue_setup, 2088 .rx_queue_release = mlx5_rx_queue_release, 2089 .tx_queue_release = mlx5_tx_queue_release, 2090 .rx_queue_start = mlx5_rx_queue_start, 2091 .rx_queue_stop = mlx5_rx_queue_stop, 2092 .tx_queue_start = mlx5_tx_queue_start, 2093 .tx_queue_stop = mlx5_tx_queue_stop, 2094 .flow_ctrl_get = mlx5_dev_get_flow_ctrl, 2095 .flow_ctrl_set = mlx5_dev_set_flow_ctrl, 2096 .mac_addr_remove = mlx5_mac_addr_remove, 2097 .mac_addr_add = mlx5_mac_addr_add, 2098 .mac_addr_set = mlx5_mac_addr_set, 2099 .set_mc_addr_list = mlx5_set_mc_addr_list, 2100 .mtu_set = mlx5_dev_set_mtu, 2101 .vlan_strip_queue_set = mlx5_vlan_strip_queue_set, 2102 .vlan_offload_set = mlx5_vlan_offload_set, 2103 .reta_update = mlx5_dev_rss_reta_update, 2104 .reta_query = mlx5_dev_rss_reta_query, 2105 .rss_hash_update = mlx5_rss_hash_update, 2106 .rss_hash_conf_get = mlx5_rss_hash_conf_get, 2107 .flow_ops_get = mlx5_flow_ops_get, 2108 .rxq_info_get = mlx5_rxq_info_get, 2109 .txq_info_get = mlx5_txq_info_get, 2110 .rx_burst_mode_get = mlx5_rx_burst_mode_get, 2111 .tx_burst_mode_get = mlx5_tx_burst_mode_get, 2112 .rx_queue_intr_enable = mlx5_rx_intr_enable, 2113 .rx_queue_intr_disable = mlx5_rx_intr_disable, 2114 .is_removed = mlx5_is_removed, 2115 .udp_tunnel_port_add = mlx5_udp_tunnel_port_add, 2116 .get_module_info = mlx5_get_module_info, 2117 .get_module_eeprom = mlx5_get_module_eeprom, 2118 .hairpin_cap_get = mlx5_hairpin_cap_get, 2119 .mtr_ops_get = mlx5_flow_meter_ops_get, 2120 .hairpin_bind = mlx5_hairpin_bind, 2121 .hairpin_unbind = mlx5_hairpin_unbind, 2122 .hairpin_get_peer_ports = mlx5_hairpin_get_peer_ports, 2123 .hairpin_queue_peer_update = mlx5_hairpin_queue_peer_update, 2124 .hairpin_queue_peer_bind = mlx5_hairpin_queue_peer_bind, 2125 .hairpin_queue_peer_unbind = mlx5_hairpin_queue_peer_unbind, 2126 .get_monitor_addr = mlx5_get_monitor_addr, 2127 }; 2128 2129 /* Available operations from secondary process. */ 2130 const struct eth_dev_ops mlx5_dev_sec_ops = { 2131 .stats_get = mlx5_stats_get, 2132 .stats_reset = mlx5_stats_reset, 2133 .xstats_get = mlx5_xstats_get, 2134 .xstats_reset = mlx5_xstats_reset, 2135 .xstats_get_names = mlx5_xstats_get_names, 2136 .fw_version_get = mlx5_fw_version_get, 2137 .dev_infos_get = mlx5_dev_infos_get, 2138 .representor_info_get = mlx5_representor_info_get, 2139 .read_clock = mlx5_txpp_read_clock, 2140 .rx_queue_start = mlx5_rx_queue_start, 2141 .rx_queue_stop = mlx5_rx_queue_stop, 2142 .tx_queue_start = mlx5_tx_queue_start, 2143 .tx_queue_stop = mlx5_tx_queue_stop, 2144 .rxq_info_get = mlx5_rxq_info_get, 2145 .txq_info_get = mlx5_txq_info_get, 2146 .rx_burst_mode_get = mlx5_rx_burst_mode_get, 2147 .tx_burst_mode_get = mlx5_tx_burst_mode_get, 2148 .get_module_info = mlx5_get_module_info, 2149 .get_module_eeprom = mlx5_get_module_eeprom, 2150 }; 2151 2152 /* Available operations in flow isolated mode. */ 2153 const struct eth_dev_ops mlx5_dev_ops_isolate = { 2154 .dev_configure = mlx5_dev_configure, 2155 .dev_start = mlx5_dev_start, 2156 .dev_stop = mlx5_dev_stop, 2157 .dev_set_link_down = mlx5_set_link_down, 2158 .dev_set_link_up = mlx5_set_link_up, 2159 .dev_close = mlx5_dev_close, 2160 .promiscuous_enable = mlx5_promiscuous_enable, 2161 .promiscuous_disable = mlx5_promiscuous_disable, 2162 .allmulticast_enable = mlx5_allmulticast_enable, 2163 .allmulticast_disable = mlx5_allmulticast_disable, 2164 .link_update = mlx5_link_update, 2165 .stats_get = mlx5_stats_get, 2166 .stats_reset = mlx5_stats_reset, 2167 .xstats_get = mlx5_xstats_get, 2168 .xstats_reset = mlx5_xstats_reset, 2169 .xstats_get_names = mlx5_xstats_get_names, 2170 .fw_version_get = mlx5_fw_version_get, 2171 .dev_infos_get = mlx5_dev_infos_get, 2172 .representor_info_get = mlx5_representor_info_get, 2173 .read_clock = mlx5_txpp_read_clock, 2174 .dev_supported_ptypes_get = mlx5_dev_supported_ptypes_get, 2175 .vlan_filter_set = mlx5_vlan_filter_set, 2176 .rx_queue_setup = mlx5_rx_queue_setup, 2177 .rx_hairpin_queue_setup = mlx5_rx_hairpin_queue_setup, 2178 .tx_queue_setup = mlx5_tx_queue_setup, 2179 .tx_hairpin_queue_setup = mlx5_tx_hairpin_queue_setup, 2180 .rx_queue_release = mlx5_rx_queue_release, 2181 .tx_queue_release = mlx5_tx_queue_release, 2182 .rx_queue_start = mlx5_rx_queue_start, 2183 .rx_queue_stop = mlx5_rx_queue_stop, 2184 .tx_queue_start = mlx5_tx_queue_start, 2185 .tx_queue_stop = mlx5_tx_queue_stop, 2186 .flow_ctrl_get = mlx5_dev_get_flow_ctrl, 2187 .flow_ctrl_set = mlx5_dev_set_flow_ctrl, 2188 .mac_addr_remove = mlx5_mac_addr_remove, 2189 .mac_addr_add = mlx5_mac_addr_add, 2190 .mac_addr_set = mlx5_mac_addr_set, 2191 .set_mc_addr_list = mlx5_set_mc_addr_list, 2192 .mtu_set = mlx5_dev_set_mtu, 2193 .vlan_strip_queue_set = mlx5_vlan_strip_queue_set, 2194 .vlan_offload_set = mlx5_vlan_offload_set, 2195 .flow_ops_get = mlx5_flow_ops_get, 2196 .rxq_info_get = mlx5_rxq_info_get, 2197 .txq_info_get = mlx5_txq_info_get, 2198 .rx_burst_mode_get = mlx5_rx_burst_mode_get, 2199 .tx_burst_mode_get = mlx5_tx_burst_mode_get, 2200 .rx_queue_intr_enable = mlx5_rx_intr_enable, 2201 .rx_queue_intr_disable = mlx5_rx_intr_disable, 2202 .is_removed = mlx5_is_removed, 2203 .get_module_info = mlx5_get_module_info, 2204 .get_module_eeprom = mlx5_get_module_eeprom, 2205 .hairpin_cap_get = mlx5_hairpin_cap_get, 2206 .mtr_ops_get = mlx5_flow_meter_ops_get, 2207 .hairpin_bind = mlx5_hairpin_bind, 2208 .hairpin_unbind = mlx5_hairpin_unbind, 2209 .hairpin_get_peer_ports = mlx5_hairpin_get_peer_ports, 2210 .hairpin_queue_peer_update = mlx5_hairpin_queue_peer_update, 2211 .hairpin_queue_peer_bind = mlx5_hairpin_queue_peer_bind, 2212 .hairpin_queue_peer_unbind = mlx5_hairpin_queue_peer_unbind, 2213 .get_monitor_addr = mlx5_get_monitor_addr, 2214 }; 2215 2216 /** 2217 * Verify and store value for device argument. 2218 * 2219 * @param[in] key 2220 * Key argument to verify. 2221 * @param[in] val 2222 * Value associated with key. 2223 * @param opaque 2224 * User data. 2225 * 2226 * @return 2227 * 0 on success, a negative errno value otherwise and rte_errno is set. 2228 */ 2229 static int 2230 mlx5_port_args_check_handler(const char *key, const char *val, void *opaque) 2231 { 2232 struct mlx5_port_config *config = opaque; 2233 signed long tmp; 2234 2235 /* No-op, port representors are processed in mlx5_dev_spawn(). */ 2236 if (!strcmp(MLX5_REPRESENTOR, key)) 2237 return 0; 2238 errno = 0; 2239 tmp = strtol(val, NULL, 0); 2240 if (errno) { 2241 rte_errno = errno; 2242 DRV_LOG(WARNING, "%s: \"%s\" is not a valid integer", key, val); 2243 return -rte_errno; 2244 } 2245 if (tmp < 0) { 2246 /* Negative values are acceptable for some keys only. */ 2247 rte_errno = EINVAL; 2248 DRV_LOG(WARNING, "%s: invalid negative value \"%s\"", key, val); 2249 return -rte_errno; 2250 } 2251 if (strcmp(MLX5_RXQ_CQE_COMP_EN, key) == 0) { 2252 if (tmp > MLX5_CQE_RESP_FORMAT_L34H_STRIDX) { 2253 DRV_LOG(ERR, "invalid CQE compression " 2254 "format parameter"); 2255 rte_errno = EINVAL; 2256 return -rte_errno; 2257 } 2258 config->cqe_comp = !!tmp; 2259 config->cqe_comp_fmt = tmp; 2260 } else if (strcmp(MLX5_RXQ_PKT_PAD_EN, key) == 0) { 2261 config->hw_padding = !!tmp; 2262 } else if (strcmp(MLX5_RX_MPRQ_EN, key) == 0) { 2263 config->mprq.enabled = !!tmp; 2264 } else if (strcmp(MLX5_RX_MPRQ_LOG_STRIDE_NUM, key) == 0) { 2265 config->mprq.log_stride_num = tmp; 2266 } else if (strcmp(MLX5_RX_MPRQ_LOG_STRIDE_SIZE, key) == 0) { 2267 config->mprq.log_stride_size = tmp; 2268 } else if (strcmp(MLX5_RX_MPRQ_MAX_MEMCPY_LEN, key) == 0) { 2269 config->mprq.max_memcpy_len = tmp; 2270 } else if (strcmp(MLX5_RXQS_MIN_MPRQ, key) == 0) { 2271 config->mprq.min_rxqs_num = tmp; 2272 } else if (strcmp(MLX5_TXQ_INLINE, key) == 0) { 2273 DRV_LOG(WARNING, "%s: deprecated parameter," 2274 " converted to txq_inline_max", key); 2275 config->txq_inline_max = tmp; 2276 } else if (strcmp(MLX5_TXQ_INLINE_MAX, key) == 0) { 2277 config->txq_inline_max = tmp; 2278 } else if (strcmp(MLX5_TXQ_INLINE_MIN, key) == 0) { 2279 config->txq_inline_min = tmp; 2280 } else if (strcmp(MLX5_TXQ_INLINE_MPW, key) == 0) { 2281 config->txq_inline_mpw = tmp; 2282 } else if (strcmp(MLX5_TXQS_MIN_INLINE, key) == 0) { 2283 config->txqs_inline = tmp; 2284 } else if (strcmp(MLX5_TXQS_MAX_VEC, key) == 0) { 2285 DRV_LOG(WARNING, "%s: deprecated parameter, ignored", key); 2286 } else if (strcmp(MLX5_TXQ_MPW_EN, key) == 0) { 2287 config->mps = !!tmp; 2288 } else if (strcmp(MLX5_TXQ_MPW_HDR_DSEG_EN, key) == 0) { 2289 DRV_LOG(WARNING, "%s: deprecated parameter, ignored", key); 2290 } else if (strcmp(MLX5_TXQ_MAX_INLINE_LEN, key) == 0) { 2291 DRV_LOG(WARNING, "%s: deprecated parameter," 2292 " converted to txq_inline_mpw", key); 2293 config->txq_inline_mpw = tmp; 2294 } else if (strcmp(MLX5_TX_VEC_EN, key) == 0) { 2295 DRV_LOG(WARNING, "%s: deprecated parameter, ignored", key); 2296 } else if (strcmp(MLX5_RX_VEC_EN, key) == 0) { 2297 config->rx_vec_en = !!tmp; 2298 } else if (strcmp(MLX5_MAX_DUMP_FILES_NUM, key) == 0) { 2299 config->max_dump_files_num = tmp; 2300 } else if (strcmp(MLX5_LRO_TIMEOUT_USEC, key) == 0) { 2301 config->lro_timeout = tmp; 2302 } else if (strcmp(MLX5_HP_BUF_SIZE, key) == 0) { 2303 config->log_hp_size = tmp; 2304 } else if (strcmp(MLX5_DELAY_DROP, key) == 0) { 2305 config->std_delay_drop = !!(tmp & MLX5_DELAY_DROP_STANDARD); 2306 config->hp_delay_drop = !!(tmp & MLX5_DELAY_DROP_HAIRPIN); 2307 } 2308 return 0; 2309 } 2310 2311 /** 2312 * Parse user port parameters and adjust them according to device capabilities. 2313 * 2314 * @param priv 2315 * Pointer to shared device context. 2316 * @param mkvlist 2317 * Pointer to mlx5 kvargs control, can be NULL if there is no devargs. 2318 * @param config 2319 * Pointer to port configuration structure. 2320 * 2321 * @return 2322 * 0 on success, a negative errno value otherwise and rte_errno is set. 2323 */ 2324 int 2325 mlx5_port_args_config(struct mlx5_priv *priv, struct mlx5_kvargs_ctrl *mkvlist, 2326 struct mlx5_port_config *config) 2327 { 2328 struct mlx5_hca_attr *hca_attr = &priv->sh->cdev->config.hca_attr; 2329 struct mlx5_dev_cap *dev_cap = &priv->sh->dev_cap; 2330 bool devx = priv->sh->cdev->config.devx; 2331 const char **params = (const char *[]){ 2332 MLX5_RXQ_CQE_COMP_EN, 2333 MLX5_RXQ_PKT_PAD_EN, 2334 MLX5_RX_MPRQ_EN, 2335 MLX5_RX_MPRQ_LOG_STRIDE_NUM, 2336 MLX5_RX_MPRQ_LOG_STRIDE_SIZE, 2337 MLX5_RX_MPRQ_MAX_MEMCPY_LEN, 2338 MLX5_RXQS_MIN_MPRQ, 2339 MLX5_TXQ_INLINE, 2340 MLX5_TXQ_INLINE_MIN, 2341 MLX5_TXQ_INLINE_MAX, 2342 MLX5_TXQ_INLINE_MPW, 2343 MLX5_TXQS_MIN_INLINE, 2344 MLX5_TXQS_MAX_VEC, 2345 MLX5_TXQ_MPW_EN, 2346 MLX5_TXQ_MPW_HDR_DSEG_EN, 2347 MLX5_TXQ_MAX_INLINE_LEN, 2348 MLX5_TX_VEC_EN, 2349 MLX5_RX_VEC_EN, 2350 MLX5_REPRESENTOR, 2351 MLX5_MAX_DUMP_FILES_NUM, 2352 MLX5_LRO_TIMEOUT_USEC, 2353 MLX5_HP_BUF_SIZE, 2354 MLX5_DELAY_DROP, 2355 NULL, 2356 }; 2357 int ret = 0; 2358 2359 /* Default configuration. */ 2360 memset(config, 0, sizeof(*config)); 2361 config->mps = MLX5_ARG_UNSET; 2362 config->cqe_comp = 1; 2363 config->rx_vec_en = 1; 2364 config->txq_inline_max = MLX5_ARG_UNSET; 2365 config->txq_inline_min = MLX5_ARG_UNSET; 2366 config->txq_inline_mpw = MLX5_ARG_UNSET; 2367 config->txqs_inline = MLX5_ARG_UNSET; 2368 config->mprq.max_memcpy_len = MLX5_MPRQ_MEMCPY_DEFAULT_LEN; 2369 config->mprq.min_rxqs_num = MLX5_MPRQ_MIN_RXQS; 2370 config->mprq.log_stride_num = MLX5_MPRQ_DEFAULT_LOG_STRIDE_NUM; 2371 config->log_hp_size = MLX5_ARG_UNSET; 2372 config->std_delay_drop = 0; 2373 config->hp_delay_drop = 0; 2374 if (mkvlist != NULL) { 2375 /* Process parameters. */ 2376 ret = mlx5_kvargs_process(mkvlist, params, 2377 mlx5_port_args_check_handler, config); 2378 if (ret) { 2379 DRV_LOG(ERR, "Failed to process port arguments: %s", 2380 strerror(rte_errno)); 2381 return -rte_errno; 2382 } 2383 } 2384 /* Adjust parameters according to device capabilities. */ 2385 if (config->hw_padding && !dev_cap->hw_padding) { 2386 DRV_LOG(DEBUG, "Rx end alignment padding isn't supported."); 2387 config->hw_padding = 0; 2388 } else if (config->hw_padding) { 2389 DRV_LOG(DEBUG, "Rx end alignment padding is enabled."); 2390 } 2391 /* 2392 * MPW is disabled by default, while the Enhanced MPW is enabled 2393 * by default. 2394 */ 2395 if (config->mps == MLX5_ARG_UNSET) 2396 config->mps = (dev_cap->mps == MLX5_MPW_ENHANCED) ? 2397 MLX5_MPW_ENHANCED : MLX5_MPW_DISABLED; 2398 else 2399 config->mps = config->mps ? dev_cap->mps : MLX5_MPW_DISABLED; 2400 DRV_LOG(INFO, "%sMPS is %s", 2401 config->mps == MLX5_MPW_ENHANCED ? "enhanced " : 2402 config->mps == MLX5_MPW ? "legacy " : "", 2403 config->mps != MLX5_MPW_DISABLED ? "enabled" : "disabled"); 2404 if (priv->sh->config.lro_allowed) { 2405 /* 2406 * If LRO timeout is not configured by application, 2407 * use the minimal supported value. 2408 */ 2409 if (!config->lro_timeout) 2410 config->lro_timeout = 2411 hca_attr->lro_timer_supported_periods[0]; 2412 DRV_LOG(DEBUG, "LRO session timeout set to %d usec.", 2413 config->lro_timeout); 2414 } 2415 if (config->cqe_comp && !dev_cap->cqe_comp) { 2416 DRV_LOG(WARNING, "Rx CQE 128B compression is not supported."); 2417 config->cqe_comp = 0; 2418 } 2419 if (config->cqe_comp_fmt == MLX5_CQE_RESP_FORMAT_FTAG_STRIDX && 2420 (!devx || !hca_attr->mini_cqe_resp_flow_tag)) { 2421 DRV_LOG(WARNING, 2422 "Flow Tag CQE compression format isn't supported."); 2423 config->cqe_comp = 0; 2424 } 2425 if (config->cqe_comp_fmt == MLX5_CQE_RESP_FORMAT_L34H_STRIDX && 2426 (!devx || !hca_attr->mini_cqe_resp_l3_l4_tag)) { 2427 DRV_LOG(WARNING, 2428 "L3/L4 Header CQE compression format isn't supported."); 2429 config->cqe_comp = 0; 2430 } 2431 DRV_LOG(DEBUG, "Rx CQE compression is %ssupported.", 2432 config->cqe_comp ? "" : "not "); 2433 if ((config->std_delay_drop || config->hp_delay_drop) && 2434 !dev_cap->rq_delay_drop_en) { 2435 config->std_delay_drop = 0; 2436 config->hp_delay_drop = 0; 2437 DRV_LOG(WARNING, "dev_port-%u: Rxq delay drop isn't supported.", 2438 priv->dev_port); 2439 } 2440 if (config->mprq.enabled && !priv->sh->dev_cap.mprq.enabled) { 2441 DRV_LOG(WARNING, "Multi-Packet RQ isn't supported."); 2442 config->mprq.enabled = 0; 2443 } 2444 if (config->max_dump_files_num == 0) 2445 config->max_dump_files_num = 128; 2446 /* Detect minimal data bytes to inline. */ 2447 mlx5_set_min_inline(priv); 2448 DRV_LOG(DEBUG, "VLAN insertion in WQE is %ssupported.", 2449 config->hw_vlan_insert ? "" : "not "); 2450 DRV_LOG(DEBUG, "\"rxq_pkt_pad_en\" is %u.", config->hw_padding); 2451 DRV_LOG(DEBUG, "\"rxq_cqe_comp_en\" is %u.", config->cqe_comp); 2452 DRV_LOG(DEBUG, "\"cqe_comp_fmt\" is %u.", config->cqe_comp_fmt); 2453 DRV_LOG(DEBUG, "\"rx_vec_en\" is %u.", config->rx_vec_en); 2454 DRV_LOG(DEBUG, "Standard \"delay_drop\" is %u.", 2455 config->std_delay_drop); 2456 DRV_LOG(DEBUG, "Hairpin \"delay_drop\" is %u.", config->hp_delay_drop); 2457 DRV_LOG(DEBUG, "\"max_dump_files_num\" is %u.", 2458 config->max_dump_files_num); 2459 DRV_LOG(DEBUG, "\"log_hp_size\" is %u.", config->log_hp_size); 2460 DRV_LOG(DEBUG, "\"mprq_en\" is %u.", config->mprq.enabled); 2461 DRV_LOG(DEBUG, "\"mprq_log_stride_num\" is %u.", 2462 config->mprq.log_stride_num); 2463 DRV_LOG(DEBUG, "\"mprq_log_stride_size\" is %u.", 2464 config->mprq.log_stride_size); 2465 DRV_LOG(DEBUG, "\"mprq_max_memcpy_len\" is %u.", 2466 config->mprq.max_memcpy_len); 2467 DRV_LOG(DEBUG, "\"rxqs_min_mprq\" is %u.", config->mprq.min_rxqs_num); 2468 DRV_LOG(DEBUG, "\"lro_timeout_usec\" is %u.", config->lro_timeout); 2469 DRV_LOG(DEBUG, "\"txq_mpw_en\" is %d.", config->mps); 2470 DRV_LOG(DEBUG, "\"txqs_min_inline\" is %d.", config->txqs_inline); 2471 DRV_LOG(DEBUG, "\"txq_inline_min\" is %d.", config->txq_inline_min); 2472 DRV_LOG(DEBUG, "\"txq_inline_max\" is %d.", config->txq_inline_max); 2473 DRV_LOG(DEBUG, "\"txq_inline_mpw\" is %d.", config->txq_inline_mpw); 2474 return 0; 2475 } 2476 2477 /** 2478 * Print the key for device argument. 2479 * 2480 * It is "dummy" handler whose whole purpose is to enable using 2481 * mlx5_kvargs_process() function which set devargs as used. 2482 * 2483 * @param key 2484 * Key argument. 2485 * @param val 2486 * Value associated with key, unused. 2487 * @param opaque 2488 * Unused, can be NULL. 2489 * 2490 * @return 2491 * 0 on success, function cannot fail. 2492 */ 2493 static int 2494 mlx5_dummy_handler(const char *key, const char *val, void *opaque) 2495 { 2496 DRV_LOG(DEBUG, "\tKey: \"%s\" is set as used.", key); 2497 RTE_SET_USED(opaque); 2498 RTE_SET_USED(val); 2499 return 0; 2500 } 2501 2502 /** 2503 * Set requested devargs as used when device is already spawned. 2504 * 2505 * It is necessary since it is valid to ask probe again for existing device, 2506 * if its devargs don't assign as used, mlx5_kvargs_validate() will fail. 2507 * 2508 * @param name 2509 * Name of the existing device. 2510 * @param port_id 2511 * Port identifier of the device. 2512 * @param mkvlist 2513 * Pointer to mlx5 kvargs control to sign as used. 2514 */ 2515 void 2516 mlx5_port_args_set_used(const char *name, uint16_t port_id, 2517 struct mlx5_kvargs_ctrl *mkvlist) 2518 { 2519 const char **params = (const char *[]){ 2520 MLX5_RXQ_CQE_COMP_EN, 2521 MLX5_RXQ_PKT_PAD_EN, 2522 MLX5_RX_MPRQ_EN, 2523 MLX5_RX_MPRQ_LOG_STRIDE_NUM, 2524 MLX5_RX_MPRQ_LOG_STRIDE_SIZE, 2525 MLX5_RX_MPRQ_MAX_MEMCPY_LEN, 2526 MLX5_RXQS_MIN_MPRQ, 2527 MLX5_TXQ_INLINE, 2528 MLX5_TXQ_INLINE_MIN, 2529 MLX5_TXQ_INLINE_MAX, 2530 MLX5_TXQ_INLINE_MPW, 2531 MLX5_TXQS_MIN_INLINE, 2532 MLX5_TXQS_MAX_VEC, 2533 MLX5_TXQ_MPW_EN, 2534 MLX5_TXQ_MPW_HDR_DSEG_EN, 2535 MLX5_TXQ_MAX_INLINE_LEN, 2536 MLX5_TX_VEC_EN, 2537 MLX5_RX_VEC_EN, 2538 MLX5_REPRESENTOR, 2539 MLX5_MAX_DUMP_FILES_NUM, 2540 MLX5_LRO_TIMEOUT_USEC, 2541 MLX5_HP_BUF_SIZE, 2542 MLX5_DELAY_DROP, 2543 NULL, 2544 }; 2545 2546 /* Secondary process should not handle devargs. */ 2547 if (rte_eal_process_type() != RTE_PROC_PRIMARY) 2548 return; 2549 MLX5_ASSERT(mkvlist != NULL); 2550 DRV_LOG(DEBUG, "Ethernet device \"%s\" for port %u " 2551 "already exists, set devargs as used:", name, port_id); 2552 /* This function cannot fail with this handler. */ 2553 mlx5_kvargs_process(mkvlist, params, mlx5_dummy_handler, NULL); 2554 } 2555 2556 /** 2557 * Check sibling device configurations when probing again. 2558 * 2559 * Sibling devices sharing infiniband device context should have compatible 2560 * configurations. This regards representors and bonding device. 2561 * 2562 * @param cdev 2563 * Pointer to mlx5 device structure. 2564 * @param mkvlist 2565 * Pointer to mlx5 kvargs control, can be NULL if there is no devargs. 2566 * 2567 * @return 2568 * 0 on success, a negative errno value otherwise and rte_errno is set. 2569 */ 2570 int 2571 mlx5_probe_again_args_validate(struct mlx5_common_device *cdev, 2572 struct mlx5_kvargs_ctrl *mkvlist) 2573 { 2574 struct mlx5_dev_ctx_shared *sh = NULL; 2575 struct mlx5_sh_config *config; 2576 int ret; 2577 2578 /* Secondary process should not handle devargs. */ 2579 if (rte_eal_process_type() != RTE_PROC_PRIMARY) 2580 return 0; 2581 pthread_mutex_lock(&mlx5_dev_ctx_list_mutex); 2582 /* Search for IB context by common device pointer. */ 2583 LIST_FOREACH(sh, &mlx5_dev_ctx_list, next) 2584 if (sh->cdev == cdev) 2585 break; 2586 pthread_mutex_unlock(&mlx5_dev_ctx_list_mutex); 2587 /* There is sh for this device -> it isn't probe again. */ 2588 if (sh == NULL) 2589 return 0; 2590 config = mlx5_malloc(MLX5_MEM_ZERO | MLX5_MEM_RTE, 2591 sizeof(struct mlx5_sh_config), 2592 RTE_CACHE_LINE_SIZE, SOCKET_ID_ANY); 2593 if (config == NULL) { 2594 rte_errno = -ENOMEM; 2595 return -rte_errno; 2596 } 2597 /* 2598 * Creates a temporary IB context configure structure according to new 2599 * devargs attached in probing again. 2600 */ 2601 ret = mlx5_shared_dev_ctx_args_config(sh, mkvlist, config); 2602 if (ret) { 2603 DRV_LOG(ERR, "Failed to process device configure: %s", 2604 strerror(rte_errno)); 2605 mlx5_free(config); 2606 return ret; 2607 } 2608 /* 2609 * Checks the match between the temporary structure and the existing 2610 * IB context structure. 2611 */ 2612 if (sh->config.dv_flow_en ^ config->dv_flow_en) { 2613 DRV_LOG(ERR, "\"dv_flow_en\" " 2614 "configuration mismatch for shared %s context.", 2615 sh->ibdev_name); 2616 goto error; 2617 } 2618 if ((sh->config.dv_xmeta_en ^ config->dv_xmeta_en) || 2619 (sh->config.dv_miss_info ^ config->dv_miss_info)) { 2620 DRV_LOG(ERR, "\"dv_xmeta_en\" " 2621 "configuration mismatch for shared %s context.", 2622 sh->ibdev_name); 2623 goto error; 2624 } 2625 if (sh->config.dv_esw_en ^ config->dv_esw_en) { 2626 DRV_LOG(ERR, "\"dv_esw_en\" " 2627 "configuration mismatch for shared %s context.", 2628 sh->ibdev_name); 2629 goto error; 2630 } 2631 if (sh->config.reclaim_mode ^ config->reclaim_mode) { 2632 DRV_LOG(ERR, "\"reclaim_mode\" " 2633 "configuration mismatch for shared %s context.", 2634 sh->ibdev_name); 2635 goto error; 2636 } 2637 if (sh->config.allow_duplicate_pattern ^ 2638 config->allow_duplicate_pattern) { 2639 DRV_LOG(ERR, "\"allow_duplicate_pattern\" " 2640 "configuration mismatch for shared %s context.", 2641 sh->ibdev_name); 2642 goto error; 2643 } 2644 if (sh->config.l3_vxlan_en ^ config->l3_vxlan_en) { 2645 DRV_LOG(ERR, "\"l3_vxlan_en\" " 2646 "configuration mismatch for shared %s context.", 2647 sh->ibdev_name); 2648 goto error; 2649 } 2650 if (sh->config.decap_en ^ config->decap_en) { 2651 DRV_LOG(ERR, "\"decap_en\" " 2652 "configuration mismatch for shared %s context.", 2653 sh->ibdev_name); 2654 goto error; 2655 } 2656 if (sh->config.lacp_by_user ^ config->lacp_by_user) { 2657 DRV_LOG(ERR, "\"lacp_by_user\" " 2658 "configuration mismatch for shared %s context.", 2659 sh->ibdev_name); 2660 goto error; 2661 } 2662 if (sh->config.tx_pp ^ config->tx_pp) { 2663 DRV_LOG(ERR, "\"tx_pp\" " 2664 "configuration mismatch for shared %s context.", 2665 sh->ibdev_name); 2666 goto error; 2667 } 2668 if (sh->config.tx_skew ^ config->tx_skew) { 2669 DRV_LOG(ERR, "\"tx_skew\" " 2670 "configuration mismatch for shared %s context.", 2671 sh->ibdev_name); 2672 goto error; 2673 } 2674 mlx5_free(config); 2675 return 0; 2676 error: 2677 mlx5_free(config); 2678 rte_errno = EINVAL; 2679 return -rte_errno; 2680 } 2681 2682 /** 2683 * Configures the minimal amount of data to inline into WQE 2684 * while sending packets. 2685 * 2686 * - the txq_inline_min has the maximal priority, if this 2687 * key is specified in devargs 2688 * - if DevX is enabled the inline mode is queried from the 2689 * device (HCA attributes and NIC vport context if needed). 2690 * - otherwise L2 mode (18 bytes) is assumed for ConnectX-4/4 Lx 2691 * and none (0 bytes) for other NICs 2692 * 2693 * @param priv 2694 * Pointer to the private device data structure. 2695 */ 2696 void 2697 mlx5_set_min_inline(struct mlx5_priv *priv) 2698 { 2699 struct mlx5_hca_attr *hca_attr = &priv->sh->cdev->config.hca_attr; 2700 struct mlx5_port_config *config = &priv->config; 2701 2702 if (config->txq_inline_min != MLX5_ARG_UNSET) { 2703 /* Application defines size of inlined data explicitly. */ 2704 if (priv->pci_dev != NULL) { 2705 switch (priv->pci_dev->id.device_id) { 2706 case PCI_DEVICE_ID_MELLANOX_CONNECTX4: 2707 case PCI_DEVICE_ID_MELLANOX_CONNECTX4VF: 2708 if (config->txq_inline_min < 2709 (int)MLX5_INLINE_HSIZE_L2) { 2710 DRV_LOG(DEBUG, 2711 "txq_inline_mix aligned to minimal ConnectX-4 required value %d", 2712 (int)MLX5_INLINE_HSIZE_L2); 2713 config->txq_inline_min = 2714 MLX5_INLINE_HSIZE_L2; 2715 } 2716 break; 2717 } 2718 } 2719 goto exit; 2720 } 2721 if (hca_attr->eth_net_offloads) { 2722 /* We have DevX enabled, inline mode queried successfully. */ 2723 switch (hca_attr->wqe_inline_mode) { 2724 case MLX5_CAP_INLINE_MODE_L2: 2725 /* outer L2 header must be inlined. */ 2726 config->txq_inline_min = MLX5_INLINE_HSIZE_L2; 2727 goto exit; 2728 case MLX5_CAP_INLINE_MODE_NOT_REQUIRED: 2729 /* No inline data are required by NIC. */ 2730 config->txq_inline_min = MLX5_INLINE_HSIZE_NONE; 2731 config->hw_vlan_insert = 2732 hca_attr->wqe_vlan_insert; 2733 DRV_LOG(DEBUG, "Tx VLAN insertion is supported"); 2734 goto exit; 2735 case MLX5_CAP_INLINE_MODE_VPORT_CONTEXT: 2736 /* inline mode is defined by NIC vport context. */ 2737 if (!hca_attr->eth_virt) 2738 break; 2739 switch (hca_attr->vport_inline_mode) { 2740 case MLX5_INLINE_MODE_NONE: 2741 config->txq_inline_min = 2742 MLX5_INLINE_HSIZE_NONE; 2743 goto exit; 2744 case MLX5_INLINE_MODE_L2: 2745 config->txq_inline_min = 2746 MLX5_INLINE_HSIZE_L2; 2747 goto exit; 2748 case MLX5_INLINE_MODE_IP: 2749 config->txq_inline_min = 2750 MLX5_INLINE_HSIZE_L3; 2751 goto exit; 2752 case MLX5_INLINE_MODE_TCP_UDP: 2753 config->txq_inline_min = 2754 MLX5_INLINE_HSIZE_L4; 2755 goto exit; 2756 case MLX5_INLINE_MODE_INNER_L2: 2757 config->txq_inline_min = 2758 MLX5_INLINE_HSIZE_INNER_L2; 2759 goto exit; 2760 case MLX5_INLINE_MODE_INNER_IP: 2761 config->txq_inline_min = 2762 MLX5_INLINE_HSIZE_INNER_L3; 2763 goto exit; 2764 case MLX5_INLINE_MODE_INNER_TCP_UDP: 2765 config->txq_inline_min = 2766 MLX5_INLINE_HSIZE_INNER_L4; 2767 goto exit; 2768 } 2769 } 2770 } 2771 if (priv->pci_dev == NULL) { 2772 config->txq_inline_min = MLX5_INLINE_HSIZE_NONE; 2773 goto exit; 2774 } 2775 /* 2776 * We get here if we are unable to deduce 2777 * inline data size with DevX. Try PCI ID 2778 * to determine old NICs. 2779 */ 2780 switch (priv->pci_dev->id.device_id) { 2781 case PCI_DEVICE_ID_MELLANOX_CONNECTX4: 2782 case PCI_DEVICE_ID_MELLANOX_CONNECTX4VF: 2783 case PCI_DEVICE_ID_MELLANOX_CONNECTX4LX: 2784 case PCI_DEVICE_ID_MELLANOX_CONNECTX4LXVF: 2785 config->txq_inline_min = MLX5_INLINE_HSIZE_L2; 2786 config->hw_vlan_insert = 0; 2787 break; 2788 case PCI_DEVICE_ID_MELLANOX_CONNECTX5: 2789 case PCI_DEVICE_ID_MELLANOX_CONNECTX5VF: 2790 case PCI_DEVICE_ID_MELLANOX_CONNECTX5EX: 2791 case PCI_DEVICE_ID_MELLANOX_CONNECTX5EXVF: 2792 /* 2793 * These NICs support VLAN insertion from WQE and 2794 * report the wqe_vlan_insert flag. But there is the bug 2795 * and PFC control may be broken, so disable feature. 2796 */ 2797 config->hw_vlan_insert = 0; 2798 config->txq_inline_min = MLX5_INLINE_HSIZE_NONE; 2799 break; 2800 default: 2801 config->txq_inline_min = MLX5_INLINE_HSIZE_NONE; 2802 break; 2803 } 2804 exit: 2805 DRV_LOG(DEBUG, "min tx inline configured: %d", config->txq_inline_min); 2806 } 2807 2808 /** 2809 * Configures the metadata mask fields in the shared context. 2810 * 2811 * @param [in] dev 2812 * Pointer to Ethernet device. 2813 */ 2814 void 2815 mlx5_set_metadata_mask(struct rte_eth_dev *dev) 2816 { 2817 struct mlx5_priv *priv = dev->data->dev_private; 2818 struct mlx5_dev_ctx_shared *sh = priv->sh; 2819 uint32_t meta, mark, reg_c0; 2820 2821 reg_c0 = ~priv->vport_meta_mask; 2822 switch (sh->config.dv_xmeta_en) { 2823 case MLX5_XMETA_MODE_LEGACY: 2824 meta = UINT32_MAX; 2825 mark = MLX5_FLOW_MARK_MASK; 2826 break; 2827 case MLX5_XMETA_MODE_META16: 2828 meta = reg_c0 >> rte_bsf32(reg_c0); 2829 mark = MLX5_FLOW_MARK_MASK; 2830 break; 2831 case MLX5_XMETA_MODE_META32: 2832 meta = UINT32_MAX; 2833 mark = (reg_c0 >> rte_bsf32(reg_c0)) & MLX5_FLOW_MARK_MASK; 2834 break; 2835 default: 2836 meta = 0; 2837 mark = 0; 2838 MLX5_ASSERT(false); 2839 break; 2840 } 2841 if (sh->dv_mark_mask && sh->dv_mark_mask != mark) 2842 DRV_LOG(WARNING, "metadata MARK mask mismatch %08X:%08X", 2843 sh->dv_mark_mask, mark); 2844 else 2845 sh->dv_mark_mask = mark; 2846 if (sh->dv_meta_mask && sh->dv_meta_mask != meta) 2847 DRV_LOG(WARNING, "metadata META mask mismatch %08X:%08X", 2848 sh->dv_meta_mask, meta); 2849 else 2850 sh->dv_meta_mask = meta; 2851 if (sh->dv_regc0_mask && sh->dv_regc0_mask != reg_c0) 2852 DRV_LOG(WARNING, "metadata reg_c0 mask mismatch %08X:%08X", 2853 sh->dv_meta_mask, reg_c0); 2854 else 2855 sh->dv_regc0_mask = reg_c0; 2856 DRV_LOG(DEBUG, "metadata mode %u", sh->config.dv_xmeta_en); 2857 DRV_LOG(DEBUG, "metadata MARK mask %08X", sh->dv_mark_mask); 2858 DRV_LOG(DEBUG, "metadata META mask %08X", sh->dv_meta_mask); 2859 DRV_LOG(DEBUG, "metadata reg_c0 mask %08X", sh->dv_regc0_mask); 2860 } 2861 2862 int 2863 rte_pmd_mlx5_get_dyn_flag_names(char *names[], unsigned int n) 2864 { 2865 static const char *const dynf_names[] = { 2866 RTE_PMD_MLX5_FINE_GRANULARITY_INLINE, 2867 RTE_MBUF_DYNFLAG_METADATA_NAME, 2868 RTE_MBUF_DYNFLAG_TX_TIMESTAMP_NAME 2869 }; 2870 unsigned int i; 2871 2872 if (n < RTE_DIM(dynf_names)) 2873 return -ENOMEM; 2874 for (i = 0; i < RTE_DIM(dynf_names); i++) { 2875 if (names[i] == NULL) 2876 return -EINVAL; 2877 strcpy(names[i], dynf_names[i]); 2878 } 2879 return RTE_DIM(dynf_names); 2880 } 2881 2882 /** 2883 * Look for the ethernet device belonging to mlx5 driver. 2884 * 2885 * @param[in] port_id 2886 * port_id to start looking for device. 2887 * @param[in] odev 2888 * Pointer to the hint device. When device is being probed 2889 * the its siblings (master and preceding representors might 2890 * not have assigned driver yet (because the mlx5_os_pci_probe() 2891 * is not completed yet, for this case match on hint 2892 * device may be used to detect sibling device. 2893 * 2894 * @return 2895 * port_id of found device, RTE_MAX_ETHPORT if not found. 2896 */ 2897 uint16_t 2898 mlx5_eth_find_next(uint16_t port_id, struct rte_device *odev) 2899 { 2900 while (port_id < RTE_MAX_ETHPORTS) { 2901 struct rte_eth_dev *dev = &rte_eth_devices[port_id]; 2902 2903 if (dev->state != RTE_ETH_DEV_UNUSED && 2904 dev->device && 2905 (dev->device == odev || 2906 (dev->device->driver && 2907 dev->device->driver->name && 2908 ((strcmp(dev->device->driver->name, 2909 MLX5_PCI_DRIVER_NAME) == 0) || 2910 (strcmp(dev->device->driver->name, 2911 MLX5_AUXILIARY_DRIVER_NAME) == 0))))) 2912 break; 2913 port_id++; 2914 } 2915 if (port_id >= RTE_MAX_ETHPORTS) 2916 return RTE_MAX_ETHPORTS; 2917 return port_id; 2918 } 2919 2920 /** 2921 * Callback to remove a device. 2922 * 2923 * This function removes all Ethernet devices belong to a given device. 2924 * 2925 * @param[in] cdev 2926 * Pointer to the generic device. 2927 * 2928 * @return 2929 * 0 on success, the function cannot fail. 2930 */ 2931 int 2932 mlx5_net_remove(struct mlx5_common_device *cdev) 2933 { 2934 uint16_t port_id; 2935 int ret = 0; 2936 2937 RTE_ETH_FOREACH_DEV_OF(port_id, cdev->dev) { 2938 /* 2939 * mlx5_dev_close() is not registered to secondary process, 2940 * call the close function explicitly for secondary process. 2941 */ 2942 if (rte_eal_process_type() == RTE_PROC_SECONDARY) 2943 ret |= mlx5_dev_close(&rte_eth_devices[port_id]); 2944 else 2945 ret |= rte_eth_dev_close(port_id); 2946 } 2947 return ret == 0 ? 0 : -EIO; 2948 } 2949 2950 static const struct rte_pci_id mlx5_pci_id_map[] = { 2951 { 2952 RTE_PCI_DEVICE(PCI_VENDOR_ID_MELLANOX, 2953 PCI_DEVICE_ID_MELLANOX_CONNECTX4) 2954 }, 2955 { 2956 RTE_PCI_DEVICE(PCI_VENDOR_ID_MELLANOX, 2957 PCI_DEVICE_ID_MELLANOX_CONNECTX4VF) 2958 }, 2959 { 2960 RTE_PCI_DEVICE(PCI_VENDOR_ID_MELLANOX, 2961 PCI_DEVICE_ID_MELLANOX_CONNECTX4LX) 2962 }, 2963 { 2964 RTE_PCI_DEVICE(PCI_VENDOR_ID_MELLANOX, 2965 PCI_DEVICE_ID_MELLANOX_CONNECTX4LXVF) 2966 }, 2967 { 2968 RTE_PCI_DEVICE(PCI_VENDOR_ID_MELLANOX, 2969 PCI_DEVICE_ID_MELLANOX_CONNECTX5) 2970 }, 2971 { 2972 RTE_PCI_DEVICE(PCI_VENDOR_ID_MELLANOX, 2973 PCI_DEVICE_ID_MELLANOX_CONNECTX5VF) 2974 }, 2975 { 2976 RTE_PCI_DEVICE(PCI_VENDOR_ID_MELLANOX, 2977 PCI_DEVICE_ID_MELLANOX_CONNECTX5EX) 2978 }, 2979 { 2980 RTE_PCI_DEVICE(PCI_VENDOR_ID_MELLANOX, 2981 PCI_DEVICE_ID_MELLANOX_CONNECTX5EXVF) 2982 }, 2983 { 2984 RTE_PCI_DEVICE(PCI_VENDOR_ID_MELLANOX, 2985 PCI_DEVICE_ID_MELLANOX_CONNECTX5BF) 2986 }, 2987 { 2988 RTE_PCI_DEVICE(PCI_VENDOR_ID_MELLANOX, 2989 PCI_DEVICE_ID_MELLANOX_CONNECTX5BFVF) 2990 }, 2991 { 2992 RTE_PCI_DEVICE(PCI_VENDOR_ID_MELLANOX, 2993 PCI_DEVICE_ID_MELLANOX_CONNECTX6) 2994 }, 2995 { 2996 RTE_PCI_DEVICE(PCI_VENDOR_ID_MELLANOX, 2997 PCI_DEVICE_ID_MELLANOX_CONNECTX6VF) 2998 }, 2999 { 3000 RTE_PCI_DEVICE(PCI_VENDOR_ID_MELLANOX, 3001 PCI_DEVICE_ID_MELLANOX_CONNECTX6DX) 3002 }, 3003 { 3004 RTE_PCI_DEVICE(PCI_VENDOR_ID_MELLANOX, 3005 PCI_DEVICE_ID_MELLANOX_CONNECTXVF) 3006 }, 3007 { 3008 RTE_PCI_DEVICE(PCI_VENDOR_ID_MELLANOX, 3009 PCI_DEVICE_ID_MELLANOX_CONNECTX6DXBF) 3010 }, 3011 { 3012 RTE_PCI_DEVICE(PCI_VENDOR_ID_MELLANOX, 3013 PCI_DEVICE_ID_MELLANOX_CONNECTX6LX) 3014 }, 3015 { 3016 RTE_PCI_DEVICE(PCI_VENDOR_ID_MELLANOX, 3017 PCI_DEVICE_ID_MELLANOX_CONNECTX7) 3018 }, 3019 { 3020 RTE_PCI_DEVICE(PCI_VENDOR_ID_MELLANOX, 3021 PCI_DEVICE_ID_MELLANOX_CONNECTX7BF) 3022 }, 3023 { 3024 .vendor_id = 0 3025 } 3026 }; 3027 3028 static struct mlx5_class_driver mlx5_net_driver = { 3029 .drv_class = MLX5_CLASS_ETH, 3030 .name = RTE_STR(MLX5_ETH_DRIVER_NAME), 3031 .id_table = mlx5_pci_id_map, 3032 .probe = mlx5_os_net_probe, 3033 .remove = mlx5_net_remove, 3034 .probe_again = 1, 3035 .intr_lsc = 1, 3036 .intr_rmv = 1, 3037 }; 3038 3039 /* Initialize driver log type. */ 3040 RTE_LOG_REGISTER_DEFAULT(mlx5_logtype, NOTICE) 3041 3042 /** 3043 * Driver initialization routine. 3044 */ 3045 RTE_INIT(rte_mlx5_pmd_init) 3046 { 3047 pthread_mutex_init(&mlx5_dev_ctx_list_mutex, NULL); 3048 mlx5_common_init(); 3049 /* Build the static tables for Verbs conversion. */ 3050 mlx5_set_ptype_table(); 3051 mlx5_set_cksum_table(); 3052 mlx5_set_swp_types_table(); 3053 if (mlx5_glue) 3054 mlx5_class_driver_register(&mlx5_net_driver); 3055 } 3056 3057 RTE_PMD_EXPORT_NAME(MLX5_ETH_DRIVER_NAME, __COUNTER__); 3058 RTE_PMD_REGISTER_PCI_TABLE(MLX5_ETH_DRIVER_NAME, mlx5_pci_id_map); 3059 RTE_PMD_REGISTER_KMOD_DEP(MLX5_ETH_DRIVER_NAME, "* ib_uverbs & mlx5_core & mlx5_ib"); 3060