1 /* SPDX-License-Identifier: BSD-3-Clause 2 * Copyright 2015 6WIND S.A. 3 * Copyright 2015 Mellanox Technologies, Ltd 4 */ 5 6 #include <stddef.h> 7 #include <unistd.h> 8 #include <string.h> 9 #include <assert.h> 10 #include <dlfcn.h> 11 #include <stdint.h> 12 #include <stdlib.h> 13 #include <errno.h> 14 #include <net/if.h> 15 #include <sys/mman.h> 16 #include <linux/netlink.h> 17 #include <linux/rtnetlink.h> 18 19 /* Verbs header. */ 20 /* ISO C doesn't support unnamed structs/unions, disabling -pedantic. */ 21 #ifdef PEDANTIC 22 #pragma GCC diagnostic ignored "-Wpedantic" 23 #endif 24 #include <infiniband/verbs.h> 25 #ifdef PEDANTIC 26 #pragma GCC diagnostic error "-Wpedantic" 27 #endif 28 29 #include <rte_malloc.h> 30 #include <rte_ethdev_driver.h> 31 #include <rte_ethdev_pci.h> 32 #include <rte_pci.h> 33 #include <rte_bus_pci.h> 34 #include <rte_common.h> 35 #include <rte_config.h> 36 #include <rte_eal_memconfig.h> 37 #include <rte_kvargs.h> 38 #include <rte_rwlock.h> 39 #include <rte_spinlock.h> 40 #include <rte_string_fns.h> 41 42 #include "mlx5.h" 43 #include "mlx5_utils.h" 44 #include "mlx5_rxtx.h" 45 #include "mlx5_autoconf.h" 46 #include "mlx5_defs.h" 47 #include "mlx5_glue.h" 48 #include "mlx5_mr.h" 49 #include "mlx5_flow.h" 50 51 /* Device parameter to enable RX completion queue compression. */ 52 #define MLX5_RXQ_CQE_COMP_EN "rxq_cqe_comp_en" 53 54 /* Device parameter to enable Multi-Packet Rx queue. */ 55 #define MLX5_RX_MPRQ_EN "mprq_en" 56 57 /* Device parameter to configure log 2 of the number of strides for MPRQ. */ 58 #define MLX5_RX_MPRQ_LOG_STRIDE_NUM "mprq_log_stride_num" 59 60 /* Device parameter to limit the size of memcpy'd packet for MPRQ. */ 61 #define MLX5_RX_MPRQ_MAX_MEMCPY_LEN "mprq_max_memcpy_len" 62 63 /* Device parameter to set the minimum number of Rx queues to enable MPRQ. */ 64 #define MLX5_RXQS_MIN_MPRQ "rxqs_min_mprq" 65 66 /* Device parameter to configure inline send. */ 67 #define MLX5_TXQ_INLINE "txq_inline" 68 69 /* 70 * Device parameter to configure the number of TX queues threshold for 71 * enabling inline send. 72 */ 73 #define MLX5_TXQS_MIN_INLINE "txqs_min_inline" 74 75 /* Device parameter to enable multi-packet send WQEs. */ 76 #define MLX5_TXQ_MPW_EN "txq_mpw_en" 77 78 /* Device parameter to include 2 dsegs in the title WQEBB. */ 79 #define MLX5_TXQ_MPW_HDR_DSEG_EN "txq_mpw_hdr_dseg_en" 80 81 /* Device parameter to limit the size of inlining packet. */ 82 #define MLX5_TXQ_MAX_INLINE_LEN "txq_max_inline_len" 83 84 /* Device parameter to enable hardware Tx vector. */ 85 #define MLX5_TX_VEC_EN "tx_vec_en" 86 87 /* Device parameter to enable hardware Rx vector. */ 88 #define MLX5_RX_VEC_EN "rx_vec_en" 89 90 /* Allow L3 VXLAN flow creation. */ 91 #define MLX5_L3_VXLAN_EN "l3_vxlan_en" 92 93 /* Activate DV flow steering. */ 94 #define MLX5_DV_FLOW_EN "dv_flow_en" 95 96 /* Activate Netlink support in VF mode. */ 97 #define MLX5_VF_NL_EN "vf_nl_en" 98 99 /* Select port representors to instantiate. */ 100 #define MLX5_REPRESENTOR "representor" 101 102 #ifndef HAVE_IBV_MLX5_MOD_MPW 103 #define MLX5DV_CONTEXT_FLAGS_MPW_ALLOWED (1 << 2) 104 #define MLX5DV_CONTEXT_FLAGS_ENHANCED_MPW (1 << 3) 105 #endif 106 107 #ifndef HAVE_IBV_MLX5_MOD_CQE_128B_COMP 108 #define MLX5DV_CONTEXT_FLAGS_CQE_128B_COMP (1 << 4) 109 #endif 110 111 static const char *MZ_MLX5_PMD_SHARED_DATA = "mlx5_pmd_shared_data"; 112 113 /* Shared memory between primary and secondary processes. */ 114 struct mlx5_shared_data *mlx5_shared_data; 115 116 /* Spinlock for mlx5_shared_data allocation. */ 117 static rte_spinlock_t mlx5_shared_data_lock = RTE_SPINLOCK_INITIALIZER; 118 119 /** Driver-specific log messages type. */ 120 int mlx5_logtype; 121 122 /** 123 * Prepare shared data between primary and secondary process. 124 */ 125 static void 126 mlx5_prepare_shared_data(void) 127 { 128 const struct rte_memzone *mz; 129 130 rte_spinlock_lock(&mlx5_shared_data_lock); 131 if (mlx5_shared_data == NULL) { 132 if (rte_eal_process_type() == RTE_PROC_PRIMARY) { 133 /* Allocate shared memory. */ 134 mz = rte_memzone_reserve(MZ_MLX5_PMD_SHARED_DATA, 135 sizeof(*mlx5_shared_data), 136 SOCKET_ID_ANY, 0); 137 } else { 138 /* Lookup allocated shared memory. */ 139 mz = rte_memzone_lookup(MZ_MLX5_PMD_SHARED_DATA); 140 } 141 if (mz == NULL) 142 rte_panic("Cannot allocate mlx5 shared data\n"); 143 mlx5_shared_data = mz->addr; 144 /* Initialize shared data. */ 145 if (rte_eal_process_type() == RTE_PROC_PRIMARY) { 146 LIST_INIT(&mlx5_shared_data->mem_event_cb_list); 147 rte_rwlock_init(&mlx5_shared_data->mem_event_rwlock); 148 } 149 rte_mem_event_callback_register("MLX5_MEM_EVENT_CB", 150 mlx5_mr_mem_event_cb, NULL); 151 } 152 rte_spinlock_unlock(&mlx5_shared_data_lock); 153 } 154 155 /** 156 * Retrieve integer value from environment variable. 157 * 158 * @param[in] name 159 * Environment variable name. 160 * 161 * @return 162 * Integer value, 0 if the variable is not set. 163 */ 164 int 165 mlx5_getenv_int(const char *name) 166 { 167 const char *val = getenv(name); 168 169 if (val == NULL) 170 return 0; 171 return atoi(val); 172 } 173 174 /** 175 * Verbs callback to allocate a memory. This function should allocate the space 176 * according to the size provided residing inside a huge page. 177 * Please note that all allocation must respect the alignment from libmlx5 178 * (i.e. currently sysconf(_SC_PAGESIZE)). 179 * 180 * @param[in] size 181 * The size in bytes of the memory to allocate. 182 * @param[in] data 183 * A pointer to the callback data. 184 * 185 * @return 186 * Allocated buffer, NULL otherwise and rte_errno is set. 187 */ 188 static void * 189 mlx5_alloc_verbs_buf(size_t size, void *data) 190 { 191 struct priv *priv = data; 192 void *ret; 193 size_t alignment = sysconf(_SC_PAGESIZE); 194 unsigned int socket = SOCKET_ID_ANY; 195 196 if (priv->verbs_alloc_ctx.type == MLX5_VERBS_ALLOC_TYPE_TX_QUEUE) { 197 const struct mlx5_txq_ctrl *ctrl = priv->verbs_alloc_ctx.obj; 198 199 socket = ctrl->socket; 200 } else if (priv->verbs_alloc_ctx.type == 201 MLX5_VERBS_ALLOC_TYPE_RX_QUEUE) { 202 const struct mlx5_rxq_ctrl *ctrl = priv->verbs_alloc_ctx.obj; 203 204 socket = ctrl->socket; 205 } 206 assert(data != NULL); 207 ret = rte_malloc_socket(__func__, size, alignment, socket); 208 if (!ret && size) 209 rte_errno = ENOMEM; 210 return ret; 211 } 212 213 /** 214 * Verbs callback to free a memory. 215 * 216 * @param[in] ptr 217 * A pointer to the memory to free. 218 * @param[in] data 219 * A pointer to the callback data. 220 */ 221 static void 222 mlx5_free_verbs_buf(void *ptr, void *data __rte_unused) 223 { 224 assert(data != NULL); 225 rte_free(ptr); 226 } 227 228 /** 229 * DPDK callback to close the device. 230 * 231 * Destroy all queues and objects, free memory. 232 * 233 * @param dev 234 * Pointer to Ethernet device structure. 235 */ 236 static void 237 mlx5_dev_close(struct rte_eth_dev *dev) 238 { 239 struct priv *priv = dev->data->dev_private; 240 unsigned int i; 241 int ret; 242 243 DRV_LOG(DEBUG, "port %u closing device \"%s\"", 244 dev->data->port_id, 245 ((priv->ctx != NULL) ? priv->ctx->device->name : "")); 246 /* In case mlx5_dev_stop() has not been called. */ 247 mlx5_dev_interrupt_handler_uninstall(dev); 248 mlx5_traffic_disable(dev); 249 mlx5_flow_flush(dev, NULL); 250 /* Prevent crashes when queues are still in use. */ 251 dev->rx_pkt_burst = removed_rx_burst; 252 dev->tx_pkt_burst = removed_tx_burst; 253 if (priv->rxqs != NULL) { 254 /* XXX race condition if mlx5_rx_burst() is still running. */ 255 usleep(1000); 256 for (i = 0; (i != priv->rxqs_n); ++i) 257 mlx5_rxq_release(dev, i); 258 priv->rxqs_n = 0; 259 priv->rxqs = NULL; 260 } 261 if (priv->txqs != NULL) { 262 /* XXX race condition if mlx5_tx_burst() is still running. */ 263 usleep(1000); 264 for (i = 0; (i != priv->txqs_n); ++i) 265 mlx5_txq_release(dev, i); 266 priv->txqs_n = 0; 267 priv->txqs = NULL; 268 } 269 mlx5_mprq_free_mp(dev); 270 mlx5_mr_release(dev); 271 if (priv->pd != NULL) { 272 assert(priv->ctx != NULL); 273 claim_zero(mlx5_glue->dealloc_pd(priv->pd)); 274 claim_zero(mlx5_glue->close_device(priv->ctx)); 275 } else 276 assert(priv->ctx == NULL); 277 if (priv->rss_conf.rss_key != NULL) 278 rte_free(priv->rss_conf.rss_key); 279 if (priv->reta_idx != NULL) 280 rte_free(priv->reta_idx); 281 if (priv->primary_socket) 282 mlx5_socket_uninit(dev); 283 if (priv->config.vf) 284 mlx5_nl_mac_addr_flush(dev); 285 if (priv->nl_socket_route >= 0) 286 close(priv->nl_socket_route); 287 if (priv->nl_socket_rdma >= 0) 288 close(priv->nl_socket_rdma); 289 if (priv->tcf_context) 290 mlx5_flow_tcf_context_destroy(priv->tcf_context); 291 ret = mlx5_hrxq_ibv_verify(dev); 292 if (ret) 293 DRV_LOG(WARNING, "port %u some hash Rx queue still remain", 294 dev->data->port_id); 295 ret = mlx5_ind_table_ibv_verify(dev); 296 if (ret) 297 DRV_LOG(WARNING, "port %u some indirection table still remain", 298 dev->data->port_id); 299 ret = mlx5_rxq_ibv_verify(dev); 300 if (ret) 301 DRV_LOG(WARNING, "port %u some Verbs Rx queue still remain", 302 dev->data->port_id); 303 ret = mlx5_rxq_verify(dev); 304 if (ret) 305 DRV_LOG(WARNING, "port %u some Rx queues still remain", 306 dev->data->port_id); 307 ret = mlx5_txq_ibv_verify(dev); 308 if (ret) 309 DRV_LOG(WARNING, "port %u some Verbs Tx queue still remain", 310 dev->data->port_id); 311 ret = mlx5_txq_verify(dev); 312 if (ret) 313 DRV_LOG(WARNING, "port %u some Tx queues still remain", 314 dev->data->port_id); 315 ret = mlx5_flow_verify(dev); 316 if (ret) 317 DRV_LOG(WARNING, "port %u some flows still remain", 318 dev->data->port_id); 319 if (priv->domain_id != RTE_ETH_DEV_SWITCH_DOMAIN_ID_INVALID) { 320 unsigned int c = 0; 321 unsigned int i = mlx5_dev_to_port_id(dev->device, NULL, 0); 322 uint16_t port_id[i]; 323 324 i = RTE_MIN(mlx5_dev_to_port_id(dev->device, port_id, i), i); 325 while (i--) { 326 struct priv *opriv = 327 rte_eth_devices[port_id[i]].data->dev_private; 328 329 if (!opriv || 330 opriv->domain_id != priv->domain_id || 331 &rte_eth_devices[port_id[i]] == dev) 332 continue; 333 ++c; 334 } 335 if (!c) 336 claim_zero(rte_eth_switch_domain_free(priv->domain_id)); 337 } 338 memset(priv, 0, sizeof(*priv)); 339 priv->domain_id = RTE_ETH_DEV_SWITCH_DOMAIN_ID_INVALID; 340 /* 341 * flag to rte_eth_dev_close() that it should release the port resources 342 * (calling rte_eth_dev_release_port()) in addition to closing it. 343 */ 344 dev->data->dev_flags |= RTE_ETH_DEV_CLOSE_REMOVE; 345 /* 346 * Reset mac_addrs to NULL such that it is not freed as part of 347 * rte_eth_dev_release_port(). mac_addrs is part of dev_private so 348 * it is freed when dev_private is freed. 349 */ 350 dev->data->mac_addrs = NULL; 351 } 352 353 const struct eth_dev_ops mlx5_dev_ops = { 354 .dev_configure = mlx5_dev_configure, 355 .dev_start = mlx5_dev_start, 356 .dev_stop = mlx5_dev_stop, 357 .dev_set_link_down = mlx5_set_link_down, 358 .dev_set_link_up = mlx5_set_link_up, 359 .dev_close = mlx5_dev_close, 360 .promiscuous_enable = mlx5_promiscuous_enable, 361 .promiscuous_disable = mlx5_promiscuous_disable, 362 .allmulticast_enable = mlx5_allmulticast_enable, 363 .allmulticast_disable = mlx5_allmulticast_disable, 364 .link_update = mlx5_link_update, 365 .stats_get = mlx5_stats_get, 366 .stats_reset = mlx5_stats_reset, 367 .xstats_get = mlx5_xstats_get, 368 .xstats_reset = mlx5_xstats_reset, 369 .xstats_get_names = mlx5_xstats_get_names, 370 .dev_infos_get = mlx5_dev_infos_get, 371 .dev_supported_ptypes_get = mlx5_dev_supported_ptypes_get, 372 .vlan_filter_set = mlx5_vlan_filter_set, 373 .rx_queue_setup = mlx5_rx_queue_setup, 374 .tx_queue_setup = mlx5_tx_queue_setup, 375 .rx_queue_release = mlx5_rx_queue_release, 376 .tx_queue_release = mlx5_tx_queue_release, 377 .flow_ctrl_get = mlx5_dev_get_flow_ctrl, 378 .flow_ctrl_set = mlx5_dev_set_flow_ctrl, 379 .mac_addr_remove = mlx5_mac_addr_remove, 380 .mac_addr_add = mlx5_mac_addr_add, 381 .mac_addr_set = mlx5_mac_addr_set, 382 .set_mc_addr_list = mlx5_set_mc_addr_list, 383 .mtu_set = mlx5_dev_set_mtu, 384 .vlan_strip_queue_set = mlx5_vlan_strip_queue_set, 385 .vlan_offload_set = mlx5_vlan_offload_set, 386 .reta_update = mlx5_dev_rss_reta_update, 387 .reta_query = mlx5_dev_rss_reta_query, 388 .rss_hash_update = mlx5_rss_hash_update, 389 .rss_hash_conf_get = mlx5_rss_hash_conf_get, 390 .filter_ctrl = mlx5_dev_filter_ctrl, 391 .rx_descriptor_status = mlx5_rx_descriptor_status, 392 .tx_descriptor_status = mlx5_tx_descriptor_status, 393 .rx_queue_intr_enable = mlx5_rx_intr_enable, 394 .rx_queue_intr_disable = mlx5_rx_intr_disable, 395 .is_removed = mlx5_is_removed, 396 }; 397 398 static const struct eth_dev_ops mlx5_dev_sec_ops = { 399 .stats_get = mlx5_stats_get, 400 .stats_reset = mlx5_stats_reset, 401 .xstats_get = mlx5_xstats_get, 402 .xstats_reset = mlx5_xstats_reset, 403 .xstats_get_names = mlx5_xstats_get_names, 404 .dev_infos_get = mlx5_dev_infos_get, 405 .rx_descriptor_status = mlx5_rx_descriptor_status, 406 .tx_descriptor_status = mlx5_tx_descriptor_status, 407 }; 408 409 /* Available operators in flow isolated mode. */ 410 const struct eth_dev_ops mlx5_dev_ops_isolate = { 411 .dev_configure = mlx5_dev_configure, 412 .dev_start = mlx5_dev_start, 413 .dev_stop = mlx5_dev_stop, 414 .dev_set_link_down = mlx5_set_link_down, 415 .dev_set_link_up = mlx5_set_link_up, 416 .dev_close = mlx5_dev_close, 417 .promiscuous_enable = mlx5_promiscuous_enable, 418 .promiscuous_disable = mlx5_promiscuous_disable, 419 .allmulticast_enable = mlx5_allmulticast_enable, 420 .allmulticast_disable = mlx5_allmulticast_disable, 421 .link_update = mlx5_link_update, 422 .stats_get = mlx5_stats_get, 423 .stats_reset = mlx5_stats_reset, 424 .xstats_get = mlx5_xstats_get, 425 .xstats_reset = mlx5_xstats_reset, 426 .xstats_get_names = mlx5_xstats_get_names, 427 .dev_infos_get = mlx5_dev_infos_get, 428 .dev_supported_ptypes_get = mlx5_dev_supported_ptypes_get, 429 .vlan_filter_set = mlx5_vlan_filter_set, 430 .rx_queue_setup = mlx5_rx_queue_setup, 431 .tx_queue_setup = mlx5_tx_queue_setup, 432 .rx_queue_release = mlx5_rx_queue_release, 433 .tx_queue_release = mlx5_tx_queue_release, 434 .flow_ctrl_get = mlx5_dev_get_flow_ctrl, 435 .flow_ctrl_set = mlx5_dev_set_flow_ctrl, 436 .mac_addr_remove = mlx5_mac_addr_remove, 437 .mac_addr_add = mlx5_mac_addr_add, 438 .mac_addr_set = mlx5_mac_addr_set, 439 .set_mc_addr_list = mlx5_set_mc_addr_list, 440 .mtu_set = mlx5_dev_set_mtu, 441 .vlan_strip_queue_set = mlx5_vlan_strip_queue_set, 442 .vlan_offload_set = mlx5_vlan_offload_set, 443 .filter_ctrl = mlx5_dev_filter_ctrl, 444 .rx_descriptor_status = mlx5_rx_descriptor_status, 445 .tx_descriptor_status = mlx5_tx_descriptor_status, 446 .rx_queue_intr_enable = mlx5_rx_intr_enable, 447 .rx_queue_intr_disable = mlx5_rx_intr_disable, 448 .is_removed = mlx5_is_removed, 449 }; 450 451 /** 452 * Verify and store value for device argument. 453 * 454 * @param[in] key 455 * Key argument to verify. 456 * @param[in] val 457 * Value associated with key. 458 * @param opaque 459 * User data. 460 * 461 * @return 462 * 0 on success, a negative errno value otherwise and rte_errno is set. 463 */ 464 static int 465 mlx5_args_check(const char *key, const char *val, void *opaque) 466 { 467 struct mlx5_dev_config *config = opaque; 468 unsigned long tmp; 469 470 /* No-op, port representors are processed in mlx5_dev_spawn(). */ 471 if (!strcmp(MLX5_REPRESENTOR, key)) 472 return 0; 473 errno = 0; 474 tmp = strtoul(val, NULL, 0); 475 if (errno) { 476 rte_errno = errno; 477 DRV_LOG(WARNING, "%s: \"%s\" is not a valid integer", key, val); 478 return -rte_errno; 479 } 480 if (strcmp(MLX5_RXQ_CQE_COMP_EN, key) == 0) { 481 config->cqe_comp = !!tmp; 482 } else if (strcmp(MLX5_RX_MPRQ_EN, key) == 0) { 483 config->mprq.enabled = !!tmp; 484 } else if (strcmp(MLX5_RX_MPRQ_LOG_STRIDE_NUM, key) == 0) { 485 config->mprq.stride_num_n = tmp; 486 } else if (strcmp(MLX5_RX_MPRQ_MAX_MEMCPY_LEN, key) == 0) { 487 config->mprq.max_memcpy_len = tmp; 488 } else if (strcmp(MLX5_RXQS_MIN_MPRQ, key) == 0) { 489 config->mprq.min_rxqs_num = tmp; 490 } else if (strcmp(MLX5_TXQ_INLINE, key) == 0) { 491 config->txq_inline = tmp; 492 } else if (strcmp(MLX5_TXQS_MIN_INLINE, key) == 0) { 493 config->txqs_inline = tmp; 494 } else if (strcmp(MLX5_TXQ_MPW_EN, key) == 0) { 495 config->mps = !!tmp; 496 } else if (strcmp(MLX5_TXQ_MPW_HDR_DSEG_EN, key) == 0) { 497 config->mpw_hdr_dseg = !!tmp; 498 } else if (strcmp(MLX5_TXQ_MAX_INLINE_LEN, key) == 0) { 499 config->inline_max_packet_sz = tmp; 500 } else if (strcmp(MLX5_TX_VEC_EN, key) == 0) { 501 config->tx_vec_en = !!tmp; 502 } else if (strcmp(MLX5_RX_VEC_EN, key) == 0) { 503 config->rx_vec_en = !!tmp; 504 } else if (strcmp(MLX5_L3_VXLAN_EN, key) == 0) { 505 config->l3_vxlan_en = !!tmp; 506 } else if (strcmp(MLX5_VF_NL_EN, key) == 0) { 507 config->vf_nl_en = !!tmp; 508 } else if (strcmp(MLX5_DV_FLOW_EN, key) == 0) { 509 config->dv_flow_en = !!tmp; 510 } else { 511 DRV_LOG(WARNING, "%s: unknown parameter", key); 512 rte_errno = EINVAL; 513 return -rte_errno; 514 } 515 return 0; 516 } 517 518 /** 519 * Parse device parameters. 520 * 521 * @param config 522 * Pointer to device configuration structure. 523 * @param devargs 524 * Device arguments structure. 525 * 526 * @return 527 * 0 on success, a negative errno value otherwise and rte_errno is set. 528 */ 529 static int 530 mlx5_args(struct mlx5_dev_config *config, struct rte_devargs *devargs) 531 { 532 const char **params = (const char *[]){ 533 MLX5_RXQ_CQE_COMP_EN, 534 MLX5_RX_MPRQ_EN, 535 MLX5_RX_MPRQ_LOG_STRIDE_NUM, 536 MLX5_RX_MPRQ_MAX_MEMCPY_LEN, 537 MLX5_RXQS_MIN_MPRQ, 538 MLX5_TXQ_INLINE, 539 MLX5_TXQS_MIN_INLINE, 540 MLX5_TXQ_MPW_EN, 541 MLX5_TXQ_MPW_HDR_DSEG_EN, 542 MLX5_TXQ_MAX_INLINE_LEN, 543 MLX5_TX_VEC_EN, 544 MLX5_RX_VEC_EN, 545 MLX5_L3_VXLAN_EN, 546 MLX5_VF_NL_EN, 547 MLX5_DV_FLOW_EN, 548 MLX5_REPRESENTOR, 549 NULL, 550 }; 551 struct rte_kvargs *kvlist; 552 int ret = 0; 553 int i; 554 555 if (devargs == NULL) 556 return 0; 557 /* Following UGLY cast is done to pass checkpatch. */ 558 kvlist = rte_kvargs_parse(devargs->args, params); 559 if (kvlist == NULL) 560 return 0; 561 /* Process parameters. */ 562 for (i = 0; (params[i] != NULL); ++i) { 563 if (rte_kvargs_count(kvlist, params[i])) { 564 ret = rte_kvargs_process(kvlist, params[i], 565 mlx5_args_check, config); 566 if (ret) { 567 rte_errno = EINVAL; 568 rte_kvargs_free(kvlist); 569 return -rte_errno; 570 } 571 } 572 } 573 rte_kvargs_free(kvlist); 574 return 0; 575 } 576 577 static struct rte_pci_driver mlx5_driver; 578 579 /* 580 * Reserved UAR address space for TXQ UAR(hw doorbell) mapping, process 581 * local resource used by both primary and secondary to avoid duplicate 582 * reservation. 583 * The space has to be available on both primary and secondary process, 584 * TXQ UAR maps to this area using fixed mmap w/o double check. 585 */ 586 static void *uar_base; 587 588 static int 589 find_lower_va_bound(const struct rte_memseg_list *msl, 590 const struct rte_memseg *ms, void *arg) 591 { 592 void **addr = arg; 593 594 if (msl->external) 595 return 0; 596 if (*addr == NULL) 597 *addr = ms->addr; 598 else 599 *addr = RTE_MIN(*addr, ms->addr); 600 601 return 0; 602 } 603 604 /** 605 * Reserve UAR address space for primary process. 606 * 607 * @param[in] dev 608 * Pointer to Ethernet device. 609 * 610 * @return 611 * 0 on success, a negative errno value otherwise and rte_errno is set. 612 */ 613 static int 614 mlx5_uar_init_primary(struct rte_eth_dev *dev) 615 { 616 struct priv *priv = dev->data->dev_private; 617 void *addr = (void *)0; 618 619 if (uar_base) { /* UAR address space mapped. */ 620 priv->uar_base = uar_base; 621 return 0; 622 } 623 /* find out lower bound of hugepage segments */ 624 rte_memseg_walk(find_lower_va_bound, &addr); 625 626 /* keep distance to hugepages to minimize potential conflicts. */ 627 addr = RTE_PTR_SUB(addr, (uintptr_t)(MLX5_UAR_OFFSET + MLX5_UAR_SIZE)); 628 /* anonymous mmap, no real memory consumption. */ 629 addr = mmap(addr, MLX5_UAR_SIZE, 630 PROT_NONE, MAP_PRIVATE | MAP_ANONYMOUS, -1, 0); 631 if (addr == MAP_FAILED) { 632 DRV_LOG(ERR, 633 "port %u failed to reserve UAR address space, please" 634 " adjust MLX5_UAR_SIZE or try --base-virtaddr", 635 dev->data->port_id); 636 rte_errno = ENOMEM; 637 return -rte_errno; 638 } 639 /* Accept either same addr or a new addr returned from mmap if target 640 * range occupied. 641 */ 642 DRV_LOG(INFO, "port %u reserved UAR address space: %p", 643 dev->data->port_id, addr); 644 priv->uar_base = addr; /* for primary and secondary UAR re-mmap. */ 645 uar_base = addr; /* process local, don't reserve again. */ 646 return 0; 647 } 648 649 /** 650 * Reserve UAR address space for secondary process, align with 651 * primary process. 652 * 653 * @param[in] dev 654 * Pointer to Ethernet device. 655 * 656 * @return 657 * 0 on success, a negative errno value otherwise and rte_errno is set. 658 */ 659 static int 660 mlx5_uar_init_secondary(struct rte_eth_dev *dev) 661 { 662 struct priv *priv = dev->data->dev_private; 663 void *addr; 664 665 assert(priv->uar_base); 666 if (uar_base) { /* already reserved. */ 667 assert(uar_base == priv->uar_base); 668 return 0; 669 } 670 /* anonymous mmap, no real memory consumption. */ 671 addr = mmap(priv->uar_base, MLX5_UAR_SIZE, 672 PROT_NONE, MAP_PRIVATE | MAP_ANONYMOUS, -1, 0); 673 if (addr == MAP_FAILED) { 674 DRV_LOG(ERR, "port %u UAR mmap failed: %p size: %llu", 675 dev->data->port_id, priv->uar_base, MLX5_UAR_SIZE); 676 rte_errno = ENXIO; 677 return -rte_errno; 678 } 679 if (priv->uar_base != addr) { 680 DRV_LOG(ERR, 681 "port %u UAR address %p size %llu occupied, please" 682 " adjust MLX5_UAR_OFFSET or try EAL parameter" 683 " --base-virtaddr", 684 dev->data->port_id, priv->uar_base, MLX5_UAR_SIZE); 685 rte_errno = ENXIO; 686 return -rte_errno; 687 } 688 uar_base = addr; /* process local, don't reserve again */ 689 DRV_LOG(INFO, "port %u reserved UAR address space: %p", 690 dev->data->port_id, addr); 691 return 0; 692 } 693 694 /** 695 * Spawn an Ethernet device from Verbs information. 696 * 697 * @param dpdk_dev 698 * Backing DPDK device. 699 * @param ibv_dev 700 * Verbs device. 701 * @param vf 702 * If nonzero, enable VF-specific features. 703 * @param[in] switch_info 704 * Switch properties of Ethernet device. 705 * 706 * @return 707 * A valid Ethernet device object on success, NULL otherwise and rte_errno 708 * is set. The following errors are defined: 709 * 710 * EBUSY: device is not supposed to be spawned. 711 * EEXIST: device is already spawned 712 */ 713 static struct rte_eth_dev * 714 mlx5_dev_spawn(struct rte_device *dpdk_dev, 715 struct ibv_device *ibv_dev, 716 int vf, 717 const struct mlx5_switch_info *switch_info) 718 { 719 struct ibv_context *ctx; 720 struct ibv_device_attr_ex attr; 721 struct ibv_port_attr port_attr; 722 struct ibv_pd *pd = NULL; 723 struct mlx5dv_context dv_attr = { .comp_mask = 0 }; 724 struct mlx5_dev_config config = { 725 .vf = !!vf, 726 .mps = MLX5_ARG_UNSET, 727 .tx_vec_en = 1, 728 .rx_vec_en = 1, 729 .mpw_hdr_dseg = 0, 730 .txq_inline = MLX5_ARG_UNSET, 731 .txqs_inline = MLX5_ARG_UNSET, 732 .inline_max_packet_sz = MLX5_ARG_UNSET, 733 .vf_nl_en = 1, 734 .mprq = { 735 .enabled = 0, 736 .stride_num_n = MLX5_MPRQ_STRIDE_NUM_N, 737 .max_memcpy_len = MLX5_MPRQ_MEMCPY_DEFAULT_LEN, 738 .min_rxqs_num = MLX5_MPRQ_MIN_RXQS, 739 }, 740 }; 741 struct rte_eth_dev *eth_dev = NULL; 742 struct priv *priv = NULL; 743 int err = 0; 744 unsigned int mps; 745 unsigned int cqe_comp; 746 unsigned int tunnel_en = 0; 747 unsigned int mpls_en = 0; 748 unsigned int swp = 0; 749 unsigned int mprq = 0; 750 unsigned int mprq_min_stride_size_n = 0; 751 unsigned int mprq_max_stride_size_n = 0; 752 unsigned int mprq_min_stride_num_n = 0; 753 unsigned int mprq_max_stride_num_n = 0; 754 struct ether_addr mac; 755 char name[RTE_ETH_NAME_MAX_LEN]; 756 int own_domain_id = 0; 757 uint16_t port_id; 758 unsigned int i; 759 760 /* Determine if this port representor is supposed to be spawned. */ 761 if (switch_info->representor && dpdk_dev->devargs) { 762 struct rte_eth_devargs eth_da; 763 764 err = rte_eth_devargs_parse(dpdk_dev->devargs->args, ð_da); 765 if (err) { 766 rte_errno = -err; 767 DRV_LOG(ERR, "failed to process device arguments: %s", 768 strerror(rte_errno)); 769 return NULL; 770 } 771 for (i = 0; i < eth_da.nb_representor_ports; ++i) 772 if (eth_da.representor_ports[i] == 773 (uint16_t)switch_info->port_name) 774 break; 775 if (i == eth_da.nb_representor_ports) { 776 rte_errno = EBUSY; 777 return NULL; 778 } 779 } 780 /* Build device name. */ 781 if (!switch_info->representor) 782 rte_strlcpy(name, dpdk_dev->name, sizeof(name)); 783 else 784 snprintf(name, sizeof(name), "%s_representor_%u", 785 dpdk_dev->name, switch_info->port_name); 786 /* check if the device is already spawned */ 787 if (rte_eth_dev_get_port_by_name(name, &port_id) == 0) { 788 rte_errno = EEXIST; 789 return NULL; 790 } 791 /* Prepare shared data between primary and secondary process. */ 792 mlx5_prepare_shared_data(); 793 errno = 0; 794 ctx = mlx5_glue->open_device(ibv_dev); 795 if (!ctx) { 796 rte_errno = errno ? errno : ENODEV; 797 return NULL; 798 } 799 #ifdef HAVE_IBV_MLX5_MOD_SWP 800 dv_attr.comp_mask |= MLX5DV_CONTEXT_MASK_SWP; 801 #endif 802 /* 803 * Multi-packet send is supported by ConnectX-4 Lx PF as well 804 * as all ConnectX-5 devices. 805 */ 806 #ifdef HAVE_IBV_DEVICE_TUNNEL_SUPPORT 807 dv_attr.comp_mask |= MLX5DV_CONTEXT_MASK_TUNNEL_OFFLOADS; 808 #endif 809 #ifdef HAVE_IBV_DEVICE_STRIDING_RQ_SUPPORT 810 dv_attr.comp_mask |= MLX5DV_CONTEXT_MASK_STRIDING_RQ; 811 #endif 812 mlx5_glue->dv_query_device(ctx, &dv_attr); 813 if (dv_attr.flags & MLX5DV_CONTEXT_FLAGS_MPW_ALLOWED) { 814 if (dv_attr.flags & MLX5DV_CONTEXT_FLAGS_ENHANCED_MPW) { 815 DRV_LOG(DEBUG, "enhanced MPW is supported"); 816 mps = MLX5_MPW_ENHANCED; 817 } else { 818 DRV_LOG(DEBUG, "MPW is supported"); 819 mps = MLX5_MPW; 820 } 821 } else { 822 DRV_LOG(DEBUG, "MPW isn't supported"); 823 mps = MLX5_MPW_DISABLED; 824 } 825 #ifdef HAVE_IBV_MLX5_MOD_SWP 826 if (dv_attr.comp_mask & MLX5DV_CONTEXT_MASK_SWP) 827 swp = dv_attr.sw_parsing_caps.sw_parsing_offloads; 828 DRV_LOG(DEBUG, "SWP support: %u", swp); 829 #endif 830 config.swp = !!swp; 831 #ifdef HAVE_IBV_DEVICE_STRIDING_RQ_SUPPORT 832 if (dv_attr.comp_mask & MLX5DV_CONTEXT_MASK_STRIDING_RQ) { 833 struct mlx5dv_striding_rq_caps mprq_caps = 834 dv_attr.striding_rq_caps; 835 836 DRV_LOG(DEBUG, "\tmin_single_stride_log_num_of_bytes: %d", 837 mprq_caps.min_single_stride_log_num_of_bytes); 838 DRV_LOG(DEBUG, "\tmax_single_stride_log_num_of_bytes: %d", 839 mprq_caps.max_single_stride_log_num_of_bytes); 840 DRV_LOG(DEBUG, "\tmin_single_wqe_log_num_of_strides: %d", 841 mprq_caps.min_single_wqe_log_num_of_strides); 842 DRV_LOG(DEBUG, "\tmax_single_wqe_log_num_of_strides: %d", 843 mprq_caps.max_single_wqe_log_num_of_strides); 844 DRV_LOG(DEBUG, "\tsupported_qpts: %d", 845 mprq_caps.supported_qpts); 846 DRV_LOG(DEBUG, "device supports Multi-Packet RQ"); 847 mprq = 1; 848 mprq_min_stride_size_n = 849 mprq_caps.min_single_stride_log_num_of_bytes; 850 mprq_max_stride_size_n = 851 mprq_caps.max_single_stride_log_num_of_bytes; 852 mprq_min_stride_num_n = 853 mprq_caps.min_single_wqe_log_num_of_strides; 854 mprq_max_stride_num_n = 855 mprq_caps.max_single_wqe_log_num_of_strides; 856 config.mprq.stride_num_n = RTE_MAX(MLX5_MPRQ_STRIDE_NUM_N, 857 mprq_min_stride_num_n); 858 } 859 #endif 860 if (RTE_CACHE_LINE_SIZE == 128 && 861 !(dv_attr.flags & MLX5DV_CONTEXT_FLAGS_CQE_128B_COMP)) 862 cqe_comp = 0; 863 else 864 cqe_comp = 1; 865 config.cqe_comp = cqe_comp; 866 #ifdef HAVE_IBV_DEVICE_TUNNEL_SUPPORT 867 if (dv_attr.comp_mask & MLX5DV_CONTEXT_MASK_TUNNEL_OFFLOADS) { 868 tunnel_en = ((dv_attr.tunnel_offloads_caps & 869 MLX5DV_RAW_PACKET_CAP_TUNNELED_OFFLOAD_VXLAN) && 870 (dv_attr.tunnel_offloads_caps & 871 MLX5DV_RAW_PACKET_CAP_TUNNELED_OFFLOAD_GRE)); 872 } 873 DRV_LOG(DEBUG, "tunnel offloading is %ssupported", 874 tunnel_en ? "" : "not "); 875 #else 876 DRV_LOG(WARNING, 877 "tunnel offloading disabled due to old OFED/rdma-core version"); 878 #endif 879 config.tunnel_en = tunnel_en; 880 #ifdef HAVE_IBV_DEVICE_MPLS_SUPPORT 881 mpls_en = ((dv_attr.tunnel_offloads_caps & 882 MLX5DV_RAW_PACKET_CAP_TUNNELED_OFFLOAD_CW_MPLS_OVER_GRE) && 883 (dv_attr.tunnel_offloads_caps & 884 MLX5DV_RAW_PACKET_CAP_TUNNELED_OFFLOAD_CW_MPLS_OVER_UDP)); 885 DRV_LOG(DEBUG, "MPLS over GRE/UDP tunnel offloading is %ssupported", 886 mpls_en ? "" : "not "); 887 #else 888 DRV_LOG(WARNING, "MPLS over GRE/UDP tunnel offloading disabled due to" 889 " old OFED/rdma-core version or firmware configuration"); 890 #endif 891 config.mpls_en = mpls_en; 892 err = mlx5_glue->query_device_ex(ctx, NULL, &attr); 893 if (err) { 894 DEBUG("ibv_query_device_ex() failed"); 895 goto error; 896 } 897 DRV_LOG(DEBUG, "naming Ethernet device \"%s\"", name); 898 if (rte_eal_process_type() == RTE_PROC_SECONDARY) { 899 eth_dev = rte_eth_dev_attach_secondary(name); 900 if (eth_dev == NULL) { 901 DRV_LOG(ERR, "can not attach rte ethdev"); 902 rte_errno = ENOMEM; 903 err = rte_errno; 904 goto error; 905 } 906 eth_dev->device = dpdk_dev; 907 eth_dev->dev_ops = &mlx5_dev_sec_ops; 908 err = mlx5_uar_init_secondary(eth_dev); 909 if (err) { 910 err = rte_errno; 911 goto error; 912 } 913 /* Receive command fd from primary process */ 914 err = mlx5_socket_connect(eth_dev); 915 if (err < 0) { 916 err = rte_errno; 917 goto error; 918 } 919 /* Remap UAR for Tx queues. */ 920 err = mlx5_tx_uar_remap(eth_dev, err); 921 if (err) { 922 err = rte_errno; 923 goto error; 924 } 925 /* 926 * Ethdev pointer is still required as input since 927 * the primary device is not accessible from the 928 * secondary process. 929 */ 930 eth_dev->rx_pkt_burst = mlx5_select_rx_function(eth_dev); 931 eth_dev->tx_pkt_burst = mlx5_select_tx_function(eth_dev); 932 claim_zero(mlx5_glue->close_device(ctx)); 933 return eth_dev; 934 } 935 /* Check port status. */ 936 err = mlx5_glue->query_port(ctx, 1, &port_attr); 937 if (err) { 938 DRV_LOG(ERR, "port query failed: %s", strerror(err)); 939 goto error; 940 } 941 if (port_attr.link_layer != IBV_LINK_LAYER_ETHERNET) { 942 DRV_LOG(ERR, "port is not configured in Ethernet mode"); 943 err = EINVAL; 944 goto error; 945 } 946 if (port_attr.state != IBV_PORT_ACTIVE) 947 DRV_LOG(DEBUG, "port is not active: \"%s\" (%d)", 948 mlx5_glue->port_state_str(port_attr.state), 949 port_attr.state); 950 /* Allocate protection domain. */ 951 pd = mlx5_glue->alloc_pd(ctx); 952 if (pd == NULL) { 953 DRV_LOG(ERR, "PD allocation failure"); 954 err = ENOMEM; 955 goto error; 956 } 957 priv = rte_zmalloc("ethdev private structure", 958 sizeof(*priv), 959 RTE_CACHE_LINE_SIZE); 960 if (priv == NULL) { 961 DRV_LOG(ERR, "priv allocation failure"); 962 err = ENOMEM; 963 goto error; 964 } 965 priv->ctx = ctx; 966 strncpy(priv->ibdev_name, priv->ctx->device->name, 967 sizeof(priv->ibdev_name)); 968 strncpy(priv->ibdev_path, priv->ctx->device->ibdev_path, 969 sizeof(priv->ibdev_path)); 970 priv->device_attr = attr; 971 priv->pd = pd; 972 priv->mtu = ETHER_MTU; 973 #ifndef RTE_ARCH_64 974 /* Initialize UAR access locks for 32bit implementations. */ 975 rte_spinlock_init(&priv->uar_lock_cq); 976 for (i = 0; i < MLX5_UAR_PAGE_NUM_MAX; i++) 977 rte_spinlock_init(&priv->uar_lock[i]); 978 #endif 979 /* Some internal functions rely on Netlink sockets, open them now. */ 980 priv->nl_socket_rdma = mlx5_nl_init(NETLINK_RDMA); 981 priv->nl_socket_route = mlx5_nl_init(NETLINK_ROUTE); 982 priv->nl_sn = 0; 983 priv->representor = !!switch_info->representor; 984 priv->domain_id = RTE_ETH_DEV_SWITCH_DOMAIN_ID_INVALID; 985 priv->representor_id = 986 switch_info->representor ? switch_info->port_name : -1; 987 /* 988 * Look for sibling devices in order to reuse their switch domain 989 * if any, otherwise allocate one. 990 */ 991 i = mlx5_dev_to_port_id(dpdk_dev, NULL, 0); 992 if (i > 0) { 993 uint16_t port_id[i]; 994 995 i = RTE_MIN(mlx5_dev_to_port_id(dpdk_dev, port_id, i), i); 996 while (i--) { 997 const struct priv *opriv = 998 rte_eth_devices[port_id[i]].data->dev_private; 999 1000 if (!opriv || 1001 opriv->domain_id == 1002 RTE_ETH_DEV_SWITCH_DOMAIN_ID_INVALID) 1003 continue; 1004 priv->domain_id = opriv->domain_id; 1005 break; 1006 } 1007 } 1008 if (priv->domain_id == RTE_ETH_DEV_SWITCH_DOMAIN_ID_INVALID) { 1009 err = rte_eth_switch_domain_alloc(&priv->domain_id); 1010 if (err) { 1011 err = rte_errno; 1012 DRV_LOG(ERR, "unable to allocate switch domain: %s", 1013 strerror(rte_errno)); 1014 goto error; 1015 } 1016 own_domain_id = 1; 1017 } 1018 err = mlx5_args(&config, dpdk_dev->devargs); 1019 if (err) { 1020 err = rte_errno; 1021 DRV_LOG(ERR, "failed to process device arguments: %s", 1022 strerror(rte_errno)); 1023 goto error; 1024 } 1025 config.hw_csum = !!(attr.device_cap_flags_ex & IBV_DEVICE_RAW_IP_CSUM); 1026 DRV_LOG(DEBUG, "checksum offloading is %ssupported", 1027 (config.hw_csum ? "" : "not ")); 1028 #if !defined(HAVE_IBV_DEVICE_COUNTERS_SET_V42) && \ 1029 !defined(HAVE_IBV_DEVICE_COUNTERS_SET_V45) 1030 DRV_LOG(DEBUG, "counters are not supported"); 1031 #endif 1032 #ifndef HAVE_IBV_FLOW_DV_SUPPORT 1033 if (config.dv_flow_en) { 1034 DRV_LOG(WARNING, "DV flow is not supported"); 1035 config.dv_flow_en = 0; 1036 } 1037 #endif 1038 config.ind_table_max_size = 1039 attr.rss_caps.max_rwq_indirection_table_size; 1040 /* 1041 * Remove this check once DPDK supports larger/variable 1042 * indirection tables. 1043 */ 1044 if (config.ind_table_max_size > (unsigned int)ETH_RSS_RETA_SIZE_512) 1045 config.ind_table_max_size = ETH_RSS_RETA_SIZE_512; 1046 DRV_LOG(DEBUG, "maximum Rx indirection table size is %u", 1047 config.ind_table_max_size); 1048 config.hw_vlan_strip = !!(attr.raw_packet_caps & 1049 IBV_RAW_PACKET_CAP_CVLAN_STRIPPING); 1050 DRV_LOG(DEBUG, "VLAN stripping is %ssupported", 1051 (config.hw_vlan_strip ? "" : "not ")); 1052 config.hw_fcs_strip = !!(attr.raw_packet_caps & 1053 IBV_RAW_PACKET_CAP_SCATTER_FCS); 1054 DRV_LOG(DEBUG, "FCS stripping configuration is %ssupported", 1055 (config.hw_fcs_strip ? "" : "not ")); 1056 #ifdef HAVE_IBV_WQ_FLAG_RX_END_PADDING 1057 config.hw_padding = !!attr.rx_pad_end_addr_align; 1058 #endif 1059 DRV_LOG(DEBUG, "hardware Rx end alignment padding is %ssupported", 1060 (config.hw_padding ? "" : "not ")); 1061 config.tso = (attr.tso_caps.max_tso > 0 && 1062 (attr.tso_caps.supported_qpts & 1063 (1 << IBV_QPT_RAW_PACKET))); 1064 if (config.tso) 1065 config.tso_max_payload_sz = attr.tso_caps.max_tso; 1066 /* 1067 * MPW is disabled by default, while the Enhanced MPW is enabled 1068 * by default. 1069 */ 1070 if (config.mps == MLX5_ARG_UNSET) 1071 config.mps = (mps == MLX5_MPW_ENHANCED) ? MLX5_MPW_ENHANCED : 1072 MLX5_MPW_DISABLED; 1073 else 1074 config.mps = config.mps ? mps : MLX5_MPW_DISABLED; 1075 DRV_LOG(INFO, "%sMPS is %s", 1076 config.mps == MLX5_MPW_ENHANCED ? "enhanced " : "", 1077 config.mps != MLX5_MPW_DISABLED ? "enabled" : "disabled"); 1078 if (config.cqe_comp && !cqe_comp) { 1079 DRV_LOG(WARNING, "Rx CQE compression isn't supported"); 1080 config.cqe_comp = 0; 1081 } 1082 if (config.mprq.enabled && mprq) { 1083 if (config.mprq.stride_num_n > mprq_max_stride_num_n || 1084 config.mprq.stride_num_n < mprq_min_stride_num_n) { 1085 config.mprq.stride_num_n = 1086 RTE_MAX(MLX5_MPRQ_STRIDE_NUM_N, 1087 mprq_min_stride_num_n); 1088 DRV_LOG(WARNING, 1089 "the number of strides" 1090 " for Multi-Packet RQ is out of range," 1091 " setting default value (%u)", 1092 1 << config.mprq.stride_num_n); 1093 } 1094 config.mprq.min_stride_size_n = mprq_min_stride_size_n; 1095 config.mprq.max_stride_size_n = mprq_max_stride_size_n; 1096 } else if (config.mprq.enabled && !mprq) { 1097 DRV_LOG(WARNING, "Multi-Packet RQ isn't supported"); 1098 config.mprq.enabled = 0; 1099 } 1100 eth_dev = rte_eth_dev_allocate(name); 1101 if (eth_dev == NULL) { 1102 DRV_LOG(ERR, "can not allocate rte ethdev"); 1103 err = ENOMEM; 1104 goto error; 1105 } 1106 if (priv->representor) { 1107 eth_dev->data->dev_flags |= RTE_ETH_DEV_REPRESENTOR; 1108 eth_dev->data->representor_id = priv->representor_id; 1109 } 1110 eth_dev->data->dev_private = priv; 1111 priv->dev_data = eth_dev->data; 1112 eth_dev->data->mac_addrs = priv->mac; 1113 eth_dev->device = dpdk_dev; 1114 err = mlx5_uar_init_primary(eth_dev); 1115 if (err) { 1116 err = rte_errno; 1117 goto error; 1118 } 1119 /* Configure the first MAC address by default. */ 1120 if (mlx5_get_mac(eth_dev, &mac.addr_bytes)) { 1121 DRV_LOG(ERR, 1122 "port %u cannot get MAC address, is mlx5_en" 1123 " loaded? (errno: %s)", 1124 eth_dev->data->port_id, strerror(rte_errno)); 1125 err = ENODEV; 1126 goto error; 1127 } 1128 DRV_LOG(INFO, 1129 "port %u MAC address is %02x:%02x:%02x:%02x:%02x:%02x", 1130 eth_dev->data->port_id, 1131 mac.addr_bytes[0], mac.addr_bytes[1], 1132 mac.addr_bytes[2], mac.addr_bytes[3], 1133 mac.addr_bytes[4], mac.addr_bytes[5]); 1134 #ifndef NDEBUG 1135 { 1136 char ifname[IF_NAMESIZE]; 1137 1138 if (mlx5_get_ifname(eth_dev, &ifname) == 0) 1139 DRV_LOG(DEBUG, "port %u ifname is \"%s\"", 1140 eth_dev->data->port_id, ifname); 1141 else 1142 DRV_LOG(DEBUG, "port %u ifname is unknown", 1143 eth_dev->data->port_id); 1144 } 1145 #endif 1146 /* Get actual MTU if possible. */ 1147 err = mlx5_get_mtu(eth_dev, &priv->mtu); 1148 if (err) { 1149 err = rte_errno; 1150 goto error; 1151 } 1152 DRV_LOG(DEBUG, "port %u MTU is %u", eth_dev->data->port_id, 1153 priv->mtu); 1154 /* Initialize burst functions to prevent crashes before link-up. */ 1155 eth_dev->rx_pkt_burst = removed_rx_burst; 1156 eth_dev->tx_pkt_burst = removed_tx_burst; 1157 eth_dev->dev_ops = &mlx5_dev_ops; 1158 /* Register MAC address. */ 1159 claim_zero(mlx5_mac_addr_add(eth_dev, &mac, 0, 0)); 1160 if (vf && config.vf_nl_en) 1161 mlx5_nl_mac_addr_sync(eth_dev); 1162 priv->tcf_context = mlx5_flow_tcf_context_create(); 1163 if (!priv->tcf_context) { 1164 err = -rte_errno; 1165 DRV_LOG(WARNING, 1166 "flow rules relying on switch offloads will not be" 1167 " supported: cannot open libmnl socket: %s", 1168 strerror(rte_errno)); 1169 } else { 1170 struct rte_flow_error error; 1171 unsigned int ifindex = mlx5_ifindex(eth_dev); 1172 1173 if (!ifindex) { 1174 err = -rte_errno; 1175 error.message = 1176 "cannot retrieve network interface index"; 1177 } else { 1178 err = mlx5_flow_tcf_init(priv->tcf_context, 1179 ifindex, &error); 1180 } 1181 if (err) { 1182 DRV_LOG(WARNING, 1183 "flow rules relying on switch offloads will" 1184 " not be supported: %s: %s", 1185 error.message, strerror(rte_errno)); 1186 mlx5_flow_tcf_context_destroy(priv->tcf_context); 1187 priv->tcf_context = NULL; 1188 } 1189 } 1190 TAILQ_INIT(&priv->flows); 1191 TAILQ_INIT(&priv->ctrl_flows); 1192 /* Hint libmlx5 to use PMD allocator for data plane resources */ 1193 struct mlx5dv_ctx_allocators alctr = { 1194 .alloc = &mlx5_alloc_verbs_buf, 1195 .free = &mlx5_free_verbs_buf, 1196 .data = priv, 1197 }; 1198 mlx5_glue->dv_set_context_attr(ctx, MLX5DV_CTX_ATTR_BUF_ALLOCATORS, 1199 (void *)((uintptr_t)&alctr)); 1200 /* Bring Ethernet device up. */ 1201 DRV_LOG(DEBUG, "port %u forcing Ethernet interface up", 1202 eth_dev->data->port_id); 1203 mlx5_set_link_up(eth_dev); 1204 /* 1205 * Even though the interrupt handler is not installed yet, 1206 * interrupts will still trigger on the asyn_fd from 1207 * Verbs context returned by ibv_open_device(). 1208 */ 1209 mlx5_link_update(eth_dev, 0); 1210 /* Store device configuration on private structure. */ 1211 priv->config = config; 1212 /* Supported Verbs flow priority number detection. */ 1213 err = mlx5_flow_discover_priorities(eth_dev); 1214 if (err < 0) 1215 goto error; 1216 priv->config.flow_prio = err; 1217 /* 1218 * Once the device is added to the list of memory event 1219 * callback, its global MR cache table cannot be expanded 1220 * on the fly because of deadlock. If it overflows, lookup 1221 * should be done by searching MR list linearly, which is slow. 1222 */ 1223 err = mlx5_mr_btree_init(&priv->mr.cache, 1224 MLX5_MR_BTREE_CACHE_N * 2, 1225 eth_dev->device->numa_node); 1226 if (err) { 1227 err = rte_errno; 1228 goto error; 1229 } 1230 /* Add device to memory callback list. */ 1231 rte_rwlock_write_lock(&mlx5_shared_data->mem_event_rwlock); 1232 LIST_INSERT_HEAD(&mlx5_shared_data->mem_event_cb_list, 1233 priv, mem_event_cb); 1234 rte_rwlock_write_unlock(&mlx5_shared_data->mem_event_rwlock); 1235 return eth_dev; 1236 error: 1237 if (priv) { 1238 if (priv->nl_socket_route >= 0) 1239 close(priv->nl_socket_route); 1240 if (priv->nl_socket_rdma >= 0) 1241 close(priv->nl_socket_rdma); 1242 if (priv->tcf_context) 1243 mlx5_flow_tcf_context_destroy(priv->tcf_context); 1244 if (own_domain_id) 1245 claim_zero(rte_eth_switch_domain_free(priv->domain_id)); 1246 rte_free(priv); 1247 if (eth_dev != NULL) 1248 eth_dev->data->dev_private = NULL; 1249 } 1250 if (pd) 1251 claim_zero(mlx5_glue->dealloc_pd(pd)); 1252 if (eth_dev != NULL) { 1253 /* mac_addrs must not be freed alone because part of dev_private */ 1254 eth_dev->data->mac_addrs = NULL; 1255 rte_eth_dev_release_port(eth_dev); 1256 } 1257 if (ctx) 1258 claim_zero(mlx5_glue->close_device(ctx)); 1259 assert(err > 0); 1260 rte_errno = err; 1261 return NULL; 1262 } 1263 1264 /** Data associated with devices to spawn. */ 1265 struct mlx5_dev_spawn_data { 1266 unsigned int ifindex; /**< Network interface index. */ 1267 struct mlx5_switch_info info; /**< Switch information. */ 1268 struct ibv_device *ibv_dev; /**< Associated IB device. */ 1269 struct rte_eth_dev *eth_dev; /**< Associated Ethernet device. */ 1270 }; 1271 1272 /** 1273 * Comparison callback to sort device data. 1274 * 1275 * This is meant to be used with qsort(). 1276 * 1277 * @param a[in] 1278 * Pointer to pointer to first data object. 1279 * @param b[in] 1280 * Pointer to pointer to second data object. 1281 * 1282 * @return 1283 * 0 if both objects are equal, less than 0 if the first argument is less 1284 * than the second, greater than 0 otherwise. 1285 */ 1286 static int 1287 mlx5_dev_spawn_data_cmp(const void *a, const void *b) 1288 { 1289 const struct mlx5_switch_info *si_a = 1290 &((const struct mlx5_dev_spawn_data *)a)->info; 1291 const struct mlx5_switch_info *si_b = 1292 &((const struct mlx5_dev_spawn_data *)b)->info; 1293 int ret; 1294 1295 /* Master device first. */ 1296 ret = si_b->master - si_a->master; 1297 if (ret) 1298 return ret; 1299 /* Then representor devices. */ 1300 ret = si_b->representor - si_a->representor; 1301 if (ret) 1302 return ret; 1303 /* Unidentified devices come last in no specific order. */ 1304 if (!si_a->representor) 1305 return 0; 1306 /* Order representors by name. */ 1307 return si_a->port_name - si_b->port_name; 1308 } 1309 1310 /** 1311 * DPDK callback to register a PCI device. 1312 * 1313 * This function spawns Ethernet devices out of a given PCI device. 1314 * 1315 * @param[in] pci_drv 1316 * PCI driver structure (mlx5_driver). 1317 * @param[in] pci_dev 1318 * PCI device information. 1319 * 1320 * @return 1321 * 0 on success, a negative errno value otherwise and rte_errno is set. 1322 */ 1323 static int 1324 mlx5_pci_probe(struct rte_pci_driver *pci_drv __rte_unused, 1325 struct rte_pci_device *pci_dev) 1326 { 1327 struct ibv_device **ibv_list; 1328 unsigned int n = 0; 1329 int vf; 1330 int ret; 1331 1332 assert(pci_drv == &mlx5_driver); 1333 errno = 0; 1334 ibv_list = mlx5_glue->get_device_list(&ret); 1335 if (!ibv_list) { 1336 rte_errno = errno ? errno : ENOSYS; 1337 DRV_LOG(ERR, "cannot list devices, is ib_uverbs loaded?"); 1338 return -rte_errno; 1339 } 1340 1341 struct ibv_device *ibv_match[ret + 1]; 1342 1343 while (ret-- > 0) { 1344 struct rte_pci_addr pci_addr; 1345 1346 DRV_LOG(DEBUG, "checking device \"%s\"", ibv_list[ret]->name); 1347 if (mlx5_ibv_device_to_pci_addr(ibv_list[ret], &pci_addr)) 1348 continue; 1349 if (pci_dev->addr.domain != pci_addr.domain || 1350 pci_dev->addr.bus != pci_addr.bus || 1351 pci_dev->addr.devid != pci_addr.devid || 1352 pci_dev->addr.function != pci_addr.function) 1353 continue; 1354 DRV_LOG(INFO, "PCI information matches for device \"%s\"", 1355 ibv_list[ret]->name); 1356 ibv_match[n++] = ibv_list[ret]; 1357 } 1358 ibv_match[n] = NULL; 1359 1360 struct mlx5_dev_spawn_data list[n]; 1361 int nl_route = n ? mlx5_nl_init(NETLINK_ROUTE) : -1; 1362 int nl_rdma = n ? mlx5_nl_init(NETLINK_RDMA) : -1; 1363 unsigned int i; 1364 unsigned int u; 1365 1366 /* 1367 * The existence of several matching entries (n > 1) means port 1368 * representors have been instantiated. No existing Verbs call nor 1369 * /sys entries can tell them apart, this can only be done through 1370 * Netlink calls assuming kernel drivers are recent enough to 1371 * support them. 1372 * 1373 * In the event of identification failure through Netlink, try again 1374 * through sysfs, then either: 1375 * 1376 * 1. No device matches (n == 0), complain and bail out. 1377 * 2. A single IB device matches (n == 1) and is not a representor, 1378 * assume no switch support. 1379 * 3. Otherwise no safe assumptions can be made; complain louder and 1380 * bail out. 1381 */ 1382 for (i = 0; i != n; ++i) { 1383 list[i].ibv_dev = ibv_match[i]; 1384 list[i].eth_dev = NULL; 1385 if (nl_rdma < 0) 1386 list[i].ifindex = 0; 1387 else 1388 list[i].ifindex = mlx5_nl_ifindex 1389 (nl_rdma, list[i].ibv_dev->name); 1390 if (nl_route < 0 || 1391 !list[i].ifindex || 1392 mlx5_nl_switch_info(nl_route, list[i].ifindex, 1393 &list[i].info) || 1394 ((!list[i].info.representor && !list[i].info.master) && 1395 mlx5_sysfs_switch_info(list[i].ifindex, &list[i].info))) { 1396 list[i].ifindex = 0; 1397 memset(&list[i].info, 0, sizeof(list[i].info)); 1398 continue; 1399 } 1400 } 1401 if (nl_rdma >= 0) 1402 close(nl_rdma); 1403 if (nl_route >= 0) 1404 close(nl_route); 1405 /* Count unidentified devices. */ 1406 for (u = 0, i = 0; i != n; ++i) 1407 if (!list[i].info.master && !list[i].info.representor) 1408 ++u; 1409 if (u) { 1410 if (n == 1 && u == 1) { 1411 /* Case #2. */ 1412 DRV_LOG(INFO, "no switch support detected"); 1413 } else { 1414 /* Case #3. */ 1415 DRV_LOG(ERR, 1416 "unable to tell which of the matching devices" 1417 " is the master (lack of kernel support?)"); 1418 n = 0; 1419 } 1420 } 1421 /* 1422 * Sort list to probe devices in natural order for users convenience 1423 * (i.e. master first, then representors from lowest to highest ID). 1424 */ 1425 if (n) 1426 qsort(list, n, sizeof(*list), mlx5_dev_spawn_data_cmp); 1427 switch (pci_dev->id.device_id) { 1428 case PCI_DEVICE_ID_MELLANOX_CONNECTX4VF: 1429 case PCI_DEVICE_ID_MELLANOX_CONNECTX4LXVF: 1430 case PCI_DEVICE_ID_MELLANOX_CONNECTX5VF: 1431 case PCI_DEVICE_ID_MELLANOX_CONNECTX5EXVF: 1432 vf = 1; 1433 break; 1434 default: 1435 vf = 0; 1436 } 1437 for (i = 0; i != n; ++i) { 1438 uint32_t restore; 1439 1440 list[i].eth_dev = mlx5_dev_spawn 1441 (&pci_dev->device, list[i].ibv_dev, vf, &list[i].info); 1442 if (!list[i].eth_dev) { 1443 if (rte_errno != EBUSY && rte_errno != EEXIST) 1444 break; 1445 /* Device is disabled or already spawned. Ignore it. */ 1446 continue; 1447 } 1448 restore = list[i].eth_dev->data->dev_flags; 1449 rte_eth_copy_pci_info(list[i].eth_dev, pci_dev); 1450 /* Restore non-PCI flags cleared by the above call. */ 1451 list[i].eth_dev->data->dev_flags |= restore; 1452 rte_eth_dev_probing_finish(list[i].eth_dev); 1453 } 1454 mlx5_glue->free_device_list(ibv_list); 1455 if (!n) { 1456 DRV_LOG(WARNING, 1457 "no Verbs device matches PCI device " PCI_PRI_FMT "," 1458 " are kernel drivers loaded?", 1459 pci_dev->addr.domain, pci_dev->addr.bus, 1460 pci_dev->addr.devid, pci_dev->addr.function); 1461 rte_errno = ENOENT; 1462 ret = -rte_errno; 1463 } else if (i != n) { 1464 DRV_LOG(ERR, 1465 "probe of PCI device " PCI_PRI_FMT " aborted after" 1466 " encountering an error: %s", 1467 pci_dev->addr.domain, pci_dev->addr.bus, 1468 pci_dev->addr.devid, pci_dev->addr.function, 1469 strerror(rte_errno)); 1470 ret = -rte_errno; 1471 /* Roll back. */ 1472 while (i--) { 1473 if (!list[i].eth_dev) 1474 continue; 1475 mlx5_dev_close(list[i].eth_dev); 1476 /* mac_addrs must not be freed because in dev_private */ 1477 list[i].eth_dev->data->mac_addrs = NULL; 1478 claim_zero(rte_eth_dev_release_port(list[i].eth_dev)); 1479 } 1480 /* Restore original error. */ 1481 rte_errno = -ret; 1482 } else { 1483 ret = 0; 1484 } 1485 return ret; 1486 } 1487 1488 /** 1489 * DPDK callback to remove a PCI device. 1490 * 1491 * This function removes all Ethernet devices belong to a given PCI device. 1492 * 1493 * @param[in] pci_dev 1494 * Pointer to the PCI device. 1495 * 1496 * @return 1497 * 0 on success, the function cannot fail. 1498 */ 1499 static int 1500 mlx5_pci_remove(struct rte_pci_device *pci_dev) 1501 { 1502 uint16_t port_id; 1503 struct rte_eth_dev *port; 1504 1505 for (port_id = 0; port_id < RTE_MAX_ETHPORTS; port_id++) { 1506 port = &rte_eth_devices[port_id]; 1507 if (port->state != RTE_ETH_DEV_UNUSED && 1508 port->device == &pci_dev->device) 1509 rte_eth_dev_close(port_id); 1510 } 1511 return 0; 1512 } 1513 1514 static const struct rte_pci_id mlx5_pci_id_map[] = { 1515 { 1516 RTE_PCI_DEVICE(PCI_VENDOR_ID_MELLANOX, 1517 PCI_DEVICE_ID_MELLANOX_CONNECTX4) 1518 }, 1519 { 1520 RTE_PCI_DEVICE(PCI_VENDOR_ID_MELLANOX, 1521 PCI_DEVICE_ID_MELLANOX_CONNECTX4VF) 1522 }, 1523 { 1524 RTE_PCI_DEVICE(PCI_VENDOR_ID_MELLANOX, 1525 PCI_DEVICE_ID_MELLANOX_CONNECTX4LX) 1526 }, 1527 { 1528 RTE_PCI_DEVICE(PCI_VENDOR_ID_MELLANOX, 1529 PCI_DEVICE_ID_MELLANOX_CONNECTX4LXVF) 1530 }, 1531 { 1532 RTE_PCI_DEVICE(PCI_VENDOR_ID_MELLANOX, 1533 PCI_DEVICE_ID_MELLANOX_CONNECTX5) 1534 }, 1535 { 1536 RTE_PCI_DEVICE(PCI_VENDOR_ID_MELLANOX, 1537 PCI_DEVICE_ID_MELLANOX_CONNECTX5VF) 1538 }, 1539 { 1540 RTE_PCI_DEVICE(PCI_VENDOR_ID_MELLANOX, 1541 PCI_DEVICE_ID_MELLANOX_CONNECTX5EX) 1542 }, 1543 { 1544 RTE_PCI_DEVICE(PCI_VENDOR_ID_MELLANOX, 1545 PCI_DEVICE_ID_MELLANOX_CONNECTX5EXVF) 1546 }, 1547 { 1548 RTE_PCI_DEVICE(PCI_VENDOR_ID_MELLANOX, 1549 PCI_DEVICE_ID_MELLANOX_CONNECTX5BF) 1550 }, 1551 { 1552 RTE_PCI_DEVICE(PCI_VENDOR_ID_MELLANOX, 1553 PCI_DEVICE_ID_MELLANOX_CONNECTX5BFVF) 1554 }, 1555 { 1556 .vendor_id = 0 1557 } 1558 }; 1559 1560 static struct rte_pci_driver mlx5_driver = { 1561 .driver = { 1562 .name = MLX5_DRIVER_NAME 1563 }, 1564 .id_table = mlx5_pci_id_map, 1565 .probe = mlx5_pci_probe, 1566 .remove = mlx5_pci_remove, 1567 .drv_flags = (RTE_PCI_DRV_INTR_LSC | RTE_PCI_DRV_INTR_RMV | 1568 RTE_PCI_DRV_PROBE_AGAIN), 1569 }; 1570 1571 #ifdef RTE_LIBRTE_MLX5_DLOPEN_DEPS 1572 1573 /** 1574 * Suffix RTE_EAL_PMD_PATH with "-glue". 1575 * 1576 * This function performs a sanity check on RTE_EAL_PMD_PATH before 1577 * suffixing its last component. 1578 * 1579 * @param buf[out] 1580 * Output buffer, should be large enough otherwise NULL is returned. 1581 * @param size 1582 * Size of @p out. 1583 * 1584 * @return 1585 * Pointer to @p buf or @p NULL in case suffix cannot be appended. 1586 */ 1587 static char * 1588 mlx5_glue_path(char *buf, size_t size) 1589 { 1590 static const char *const bad[] = { "/", ".", "..", NULL }; 1591 const char *path = RTE_EAL_PMD_PATH; 1592 size_t len = strlen(path); 1593 size_t off; 1594 int i; 1595 1596 while (len && path[len - 1] == '/') 1597 --len; 1598 for (off = len; off && path[off - 1] != '/'; --off) 1599 ; 1600 for (i = 0; bad[i]; ++i) 1601 if (!strncmp(path + off, bad[i], (int)(len - off))) 1602 goto error; 1603 i = snprintf(buf, size, "%.*s-glue", (int)len, path); 1604 if (i == -1 || (size_t)i >= size) 1605 goto error; 1606 return buf; 1607 error: 1608 DRV_LOG(ERR, 1609 "unable to append \"-glue\" to last component of" 1610 " RTE_EAL_PMD_PATH (\"" RTE_EAL_PMD_PATH "\")," 1611 " please re-configure DPDK"); 1612 return NULL; 1613 } 1614 1615 /** 1616 * Initialization routine for run-time dependency on rdma-core. 1617 */ 1618 static int 1619 mlx5_glue_init(void) 1620 { 1621 char glue_path[sizeof(RTE_EAL_PMD_PATH) - 1 + sizeof("-glue")]; 1622 const char *path[] = { 1623 /* 1624 * A basic security check is necessary before trusting 1625 * MLX5_GLUE_PATH, which may override RTE_EAL_PMD_PATH. 1626 */ 1627 (geteuid() == getuid() && getegid() == getgid() ? 1628 getenv("MLX5_GLUE_PATH") : NULL), 1629 /* 1630 * When RTE_EAL_PMD_PATH is set, use its glue-suffixed 1631 * variant, otherwise let dlopen() look up libraries on its 1632 * own. 1633 */ 1634 (*RTE_EAL_PMD_PATH ? 1635 mlx5_glue_path(glue_path, sizeof(glue_path)) : ""), 1636 }; 1637 unsigned int i = 0; 1638 void *handle = NULL; 1639 void **sym; 1640 const char *dlmsg; 1641 1642 while (!handle && i != RTE_DIM(path)) { 1643 const char *end; 1644 size_t len; 1645 int ret; 1646 1647 if (!path[i]) { 1648 ++i; 1649 continue; 1650 } 1651 end = strpbrk(path[i], ":;"); 1652 if (!end) 1653 end = path[i] + strlen(path[i]); 1654 len = end - path[i]; 1655 ret = 0; 1656 do { 1657 char name[ret + 1]; 1658 1659 ret = snprintf(name, sizeof(name), "%.*s%s" MLX5_GLUE, 1660 (int)len, path[i], 1661 (!len || *(end - 1) == '/') ? "" : "/"); 1662 if (ret == -1) 1663 break; 1664 if (sizeof(name) != (size_t)ret + 1) 1665 continue; 1666 DRV_LOG(DEBUG, "looking for rdma-core glue as \"%s\"", 1667 name); 1668 handle = dlopen(name, RTLD_LAZY); 1669 break; 1670 } while (1); 1671 path[i] = end + 1; 1672 if (!*end) 1673 ++i; 1674 } 1675 if (!handle) { 1676 rte_errno = EINVAL; 1677 dlmsg = dlerror(); 1678 if (dlmsg) 1679 DRV_LOG(WARNING, "cannot load glue library: %s", dlmsg); 1680 goto glue_error; 1681 } 1682 sym = dlsym(handle, "mlx5_glue"); 1683 if (!sym || !*sym) { 1684 rte_errno = EINVAL; 1685 dlmsg = dlerror(); 1686 if (dlmsg) 1687 DRV_LOG(ERR, "cannot resolve glue symbol: %s", dlmsg); 1688 goto glue_error; 1689 } 1690 mlx5_glue = *sym; 1691 return 0; 1692 glue_error: 1693 if (handle) 1694 dlclose(handle); 1695 DRV_LOG(WARNING, 1696 "cannot initialize PMD due to missing run-time dependency on" 1697 " rdma-core libraries (libibverbs, libmlx5)"); 1698 return -rte_errno; 1699 } 1700 1701 #endif 1702 1703 /** 1704 * Driver initialization routine. 1705 */ 1706 RTE_INIT(rte_mlx5_pmd_init) 1707 { 1708 /* Initialize driver log type. */ 1709 mlx5_logtype = rte_log_register("pmd.net.mlx5"); 1710 if (mlx5_logtype >= 0) 1711 rte_log_set_level(mlx5_logtype, RTE_LOG_NOTICE); 1712 1713 /* Build the static tables for Verbs conversion. */ 1714 mlx5_set_ptype_table(); 1715 mlx5_set_cksum_table(); 1716 mlx5_set_swp_types_table(); 1717 /* 1718 * RDMAV_HUGEPAGES_SAFE tells ibv_fork_init() we intend to use 1719 * huge pages. Calling ibv_fork_init() during init allows 1720 * applications to use fork() safely for purposes other than 1721 * using this PMD, which is not supported in forked processes. 1722 */ 1723 setenv("RDMAV_HUGEPAGES_SAFE", "1", 1); 1724 /* Match the size of Rx completion entry to the size of a cacheline. */ 1725 if (RTE_CACHE_LINE_SIZE == 128) 1726 setenv("MLX5_CQE_SIZE", "128", 0); 1727 /* 1728 * MLX5_DEVICE_FATAL_CLEANUP tells ibv_destroy functions to 1729 * cleanup all the Verbs resources even when the device was removed. 1730 */ 1731 setenv("MLX5_DEVICE_FATAL_CLEANUP", "1", 1); 1732 #ifdef RTE_LIBRTE_MLX5_DLOPEN_DEPS 1733 if (mlx5_glue_init()) 1734 return; 1735 assert(mlx5_glue); 1736 #endif 1737 #ifndef NDEBUG 1738 /* Glue structure must not contain any NULL pointers. */ 1739 { 1740 unsigned int i; 1741 1742 for (i = 0; i != sizeof(*mlx5_glue) / sizeof(void *); ++i) 1743 assert(((const void *const *)mlx5_glue)[i]); 1744 } 1745 #endif 1746 if (strcmp(mlx5_glue->version, MLX5_GLUE_VERSION)) { 1747 DRV_LOG(ERR, 1748 "rdma-core glue \"%s\" mismatch: \"%s\" is required", 1749 mlx5_glue->version, MLX5_GLUE_VERSION); 1750 return; 1751 } 1752 mlx5_glue->fork_init(); 1753 rte_pci_register(&mlx5_driver); 1754 } 1755 1756 RTE_PMD_EXPORT_NAME(net_mlx5, __COUNTER__); 1757 RTE_PMD_REGISTER_PCI_TABLE(net_mlx5, mlx5_pci_id_map); 1758 RTE_PMD_REGISTER_KMOD_DEP(net_mlx5, "* ib_uverbs & mlx5_core & mlx5_ib"); 1759