1 /*- 2 * BSD LICENSE 3 * 4 * Copyright 2015 6WIND S.A. 5 * Copyright 2015 Mellanox. 6 * 7 * Redistribution and use in source and binary forms, with or without 8 * modification, are permitted provided that the following conditions 9 * are met: 10 * 11 * * Redistributions of source code must retain the above copyright 12 * notice, this list of conditions and the following disclaimer. 13 * * Redistributions in binary form must reproduce the above copyright 14 * notice, this list of conditions and the following disclaimer in 15 * the documentation and/or other materials provided with the 16 * distribution. 17 * * Neither the name of 6WIND S.A. nor the names of its 18 * contributors may be used to endorse or promote products derived 19 * from this software without specific prior written permission. 20 * 21 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 22 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 23 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 24 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 25 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 26 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 27 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 28 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 29 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 30 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 31 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 32 */ 33 34 #include <stddef.h> 35 #include <unistd.h> 36 #include <string.h> 37 #include <assert.h> 38 #include <stdint.h> 39 #include <stdlib.h> 40 #include <errno.h> 41 #include <net/if.h> 42 43 /* Verbs header. */ 44 /* ISO C doesn't support unnamed structs/unions, disabling -pedantic. */ 45 #ifdef PEDANTIC 46 #pragma GCC diagnostic ignored "-Wpedantic" 47 #endif 48 #include <infiniband/verbs.h> 49 #ifdef PEDANTIC 50 #pragma GCC diagnostic error "-Wpedantic" 51 #endif 52 53 /* DPDK headers don't like -pedantic. */ 54 #ifdef PEDANTIC 55 #pragma GCC diagnostic ignored "-Wpedantic" 56 #endif 57 #include <rte_malloc.h> 58 #include <rte_ethdev.h> 59 #include <rte_ethdev_pci.h> 60 #include <rte_pci.h> 61 #include <rte_common.h> 62 #include <rte_kvargs.h> 63 #ifdef PEDANTIC 64 #pragma GCC diagnostic error "-Wpedantic" 65 #endif 66 67 #include "mlx5.h" 68 #include "mlx5_utils.h" 69 #include "mlx5_rxtx.h" 70 #include "mlx5_autoconf.h" 71 #include "mlx5_defs.h" 72 73 /* Device parameter to enable RX completion queue compression. */ 74 #define MLX5_RXQ_CQE_COMP_EN "rxq_cqe_comp_en" 75 76 /* Device parameter to configure inline send. */ 77 #define MLX5_TXQ_INLINE "txq_inline" 78 79 /* 80 * Device parameter to configure the number of TX queues threshold for 81 * enabling inline send. 82 */ 83 #define MLX5_TXQS_MIN_INLINE "txqs_min_inline" 84 85 /* Device parameter to enable multi-packet send WQEs. */ 86 #define MLX5_TXQ_MPW_EN "txq_mpw_en" 87 88 /* Device parameter to include 2 dsegs in the title WQEBB. */ 89 #define MLX5_TXQ_MPW_HDR_DSEG_EN "txq_mpw_hdr_dseg_en" 90 91 /* Device parameter to limit the size of inlining packet. */ 92 #define MLX5_TXQ_MAX_INLINE_LEN "txq_max_inline_len" 93 94 /* Device parameter to enable hardware TSO offload. */ 95 #define MLX5_TSO "tso" 96 97 /* Default PMD specific parameter value. */ 98 #define MLX5_ARG_UNSET (-1) 99 100 struct mlx5_args { 101 int cqe_comp; 102 int txq_inline; 103 int txqs_inline; 104 int mps; 105 int mpw_hdr_dseg; 106 int inline_max_packet_sz; 107 int tso; 108 }; 109 /** 110 * Retrieve integer value from environment variable. 111 * 112 * @param[in] name 113 * Environment variable name. 114 * 115 * @return 116 * Integer value, 0 if the variable is not set. 117 */ 118 int 119 mlx5_getenv_int(const char *name) 120 { 121 const char *val = getenv(name); 122 123 if (val == NULL) 124 return 0; 125 return atoi(val); 126 } 127 128 /** 129 * DPDK callback to close the device. 130 * 131 * Destroy all queues and objects, free memory. 132 * 133 * @param dev 134 * Pointer to Ethernet device structure. 135 */ 136 static void 137 mlx5_dev_close(struct rte_eth_dev *dev) 138 { 139 struct priv *priv = mlx5_get_priv(dev); 140 unsigned int i; 141 142 priv_lock(priv); 143 DEBUG("%p: closing device \"%s\"", 144 (void *)dev, 145 ((priv->ctx != NULL) ? priv->ctx->device->name : "")); 146 /* In case mlx5_dev_stop() has not been called. */ 147 priv_dev_interrupt_handler_uninstall(priv, dev); 148 priv_special_flow_disable_all(priv); 149 priv_mac_addrs_disable(priv); 150 priv_destroy_hash_rxqs(priv); 151 152 /* Remove flow director elements. */ 153 priv_fdir_disable(priv); 154 priv_fdir_delete_filters_list(priv); 155 156 /* Prevent crashes when queues are still in use. */ 157 dev->rx_pkt_burst = removed_rx_burst; 158 dev->tx_pkt_burst = removed_tx_burst; 159 if (priv->rxqs != NULL) { 160 /* XXX race condition if mlx5_rx_burst() is still running. */ 161 usleep(1000); 162 for (i = 0; (i != priv->rxqs_n); ++i) { 163 struct rxq *rxq = (*priv->rxqs)[i]; 164 struct rxq_ctrl *rxq_ctrl; 165 166 if (rxq == NULL) 167 continue; 168 rxq_ctrl = container_of(rxq, struct rxq_ctrl, rxq); 169 (*priv->rxqs)[i] = NULL; 170 rxq_cleanup(rxq_ctrl); 171 rte_free(rxq_ctrl); 172 } 173 priv->rxqs_n = 0; 174 priv->rxqs = NULL; 175 } 176 if (priv->txqs != NULL) { 177 /* XXX race condition if mlx5_tx_burst() is still running. */ 178 usleep(1000); 179 for (i = 0; (i != priv->txqs_n); ++i) { 180 struct txq *txq = (*priv->txqs)[i]; 181 struct txq_ctrl *txq_ctrl; 182 183 if (txq == NULL) 184 continue; 185 txq_ctrl = container_of(txq, struct txq_ctrl, txq); 186 (*priv->txqs)[i] = NULL; 187 txq_cleanup(txq_ctrl); 188 rte_free(txq_ctrl); 189 } 190 priv->txqs_n = 0; 191 priv->txqs = NULL; 192 } 193 if (priv->pd != NULL) { 194 assert(priv->ctx != NULL); 195 claim_zero(ibv_dealloc_pd(priv->pd)); 196 claim_zero(ibv_close_device(priv->ctx)); 197 } else 198 assert(priv->ctx == NULL); 199 if (priv->rss_conf != NULL) { 200 for (i = 0; (i != hash_rxq_init_n); ++i) 201 rte_free((*priv->rss_conf)[i]); 202 rte_free(priv->rss_conf); 203 } 204 if (priv->reta_idx != NULL) 205 rte_free(priv->reta_idx); 206 priv_unlock(priv); 207 memset(priv, 0, sizeof(*priv)); 208 } 209 210 static const struct eth_dev_ops mlx5_dev_ops = { 211 .dev_configure = mlx5_dev_configure, 212 .dev_start = mlx5_dev_start, 213 .dev_stop = mlx5_dev_stop, 214 .dev_set_link_down = mlx5_set_link_down, 215 .dev_set_link_up = mlx5_set_link_up, 216 .dev_close = mlx5_dev_close, 217 .promiscuous_enable = mlx5_promiscuous_enable, 218 .promiscuous_disable = mlx5_promiscuous_disable, 219 .allmulticast_enable = mlx5_allmulticast_enable, 220 .allmulticast_disable = mlx5_allmulticast_disable, 221 .link_update = mlx5_link_update, 222 .stats_get = mlx5_stats_get, 223 .stats_reset = mlx5_stats_reset, 224 .xstats_get = mlx5_xstats_get, 225 .xstats_reset = mlx5_xstats_reset, 226 .xstats_get_names = mlx5_xstats_get_names, 227 .dev_infos_get = mlx5_dev_infos_get, 228 .dev_supported_ptypes_get = mlx5_dev_supported_ptypes_get, 229 .vlan_filter_set = mlx5_vlan_filter_set, 230 .rx_queue_setup = mlx5_rx_queue_setup, 231 .tx_queue_setup = mlx5_tx_queue_setup, 232 .rx_queue_release = mlx5_rx_queue_release, 233 .tx_queue_release = mlx5_tx_queue_release, 234 .flow_ctrl_get = mlx5_dev_get_flow_ctrl, 235 .flow_ctrl_set = mlx5_dev_set_flow_ctrl, 236 .mac_addr_remove = mlx5_mac_addr_remove, 237 .mac_addr_add = mlx5_mac_addr_add, 238 .mac_addr_set = mlx5_mac_addr_set, 239 .mtu_set = mlx5_dev_set_mtu, 240 .vlan_strip_queue_set = mlx5_vlan_strip_queue_set, 241 .vlan_offload_set = mlx5_vlan_offload_set, 242 .reta_update = mlx5_dev_rss_reta_update, 243 .reta_query = mlx5_dev_rss_reta_query, 244 .rss_hash_update = mlx5_rss_hash_update, 245 .rss_hash_conf_get = mlx5_rss_hash_conf_get, 246 .filter_ctrl = mlx5_dev_filter_ctrl, 247 .rx_descriptor_status = mlx5_rx_descriptor_status, 248 .tx_descriptor_status = mlx5_tx_descriptor_status, 249 .rx_queue_intr_enable = mlx5_rx_intr_enable, 250 .rx_queue_intr_disable = mlx5_rx_intr_disable, 251 }; 252 253 static struct { 254 struct rte_pci_addr pci_addr; /* associated PCI address */ 255 uint32_t ports; /* physical ports bitfield. */ 256 } mlx5_dev[32]; 257 258 /** 259 * Get device index in mlx5_dev[] from PCI bus address. 260 * 261 * @param[in] pci_addr 262 * PCI bus address to look for. 263 * 264 * @return 265 * mlx5_dev[] index on success, -1 on failure. 266 */ 267 static int 268 mlx5_dev_idx(struct rte_pci_addr *pci_addr) 269 { 270 unsigned int i; 271 int ret = -1; 272 273 assert(pci_addr != NULL); 274 for (i = 0; (i != RTE_DIM(mlx5_dev)); ++i) { 275 if ((mlx5_dev[i].pci_addr.domain == pci_addr->domain) && 276 (mlx5_dev[i].pci_addr.bus == pci_addr->bus) && 277 (mlx5_dev[i].pci_addr.devid == pci_addr->devid) && 278 (mlx5_dev[i].pci_addr.function == pci_addr->function)) 279 return i; 280 if ((mlx5_dev[i].ports == 0) && (ret == -1)) 281 ret = i; 282 } 283 return ret; 284 } 285 286 /** 287 * Verify and store value for device argument. 288 * 289 * @param[in] key 290 * Key argument to verify. 291 * @param[in] val 292 * Value associated with key. 293 * @param opaque 294 * User data. 295 * 296 * @return 297 * 0 on success, negative errno value on failure. 298 */ 299 static int 300 mlx5_args_check(const char *key, const char *val, void *opaque) 301 { 302 struct mlx5_args *args = opaque; 303 unsigned long tmp; 304 305 errno = 0; 306 tmp = strtoul(val, NULL, 0); 307 if (errno) { 308 WARN("%s: \"%s\" is not a valid integer", key, val); 309 return errno; 310 } 311 if (strcmp(MLX5_RXQ_CQE_COMP_EN, key) == 0) { 312 args->cqe_comp = !!tmp; 313 } else if (strcmp(MLX5_TXQ_INLINE, key) == 0) { 314 args->txq_inline = tmp; 315 } else if (strcmp(MLX5_TXQS_MIN_INLINE, key) == 0) { 316 args->txqs_inline = tmp; 317 } else if (strcmp(MLX5_TXQ_MPW_EN, key) == 0) { 318 args->mps = !!tmp; 319 } else if (strcmp(MLX5_TXQ_MPW_HDR_DSEG_EN, key) == 0) { 320 args->mpw_hdr_dseg = !!tmp; 321 } else if (strcmp(MLX5_TXQ_MAX_INLINE_LEN, key) == 0) { 322 args->inline_max_packet_sz = tmp; 323 } else if (strcmp(MLX5_TSO, key) == 0) { 324 args->tso = !!tmp; 325 } else { 326 WARN("%s: unknown parameter", key); 327 return -EINVAL; 328 } 329 return 0; 330 } 331 332 /** 333 * Parse device parameters. 334 * 335 * @param priv 336 * Pointer to private structure. 337 * @param devargs 338 * Device arguments structure. 339 * 340 * @return 341 * 0 on success, errno value on failure. 342 */ 343 static int 344 mlx5_args(struct mlx5_args *args, struct rte_devargs *devargs) 345 { 346 const char **params = (const char *[]){ 347 MLX5_RXQ_CQE_COMP_EN, 348 MLX5_TXQ_INLINE, 349 MLX5_TXQS_MIN_INLINE, 350 MLX5_TXQ_MPW_EN, 351 MLX5_TXQ_MPW_HDR_DSEG_EN, 352 MLX5_TXQ_MAX_INLINE_LEN, 353 MLX5_TSO, 354 NULL, 355 }; 356 struct rte_kvargs *kvlist; 357 int ret = 0; 358 int i; 359 360 if (devargs == NULL) 361 return 0; 362 /* Following UGLY cast is done to pass checkpatch. */ 363 kvlist = rte_kvargs_parse(devargs->args, params); 364 if (kvlist == NULL) 365 return 0; 366 /* Process parameters. */ 367 for (i = 0; (params[i] != NULL); ++i) { 368 if (rte_kvargs_count(kvlist, params[i])) { 369 ret = rte_kvargs_process(kvlist, params[i], 370 mlx5_args_check, args); 371 if (ret != 0) { 372 rte_kvargs_free(kvlist); 373 return ret; 374 } 375 } 376 } 377 rte_kvargs_free(kvlist); 378 return 0; 379 } 380 381 static struct rte_pci_driver mlx5_driver; 382 383 /** 384 * Assign parameters from args into priv, only non default 385 * values are considered. 386 * 387 * @param[out] priv 388 * Pointer to private structure. 389 * @param[in] args 390 * Pointer to args values. 391 */ 392 static void 393 mlx5_args_assign(struct priv *priv, struct mlx5_args *args) 394 { 395 if (args->cqe_comp != MLX5_ARG_UNSET) 396 priv->cqe_comp = args->cqe_comp; 397 if (args->txq_inline != MLX5_ARG_UNSET) 398 priv->txq_inline = args->txq_inline; 399 if (args->txqs_inline != MLX5_ARG_UNSET) 400 priv->txqs_inline = args->txqs_inline; 401 if (args->mps != MLX5_ARG_UNSET) 402 priv->mps = args->mps ? priv->mps : 0; 403 if (args->mpw_hdr_dseg != MLX5_ARG_UNSET) 404 priv->mpw_hdr_dseg = args->mpw_hdr_dseg; 405 if (args->inline_max_packet_sz != MLX5_ARG_UNSET) 406 priv->inline_max_packet_sz = args->inline_max_packet_sz; 407 if (args->tso != MLX5_ARG_UNSET) 408 priv->tso = args->tso; 409 } 410 411 /** 412 * DPDK callback to register a PCI device. 413 * 414 * This function creates an Ethernet device for each port of a given 415 * PCI device. 416 * 417 * @param[in] pci_drv 418 * PCI driver structure (mlx5_driver). 419 * @param[in] pci_dev 420 * PCI device information. 421 * 422 * @return 423 * 0 on success, negative errno value on failure. 424 */ 425 static int 426 mlx5_pci_probe(struct rte_pci_driver *pci_drv, struct rte_pci_device *pci_dev) 427 { 428 struct ibv_device **list; 429 struct ibv_device *ibv_dev; 430 int err = 0; 431 struct ibv_context *attr_ctx = NULL; 432 struct ibv_device_attr device_attr; 433 unsigned int sriov; 434 unsigned int mps; 435 unsigned int tunnel_en; 436 int idx; 437 int i; 438 439 (void)pci_drv; 440 assert(pci_drv == &mlx5_driver); 441 /* Get mlx5_dev[] index. */ 442 idx = mlx5_dev_idx(&pci_dev->addr); 443 if (idx == -1) { 444 ERROR("this driver cannot support any more adapters"); 445 return -ENOMEM; 446 } 447 DEBUG("using driver device index %d", idx); 448 449 /* Save PCI address. */ 450 mlx5_dev[idx].pci_addr = pci_dev->addr; 451 list = ibv_get_device_list(&i); 452 if (list == NULL) { 453 assert(errno); 454 if (errno == ENOSYS) 455 ERROR("cannot list devices, is ib_uverbs loaded?"); 456 return -errno; 457 } 458 assert(i >= 0); 459 /* 460 * For each listed device, check related sysfs entry against 461 * the provided PCI ID. 462 */ 463 while (i != 0) { 464 struct rte_pci_addr pci_addr; 465 466 --i; 467 DEBUG("checking device \"%s\"", list[i]->name); 468 if (mlx5_ibv_device_to_pci_addr(list[i], &pci_addr)) 469 continue; 470 if ((pci_dev->addr.domain != pci_addr.domain) || 471 (pci_dev->addr.bus != pci_addr.bus) || 472 (pci_dev->addr.devid != pci_addr.devid) || 473 (pci_dev->addr.function != pci_addr.function)) 474 continue; 475 sriov = ((pci_dev->id.device_id == 476 PCI_DEVICE_ID_MELLANOX_CONNECTX4VF) || 477 (pci_dev->id.device_id == 478 PCI_DEVICE_ID_MELLANOX_CONNECTX4LXVF) || 479 (pci_dev->id.device_id == 480 PCI_DEVICE_ID_MELLANOX_CONNECTX5VF) || 481 (pci_dev->id.device_id == 482 PCI_DEVICE_ID_MELLANOX_CONNECTX5EXVF)); 483 /* 484 * Multi-packet send is supported by ConnectX-4 Lx PF as well 485 * as all ConnectX-5 devices. 486 */ 487 switch (pci_dev->id.device_id) { 488 case PCI_DEVICE_ID_MELLANOX_CONNECTX4: 489 tunnel_en = 1; 490 mps = MLX5_MPW_DISABLED; 491 break; 492 case PCI_DEVICE_ID_MELLANOX_CONNECTX4LX: 493 mps = MLX5_MPW; 494 break; 495 case PCI_DEVICE_ID_MELLANOX_CONNECTX5: 496 case PCI_DEVICE_ID_MELLANOX_CONNECTX5VF: 497 case PCI_DEVICE_ID_MELLANOX_CONNECTX5EX: 498 case PCI_DEVICE_ID_MELLANOX_CONNECTX5EXVF: 499 tunnel_en = 1; 500 mps = MLX5_MPW_ENHANCED; 501 break; 502 default: 503 mps = MLX5_MPW_DISABLED; 504 } 505 INFO("PCI information matches, using device \"%s\"" 506 " (SR-IOV: %s, %sMPS: %s)", 507 list[i]->name, 508 sriov ? "true" : "false", 509 mps == MLX5_MPW_ENHANCED ? "Enhanced " : "", 510 mps != MLX5_MPW_DISABLED ? "true" : "false"); 511 attr_ctx = ibv_open_device(list[i]); 512 err = errno; 513 break; 514 } 515 if (attr_ctx == NULL) { 516 ibv_free_device_list(list); 517 switch (err) { 518 case 0: 519 ERROR("cannot access device, is mlx5_ib loaded?"); 520 return -ENODEV; 521 case EINVAL: 522 ERROR("cannot use device, are drivers up to date?"); 523 return -EINVAL; 524 } 525 assert(err > 0); 526 return -err; 527 } 528 ibv_dev = list[i]; 529 530 DEBUG("device opened"); 531 if (ibv_query_device(attr_ctx, &device_attr)) 532 goto error; 533 INFO("%u port(s) detected", device_attr.phys_port_cnt); 534 535 for (i = 0; i < device_attr.phys_port_cnt; i++) { 536 uint32_t port = i + 1; /* ports are indexed from one */ 537 uint32_t test = (1 << i); 538 struct ibv_context *ctx = NULL; 539 struct ibv_port_attr port_attr; 540 struct ibv_pd *pd = NULL; 541 struct priv *priv = NULL; 542 struct rte_eth_dev *eth_dev; 543 struct ibv_exp_device_attr exp_device_attr; 544 struct ether_addr mac; 545 uint16_t num_vfs = 0; 546 struct mlx5_args args = { 547 .cqe_comp = MLX5_ARG_UNSET, 548 .txq_inline = MLX5_ARG_UNSET, 549 .txqs_inline = MLX5_ARG_UNSET, 550 .mps = MLX5_ARG_UNSET, 551 .mpw_hdr_dseg = MLX5_ARG_UNSET, 552 .inline_max_packet_sz = MLX5_ARG_UNSET, 553 .tso = MLX5_ARG_UNSET, 554 }; 555 556 exp_device_attr.comp_mask = 557 IBV_EXP_DEVICE_ATTR_EXP_CAP_FLAGS | 558 IBV_EXP_DEVICE_ATTR_RX_HASH | 559 IBV_EXP_DEVICE_ATTR_VLAN_OFFLOADS | 560 IBV_EXP_DEVICE_ATTR_RX_PAD_END_ALIGN | 561 IBV_EXP_DEVICE_ATTR_TSO_CAPS | 562 0; 563 564 DEBUG("using port %u (%08" PRIx32 ")", port, test); 565 566 ctx = ibv_open_device(ibv_dev); 567 if (ctx == NULL) 568 goto port_error; 569 570 /* Check port status. */ 571 err = ibv_query_port(ctx, port, &port_attr); 572 if (err) { 573 ERROR("port query failed: %s", strerror(err)); 574 goto port_error; 575 } 576 577 if (port_attr.link_layer != IBV_LINK_LAYER_ETHERNET) { 578 ERROR("port %d is not configured in Ethernet mode", 579 port); 580 goto port_error; 581 } 582 583 if (port_attr.state != IBV_PORT_ACTIVE) 584 DEBUG("port %d is not active: \"%s\" (%d)", 585 port, ibv_port_state_str(port_attr.state), 586 port_attr.state); 587 588 /* Allocate protection domain. */ 589 pd = ibv_alloc_pd(ctx); 590 if (pd == NULL) { 591 ERROR("PD allocation failure"); 592 err = ENOMEM; 593 goto port_error; 594 } 595 596 mlx5_dev[idx].ports |= test; 597 598 /* from rte_ethdev.c */ 599 priv = rte_zmalloc("ethdev private structure", 600 sizeof(*priv), 601 RTE_CACHE_LINE_SIZE); 602 if (priv == NULL) { 603 ERROR("priv allocation failure"); 604 err = ENOMEM; 605 goto port_error; 606 } 607 608 priv->ctx = ctx; 609 priv->device_attr = device_attr; 610 priv->port = port; 611 priv->pd = pd; 612 priv->mtu = ETHER_MTU; 613 priv->mps = mps; /* Enable MPW by default if supported. */ 614 priv->cqe_comp = 1; /* Enable compression by default. */ 615 priv->tunnel_en = tunnel_en; 616 err = mlx5_args(&args, pci_dev->device.devargs); 617 if (err) { 618 ERROR("failed to process device arguments: %s", 619 strerror(err)); 620 goto port_error; 621 } 622 mlx5_args_assign(priv, &args); 623 if (ibv_exp_query_device(ctx, &exp_device_attr)) { 624 ERROR("ibv_exp_query_device() failed"); 625 goto port_error; 626 } 627 628 priv->hw_csum = 629 ((exp_device_attr.exp_device_cap_flags & 630 IBV_EXP_DEVICE_RX_CSUM_TCP_UDP_PKT) && 631 (exp_device_attr.exp_device_cap_flags & 632 IBV_EXP_DEVICE_RX_CSUM_IP_PKT)); 633 DEBUG("checksum offloading is %ssupported", 634 (priv->hw_csum ? "" : "not ")); 635 636 priv->hw_csum_l2tun = !!(exp_device_attr.exp_device_cap_flags & 637 IBV_EXP_DEVICE_VXLAN_SUPPORT); 638 DEBUG("L2 tunnel checksum offloads are %ssupported", 639 (priv->hw_csum_l2tun ? "" : "not ")); 640 641 priv->ind_table_max_size = exp_device_attr.rx_hash_caps.max_rwq_indirection_table_size; 642 /* Remove this check once DPDK supports larger/variable 643 * indirection tables. */ 644 if (priv->ind_table_max_size > 645 (unsigned int)ETH_RSS_RETA_SIZE_512) 646 priv->ind_table_max_size = ETH_RSS_RETA_SIZE_512; 647 DEBUG("maximum RX indirection table size is %u", 648 priv->ind_table_max_size); 649 priv->hw_vlan_strip = !!(exp_device_attr.wq_vlan_offloads_cap & 650 IBV_EXP_RECEIVE_WQ_CVLAN_STRIP); 651 DEBUG("VLAN stripping is %ssupported", 652 (priv->hw_vlan_strip ? "" : "not ")); 653 654 priv->hw_fcs_strip = !!(exp_device_attr.exp_device_cap_flags & 655 IBV_EXP_DEVICE_SCATTER_FCS); 656 DEBUG("FCS stripping configuration is %ssupported", 657 (priv->hw_fcs_strip ? "" : "not ")); 658 659 priv->hw_padding = !!exp_device_attr.rx_pad_end_addr_align; 660 DEBUG("hardware RX end alignment padding is %ssupported", 661 (priv->hw_padding ? "" : "not ")); 662 663 priv_get_num_vfs(priv, &num_vfs); 664 priv->sriov = (num_vfs || sriov); 665 priv->tso = ((priv->tso) && 666 (exp_device_attr.tso_caps.max_tso > 0) && 667 (exp_device_attr.tso_caps.supported_qpts & 668 (1 << IBV_QPT_RAW_ETH))); 669 if (priv->tso) 670 priv->max_tso_payload_sz = 671 exp_device_attr.tso_caps.max_tso; 672 if (priv->mps && !mps) { 673 ERROR("multi-packet send not supported on this device" 674 " (" MLX5_TXQ_MPW_EN ")"); 675 err = ENOTSUP; 676 goto port_error; 677 } else if (priv->mps && priv->tso) { 678 WARN("multi-packet send not supported in conjunction " 679 "with TSO. MPS disabled"); 680 priv->mps = 0; 681 } 682 INFO("%sMPS is %s", 683 priv->mps == MLX5_MPW_ENHANCED ? "Enhanced " : "", 684 priv->mps != MLX5_MPW_DISABLED ? "enabled" : "disabled"); 685 /* Set default values for Enhanced MPW, a.k.a MPWv2. */ 686 if (priv->mps == MLX5_MPW_ENHANCED) { 687 if (args.txqs_inline == MLX5_ARG_UNSET) 688 priv->txqs_inline = MLX5_EMPW_MIN_TXQS; 689 if (args.inline_max_packet_sz == MLX5_ARG_UNSET) 690 priv->inline_max_packet_sz = 691 MLX5_EMPW_MAX_INLINE_LEN; 692 if (args.txq_inline == MLX5_ARG_UNSET) 693 priv->txq_inline = MLX5_WQE_SIZE_MAX - 694 MLX5_WQE_SIZE; 695 } 696 /* Allocate and register default RSS hash keys. */ 697 priv->rss_conf = rte_calloc(__func__, hash_rxq_init_n, 698 sizeof((*priv->rss_conf)[0]), 0); 699 if (priv->rss_conf == NULL) { 700 err = ENOMEM; 701 goto port_error; 702 } 703 err = rss_hash_rss_conf_new_key(priv, 704 rss_hash_default_key, 705 rss_hash_default_key_len, 706 ETH_RSS_PROTO_MASK); 707 if (err) 708 goto port_error; 709 /* Configure the first MAC address by default. */ 710 if (priv_get_mac(priv, &mac.addr_bytes)) { 711 ERROR("cannot get MAC address, is mlx5_en loaded?" 712 " (errno: %s)", strerror(errno)); 713 goto port_error; 714 } 715 INFO("port %u MAC address is %02x:%02x:%02x:%02x:%02x:%02x", 716 priv->port, 717 mac.addr_bytes[0], mac.addr_bytes[1], 718 mac.addr_bytes[2], mac.addr_bytes[3], 719 mac.addr_bytes[4], mac.addr_bytes[5]); 720 /* Register MAC address. */ 721 claim_zero(priv_mac_addr_add(priv, 0, 722 (const uint8_t (*)[ETHER_ADDR_LEN]) 723 mac.addr_bytes)); 724 /* Initialize FD filters list. */ 725 err = fdir_init_filters_list(priv); 726 if (err) 727 goto port_error; 728 #ifndef NDEBUG 729 { 730 char ifname[IF_NAMESIZE]; 731 732 if (priv_get_ifname(priv, &ifname) == 0) 733 DEBUG("port %u ifname is \"%s\"", 734 priv->port, ifname); 735 else 736 DEBUG("port %u ifname is unknown", priv->port); 737 } 738 #endif 739 /* Get actual MTU if possible. */ 740 priv_get_mtu(priv, &priv->mtu); 741 DEBUG("port %u MTU is %u", priv->port, priv->mtu); 742 743 /* from rte_ethdev.c */ 744 { 745 char name[RTE_ETH_NAME_MAX_LEN]; 746 747 snprintf(name, sizeof(name), "%s port %u", 748 ibv_get_device_name(ibv_dev), port); 749 eth_dev = rte_eth_dev_allocate(name); 750 } 751 if (eth_dev == NULL) { 752 ERROR("can not allocate rte ethdev"); 753 err = ENOMEM; 754 goto port_error; 755 } 756 757 /* Secondary processes have to use local storage for their 758 * private data as well as a copy of eth_dev->data, but this 759 * pointer must not be modified before burst functions are 760 * actually called. */ 761 if (mlx5_is_secondary()) { 762 struct mlx5_secondary_data *sd = 763 &mlx5_secondary_data[eth_dev->data->port_id]; 764 sd->primary_priv = eth_dev->data->dev_private; 765 if (sd->primary_priv == NULL) { 766 ERROR("no private data for port %u", 767 eth_dev->data->port_id); 768 err = EINVAL; 769 goto port_error; 770 } 771 sd->shared_dev_data = eth_dev->data; 772 rte_spinlock_init(&sd->lock); 773 memcpy(sd->data.name, sd->shared_dev_data->name, 774 sizeof(sd->data.name)); 775 sd->data.dev_private = priv; 776 sd->data.rx_mbuf_alloc_failed = 0; 777 sd->data.mtu = ETHER_MTU; 778 sd->data.port_id = sd->shared_dev_data->port_id; 779 sd->data.mac_addrs = priv->mac; 780 eth_dev->tx_pkt_burst = mlx5_tx_burst_secondary_setup; 781 eth_dev->rx_pkt_burst = mlx5_rx_burst_secondary_setup; 782 } else { 783 eth_dev->data->dev_private = priv; 784 eth_dev->data->mac_addrs = priv->mac; 785 } 786 787 eth_dev->device = &pci_dev->device; 788 rte_eth_copy_pci_info(eth_dev, pci_dev); 789 eth_dev->device->driver = &mlx5_driver.driver; 790 priv->dev = eth_dev; 791 eth_dev->dev_ops = &mlx5_dev_ops; 792 793 /* Bring Ethernet device up. */ 794 DEBUG("forcing Ethernet interface up"); 795 priv_set_flags(priv, ~IFF_UP, IFF_UP); 796 mlx5_link_update(priv->dev, 1); 797 continue; 798 799 port_error: 800 if (priv) { 801 rte_free(priv->rss_conf); 802 rte_free(priv); 803 } 804 if (pd) 805 claim_zero(ibv_dealloc_pd(pd)); 806 if (ctx) 807 claim_zero(ibv_close_device(ctx)); 808 break; 809 } 810 811 /* 812 * XXX if something went wrong in the loop above, there is a resource 813 * leak (ctx, pd, priv, dpdk ethdev) but we can do nothing about it as 814 * long as the dpdk does not provide a way to deallocate a ethdev and a 815 * way to enumerate the registered ethdevs to free the previous ones. 816 */ 817 818 /* no port found, complain */ 819 if (!mlx5_dev[idx].ports) { 820 err = ENODEV; 821 goto error; 822 } 823 824 error: 825 if (attr_ctx) 826 claim_zero(ibv_close_device(attr_ctx)); 827 if (list) 828 ibv_free_device_list(list); 829 assert(err >= 0); 830 return -err; 831 } 832 833 static const struct rte_pci_id mlx5_pci_id_map[] = { 834 { 835 RTE_PCI_DEVICE(PCI_VENDOR_ID_MELLANOX, 836 PCI_DEVICE_ID_MELLANOX_CONNECTX4) 837 }, 838 { 839 RTE_PCI_DEVICE(PCI_VENDOR_ID_MELLANOX, 840 PCI_DEVICE_ID_MELLANOX_CONNECTX4VF) 841 }, 842 { 843 RTE_PCI_DEVICE(PCI_VENDOR_ID_MELLANOX, 844 PCI_DEVICE_ID_MELLANOX_CONNECTX4LX) 845 }, 846 { 847 RTE_PCI_DEVICE(PCI_VENDOR_ID_MELLANOX, 848 PCI_DEVICE_ID_MELLANOX_CONNECTX4LXVF) 849 }, 850 { 851 RTE_PCI_DEVICE(PCI_VENDOR_ID_MELLANOX, 852 PCI_DEVICE_ID_MELLANOX_CONNECTX5) 853 }, 854 { 855 RTE_PCI_DEVICE(PCI_VENDOR_ID_MELLANOX, 856 PCI_DEVICE_ID_MELLANOX_CONNECTX5VF) 857 }, 858 { 859 RTE_PCI_DEVICE(PCI_VENDOR_ID_MELLANOX, 860 PCI_DEVICE_ID_MELLANOX_CONNECTX5EX) 861 }, 862 { 863 RTE_PCI_DEVICE(PCI_VENDOR_ID_MELLANOX, 864 PCI_DEVICE_ID_MELLANOX_CONNECTX5EXVF) 865 }, 866 { 867 .vendor_id = 0 868 } 869 }; 870 871 static struct rte_pci_driver mlx5_driver = { 872 .driver = { 873 .name = MLX5_DRIVER_NAME 874 }, 875 .id_table = mlx5_pci_id_map, 876 .probe = mlx5_pci_probe, 877 .drv_flags = RTE_PCI_DRV_INTR_LSC, 878 }; 879 880 /** 881 * Driver initialization routine. 882 */ 883 RTE_INIT(rte_mlx5_pmd_init); 884 static void 885 rte_mlx5_pmd_init(void) 886 { 887 /* 888 * RDMAV_HUGEPAGES_SAFE tells ibv_fork_init() we intend to use 889 * huge pages. Calling ibv_fork_init() during init allows 890 * applications to use fork() safely for purposes other than 891 * using this PMD, which is not supported in forked processes. 892 */ 893 setenv("RDMAV_HUGEPAGES_SAFE", "1", 1); 894 ibv_fork_init(); 895 rte_eal_pci_register(&mlx5_driver); 896 } 897 898 RTE_PMD_EXPORT_NAME(net_mlx5, __COUNTER__); 899 RTE_PMD_REGISTER_PCI_TABLE(net_mlx5, mlx5_pci_id_map); 900 RTE_PMD_REGISTER_KMOD_DEP(net_mlx5, "* ib_uverbs & mlx5_core & mlx5_ib"); 901