1 /* SPDX-License-Identifier: BSD-3-Clause 2 * Copyright 2015 6WIND S.A. 3 * Copyright 2015 Mellanox Technologies, Ltd 4 */ 5 6 #include <stddef.h> 7 #include <unistd.h> 8 #include <string.h> 9 #include <stdint.h> 10 #include <stdlib.h> 11 #include <errno.h> 12 #include <fcntl.h> 13 14 #include <rte_malloc.h> 15 #include <ethdev_driver.h> 16 #include <rte_pci.h> 17 #include <bus_pci_driver.h> 18 #include <rte_common.h> 19 #include <rte_kvargs.h> 20 #include <rte_rwlock.h> 21 #include <rte_spinlock.h> 22 #include <rte_string_fns.h> 23 #include <rte_eal_paging.h> 24 #include <rte_alarm.h> 25 #include <rte_cycles.h> 26 #include <rte_interrupts.h> 27 28 #include <mlx5_glue.h> 29 #include <mlx5_devx_cmds.h> 30 #include <mlx5_common.h> 31 #include <mlx5_common_os.h> 32 #include <mlx5_common_mp.h> 33 #include <mlx5_malloc.h> 34 35 #include "mlx5_defs.h" 36 #include "mlx5.h" 37 #include "mlx5_utils.h" 38 #include "mlx5_rxtx.h" 39 #include "mlx5_rx.h" 40 #include "mlx5_tx.h" 41 #include "mlx5_autoconf.h" 42 #include "mlx5_flow.h" 43 #include "mlx5_flow_os.h" 44 #include "rte_pmd_mlx5.h" 45 46 #define MLX5_ETH_DRIVER_NAME mlx5_eth 47 48 /* Device parameter to enable RX completion queue compression. */ 49 #define MLX5_RXQ_CQE_COMP_EN "rxq_cqe_comp_en" 50 51 /* Device parameter to enable padding Rx packet to cacheline size. */ 52 #define MLX5_RXQ_PKT_PAD_EN "rxq_pkt_pad_en" 53 54 /* Device parameter to enable Multi-Packet Rx queue. */ 55 #define MLX5_RX_MPRQ_EN "mprq_en" 56 57 /* Device parameter to configure log 2 of the number of strides for MPRQ. */ 58 #define MLX5_RX_MPRQ_LOG_STRIDE_NUM "mprq_log_stride_num" 59 60 /* Device parameter to configure log 2 of the stride size for MPRQ. */ 61 #define MLX5_RX_MPRQ_LOG_STRIDE_SIZE "mprq_log_stride_size" 62 63 /* Device parameter to limit the size of memcpy'd packet for MPRQ. */ 64 #define MLX5_RX_MPRQ_MAX_MEMCPY_LEN "mprq_max_memcpy_len" 65 66 /* Device parameter to set the minimum number of Rx queues to enable MPRQ. */ 67 #define MLX5_RXQS_MIN_MPRQ "rxqs_min_mprq" 68 69 /* Device parameter to configure inline send. Deprecated, ignored.*/ 70 #define MLX5_TXQ_INLINE "txq_inline" 71 72 /* Device parameter to limit packet size to inline with ordinary SEND. */ 73 #define MLX5_TXQ_INLINE_MAX "txq_inline_max" 74 75 /* Device parameter to configure minimal data size to inline. */ 76 #define MLX5_TXQ_INLINE_MIN "txq_inline_min" 77 78 /* Device parameter to limit packet size to inline with Enhanced MPW. */ 79 #define MLX5_TXQ_INLINE_MPW "txq_inline_mpw" 80 81 /* 82 * Device parameter to configure the number of TX queues threshold for 83 * enabling inline send. 84 */ 85 #define MLX5_TXQS_MIN_INLINE "txqs_min_inline" 86 87 /* 88 * Device parameter to configure the number of TX queues threshold for 89 * enabling vectorized Tx, deprecated, ignored (no vectorized Tx routines). 90 */ 91 #define MLX5_TXQS_MAX_VEC "txqs_max_vec" 92 93 /* Device parameter to enable multi-packet send WQEs. */ 94 #define MLX5_TXQ_MPW_EN "txq_mpw_en" 95 96 /* 97 * Device parameter to include 2 dsegs in the title WQEBB. 98 * Deprecated, ignored. 99 */ 100 #define MLX5_TXQ_MPW_HDR_DSEG_EN "txq_mpw_hdr_dseg_en" 101 102 /* 103 * Device parameter to limit the size of inlining packet. 104 * Deprecated, ignored. 105 */ 106 #define MLX5_TXQ_MAX_INLINE_LEN "txq_max_inline_len" 107 108 /* 109 * Device parameter to enable Tx scheduling on timestamps 110 * and specify the packet pacing granularity in nanoseconds. 111 */ 112 #define MLX5_TX_PP "tx_pp" 113 114 /* 115 * Device parameter to specify skew in nanoseconds on Tx datapath, 116 * it represents the time between SQ start WQE processing and 117 * appearing actual packet data on the wire. 118 */ 119 #define MLX5_TX_SKEW "tx_skew" 120 121 /* 122 * Device parameter to enable hardware Tx vector. 123 * Deprecated, ignored (no vectorized Tx routines anymore). 124 */ 125 #define MLX5_TX_VEC_EN "tx_vec_en" 126 127 /* Device parameter to enable hardware Rx vector. */ 128 #define MLX5_RX_VEC_EN "rx_vec_en" 129 130 /* Allow L3 VXLAN flow creation. */ 131 #define MLX5_L3_VXLAN_EN "l3_vxlan_en" 132 133 /* Activate DV E-Switch flow steering. */ 134 #define MLX5_DV_ESW_EN "dv_esw_en" 135 136 /* Activate DV flow steering. */ 137 #define MLX5_DV_FLOW_EN "dv_flow_en" 138 139 /* Enable extensive flow metadata support. */ 140 #define MLX5_DV_XMETA_EN "dv_xmeta_en" 141 142 /* Device parameter to let the user manage the lacp traffic of bonding device */ 143 #define MLX5_LACP_BY_USER "lacp_by_user" 144 145 /* Activate Netlink support in VF mode. */ 146 #define MLX5_VF_NL_EN "vf_nl_en" 147 148 /* Select port representors to instantiate. */ 149 #define MLX5_REPRESENTOR "representor" 150 151 /* Device parameter to configure the maximum number of dump files per queue. */ 152 #define MLX5_MAX_DUMP_FILES_NUM "max_dump_files_num" 153 154 /* Configure timeout of LRO session (in microseconds). */ 155 #define MLX5_LRO_TIMEOUT_USEC "lro_timeout_usec" 156 157 /* 158 * Device parameter to configure the total data buffer size for a single 159 * hairpin queue (logarithm value). 160 */ 161 #define MLX5_HP_BUF_SIZE "hp_buf_log_sz" 162 163 /* Flow memory reclaim mode. */ 164 #define MLX5_RECLAIM_MEM "reclaim_mem_mode" 165 166 /* Decap will be used or not. */ 167 #define MLX5_DECAP_EN "decap_en" 168 169 /* Device parameter to configure allow or prevent duplicate rules pattern. */ 170 #define MLX5_ALLOW_DUPLICATE_PATTERN "allow_duplicate_pattern" 171 172 /* Device parameter to configure the delay drop when creating Rxqs. */ 173 #define MLX5_DELAY_DROP "delay_drop" 174 175 /* Device parameter to create the fdb default rule in PMD */ 176 #define MLX5_FDB_DEFAULT_RULE_EN "fdb_def_rule_en" 177 178 /* HW steering counter configuration. */ 179 #define MLX5_HWS_CNT_SERVICE_CORE "service_core" 180 181 /* HW steering counter's query interval. */ 182 #define MLX5_HWS_CNT_CYCLE_TIME "svc_cycle_time" 183 184 /* Device parameter to control representor matching in ingress/egress flows with HWS. */ 185 #define MLX5_REPR_MATCHING_EN "repr_matching_en" 186 187 /* Shared memory between primary and secondary processes. */ 188 struct mlx5_shared_data *mlx5_shared_data; 189 190 /** Driver-specific log messages type. */ 191 int mlx5_logtype; 192 193 static LIST_HEAD(, mlx5_dev_ctx_shared) mlx5_dev_ctx_list = 194 LIST_HEAD_INITIALIZER(); 195 static pthread_mutex_t mlx5_dev_ctx_list_mutex; 196 static const struct mlx5_indexed_pool_config mlx5_ipool_cfg[] = { 197 #if defined(HAVE_IBV_FLOW_DV_SUPPORT) || !defined(HAVE_INFINIBAND_VERBS_H) 198 [MLX5_IPOOL_DECAP_ENCAP] = { 199 .size = sizeof(struct mlx5_flow_dv_encap_decap_resource), 200 .trunk_size = 64, 201 .grow_trunk = 3, 202 .grow_shift = 2, 203 .need_lock = 1, 204 .release_mem_en = 1, 205 .malloc = mlx5_malloc, 206 .free = mlx5_free, 207 .type = "mlx5_encap_decap_ipool", 208 }, 209 [MLX5_IPOOL_PUSH_VLAN] = { 210 .size = sizeof(struct mlx5_flow_dv_push_vlan_action_resource), 211 .trunk_size = 64, 212 .grow_trunk = 3, 213 .grow_shift = 2, 214 .need_lock = 1, 215 .release_mem_en = 1, 216 .malloc = mlx5_malloc, 217 .free = mlx5_free, 218 .type = "mlx5_push_vlan_ipool", 219 }, 220 [MLX5_IPOOL_TAG] = { 221 .size = sizeof(struct mlx5_flow_dv_tag_resource), 222 .trunk_size = 64, 223 .grow_trunk = 3, 224 .grow_shift = 2, 225 .need_lock = 1, 226 .release_mem_en = 0, 227 .per_core_cache = (1 << 16), 228 .malloc = mlx5_malloc, 229 .free = mlx5_free, 230 .type = "mlx5_tag_ipool", 231 }, 232 [MLX5_IPOOL_PORT_ID] = { 233 .size = sizeof(struct mlx5_flow_dv_port_id_action_resource), 234 .trunk_size = 64, 235 .grow_trunk = 3, 236 .grow_shift = 2, 237 .need_lock = 1, 238 .release_mem_en = 1, 239 .malloc = mlx5_malloc, 240 .free = mlx5_free, 241 .type = "mlx5_port_id_ipool", 242 }, 243 [MLX5_IPOOL_JUMP] = { 244 /* 245 * MLX5_IPOOL_JUMP ipool entry size depends on selected flow engine. 246 * When HW steering is enabled mlx5_flow_group struct is used. 247 * Otherwise mlx5_flow_tbl_data_entry struct is used. 248 */ 249 .size = 0, 250 .trunk_size = 64, 251 .grow_trunk = 3, 252 .grow_shift = 2, 253 .need_lock = 1, 254 .release_mem_en = 1, 255 .malloc = mlx5_malloc, 256 .free = mlx5_free, 257 .type = "mlx5_jump_ipool", 258 }, 259 [MLX5_IPOOL_SAMPLE] = { 260 .size = sizeof(struct mlx5_flow_dv_sample_resource), 261 .trunk_size = 64, 262 .grow_trunk = 3, 263 .grow_shift = 2, 264 .need_lock = 1, 265 .release_mem_en = 1, 266 .malloc = mlx5_malloc, 267 .free = mlx5_free, 268 .type = "mlx5_sample_ipool", 269 }, 270 [MLX5_IPOOL_DEST_ARRAY] = { 271 .size = sizeof(struct mlx5_flow_dv_dest_array_resource), 272 .trunk_size = 64, 273 .grow_trunk = 3, 274 .grow_shift = 2, 275 .need_lock = 1, 276 .release_mem_en = 1, 277 .malloc = mlx5_malloc, 278 .free = mlx5_free, 279 .type = "mlx5_dest_array_ipool", 280 }, 281 [MLX5_IPOOL_TUNNEL_ID] = { 282 .size = sizeof(struct mlx5_flow_tunnel), 283 .trunk_size = MLX5_MAX_TUNNELS, 284 .need_lock = 1, 285 .release_mem_en = 1, 286 .type = "mlx5_tunnel_offload", 287 }, 288 [MLX5_IPOOL_TNL_TBL_ID] = { 289 .size = 0, 290 .need_lock = 1, 291 .type = "mlx5_flow_tnl_tbl_ipool", 292 }, 293 #endif 294 [MLX5_IPOOL_MTR] = { 295 /** 296 * The ipool index should grow continually from small to big, 297 * for meter idx, so not set grow_trunk to avoid meter index 298 * not jump continually. 299 */ 300 .size = sizeof(struct mlx5_legacy_flow_meter), 301 .trunk_size = 64, 302 .need_lock = 1, 303 .release_mem_en = 1, 304 .malloc = mlx5_malloc, 305 .free = mlx5_free, 306 .type = "mlx5_meter_ipool", 307 }, 308 [MLX5_IPOOL_MCP] = { 309 .size = sizeof(struct mlx5_flow_mreg_copy_resource), 310 .trunk_size = 64, 311 .grow_trunk = 3, 312 .grow_shift = 2, 313 .need_lock = 1, 314 .release_mem_en = 1, 315 .malloc = mlx5_malloc, 316 .free = mlx5_free, 317 .type = "mlx5_mcp_ipool", 318 }, 319 [MLX5_IPOOL_HRXQ] = { 320 .size = (sizeof(struct mlx5_hrxq) + MLX5_RSS_HASH_KEY_LEN), 321 .trunk_size = 64, 322 .grow_trunk = 3, 323 .grow_shift = 2, 324 .need_lock = 1, 325 .release_mem_en = 1, 326 .malloc = mlx5_malloc, 327 .free = mlx5_free, 328 .type = "mlx5_hrxq_ipool", 329 }, 330 [MLX5_IPOOL_MLX5_FLOW] = { 331 /* 332 * MLX5_IPOOL_MLX5_FLOW size varies for DV and VERBS flows. 333 * It set in run time according to PCI function configuration. 334 */ 335 .size = 0, 336 .trunk_size = 64, 337 .grow_trunk = 3, 338 .grow_shift = 2, 339 .need_lock = 1, 340 .release_mem_en = 0, 341 .per_core_cache = 1 << 19, 342 .malloc = mlx5_malloc, 343 .free = mlx5_free, 344 .type = "mlx5_flow_handle_ipool", 345 }, 346 [MLX5_IPOOL_RTE_FLOW] = { 347 .size = sizeof(struct rte_flow), 348 .trunk_size = 4096, 349 .need_lock = 1, 350 .release_mem_en = 1, 351 .malloc = mlx5_malloc, 352 .free = mlx5_free, 353 .type = "rte_flow_ipool", 354 }, 355 [MLX5_IPOOL_RSS_EXPANTION_FLOW_ID] = { 356 .size = 0, 357 .need_lock = 1, 358 .type = "mlx5_flow_rss_id_ipool", 359 }, 360 [MLX5_IPOOL_RSS_SHARED_ACTIONS] = { 361 .size = sizeof(struct mlx5_shared_action_rss), 362 .trunk_size = 64, 363 .grow_trunk = 3, 364 .grow_shift = 2, 365 .need_lock = 1, 366 .release_mem_en = 1, 367 .malloc = mlx5_malloc, 368 .free = mlx5_free, 369 .type = "mlx5_shared_action_rss", 370 }, 371 [MLX5_IPOOL_MTR_POLICY] = { 372 /** 373 * The ipool index should grow continually from small to big, 374 * for policy idx, so not set grow_trunk to avoid policy index 375 * not jump continually. 376 */ 377 .size = sizeof(struct mlx5_flow_meter_sub_policy), 378 .trunk_size = 64, 379 .need_lock = 1, 380 .release_mem_en = 1, 381 .malloc = mlx5_malloc, 382 .free = mlx5_free, 383 .type = "mlx5_meter_policy_ipool", 384 }, 385 }; 386 387 #define MLX5_FLOW_MIN_ID_POOL_SIZE 512 388 #define MLX5_ID_GENERATION_ARRAY_FACTOR 16 389 390 #define MLX5_FLOW_TABLE_HLIST_ARRAY_SIZE 1024 391 392 #define MLX5_RXQ_ENH_CQE_COMP_MASK 0x80 393 394 /** 395 * Decide whether representor ID is a HPF(host PF) port on BF2. 396 * 397 * @param dev 398 * Pointer to Ethernet device structure. 399 * 400 * @return 401 * Non-zero if HPF, otherwise 0. 402 */ 403 bool 404 mlx5_is_hpf(struct rte_eth_dev *dev) 405 { 406 struct mlx5_priv *priv = dev->data->dev_private; 407 uint16_t repr = MLX5_REPRESENTOR_REPR(priv->representor_id); 408 int type = MLX5_REPRESENTOR_TYPE(priv->representor_id); 409 410 return priv->representor != 0 && type == RTE_ETH_REPRESENTOR_VF && 411 MLX5_REPRESENTOR_REPR(-1) == repr; 412 } 413 414 /** 415 * Decide whether representor ID is a SF port representor. 416 * 417 * @param dev 418 * Pointer to Ethernet device structure. 419 * 420 * @return 421 * Non-zero if HPF, otherwise 0. 422 */ 423 bool 424 mlx5_is_sf_repr(struct rte_eth_dev *dev) 425 { 426 struct mlx5_priv *priv = dev->data->dev_private; 427 int type = MLX5_REPRESENTOR_TYPE(priv->representor_id); 428 429 return priv->representor != 0 && type == RTE_ETH_REPRESENTOR_SF; 430 } 431 432 /** 433 * Initialize the ASO aging management structure. 434 * 435 * @param[in] sh 436 * Pointer to mlx5_dev_ctx_shared object to free 437 * 438 * @return 439 * 0 on success, a negative errno value otherwise and rte_errno is set. 440 */ 441 int 442 mlx5_flow_aso_age_mng_init(struct mlx5_dev_ctx_shared *sh) 443 { 444 int err; 445 446 if (sh->aso_age_mng) 447 return 0; 448 sh->aso_age_mng = mlx5_malloc(MLX5_MEM_ZERO, sizeof(*sh->aso_age_mng), 449 RTE_CACHE_LINE_SIZE, SOCKET_ID_ANY); 450 if (!sh->aso_age_mng) { 451 DRV_LOG(ERR, "aso_age_mng allocation was failed."); 452 rte_errno = ENOMEM; 453 return -ENOMEM; 454 } 455 err = mlx5_aso_queue_init(sh, ASO_OPC_MOD_FLOW_HIT, 1); 456 if (err) { 457 mlx5_free(sh->aso_age_mng); 458 return -1; 459 } 460 rte_rwlock_init(&sh->aso_age_mng->resize_rwl); 461 rte_spinlock_init(&sh->aso_age_mng->free_sl); 462 LIST_INIT(&sh->aso_age_mng->free); 463 return 0; 464 } 465 466 /** 467 * Close and release all the resources of the ASO aging management structure. 468 * 469 * @param[in] sh 470 * Pointer to mlx5_dev_ctx_shared object to free. 471 */ 472 static void 473 mlx5_flow_aso_age_mng_close(struct mlx5_dev_ctx_shared *sh) 474 { 475 int i, j; 476 477 mlx5_aso_flow_hit_queue_poll_stop(sh); 478 mlx5_aso_queue_uninit(sh, ASO_OPC_MOD_FLOW_HIT); 479 if (sh->aso_age_mng->pools) { 480 struct mlx5_aso_age_pool *pool; 481 482 for (i = 0; i < sh->aso_age_mng->next; ++i) { 483 pool = sh->aso_age_mng->pools[i]; 484 claim_zero(mlx5_devx_cmd_destroy 485 (pool->flow_hit_aso_obj)); 486 for (j = 0; j < MLX5_COUNTERS_PER_POOL; ++j) 487 if (pool->actions[j].dr_action) 488 claim_zero 489 (mlx5_flow_os_destroy_flow_action 490 (pool->actions[j].dr_action)); 491 mlx5_free(pool); 492 } 493 mlx5_free(sh->aso_age_mng->pools); 494 } 495 mlx5_free(sh->aso_age_mng); 496 } 497 498 /** 499 * Initialize the shared aging list information per port. 500 * 501 * @param[in] sh 502 * Pointer to mlx5_dev_ctx_shared object. 503 */ 504 static void 505 mlx5_flow_aging_init(struct mlx5_dev_ctx_shared *sh) 506 { 507 uint32_t i; 508 struct mlx5_age_info *age_info; 509 510 /* 511 * In HW steering, aging information structure is initialized later 512 * during configure function. 513 */ 514 if (sh->config.dv_flow_en == 2) 515 return; 516 for (i = 0; i < sh->max_port; i++) { 517 age_info = &sh->port[i].age_info; 518 age_info->flags = 0; 519 TAILQ_INIT(&age_info->aged_counters); 520 LIST_INIT(&age_info->aged_aso); 521 rte_spinlock_init(&age_info->aged_sl); 522 MLX5_AGE_SET(age_info, MLX5_AGE_TRIGGER); 523 } 524 } 525 526 /** 527 * DV flow counter mode detect and config. 528 * 529 * @param dev 530 * Pointer to rte_eth_dev structure. 531 * 532 */ 533 void 534 mlx5_flow_counter_mode_config(struct rte_eth_dev *dev __rte_unused) 535 { 536 #ifdef HAVE_IBV_FLOW_DV_SUPPORT 537 struct mlx5_priv *priv = dev->data->dev_private; 538 struct mlx5_dev_ctx_shared *sh = priv->sh; 539 struct mlx5_hca_attr *hca_attr = &sh->cdev->config.hca_attr; 540 bool fallback; 541 542 #ifndef HAVE_IBV_DEVX_ASYNC 543 fallback = true; 544 #else 545 fallback = false; 546 if (!sh->cdev->config.devx || !sh->config.dv_flow_en || 547 !hca_attr->flow_counters_dump || 548 !(hca_attr->flow_counter_bulk_alloc_bitmap & 0x4) || 549 (mlx5_flow_dv_discover_counter_offset_support(dev) == -ENOTSUP)) 550 fallback = true; 551 #endif 552 if (fallback) 553 DRV_LOG(INFO, "Use fall-back DV counter management. Flow " 554 "counter dump:%d, bulk_alloc_bitmap:0x%hhx.", 555 hca_attr->flow_counters_dump, 556 hca_attr->flow_counter_bulk_alloc_bitmap); 557 /* Initialize fallback mode only on the port initializes sh. */ 558 if (sh->refcnt == 1) 559 sh->sws_cmng.counter_fallback = fallback; 560 else if (fallback != sh->sws_cmng.counter_fallback) 561 DRV_LOG(WARNING, "Port %d in sh has different fallback mode " 562 "with others:%d.", PORT_ID(priv), fallback); 563 #endif 564 } 565 566 /** 567 * Initialize the counters management structure. 568 * 569 * @param[in] sh 570 * Pointer to mlx5_dev_ctx_shared object to free 571 * 572 * @return 573 * 0 on success, otherwise negative errno value and rte_errno is set. 574 */ 575 static int 576 mlx5_flow_counters_mng_init(struct mlx5_dev_ctx_shared *sh) 577 { 578 int i, j; 579 580 if (sh->config.dv_flow_en < 2) { 581 void *pools; 582 583 pools = mlx5_malloc(MLX5_MEM_ZERO, 584 sizeof(struct mlx5_flow_counter_pool *) * 585 MLX5_COUNTER_POOLS_MAX_NUM, 586 0, SOCKET_ID_ANY); 587 if (!pools) { 588 DRV_LOG(ERR, 589 "Counter management allocation was failed."); 590 rte_errno = ENOMEM; 591 return -rte_errno; 592 } 593 memset(&sh->sws_cmng, 0, sizeof(sh->sws_cmng)); 594 TAILQ_INIT(&sh->sws_cmng.flow_counters); 595 sh->sws_cmng.min_id = MLX5_CNT_BATCH_OFFSET; 596 sh->sws_cmng.max_id = -1; 597 sh->sws_cmng.last_pool_idx = POOL_IDX_INVALID; 598 sh->sws_cmng.pools = pools; 599 rte_spinlock_init(&sh->sws_cmng.pool_update_sl); 600 for (i = 0; i < MLX5_COUNTER_TYPE_MAX; i++) { 601 TAILQ_INIT(&sh->sws_cmng.counters[i]); 602 rte_spinlock_init(&sh->sws_cmng.csl[i]); 603 } 604 } else { 605 struct mlx5_hca_attr *attr = &sh->cdev->config.hca_attr; 606 uint32_t fw_max_nb_cnts = attr->max_flow_counter; 607 uint8_t log_dcs = log2above(fw_max_nb_cnts) - 1; 608 uint32_t max_nb_cnts = 0; 609 610 for (i = 0, j = 0; j < MLX5_HWS_CNT_DCS_NUM; ++i) { 611 int log_dcs_i = log_dcs - i; 612 613 if (log_dcs_i < 0) 614 break; 615 if ((max_nb_cnts | RTE_BIT32(log_dcs_i)) > 616 fw_max_nb_cnts) 617 continue; 618 max_nb_cnts |= RTE_BIT32(log_dcs_i); 619 j++; 620 } 621 sh->hws_max_log_bulk_sz = log_dcs; 622 sh->hws_max_nb_counters = max_nb_cnts; 623 } 624 return 0; 625 } 626 627 /** 628 * Destroy all the resources allocated for a counter memory management. 629 * 630 * @param[in] mng 631 * Pointer to the memory management structure. 632 */ 633 static void 634 mlx5_flow_destroy_counter_stat_mem_mng(struct mlx5_counter_stats_mem_mng *mng) 635 { 636 uint8_t *mem = (uint8_t *)(uintptr_t)mng->raws[0].data; 637 638 LIST_REMOVE(mng, next); 639 mlx5_os_wrapped_mkey_destroy(&mng->wm); 640 mlx5_free(mem); 641 } 642 643 /** 644 * Close and release all the resources of the counters management. 645 * 646 * @param[in] sh 647 * Pointer to mlx5_dev_ctx_shared object to free. 648 */ 649 static void 650 mlx5_flow_counters_mng_close(struct mlx5_dev_ctx_shared *sh) 651 { 652 struct mlx5_counter_stats_mem_mng *mng; 653 int i, j; 654 int retries = 1024; 655 656 rte_errno = 0; 657 while (--retries) { 658 rte_eal_alarm_cancel(mlx5_flow_query_alarm, sh); 659 if (rte_errno != EINPROGRESS) 660 break; 661 rte_pause(); 662 } 663 664 if (sh->sws_cmng.pools) { 665 struct mlx5_flow_counter_pool *pool; 666 uint16_t n_valid = sh->sws_cmng.n_valid; 667 bool fallback = sh->sws_cmng.counter_fallback; 668 669 for (i = 0; i < n_valid; ++i) { 670 pool = sh->sws_cmng.pools[i]; 671 if (!fallback && pool->min_dcs) 672 claim_zero(mlx5_devx_cmd_destroy 673 (pool->min_dcs)); 674 for (j = 0; j < MLX5_COUNTERS_PER_POOL; ++j) { 675 struct mlx5_flow_counter *cnt = 676 MLX5_POOL_GET_CNT(pool, j); 677 678 if (cnt->action) 679 claim_zero 680 (mlx5_flow_os_destroy_flow_action 681 (cnt->action)); 682 if (fallback && cnt->dcs_when_free) 683 claim_zero(mlx5_devx_cmd_destroy 684 (cnt->dcs_when_free)); 685 } 686 mlx5_free(pool); 687 } 688 mlx5_free(sh->sws_cmng.pools); 689 } 690 mng = LIST_FIRST(&sh->sws_cmng.mem_mngs); 691 while (mng) { 692 mlx5_flow_destroy_counter_stat_mem_mng(mng); 693 mng = LIST_FIRST(&sh->sws_cmng.mem_mngs); 694 } 695 memset(&sh->sws_cmng, 0, sizeof(sh->sws_cmng)); 696 } 697 698 /** 699 * Initialize the aso flow meters management structure. 700 * 701 * @param[in] sh 702 * Pointer to mlx5_dev_ctx_shared object to free 703 */ 704 int 705 mlx5_aso_flow_mtrs_mng_init(struct mlx5_dev_ctx_shared *sh) 706 { 707 if (!sh->mtrmng) { 708 sh->mtrmng = mlx5_malloc(MLX5_MEM_ZERO, 709 sizeof(*sh->mtrmng), 710 RTE_CACHE_LINE_SIZE, SOCKET_ID_ANY); 711 if (!sh->mtrmng) { 712 DRV_LOG(ERR, 713 "meter management allocation was failed."); 714 rte_errno = ENOMEM; 715 return -ENOMEM; 716 } 717 if (sh->meter_aso_en) { 718 rte_spinlock_init(&sh->mtrmng->pools_mng.mtrsl); 719 rte_rwlock_init(&sh->mtrmng->pools_mng.resize_mtrwl); 720 LIST_INIT(&sh->mtrmng->pools_mng.meters); 721 } 722 sh->mtrmng->def_policy_id = MLX5_INVALID_POLICY_ID; 723 } 724 return 0; 725 } 726 727 /** 728 * Close and release all the resources of 729 * the ASO flow meter management structure. 730 * 731 * @param[in] sh 732 * Pointer to mlx5_dev_ctx_shared object to free. 733 */ 734 static void 735 mlx5_aso_flow_mtrs_mng_close(struct mlx5_dev_ctx_shared *sh) 736 { 737 struct mlx5_aso_mtr_pool *mtr_pool; 738 struct mlx5_flow_mtr_mng *mtrmng = sh->mtrmng; 739 uint32_t idx; 740 #ifdef HAVE_MLX5_DR_CREATE_ACTION_ASO 741 struct mlx5_aso_mtr *aso_mtr; 742 int i; 743 #endif /* HAVE_MLX5_DR_CREATE_ACTION_ASO */ 744 745 if (sh->meter_aso_en) { 746 mlx5_aso_queue_uninit(sh, ASO_OPC_MOD_POLICER); 747 idx = mtrmng->pools_mng.n_valid; 748 while (idx--) { 749 mtr_pool = mtrmng->pools_mng.pools[idx]; 750 #ifdef HAVE_MLX5_DR_CREATE_ACTION_ASO 751 for (i = 0; i < MLX5_ASO_MTRS_PER_POOL; i++) { 752 aso_mtr = &mtr_pool->mtrs[i]; 753 if (aso_mtr->fm.meter_action_g) 754 claim_zero 755 (mlx5_glue->destroy_flow_action 756 (aso_mtr->fm.meter_action_g)); 757 if (aso_mtr->fm.meter_action_y) 758 claim_zero 759 (mlx5_glue->destroy_flow_action 760 (aso_mtr->fm.meter_action_y)); 761 } 762 #endif /* HAVE_MLX5_DR_CREATE_ACTION_ASO */ 763 claim_zero(mlx5_devx_cmd_destroy 764 (mtr_pool->devx_obj)); 765 mtrmng->pools_mng.n_valid--; 766 mlx5_free(mtr_pool); 767 } 768 mlx5_free(sh->mtrmng->pools_mng.pools); 769 } 770 mlx5_free(sh->mtrmng); 771 sh->mtrmng = NULL; 772 } 773 774 /* Send FLOW_AGED event if needed. */ 775 void 776 mlx5_age_event_prepare(struct mlx5_dev_ctx_shared *sh) 777 { 778 struct mlx5_age_info *age_info; 779 uint32_t i; 780 781 for (i = 0; i < sh->max_port; i++) { 782 age_info = &sh->port[i].age_info; 783 if (!MLX5_AGE_GET(age_info, MLX5_AGE_EVENT_NEW)) 784 continue; 785 MLX5_AGE_UNSET(age_info, MLX5_AGE_EVENT_NEW); 786 if (MLX5_AGE_GET(age_info, MLX5_AGE_TRIGGER)) { 787 MLX5_AGE_UNSET(age_info, MLX5_AGE_TRIGGER); 788 rte_eth_dev_callback_process 789 (&rte_eth_devices[sh->port[i].devx_ih_port_id], 790 RTE_ETH_EVENT_FLOW_AGED, NULL); 791 } 792 } 793 } 794 795 /* 796 * Initialize the ASO connection tracking structure. 797 * 798 * @param[in] sh 799 * Pointer to mlx5_dev_ctx_shared object. 800 * 801 * @return 802 * 0 on success, a negative errno value otherwise and rte_errno is set. 803 */ 804 int 805 mlx5_flow_aso_ct_mng_init(struct mlx5_dev_ctx_shared *sh) 806 { 807 int err; 808 809 if (sh->ct_mng) 810 return 0; 811 sh->ct_mng = mlx5_malloc(MLX5_MEM_ZERO, sizeof(*sh->ct_mng) + 812 sizeof(struct mlx5_aso_sq) * MLX5_ASO_CT_SQ_NUM, 813 RTE_CACHE_LINE_SIZE, SOCKET_ID_ANY); 814 if (!sh->ct_mng) { 815 DRV_LOG(ERR, "ASO CT management allocation failed."); 816 rte_errno = ENOMEM; 817 return -rte_errno; 818 } 819 err = mlx5_aso_queue_init(sh, ASO_OPC_MOD_CONNECTION_TRACKING, MLX5_ASO_CT_SQ_NUM); 820 if (err) { 821 mlx5_free(sh->ct_mng); 822 /* rte_errno should be extracted from the failure. */ 823 rte_errno = EINVAL; 824 return -rte_errno; 825 } 826 rte_spinlock_init(&sh->ct_mng->ct_sl); 827 rte_rwlock_init(&sh->ct_mng->resize_rwl); 828 LIST_INIT(&sh->ct_mng->free_cts); 829 return 0; 830 } 831 832 /* 833 * Close and release all the resources of the 834 * ASO connection tracking management structure. 835 * 836 * @param[in] sh 837 * Pointer to mlx5_dev_ctx_shared object to free. 838 */ 839 static void 840 mlx5_flow_aso_ct_mng_close(struct mlx5_dev_ctx_shared *sh) 841 { 842 struct mlx5_aso_ct_pools_mng *mng = sh->ct_mng; 843 struct mlx5_aso_ct_pool *ct_pool; 844 struct mlx5_aso_ct_action *ct; 845 uint32_t idx; 846 uint32_t val; 847 uint32_t cnt; 848 int i; 849 850 mlx5_aso_queue_uninit(sh, ASO_OPC_MOD_CONNECTION_TRACKING); 851 idx = mng->next; 852 while (idx--) { 853 cnt = 0; 854 ct_pool = mng->pools[idx]; 855 for (i = 0; i < MLX5_ASO_CT_ACTIONS_PER_POOL; i++) { 856 ct = &ct_pool->actions[i]; 857 val = __atomic_fetch_sub(&ct->refcnt, 1, 858 __ATOMIC_RELAXED); 859 MLX5_ASSERT(val == 1); 860 if (val > 1) 861 cnt++; 862 #ifdef HAVE_MLX5_DR_ACTION_ASO_CT 863 if (ct->dr_action_orig) 864 claim_zero(mlx5_glue->destroy_flow_action 865 (ct->dr_action_orig)); 866 if (ct->dr_action_rply) 867 claim_zero(mlx5_glue->destroy_flow_action 868 (ct->dr_action_rply)); 869 #endif 870 } 871 claim_zero(mlx5_devx_cmd_destroy(ct_pool->devx_obj)); 872 if (cnt) { 873 DRV_LOG(DEBUG, "%u ASO CT objects are being used in the pool %u", 874 cnt, i); 875 } 876 mlx5_free(ct_pool); 877 /* in case of failure. */ 878 mng->next--; 879 } 880 mlx5_free(mng->pools); 881 mlx5_free(mng); 882 /* Management structure must be cleared to 0s during allocation. */ 883 sh->ct_mng = NULL; 884 } 885 886 /** 887 * Initialize the flow resources' indexed mempool. 888 * 889 * @param[in] sh 890 * Pointer to mlx5_dev_ctx_shared object. 891 */ 892 static void 893 mlx5_flow_ipool_create(struct mlx5_dev_ctx_shared *sh) 894 { 895 uint8_t i; 896 struct mlx5_indexed_pool_config cfg; 897 898 for (i = 0; i < MLX5_IPOOL_MAX; ++i) { 899 cfg = mlx5_ipool_cfg[i]; 900 switch (i) { 901 default: 902 break; 903 /* 904 * Set MLX5_IPOOL_MLX5_FLOW ipool size 905 * according to PCI function flow configuration. 906 */ 907 case MLX5_IPOOL_MLX5_FLOW: 908 cfg.size = sh->config.dv_flow_en ? 909 sizeof(struct mlx5_flow_handle) : 910 MLX5_FLOW_HANDLE_VERBS_SIZE; 911 break; 912 #if defined(HAVE_IBV_FLOW_DV_SUPPORT) || !defined(HAVE_INFINIBAND_VERBS_H) 913 /* Set MLX5_IPOOL_JUMP ipool entry size depending on selected flow engine. */ 914 case MLX5_IPOOL_JUMP: 915 cfg.size = sh->config.dv_flow_en == 2 ? 916 sizeof(struct mlx5_flow_group) : 917 sizeof(struct mlx5_flow_tbl_data_entry); 918 break; 919 #endif 920 } 921 if (sh->config.reclaim_mode) { 922 cfg.release_mem_en = 1; 923 cfg.per_core_cache = 0; 924 } else { 925 cfg.release_mem_en = 0; 926 } 927 sh->ipool[i] = mlx5_ipool_create(&cfg); 928 } 929 } 930 931 932 /** 933 * Release the flow resources' indexed mempool. 934 * 935 * @param[in] sh 936 * Pointer to mlx5_dev_ctx_shared object. 937 */ 938 static void 939 mlx5_flow_ipool_destroy(struct mlx5_dev_ctx_shared *sh) 940 { 941 uint8_t i; 942 943 for (i = 0; i < MLX5_IPOOL_MAX; ++i) 944 mlx5_ipool_destroy(sh->ipool[i]); 945 for (i = 0; i < MLX5_MAX_MODIFY_NUM; ++i) 946 if (sh->mdh_ipools[i]) 947 mlx5_ipool_destroy(sh->mdh_ipools[i]); 948 } 949 950 /* 951 * Check if dynamic flex parser for eCPRI already exists. 952 * 953 * @param dev 954 * Pointer to Ethernet device structure. 955 * 956 * @return 957 * true on exists, false on not. 958 */ 959 bool 960 mlx5_flex_parser_ecpri_exist(struct rte_eth_dev *dev) 961 { 962 struct mlx5_priv *priv = dev->data->dev_private; 963 struct mlx5_ecpri_parser_profile *prf = &priv->sh->ecpri_parser; 964 965 return !!prf->obj; 966 } 967 968 /* 969 * Allocation of a flex parser for eCPRI. Once created, this parser related 970 * resources will be held until the device is closed. 971 * 972 * @param dev 973 * Pointer to Ethernet device structure. 974 * 975 * @return 976 * 0 on success, a negative errno value otherwise and rte_errno is set. 977 */ 978 int 979 mlx5_flex_parser_ecpri_alloc(struct rte_eth_dev *dev) 980 { 981 struct mlx5_priv *priv = dev->data->dev_private; 982 struct mlx5_ecpri_parser_profile *prf = &priv->sh->ecpri_parser; 983 struct mlx5_devx_graph_node_attr node = { 984 .modify_field_select = 0, 985 }; 986 uint32_t ids[8]; 987 int ret; 988 989 if (!priv->sh->cdev->config.hca_attr.parse_graph_flex_node) { 990 DRV_LOG(ERR, "Dynamic flex parser is not supported " 991 "for device %s.", priv->dev_data->name); 992 return -ENOTSUP; 993 } 994 node.header_length_mode = MLX5_GRAPH_NODE_LEN_FIXED; 995 /* 8 bytes now: 4B common header + 4B message body header. */ 996 node.header_length_base_value = 0x8; 997 /* After MAC layer: Ether / VLAN. */ 998 node.in[0].arc_parse_graph_node = MLX5_GRAPH_ARC_NODE_MAC; 999 /* Type of compared condition should be 0xAEFE in the L2 layer. */ 1000 node.in[0].compare_condition_value = RTE_ETHER_TYPE_ECPRI; 1001 /* Sample #0: type in common header. */ 1002 node.sample[0].flow_match_sample_en = 1; 1003 /* Fixed offset. */ 1004 node.sample[0].flow_match_sample_offset_mode = 0x0; 1005 /* Only the 2nd byte will be used. */ 1006 node.sample[0].flow_match_sample_field_base_offset = 0x0; 1007 /* Sample #1: message payload. */ 1008 node.sample[1].flow_match_sample_en = 1; 1009 /* Fixed offset. */ 1010 node.sample[1].flow_match_sample_offset_mode = 0x0; 1011 /* 1012 * Only the first two bytes will be used right now, and its offset will 1013 * start after the common header that with the length of a DW(u32). 1014 */ 1015 node.sample[1].flow_match_sample_field_base_offset = sizeof(uint32_t); 1016 prf->obj = mlx5_devx_cmd_create_flex_parser(priv->sh->cdev->ctx, &node); 1017 if (!prf->obj) { 1018 DRV_LOG(ERR, "Failed to create flex parser node object."); 1019 return (rte_errno == 0) ? -ENODEV : -rte_errno; 1020 } 1021 prf->num = 2; 1022 ret = mlx5_devx_cmd_query_parse_samples(prf->obj, ids, prf->num, NULL); 1023 if (ret) { 1024 DRV_LOG(ERR, "Failed to query sample IDs."); 1025 goto error; 1026 } 1027 prf->offset[0] = 0x0; 1028 prf->offset[1] = sizeof(uint32_t); 1029 prf->ids[0] = ids[0]; 1030 prf->ids[1] = ids[1]; 1031 return 0; 1032 error: 1033 mlx5_devx_cmd_destroy(prf->obj); 1034 return (rte_errno == 0) ? -ENODEV : -rte_errno; 1035 } 1036 1037 /* 1038 * Destroy the flex parser node, including the parser itself, input / output 1039 * arcs and DW samples. Resources could be reused then. 1040 * 1041 * @param dev 1042 * Pointer to Ethernet device structure. 1043 */ 1044 static void 1045 mlx5_flex_parser_ecpri_release(struct rte_eth_dev *dev) 1046 { 1047 struct mlx5_priv *priv = dev->data->dev_private; 1048 struct mlx5_ecpri_parser_profile *prf = &priv->sh->ecpri_parser; 1049 1050 if (prf->obj) 1051 mlx5_devx_cmd_destroy(prf->obj); 1052 prf->obj = NULL; 1053 } 1054 1055 /* 1056 * Allocation of a flex parser for srh. Once refcnt is zero, the resources held 1057 * by this parser will be freed. 1058 * @param dev 1059 * Pointer to Ethernet device structure. 1060 * 1061 * @return 1062 * 0 on success, a negative errno value otherwise and rte_errno is set. 1063 */ 1064 int 1065 mlx5_alloc_srh_flex_parser(struct rte_eth_dev *dev) 1066 { 1067 struct mlx5_devx_graph_node_attr node = { 1068 .modify_field_select = 0, 1069 }; 1070 uint32_t i; 1071 uint32_t ids[MLX5_GRAPH_NODE_SAMPLE_NUM]; 1072 struct mlx5_priv *priv = dev->data->dev_private; 1073 struct mlx5_common_dev_config *config = &priv->sh->cdev->config; 1074 struct mlx5_hca_flex_attr *attr = &priv->sh->cdev->config.hca_attr.flex; 1075 void *fp = NULL, *ibv_ctx = priv->sh->cdev->ctx; 1076 int ret; 1077 1078 memset(ids, 0xff, sizeof(ids)); 1079 if (!config->hca_attr.parse_graph_flex_node || 1080 !config->hca_attr.flex.query_match_sample_info) { 1081 DRV_LOG(ERR, "Dynamic flex parser is not supported on HWS"); 1082 return -ENOTSUP; 1083 } 1084 if (__atomic_fetch_add(&priv->sh->srh_flex_parser.refcnt, 1, __ATOMIC_RELAXED) + 1 > 1) 1085 return 0; 1086 priv->sh->srh_flex_parser.flex.devx_fp = mlx5_malloc(MLX5_MEM_ZERO, 1087 sizeof(struct mlx5_flex_parser_devx), 0, SOCKET_ID_ANY); 1088 if (!priv->sh->srh_flex_parser.flex.devx_fp) 1089 return -ENOMEM; 1090 node.header_length_mode = MLX5_GRAPH_NODE_LEN_FIELD; 1091 /* Srv6 first two DW are not counted in. */ 1092 node.header_length_base_value = 0x8; 1093 /* The unit is uint64_t. */ 1094 node.header_length_field_shift = 0x3; 1095 /* Header length is the 2nd byte. */ 1096 node.header_length_field_offset = 0x8; 1097 if (attr->header_length_mask_width < 8) 1098 node.header_length_field_offset += 8 - attr->header_length_mask_width; 1099 node.header_length_field_mask = 0xF; 1100 /* One byte next header protocol. */ 1101 node.next_header_field_size = 0x8; 1102 node.in[0].arc_parse_graph_node = MLX5_GRAPH_ARC_NODE_IP; 1103 node.in[0].compare_condition_value = IPPROTO_ROUTING; 1104 /* Final IPv6 address. */ 1105 for (i = 0; i <= MLX5_SRV6_SAMPLE_NUM - 1 && i < MLX5_GRAPH_NODE_SAMPLE_NUM; i++) { 1106 node.sample[i].flow_match_sample_en = 1; 1107 node.sample[i].flow_match_sample_offset_mode = 1108 MLX5_GRAPH_SAMPLE_OFFSET_FIXED; 1109 /* First come first serve no matter inner or outer. */ 1110 node.sample[i].flow_match_sample_tunnel_mode = 1111 MLX5_GRAPH_SAMPLE_TUNNEL_FIRST; 1112 node.sample[i].flow_match_sample_field_base_offset = 1113 (i + 1) * sizeof(uint32_t); /* in bytes */ 1114 } 1115 node.sample[0].flow_match_sample_field_base_offset = 0; 1116 node.out[0].arc_parse_graph_node = MLX5_GRAPH_ARC_NODE_TCP; 1117 node.out[0].compare_condition_value = IPPROTO_TCP; 1118 node.out[1].arc_parse_graph_node = MLX5_GRAPH_ARC_NODE_UDP; 1119 node.out[1].compare_condition_value = IPPROTO_UDP; 1120 node.out[2].arc_parse_graph_node = MLX5_GRAPH_ARC_NODE_IPV6; 1121 node.out[2].compare_condition_value = IPPROTO_IPV6; 1122 fp = mlx5_devx_cmd_create_flex_parser(ibv_ctx, &node); 1123 if (!fp) { 1124 DRV_LOG(ERR, "Failed to create flex parser node object."); 1125 goto error; 1126 } 1127 priv->sh->srh_flex_parser.flex.devx_fp->devx_obj = fp; 1128 priv->sh->srh_flex_parser.flex.mapnum = MLX5_SRV6_SAMPLE_NUM; 1129 priv->sh->srh_flex_parser.flex.devx_fp->num_samples = MLX5_SRV6_SAMPLE_NUM; 1130 1131 ret = mlx5_devx_cmd_query_parse_samples(fp, ids, priv->sh->srh_flex_parser.flex.mapnum, 1132 &priv->sh->srh_flex_parser.flex.devx_fp->anchor_id); 1133 if (ret) { 1134 DRV_LOG(ERR, "Failed to query sample IDs."); 1135 goto error; 1136 } 1137 for (i = 0; i <= MLX5_SRV6_SAMPLE_NUM - 1 && i < MLX5_GRAPH_NODE_SAMPLE_NUM; i++) { 1138 ret = mlx5_devx_cmd_match_sample_info_query(ibv_ctx, ids[i], 1139 &priv->sh->srh_flex_parser.flex.devx_fp->sample_info[i]); 1140 if (ret) { 1141 DRV_LOG(ERR, "Failed to query sample id %u information.", ids[i]); 1142 goto error; 1143 } 1144 } 1145 for (i = 0; i <= MLX5_SRV6_SAMPLE_NUM - 1 && i < MLX5_GRAPH_NODE_SAMPLE_NUM; i++) { 1146 priv->sh->srh_flex_parser.flex.devx_fp->sample_ids[i] = ids[i]; 1147 priv->sh->srh_flex_parser.flex.map[i].width = sizeof(uint32_t) * CHAR_BIT; 1148 priv->sh->srh_flex_parser.flex.map[i].reg_id = i; 1149 priv->sh->srh_flex_parser.flex.map[i].shift = 1150 (i + 1) * sizeof(uint32_t) * CHAR_BIT; 1151 } 1152 priv->sh->srh_flex_parser.flex.map[0].shift = 0; 1153 return 0; 1154 error: 1155 if (fp) 1156 mlx5_devx_cmd_destroy(fp); 1157 if (priv->sh->srh_flex_parser.flex.devx_fp) 1158 mlx5_free(priv->sh->srh_flex_parser.flex.devx_fp); 1159 return (rte_errno == 0) ? -ENODEV : -rte_errno; 1160 } 1161 1162 /* 1163 * Destroy the flex parser node, including the parser itself, input / output 1164 * arcs and DW samples. Resources could be reused then. 1165 * 1166 * @param dev 1167 * Pointer to Ethernet device structure 1168 */ 1169 void 1170 mlx5_free_srh_flex_parser(struct rte_eth_dev *dev) 1171 { 1172 struct mlx5_priv *priv = dev->data->dev_private; 1173 struct mlx5_internal_flex_parser_profile *fp = &priv->sh->srh_flex_parser; 1174 1175 if (__atomic_fetch_sub(&fp->refcnt, 1, __ATOMIC_RELAXED) - 1) 1176 return; 1177 mlx5_devx_cmd_destroy(fp->flex.devx_fp->devx_obj); 1178 mlx5_free(fp->flex.devx_fp); 1179 fp->flex.devx_fp = NULL; 1180 } 1181 1182 uint32_t 1183 mlx5_get_supported_sw_parsing_offloads(const struct mlx5_hca_attr *attr) 1184 { 1185 uint32_t sw_parsing_offloads = 0; 1186 1187 if (attr->swp) { 1188 sw_parsing_offloads |= MLX5_SW_PARSING_CAP; 1189 if (attr->swp_csum) 1190 sw_parsing_offloads |= MLX5_SW_PARSING_CSUM_CAP; 1191 1192 if (attr->swp_lso) 1193 sw_parsing_offloads |= MLX5_SW_PARSING_TSO_CAP; 1194 } 1195 return sw_parsing_offloads; 1196 } 1197 1198 uint32_t 1199 mlx5_get_supported_tunneling_offloads(const struct mlx5_hca_attr *attr) 1200 { 1201 uint32_t tn_offloads = 0; 1202 1203 if (attr->tunnel_stateless_vxlan) 1204 tn_offloads |= MLX5_TUNNELED_OFFLOADS_VXLAN_CAP; 1205 if (attr->tunnel_stateless_gre) 1206 tn_offloads |= MLX5_TUNNELED_OFFLOADS_GRE_CAP; 1207 if (attr->tunnel_stateless_geneve_rx) 1208 tn_offloads |= MLX5_TUNNELED_OFFLOADS_GENEVE_CAP; 1209 return tn_offloads; 1210 } 1211 1212 /* Fill all fields of UAR structure. */ 1213 static int 1214 mlx5_rxtx_uars_prepare(struct mlx5_dev_ctx_shared *sh) 1215 { 1216 int ret; 1217 1218 ret = mlx5_devx_uar_prepare(sh->cdev, &sh->tx_uar); 1219 if (ret) { 1220 DRV_LOG(ERR, "Failed to prepare Tx DevX UAR."); 1221 return -rte_errno; 1222 } 1223 MLX5_ASSERT(sh->tx_uar.obj); 1224 MLX5_ASSERT(mlx5_os_get_devx_uar_base_addr(sh->tx_uar.obj)); 1225 ret = mlx5_devx_uar_prepare(sh->cdev, &sh->rx_uar); 1226 if (ret) { 1227 DRV_LOG(ERR, "Failed to prepare Rx DevX UAR."); 1228 mlx5_devx_uar_release(&sh->tx_uar); 1229 return -rte_errno; 1230 } 1231 MLX5_ASSERT(sh->rx_uar.obj); 1232 MLX5_ASSERT(mlx5_os_get_devx_uar_base_addr(sh->rx_uar.obj)); 1233 return 0; 1234 } 1235 1236 static void 1237 mlx5_rxtx_uars_release(struct mlx5_dev_ctx_shared *sh) 1238 { 1239 mlx5_devx_uar_release(&sh->rx_uar); 1240 mlx5_devx_uar_release(&sh->tx_uar); 1241 } 1242 1243 /** 1244 * rte_mempool_walk() callback to unregister Rx mempools. 1245 * It used when implicit mempool registration is disabled. 1246 * 1247 * @param mp 1248 * The mempool being walked. 1249 * @param arg 1250 * Pointer to the device shared context. 1251 */ 1252 static void 1253 mlx5_dev_ctx_shared_rx_mempool_unregister_cb(struct rte_mempool *mp, void *arg) 1254 { 1255 struct mlx5_dev_ctx_shared *sh = arg; 1256 1257 mlx5_dev_mempool_unregister(sh->cdev, mp); 1258 } 1259 1260 /** 1261 * Callback used when implicit mempool registration is disabled 1262 * in order to track Rx mempool destruction. 1263 * 1264 * @param event 1265 * Mempool life cycle event. 1266 * @param mp 1267 * An Rx mempool registered explicitly when the port is started. 1268 * @param arg 1269 * Pointer to a device shared context. 1270 */ 1271 static void 1272 mlx5_dev_ctx_shared_rx_mempool_event_cb(enum rte_mempool_event event, 1273 struct rte_mempool *mp, void *arg) 1274 { 1275 struct mlx5_dev_ctx_shared *sh = arg; 1276 1277 if (event == RTE_MEMPOOL_EVENT_DESTROY) 1278 mlx5_dev_mempool_unregister(sh->cdev, mp); 1279 } 1280 1281 int 1282 mlx5_dev_ctx_shared_mempool_subscribe(struct rte_eth_dev *dev) 1283 { 1284 struct mlx5_priv *priv = dev->data->dev_private; 1285 struct mlx5_dev_ctx_shared *sh = priv->sh; 1286 int ret; 1287 1288 /* Check if we only need to track Rx mempool destruction. */ 1289 if (!sh->cdev->config.mr_mempool_reg_en) { 1290 ret = rte_mempool_event_callback_register 1291 (mlx5_dev_ctx_shared_rx_mempool_event_cb, sh); 1292 return ret == 0 || rte_errno == EEXIST ? 0 : ret; 1293 } 1294 return mlx5_dev_mempool_subscribe(sh->cdev); 1295 } 1296 1297 /** 1298 * Set up multiple TISs with different affinities according to 1299 * number of bonding ports 1300 * 1301 * @param priv 1302 * Pointer of shared context. 1303 * 1304 * @return 1305 * Zero on success, -1 otherwise. 1306 */ 1307 static int 1308 mlx5_setup_tis(struct mlx5_dev_ctx_shared *sh) 1309 { 1310 struct mlx5_devx_lag_context lag_ctx = { 0 }; 1311 struct mlx5_devx_tis_attr tis_attr = { 0 }; 1312 int i; 1313 1314 tis_attr.transport_domain = sh->td->id; 1315 if (sh->bond.n_port) { 1316 if (!mlx5_devx_cmd_query_lag(sh->cdev->ctx, &lag_ctx)) { 1317 sh->lag.tx_remap_affinity[0] = 1318 lag_ctx.tx_remap_affinity_1; 1319 sh->lag.tx_remap_affinity[1] = 1320 lag_ctx.tx_remap_affinity_2; 1321 sh->lag.affinity_mode = lag_ctx.port_select_mode; 1322 } else { 1323 DRV_LOG(ERR, "Failed to query lag affinity."); 1324 return -1; 1325 } 1326 if (sh->lag.affinity_mode == MLX5_LAG_MODE_TIS) 1327 DRV_LOG(DEBUG, "LAG number of ports : %d, affinity_1 & 2 : pf%d & %d.\n", 1328 sh->bond.n_port, lag_ctx.tx_remap_affinity_1, 1329 lag_ctx.tx_remap_affinity_2); 1330 else if (sh->lag.affinity_mode == MLX5_LAG_MODE_HASH) 1331 DRV_LOG(INFO, "Device %s enabled HW hash based LAG.", 1332 sh->ibdev_name); 1333 } 1334 for (i = 0; i <= sh->bond.n_port; i++) { 1335 /* 1336 * lag_tx_port_affinity: 0 auto-selection, 1 PF1, 2 PF2 vice versa. 1337 * Each TIS binds to one PF by setting lag_tx_port_affinity (> 0). 1338 * Once LAG enabled, we create multiple TISs and bind each one to 1339 * different PFs, then TIS[i+1] gets affinity i+1 and goes to PF i+1. 1340 * TIS[0] is reserved for HW Hash mode. 1341 */ 1342 tis_attr.lag_tx_port_affinity = i; 1343 sh->tis[i] = mlx5_devx_cmd_create_tis(sh->cdev->ctx, &tis_attr); 1344 if (!sh->tis[i]) { 1345 DRV_LOG(ERR, "Failed to create TIS %d/%d for [bonding] device" 1346 " %s.", i, sh->bond.n_port, 1347 sh->ibdev_name); 1348 return -1; 1349 } 1350 } 1351 return 0; 1352 } 1353 1354 /** 1355 * Verify and store value for share device argument. 1356 * 1357 * @param[in] key 1358 * Key argument to verify. 1359 * @param[in] val 1360 * Value associated with key. 1361 * @param opaque 1362 * User data. 1363 * 1364 * @return 1365 * 0 on success, a negative errno value otherwise and rte_errno is set. 1366 */ 1367 static int 1368 mlx5_dev_args_check_handler(const char *key, const char *val, void *opaque) 1369 { 1370 struct mlx5_sh_config *config = opaque; 1371 signed long tmp; 1372 1373 errno = 0; 1374 tmp = strtol(val, NULL, 0); 1375 if (errno) { 1376 rte_errno = errno; 1377 DRV_LOG(WARNING, "%s: \"%s\" is not a valid integer", key, val); 1378 return -rte_errno; 1379 } 1380 if (tmp < 0 && strcmp(MLX5_TX_PP, key) && strcmp(MLX5_TX_SKEW, key)) { 1381 /* Negative values are acceptable for some keys only. */ 1382 rte_errno = EINVAL; 1383 DRV_LOG(WARNING, "%s: invalid negative value \"%s\"", key, val); 1384 return -rte_errno; 1385 } 1386 if (strcmp(MLX5_TX_PP, key) == 0) { 1387 unsigned long mod = tmp >= 0 ? tmp : -tmp; 1388 1389 if (!mod) { 1390 DRV_LOG(ERR, "Zero Tx packet pacing parameter."); 1391 rte_errno = EINVAL; 1392 return -rte_errno; 1393 } 1394 config->tx_pp = tmp; 1395 } else if (strcmp(MLX5_TX_SKEW, key) == 0) { 1396 config->tx_skew = tmp; 1397 } else if (strcmp(MLX5_L3_VXLAN_EN, key) == 0) { 1398 config->l3_vxlan_en = !!tmp; 1399 } else if (strcmp(MLX5_VF_NL_EN, key) == 0) { 1400 config->vf_nl_en = !!tmp; 1401 } else if (strcmp(MLX5_DV_ESW_EN, key) == 0) { 1402 config->dv_esw_en = !!tmp; 1403 } else if (strcmp(MLX5_DV_FLOW_EN, key) == 0) { 1404 if (tmp > 2) { 1405 DRV_LOG(ERR, "Invalid %s parameter.", key); 1406 rte_errno = EINVAL; 1407 return -rte_errno; 1408 } 1409 config->dv_flow_en = tmp; 1410 } else if (strcmp(MLX5_DV_XMETA_EN, key) == 0) { 1411 if (tmp != MLX5_XMETA_MODE_LEGACY && 1412 tmp != MLX5_XMETA_MODE_META16 && 1413 tmp != MLX5_XMETA_MODE_META32 && 1414 tmp != MLX5_XMETA_MODE_MISS_INFO && 1415 tmp != MLX5_XMETA_MODE_META32_HWS) { 1416 DRV_LOG(ERR, "Invalid extensive metadata parameter."); 1417 rte_errno = EINVAL; 1418 return -rte_errno; 1419 } 1420 if (tmp != MLX5_XMETA_MODE_MISS_INFO) 1421 config->dv_xmeta_en = tmp; 1422 else 1423 config->dv_miss_info = 1; 1424 } else if (strcmp(MLX5_LACP_BY_USER, key) == 0) { 1425 config->lacp_by_user = !!tmp; 1426 } else if (strcmp(MLX5_RECLAIM_MEM, key) == 0) { 1427 if (tmp != MLX5_RCM_NONE && 1428 tmp != MLX5_RCM_LIGHT && 1429 tmp != MLX5_RCM_AGGR) { 1430 DRV_LOG(ERR, "Unrecognize %s: \"%s\"", key, val); 1431 rte_errno = EINVAL; 1432 return -rte_errno; 1433 } 1434 config->reclaim_mode = tmp; 1435 } else if (strcmp(MLX5_DECAP_EN, key) == 0) { 1436 config->decap_en = !!tmp; 1437 } else if (strcmp(MLX5_ALLOW_DUPLICATE_PATTERN, key) == 0) { 1438 config->allow_duplicate_pattern = !!tmp; 1439 } else if (strcmp(MLX5_FDB_DEFAULT_RULE_EN, key) == 0) { 1440 config->fdb_def_rule = !!tmp; 1441 } else if (strcmp(MLX5_HWS_CNT_SERVICE_CORE, key) == 0) { 1442 config->cnt_svc.service_core = tmp; 1443 } else if (strcmp(MLX5_HWS_CNT_CYCLE_TIME, key) == 0) { 1444 config->cnt_svc.cycle_time = tmp; 1445 } else if (strcmp(MLX5_REPR_MATCHING_EN, key) == 0) { 1446 config->repr_matching = !!tmp; 1447 } 1448 return 0; 1449 } 1450 1451 /** 1452 * Parse user device parameters and adjust them according to device 1453 * capabilities. 1454 * 1455 * @param sh 1456 * Pointer to shared device context. 1457 * @param mkvlist 1458 * Pointer to mlx5 kvargs control, can be NULL if there is no devargs. 1459 * @param config 1460 * Pointer to shared device configuration structure. 1461 * 1462 * @return 1463 * 0 on success, a negative errno value otherwise and rte_errno is set. 1464 */ 1465 static int 1466 mlx5_shared_dev_ctx_args_config(struct mlx5_dev_ctx_shared *sh, 1467 struct mlx5_kvargs_ctrl *mkvlist, 1468 struct mlx5_sh_config *config) 1469 { 1470 const char **params = (const char *[]){ 1471 MLX5_TX_PP, 1472 MLX5_TX_SKEW, 1473 MLX5_L3_VXLAN_EN, 1474 MLX5_VF_NL_EN, 1475 MLX5_DV_ESW_EN, 1476 MLX5_DV_FLOW_EN, 1477 MLX5_DV_XMETA_EN, 1478 MLX5_LACP_BY_USER, 1479 MLX5_RECLAIM_MEM, 1480 MLX5_DECAP_EN, 1481 MLX5_ALLOW_DUPLICATE_PATTERN, 1482 MLX5_FDB_DEFAULT_RULE_EN, 1483 MLX5_HWS_CNT_SERVICE_CORE, 1484 MLX5_HWS_CNT_CYCLE_TIME, 1485 MLX5_REPR_MATCHING_EN, 1486 NULL, 1487 }; 1488 int ret = 0; 1489 1490 /* Default configuration. */ 1491 memset(config, 0, sizeof(*config)); 1492 config->vf_nl_en = 1; 1493 config->dv_esw_en = 1; 1494 config->dv_flow_en = 1; 1495 config->decap_en = 1; 1496 config->allow_duplicate_pattern = 1; 1497 config->fdb_def_rule = 1; 1498 config->cnt_svc.cycle_time = MLX5_CNT_SVC_CYCLE_TIME_DEFAULT; 1499 config->cnt_svc.service_core = rte_get_main_lcore(); 1500 config->repr_matching = 1; 1501 if (mkvlist != NULL) { 1502 /* Process parameters. */ 1503 ret = mlx5_kvargs_process(mkvlist, params, 1504 mlx5_dev_args_check_handler, config); 1505 if (ret) { 1506 DRV_LOG(ERR, "Failed to process device arguments: %s", 1507 strerror(rte_errno)); 1508 return -rte_errno; 1509 } 1510 } 1511 /* Adjust parameters according to device capabilities. */ 1512 if (config->dv_flow_en && !sh->dev_cap.dv_flow_en) { 1513 DRV_LOG(WARNING, "DV flow is not supported."); 1514 config->dv_flow_en = 0; 1515 } 1516 if (config->dv_esw_en && !sh->dev_cap.dv_esw_en) { 1517 DRV_LOG(DEBUG, "E-Switch DV flow is not supported."); 1518 config->dv_esw_en = 0; 1519 } 1520 if (config->dv_esw_en && !config->dv_flow_en) { 1521 DRV_LOG(DEBUG, 1522 "E-Switch DV flow is supported only when DV flow is enabled."); 1523 config->dv_esw_en = 0; 1524 } 1525 if (config->dv_miss_info && config->dv_esw_en) 1526 config->dv_xmeta_en = MLX5_XMETA_MODE_META16; 1527 if (!config->dv_esw_en && 1528 config->dv_xmeta_en != MLX5_XMETA_MODE_LEGACY) { 1529 DRV_LOG(WARNING, 1530 "Metadata mode %u is not supported (no E-Switch).", 1531 config->dv_xmeta_en); 1532 config->dv_xmeta_en = MLX5_XMETA_MODE_LEGACY; 1533 } 1534 if (config->dv_flow_en != 2 && !config->repr_matching) { 1535 DRV_LOG(DEBUG, "Disabling representor matching is valid only " 1536 "when HW Steering is enabled."); 1537 config->repr_matching = 1; 1538 } 1539 if (config->tx_pp && !sh->dev_cap.txpp_en) { 1540 DRV_LOG(ERR, "Packet pacing is not supported."); 1541 rte_errno = ENODEV; 1542 return -rte_errno; 1543 } 1544 if (!config->tx_pp && config->tx_skew && 1545 !sh->cdev->config.hca_attr.wait_on_time) { 1546 DRV_LOG(WARNING, 1547 "\"tx_skew\" doesn't affect without \"tx_pp\"."); 1548 } 1549 /* Check for LRO support. */ 1550 if (mlx5_devx_obj_ops_en(sh) && sh->cdev->config.hca_attr.lro_cap) { 1551 /* TBD check tunnel lro caps. */ 1552 config->lro_allowed = 1; 1553 DRV_LOG(DEBUG, "LRO is allowed."); 1554 DRV_LOG(DEBUG, 1555 "LRO minimal size of TCP segment required for coalescing is %d bytes.", 1556 sh->cdev->config.hca_attr.lro_min_mss_size); 1557 } 1558 /* 1559 * If HW has bug working with tunnel packet decapsulation and scatter 1560 * FCS, and decapsulation is needed, clear the hw_fcs_strip bit. 1561 * Then RTE_ETH_RX_OFFLOAD_KEEP_CRC bit will not be set anymore. 1562 */ 1563 if (sh->dev_cap.scatter_fcs_w_decap_disable && sh->config.decap_en) 1564 config->hw_fcs_strip = 0; 1565 else 1566 config->hw_fcs_strip = sh->dev_cap.hw_fcs_strip; 1567 DRV_LOG(DEBUG, "FCS stripping configuration is %ssupported", 1568 (config->hw_fcs_strip ? "" : "not ")); 1569 DRV_LOG(DEBUG, "\"tx_pp\" is %d.", config->tx_pp); 1570 DRV_LOG(DEBUG, "\"tx_skew\" is %d.", config->tx_skew); 1571 DRV_LOG(DEBUG, "\"reclaim_mode\" is %u.", config->reclaim_mode); 1572 DRV_LOG(DEBUG, "\"dv_esw_en\" is %u.", config->dv_esw_en); 1573 DRV_LOG(DEBUG, "\"dv_flow_en\" is %u.", config->dv_flow_en); 1574 DRV_LOG(DEBUG, "\"dv_xmeta_en\" is %u.", config->dv_xmeta_en); 1575 DRV_LOG(DEBUG, "\"dv_miss_info\" is %u.", config->dv_miss_info); 1576 DRV_LOG(DEBUG, "\"l3_vxlan_en\" is %u.", config->l3_vxlan_en); 1577 DRV_LOG(DEBUG, "\"vf_nl_en\" is %u.", config->vf_nl_en); 1578 DRV_LOG(DEBUG, "\"lacp_by_user\" is %u.", config->lacp_by_user); 1579 DRV_LOG(DEBUG, "\"decap_en\" is %u.", config->decap_en); 1580 DRV_LOG(DEBUG, "\"allow_duplicate_pattern\" is %u.", 1581 config->allow_duplicate_pattern); 1582 DRV_LOG(DEBUG, "\"fdb_def_rule_en\" is %u.", config->fdb_def_rule); 1583 DRV_LOG(DEBUG, "\"repr_matching_en\" is %u.", config->repr_matching); 1584 return 0; 1585 } 1586 1587 /** 1588 * Configure realtime timestamp format. 1589 * 1590 * @param sh 1591 * Pointer to mlx5_dev_ctx_shared object. 1592 * @param hca_attr 1593 * Pointer to DevX HCA capabilities structure. 1594 */ 1595 void 1596 mlx5_rt_timestamp_config(struct mlx5_dev_ctx_shared *sh, 1597 struct mlx5_hca_attr *hca_attr) 1598 { 1599 uint32_t dw_cnt = MLX5_ST_SZ_DW(register_mtutc); 1600 uint32_t reg[dw_cnt]; 1601 int ret = ENOTSUP; 1602 1603 if (hca_attr->access_register_user) 1604 ret = mlx5_devx_cmd_register_read(sh->cdev->ctx, 1605 MLX5_REGISTER_ID_MTUTC, 0, 1606 reg, dw_cnt); 1607 if (!ret) { 1608 uint32_t ts_mode; 1609 1610 /* MTUTC register is read successfully. */ 1611 ts_mode = MLX5_GET(register_mtutc, reg, time_stamp_mode); 1612 if (ts_mode == MLX5_MTUTC_TIMESTAMP_MODE_REAL_TIME) 1613 sh->dev_cap.rt_timestamp = 1; 1614 } else { 1615 /* Kernel does not support register reading. */ 1616 if (hca_attr->dev_freq_khz == (NS_PER_S / MS_PER_S)) 1617 sh->dev_cap.rt_timestamp = 1; 1618 } 1619 } 1620 1621 static void 1622 mlx5_init_hws_flow_tags_registers(struct mlx5_dev_ctx_shared *sh) 1623 { 1624 struct mlx5_dev_registers *reg = &sh->registers; 1625 uint32_t meta_mode = sh->config.dv_xmeta_en; 1626 uint16_t masks = (uint16_t)sh->cdev->config.hca_attr.set_reg_c; 1627 uint16_t unset = 0; 1628 uint32_t i, j; 1629 1630 /* 1631 * The CAPA is global for common device but only used in net. 1632 * It is shared per eswitch domain. 1633 */ 1634 if (reg->aso_reg != REG_NON) 1635 unset |= 1 << mlx5_regc_index(reg->aso_reg); 1636 unset |= 1 << mlx5_regc_index(REG_C_6); 1637 if (sh->config.dv_esw_en) 1638 unset |= 1 << mlx5_regc_index(REG_C_0); 1639 if (meta_mode == MLX5_XMETA_MODE_META32_HWS) 1640 unset |= 1 << mlx5_regc_index(REG_C_1); 1641 masks &= ~unset; 1642 for (i = 0, j = 0; i < MLX5_FLOW_HW_TAGS_MAX; i++) { 1643 if (!!((1 << i) & masks)) 1644 reg->hw_avl_tags[j++] = mlx5_regc_value(i); 1645 } 1646 } 1647 1648 static void 1649 mlx5_init_aso_register(struct mlx5_dev_ctx_shared *sh) 1650 { 1651 #if defined(HAVE_MLX5_DR_CREATE_ACTION_ASO_EXT) 1652 const struct mlx5_hca_attr *hca_attr = &sh->cdev->config.hca_attr; 1653 const struct mlx5_hca_qos_attr *qos = &hca_attr->qos; 1654 uint8_t reg_c_mask = qos->flow_meter_reg_c_ids & 0xfc; 1655 1656 if (!(qos->sup && qos->flow_meter_old && sh->config.dv_flow_en)) 1657 return; 1658 /* 1659 * Meter needs two REG_C's for color match and pre-sfx 1660 * flow match. Here get the REG_C for color match. 1661 * REG_C_0 and REG_C_1 is reserved for metadata feature. 1662 */ 1663 if (rte_popcount32(reg_c_mask) > 0) { 1664 /* 1665 * The meter color register is used by the 1666 * flow-hit feature as well. 1667 * The flow-hit feature must use REG_C_3 1668 * Prefer REG_C_3 if it is available. 1669 */ 1670 if (reg_c_mask & (1 << mlx5_regc_index(REG_C_3))) 1671 sh->registers.aso_reg = REG_C_3; 1672 else 1673 sh->registers.aso_reg = 1674 mlx5_regc_value(ffs(reg_c_mask) - 1); 1675 } 1676 #else 1677 RTE_SET_USED(sh); 1678 #endif 1679 } 1680 1681 static void 1682 mlx5_init_shared_dev_registers(struct mlx5_dev_ctx_shared *sh) 1683 { 1684 if (sh->cdev->config.devx) 1685 mlx5_init_aso_register(sh); 1686 if (sh->registers.aso_reg != REG_NON) { 1687 DRV_LOG(DEBUG, "ASO register: REG_C%d", 1688 mlx5_regc_index(sh->registers.aso_reg)); 1689 } else { 1690 DRV_LOG(DEBUG, "ASO register: NONE"); 1691 } 1692 mlx5_init_hws_flow_tags_registers(sh); 1693 } 1694 1695 /** 1696 * Allocate shared device context. If there is multiport device the 1697 * master and representors will share this context, if there is single 1698 * port dedicated device, the context will be used by only given 1699 * port due to unification. 1700 * 1701 * Routine first searches the context for the specified device name, 1702 * if found the shared context assumed and reference counter is incremented. 1703 * If no context found the new one is created and initialized with specified 1704 * device context and parameters. 1705 * 1706 * @param[in] spawn 1707 * Pointer to the device attributes (name, port, etc). 1708 * @param mkvlist 1709 * Pointer to mlx5 kvargs control, can be NULL if there is no devargs. 1710 * 1711 * @return 1712 * Pointer to mlx5_dev_ctx_shared object on success, 1713 * otherwise NULL and rte_errno is set. 1714 */ 1715 struct mlx5_dev_ctx_shared * 1716 mlx5_alloc_shared_dev_ctx(const struct mlx5_dev_spawn_data *spawn, 1717 struct mlx5_kvargs_ctrl *mkvlist) 1718 { 1719 struct mlx5_dev_ctx_shared *sh; 1720 int err = 0; 1721 uint32_t i; 1722 1723 MLX5_ASSERT(spawn); 1724 /* Secondary process should not create the shared context. */ 1725 MLX5_ASSERT(rte_eal_process_type() == RTE_PROC_PRIMARY); 1726 pthread_mutex_lock(&mlx5_dev_ctx_list_mutex); 1727 /* Search for IB context by device name. */ 1728 LIST_FOREACH(sh, &mlx5_dev_ctx_list, next) { 1729 if (!strcmp(sh->ibdev_name, spawn->phys_dev_name)) { 1730 sh->refcnt++; 1731 goto exit; 1732 } 1733 } 1734 /* No device found, we have to create new shared context. */ 1735 MLX5_ASSERT(spawn->max_port); 1736 sh = mlx5_malloc(MLX5_MEM_ZERO | MLX5_MEM_RTE, 1737 sizeof(struct mlx5_dev_ctx_shared) + 1738 spawn->max_port * sizeof(struct mlx5_dev_shared_port), 1739 RTE_CACHE_LINE_SIZE, SOCKET_ID_ANY); 1740 if (!sh) { 1741 DRV_LOG(ERR, "Shared context allocation failure."); 1742 rte_errno = ENOMEM; 1743 goto exit; 1744 } 1745 pthread_mutex_init(&sh->txpp.mutex, NULL); 1746 sh->numa_node = spawn->cdev->dev->numa_node; 1747 sh->cdev = spawn->cdev; 1748 sh->esw_mode = !!(spawn->info.master || spawn->info.representor); 1749 if (spawn->bond_info) 1750 sh->bond = *spawn->bond_info; 1751 err = mlx5_os_capabilities_prepare(sh); 1752 if (err) { 1753 DRV_LOG(ERR, "Fail to configure device capabilities."); 1754 goto error; 1755 } 1756 err = mlx5_shared_dev_ctx_args_config(sh, mkvlist, &sh->config); 1757 if (err) { 1758 DRV_LOG(ERR, "Failed to process device configure: %s", 1759 strerror(rte_errno)); 1760 goto error; 1761 } 1762 sh->refcnt = 1; 1763 sh->max_port = spawn->max_port; 1764 strncpy(sh->ibdev_name, mlx5_os_get_ctx_device_name(sh->cdev->ctx), 1765 sizeof(sh->ibdev_name) - 1); 1766 strncpy(sh->ibdev_path, mlx5_os_get_ctx_device_path(sh->cdev->ctx), 1767 sizeof(sh->ibdev_path) - 1); 1768 /* 1769 * Setting port_id to max unallowed value means there is no interrupt 1770 * subhandler installed for the given port index i. 1771 */ 1772 for (i = 0; i < sh->max_port; i++) { 1773 sh->port[i].ih_port_id = RTE_MAX_ETHPORTS; 1774 sh->port[i].devx_ih_port_id = RTE_MAX_ETHPORTS; 1775 sh->port[i].nl_ih_port_id = RTE_MAX_ETHPORTS; 1776 } 1777 if (sh->cdev->config.devx) { 1778 sh->td = mlx5_devx_cmd_create_td(sh->cdev->ctx); 1779 if (!sh->td) { 1780 DRV_LOG(ERR, "TD allocation failure"); 1781 rte_errno = ENOMEM; 1782 goto error; 1783 } 1784 if (mlx5_setup_tis(sh)) { 1785 DRV_LOG(ERR, "TIS allocation failure"); 1786 rte_errno = ENOMEM; 1787 goto error; 1788 } 1789 err = mlx5_rxtx_uars_prepare(sh); 1790 if (err) 1791 goto error; 1792 #ifndef RTE_ARCH_64 1793 } else { 1794 /* Initialize UAR access locks for 32bit implementations. */ 1795 rte_spinlock_init(&sh->uar_lock_cq); 1796 for (i = 0; i < MLX5_UAR_PAGE_NUM_MAX; i++) 1797 rte_spinlock_init(&sh->uar_lock[i]); 1798 #endif 1799 } 1800 mlx5_os_dev_shared_handler_install(sh); 1801 if (LIST_EMPTY(&mlx5_dev_ctx_list)) { 1802 err = mlx5_flow_os_init_workspace_once(); 1803 if (err) 1804 goto error; 1805 } 1806 err = mlx5_flow_counters_mng_init(sh); 1807 if (err) { 1808 DRV_LOG(ERR, "Fail to initialize counters manage."); 1809 goto error; 1810 } 1811 mlx5_flow_aging_init(sh); 1812 mlx5_flow_ipool_create(sh); 1813 /* Add context to the global device list. */ 1814 LIST_INSERT_HEAD(&mlx5_dev_ctx_list, sh, next); 1815 rte_spinlock_init(&sh->geneve_tlv_opt_sl); 1816 mlx5_init_shared_dev_registers(sh); 1817 /* Init counter pool list header and lock. */ 1818 LIST_INIT(&sh->hws_cpool_list); 1819 rte_spinlock_init(&sh->cpool_lock); 1820 exit: 1821 pthread_mutex_unlock(&mlx5_dev_ctx_list_mutex); 1822 return sh; 1823 error: 1824 err = rte_errno; 1825 pthread_mutex_destroy(&sh->txpp.mutex); 1826 pthread_mutex_unlock(&mlx5_dev_ctx_list_mutex); 1827 MLX5_ASSERT(sh); 1828 mlx5_rxtx_uars_release(sh); 1829 i = 0; 1830 do { 1831 if (sh->tis[i]) 1832 claim_zero(mlx5_devx_cmd_destroy(sh->tis[i])); 1833 } while (++i <= (uint32_t)sh->bond.n_port); 1834 if (sh->td) 1835 claim_zero(mlx5_devx_cmd_destroy(sh->td)); 1836 mlx5_free(sh); 1837 rte_errno = err; 1838 return NULL; 1839 } 1840 1841 /** 1842 * Create LWM event_channel and interrupt handle for shared device 1843 * context. All rxqs sharing the device context share the event_channel. 1844 * A callback is registered in interrupt thread to receive the LWM event. 1845 * 1846 * @param[in] priv 1847 * Pointer to mlx5_priv instance. 1848 * 1849 * @return 1850 * 0 on success, negative with rte_errno set. 1851 */ 1852 int 1853 mlx5_lwm_setup(struct mlx5_priv *priv) 1854 { 1855 int fd_lwm; 1856 1857 pthread_mutex_init(&priv->sh->lwm_config_lock, NULL); 1858 priv->sh->devx_channel_lwm = mlx5_os_devx_create_event_channel 1859 (priv->sh->cdev->ctx, 1860 MLX5DV_DEVX_CREATE_EVENT_CHANNEL_FLAGS_OMIT_EV_DATA); 1861 if (!priv->sh->devx_channel_lwm) 1862 goto err; 1863 fd_lwm = mlx5_os_get_devx_channel_fd(priv->sh->devx_channel_lwm); 1864 priv->sh->intr_handle_lwm = mlx5_os_interrupt_handler_create 1865 (RTE_INTR_INSTANCE_F_SHARED, true, 1866 fd_lwm, mlx5_dev_interrupt_handler_lwm, priv); 1867 if (!priv->sh->intr_handle_lwm) 1868 goto err; 1869 return 0; 1870 err: 1871 if (priv->sh->devx_channel_lwm) { 1872 mlx5_os_devx_destroy_event_channel 1873 (priv->sh->devx_channel_lwm); 1874 priv->sh->devx_channel_lwm = NULL; 1875 } 1876 pthread_mutex_destroy(&priv->sh->lwm_config_lock); 1877 return -rte_errno; 1878 } 1879 1880 /** 1881 * Destroy LWM event_channel and interrupt handle for shared device 1882 * context before free this context. The interrupt handler is also 1883 * unregistered. 1884 * 1885 * @param[in] sh 1886 * Pointer to shared device context. 1887 */ 1888 void 1889 mlx5_lwm_unset(struct mlx5_dev_ctx_shared *sh) 1890 { 1891 if (sh->intr_handle_lwm) { 1892 mlx5_os_interrupt_handler_destroy(sh->intr_handle_lwm, 1893 mlx5_dev_interrupt_handler_lwm, (void *)-1); 1894 sh->intr_handle_lwm = NULL; 1895 } 1896 if (sh->devx_channel_lwm) { 1897 mlx5_os_devx_destroy_event_channel 1898 (sh->devx_channel_lwm); 1899 sh->devx_channel_lwm = NULL; 1900 } 1901 pthread_mutex_destroy(&sh->lwm_config_lock); 1902 } 1903 1904 /** 1905 * Free shared IB device context. Decrement counter and if zero free 1906 * all allocated resources and close handles. 1907 * 1908 * @param[in] sh 1909 * Pointer to mlx5_dev_ctx_shared object to free 1910 */ 1911 void 1912 mlx5_free_shared_dev_ctx(struct mlx5_dev_ctx_shared *sh) 1913 { 1914 int ret; 1915 int i = 0; 1916 1917 pthread_mutex_lock(&mlx5_dev_ctx_list_mutex); 1918 #ifdef RTE_LIBRTE_MLX5_DEBUG 1919 /* Check the object presence in the list. */ 1920 struct mlx5_dev_ctx_shared *lctx; 1921 1922 LIST_FOREACH(lctx, &mlx5_dev_ctx_list, next) 1923 if (lctx == sh) 1924 break; 1925 MLX5_ASSERT(lctx); 1926 if (lctx != sh) { 1927 DRV_LOG(ERR, "Freeing non-existing shared IB context"); 1928 goto exit; 1929 } 1930 #endif 1931 MLX5_ASSERT(sh); 1932 MLX5_ASSERT(sh->refcnt); 1933 /* Secondary process should not free the shared context. */ 1934 MLX5_ASSERT(rte_eal_process_type() == RTE_PROC_PRIMARY); 1935 if (--sh->refcnt) 1936 goto exit; 1937 /* Stop watching for mempool events and unregister all mempools. */ 1938 if (!sh->cdev->config.mr_mempool_reg_en) { 1939 ret = rte_mempool_event_callback_unregister 1940 (mlx5_dev_ctx_shared_rx_mempool_event_cb, sh); 1941 if (ret == 0) 1942 rte_mempool_walk 1943 (mlx5_dev_ctx_shared_rx_mempool_unregister_cb, sh); 1944 } 1945 /* Remove context from the global device list. */ 1946 LIST_REMOVE(sh, next); 1947 /* Release resources on the last device removal. */ 1948 if (LIST_EMPTY(&mlx5_dev_ctx_list)) { 1949 mlx5_os_net_cleanup(); 1950 mlx5_flow_os_release_workspace(); 1951 } 1952 pthread_mutex_unlock(&mlx5_dev_ctx_list_mutex); 1953 if (sh->flex_parsers_dv) { 1954 mlx5_list_destroy(sh->flex_parsers_dv); 1955 sh->flex_parsers_dv = NULL; 1956 } 1957 /* 1958 * Ensure there is no async event handler installed. 1959 * Only primary process handles async device events. 1960 **/ 1961 mlx5_flow_counters_mng_close(sh); 1962 if (sh->ct_mng) 1963 mlx5_flow_aso_ct_mng_close(sh); 1964 if (sh->aso_age_mng) { 1965 mlx5_flow_aso_age_mng_close(sh); 1966 sh->aso_age_mng = NULL; 1967 } 1968 if (sh->mtrmng) 1969 mlx5_aso_flow_mtrs_mng_close(sh); 1970 mlx5_flow_ipool_destroy(sh); 1971 mlx5_os_dev_shared_handler_uninstall(sh); 1972 mlx5_rxtx_uars_release(sh); 1973 do { 1974 if (sh->tis[i]) 1975 claim_zero(mlx5_devx_cmd_destroy(sh->tis[i])); 1976 } while (++i <= sh->bond.n_port); 1977 if (sh->td) 1978 claim_zero(mlx5_devx_cmd_destroy(sh->td)); 1979 #ifdef HAVE_MLX5_HWS_SUPPORT 1980 /* HWS manages geneve_tlv_option resource as global. */ 1981 if (sh->config.dv_flow_en == 2) 1982 flow_dev_geneve_tlv_option_resource_release(sh); 1983 else 1984 #endif 1985 MLX5_ASSERT(sh->geneve_tlv_option_resource == NULL); 1986 pthread_mutex_destroy(&sh->txpp.mutex); 1987 mlx5_lwm_unset(sh); 1988 mlx5_free(sh); 1989 return; 1990 exit: 1991 pthread_mutex_unlock(&mlx5_dev_ctx_list_mutex); 1992 } 1993 1994 /** 1995 * Destroy table hash list. 1996 * 1997 * @param[in] priv 1998 * Pointer to the private device data structure. 1999 */ 2000 void 2001 mlx5_free_table_hash_list(struct mlx5_priv *priv) 2002 { 2003 struct mlx5_dev_ctx_shared *sh = priv->sh; 2004 struct mlx5_hlist **tbls = (priv->sh->config.dv_flow_en == 2) ? 2005 &sh->groups : &sh->flow_tbls; 2006 if (*tbls == NULL) 2007 return; 2008 mlx5_hlist_destroy(*tbls); 2009 *tbls = NULL; 2010 } 2011 2012 #ifdef HAVE_MLX5_HWS_SUPPORT 2013 /** 2014 * Allocate HW steering group hash list. 2015 * 2016 * @param[in] priv 2017 * Pointer to the private device data structure. 2018 */ 2019 static int 2020 mlx5_alloc_hw_group_hash_list(struct mlx5_priv *priv) 2021 { 2022 int err = 0; 2023 struct mlx5_dev_ctx_shared *sh = priv->sh; 2024 char s[MLX5_NAME_SIZE]; 2025 2026 MLX5_ASSERT(sh); 2027 snprintf(s, sizeof(s), "%s_flow_groups", priv->sh->ibdev_name); 2028 sh->groups = mlx5_hlist_create 2029 (s, MLX5_FLOW_TABLE_HLIST_ARRAY_SIZE, 2030 false, true, sh, 2031 flow_hw_grp_create_cb, 2032 flow_hw_grp_match_cb, 2033 flow_hw_grp_remove_cb, 2034 flow_hw_grp_clone_cb, 2035 flow_hw_grp_clone_free_cb); 2036 if (!sh->groups) { 2037 DRV_LOG(ERR, "flow groups with hash creation failed."); 2038 err = ENOMEM; 2039 } 2040 return err; 2041 } 2042 #endif 2043 2044 2045 /** 2046 * Initialize flow table hash list and create the root tables entry 2047 * for each domain. 2048 * 2049 * @param[in] priv 2050 * Pointer to the private device data structure. 2051 * 2052 * @return 2053 * Zero on success, positive error code otherwise. 2054 */ 2055 int 2056 mlx5_alloc_table_hash_list(struct mlx5_priv *priv __rte_unused) 2057 { 2058 int err = 0; 2059 2060 /* Tables are only used in DV and DR modes. */ 2061 #if defined(HAVE_IBV_FLOW_DV_SUPPORT) || !defined(HAVE_INFINIBAND_VERBS_H) 2062 struct mlx5_dev_ctx_shared *sh = priv->sh; 2063 char s[MLX5_NAME_SIZE]; 2064 2065 #ifdef HAVE_MLX5_HWS_SUPPORT 2066 if (priv->sh->config.dv_flow_en == 2) 2067 return mlx5_alloc_hw_group_hash_list(priv); 2068 #endif 2069 MLX5_ASSERT(sh); 2070 snprintf(s, sizeof(s), "%s_flow_table", priv->sh->ibdev_name); 2071 sh->flow_tbls = mlx5_hlist_create(s, MLX5_FLOW_TABLE_HLIST_ARRAY_SIZE, 2072 false, true, sh, 2073 flow_dv_tbl_create_cb, 2074 flow_dv_tbl_match_cb, 2075 flow_dv_tbl_remove_cb, 2076 flow_dv_tbl_clone_cb, 2077 flow_dv_tbl_clone_free_cb); 2078 if (!sh->flow_tbls) { 2079 DRV_LOG(ERR, "flow tables with hash creation failed."); 2080 err = ENOMEM; 2081 return err; 2082 } 2083 #ifndef HAVE_MLX5DV_DR 2084 struct rte_flow_error error; 2085 struct rte_eth_dev *dev = &rte_eth_devices[priv->dev_data->port_id]; 2086 2087 /* 2088 * In case we have not DR support, the zero tables should be created 2089 * because DV expect to see them even if they cannot be created by 2090 * RDMA-CORE. 2091 */ 2092 if (!flow_dv_tbl_resource_get(dev, 0, 0, 0, 0, 2093 NULL, 0, 1, 0, &error) || 2094 !flow_dv_tbl_resource_get(dev, 0, 1, 0, 0, 2095 NULL, 0, 1, 0, &error) || 2096 !flow_dv_tbl_resource_get(dev, 0, 0, 1, 0, 2097 NULL, 0, 1, 0, &error)) { 2098 err = ENOMEM; 2099 goto error; 2100 } 2101 return err; 2102 error: 2103 mlx5_free_table_hash_list(priv); 2104 #endif /* HAVE_MLX5DV_DR */ 2105 #endif 2106 return err; 2107 } 2108 2109 /** 2110 * Retrieve integer value from environment variable. 2111 * 2112 * @param[in] name 2113 * Environment variable name. 2114 * 2115 * @return 2116 * Integer value, 0 if the variable is not set. 2117 */ 2118 int 2119 mlx5_getenv_int(const char *name) 2120 { 2121 const char *val = getenv(name); 2122 2123 if (val == NULL) 2124 return 0; 2125 return atoi(val); 2126 } 2127 2128 /** 2129 * DPDK callback to add udp tunnel port 2130 * 2131 * @param[in] dev 2132 * A pointer to eth_dev 2133 * @param[in] udp_tunnel 2134 * A pointer to udp tunnel 2135 * 2136 * @return 2137 * 0 on valid udp ports and tunnels, -ENOTSUP otherwise. 2138 */ 2139 int 2140 mlx5_udp_tunnel_port_add(struct rte_eth_dev *dev __rte_unused, 2141 struct rte_eth_udp_tunnel *udp_tunnel) 2142 { 2143 MLX5_ASSERT(udp_tunnel != NULL); 2144 if (udp_tunnel->prot_type == RTE_ETH_TUNNEL_TYPE_VXLAN && 2145 udp_tunnel->udp_port == 4789) 2146 return 0; 2147 if (udp_tunnel->prot_type == RTE_ETH_TUNNEL_TYPE_VXLAN_GPE && 2148 udp_tunnel->udp_port == 4790) 2149 return 0; 2150 return -ENOTSUP; 2151 } 2152 2153 /** 2154 * Initialize process private data structure. 2155 * 2156 * @param dev 2157 * Pointer to Ethernet device structure. 2158 * 2159 * @return 2160 * 0 on success, a negative errno value otherwise and rte_errno is set. 2161 */ 2162 int 2163 mlx5_proc_priv_init(struct rte_eth_dev *dev) 2164 { 2165 struct mlx5_priv *priv = dev->data->dev_private; 2166 struct mlx5_proc_priv *ppriv; 2167 size_t ppriv_size; 2168 2169 mlx5_proc_priv_uninit(dev); 2170 /* 2171 * UAR register table follows the process private structure. BlueFlame 2172 * registers for Tx queues are stored in the table. 2173 */ 2174 ppriv_size = sizeof(struct mlx5_proc_priv) + 2175 priv->txqs_n * sizeof(struct mlx5_uar_data); 2176 ppriv = mlx5_malloc(MLX5_MEM_RTE | MLX5_MEM_ZERO, ppriv_size, 2177 RTE_CACHE_LINE_SIZE, dev->device->numa_node); 2178 if (!ppriv) { 2179 rte_errno = ENOMEM; 2180 return -rte_errno; 2181 } 2182 ppriv->uar_table_sz = priv->txqs_n; 2183 dev->process_private = ppriv; 2184 if (rte_eal_process_type() == RTE_PROC_PRIMARY) 2185 priv->sh->pppriv = ppriv; 2186 return 0; 2187 } 2188 2189 /** 2190 * Un-initialize process private data structure. 2191 * 2192 * @param dev 2193 * Pointer to Ethernet device structure. 2194 */ 2195 void 2196 mlx5_proc_priv_uninit(struct rte_eth_dev *dev) 2197 { 2198 struct mlx5_proc_priv *ppriv = dev->process_private; 2199 2200 if (!ppriv) 2201 return; 2202 if (ppriv->hca_bar) 2203 mlx5_txpp_unmap_hca_bar(dev); 2204 mlx5_free(dev->process_private); 2205 dev->process_private = NULL; 2206 } 2207 2208 /** 2209 * DPDK callback to close the device. 2210 * 2211 * Destroy all queues and objects, free memory. 2212 * 2213 * @param dev 2214 * Pointer to Ethernet device structure. 2215 */ 2216 int 2217 mlx5_dev_close(struct rte_eth_dev *dev) 2218 { 2219 struct mlx5_priv *priv = dev->data->dev_private; 2220 unsigned int i; 2221 int ret; 2222 2223 if (rte_eal_process_type() == RTE_PROC_SECONDARY) { 2224 /* Check if process_private released. */ 2225 if (!dev->process_private) 2226 return 0; 2227 mlx5_tx_uar_uninit_secondary(dev); 2228 mlx5_proc_priv_uninit(dev); 2229 rte_eth_dev_release_port(dev); 2230 return 0; 2231 } 2232 if (!priv->sh) 2233 return 0; 2234 if (priv->shared_refcnt) { 2235 DRV_LOG(ERR, "port %u is shared host in use (%u)", 2236 dev->data->port_id, priv->shared_refcnt); 2237 rte_errno = EBUSY; 2238 return -EBUSY; 2239 } 2240 DRV_LOG(DEBUG, "port %u closing device \"%s\"", 2241 dev->data->port_id, 2242 ((priv->sh->cdev->ctx != NULL) ? 2243 mlx5_os_get_ctx_device_name(priv->sh->cdev->ctx) : "")); 2244 /* 2245 * If default mreg copy action is removed at the stop stage, 2246 * the search will return none and nothing will be done anymore. 2247 */ 2248 if (priv->sh->config.dv_flow_en != 2) 2249 mlx5_flow_stop_default(dev); 2250 mlx5_traffic_disable(dev); 2251 /* 2252 * If all the flows are already flushed in the device stop stage, 2253 * then this will return directly without any action. 2254 */ 2255 mlx5_flow_list_flush(dev, MLX5_FLOW_TYPE_GEN, true); 2256 mlx5_action_handle_flush(dev); 2257 mlx5_flow_meter_flush(dev, NULL); 2258 /* Prevent crashes when queues are still in use. */ 2259 dev->rx_pkt_burst = rte_eth_pkt_burst_dummy; 2260 dev->tx_pkt_burst = rte_eth_pkt_burst_dummy; 2261 rte_wmb(); 2262 /* Disable datapath on secondary process. */ 2263 mlx5_mp_os_req_stop_rxtx(dev); 2264 /* Free the eCPRI flex parser resource. */ 2265 mlx5_flex_parser_ecpri_release(dev); 2266 mlx5_flex_item_port_cleanup(dev); 2267 mlx5_indirect_list_handles_release(dev); 2268 #ifdef HAVE_MLX5_HWS_SUPPORT 2269 flow_hw_destroy_vport_action(dev); 2270 flow_hw_resource_release(dev); 2271 flow_hw_clear_port_info(dev); 2272 #endif 2273 if (priv->rxq_privs != NULL) { 2274 /* XXX race condition if mlx5_rx_burst() is still running. */ 2275 rte_delay_us_sleep(1000); 2276 for (i = 0; (i != priv->rxqs_n); ++i) 2277 mlx5_rxq_release(dev, i); 2278 priv->rxqs_n = 0; 2279 mlx5_free(priv->rxq_privs); 2280 priv->rxq_privs = NULL; 2281 } 2282 if (priv->txqs != NULL) { 2283 /* XXX race condition if mlx5_tx_burst() is still running. */ 2284 rte_delay_us_sleep(1000); 2285 for (i = 0; (i != priv->txqs_n); ++i) 2286 mlx5_txq_release(dev, i); 2287 priv->txqs_n = 0; 2288 priv->txqs = NULL; 2289 } 2290 mlx5_proc_priv_uninit(dev); 2291 if (priv->q_counters) { 2292 mlx5_devx_cmd_destroy(priv->q_counters); 2293 priv->q_counters = NULL; 2294 } 2295 if (priv->drop_queue.hrxq) 2296 mlx5_drop_action_destroy(dev); 2297 if (priv->mreg_cp_tbl) 2298 mlx5_hlist_destroy(priv->mreg_cp_tbl); 2299 mlx5_mprq_free_mp(dev); 2300 mlx5_os_free_shared_dr(priv); 2301 if (priv->rss_conf.rss_key != NULL) 2302 mlx5_free(priv->rss_conf.rss_key); 2303 if (priv->reta_idx != NULL) 2304 mlx5_free(priv->reta_idx); 2305 if (priv->sh->dev_cap.vf) 2306 mlx5_os_mac_addr_flush(dev); 2307 if (priv->nl_socket_route >= 0) 2308 close(priv->nl_socket_route); 2309 if (priv->nl_socket_rdma >= 0) 2310 close(priv->nl_socket_rdma); 2311 if (priv->vmwa_context) 2312 mlx5_vlan_vmwa_exit(priv->vmwa_context); 2313 ret = mlx5_hrxq_verify(dev); 2314 if (ret) 2315 DRV_LOG(WARNING, "port %u some hash Rx queue still remain", 2316 dev->data->port_id); 2317 ret = mlx5_ind_table_obj_verify(dev); 2318 if (ret) 2319 DRV_LOG(WARNING, "port %u some indirection table still remain", 2320 dev->data->port_id); 2321 ret = mlx5_rxq_obj_verify(dev); 2322 if (ret) 2323 DRV_LOG(WARNING, "port %u some Rx queue objects still remain", 2324 dev->data->port_id); 2325 ret = mlx5_ext_rxq_verify(dev); 2326 if (ret) 2327 DRV_LOG(WARNING, "Port %u some external RxQ still remain.", 2328 dev->data->port_id); 2329 ret = mlx5_rxq_verify(dev); 2330 if (ret) 2331 DRV_LOG(WARNING, "port %u some Rx queues still remain", 2332 dev->data->port_id); 2333 ret = mlx5_txq_obj_verify(dev); 2334 if (ret) 2335 DRV_LOG(WARNING, "port %u some Verbs Tx queue still remain", 2336 dev->data->port_id); 2337 ret = mlx5_txq_verify(dev); 2338 if (ret) 2339 DRV_LOG(WARNING, "port %u some Tx queues still remain", 2340 dev->data->port_id); 2341 ret = mlx5_flow_verify(dev); 2342 if (ret) 2343 DRV_LOG(WARNING, "port %u some flows still remain", 2344 dev->data->port_id); 2345 if (priv->hrxqs) 2346 mlx5_list_destroy(priv->hrxqs); 2347 mlx5_free(priv->ext_rxqs); 2348 priv->sh->port[priv->dev_port - 1].nl_ih_port_id = RTE_MAX_ETHPORTS; 2349 /* 2350 * The interrupt handler port id must be reset before priv is reset 2351 * since 'mlx5_dev_interrupt_nl_cb' uses priv. 2352 */ 2353 rte_io_wmb(); 2354 /* 2355 * Free the shared context in last turn, because the cleanup 2356 * routines above may use some shared fields, like 2357 * mlx5_os_mac_addr_flush() uses ibdev_path for retrieving 2358 * ifindex if Netlink fails. 2359 */ 2360 mlx5_free_shared_dev_ctx(priv->sh); 2361 if (priv->domain_id != RTE_ETH_DEV_SWITCH_DOMAIN_ID_INVALID) { 2362 unsigned int c = 0; 2363 uint16_t port_id; 2364 2365 MLX5_ETH_FOREACH_DEV(port_id, dev->device) { 2366 struct mlx5_priv *opriv = 2367 rte_eth_devices[port_id].data->dev_private; 2368 2369 if (!opriv || 2370 opriv->domain_id != priv->domain_id || 2371 &rte_eth_devices[port_id] == dev) 2372 continue; 2373 ++c; 2374 break; 2375 } 2376 if (!c) 2377 claim_zero(rte_eth_switch_domain_free(priv->domain_id)); 2378 } 2379 memset(priv, 0, sizeof(*priv)); 2380 priv->domain_id = RTE_ETH_DEV_SWITCH_DOMAIN_ID_INVALID; 2381 /* 2382 * Reset mac_addrs to NULL such that it is not freed as part of 2383 * rte_eth_dev_release_port(). mac_addrs is part of dev_private so 2384 * it is freed when dev_private is freed. 2385 */ 2386 dev->data->mac_addrs = NULL; 2387 return 0; 2388 } 2389 2390 const struct eth_dev_ops mlx5_dev_ops = { 2391 .dev_configure = mlx5_dev_configure, 2392 .dev_start = mlx5_dev_start, 2393 .dev_stop = mlx5_dev_stop, 2394 .dev_set_link_down = mlx5_set_link_down, 2395 .dev_set_link_up = mlx5_set_link_up, 2396 .dev_close = mlx5_dev_close, 2397 .promiscuous_enable = mlx5_promiscuous_enable, 2398 .promiscuous_disable = mlx5_promiscuous_disable, 2399 .allmulticast_enable = mlx5_allmulticast_enable, 2400 .allmulticast_disable = mlx5_allmulticast_disable, 2401 .link_update = mlx5_link_update, 2402 .stats_get = mlx5_stats_get, 2403 .stats_reset = mlx5_stats_reset, 2404 .xstats_get = mlx5_xstats_get, 2405 .xstats_reset = mlx5_xstats_reset, 2406 .xstats_get_names = mlx5_xstats_get_names, 2407 .fw_version_get = mlx5_fw_version_get, 2408 .dev_infos_get = mlx5_dev_infos_get, 2409 .representor_info_get = mlx5_representor_info_get, 2410 .read_clock = mlx5_txpp_read_clock, 2411 .dev_supported_ptypes_get = mlx5_dev_supported_ptypes_get, 2412 .vlan_filter_set = mlx5_vlan_filter_set, 2413 .rx_queue_setup = mlx5_rx_queue_setup, 2414 .rx_queue_avail_thresh_set = mlx5_rx_queue_lwm_set, 2415 .rx_queue_avail_thresh_query = mlx5_rx_queue_lwm_query, 2416 .rx_hairpin_queue_setup = mlx5_rx_hairpin_queue_setup, 2417 .tx_queue_setup = mlx5_tx_queue_setup, 2418 .tx_hairpin_queue_setup = mlx5_tx_hairpin_queue_setup, 2419 .rx_queue_release = mlx5_rx_queue_release, 2420 .tx_queue_release = mlx5_tx_queue_release, 2421 .rx_queue_start = mlx5_rx_queue_start, 2422 .rx_queue_stop = mlx5_rx_queue_stop, 2423 .tx_queue_start = mlx5_tx_queue_start, 2424 .tx_queue_stop = mlx5_tx_queue_stop, 2425 .flow_ctrl_get = mlx5_dev_get_flow_ctrl, 2426 .flow_ctrl_set = mlx5_dev_set_flow_ctrl, 2427 .mac_addr_remove = mlx5_mac_addr_remove, 2428 .mac_addr_add = mlx5_mac_addr_add, 2429 .mac_addr_set = mlx5_mac_addr_set, 2430 .set_mc_addr_list = mlx5_set_mc_addr_list, 2431 .mtu_set = mlx5_dev_set_mtu, 2432 .vlan_strip_queue_set = mlx5_vlan_strip_queue_set, 2433 .vlan_offload_set = mlx5_vlan_offload_set, 2434 .reta_update = mlx5_dev_rss_reta_update, 2435 .reta_query = mlx5_dev_rss_reta_query, 2436 .rss_hash_update = mlx5_rss_hash_update, 2437 .rss_hash_conf_get = mlx5_rss_hash_conf_get, 2438 .flow_ops_get = mlx5_flow_ops_get, 2439 .rxq_info_get = mlx5_rxq_info_get, 2440 .txq_info_get = mlx5_txq_info_get, 2441 .rx_burst_mode_get = mlx5_rx_burst_mode_get, 2442 .tx_burst_mode_get = mlx5_tx_burst_mode_get, 2443 .rx_queue_intr_enable = mlx5_rx_intr_enable, 2444 .rx_queue_intr_disable = mlx5_rx_intr_disable, 2445 .is_removed = mlx5_is_removed, 2446 .udp_tunnel_port_add = mlx5_udp_tunnel_port_add, 2447 .get_module_info = mlx5_get_module_info, 2448 .get_module_eeprom = mlx5_get_module_eeprom, 2449 .hairpin_cap_get = mlx5_hairpin_cap_get, 2450 .mtr_ops_get = mlx5_flow_meter_ops_get, 2451 .hairpin_bind = mlx5_hairpin_bind, 2452 .hairpin_unbind = mlx5_hairpin_unbind, 2453 .hairpin_get_peer_ports = mlx5_hairpin_get_peer_ports, 2454 .hairpin_queue_peer_update = mlx5_hairpin_queue_peer_update, 2455 .hairpin_queue_peer_bind = mlx5_hairpin_queue_peer_bind, 2456 .hairpin_queue_peer_unbind = mlx5_hairpin_queue_peer_unbind, 2457 .get_monitor_addr = mlx5_get_monitor_addr, 2458 .count_aggr_ports = mlx5_count_aggr_ports, 2459 .map_aggr_tx_affinity = mlx5_map_aggr_tx_affinity, 2460 .rx_metadata_negotiate = mlx5_flow_rx_metadata_negotiate, 2461 }; 2462 2463 /* Available operations from secondary process. */ 2464 const struct eth_dev_ops mlx5_dev_sec_ops = { 2465 .stats_get = mlx5_stats_get, 2466 .stats_reset = mlx5_stats_reset, 2467 .xstats_get = mlx5_xstats_get, 2468 .xstats_reset = mlx5_xstats_reset, 2469 .xstats_get_names = mlx5_xstats_get_names, 2470 .fw_version_get = mlx5_fw_version_get, 2471 .dev_infos_get = mlx5_dev_infos_get, 2472 .representor_info_get = mlx5_representor_info_get, 2473 .read_clock = mlx5_txpp_read_clock, 2474 .rx_queue_start = mlx5_rx_queue_start, 2475 .rx_queue_stop = mlx5_rx_queue_stop, 2476 .tx_queue_start = mlx5_tx_queue_start, 2477 .tx_queue_stop = mlx5_tx_queue_stop, 2478 .rxq_info_get = mlx5_rxq_info_get, 2479 .txq_info_get = mlx5_txq_info_get, 2480 .rx_burst_mode_get = mlx5_rx_burst_mode_get, 2481 .tx_burst_mode_get = mlx5_tx_burst_mode_get, 2482 .get_module_info = mlx5_get_module_info, 2483 .get_module_eeprom = mlx5_get_module_eeprom, 2484 .count_aggr_ports = mlx5_count_aggr_ports, 2485 .map_aggr_tx_affinity = mlx5_map_aggr_tx_affinity, 2486 .rx_metadata_negotiate = mlx5_flow_rx_metadata_negotiate, 2487 }; 2488 2489 /* Available operations in flow isolated mode. */ 2490 const struct eth_dev_ops mlx5_dev_ops_isolate = { 2491 .dev_configure = mlx5_dev_configure, 2492 .dev_start = mlx5_dev_start, 2493 .dev_stop = mlx5_dev_stop, 2494 .dev_set_link_down = mlx5_set_link_down, 2495 .dev_set_link_up = mlx5_set_link_up, 2496 .dev_close = mlx5_dev_close, 2497 .promiscuous_enable = mlx5_promiscuous_enable, 2498 .promiscuous_disable = mlx5_promiscuous_disable, 2499 .allmulticast_enable = mlx5_allmulticast_enable, 2500 .allmulticast_disable = mlx5_allmulticast_disable, 2501 .link_update = mlx5_link_update, 2502 .stats_get = mlx5_stats_get, 2503 .stats_reset = mlx5_stats_reset, 2504 .xstats_get = mlx5_xstats_get, 2505 .xstats_reset = mlx5_xstats_reset, 2506 .xstats_get_names = mlx5_xstats_get_names, 2507 .fw_version_get = mlx5_fw_version_get, 2508 .dev_infos_get = mlx5_dev_infos_get, 2509 .representor_info_get = mlx5_representor_info_get, 2510 .read_clock = mlx5_txpp_read_clock, 2511 .dev_supported_ptypes_get = mlx5_dev_supported_ptypes_get, 2512 .vlan_filter_set = mlx5_vlan_filter_set, 2513 .rx_queue_setup = mlx5_rx_queue_setup, 2514 .rx_hairpin_queue_setup = mlx5_rx_hairpin_queue_setup, 2515 .tx_queue_setup = mlx5_tx_queue_setup, 2516 .tx_hairpin_queue_setup = mlx5_tx_hairpin_queue_setup, 2517 .rx_queue_release = mlx5_rx_queue_release, 2518 .tx_queue_release = mlx5_tx_queue_release, 2519 .rx_queue_start = mlx5_rx_queue_start, 2520 .rx_queue_stop = mlx5_rx_queue_stop, 2521 .tx_queue_start = mlx5_tx_queue_start, 2522 .tx_queue_stop = mlx5_tx_queue_stop, 2523 .flow_ctrl_get = mlx5_dev_get_flow_ctrl, 2524 .flow_ctrl_set = mlx5_dev_set_flow_ctrl, 2525 .mac_addr_remove = mlx5_mac_addr_remove, 2526 .mac_addr_add = mlx5_mac_addr_add, 2527 .mac_addr_set = mlx5_mac_addr_set, 2528 .set_mc_addr_list = mlx5_set_mc_addr_list, 2529 .mtu_set = mlx5_dev_set_mtu, 2530 .vlan_strip_queue_set = mlx5_vlan_strip_queue_set, 2531 .vlan_offload_set = mlx5_vlan_offload_set, 2532 .flow_ops_get = mlx5_flow_ops_get, 2533 .rxq_info_get = mlx5_rxq_info_get, 2534 .txq_info_get = mlx5_txq_info_get, 2535 .rx_burst_mode_get = mlx5_rx_burst_mode_get, 2536 .tx_burst_mode_get = mlx5_tx_burst_mode_get, 2537 .rx_queue_intr_enable = mlx5_rx_intr_enable, 2538 .rx_queue_intr_disable = mlx5_rx_intr_disable, 2539 .is_removed = mlx5_is_removed, 2540 .get_module_info = mlx5_get_module_info, 2541 .get_module_eeprom = mlx5_get_module_eeprom, 2542 .hairpin_cap_get = mlx5_hairpin_cap_get, 2543 .mtr_ops_get = mlx5_flow_meter_ops_get, 2544 .hairpin_bind = mlx5_hairpin_bind, 2545 .hairpin_unbind = mlx5_hairpin_unbind, 2546 .hairpin_get_peer_ports = mlx5_hairpin_get_peer_ports, 2547 .hairpin_queue_peer_update = mlx5_hairpin_queue_peer_update, 2548 .hairpin_queue_peer_bind = mlx5_hairpin_queue_peer_bind, 2549 .hairpin_queue_peer_unbind = mlx5_hairpin_queue_peer_unbind, 2550 .get_monitor_addr = mlx5_get_monitor_addr, 2551 .count_aggr_ports = mlx5_count_aggr_ports, 2552 .map_aggr_tx_affinity = mlx5_map_aggr_tx_affinity, 2553 }; 2554 2555 /** 2556 * Verify and store value for device argument. 2557 * 2558 * @param[in] key 2559 * Key argument to verify. 2560 * @param[in] val 2561 * Value associated with key. 2562 * @param opaque 2563 * User data. 2564 * 2565 * @return 2566 * 0 on success, a negative errno value otherwise and rte_errno is set. 2567 */ 2568 static int 2569 mlx5_port_args_check_handler(const char *key, const char *val, void *opaque) 2570 { 2571 struct mlx5_port_config *config = opaque; 2572 signed long tmp; 2573 2574 /* No-op, port representors are processed in mlx5_dev_spawn(). */ 2575 if (!strcmp(MLX5_REPRESENTOR, key)) 2576 return 0; 2577 errno = 0; 2578 tmp = strtol(val, NULL, 0); 2579 if (errno) { 2580 rte_errno = errno; 2581 DRV_LOG(WARNING, "%s: \"%s\" is not a valid integer", key, val); 2582 return -rte_errno; 2583 } 2584 if (tmp < 0) { 2585 /* Negative values are acceptable for some keys only. */ 2586 rte_errno = EINVAL; 2587 DRV_LOG(WARNING, "%s: invalid negative value \"%s\"", key, val); 2588 return -rte_errno; 2589 } 2590 if (strcmp(MLX5_RXQ_CQE_COMP_EN, key) == 0) { 2591 if ((tmp & ~MLX5_RXQ_ENH_CQE_COMP_MASK) > 2592 MLX5_CQE_RESP_FORMAT_L34H_STRIDX) { 2593 DRV_LOG(ERR, "invalid CQE compression " 2594 "format parameter"); 2595 rte_errno = EINVAL; 2596 return -rte_errno; 2597 } 2598 config->cqe_comp = !!tmp; 2599 config->cqe_comp_fmt = tmp & ~MLX5_RXQ_ENH_CQE_COMP_MASK; 2600 config->enh_cqe_comp = !!(tmp & MLX5_RXQ_ENH_CQE_COMP_MASK); 2601 } else if (strcmp(MLX5_RXQ_PKT_PAD_EN, key) == 0) { 2602 config->hw_padding = !!tmp; 2603 } else if (strcmp(MLX5_RX_MPRQ_EN, key) == 0) { 2604 config->mprq.enabled = !!tmp; 2605 } else if (strcmp(MLX5_RX_MPRQ_LOG_STRIDE_NUM, key) == 0) { 2606 config->mprq.log_stride_num = tmp; 2607 } else if (strcmp(MLX5_RX_MPRQ_LOG_STRIDE_SIZE, key) == 0) { 2608 config->mprq.log_stride_size = tmp; 2609 } else if (strcmp(MLX5_RX_MPRQ_MAX_MEMCPY_LEN, key) == 0) { 2610 config->mprq.max_memcpy_len = tmp; 2611 } else if (strcmp(MLX5_RXQS_MIN_MPRQ, key) == 0) { 2612 config->mprq.min_rxqs_num = tmp; 2613 } else if (strcmp(MLX5_TXQ_INLINE, key) == 0) { 2614 DRV_LOG(WARNING, "%s: deprecated parameter," 2615 " converted to txq_inline_max", key); 2616 config->txq_inline_max = tmp; 2617 } else if (strcmp(MLX5_TXQ_INLINE_MAX, key) == 0) { 2618 config->txq_inline_max = tmp; 2619 } else if (strcmp(MLX5_TXQ_INLINE_MIN, key) == 0) { 2620 config->txq_inline_min = tmp; 2621 } else if (strcmp(MLX5_TXQ_INLINE_MPW, key) == 0) { 2622 config->txq_inline_mpw = tmp; 2623 } else if (strcmp(MLX5_TXQS_MIN_INLINE, key) == 0) { 2624 config->txqs_inline = tmp; 2625 } else if (strcmp(MLX5_TXQS_MAX_VEC, key) == 0) { 2626 DRV_LOG(WARNING, "%s: deprecated parameter, ignored", key); 2627 } else if (strcmp(MLX5_TXQ_MPW_EN, key) == 0) { 2628 config->mps = !!tmp; 2629 } else if (strcmp(MLX5_TXQ_MPW_HDR_DSEG_EN, key) == 0) { 2630 DRV_LOG(WARNING, "%s: deprecated parameter, ignored", key); 2631 } else if (strcmp(MLX5_TXQ_MAX_INLINE_LEN, key) == 0) { 2632 DRV_LOG(WARNING, "%s: deprecated parameter," 2633 " converted to txq_inline_mpw", key); 2634 config->txq_inline_mpw = tmp; 2635 } else if (strcmp(MLX5_TX_VEC_EN, key) == 0) { 2636 DRV_LOG(WARNING, "%s: deprecated parameter, ignored", key); 2637 } else if (strcmp(MLX5_RX_VEC_EN, key) == 0) { 2638 config->rx_vec_en = !!tmp; 2639 } else if (strcmp(MLX5_MAX_DUMP_FILES_NUM, key) == 0) { 2640 config->max_dump_files_num = tmp; 2641 } else if (strcmp(MLX5_LRO_TIMEOUT_USEC, key) == 0) { 2642 config->lro_timeout = tmp; 2643 } else if (strcmp(MLX5_HP_BUF_SIZE, key) == 0) { 2644 config->log_hp_size = tmp; 2645 } else if (strcmp(MLX5_DELAY_DROP, key) == 0) { 2646 config->std_delay_drop = !!(tmp & MLX5_DELAY_DROP_STANDARD); 2647 config->hp_delay_drop = !!(tmp & MLX5_DELAY_DROP_HAIRPIN); 2648 } 2649 return 0; 2650 } 2651 2652 /** 2653 * Parse user port parameters and adjust them according to device capabilities. 2654 * 2655 * @param priv 2656 * Pointer to shared device context. 2657 * @param mkvlist 2658 * Pointer to mlx5 kvargs control, can be NULL if there is no devargs. 2659 * @param config 2660 * Pointer to port configuration structure. 2661 * 2662 * @return 2663 * 0 on success, a negative errno value otherwise and rte_errno is set. 2664 */ 2665 int 2666 mlx5_port_args_config(struct mlx5_priv *priv, struct mlx5_kvargs_ctrl *mkvlist, 2667 struct mlx5_port_config *config) 2668 { 2669 struct mlx5_hca_attr *hca_attr = &priv->sh->cdev->config.hca_attr; 2670 struct mlx5_dev_cap *dev_cap = &priv->sh->dev_cap; 2671 bool devx = priv->sh->cdev->config.devx; 2672 const char **params = (const char *[]){ 2673 MLX5_RXQ_CQE_COMP_EN, 2674 MLX5_RXQ_PKT_PAD_EN, 2675 MLX5_RX_MPRQ_EN, 2676 MLX5_RX_MPRQ_LOG_STRIDE_NUM, 2677 MLX5_RX_MPRQ_LOG_STRIDE_SIZE, 2678 MLX5_RX_MPRQ_MAX_MEMCPY_LEN, 2679 MLX5_RXQS_MIN_MPRQ, 2680 MLX5_TXQ_INLINE, 2681 MLX5_TXQ_INLINE_MIN, 2682 MLX5_TXQ_INLINE_MAX, 2683 MLX5_TXQ_INLINE_MPW, 2684 MLX5_TXQS_MIN_INLINE, 2685 MLX5_TXQS_MAX_VEC, 2686 MLX5_TXQ_MPW_EN, 2687 MLX5_TXQ_MPW_HDR_DSEG_EN, 2688 MLX5_TXQ_MAX_INLINE_LEN, 2689 MLX5_TX_VEC_EN, 2690 MLX5_RX_VEC_EN, 2691 MLX5_REPRESENTOR, 2692 MLX5_MAX_DUMP_FILES_NUM, 2693 MLX5_LRO_TIMEOUT_USEC, 2694 MLX5_HP_BUF_SIZE, 2695 MLX5_DELAY_DROP, 2696 NULL, 2697 }; 2698 int ret = 0; 2699 2700 /* Default configuration. */ 2701 memset(config, 0, sizeof(*config)); 2702 config->mps = MLX5_ARG_UNSET; 2703 config->cqe_comp = 1; 2704 config->rx_vec_en = 1; 2705 config->txq_inline_max = MLX5_ARG_UNSET; 2706 config->txq_inline_min = MLX5_ARG_UNSET; 2707 config->txq_inline_mpw = MLX5_ARG_UNSET; 2708 config->txqs_inline = MLX5_ARG_UNSET; 2709 config->mprq.max_memcpy_len = MLX5_MPRQ_MEMCPY_DEFAULT_LEN; 2710 config->mprq.min_rxqs_num = MLX5_MPRQ_MIN_RXQS; 2711 config->mprq.log_stride_num = MLX5_MPRQ_DEFAULT_LOG_STRIDE_NUM; 2712 config->mprq.log_stride_size = MLX5_ARG_UNSET; 2713 config->log_hp_size = MLX5_ARG_UNSET; 2714 config->std_delay_drop = 0; 2715 config->hp_delay_drop = 0; 2716 if (mkvlist != NULL) { 2717 /* Process parameters. */ 2718 ret = mlx5_kvargs_process(mkvlist, params, 2719 mlx5_port_args_check_handler, config); 2720 if (ret) { 2721 DRV_LOG(ERR, "Failed to process port arguments: %s", 2722 strerror(rte_errno)); 2723 return -rte_errno; 2724 } 2725 } 2726 /* Adjust parameters according to device capabilities. */ 2727 if (config->hw_padding && !dev_cap->hw_padding) { 2728 DRV_LOG(DEBUG, "Rx end alignment padding isn't supported."); 2729 config->hw_padding = 0; 2730 } else if (config->hw_padding) { 2731 DRV_LOG(DEBUG, "Rx end alignment padding is enabled."); 2732 } 2733 /* 2734 * MPW is disabled by default, while the Enhanced MPW is enabled 2735 * by default. 2736 */ 2737 if (config->mps == MLX5_ARG_UNSET) 2738 config->mps = (dev_cap->mps == MLX5_MPW_ENHANCED) ? 2739 MLX5_MPW_ENHANCED : MLX5_MPW_DISABLED; 2740 else 2741 config->mps = config->mps ? dev_cap->mps : MLX5_MPW_DISABLED; 2742 DRV_LOG(INFO, "%sMPS is %s", 2743 config->mps == MLX5_MPW_ENHANCED ? "enhanced " : 2744 config->mps == MLX5_MPW ? "legacy " : "", 2745 config->mps != MLX5_MPW_DISABLED ? "enabled" : "disabled"); 2746 if (priv->sh->config.lro_allowed) { 2747 /* 2748 * If LRO timeout is not configured by application, 2749 * use the minimal supported value. 2750 */ 2751 if (!config->lro_timeout) 2752 config->lro_timeout = 2753 hca_attr->lro_timer_supported_periods[0]; 2754 DRV_LOG(DEBUG, "LRO session timeout set to %d usec.", 2755 config->lro_timeout); 2756 } 2757 if (config->cqe_comp && !dev_cap->cqe_comp) { 2758 DRV_LOG(WARNING, "Rx CQE 128B compression is not supported."); 2759 config->cqe_comp = 0; 2760 } 2761 if (config->cqe_comp_fmt == MLX5_CQE_RESP_FORMAT_FTAG_STRIDX && 2762 (!devx || !hca_attr->mini_cqe_resp_flow_tag)) { 2763 DRV_LOG(WARNING, 2764 "Flow Tag CQE compression format isn't supported."); 2765 config->cqe_comp = 0; 2766 } 2767 if (config->cqe_comp_fmt == MLX5_CQE_RESP_FORMAT_L34H_STRIDX && 2768 (!devx || !hca_attr->mini_cqe_resp_l3_l4_tag)) { 2769 DRV_LOG(WARNING, 2770 "L3/L4 Header CQE compression format isn't supported."); 2771 config->cqe_comp = 0; 2772 } 2773 if (config->enh_cqe_comp && !hca_attr->enhanced_cqe_compression) { 2774 DRV_LOG(WARNING, 2775 "Enhanced CQE compression isn't supported."); 2776 config->enh_cqe_comp = 0; 2777 } 2778 DRV_LOG(DEBUG, "%sRx CQE compression is %ssupported.", 2779 config->enh_cqe_comp ? "Enhanced " : "", 2780 config->cqe_comp ? "" : "not "); 2781 if ((config->std_delay_drop || config->hp_delay_drop) && 2782 !dev_cap->rq_delay_drop_en) { 2783 config->std_delay_drop = 0; 2784 config->hp_delay_drop = 0; 2785 DRV_LOG(WARNING, "dev_port-%u: Rxq delay drop isn't supported.", 2786 priv->dev_port); 2787 } 2788 if (config->mprq.enabled && !priv->sh->dev_cap.mprq.enabled) { 2789 DRV_LOG(WARNING, "Multi-Packet RQ isn't supported."); 2790 config->mprq.enabled = 0; 2791 } 2792 if (config->max_dump_files_num == 0) 2793 config->max_dump_files_num = 128; 2794 /* Detect minimal data bytes to inline. */ 2795 mlx5_set_min_inline(priv); 2796 DRV_LOG(DEBUG, "VLAN insertion in WQE is %ssupported.", 2797 config->hw_vlan_insert ? "" : "not "); 2798 DRV_LOG(DEBUG, "\"rxq_pkt_pad_en\" is %u.", config->hw_padding); 2799 DRV_LOG(DEBUG, "\"rxq_cqe_comp_en\" is %u.", config->cqe_comp); 2800 DRV_LOG(DEBUG, "\"cqe_comp_fmt\" is %u.", config->cqe_comp_fmt); 2801 DRV_LOG(DEBUG, "\"enh_cqe_comp\" is %u.", config->enh_cqe_comp); 2802 DRV_LOG(DEBUG, "\"rx_vec_en\" is %u.", config->rx_vec_en); 2803 DRV_LOG(DEBUG, "Standard \"delay_drop\" is %u.", 2804 config->std_delay_drop); 2805 DRV_LOG(DEBUG, "Hairpin \"delay_drop\" is %u.", config->hp_delay_drop); 2806 DRV_LOG(DEBUG, "\"max_dump_files_num\" is %u.", 2807 config->max_dump_files_num); 2808 DRV_LOG(DEBUG, "\"log_hp_size\" is %u.", config->log_hp_size); 2809 DRV_LOG(DEBUG, "\"mprq_en\" is %u.", config->mprq.enabled); 2810 DRV_LOG(DEBUG, "\"mprq_log_stride_num\" is %u.", 2811 config->mprq.log_stride_num); 2812 DRV_LOG(DEBUG, "\"mprq_log_stride_size\" is %u.", 2813 config->mprq.log_stride_size); 2814 DRV_LOG(DEBUG, "\"mprq_max_memcpy_len\" is %u.", 2815 config->mprq.max_memcpy_len); 2816 DRV_LOG(DEBUG, "\"rxqs_min_mprq\" is %u.", config->mprq.min_rxqs_num); 2817 DRV_LOG(DEBUG, "\"lro_timeout_usec\" is %u.", config->lro_timeout); 2818 DRV_LOG(DEBUG, "\"txq_mpw_en\" is %d.", config->mps); 2819 DRV_LOG(DEBUG, "\"txqs_min_inline\" is %d.", config->txqs_inline); 2820 DRV_LOG(DEBUG, "\"txq_inline_min\" is %d.", config->txq_inline_min); 2821 DRV_LOG(DEBUG, "\"txq_inline_max\" is %d.", config->txq_inline_max); 2822 DRV_LOG(DEBUG, "\"txq_inline_mpw\" is %d.", config->txq_inline_mpw); 2823 return 0; 2824 } 2825 2826 /** 2827 * Print the key for device argument. 2828 * 2829 * It is "dummy" handler whose whole purpose is to enable using 2830 * mlx5_kvargs_process() function which set devargs as used. 2831 * 2832 * @param key 2833 * Key argument. 2834 * @param val 2835 * Value associated with key, unused. 2836 * @param opaque 2837 * Unused, can be NULL. 2838 * 2839 * @return 2840 * 0 on success, function cannot fail. 2841 */ 2842 static int 2843 mlx5_dummy_handler(const char *key, const char *val, void *opaque) 2844 { 2845 DRV_LOG(DEBUG, "\tKey: \"%s\" is set as used.", key); 2846 RTE_SET_USED(opaque); 2847 RTE_SET_USED(val); 2848 return 0; 2849 } 2850 2851 /** 2852 * Set requested devargs as used when device is already spawned. 2853 * 2854 * It is necessary since it is valid to ask probe again for existing device, 2855 * if its devargs don't assign as used, mlx5_kvargs_validate() will fail. 2856 * 2857 * @param name 2858 * Name of the existing device. 2859 * @param port_id 2860 * Port identifier of the device. 2861 * @param mkvlist 2862 * Pointer to mlx5 kvargs control to sign as used. 2863 */ 2864 void 2865 mlx5_port_args_set_used(const char *name, uint16_t port_id, 2866 struct mlx5_kvargs_ctrl *mkvlist) 2867 { 2868 const char **params = (const char *[]){ 2869 MLX5_RXQ_CQE_COMP_EN, 2870 MLX5_RXQ_PKT_PAD_EN, 2871 MLX5_RX_MPRQ_EN, 2872 MLX5_RX_MPRQ_LOG_STRIDE_NUM, 2873 MLX5_RX_MPRQ_LOG_STRIDE_SIZE, 2874 MLX5_RX_MPRQ_MAX_MEMCPY_LEN, 2875 MLX5_RXQS_MIN_MPRQ, 2876 MLX5_TXQ_INLINE, 2877 MLX5_TXQ_INLINE_MIN, 2878 MLX5_TXQ_INLINE_MAX, 2879 MLX5_TXQ_INLINE_MPW, 2880 MLX5_TXQS_MIN_INLINE, 2881 MLX5_TXQS_MAX_VEC, 2882 MLX5_TXQ_MPW_EN, 2883 MLX5_TXQ_MPW_HDR_DSEG_EN, 2884 MLX5_TXQ_MAX_INLINE_LEN, 2885 MLX5_TX_VEC_EN, 2886 MLX5_RX_VEC_EN, 2887 MLX5_REPRESENTOR, 2888 MLX5_MAX_DUMP_FILES_NUM, 2889 MLX5_LRO_TIMEOUT_USEC, 2890 MLX5_HP_BUF_SIZE, 2891 MLX5_DELAY_DROP, 2892 NULL, 2893 }; 2894 2895 /* Secondary process should not handle devargs. */ 2896 if (rte_eal_process_type() != RTE_PROC_PRIMARY) 2897 return; 2898 MLX5_ASSERT(mkvlist != NULL); 2899 DRV_LOG(DEBUG, "Ethernet device \"%s\" for port %u " 2900 "already exists, set devargs as used:", name, port_id); 2901 /* This function cannot fail with this handler. */ 2902 mlx5_kvargs_process(mkvlist, params, mlx5_dummy_handler, NULL); 2903 } 2904 2905 /** 2906 * Check sibling device configurations when probing again. 2907 * 2908 * Sibling devices sharing infiniband device context should have compatible 2909 * configurations. This regards representors and bonding device. 2910 * 2911 * @param cdev 2912 * Pointer to mlx5 device structure. 2913 * @param mkvlist 2914 * Pointer to mlx5 kvargs control, can be NULL if there is no devargs. 2915 * 2916 * @return 2917 * 0 on success, a negative errno value otherwise and rte_errno is set. 2918 */ 2919 int 2920 mlx5_probe_again_args_validate(struct mlx5_common_device *cdev, 2921 struct mlx5_kvargs_ctrl *mkvlist) 2922 { 2923 struct mlx5_dev_ctx_shared *sh = NULL; 2924 struct mlx5_sh_config *config; 2925 int ret; 2926 2927 /* Secondary process should not handle devargs. */ 2928 if (rte_eal_process_type() != RTE_PROC_PRIMARY) 2929 return 0; 2930 pthread_mutex_lock(&mlx5_dev_ctx_list_mutex); 2931 /* Search for IB context by common device pointer. */ 2932 LIST_FOREACH(sh, &mlx5_dev_ctx_list, next) 2933 if (sh->cdev == cdev) 2934 break; 2935 pthread_mutex_unlock(&mlx5_dev_ctx_list_mutex); 2936 /* There is sh for this device -> it isn't probe again. */ 2937 if (sh == NULL) 2938 return 0; 2939 config = mlx5_malloc(MLX5_MEM_ZERO | MLX5_MEM_RTE, 2940 sizeof(struct mlx5_sh_config), 2941 RTE_CACHE_LINE_SIZE, SOCKET_ID_ANY); 2942 if (config == NULL) { 2943 rte_errno = -ENOMEM; 2944 return -rte_errno; 2945 } 2946 /* 2947 * Creates a temporary IB context configure structure according to new 2948 * devargs attached in probing again. 2949 */ 2950 ret = mlx5_shared_dev_ctx_args_config(sh, mkvlist, config); 2951 if (ret) { 2952 DRV_LOG(ERR, "Failed to process device configure: %s", 2953 strerror(rte_errno)); 2954 mlx5_free(config); 2955 return ret; 2956 } 2957 /* 2958 * Checks the match between the temporary structure and the existing 2959 * IB context structure. 2960 */ 2961 if (sh->config.dv_flow_en ^ config->dv_flow_en) { 2962 DRV_LOG(ERR, "\"dv_flow_en\" " 2963 "configuration mismatch for shared %s context.", 2964 sh->ibdev_name); 2965 goto error; 2966 } 2967 if ((sh->config.dv_xmeta_en ^ config->dv_xmeta_en) || 2968 (sh->config.dv_miss_info ^ config->dv_miss_info)) { 2969 DRV_LOG(ERR, "\"dv_xmeta_en\" " 2970 "configuration mismatch for shared %s context.", 2971 sh->ibdev_name); 2972 goto error; 2973 } 2974 if (sh->config.dv_esw_en ^ config->dv_esw_en) { 2975 DRV_LOG(ERR, "\"dv_esw_en\" " 2976 "configuration mismatch for shared %s context.", 2977 sh->ibdev_name); 2978 goto error; 2979 } 2980 if (sh->config.reclaim_mode ^ config->reclaim_mode) { 2981 DRV_LOG(ERR, "\"reclaim_mode\" " 2982 "configuration mismatch for shared %s context.", 2983 sh->ibdev_name); 2984 goto error; 2985 } 2986 if (sh->config.allow_duplicate_pattern ^ 2987 config->allow_duplicate_pattern) { 2988 DRV_LOG(ERR, "\"allow_duplicate_pattern\" " 2989 "configuration mismatch for shared %s context.", 2990 sh->ibdev_name); 2991 goto error; 2992 } 2993 if (sh->config.fdb_def_rule ^ config->fdb_def_rule) { 2994 DRV_LOG(ERR, "\"fdb_def_rule_en\" configuration mismatch for shared %s context.", 2995 sh->ibdev_name); 2996 goto error; 2997 } 2998 if (sh->config.l3_vxlan_en ^ config->l3_vxlan_en) { 2999 DRV_LOG(ERR, "\"l3_vxlan_en\" " 3000 "configuration mismatch for shared %s context.", 3001 sh->ibdev_name); 3002 goto error; 3003 } 3004 if (sh->config.decap_en ^ config->decap_en) { 3005 DRV_LOG(ERR, "\"decap_en\" " 3006 "configuration mismatch for shared %s context.", 3007 sh->ibdev_name); 3008 goto error; 3009 } 3010 if (sh->config.lacp_by_user ^ config->lacp_by_user) { 3011 DRV_LOG(ERR, "\"lacp_by_user\" " 3012 "configuration mismatch for shared %s context.", 3013 sh->ibdev_name); 3014 goto error; 3015 } 3016 if (sh->config.tx_pp ^ config->tx_pp) { 3017 DRV_LOG(ERR, "\"tx_pp\" " 3018 "configuration mismatch for shared %s context.", 3019 sh->ibdev_name); 3020 goto error; 3021 } 3022 if (sh->config.tx_skew ^ config->tx_skew) { 3023 DRV_LOG(ERR, "\"tx_skew\" " 3024 "configuration mismatch for shared %s context.", 3025 sh->ibdev_name); 3026 goto error; 3027 } 3028 mlx5_free(config); 3029 return 0; 3030 error: 3031 mlx5_free(config); 3032 rte_errno = EINVAL; 3033 return -rte_errno; 3034 } 3035 3036 /** 3037 * Configures the minimal amount of data to inline into WQE 3038 * while sending packets. 3039 * 3040 * - the txq_inline_min has the maximal priority, if this 3041 * key is specified in devargs 3042 * - if DevX is enabled the inline mode is queried from the 3043 * device (HCA attributes and NIC vport context if needed). 3044 * - otherwise L2 mode (18 bytes) is assumed for ConnectX-4/4 Lx 3045 * and none (0 bytes) for other NICs 3046 * 3047 * @param priv 3048 * Pointer to the private device data structure. 3049 */ 3050 void 3051 mlx5_set_min_inline(struct mlx5_priv *priv) 3052 { 3053 struct mlx5_hca_attr *hca_attr = &priv->sh->cdev->config.hca_attr; 3054 struct mlx5_port_config *config = &priv->config; 3055 3056 if (config->txq_inline_min != MLX5_ARG_UNSET) { 3057 /* Application defines size of inlined data explicitly. */ 3058 if (priv->pci_dev != NULL) { 3059 switch (priv->pci_dev->id.device_id) { 3060 case PCI_DEVICE_ID_MELLANOX_CONNECTX4: 3061 case PCI_DEVICE_ID_MELLANOX_CONNECTX4VF: 3062 if (config->txq_inline_min < 3063 (int)MLX5_INLINE_HSIZE_L2) { 3064 DRV_LOG(DEBUG, 3065 "txq_inline_mix aligned to minimal ConnectX-4 required value %d", 3066 (int)MLX5_INLINE_HSIZE_L2); 3067 config->txq_inline_min = 3068 MLX5_INLINE_HSIZE_L2; 3069 } 3070 break; 3071 } 3072 } 3073 goto exit; 3074 } 3075 if (hca_attr->eth_net_offloads) { 3076 /* We have DevX enabled, inline mode queried successfully. */ 3077 switch (hca_attr->wqe_inline_mode) { 3078 case MLX5_CAP_INLINE_MODE_L2: 3079 /* outer L2 header must be inlined. */ 3080 config->txq_inline_min = MLX5_INLINE_HSIZE_L2; 3081 goto exit; 3082 case MLX5_CAP_INLINE_MODE_NOT_REQUIRED: 3083 /* No inline data are required by NIC. */ 3084 config->txq_inline_min = MLX5_INLINE_HSIZE_NONE; 3085 config->hw_vlan_insert = 3086 hca_attr->wqe_vlan_insert; 3087 DRV_LOG(DEBUG, "Tx VLAN insertion is supported"); 3088 goto exit; 3089 case MLX5_CAP_INLINE_MODE_VPORT_CONTEXT: 3090 /* inline mode is defined by NIC vport context. */ 3091 if (!hca_attr->eth_virt) 3092 break; 3093 switch (hca_attr->vport_inline_mode) { 3094 case MLX5_INLINE_MODE_NONE: 3095 config->txq_inline_min = 3096 MLX5_INLINE_HSIZE_NONE; 3097 goto exit; 3098 case MLX5_INLINE_MODE_L2: 3099 config->txq_inline_min = 3100 MLX5_INLINE_HSIZE_L2; 3101 goto exit; 3102 case MLX5_INLINE_MODE_IP: 3103 config->txq_inline_min = 3104 MLX5_INLINE_HSIZE_L3; 3105 goto exit; 3106 case MLX5_INLINE_MODE_TCP_UDP: 3107 config->txq_inline_min = 3108 MLX5_INLINE_HSIZE_L4; 3109 goto exit; 3110 case MLX5_INLINE_MODE_INNER_L2: 3111 config->txq_inline_min = 3112 MLX5_INLINE_HSIZE_INNER_L2; 3113 goto exit; 3114 case MLX5_INLINE_MODE_INNER_IP: 3115 config->txq_inline_min = 3116 MLX5_INLINE_HSIZE_INNER_L3; 3117 goto exit; 3118 case MLX5_INLINE_MODE_INNER_TCP_UDP: 3119 config->txq_inline_min = 3120 MLX5_INLINE_HSIZE_INNER_L4; 3121 goto exit; 3122 } 3123 } 3124 } 3125 if (priv->pci_dev == NULL) { 3126 config->txq_inline_min = MLX5_INLINE_HSIZE_NONE; 3127 goto exit; 3128 } 3129 /* 3130 * We get here if we are unable to deduce 3131 * inline data size with DevX. Try PCI ID 3132 * to determine old NICs. 3133 */ 3134 switch (priv->pci_dev->id.device_id) { 3135 case PCI_DEVICE_ID_MELLANOX_CONNECTX4: 3136 case PCI_DEVICE_ID_MELLANOX_CONNECTX4VF: 3137 case PCI_DEVICE_ID_MELLANOX_CONNECTX4LX: 3138 case PCI_DEVICE_ID_MELLANOX_CONNECTX4LXVF: 3139 config->txq_inline_min = MLX5_INLINE_HSIZE_L2; 3140 config->hw_vlan_insert = 0; 3141 break; 3142 case PCI_DEVICE_ID_MELLANOX_CONNECTX5: 3143 case PCI_DEVICE_ID_MELLANOX_CONNECTX5VF: 3144 case PCI_DEVICE_ID_MELLANOX_CONNECTX5EX: 3145 case PCI_DEVICE_ID_MELLANOX_CONNECTX5EXVF: 3146 /* 3147 * These NICs support VLAN insertion from WQE and 3148 * report the wqe_vlan_insert flag. But there is the bug 3149 * and PFC control may be broken, so disable feature. 3150 */ 3151 config->hw_vlan_insert = 0; 3152 config->txq_inline_min = MLX5_INLINE_HSIZE_NONE; 3153 break; 3154 default: 3155 config->txq_inline_min = MLX5_INLINE_HSIZE_NONE; 3156 break; 3157 } 3158 exit: 3159 DRV_LOG(DEBUG, "min tx inline configured: %d", config->txq_inline_min); 3160 } 3161 3162 /** 3163 * Configures the metadata mask fields in the shared context. 3164 * 3165 * @param [in] dev 3166 * Pointer to Ethernet device. 3167 */ 3168 void 3169 mlx5_set_metadata_mask(struct rte_eth_dev *dev) 3170 { 3171 struct mlx5_priv *priv = dev->data->dev_private; 3172 struct mlx5_dev_ctx_shared *sh = priv->sh; 3173 uint32_t meta, mark, reg_c0; 3174 3175 reg_c0 = ~priv->vport_meta_mask; 3176 switch (sh->config.dv_xmeta_en) { 3177 case MLX5_XMETA_MODE_LEGACY: 3178 meta = UINT32_MAX; 3179 mark = MLX5_FLOW_MARK_MASK; 3180 break; 3181 case MLX5_XMETA_MODE_META16: 3182 meta = reg_c0 >> rte_bsf32(reg_c0); 3183 mark = MLX5_FLOW_MARK_MASK; 3184 break; 3185 case MLX5_XMETA_MODE_META32: 3186 meta = UINT32_MAX; 3187 mark = (reg_c0 >> rte_bsf32(reg_c0)) & MLX5_FLOW_MARK_MASK; 3188 break; 3189 case MLX5_XMETA_MODE_META32_HWS: 3190 meta = UINT32_MAX; 3191 mark = MLX5_FLOW_MARK_MASK; 3192 break; 3193 default: 3194 meta = 0; 3195 mark = 0; 3196 MLX5_ASSERT(false); 3197 break; 3198 } 3199 if (sh->dv_mark_mask && sh->dv_mark_mask != mark) 3200 DRV_LOG(WARNING, "metadata MARK mask mismatch %08X:%08X", 3201 sh->dv_mark_mask, mark); 3202 else 3203 sh->dv_mark_mask = mark; 3204 if (sh->dv_meta_mask && sh->dv_meta_mask != meta) 3205 DRV_LOG(WARNING, "metadata META mask mismatch %08X:%08X", 3206 sh->dv_meta_mask, meta); 3207 else 3208 sh->dv_meta_mask = meta; 3209 if (sh->dv_regc0_mask && sh->dv_regc0_mask != reg_c0) 3210 DRV_LOG(WARNING, "metadata reg_c0 mask mismatch %08X:%08X", 3211 sh->dv_meta_mask, reg_c0); 3212 else 3213 sh->dv_regc0_mask = reg_c0; 3214 DRV_LOG(DEBUG, "metadata mode %u", sh->config.dv_xmeta_en); 3215 DRV_LOG(DEBUG, "metadata MARK mask %08X", sh->dv_mark_mask); 3216 DRV_LOG(DEBUG, "metadata META mask %08X", sh->dv_meta_mask); 3217 DRV_LOG(DEBUG, "metadata reg_c0 mask %08X", sh->dv_regc0_mask); 3218 } 3219 3220 int 3221 rte_pmd_mlx5_get_dyn_flag_names(char *names[], unsigned int n) 3222 { 3223 static const char *const dynf_names[] = { 3224 RTE_PMD_MLX5_FINE_GRANULARITY_INLINE, 3225 RTE_MBUF_DYNFLAG_METADATA_NAME, 3226 RTE_MBUF_DYNFLAG_TX_TIMESTAMP_NAME 3227 }; 3228 unsigned int i; 3229 3230 if (n < RTE_DIM(dynf_names)) 3231 return -ENOMEM; 3232 for (i = 0; i < RTE_DIM(dynf_names); i++) { 3233 if (names[i] == NULL) 3234 return -EINVAL; 3235 strcpy(names[i], dynf_names[i]); 3236 } 3237 return RTE_DIM(dynf_names); 3238 } 3239 3240 /** 3241 * Look for the ethernet device belonging to mlx5 driver. 3242 * 3243 * @param[in] port_id 3244 * port_id to start looking for device. 3245 * @param[in] odev 3246 * Pointer to the hint device. When device is being probed 3247 * the its siblings (master and preceding representors might 3248 * not have assigned driver yet (because the mlx5_os_pci_probe() 3249 * is not completed yet, for this case match on hint 3250 * device may be used to detect sibling device. 3251 * 3252 * @return 3253 * port_id of found device, RTE_MAX_ETHPORT if not found. 3254 */ 3255 uint16_t 3256 mlx5_eth_find_next(uint16_t port_id, struct rte_device *odev) 3257 { 3258 while (port_id < RTE_MAX_ETHPORTS) { 3259 struct rte_eth_dev *dev = &rte_eth_devices[port_id]; 3260 3261 if (dev->state != RTE_ETH_DEV_UNUSED && 3262 dev->device && 3263 (dev->device == odev || 3264 (dev->device->driver && 3265 dev->device->driver->name && 3266 ((strcmp(dev->device->driver->name, 3267 MLX5_PCI_DRIVER_NAME) == 0) || 3268 (strcmp(dev->device->driver->name, 3269 MLX5_AUXILIARY_DRIVER_NAME) == 0))))) 3270 break; 3271 port_id++; 3272 } 3273 if (port_id >= RTE_MAX_ETHPORTS) 3274 return RTE_MAX_ETHPORTS; 3275 return port_id; 3276 } 3277 3278 /** 3279 * Callback to remove a device. 3280 * 3281 * This function removes all Ethernet devices belong to a given device. 3282 * 3283 * @param[in] cdev 3284 * Pointer to the generic device. 3285 * 3286 * @return 3287 * 0 on success, the function cannot fail. 3288 */ 3289 int 3290 mlx5_net_remove(struct mlx5_common_device *cdev) 3291 { 3292 uint16_t port_id; 3293 int ret = 0; 3294 3295 RTE_ETH_FOREACH_DEV_OF(port_id, cdev->dev) { 3296 /* 3297 * mlx5_dev_close() is not registered to secondary process, 3298 * call the close function explicitly for secondary process. 3299 */ 3300 if (rte_eal_process_type() == RTE_PROC_SECONDARY) 3301 ret |= mlx5_dev_close(&rte_eth_devices[port_id]); 3302 else 3303 ret |= rte_eth_dev_close(port_id); 3304 } 3305 return ret == 0 ? 0 : -EIO; 3306 } 3307 3308 static const struct rte_pci_id mlx5_pci_id_map[] = { 3309 { 3310 RTE_PCI_DEVICE(PCI_VENDOR_ID_MELLANOX, 3311 PCI_DEVICE_ID_MELLANOX_CONNECTX4) 3312 }, 3313 { 3314 RTE_PCI_DEVICE(PCI_VENDOR_ID_MELLANOX, 3315 PCI_DEVICE_ID_MELLANOX_CONNECTX4VF) 3316 }, 3317 { 3318 RTE_PCI_DEVICE(PCI_VENDOR_ID_MELLANOX, 3319 PCI_DEVICE_ID_MELLANOX_CONNECTX4LX) 3320 }, 3321 { 3322 RTE_PCI_DEVICE(PCI_VENDOR_ID_MELLANOX, 3323 PCI_DEVICE_ID_MELLANOX_CONNECTX4LXVF) 3324 }, 3325 { 3326 RTE_PCI_DEVICE(PCI_VENDOR_ID_MELLANOX, 3327 PCI_DEVICE_ID_MELLANOX_CONNECTX5) 3328 }, 3329 { 3330 RTE_PCI_DEVICE(PCI_VENDOR_ID_MELLANOX, 3331 PCI_DEVICE_ID_MELLANOX_CONNECTX5VF) 3332 }, 3333 { 3334 RTE_PCI_DEVICE(PCI_VENDOR_ID_MELLANOX, 3335 PCI_DEVICE_ID_MELLANOX_CONNECTX5EX) 3336 }, 3337 { 3338 RTE_PCI_DEVICE(PCI_VENDOR_ID_MELLANOX, 3339 PCI_DEVICE_ID_MELLANOX_CONNECTX5EXVF) 3340 }, 3341 { 3342 RTE_PCI_DEVICE(PCI_VENDOR_ID_MELLANOX, 3343 PCI_DEVICE_ID_MELLANOX_BLUEFIELD) 3344 }, 3345 { 3346 RTE_PCI_DEVICE(PCI_VENDOR_ID_MELLANOX, 3347 PCI_DEVICE_ID_MELLANOX_BLUEFIELDVF) 3348 }, 3349 { 3350 RTE_PCI_DEVICE(PCI_VENDOR_ID_MELLANOX, 3351 PCI_DEVICE_ID_MELLANOX_CONNECTX6) 3352 }, 3353 { 3354 RTE_PCI_DEVICE(PCI_VENDOR_ID_MELLANOX, 3355 PCI_DEVICE_ID_MELLANOX_CONNECTX6VF) 3356 }, 3357 { 3358 RTE_PCI_DEVICE(PCI_VENDOR_ID_MELLANOX, 3359 PCI_DEVICE_ID_MELLANOX_CONNECTX6DX) 3360 }, 3361 { 3362 RTE_PCI_DEVICE(PCI_VENDOR_ID_MELLANOX, 3363 PCI_DEVICE_ID_MELLANOX_CONNECTXVF) 3364 }, 3365 { 3366 RTE_PCI_DEVICE(PCI_VENDOR_ID_MELLANOX, 3367 PCI_DEVICE_ID_MELLANOX_BLUEFIELD2) 3368 }, 3369 { 3370 RTE_PCI_DEVICE(PCI_VENDOR_ID_MELLANOX, 3371 PCI_DEVICE_ID_MELLANOX_CONNECTX6LX) 3372 }, 3373 { 3374 RTE_PCI_DEVICE(PCI_VENDOR_ID_MELLANOX, 3375 PCI_DEVICE_ID_MELLANOX_CONNECTX7) 3376 }, 3377 { 3378 RTE_PCI_DEVICE(PCI_VENDOR_ID_MELLANOX, 3379 PCI_DEVICE_ID_MELLANOX_BLUEFIELD3) 3380 }, 3381 { 3382 .vendor_id = 0 3383 } 3384 }; 3385 3386 static struct mlx5_class_driver mlx5_net_driver = { 3387 .drv_class = MLX5_CLASS_ETH, 3388 .name = RTE_STR(MLX5_ETH_DRIVER_NAME), 3389 .id_table = mlx5_pci_id_map, 3390 .probe = mlx5_os_net_probe, 3391 .remove = mlx5_net_remove, 3392 .probe_again = 1, 3393 .intr_lsc = 1, 3394 .intr_rmv = 1, 3395 }; 3396 3397 /* Initialize driver log type. */ 3398 RTE_LOG_REGISTER_DEFAULT(mlx5_logtype, NOTICE) 3399 3400 /** 3401 * Driver initialization routine. 3402 */ 3403 RTE_INIT(rte_mlx5_pmd_init) 3404 { 3405 pthread_mutex_init(&mlx5_dev_ctx_list_mutex, NULL); 3406 mlx5_common_init(); 3407 /* Build the static tables for Verbs conversion. */ 3408 mlx5_set_ptype_table(); 3409 mlx5_set_cksum_table(); 3410 mlx5_set_swp_types_table(); 3411 if (mlx5_glue) 3412 mlx5_class_driver_register(&mlx5_net_driver); 3413 } 3414 3415 RTE_PMD_EXPORT_NAME(MLX5_ETH_DRIVER_NAME, __COUNTER__); 3416 RTE_PMD_REGISTER_PCI_TABLE(MLX5_ETH_DRIVER_NAME, mlx5_pci_id_map); 3417 RTE_PMD_REGISTER_KMOD_DEP(MLX5_ETH_DRIVER_NAME, "* ib_uverbs & mlx5_core & mlx5_ib"); 3418