1 /* SPDX-License-Identifier: BSD-3-Clause 2 * Copyright 2015 6WIND S.A. 3 * Copyright 2015 Mellanox Technologies, Ltd 4 */ 5 6 #include <stddef.h> 7 #include <unistd.h> 8 #include <string.h> 9 #include <assert.h> 10 #include <dlfcn.h> 11 #include <stdint.h> 12 #include <stdlib.h> 13 #include <errno.h> 14 #include <net/if.h> 15 #include <sys/mman.h> 16 #include <linux/netlink.h> 17 #include <linux/rtnetlink.h> 18 19 /* Verbs header. */ 20 /* ISO C doesn't support unnamed structs/unions, disabling -pedantic. */ 21 #ifdef PEDANTIC 22 #pragma GCC diagnostic ignored "-Wpedantic" 23 #endif 24 #include <infiniband/verbs.h> 25 #ifdef PEDANTIC 26 #pragma GCC diagnostic error "-Wpedantic" 27 #endif 28 29 #include <rte_malloc.h> 30 #include <rte_ethdev_driver.h> 31 #include <rte_ethdev_pci.h> 32 #include <rte_pci.h> 33 #include <rte_bus_pci.h> 34 #include <rte_common.h> 35 #include <rte_config.h> 36 #include <rte_eal_memconfig.h> 37 #include <rte_kvargs.h> 38 #include <rte_rwlock.h> 39 #include <rte_spinlock.h> 40 #include <rte_string_fns.h> 41 42 #include "mlx5.h" 43 #include "mlx5_utils.h" 44 #include "mlx5_rxtx.h" 45 #include "mlx5_autoconf.h" 46 #include "mlx5_defs.h" 47 #include "mlx5_glue.h" 48 #include "mlx5_mr.h" 49 #include "mlx5_flow.h" 50 51 /* Device parameter to enable RX completion queue compression. */ 52 #define MLX5_RXQ_CQE_COMP_EN "rxq_cqe_comp_en" 53 54 /* Device parameter to enable RX completion entry padding to 128B. */ 55 #define MLX5_RXQ_CQE_PAD_EN "rxq_cqe_pad_en" 56 57 /* Device parameter to enable padding Rx packet to cacheline size. */ 58 #define MLX5_RXQ_PKT_PAD_EN "rxq_pkt_pad_en" 59 60 /* Device parameter to enable Multi-Packet Rx queue. */ 61 #define MLX5_RX_MPRQ_EN "mprq_en" 62 63 /* Device parameter to configure log 2 of the number of strides for MPRQ. */ 64 #define MLX5_RX_MPRQ_LOG_STRIDE_NUM "mprq_log_stride_num" 65 66 /* Device parameter to limit the size of memcpy'd packet for MPRQ. */ 67 #define MLX5_RX_MPRQ_MAX_MEMCPY_LEN "mprq_max_memcpy_len" 68 69 /* Device parameter to set the minimum number of Rx queues to enable MPRQ. */ 70 #define MLX5_RXQS_MIN_MPRQ "rxqs_min_mprq" 71 72 /* Device parameter to configure inline send. */ 73 #define MLX5_TXQ_INLINE "txq_inline" 74 75 /* 76 * Device parameter to configure the number of TX queues threshold for 77 * enabling inline send. 78 */ 79 #define MLX5_TXQS_MIN_INLINE "txqs_min_inline" 80 81 /* 82 * Device parameter to configure the number of TX queues threshold for 83 * enabling vectorized Tx. 84 */ 85 #define MLX5_TXQS_MAX_VEC "txqs_max_vec" 86 87 /* Device parameter to enable multi-packet send WQEs. */ 88 #define MLX5_TXQ_MPW_EN "txq_mpw_en" 89 90 /* Device parameter to include 2 dsegs in the title WQEBB. */ 91 #define MLX5_TXQ_MPW_HDR_DSEG_EN "txq_mpw_hdr_dseg_en" 92 93 /* Device parameter to limit the size of inlining packet. */ 94 #define MLX5_TXQ_MAX_INLINE_LEN "txq_max_inline_len" 95 96 /* Device parameter to enable hardware Tx vector. */ 97 #define MLX5_TX_VEC_EN "tx_vec_en" 98 99 /* Device parameter to enable hardware Rx vector. */ 100 #define MLX5_RX_VEC_EN "rx_vec_en" 101 102 /* Allow L3 VXLAN flow creation. */ 103 #define MLX5_L3_VXLAN_EN "l3_vxlan_en" 104 105 /* Activate DV flow steering. */ 106 #define MLX5_DV_FLOW_EN "dv_flow_en" 107 108 /* Activate Netlink support in VF mode. */ 109 #define MLX5_VF_NL_EN "vf_nl_en" 110 111 /* Select port representors to instantiate. */ 112 #define MLX5_REPRESENTOR "representor" 113 114 #ifndef HAVE_IBV_MLX5_MOD_MPW 115 #define MLX5DV_CONTEXT_FLAGS_MPW_ALLOWED (1 << 2) 116 #define MLX5DV_CONTEXT_FLAGS_ENHANCED_MPW (1 << 3) 117 #endif 118 119 #ifndef HAVE_IBV_MLX5_MOD_CQE_128B_COMP 120 #define MLX5DV_CONTEXT_FLAGS_CQE_128B_COMP (1 << 4) 121 #endif 122 123 static const char *MZ_MLX5_PMD_SHARED_DATA = "mlx5_pmd_shared_data"; 124 125 /* Shared memory between primary and secondary processes. */ 126 struct mlx5_shared_data *mlx5_shared_data; 127 128 /* Spinlock for mlx5_shared_data allocation. */ 129 static rte_spinlock_t mlx5_shared_data_lock = RTE_SPINLOCK_INITIALIZER; 130 131 /** Driver-specific log messages type. */ 132 int mlx5_logtype; 133 134 /** 135 * Prepare shared data between primary and secondary process. 136 */ 137 static void 138 mlx5_prepare_shared_data(void) 139 { 140 const struct rte_memzone *mz; 141 142 rte_spinlock_lock(&mlx5_shared_data_lock); 143 if (mlx5_shared_data == NULL) { 144 if (rte_eal_process_type() == RTE_PROC_PRIMARY) { 145 /* Allocate shared memory. */ 146 mz = rte_memzone_reserve(MZ_MLX5_PMD_SHARED_DATA, 147 sizeof(*mlx5_shared_data), 148 SOCKET_ID_ANY, 0); 149 } else { 150 /* Lookup allocated shared memory. */ 151 mz = rte_memzone_lookup(MZ_MLX5_PMD_SHARED_DATA); 152 } 153 if (mz == NULL) 154 rte_panic("Cannot allocate mlx5 shared data\n"); 155 mlx5_shared_data = mz->addr; 156 /* Initialize shared data. */ 157 if (rte_eal_process_type() == RTE_PROC_PRIMARY) { 158 LIST_INIT(&mlx5_shared_data->mem_event_cb_list); 159 rte_rwlock_init(&mlx5_shared_data->mem_event_rwlock); 160 } 161 rte_mem_event_callback_register("MLX5_MEM_EVENT_CB", 162 mlx5_mr_mem_event_cb, NULL); 163 } 164 rte_spinlock_unlock(&mlx5_shared_data_lock); 165 } 166 167 /** 168 * Retrieve integer value from environment variable. 169 * 170 * @param[in] name 171 * Environment variable name. 172 * 173 * @return 174 * Integer value, 0 if the variable is not set. 175 */ 176 int 177 mlx5_getenv_int(const char *name) 178 { 179 const char *val = getenv(name); 180 181 if (val == NULL) 182 return 0; 183 return atoi(val); 184 } 185 186 /** 187 * Verbs callback to allocate a memory. This function should allocate the space 188 * according to the size provided residing inside a huge page. 189 * Please note that all allocation must respect the alignment from libmlx5 190 * (i.e. currently sysconf(_SC_PAGESIZE)). 191 * 192 * @param[in] size 193 * The size in bytes of the memory to allocate. 194 * @param[in] data 195 * A pointer to the callback data. 196 * 197 * @return 198 * Allocated buffer, NULL otherwise and rte_errno is set. 199 */ 200 static void * 201 mlx5_alloc_verbs_buf(size_t size, void *data) 202 { 203 struct priv *priv = data; 204 void *ret; 205 size_t alignment = sysconf(_SC_PAGESIZE); 206 unsigned int socket = SOCKET_ID_ANY; 207 208 if (priv->verbs_alloc_ctx.type == MLX5_VERBS_ALLOC_TYPE_TX_QUEUE) { 209 const struct mlx5_txq_ctrl *ctrl = priv->verbs_alloc_ctx.obj; 210 211 socket = ctrl->socket; 212 } else if (priv->verbs_alloc_ctx.type == 213 MLX5_VERBS_ALLOC_TYPE_RX_QUEUE) { 214 const struct mlx5_rxq_ctrl *ctrl = priv->verbs_alloc_ctx.obj; 215 216 socket = ctrl->socket; 217 } 218 assert(data != NULL); 219 ret = rte_malloc_socket(__func__, size, alignment, socket); 220 if (!ret && size) 221 rte_errno = ENOMEM; 222 return ret; 223 } 224 225 /** 226 * Verbs callback to free a memory. 227 * 228 * @param[in] ptr 229 * A pointer to the memory to free. 230 * @param[in] data 231 * A pointer to the callback data. 232 */ 233 static void 234 mlx5_free_verbs_buf(void *ptr, void *data __rte_unused) 235 { 236 assert(data != NULL); 237 rte_free(ptr); 238 } 239 240 /** 241 * DPDK callback to close the device. 242 * 243 * Destroy all queues and objects, free memory. 244 * 245 * @param dev 246 * Pointer to Ethernet device structure. 247 */ 248 static void 249 mlx5_dev_close(struct rte_eth_dev *dev) 250 { 251 struct priv *priv = dev->data->dev_private; 252 unsigned int i; 253 int ret; 254 255 DRV_LOG(DEBUG, "port %u closing device \"%s\"", 256 dev->data->port_id, 257 ((priv->ctx != NULL) ? priv->ctx->device->name : "")); 258 /* In case mlx5_dev_stop() has not been called. */ 259 mlx5_dev_interrupt_handler_uninstall(dev); 260 mlx5_traffic_disable(dev); 261 mlx5_flow_flush(dev, NULL); 262 /* Prevent crashes when queues are still in use. */ 263 dev->rx_pkt_burst = removed_rx_burst; 264 dev->tx_pkt_burst = removed_tx_burst; 265 if (priv->rxqs != NULL) { 266 /* XXX race condition if mlx5_rx_burst() is still running. */ 267 usleep(1000); 268 for (i = 0; (i != priv->rxqs_n); ++i) 269 mlx5_rxq_release(dev, i); 270 priv->rxqs_n = 0; 271 priv->rxqs = NULL; 272 } 273 if (priv->txqs != NULL) { 274 /* XXX race condition if mlx5_tx_burst() is still running. */ 275 usleep(1000); 276 for (i = 0; (i != priv->txqs_n); ++i) 277 mlx5_txq_release(dev, i); 278 priv->txqs_n = 0; 279 priv->txqs = NULL; 280 } 281 mlx5_mprq_free_mp(dev); 282 mlx5_mr_release(dev); 283 if (priv->pd != NULL) { 284 assert(priv->ctx != NULL); 285 claim_zero(mlx5_glue->dealloc_pd(priv->pd)); 286 claim_zero(mlx5_glue->close_device(priv->ctx)); 287 } else 288 assert(priv->ctx == NULL); 289 if (priv->rss_conf.rss_key != NULL) 290 rte_free(priv->rss_conf.rss_key); 291 if (priv->reta_idx != NULL) 292 rte_free(priv->reta_idx); 293 if (priv->primary_socket) 294 mlx5_socket_uninit(dev); 295 if (priv->config.vf) 296 mlx5_nl_mac_addr_flush(dev); 297 if (priv->nl_socket_route >= 0) 298 close(priv->nl_socket_route); 299 if (priv->nl_socket_rdma >= 0) 300 close(priv->nl_socket_rdma); 301 if (priv->tcf_context) 302 mlx5_flow_tcf_context_destroy(priv->tcf_context); 303 ret = mlx5_hrxq_ibv_verify(dev); 304 if (ret) 305 DRV_LOG(WARNING, "port %u some hash Rx queue still remain", 306 dev->data->port_id); 307 ret = mlx5_ind_table_ibv_verify(dev); 308 if (ret) 309 DRV_LOG(WARNING, "port %u some indirection table still remain", 310 dev->data->port_id); 311 ret = mlx5_rxq_ibv_verify(dev); 312 if (ret) 313 DRV_LOG(WARNING, "port %u some Verbs Rx queue still remain", 314 dev->data->port_id); 315 ret = mlx5_rxq_verify(dev); 316 if (ret) 317 DRV_LOG(WARNING, "port %u some Rx queues still remain", 318 dev->data->port_id); 319 ret = mlx5_txq_ibv_verify(dev); 320 if (ret) 321 DRV_LOG(WARNING, "port %u some Verbs Tx queue still remain", 322 dev->data->port_id); 323 ret = mlx5_txq_verify(dev); 324 if (ret) 325 DRV_LOG(WARNING, "port %u some Tx queues still remain", 326 dev->data->port_id); 327 ret = mlx5_flow_verify(dev); 328 if (ret) 329 DRV_LOG(WARNING, "port %u some flows still remain", 330 dev->data->port_id); 331 if (priv->domain_id != RTE_ETH_DEV_SWITCH_DOMAIN_ID_INVALID) { 332 unsigned int c = 0; 333 unsigned int i = mlx5_dev_to_port_id(dev->device, NULL, 0); 334 uint16_t port_id[i]; 335 336 i = RTE_MIN(mlx5_dev_to_port_id(dev->device, port_id, i), i); 337 while (i--) { 338 struct priv *opriv = 339 rte_eth_devices[port_id[i]].data->dev_private; 340 341 if (!opriv || 342 opriv->domain_id != priv->domain_id || 343 &rte_eth_devices[port_id[i]] == dev) 344 continue; 345 ++c; 346 } 347 if (!c) 348 claim_zero(rte_eth_switch_domain_free(priv->domain_id)); 349 } 350 memset(priv, 0, sizeof(*priv)); 351 priv->domain_id = RTE_ETH_DEV_SWITCH_DOMAIN_ID_INVALID; 352 /* 353 * Reset mac_addrs to NULL such that it is not freed as part of 354 * rte_eth_dev_release_port(). mac_addrs is part of dev_private so 355 * it is freed when dev_private is freed. 356 */ 357 dev->data->mac_addrs = NULL; 358 } 359 360 const struct eth_dev_ops mlx5_dev_ops = { 361 .dev_configure = mlx5_dev_configure, 362 .dev_start = mlx5_dev_start, 363 .dev_stop = mlx5_dev_stop, 364 .dev_set_link_down = mlx5_set_link_down, 365 .dev_set_link_up = mlx5_set_link_up, 366 .dev_close = mlx5_dev_close, 367 .promiscuous_enable = mlx5_promiscuous_enable, 368 .promiscuous_disable = mlx5_promiscuous_disable, 369 .allmulticast_enable = mlx5_allmulticast_enable, 370 .allmulticast_disable = mlx5_allmulticast_disable, 371 .link_update = mlx5_link_update, 372 .stats_get = mlx5_stats_get, 373 .stats_reset = mlx5_stats_reset, 374 .xstats_get = mlx5_xstats_get, 375 .xstats_reset = mlx5_xstats_reset, 376 .xstats_get_names = mlx5_xstats_get_names, 377 .dev_infos_get = mlx5_dev_infos_get, 378 .dev_supported_ptypes_get = mlx5_dev_supported_ptypes_get, 379 .vlan_filter_set = mlx5_vlan_filter_set, 380 .rx_queue_setup = mlx5_rx_queue_setup, 381 .tx_queue_setup = mlx5_tx_queue_setup, 382 .rx_queue_release = mlx5_rx_queue_release, 383 .tx_queue_release = mlx5_tx_queue_release, 384 .flow_ctrl_get = mlx5_dev_get_flow_ctrl, 385 .flow_ctrl_set = mlx5_dev_set_flow_ctrl, 386 .mac_addr_remove = mlx5_mac_addr_remove, 387 .mac_addr_add = mlx5_mac_addr_add, 388 .mac_addr_set = mlx5_mac_addr_set, 389 .set_mc_addr_list = mlx5_set_mc_addr_list, 390 .mtu_set = mlx5_dev_set_mtu, 391 .vlan_strip_queue_set = mlx5_vlan_strip_queue_set, 392 .vlan_offload_set = mlx5_vlan_offload_set, 393 .reta_update = mlx5_dev_rss_reta_update, 394 .reta_query = mlx5_dev_rss_reta_query, 395 .rss_hash_update = mlx5_rss_hash_update, 396 .rss_hash_conf_get = mlx5_rss_hash_conf_get, 397 .filter_ctrl = mlx5_dev_filter_ctrl, 398 .rx_descriptor_status = mlx5_rx_descriptor_status, 399 .tx_descriptor_status = mlx5_tx_descriptor_status, 400 .rx_queue_count = mlx5_rx_queue_count, 401 .rx_queue_intr_enable = mlx5_rx_intr_enable, 402 .rx_queue_intr_disable = mlx5_rx_intr_disable, 403 .is_removed = mlx5_is_removed, 404 }; 405 406 static const struct eth_dev_ops mlx5_dev_sec_ops = { 407 .stats_get = mlx5_stats_get, 408 .stats_reset = mlx5_stats_reset, 409 .xstats_get = mlx5_xstats_get, 410 .xstats_reset = mlx5_xstats_reset, 411 .xstats_get_names = mlx5_xstats_get_names, 412 .dev_infos_get = mlx5_dev_infos_get, 413 .rx_descriptor_status = mlx5_rx_descriptor_status, 414 .tx_descriptor_status = mlx5_tx_descriptor_status, 415 }; 416 417 /* Available operators in flow isolated mode. */ 418 const struct eth_dev_ops mlx5_dev_ops_isolate = { 419 .dev_configure = mlx5_dev_configure, 420 .dev_start = mlx5_dev_start, 421 .dev_stop = mlx5_dev_stop, 422 .dev_set_link_down = mlx5_set_link_down, 423 .dev_set_link_up = mlx5_set_link_up, 424 .dev_close = mlx5_dev_close, 425 .promiscuous_enable = mlx5_promiscuous_enable, 426 .promiscuous_disable = mlx5_promiscuous_disable, 427 .allmulticast_enable = mlx5_allmulticast_enable, 428 .allmulticast_disable = mlx5_allmulticast_disable, 429 .link_update = mlx5_link_update, 430 .stats_get = mlx5_stats_get, 431 .stats_reset = mlx5_stats_reset, 432 .xstats_get = mlx5_xstats_get, 433 .xstats_reset = mlx5_xstats_reset, 434 .xstats_get_names = mlx5_xstats_get_names, 435 .dev_infos_get = mlx5_dev_infos_get, 436 .dev_supported_ptypes_get = mlx5_dev_supported_ptypes_get, 437 .vlan_filter_set = mlx5_vlan_filter_set, 438 .rx_queue_setup = mlx5_rx_queue_setup, 439 .tx_queue_setup = mlx5_tx_queue_setup, 440 .rx_queue_release = mlx5_rx_queue_release, 441 .tx_queue_release = mlx5_tx_queue_release, 442 .flow_ctrl_get = mlx5_dev_get_flow_ctrl, 443 .flow_ctrl_set = mlx5_dev_set_flow_ctrl, 444 .mac_addr_remove = mlx5_mac_addr_remove, 445 .mac_addr_add = mlx5_mac_addr_add, 446 .mac_addr_set = mlx5_mac_addr_set, 447 .set_mc_addr_list = mlx5_set_mc_addr_list, 448 .mtu_set = mlx5_dev_set_mtu, 449 .vlan_strip_queue_set = mlx5_vlan_strip_queue_set, 450 .vlan_offload_set = mlx5_vlan_offload_set, 451 .filter_ctrl = mlx5_dev_filter_ctrl, 452 .rx_descriptor_status = mlx5_rx_descriptor_status, 453 .tx_descriptor_status = mlx5_tx_descriptor_status, 454 .rx_queue_intr_enable = mlx5_rx_intr_enable, 455 .rx_queue_intr_disable = mlx5_rx_intr_disable, 456 .is_removed = mlx5_is_removed, 457 }; 458 459 /** 460 * Verify and store value for device argument. 461 * 462 * @param[in] key 463 * Key argument to verify. 464 * @param[in] val 465 * Value associated with key. 466 * @param opaque 467 * User data. 468 * 469 * @return 470 * 0 on success, a negative errno value otherwise and rte_errno is set. 471 */ 472 static int 473 mlx5_args_check(const char *key, const char *val, void *opaque) 474 { 475 struct mlx5_dev_config *config = opaque; 476 unsigned long tmp; 477 478 /* No-op, port representors are processed in mlx5_dev_spawn(). */ 479 if (!strcmp(MLX5_REPRESENTOR, key)) 480 return 0; 481 errno = 0; 482 tmp = strtoul(val, NULL, 0); 483 if (errno) { 484 rte_errno = errno; 485 DRV_LOG(WARNING, "%s: \"%s\" is not a valid integer", key, val); 486 return -rte_errno; 487 } 488 if (strcmp(MLX5_RXQ_CQE_COMP_EN, key) == 0) { 489 config->cqe_comp = !!tmp; 490 } else if (strcmp(MLX5_RXQ_CQE_PAD_EN, key) == 0) { 491 config->cqe_pad = !!tmp; 492 } else if (strcmp(MLX5_RXQ_PKT_PAD_EN, key) == 0) { 493 config->hw_padding = !!tmp; 494 } else if (strcmp(MLX5_RX_MPRQ_EN, key) == 0) { 495 config->mprq.enabled = !!tmp; 496 } else if (strcmp(MLX5_RX_MPRQ_LOG_STRIDE_NUM, key) == 0) { 497 config->mprq.stride_num_n = tmp; 498 } else if (strcmp(MLX5_RX_MPRQ_MAX_MEMCPY_LEN, key) == 0) { 499 config->mprq.max_memcpy_len = tmp; 500 } else if (strcmp(MLX5_RXQS_MIN_MPRQ, key) == 0) { 501 config->mprq.min_rxqs_num = tmp; 502 } else if (strcmp(MLX5_TXQ_INLINE, key) == 0) { 503 config->txq_inline = tmp; 504 } else if (strcmp(MLX5_TXQS_MIN_INLINE, key) == 0) { 505 config->txqs_inline = tmp; 506 } else if (strcmp(MLX5_TXQS_MAX_VEC, key) == 0) { 507 config->txqs_vec = tmp; 508 } else if (strcmp(MLX5_TXQ_MPW_EN, key) == 0) { 509 config->mps = !!tmp; 510 } else if (strcmp(MLX5_TXQ_MPW_HDR_DSEG_EN, key) == 0) { 511 config->mpw_hdr_dseg = !!tmp; 512 } else if (strcmp(MLX5_TXQ_MAX_INLINE_LEN, key) == 0) { 513 config->inline_max_packet_sz = tmp; 514 } else if (strcmp(MLX5_TX_VEC_EN, key) == 0) { 515 config->tx_vec_en = !!tmp; 516 } else if (strcmp(MLX5_RX_VEC_EN, key) == 0) { 517 config->rx_vec_en = !!tmp; 518 } else if (strcmp(MLX5_L3_VXLAN_EN, key) == 0) { 519 config->l3_vxlan_en = !!tmp; 520 } else if (strcmp(MLX5_VF_NL_EN, key) == 0) { 521 config->vf_nl_en = !!tmp; 522 } else if (strcmp(MLX5_DV_FLOW_EN, key) == 0) { 523 config->dv_flow_en = !!tmp; 524 } else { 525 DRV_LOG(WARNING, "%s: unknown parameter", key); 526 rte_errno = EINVAL; 527 return -rte_errno; 528 } 529 return 0; 530 } 531 532 /** 533 * Parse device parameters. 534 * 535 * @param config 536 * Pointer to device configuration structure. 537 * @param devargs 538 * Device arguments structure. 539 * 540 * @return 541 * 0 on success, a negative errno value otherwise and rte_errno is set. 542 */ 543 static int 544 mlx5_args(struct mlx5_dev_config *config, struct rte_devargs *devargs) 545 { 546 const char **params = (const char *[]){ 547 MLX5_RXQ_CQE_COMP_EN, 548 MLX5_RXQ_CQE_PAD_EN, 549 MLX5_RXQ_PKT_PAD_EN, 550 MLX5_RX_MPRQ_EN, 551 MLX5_RX_MPRQ_LOG_STRIDE_NUM, 552 MLX5_RX_MPRQ_MAX_MEMCPY_LEN, 553 MLX5_RXQS_MIN_MPRQ, 554 MLX5_TXQ_INLINE, 555 MLX5_TXQS_MIN_INLINE, 556 MLX5_TXQS_MAX_VEC, 557 MLX5_TXQ_MPW_EN, 558 MLX5_TXQ_MPW_HDR_DSEG_EN, 559 MLX5_TXQ_MAX_INLINE_LEN, 560 MLX5_TX_VEC_EN, 561 MLX5_RX_VEC_EN, 562 MLX5_L3_VXLAN_EN, 563 MLX5_VF_NL_EN, 564 MLX5_DV_FLOW_EN, 565 MLX5_REPRESENTOR, 566 NULL, 567 }; 568 struct rte_kvargs *kvlist; 569 int ret = 0; 570 int i; 571 572 if (devargs == NULL) 573 return 0; 574 /* Following UGLY cast is done to pass checkpatch. */ 575 kvlist = rte_kvargs_parse(devargs->args, params); 576 if (kvlist == NULL) 577 return 0; 578 /* Process parameters. */ 579 for (i = 0; (params[i] != NULL); ++i) { 580 if (rte_kvargs_count(kvlist, params[i])) { 581 ret = rte_kvargs_process(kvlist, params[i], 582 mlx5_args_check, config); 583 if (ret) { 584 rte_errno = EINVAL; 585 rte_kvargs_free(kvlist); 586 return -rte_errno; 587 } 588 } 589 } 590 rte_kvargs_free(kvlist); 591 return 0; 592 } 593 594 static struct rte_pci_driver mlx5_driver; 595 596 /* 597 * Reserved UAR address space for TXQ UAR(hw doorbell) mapping, process 598 * local resource used by both primary and secondary to avoid duplicate 599 * reservation. 600 * The space has to be available on both primary and secondary process, 601 * TXQ UAR maps to this area using fixed mmap w/o double check. 602 */ 603 static void *uar_base; 604 605 static int 606 find_lower_va_bound(const struct rte_memseg_list *msl, 607 const struct rte_memseg *ms, void *arg) 608 { 609 void **addr = arg; 610 611 if (msl->external) 612 return 0; 613 if (*addr == NULL) 614 *addr = ms->addr; 615 else 616 *addr = RTE_MIN(*addr, ms->addr); 617 618 return 0; 619 } 620 621 /** 622 * Reserve UAR address space for primary process. 623 * 624 * @param[in] dev 625 * Pointer to Ethernet device. 626 * 627 * @return 628 * 0 on success, a negative errno value otherwise and rte_errno is set. 629 */ 630 static int 631 mlx5_uar_init_primary(struct rte_eth_dev *dev) 632 { 633 struct priv *priv = dev->data->dev_private; 634 void *addr = (void *)0; 635 636 if (uar_base) { /* UAR address space mapped. */ 637 priv->uar_base = uar_base; 638 return 0; 639 } 640 /* find out lower bound of hugepage segments */ 641 rte_memseg_walk(find_lower_va_bound, &addr); 642 643 /* keep distance to hugepages to minimize potential conflicts. */ 644 addr = RTE_PTR_SUB(addr, (uintptr_t)(MLX5_UAR_OFFSET + MLX5_UAR_SIZE)); 645 /* anonymous mmap, no real memory consumption. */ 646 addr = mmap(addr, MLX5_UAR_SIZE, 647 PROT_NONE, MAP_PRIVATE | MAP_ANONYMOUS, -1, 0); 648 if (addr == MAP_FAILED) { 649 DRV_LOG(ERR, 650 "port %u failed to reserve UAR address space, please" 651 " adjust MLX5_UAR_SIZE or try --base-virtaddr", 652 dev->data->port_id); 653 rte_errno = ENOMEM; 654 return -rte_errno; 655 } 656 /* Accept either same addr or a new addr returned from mmap if target 657 * range occupied. 658 */ 659 DRV_LOG(INFO, "port %u reserved UAR address space: %p", 660 dev->data->port_id, addr); 661 priv->uar_base = addr; /* for primary and secondary UAR re-mmap. */ 662 uar_base = addr; /* process local, don't reserve again. */ 663 return 0; 664 } 665 666 /** 667 * Reserve UAR address space for secondary process, align with 668 * primary process. 669 * 670 * @param[in] dev 671 * Pointer to Ethernet device. 672 * 673 * @return 674 * 0 on success, a negative errno value otherwise and rte_errno is set. 675 */ 676 static int 677 mlx5_uar_init_secondary(struct rte_eth_dev *dev) 678 { 679 struct priv *priv = dev->data->dev_private; 680 void *addr; 681 682 assert(priv->uar_base); 683 if (uar_base) { /* already reserved. */ 684 assert(uar_base == priv->uar_base); 685 return 0; 686 } 687 /* anonymous mmap, no real memory consumption. */ 688 addr = mmap(priv->uar_base, MLX5_UAR_SIZE, 689 PROT_NONE, MAP_PRIVATE | MAP_ANONYMOUS, -1, 0); 690 if (addr == MAP_FAILED) { 691 DRV_LOG(ERR, "port %u UAR mmap failed: %p size: %llu", 692 dev->data->port_id, priv->uar_base, MLX5_UAR_SIZE); 693 rte_errno = ENXIO; 694 return -rte_errno; 695 } 696 if (priv->uar_base != addr) { 697 DRV_LOG(ERR, 698 "port %u UAR address %p size %llu occupied, please" 699 " adjust MLX5_UAR_OFFSET or try EAL parameter" 700 " --base-virtaddr", 701 dev->data->port_id, priv->uar_base, MLX5_UAR_SIZE); 702 rte_errno = ENXIO; 703 return -rte_errno; 704 } 705 uar_base = addr; /* process local, don't reserve again */ 706 DRV_LOG(INFO, "port %u reserved UAR address space: %p", 707 dev->data->port_id, addr); 708 return 0; 709 } 710 711 /** 712 * Spawn an Ethernet device from Verbs information. 713 * 714 * @param dpdk_dev 715 * Backing DPDK device. 716 * @param ibv_dev 717 * Verbs device. 718 * @param config 719 * Device configuration parameters. 720 * @param[in] switch_info 721 * Switch properties of Ethernet device. 722 * 723 * @return 724 * A valid Ethernet device object on success, NULL otherwise and rte_errno 725 * is set. The following errors are defined: 726 * 727 * EBUSY: device is not supposed to be spawned. 728 * EEXIST: device is already spawned 729 */ 730 static struct rte_eth_dev * 731 mlx5_dev_spawn(struct rte_device *dpdk_dev, 732 struct ibv_device *ibv_dev, 733 struct mlx5_dev_config config, 734 const struct mlx5_switch_info *switch_info) 735 { 736 struct ibv_context *ctx = NULL; 737 struct ibv_device_attr_ex attr; 738 struct ibv_port_attr port_attr; 739 struct ibv_pd *pd = NULL; 740 struct mlx5dv_context dv_attr = { .comp_mask = 0 }; 741 struct rte_eth_dev *eth_dev = NULL; 742 struct priv *priv = NULL; 743 int err = 0; 744 unsigned int hw_padding = 0; 745 unsigned int mps; 746 unsigned int cqe_comp; 747 unsigned int cqe_pad = 0; 748 unsigned int tunnel_en = 0; 749 unsigned int mpls_en = 0; 750 unsigned int swp = 0; 751 unsigned int mprq = 0; 752 unsigned int mprq_min_stride_size_n = 0; 753 unsigned int mprq_max_stride_size_n = 0; 754 unsigned int mprq_min_stride_num_n = 0; 755 unsigned int mprq_max_stride_num_n = 0; 756 struct ether_addr mac; 757 char name[RTE_ETH_NAME_MAX_LEN]; 758 int own_domain_id = 0; 759 uint16_t port_id; 760 unsigned int i; 761 762 /* Determine if this port representor is supposed to be spawned. */ 763 if (switch_info->representor && dpdk_dev->devargs) { 764 struct rte_eth_devargs eth_da; 765 766 err = rte_eth_devargs_parse(dpdk_dev->devargs->args, ð_da); 767 if (err) { 768 rte_errno = -err; 769 DRV_LOG(ERR, "failed to process device arguments: %s", 770 strerror(rte_errno)); 771 return NULL; 772 } 773 for (i = 0; i < eth_da.nb_representor_ports; ++i) 774 if (eth_da.representor_ports[i] == 775 (uint16_t)switch_info->port_name) 776 break; 777 if (i == eth_da.nb_representor_ports) { 778 rte_errno = EBUSY; 779 return NULL; 780 } 781 } 782 /* Build device name. */ 783 if (!switch_info->representor) 784 rte_strlcpy(name, dpdk_dev->name, sizeof(name)); 785 else 786 snprintf(name, sizeof(name), "%s_representor_%u", 787 dpdk_dev->name, switch_info->port_name); 788 /* check if the device is already spawned */ 789 if (rte_eth_dev_get_port_by_name(name, &port_id) == 0) { 790 rte_errno = EEXIST; 791 return NULL; 792 } 793 /* Prepare shared data between primary and secondary process. */ 794 mlx5_prepare_shared_data(); 795 errno = 0; 796 ctx = mlx5_glue->dv_open_device(ibv_dev); 797 if (ctx) { 798 config.devx = 1; 799 DRV_LOG(DEBUG, "DEVX is supported"); 800 } else { 801 ctx = mlx5_glue->open_device(ibv_dev); 802 if (!ctx) { 803 rte_errno = errno ? errno : ENODEV; 804 return NULL; 805 } 806 } 807 #ifdef HAVE_IBV_MLX5_MOD_SWP 808 dv_attr.comp_mask |= MLX5DV_CONTEXT_MASK_SWP; 809 #endif 810 /* 811 * Multi-packet send is supported by ConnectX-4 Lx PF as well 812 * as all ConnectX-5 devices. 813 */ 814 #ifdef HAVE_IBV_DEVICE_TUNNEL_SUPPORT 815 dv_attr.comp_mask |= MLX5DV_CONTEXT_MASK_TUNNEL_OFFLOADS; 816 #endif 817 #ifdef HAVE_IBV_DEVICE_STRIDING_RQ_SUPPORT 818 dv_attr.comp_mask |= MLX5DV_CONTEXT_MASK_STRIDING_RQ; 819 #endif 820 mlx5_glue->dv_query_device(ctx, &dv_attr); 821 if (dv_attr.flags & MLX5DV_CONTEXT_FLAGS_MPW_ALLOWED) { 822 if (dv_attr.flags & MLX5DV_CONTEXT_FLAGS_ENHANCED_MPW) { 823 DRV_LOG(DEBUG, "enhanced MPW is supported"); 824 mps = MLX5_MPW_ENHANCED; 825 } else { 826 DRV_LOG(DEBUG, "MPW is supported"); 827 mps = MLX5_MPW; 828 } 829 } else { 830 DRV_LOG(DEBUG, "MPW isn't supported"); 831 mps = MLX5_MPW_DISABLED; 832 } 833 #ifdef HAVE_IBV_MLX5_MOD_SWP 834 if (dv_attr.comp_mask & MLX5DV_CONTEXT_MASK_SWP) 835 swp = dv_attr.sw_parsing_caps.sw_parsing_offloads; 836 DRV_LOG(DEBUG, "SWP support: %u", swp); 837 #endif 838 config.swp = !!swp; 839 #ifdef HAVE_IBV_DEVICE_STRIDING_RQ_SUPPORT 840 if (dv_attr.comp_mask & MLX5DV_CONTEXT_MASK_STRIDING_RQ) { 841 struct mlx5dv_striding_rq_caps mprq_caps = 842 dv_attr.striding_rq_caps; 843 844 DRV_LOG(DEBUG, "\tmin_single_stride_log_num_of_bytes: %d", 845 mprq_caps.min_single_stride_log_num_of_bytes); 846 DRV_LOG(DEBUG, "\tmax_single_stride_log_num_of_bytes: %d", 847 mprq_caps.max_single_stride_log_num_of_bytes); 848 DRV_LOG(DEBUG, "\tmin_single_wqe_log_num_of_strides: %d", 849 mprq_caps.min_single_wqe_log_num_of_strides); 850 DRV_LOG(DEBUG, "\tmax_single_wqe_log_num_of_strides: %d", 851 mprq_caps.max_single_wqe_log_num_of_strides); 852 DRV_LOG(DEBUG, "\tsupported_qpts: %d", 853 mprq_caps.supported_qpts); 854 DRV_LOG(DEBUG, "device supports Multi-Packet RQ"); 855 mprq = 1; 856 mprq_min_stride_size_n = 857 mprq_caps.min_single_stride_log_num_of_bytes; 858 mprq_max_stride_size_n = 859 mprq_caps.max_single_stride_log_num_of_bytes; 860 mprq_min_stride_num_n = 861 mprq_caps.min_single_wqe_log_num_of_strides; 862 mprq_max_stride_num_n = 863 mprq_caps.max_single_wqe_log_num_of_strides; 864 config.mprq.stride_num_n = RTE_MAX(MLX5_MPRQ_STRIDE_NUM_N, 865 mprq_min_stride_num_n); 866 } 867 #endif 868 if (RTE_CACHE_LINE_SIZE == 128 && 869 !(dv_attr.flags & MLX5DV_CONTEXT_FLAGS_CQE_128B_COMP)) 870 cqe_comp = 0; 871 else 872 cqe_comp = 1; 873 config.cqe_comp = cqe_comp; 874 #ifdef HAVE_IBV_MLX5_MOD_CQE_128B_PAD 875 /* Whether device supports 128B Rx CQE padding. */ 876 cqe_pad = RTE_CACHE_LINE_SIZE == 128 && 877 (dv_attr.flags & MLX5DV_CONTEXT_FLAGS_CQE_128B_PAD); 878 #endif 879 #ifdef HAVE_IBV_DEVICE_TUNNEL_SUPPORT 880 if (dv_attr.comp_mask & MLX5DV_CONTEXT_MASK_TUNNEL_OFFLOADS) { 881 tunnel_en = ((dv_attr.tunnel_offloads_caps & 882 MLX5DV_RAW_PACKET_CAP_TUNNELED_OFFLOAD_VXLAN) && 883 (dv_attr.tunnel_offloads_caps & 884 MLX5DV_RAW_PACKET_CAP_TUNNELED_OFFLOAD_GRE)); 885 } 886 DRV_LOG(DEBUG, "tunnel offloading is %ssupported", 887 tunnel_en ? "" : "not "); 888 #else 889 DRV_LOG(WARNING, 890 "tunnel offloading disabled due to old OFED/rdma-core version"); 891 #endif 892 config.tunnel_en = tunnel_en; 893 #ifdef HAVE_IBV_DEVICE_MPLS_SUPPORT 894 mpls_en = ((dv_attr.tunnel_offloads_caps & 895 MLX5DV_RAW_PACKET_CAP_TUNNELED_OFFLOAD_CW_MPLS_OVER_GRE) && 896 (dv_attr.tunnel_offloads_caps & 897 MLX5DV_RAW_PACKET_CAP_TUNNELED_OFFLOAD_CW_MPLS_OVER_UDP)); 898 DRV_LOG(DEBUG, "MPLS over GRE/UDP tunnel offloading is %ssupported", 899 mpls_en ? "" : "not "); 900 #else 901 DRV_LOG(WARNING, "MPLS over GRE/UDP tunnel offloading disabled due to" 902 " old OFED/rdma-core version or firmware configuration"); 903 #endif 904 config.mpls_en = mpls_en; 905 err = mlx5_glue->query_device_ex(ctx, NULL, &attr); 906 if (err) { 907 DEBUG("ibv_query_device_ex() failed"); 908 goto error; 909 } 910 DRV_LOG(DEBUG, "naming Ethernet device \"%s\"", name); 911 if (rte_eal_process_type() == RTE_PROC_SECONDARY) { 912 eth_dev = rte_eth_dev_attach_secondary(name); 913 if (eth_dev == NULL) { 914 DRV_LOG(ERR, "can not attach rte ethdev"); 915 rte_errno = ENOMEM; 916 err = rte_errno; 917 goto error; 918 } 919 eth_dev->device = dpdk_dev; 920 eth_dev->dev_ops = &mlx5_dev_sec_ops; 921 err = mlx5_uar_init_secondary(eth_dev); 922 if (err) { 923 err = rte_errno; 924 goto error; 925 } 926 /* Receive command fd from primary process */ 927 err = mlx5_socket_connect(eth_dev); 928 if (err < 0) { 929 err = rte_errno; 930 goto error; 931 } 932 /* Remap UAR for Tx queues. */ 933 err = mlx5_tx_uar_remap(eth_dev, err); 934 if (err) { 935 err = rte_errno; 936 goto error; 937 } 938 /* 939 * Ethdev pointer is still required as input since 940 * the primary device is not accessible from the 941 * secondary process. 942 */ 943 eth_dev->rx_pkt_burst = mlx5_select_rx_function(eth_dev); 944 eth_dev->tx_pkt_burst = mlx5_select_tx_function(eth_dev); 945 claim_zero(mlx5_glue->close_device(ctx)); 946 return eth_dev; 947 } 948 /* Check port status. */ 949 err = mlx5_glue->query_port(ctx, 1, &port_attr); 950 if (err) { 951 DRV_LOG(ERR, "port query failed: %s", strerror(err)); 952 goto error; 953 } 954 if (port_attr.link_layer != IBV_LINK_LAYER_ETHERNET) { 955 DRV_LOG(ERR, "port is not configured in Ethernet mode"); 956 err = EINVAL; 957 goto error; 958 } 959 if (port_attr.state != IBV_PORT_ACTIVE) 960 DRV_LOG(DEBUG, "port is not active: \"%s\" (%d)", 961 mlx5_glue->port_state_str(port_attr.state), 962 port_attr.state); 963 /* Allocate protection domain. */ 964 pd = mlx5_glue->alloc_pd(ctx); 965 if (pd == NULL) { 966 DRV_LOG(ERR, "PD allocation failure"); 967 err = ENOMEM; 968 goto error; 969 } 970 priv = rte_zmalloc("ethdev private structure", 971 sizeof(*priv), 972 RTE_CACHE_LINE_SIZE); 973 if (priv == NULL) { 974 DRV_LOG(ERR, "priv allocation failure"); 975 err = ENOMEM; 976 goto error; 977 } 978 priv->ctx = ctx; 979 strncpy(priv->ibdev_name, priv->ctx->device->name, 980 sizeof(priv->ibdev_name)); 981 strncpy(priv->ibdev_path, priv->ctx->device->ibdev_path, 982 sizeof(priv->ibdev_path)); 983 priv->device_attr = attr; 984 priv->pd = pd; 985 priv->mtu = ETHER_MTU; 986 #ifndef RTE_ARCH_64 987 /* Initialize UAR access locks for 32bit implementations. */ 988 rte_spinlock_init(&priv->uar_lock_cq); 989 for (i = 0; i < MLX5_UAR_PAGE_NUM_MAX; i++) 990 rte_spinlock_init(&priv->uar_lock[i]); 991 #endif 992 /* Some internal functions rely on Netlink sockets, open them now. */ 993 priv->nl_socket_rdma = mlx5_nl_init(NETLINK_RDMA); 994 priv->nl_socket_route = mlx5_nl_init(NETLINK_ROUTE); 995 priv->nl_sn = 0; 996 priv->representor = !!switch_info->representor; 997 priv->domain_id = RTE_ETH_DEV_SWITCH_DOMAIN_ID_INVALID; 998 priv->representor_id = 999 switch_info->representor ? switch_info->port_name : -1; 1000 /* 1001 * Look for sibling devices in order to reuse their switch domain 1002 * if any, otherwise allocate one. 1003 */ 1004 i = mlx5_dev_to_port_id(dpdk_dev, NULL, 0); 1005 if (i > 0) { 1006 uint16_t port_id[i]; 1007 1008 i = RTE_MIN(mlx5_dev_to_port_id(dpdk_dev, port_id, i), i); 1009 while (i--) { 1010 const struct priv *opriv = 1011 rte_eth_devices[port_id[i]].data->dev_private; 1012 1013 if (!opriv || 1014 opriv->domain_id == 1015 RTE_ETH_DEV_SWITCH_DOMAIN_ID_INVALID) 1016 continue; 1017 priv->domain_id = opriv->domain_id; 1018 break; 1019 } 1020 } 1021 if (priv->domain_id == RTE_ETH_DEV_SWITCH_DOMAIN_ID_INVALID) { 1022 err = rte_eth_switch_domain_alloc(&priv->domain_id); 1023 if (err) { 1024 err = rte_errno; 1025 DRV_LOG(ERR, "unable to allocate switch domain: %s", 1026 strerror(rte_errno)); 1027 goto error; 1028 } 1029 own_domain_id = 1; 1030 } 1031 err = mlx5_args(&config, dpdk_dev->devargs); 1032 if (err) { 1033 err = rte_errno; 1034 DRV_LOG(ERR, "failed to process device arguments: %s", 1035 strerror(rte_errno)); 1036 goto error; 1037 } 1038 config.hw_csum = !!(attr.device_cap_flags_ex & IBV_DEVICE_RAW_IP_CSUM); 1039 DRV_LOG(DEBUG, "checksum offloading is %ssupported", 1040 (config.hw_csum ? "" : "not ")); 1041 #if !defined(HAVE_IBV_DEVICE_COUNTERS_SET_V42) && \ 1042 !defined(HAVE_IBV_DEVICE_COUNTERS_SET_V45) 1043 DRV_LOG(DEBUG, "counters are not supported"); 1044 #endif 1045 #ifndef HAVE_IBV_FLOW_DV_SUPPORT 1046 if (config.dv_flow_en) { 1047 DRV_LOG(WARNING, "DV flow is not supported"); 1048 config.dv_flow_en = 0; 1049 } 1050 #endif 1051 config.ind_table_max_size = 1052 attr.rss_caps.max_rwq_indirection_table_size; 1053 /* 1054 * Remove this check once DPDK supports larger/variable 1055 * indirection tables. 1056 */ 1057 if (config.ind_table_max_size > (unsigned int)ETH_RSS_RETA_SIZE_512) 1058 config.ind_table_max_size = ETH_RSS_RETA_SIZE_512; 1059 DRV_LOG(DEBUG, "maximum Rx indirection table size is %u", 1060 config.ind_table_max_size); 1061 config.hw_vlan_strip = !!(attr.raw_packet_caps & 1062 IBV_RAW_PACKET_CAP_CVLAN_STRIPPING); 1063 DRV_LOG(DEBUG, "VLAN stripping is %ssupported", 1064 (config.hw_vlan_strip ? "" : "not ")); 1065 config.hw_fcs_strip = !!(attr.raw_packet_caps & 1066 IBV_RAW_PACKET_CAP_SCATTER_FCS); 1067 DRV_LOG(DEBUG, "FCS stripping configuration is %ssupported", 1068 (config.hw_fcs_strip ? "" : "not ")); 1069 #if defined(HAVE_IBV_WQ_FLAG_RX_END_PADDING) 1070 hw_padding = !!attr.rx_pad_end_addr_align; 1071 #elif defined(HAVE_IBV_WQ_FLAGS_PCI_WRITE_END_PADDING) 1072 hw_padding = !!(attr.device_cap_flags_ex & 1073 IBV_DEVICE_PCI_WRITE_END_PADDING); 1074 #endif 1075 if (config.hw_padding && !hw_padding) { 1076 DRV_LOG(DEBUG, "Rx end alignment padding isn't supported"); 1077 config.hw_padding = 0; 1078 } else if (config.hw_padding) { 1079 DRV_LOG(DEBUG, "Rx end alignment padding is enabled"); 1080 } 1081 config.tso = (attr.tso_caps.max_tso > 0 && 1082 (attr.tso_caps.supported_qpts & 1083 (1 << IBV_QPT_RAW_PACKET))); 1084 if (config.tso) 1085 config.tso_max_payload_sz = attr.tso_caps.max_tso; 1086 /* 1087 * MPW is disabled by default, while the Enhanced MPW is enabled 1088 * by default. 1089 */ 1090 if (config.mps == MLX5_ARG_UNSET) 1091 config.mps = (mps == MLX5_MPW_ENHANCED) ? MLX5_MPW_ENHANCED : 1092 MLX5_MPW_DISABLED; 1093 else 1094 config.mps = config.mps ? mps : MLX5_MPW_DISABLED; 1095 DRV_LOG(INFO, "%sMPS is %s", 1096 config.mps == MLX5_MPW_ENHANCED ? "enhanced " : "", 1097 config.mps != MLX5_MPW_DISABLED ? "enabled" : "disabled"); 1098 if (config.cqe_comp && !cqe_comp) { 1099 DRV_LOG(WARNING, "Rx CQE compression isn't supported"); 1100 config.cqe_comp = 0; 1101 } 1102 if (config.cqe_pad && !cqe_pad) { 1103 DRV_LOG(WARNING, "Rx CQE padding isn't supported"); 1104 config.cqe_pad = 0; 1105 } else if (config.cqe_pad) { 1106 DRV_LOG(INFO, "Rx CQE padding is enabled"); 1107 } 1108 if (config.mprq.enabled && mprq) { 1109 if (config.mprq.stride_num_n > mprq_max_stride_num_n || 1110 config.mprq.stride_num_n < mprq_min_stride_num_n) { 1111 config.mprq.stride_num_n = 1112 RTE_MAX(MLX5_MPRQ_STRIDE_NUM_N, 1113 mprq_min_stride_num_n); 1114 DRV_LOG(WARNING, 1115 "the number of strides" 1116 " for Multi-Packet RQ is out of range," 1117 " setting default value (%u)", 1118 1 << config.mprq.stride_num_n); 1119 } 1120 config.mprq.min_stride_size_n = mprq_min_stride_size_n; 1121 config.mprq.max_stride_size_n = mprq_max_stride_size_n; 1122 } else if (config.mprq.enabled && !mprq) { 1123 DRV_LOG(WARNING, "Multi-Packet RQ isn't supported"); 1124 config.mprq.enabled = 0; 1125 } 1126 eth_dev = rte_eth_dev_allocate(name); 1127 if (eth_dev == NULL) { 1128 DRV_LOG(ERR, "can not allocate rte ethdev"); 1129 err = ENOMEM; 1130 goto error; 1131 } 1132 /* Flag to call rte_eth_dev_release_port() in rte_eth_dev_close(). */ 1133 eth_dev->data->dev_flags |= RTE_ETH_DEV_CLOSE_REMOVE; 1134 if (priv->representor) { 1135 eth_dev->data->dev_flags |= RTE_ETH_DEV_REPRESENTOR; 1136 eth_dev->data->representor_id = priv->representor_id; 1137 } 1138 eth_dev->data->dev_private = priv; 1139 priv->dev_data = eth_dev->data; 1140 eth_dev->data->mac_addrs = priv->mac; 1141 eth_dev->device = dpdk_dev; 1142 err = mlx5_uar_init_primary(eth_dev); 1143 if (err) { 1144 err = rte_errno; 1145 goto error; 1146 } 1147 /* Configure the first MAC address by default. */ 1148 if (mlx5_get_mac(eth_dev, &mac.addr_bytes)) { 1149 DRV_LOG(ERR, 1150 "port %u cannot get MAC address, is mlx5_en" 1151 " loaded? (errno: %s)", 1152 eth_dev->data->port_id, strerror(rte_errno)); 1153 err = ENODEV; 1154 goto error; 1155 } 1156 DRV_LOG(INFO, 1157 "port %u MAC address is %02x:%02x:%02x:%02x:%02x:%02x", 1158 eth_dev->data->port_id, 1159 mac.addr_bytes[0], mac.addr_bytes[1], 1160 mac.addr_bytes[2], mac.addr_bytes[3], 1161 mac.addr_bytes[4], mac.addr_bytes[5]); 1162 #ifndef NDEBUG 1163 { 1164 char ifname[IF_NAMESIZE]; 1165 1166 if (mlx5_get_ifname(eth_dev, &ifname) == 0) 1167 DRV_LOG(DEBUG, "port %u ifname is \"%s\"", 1168 eth_dev->data->port_id, ifname); 1169 else 1170 DRV_LOG(DEBUG, "port %u ifname is unknown", 1171 eth_dev->data->port_id); 1172 } 1173 #endif 1174 /* Get actual MTU if possible. */ 1175 err = mlx5_get_mtu(eth_dev, &priv->mtu); 1176 if (err) { 1177 err = rte_errno; 1178 goto error; 1179 } 1180 DRV_LOG(DEBUG, "port %u MTU is %u", eth_dev->data->port_id, 1181 priv->mtu); 1182 /* Initialize burst functions to prevent crashes before link-up. */ 1183 eth_dev->rx_pkt_burst = removed_rx_burst; 1184 eth_dev->tx_pkt_burst = removed_tx_burst; 1185 eth_dev->dev_ops = &mlx5_dev_ops; 1186 /* Register MAC address. */ 1187 claim_zero(mlx5_mac_addr_add(eth_dev, &mac, 0, 0)); 1188 if (config.vf && config.vf_nl_en) 1189 mlx5_nl_mac_addr_sync(eth_dev); 1190 priv->tcf_context = mlx5_flow_tcf_context_create(); 1191 if (!priv->tcf_context) { 1192 err = -rte_errno; 1193 DRV_LOG(WARNING, 1194 "flow rules relying on switch offloads will not be" 1195 " supported: cannot open libmnl socket: %s", 1196 strerror(rte_errno)); 1197 } else { 1198 struct rte_flow_error error; 1199 unsigned int ifindex = mlx5_ifindex(eth_dev); 1200 1201 if (!ifindex) { 1202 err = -rte_errno; 1203 error.message = 1204 "cannot retrieve network interface index"; 1205 } else { 1206 err = mlx5_flow_tcf_init(priv->tcf_context, 1207 ifindex, &error); 1208 } 1209 if (err) { 1210 DRV_LOG(WARNING, 1211 "flow rules relying on switch offloads will" 1212 " not be supported: %s: %s", 1213 error.message, strerror(rte_errno)); 1214 mlx5_flow_tcf_context_destroy(priv->tcf_context); 1215 priv->tcf_context = NULL; 1216 } 1217 } 1218 TAILQ_INIT(&priv->flows); 1219 TAILQ_INIT(&priv->ctrl_flows); 1220 /* Hint libmlx5 to use PMD allocator for data plane resources */ 1221 struct mlx5dv_ctx_allocators alctr = { 1222 .alloc = &mlx5_alloc_verbs_buf, 1223 .free = &mlx5_free_verbs_buf, 1224 .data = priv, 1225 }; 1226 mlx5_glue->dv_set_context_attr(ctx, MLX5DV_CTX_ATTR_BUF_ALLOCATORS, 1227 (void *)((uintptr_t)&alctr)); 1228 /* Bring Ethernet device up. */ 1229 DRV_LOG(DEBUG, "port %u forcing Ethernet interface up", 1230 eth_dev->data->port_id); 1231 mlx5_set_link_up(eth_dev); 1232 /* 1233 * Even though the interrupt handler is not installed yet, 1234 * interrupts will still trigger on the asyn_fd from 1235 * Verbs context returned by ibv_open_device(). 1236 */ 1237 mlx5_link_update(eth_dev, 0); 1238 /* Store device configuration on private structure. */ 1239 priv->config = config; 1240 /* Supported Verbs flow priority number detection. */ 1241 err = mlx5_flow_discover_priorities(eth_dev); 1242 if (err < 0) 1243 goto error; 1244 priv->config.flow_prio = err; 1245 /* 1246 * Once the device is added to the list of memory event 1247 * callback, its global MR cache table cannot be expanded 1248 * on the fly because of deadlock. If it overflows, lookup 1249 * should be done by searching MR list linearly, which is slow. 1250 */ 1251 err = mlx5_mr_btree_init(&priv->mr.cache, 1252 MLX5_MR_BTREE_CACHE_N * 2, 1253 eth_dev->device->numa_node); 1254 if (err) { 1255 err = rte_errno; 1256 goto error; 1257 } 1258 /* Add device to memory callback list. */ 1259 rte_rwlock_write_lock(&mlx5_shared_data->mem_event_rwlock); 1260 LIST_INSERT_HEAD(&mlx5_shared_data->mem_event_cb_list, 1261 priv, mem_event_cb); 1262 rte_rwlock_write_unlock(&mlx5_shared_data->mem_event_rwlock); 1263 return eth_dev; 1264 error: 1265 if (priv) { 1266 if (priv->nl_socket_route >= 0) 1267 close(priv->nl_socket_route); 1268 if (priv->nl_socket_rdma >= 0) 1269 close(priv->nl_socket_rdma); 1270 if (priv->tcf_context) 1271 mlx5_flow_tcf_context_destroy(priv->tcf_context); 1272 if (own_domain_id) 1273 claim_zero(rte_eth_switch_domain_free(priv->domain_id)); 1274 rte_free(priv); 1275 if (eth_dev != NULL) 1276 eth_dev->data->dev_private = NULL; 1277 } 1278 if (pd) 1279 claim_zero(mlx5_glue->dealloc_pd(pd)); 1280 if (eth_dev != NULL) { 1281 /* mac_addrs must not be freed alone because part of dev_private */ 1282 eth_dev->data->mac_addrs = NULL; 1283 rte_eth_dev_release_port(eth_dev); 1284 } 1285 if (ctx) 1286 claim_zero(mlx5_glue->close_device(ctx)); 1287 assert(err > 0); 1288 rte_errno = err; 1289 return NULL; 1290 } 1291 1292 /** Data associated with devices to spawn. */ 1293 struct mlx5_dev_spawn_data { 1294 unsigned int ifindex; /**< Network interface index. */ 1295 struct mlx5_switch_info info; /**< Switch information. */ 1296 struct ibv_device *ibv_dev; /**< Associated IB device. */ 1297 struct rte_eth_dev *eth_dev; /**< Associated Ethernet device. */ 1298 }; 1299 1300 /** 1301 * Comparison callback to sort device data. 1302 * 1303 * This is meant to be used with qsort(). 1304 * 1305 * @param a[in] 1306 * Pointer to pointer to first data object. 1307 * @param b[in] 1308 * Pointer to pointer to second data object. 1309 * 1310 * @return 1311 * 0 if both objects are equal, less than 0 if the first argument is less 1312 * than the second, greater than 0 otherwise. 1313 */ 1314 static int 1315 mlx5_dev_spawn_data_cmp(const void *a, const void *b) 1316 { 1317 const struct mlx5_switch_info *si_a = 1318 &((const struct mlx5_dev_spawn_data *)a)->info; 1319 const struct mlx5_switch_info *si_b = 1320 &((const struct mlx5_dev_spawn_data *)b)->info; 1321 int ret; 1322 1323 /* Master device first. */ 1324 ret = si_b->master - si_a->master; 1325 if (ret) 1326 return ret; 1327 /* Then representor devices. */ 1328 ret = si_b->representor - si_a->representor; 1329 if (ret) 1330 return ret; 1331 /* Unidentified devices come last in no specific order. */ 1332 if (!si_a->representor) 1333 return 0; 1334 /* Order representors by name. */ 1335 return si_a->port_name - si_b->port_name; 1336 } 1337 1338 /** 1339 * DPDK callback to register a PCI device. 1340 * 1341 * This function spawns Ethernet devices out of a given PCI device. 1342 * 1343 * @param[in] pci_drv 1344 * PCI driver structure (mlx5_driver). 1345 * @param[in] pci_dev 1346 * PCI device information. 1347 * 1348 * @return 1349 * 0 on success, a negative errno value otherwise and rte_errno is set. 1350 */ 1351 static int 1352 mlx5_pci_probe(struct rte_pci_driver *pci_drv __rte_unused, 1353 struct rte_pci_device *pci_dev) 1354 { 1355 struct ibv_device **ibv_list; 1356 unsigned int n = 0; 1357 struct mlx5_dev_config dev_config; 1358 int ret; 1359 1360 assert(pci_drv == &mlx5_driver); 1361 errno = 0; 1362 ibv_list = mlx5_glue->get_device_list(&ret); 1363 if (!ibv_list) { 1364 rte_errno = errno ? errno : ENOSYS; 1365 DRV_LOG(ERR, "cannot list devices, is ib_uverbs loaded?"); 1366 return -rte_errno; 1367 } 1368 1369 struct ibv_device *ibv_match[ret + 1]; 1370 1371 while (ret-- > 0) { 1372 struct rte_pci_addr pci_addr; 1373 1374 DRV_LOG(DEBUG, "checking device \"%s\"", ibv_list[ret]->name); 1375 if (mlx5_ibv_device_to_pci_addr(ibv_list[ret], &pci_addr)) 1376 continue; 1377 if (pci_dev->addr.domain != pci_addr.domain || 1378 pci_dev->addr.bus != pci_addr.bus || 1379 pci_dev->addr.devid != pci_addr.devid || 1380 pci_dev->addr.function != pci_addr.function) 1381 continue; 1382 DRV_LOG(INFO, "PCI information matches for device \"%s\"", 1383 ibv_list[ret]->name); 1384 ibv_match[n++] = ibv_list[ret]; 1385 } 1386 ibv_match[n] = NULL; 1387 1388 struct mlx5_dev_spawn_data list[n]; 1389 int nl_route = n ? mlx5_nl_init(NETLINK_ROUTE) : -1; 1390 int nl_rdma = n ? mlx5_nl_init(NETLINK_RDMA) : -1; 1391 unsigned int i; 1392 unsigned int u; 1393 1394 /* 1395 * The existence of several matching entries (n > 1) means port 1396 * representors have been instantiated. No existing Verbs call nor 1397 * /sys entries can tell them apart, this can only be done through 1398 * Netlink calls assuming kernel drivers are recent enough to 1399 * support them. 1400 * 1401 * In the event of identification failure through Netlink, try again 1402 * through sysfs, then either: 1403 * 1404 * 1. No device matches (n == 0), complain and bail out. 1405 * 2. A single IB device matches (n == 1) and is not a representor, 1406 * assume no switch support. 1407 * 3. Otherwise no safe assumptions can be made; complain louder and 1408 * bail out. 1409 */ 1410 for (i = 0; i != n; ++i) { 1411 list[i].ibv_dev = ibv_match[i]; 1412 list[i].eth_dev = NULL; 1413 if (nl_rdma < 0) 1414 list[i].ifindex = 0; 1415 else 1416 list[i].ifindex = mlx5_nl_ifindex 1417 (nl_rdma, list[i].ibv_dev->name); 1418 if (nl_route < 0 || 1419 !list[i].ifindex || 1420 mlx5_nl_switch_info(nl_route, list[i].ifindex, 1421 &list[i].info) || 1422 ((!list[i].info.representor && !list[i].info.master) && 1423 mlx5_sysfs_switch_info(list[i].ifindex, &list[i].info))) { 1424 list[i].ifindex = 0; 1425 memset(&list[i].info, 0, sizeof(list[i].info)); 1426 continue; 1427 } 1428 } 1429 if (nl_rdma >= 0) 1430 close(nl_rdma); 1431 if (nl_route >= 0) 1432 close(nl_route); 1433 /* Count unidentified devices. */ 1434 for (u = 0, i = 0; i != n; ++i) 1435 if (!list[i].info.master && !list[i].info.representor) 1436 ++u; 1437 if (u) { 1438 if (n == 1 && u == 1) { 1439 /* Case #2. */ 1440 DRV_LOG(INFO, "no switch support detected"); 1441 } else { 1442 /* Case #3. */ 1443 DRV_LOG(ERR, 1444 "unable to tell which of the matching devices" 1445 " is the master (lack of kernel support?)"); 1446 n = 0; 1447 } 1448 } 1449 /* 1450 * Sort list to probe devices in natural order for users convenience 1451 * (i.e. master first, then representors from lowest to highest ID). 1452 */ 1453 if (n) 1454 qsort(list, n, sizeof(*list), mlx5_dev_spawn_data_cmp); 1455 /* Default configuration. */ 1456 dev_config = (struct mlx5_dev_config){ 1457 .hw_padding = 0, 1458 .mps = MLX5_ARG_UNSET, 1459 .tx_vec_en = 1, 1460 .rx_vec_en = 1, 1461 .txq_inline = MLX5_ARG_UNSET, 1462 .txqs_inline = MLX5_ARG_UNSET, 1463 .txqs_vec = MLX5_ARG_UNSET, 1464 .inline_max_packet_sz = MLX5_ARG_UNSET, 1465 .vf_nl_en = 1, 1466 .mprq = { 1467 .enabled = 0, /* Disabled by default. */ 1468 .stride_num_n = MLX5_MPRQ_STRIDE_NUM_N, 1469 .max_memcpy_len = MLX5_MPRQ_MEMCPY_DEFAULT_LEN, 1470 .min_rxqs_num = MLX5_MPRQ_MIN_RXQS, 1471 }, 1472 }; 1473 /* Device speicific configuration. */ 1474 switch (pci_dev->id.device_id) { 1475 case PCI_DEVICE_ID_MELLANOX_CONNECTX5BF: 1476 dev_config.txqs_vec = MLX5_VPMD_MAX_TXQS_BLUEFIELD; 1477 break; 1478 case PCI_DEVICE_ID_MELLANOX_CONNECTX4VF: 1479 case PCI_DEVICE_ID_MELLANOX_CONNECTX4LXVF: 1480 case PCI_DEVICE_ID_MELLANOX_CONNECTX5VF: 1481 case PCI_DEVICE_ID_MELLANOX_CONNECTX5EXVF: 1482 dev_config.vf = 1; 1483 break; 1484 default: 1485 break; 1486 } 1487 /* Set architecture-dependent default value if unset. */ 1488 if (dev_config.txqs_vec == MLX5_ARG_UNSET) 1489 dev_config.txqs_vec = MLX5_VPMD_MAX_TXQS; 1490 for (i = 0; i != n; ++i) { 1491 uint32_t restore; 1492 1493 list[i].eth_dev = mlx5_dev_spawn(&pci_dev->device, 1494 list[i].ibv_dev, dev_config, 1495 &list[i].info); 1496 if (!list[i].eth_dev) { 1497 if (rte_errno != EBUSY && rte_errno != EEXIST) 1498 break; 1499 /* Device is disabled or already spawned. Ignore it. */ 1500 continue; 1501 } 1502 restore = list[i].eth_dev->data->dev_flags; 1503 rte_eth_copy_pci_info(list[i].eth_dev, pci_dev); 1504 /* Restore non-PCI flags cleared by the above call. */ 1505 list[i].eth_dev->data->dev_flags |= restore; 1506 rte_eth_dev_probing_finish(list[i].eth_dev); 1507 } 1508 mlx5_glue->free_device_list(ibv_list); 1509 if (!n) { 1510 DRV_LOG(WARNING, 1511 "no Verbs device matches PCI device " PCI_PRI_FMT "," 1512 " are kernel drivers loaded?", 1513 pci_dev->addr.domain, pci_dev->addr.bus, 1514 pci_dev->addr.devid, pci_dev->addr.function); 1515 rte_errno = ENOENT; 1516 ret = -rte_errno; 1517 } else if (i != n) { 1518 DRV_LOG(ERR, 1519 "probe of PCI device " PCI_PRI_FMT " aborted after" 1520 " encountering an error: %s", 1521 pci_dev->addr.domain, pci_dev->addr.bus, 1522 pci_dev->addr.devid, pci_dev->addr.function, 1523 strerror(rte_errno)); 1524 ret = -rte_errno; 1525 /* Roll back. */ 1526 while (i--) { 1527 if (!list[i].eth_dev) 1528 continue; 1529 mlx5_dev_close(list[i].eth_dev); 1530 /* mac_addrs must not be freed because in dev_private */ 1531 list[i].eth_dev->data->mac_addrs = NULL; 1532 claim_zero(rte_eth_dev_release_port(list[i].eth_dev)); 1533 } 1534 /* Restore original error. */ 1535 rte_errno = -ret; 1536 } else { 1537 ret = 0; 1538 } 1539 return ret; 1540 } 1541 1542 /** 1543 * DPDK callback to remove a PCI device. 1544 * 1545 * This function removes all Ethernet devices belong to a given PCI device. 1546 * 1547 * @param[in] pci_dev 1548 * Pointer to the PCI device. 1549 * 1550 * @return 1551 * 0 on success, the function cannot fail. 1552 */ 1553 static int 1554 mlx5_pci_remove(struct rte_pci_device *pci_dev) 1555 { 1556 uint16_t port_id; 1557 struct rte_eth_dev *port; 1558 1559 for (port_id = 0; port_id < RTE_MAX_ETHPORTS; port_id++) { 1560 port = &rte_eth_devices[port_id]; 1561 if (port->state != RTE_ETH_DEV_UNUSED && 1562 port->device == &pci_dev->device) 1563 rte_eth_dev_close(port_id); 1564 } 1565 return 0; 1566 } 1567 1568 static const struct rte_pci_id mlx5_pci_id_map[] = { 1569 { 1570 RTE_PCI_DEVICE(PCI_VENDOR_ID_MELLANOX, 1571 PCI_DEVICE_ID_MELLANOX_CONNECTX4) 1572 }, 1573 { 1574 RTE_PCI_DEVICE(PCI_VENDOR_ID_MELLANOX, 1575 PCI_DEVICE_ID_MELLANOX_CONNECTX4VF) 1576 }, 1577 { 1578 RTE_PCI_DEVICE(PCI_VENDOR_ID_MELLANOX, 1579 PCI_DEVICE_ID_MELLANOX_CONNECTX4LX) 1580 }, 1581 { 1582 RTE_PCI_DEVICE(PCI_VENDOR_ID_MELLANOX, 1583 PCI_DEVICE_ID_MELLANOX_CONNECTX4LXVF) 1584 }, 1585 { 1586 RTE_PCI_DEVICE(PCI_VENDOR_ID_MELLANOX, 1587 PCI_DEVICE_ID_MELLANOX_CONNECTX5) 1588 }, 1589 { 1590 RTE_PCI_DEVICE(PCI_VENDOR_ID_MELLANOX, 1591 PCI_DEVICE_ID_MELLANOX_CONNECTX5VF) 1592 }, 1593 { 1594 RTE_PCI_DEVICE(PCI_VENDOR_ID_MELLANOX, 1595 PCI_DEVICE_ID_MELLANOX_CONNECTX5EX) 1596 }, 1597 { 1598 RTE_PCI_DEVICE(PCI_VENDOR_ID_MELLANOX, 1599 PCI_DEVICE_ID_MELLANOX_CONNECTX5EXVF) 1600 }, 1601 { 1602 RTE_PCI_DEVICE(PCI_VENDOR_ID_MELLANOX, 1603 PCI_DEVICE_ID_MELLANOX_CONNECTX5BF) 1604 }, 1605 { 1606 RTE_PCI_DEVICE(PCI_VENDOR_ID_MELLANOX, 1607 PCI_DEVICE_ID_MELLANOX_CONNECTX5BFVF) 1608 }, 1609 { 1610 RTE_PCI_DEVICE(PCI_VENDOR_ID_MELLANOX, 1611 PCI_DEVICE_ID_MELLANOX_CONNECTX6) 1612 }, 1613 { 1614 RTE_PCI_DEVICE(PCI_VENDOR_ID_MELLANOX, 1615 PCI_DEVICE_ID_MELLANOX_CONNECTX6VF) 1616 }, 1617 { 1618 .vendor_id = 0 1619 } 1620 }; 1621 1622 static struct rte_pci_driver mlx5_driver = { 1623 .driver = { 1624 .name = MLX5_DRIVER_NAME 1625 }, 1626 .id_table = mlx5_pci_id_map, 1627 .probe = mlx5_pci_probe, 1628 .remove = mlx5_pci_remove, 1629 .drv_flags = (RTE_PCI_DRV_INTR_LSC | RTE_PCI_DRV_INTR_RMV | 1630 RTE_PCI_DRV_PROBE_AGAIN), 1631 }; 1632 1633 #ifdef RTE_IBVERBS_LINK_DLOPEN 1634 1635 /** 1636 * Suffix RTE_EAL_PMD_PATH with "-glue". 1637 * 1638 * This function performs a sanity check on RTE_EAL_PMD_PATH before 1639 * suffixing its last component. 1640 * 1641 * @param buf[out] 1642 * Output buffer, should be large enough otherwise NULL is returned. 1643 * @param size 1644 * Size of @p out. 1645 * 1646 * @return 1647 * Pointer to @p buf or @p NULL in case suffix cannot be appended. 1648 */ 1649 static char * 1650 mlx5_glue_path(char *buf, size_t size) 1651 { 1652 static const char *const bad[] = { "/", ".", "..", NULL }; 1653 const char *path = RTE_EAL_PMD_PATH; 1654 size_t len = strlen(path); 1655 size_t off; 1656 int i; 1657 1658 while (len && path[len - 1] == '/') 1659 --len; 1660 for (off = len; off && path[off - 1] != '/'; --off) 1661 ; 1662 for (i = 0; bad[i]; ++i) 1663 if (!strncmp(path + off, bad[i], (int)(len - off))) 1664 goto error; 1665 i = snprintf(buf, size, "%.*s-glue", (int)len, path); 1666 if (i == -1 || (size_t)i >= size) 1667 goto error; 1668 return buf; 1669 error: 1670 DRV_LOG(ERR, 1671 "unable to append \"-glue\" to last component of" 1672 " RTE_EAL_PMD_PATH (\"" RTE_EAL_PMD_PATH "\")," 1673 " please re-configure DPDK"); 1674 return NULL; 1675 } 1676 1677 /** 1678 * Initialization routine for run-time dependency on rdma-core. 1679 */ 1680 static int 1681 mlx5_glue_init(void) 1682 { 1683 char glue_path[sizeof(RTE_EAL_PMD_PATH) - 1 + sizeof("-glue")]; 1684 const char *path[] = { 1685 /* 1686 * A basic security check is necessary before trusting 1687 * MLX5_GLUE_PATH, which may override RTE_EAL_PMD_PATH. 1688 */ 1689 (geteuid() == getuid() && getegid() == getgid() ? 1690 getenv("MLX5_GLUE_PATH") : NULL), 1691 /* 1692 * When RTE_EAL_PMD_PATH is set, use its glue-suffixed 1693 * variant, otherwise let dlopen() look up libraries on its 1694 * own. 1695 */ 1696 (*RTE_EAL_PMD_PATH ? 1697 mlx5_glue_path(glue_path, sizeof(glue_path)) : ""), 1698 }; 1699 unsigned int i = 0; 1700 void *handle = NULL; 1701 void **sym; 1702 const char *dlmsg; 1703 1704 while (!handle && i != RTE_DIM(path)) { 1705 const char *end; 1706 size_t len; 1707 int ret; 1708 1709 if (!path[i]) { 1710 ++i; 1711 continue; 1712 } 1713 end = strpbrk(path[i], ":;"); 1714 if (!end) 1715 end = path[i] + strlen(path[i]); 1716 len = end - path[i]; 1717 ret = 0; 1718 do { 1719 char name[ret + 1]; 1720 1721 ret = snprintf(name, sizeof(name), "%.*s%s" MLX5_GLUE, 1722 (int)len, path[i], 1723 (!len || *(end - 1) == '/') ? "" : "/"); 1724 if (ret == -1) 1725 break; 1726 if (sizeof(name) != (size_t)ret + 1) 1727 continue; 1728 DRV_LOG(DEBUG, "looking for rdma-core glue as \"%s\"", 1729 name); 1730 handle = dlopen(name, RTLD_LAZY); 1731 break; 1732 } while (1); 1733 path[i] = end + 1; 1734 if (!*end) 1735 ++i; 1736 } 1737 if (!handle) { 1738 rte_errno = EINVAL; 1739 dlmsg = dlerror(); 1740 if (dlmsg) 1741 DRV_LOG(WARNING, "cannot load glue library: %s", dlmsg); 1742 goto glue_error; 1743 } 1744 sym = dlsym(handle, "mlx5_glue"); 1745 if (!sym || !*sym) { 1746 rte_errno = EINVAL; 1747 dlmsg = dlerror(); 1748 if (dlmsg) 1749 DRV_LOG(ERR, "cannot resolve glue symbol: %s", dlmsg); 1750 goto glue_error; 1751 } 1752 mlx5_glue = *sym; 1753 return 0; 1754 glue_error: 1755 if (handle) 1756 dlclose(handle); 1757 DRV_LOG(WARNING, 1758 "cannot initialize PMD due to missing run-time dependency on" 1759 " rdma-core libraries (libibverbs, libmlx5)"); 1760 return -rte_errno; 1761 } 1762 1763 #endif 1764 1765 /** 1766 * Driver initialization routine. 1767 */ 1768 RTE_INIT(rte_mlx5_pmd_init) 1769 { 1770 /* Initialize driver log type. */ 1771 mlx5_logtype = rte_log_register("pmd.net.mlx5"); 1772 if (mlx5_logtype >= 0) 1773 rte_log_set_level(mlx5_logtype, RTE_LOG_NOTICE); 1774 1775 /* Build the static tables for Verbs conversion. */ 1776 mlx5_set_ptype_table(); 1777 mlx5_set_cksum_table(); 1778 mlx5_set_swp_types_table(); 1779 /* 1780 * RDMAV_HUGEPAGES_SAFE tells ibv_fork_init() we intend to use 1781 * huge pages. Calling ibv_fork_init() during init allows 1782 * applications to use fork() safely for purposes other than 1783 * using this PMD, which is not supported in forked processes. 1784 */ 1785 setenv("RDMAV_HUGEPAGES_SAFE", "1", 1); 1786 /* Match the size of Rx completion entry to the size of a cacheline. */ 1787 if (RTE_CACHE_LINE_SIZE == 128) 1788 setenv("MLX5_CQE_SIZE", "128", 0); 1789 /* 1790 * MLX5_DEVICE_FATAL_CLEANUP tells ibv_destroy functions to 1791 * cleanup all the Verbs resources even when the device was removed. 1792 */ 1793 setenv("MLX5_DEVICE_FATAL_CLEANUP", "1", 1); 1794 #ifdef RTE_IBVERBS_LINK_DLOPEN 1795 if (mlx5_glue_init()) 1796 return; 1797 assert(mlx5_glue); 1798 #endif 1799 #ifndef NDEBUG 1800 /* Glue structure must not contain any NULL pointers. */ 1801 { 1802 unsigned int i; 1803 1804 for (i = 0; i != sizeof(*mlx5_glue) / sizeof(void *); ++i) 1805 assert(((const void *const *)mlx5_glue)[i]); 1806 } 1807 #endif 1808 if (strcmp(mlx5_glue->version, MLX5_GLUE_VERSION)) { 1809 DRV_LOG(ERR, 1810 "rdma-core glue \"%s\" mismatch: \"%s\" is required", 1811 mlx5_glue->version, MLX5_GLUE_VERSION); 1812 return; 1813 } 1814 mlx5_glue->fork_init(); 1815 rte_pci_register(&mlx5_driver); 1816 } 1817 1818 RTE_PMD_EXPORT_NAME(net_mlx5, __COUNTER__); 1819 RTE_PMD_REGISTER_PCI_TABLE(net_mlx5, mlx5_pci_id_map); 1820 RTE_PMD_REGISTER_KMOD_DEP(net_mlx5, "* ib_uverbs & mlx5_core & mlx5_ib"); 1821