1 /*- 2 * BSD LICENSE 3 * 4 * Copyright 2015 6WIND S.A. 5 * Copyright 2015 Mellanox. 6 * 7 * Redistribution and use in source and binary forms, with or without 8 * modification, are permitted provided that the following conditions 9 * are met: 10 * 11 * * Redistributions of source code must retain the above copyright 12 * notice, this list of conditions and the following disclaimer. 13 * * Redistributions in binary form must reproduce the above copyright 14 * notice, this list of conditions and the following disclaimer in 15 * the documentation and/or other materials provided with the 16 * distribution. 17 * * Neither the name of 6WIND S.A. nor the names of its 18 * contributors may be used to endorse or promote products derived 19 * from this software without specific prior written permission. 20 * 21 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 22 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 23 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 24 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 25 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 26 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 27 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 28 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 29 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 30 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 31 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 32 */ 33 34 #include <stddef.h> 35 #include <unistd.h> 36 #include <string.h> 37 #include <assert.h> 38 #include <stdint.h> 39 #include <stdlib.h> 40 #include <errno.h> 41 #include <net/if.h> 42 43 /* Verbs header. */ 44 /* ISO C doesn't support unnamed structs/unions, disabling -pedantic. */ 45 #ifdef PEDANTIC 46 #pragma GCC diagnostic ignored "-Wpedantic" 47 #endif 48 #include <infiniband/verbs.h> 49 #ifdef PEDANTIC 50 #pragma GCC diagnostic error "-Wpedantic" 51 #endif 52 53 /* DPDK headers don't like -pedantic. */ 54 #ifdef PEDANTIC 55 #pragma GCC diagnostic ignored "-Wpedantic" 56 #endif 57 #include <rte_malloc.h> 58 #include <rte_ethdev.h> 59 #include <rte_pci.h> 60 #include <rte_common.h> 61 #include <rte_kvargs.h> 62 #ifdef PEDANTIC 63 #pragma GCC diagnostic error "-Wpedantic" 64 #endif 65 66 #include "mlx5.h" 67 #include "mlx5_utils.h" 68 #include "mlx5_rxtx.h" 69 #include "mlx5_autoconf.h" 70 #include "mlx5_defs.h" 71 72 /* Device parameter to enable RX completion queue compression. */ 73 #define MLX5_RXQ_CQE_COMP_EN "rxq_cqe_comp_en" 74 75 /* Device parameter to configure inline send. */ 76 #define MLX5_TXQ_INLINE "txq_inline" 77 78 /* 79 * Device parameter to configure the number of TX queues threshold for 80 * enabling inline send. 81 */ 82 #define MLX5_TXQS_MIN_INLINE "txqs_min_inline" 83 84 /* Device parameter to enable multi-packet send WQEs. */ 85 #define MLX5_TXQ_MPW_EN "txq_mpw_en" 86 87 /** 88 * Retrieve integer value from environment variable. 89 * 90 * @param[in] name 91 * Environment variable name. 92 * 93 * @return 94 * Integer value, 0 if the variable is not set. 95 */ 96 int 97 mlx5_getenv_int(const char *name) 98 { 99 const char *val = getenv(name); 100 101 if (val == NULL) 102 return 0; 103 return atoi(val); 104 } 105 106 /** 107 * DPDK callback to close the device. 108 * 109 * Destroy all queues and objects, free memory. 110 * 111 * @param dev 112 * Pointer to Ethernet device structure. 113 */ 114 static void 115 mlx5_dev_close(struct rte_eth_dev *dev) 116 { 117 struct priv *priv = mlx5_get_priv(dev); 118 unsigned int i; 119 120 priv_lock(priv); 121 DEBUG("%p: closing device \"%s\"", 122 (void *)dev, 123 ((priv->ctx != NULL) ? priv->ctx->device->name : "")); 124 /* In case mlx5_dev_stop() has not been called. */ 125 priv_dev_interrupt_handler_uninstall(priv, dev); 126 priv_special_flow_disable_all(priv); 127 priv_mac_addrs_disable(priv); 128 priv_destroy_hash_rxqs(priv); 129 130 /* Remove flow director elements. */ 131 priv_fdir_disable(priv); 132 priv_fdir_delete_filters_list(priv); 133 134 /* Prevent crashes when queues are still in use. */ 135 dev->rx_pkt_burst = removed_rx_burst; 136 dev->tx_pkt_burst = removed_tx_burst; 137 if (priv->rxqs != NULL) { 138 /* XXX race condition if mlx5_rx_burst() is still running. */ 139 usleep(1000); 140 for (i = 0; (i != priv->rxqs_n); ++i) { 141 struct rxq *rxq = (*priv->rxqs)[i]; 142 struct rxq_ctrl *rxq_ctrl; 143 144 if (rxq == NULL) 145 continue; 146 rxq_ctrl = container_of(rxq, struct rxq_ctrl, rxq); 147 (*priv->rxqs)[i] = NULL; 148 rxq_cleanup(rxq_ctrl); 149 rte_free(rxq_ctrl); 150 } 151 priv->rxqs_n = 0; 152 priv->rxqs = NULL; 153 } 154 if (priv->txqs != NULL) { 155 /* XXX race condition if mlx5_tx_burst() is still running. */ 156 usleep(1000); 157 for (i = 0; (i != priv->txqs_n); ++i) { 158 struct txq *txq = (*priv->txqs)[i]; 159 struct txq_ctrl *txq_ctrl; 160 161 if (txq == NULL) 162 continue; 163 txq_ctrl = container_of(txq, struct txq_ctrl, txq); 164 (*priv->txqs)[i] = NULL; 165 txq_cleanup(txq_ctrl); 166 rte_free(txq_ctrl); 167 } 168 priv->txqs_n = 0; 169 priv->txqs = NULL; 170 } 171 if (priv->pd != NULL) { 172 assert(priv->ctx != NULL); 173 claim_zero(ibv_dealloc_pd(priv->pd)); 174 claim_zero(ibv_close_device(priv->ctx)); 175 } else 176 assert(priv->ctx == NULL); 177 if (priv->rss_conf != NULL) { 178 for (i = 0; (i != hash_rxq_init_n); ++i) 179 rte_free((*priv->rss_conf)[i]); 180 rte_free(priv->rss_conf); 181 } 182 if (priv->reta_idx != NULL) 183 rte_free(priv->reta_idx); 184 priv_unlock(priv); 185 memset(priv, 0, sizeof(*priv)); 186 } 187 188 static const struct eth_dev_ops mlx5_dev_ops = { 189 .dev_configure = mlx5_dev_configure, 190 .dev_start = mlx5_dev_start, 191 .dev_stop = mlx5_dev_stop, 192 .dev_set_link_down = mlx5_set_link_down, 193 .dev_set_link_up = mlx5_set_link_up, 194 .dev_close = mlx5_dev_close, 195 .promiscuous_enable = mlx5_promiscuous_enable, 196 .promiscuous_disable = mlx5_promiscuous_disable, 197 .allmulticast_enable = mlx5_allmulticast_enable, 198 .allmulticast_disable = mlx5_allmulticast_disable, 199 .link_update = mlx5_link_update, 200 .stats_get = mlx5_stats_get, 201 .stats_reset = mlx5_stats_reset, 202 .dev_infos_get = mlx5_dev_infos_get, 203 .dev_supported_ptypes_get = mlx5_dev_supported_ptypes_get, 204 .vlan_filter_set = mlx5_vlan_filter_set, 205 .rx_queue_setup = mlx5_rx_queue_setup, 206 .tx_queue_setup = mlx5_tx_queue_setup, 207 .rx_queue_release = mlx5_rx_queue_release, 208 .tx_queue_release = mlx5_tx_queue_release, 209 .flow_ctrl_get = mlx5_dev_get_flow_ctrl, 210 .flow_ctrl_set = mlx5_dev_set_flow_ctrl, 211 .mac_addr_remove = mlx5_mac_addr_remove, 212 .mac_addr_add = mlx5_mac_addr_add, 213 .mac_addr_set = mlx5_mac_addr_set, 214 .mtu_set = mlx5_dev_set_mtu, 215 .vlan_strip_queue_set = mlx5_vlan_strip_queue_set, 216 .vlan_offload_set = mlx5_vlan_offload_set, 217 .reta_update = mlx5_dev_rss_reta_update, 218 .reta_query = mlx5_dev_rss_reta_query, 219 .rss_hash_update = mlx5_rss_hash_update, 220 .rss_hash_conf_get = mlx5_rss_hash_conf_get, 221 .filter_ctrl = mlx5_dev_filter_ctrl, 222 }; 223 224 static struct { 225 struct rte_pci_addr pci_addr; /* associated PCI address */ 226 uint32_t ports; /* physical ports bitfield. */ 227 } mlx5_dev[32]; 228 229 /** 230 * Get device index in mlx5_dev[] from PCI bus address. 231 * 232 * @param[in] pci_addr 233 * PCI bus address to look for. 234 * 235 * @return 236 * mlx5_dev[] index on success, -1 on failure. 237 */ 238 static int 239 mlx5_dev_idx(struct rte_pci_addr *pci_addr) 240 { 241 unsigned int i; 242 int ret = -1; 243 244 assert(pci_addr != NULL); 245 for (i = 0; (i != RTE_DIM(mlx5_dev)); ++i) { 246 if ((mlx5_dev[i].pci_addr.domain == pci_addr->domain) && 247 (mlx5_dev[i].pci_addr.bus == pci_addr->bus) && 248 (mlx5_dev[i].pci_addr.devid == pci_addr->devid) && 249 (mlx5_dev[i].pci_addr.function == pci_addr->function)) 250 return i; 251 if ((mlx5_dev[i].ports == 0) && (ret == -1)) 252 ret = i; 253 } 254 return ret; 255 } 256 257 /** 258 * Verify and store value for device argument. 259 * 260 * @param[in] key 261 * Key argument to verify. 262 * @param[in] val 263 * Value associated with key. 264 * @param opaque 265 * User data. 266 * 267 * @return 268 * 0 on success, negative errno value on failure. 269 */ 270 static int 271 mlx5_args_check(const char *key, const char *val, void *opaque) 272 { 273 struct priv *priv = opaque; 274 unsigned long tmp; 275 276 errno = 0; 277 tmp = strtoul(val, NULL, 0); 278 if (errno) { 279 WARN("%s: \"%s\" is not a valid integer", key, val); 280 return errno; 281 } 282 if (strcmp(MLX5_RXQ_CQE_COMP_EN, key) == 0) { 283 priv->cqe_comp = !!tmp; 284 } else if (strcmp(MLX5_TXQ_INLINE, key) == 0) { 285 priv->txq_inline = tmp; 286 } else if (strcmp(MLX5_TXQS_MIN_INLINE, key) == 0) { 287 priv->txqs_inline = tmp; 288 } else if (strcmp(MLX5_TXQ_MPW_EN, key) == 0) { 289 priv->mps &= !!tmp; /* Enable MPW only if HW supports */ 290 } else { 291 WARN("%s: unknown parameter", key); 292 return -EINVAL; 293 } 294 return 0; 295 } 296 297 /** 298 * Parse device parameters. 299 * 300 * @param priv 301 * Pointer to private structure. 302 * @param devargs 303 * Device arguments structure. 304 * 305 * @return 306 * 0 on success, errno value on failure. 307 */ 308 static int 309 mlx5_args(struct priv *priv, struct rte_devargs *devargs) 310 { 311 const char **params = (const char *[]){ 312 MLX5_RXQ_CQE_COMP_EN, 313 MLX5_TXQ_INLINE, 314 MLX5_TXQS_MIN_INLINE, 315 MLX5_TXQ_MPW_EN, 316 NULL, 317 }; 318 struct rte_kvargs *kvlist; 319 int ret = 0; 320 int i; 321 322 if (devargs == NULL) 323 return 0; 324 /* Following UGLY cast is done to pass checkpatch. */ 325 kvlist = rte_kvargs_parse(devargs->args, params); 326 if (kvlist == NULL) 327 return 0; 328 /* Process parameters. */ 329 for (i = 0; (params[i] != NULL); ++i) { 330 if (rte_kvargs_count(kvlist, params[i])) { 331 ret = rte_kvargs_process(kvlist, params[i], 332 mlx5_args_check, priv); 333 if (ret != 0) 334 return ret; 335 } 336 } 337 rte_kvargs_free(kvlist); 338 return 0; 339 } 340 341 static struct eth_driver mlx5_driver; 342 343 /** 344 * DPDK callback to register a PCI device. 345 * 346 * This function creates an Ethernet device for each port of a given 347 * PCI device. 348 * 349 * @param[in] pci_drv 350 * PCI driver structure (mlx5_driver). 351 * @param[in] pci_dev 352 * PCI device information. 353 * 354 * @return 355 * 0 on success, negative errno value on failure. 356 */ 357 static int 358 mlx5_pci_probe(struct rte_pci_driver *pci_drv, struct rte_pci_device *pci_dev) 359 { 360 struct ibv_device **list; 361 struct ibv_device *ibv_dev; 362 int err = 0; 363 struct ibv_context *attr_ctx = NULL; 364 struct ibv_device_attr device_attr; 365 unsigned int sriov; 366 unsigned int mps; 367 int idx; 368 int i; 369 370 (void)pci_drv; 371 assert(pci_drv == &mlx5_driver.pci_drv); 372 /* Get mlx5_dev[] index. */ 373 idx = mlx5_dev_idx(&pci_dev->addr); 374 if (idx == -1) { 375 ERROR("this driver cannot support any more adapters"); 376 return -ENOMEM; 377 } 378 DEBUG("using driver device index %d", idx); 379 380 /* Save PCI address. */ 381 mlx5_dev[idx].pci_addr = pci_dev->addr; 382 list = ibv_get_device_list(&i); 383 if (list == NULL) { 384 assert(errno); 385 if (errno == ENOSYS) { 386 WARN("cannot list devices, is ib_uverbs loaded?"); 387 return 0; 388 } 389 return -errno; 390 } 391 assert(i >= 0); 392 /* 393 * For each listed device, check related sysfs entry against 394 * the provided PCI ID. 395 */ 396 while (i != 0) { 397 struct rte_pci_addr pci_addr; 398 399 --i; 400 DEBUG("checking device \"%s\"", list[i]->name); 401 if (mlx5_ibv_device_to_pci_addr(list[i], &pci_addr)) 402 continue; 403 if ((pci_dev->addr.domain != pci_addr.domain) || 404 (pci_dev->addr.bus != pci_addr.bus) || 405 (pci_dev->addr.devid != pci_addr.devid) || 406 (pci_dev->addr.function != pci_addr.function)) 407 continue; 408 sriov = ((pci_dev->id.device_id == 409 PCI_DEVICE_ID_MELLANOX_CONNECTX4VF) || 410 (pci_dev->id.device_id == 411 PCI_DEVICE_ID_MELLANOX_CONNECTX4LXVF) || 412 (pci_dev->id.device_id == 413 PCI_DEVICE_ID_MELLANOX_CONNECTX5VF) || 414 (pci_dev->id.device_id == 415 PCI_DEVICE_ID_MELLANOX_CONNECTX5EXVF)); 416 /* 417 * Multi-packet send is supported by ConnectX-4 Lx PF as well 418 * as all ConnectX-5 devices. 419 */ 420 switch (pci_dev->id.device_id) { 421 case PCI_DEVICE_ID_MELLANOX_CONNECTX4LX: 422 case PCI_DEVICE_ID_MELLANOX_CONNECTX5: 423 case PCI_DEVICE_ID_MELLANOX_CONNECTX5VF: 424 case PCI_DEVICE_ID_MELLANOX_CONNECTX5EX: 425 case PCI_DEVICE_ID_MELLANOX_CONNECTX5EXVF: 426 mps = 1; 427 break; 428 default: 429 mps = 0; 430 } 431 INFO("PCI information matches, using device \"%s\"" 432 " (SR-IOV: %s, MPS: %s)", 433 list[i]->name, 434 sriov ? "true" : "false", 435 mps ? "true" : "false"); 436 attr_ctx = ibv_open_device(list[i]); 437 err = errno; 438 break; 439 } 440 if (attr_ctx == NULL) { 441 ibv_free_device_list(list); 442 switch (err) { 443 case 0: 444 WARN("cannot access device, is mlx5_ib loaded?"); 445 return 0; 446 case EINVAL: 447 WARN("cannot use device, are drivers up to date?"); 448 return 0; 449 } 450 assert(err > 0); 451 return -err; 452 } 453 ibv_dev = list[i]; 454 455 DEBUG("device opened"); 456 if (ibv_query_device(attr_ctx, &device_attr)) 457 goto error; 458 INFO("%u port(s) detected", device_attr.phys_port_cnt); 459 460 for (i = 0; i < device_attr.phys_port_cnt; i++) { 461 uint32_t port = i + 1; /* ports are indexed from one */ 462 uint32_t test = (1 << i); 463 struct ibv_context *ctx = NULL; 464 struct ibv_port_attr port_attr; 465 struct ibv_pd *pd = NULL; 466 struct priv *priv = NULL; 467 struct rte_eth_dev *eth_dev; 468 struct ibv_exp_device_attr exp_device_attr; 469 struct ether_addr mac; 470 uint16_t num_vfs = 0; 471 472 exp_device_attr.comp_mask = 473 IBV_EXP_DEVICE_ATTR_EXP_CAP_FLAGS | 474 IBV_EXP_DEVICE_ATTR_RX_HASH | 475 IBV_EXP_DEVICE_ATTR_VLAN_OFFLOADS | 476 IBV_EXP_DEVICE_ATTR_RX_PAD_END_ALIGN | 477 0; 478 479 DEBUG("using port %u (%08" PRIx32 ")", port, test); 480 481 ctx = ibv_open_device(ibv_dev); 482 if (ctx == NULL) 483 goto port_error; 484 485 /* Check port status. */ 486 err = ibv_query_port(ctx, port, &port_attr); 487 if (err) { 488 ERROR("port query failed: %s", strerror(err)); 489 goto port_error; 490 } 491 492 if (port_attr.link_layer != IBV_LINK_LAYER_ETHERNET) { 493 ERROR("port %d is not configured in Ethernet mode", 494 port); 495 goto port_error; 496 } 497 498 if (port_attr.state != IBV_PORT_ACTIVE) 499 DEBUG("port %d is not active: \"%s\" (%d)", 500 port, ibv_port_state_str(port_attr.state), 501 port_attr.state); 502 503 /* Allocate protection domain. */ 504 pd = ibv_alloc_pd(ctx); 505 if (pd == NULL) { 506 ERROR("PD allocation failure"); 507 err = ENOMEM; 508 goto port_error; 509 } 510 511 mlx5_dev[idx].ports |= test; 512 513 /* from rte_ethdev.c */ 514 priv = rte_zmalloc("ethdev private structure", 515 sizeof(*priv), 516 RTE_CACHE_LINE_SIZE); 517 if (priv == NULL) { 518 ERROR("priv allocation failure"); 519 err = ENOMEM; 520 goto port_error; 521 } 522 523 priv->ctx = ctx; 524 priv->device_attr = device_attr; 525 priv->port = port; 526 priv->pd = pd; 527 priv->mtu = ETHER_MTU; 528 priv->mps = mps; /* Enable MPW by default if supported. */ 529 priv->cqe_comp = 1; /* Enable compression by default. */ 530 err = mlx5_args(priv, pci_dev->device.devargs); 531 if (err) { 532 ERROR("failed to process device arguments: %s", 533 strerror(err)); 534 goto port_error; 535 } 536 if (ibv_exp_query_device(ctx, &exp_device_attr)) { 537 ERROR("ibv_exp_query_device() failed"); 538 goto port_error; 539 } 540 541 priv->hw_csum = 542 ((exp_device_attr.exp_device_cap_flags & 543 IBV_EXP_DEVICE_RX_CSUM_TCP_UDP_PKT) && 544 (exp_device_attr.exp_device_cap_flags & 545 IBV_EXP_DEVICE_RX_CSUM_IP_PKT)); 546 DEBUG("checksum offloading is %ssupported", 547 (priv->hw_csum ? "" : "not ")); 548 549 priv->hw_csum_l2tun = !!(exp_device_attr.exp_device_cap_flags & 550 IBV_EXP_DEVICE_VXLAN_SUPPORT); 551 DEBUG("L2 tunnel checksum offloads are %ssupported", 552 (priv->hw_csum_l2tun ? "" : "not ")); 553 554 priv->ind_table_max_size = exp_device_attr.rx_hash_caps.max_rwq_indirection_table_size; 555 /* Remove this check once DPDK supports larger/variable 556 * indirection tables. */ 557 if (priv->ind_table_max_size > (unsigned int)RSS_INDIRECTION_TABLE_SIZE) 558 priv->ind_table_max_size = RSS_INDIRECTION_TABLE_SIZE; 559 DEBUG("maximum RX indirection table size is %u", 560 priv->ind_table_max_size); 561 priv->hw_vlan_strip = !!(exp_device_attr.wq_vlan_offloads_cap & 562 IBV_EXP_RECEIVE_WQ_CVLAN_STRIP); 563 DEBUG("VLAN stripping is %ssupported", 564 (priv->hw_vlan_strip ? "" : "not ")); 565 566 priv->hw_fcs_strip = !!(exp_device_attr.exp_device_cap_flags & 567 IBV_EXP_DEVICE_SCATTER_FCS); 568 DEBUG("FCS stripping configuration is %ssupported", 569 (priv->hw_fcs_strip ? "" : "not ")); 570 571 priv->hw_padding = !!exp_device_attr.rx_pad_end_addr_align; 572 DEBUG("hardware RX end alignment padding is %ssupported", 573 (priv->hw_padding ? "" : "not ")); 574 575 priv_get_num_vfs(priv, &num_vfs); 576 priv->sriov = (num_vfs || sriov); 577 if (priv->mps && !mps) { 578 ERROR("multi-packet send not supported on this device" 579 " (" MLX5_TXQ_MPW_EN ")"); 580 err = ENOTSUP; 581 goto port_error; 582 } 583 /* Allocate and register default RSS hash keys. */ 584 priv->rss_conf = rte_calloc(__func__, hash_rxq_init_n, 585 sizeof((*priv->rss_conf)[0]), 0); 586 if (priv->rss_conf == NULL) { 587 err = ENOMEM; 588 goto port_error; 589 } 590 err = rss_hash_rss_conf_new_key(priv, 591 rss_hash_default_key, 592 rss_hash_default_key_len, 593 ETH_RSS_PROTO_MASK); 594 if (err) 595 goto port_error; 596 /* Configure the first MAC address by default. */ 597 if (priv_get_mac(priv, &mac.addr_bytes)) { 598 ERROR("cannot get MAC address, is mlx5_en loaded?" 599 " (errno: %s)", strerror(errno)); 600 goto port_error; 601 } 602 INFO("port %u MAC address is %02x:%02x:%02x:%02x:%02x:%02x", 603 priv->port, 604 mac.addr_bytes[0], mac.addr_bytes[1], 605 mac.addr_bytes[2], mac.addr_bytes[3], 606 mac.addr_bytes[4], mac.addr_bytes[5]); 607 /* Register MAC address. */ 608 claim_zero(priv_mac_addr_add(priv, 0, 609 (const uint8_t (*)[ETHER_ADDR_LEN]) 610 mac.addr_bytes)); 611 /* Initialize FD filters list. */ 612 err = fdir_init_filters_list(priv); 613 if (err) 614 goto port_error; 615 #ifndef NDEBUG 616 { 617 char ifname[IF_NAMESIZE]; 618 619 if (priv_get_ifname(priv, &ifname) == 0) 620 DEBUG("port %u ifname is \"%s\"", 621 priv->port, ifname); 622 else 623 DEBUG("port %u ifname is unknown", priv->port); 624 } 625 #endif 626 /* Get actual MTU if possible. */ 627 priv_get_mtu(priv, &priv->mtu); 628 DEBUG("port %u MTU is %u", priv->port, priv->mtu); 629 630 /* from rte_ethdev.c */ 631 { 632 char name[RTE_ETH_NAME_MAX_LEN]; 633 634 snprintf(name, sizeof(name), "%s port %u", 635 ibv_get_device_name(ibv_dev), port); 636 eth_dev = rte_eth_dev_allocate(name); 637 } 638 if (eth_dev == NULL) { 639 ERROR("can not allocate rte ethdev"); 640 err = ENOMEM; 641 goto port_error; 642 } 643 644 /* Secondary processes have to use local storage for their 645 * private data as well as a copy of eth_dev->data, but this 646 * pointer must not be modified before burst functions are 647 * actually called. */ 648 if (mlx5_is_secondary()) { 649 struct mlx5_secondary_data *sd = 650 &mlx5_secondary_data[eth_dev->data->port_id]; 651 sd->primary_priv = eth_dev->data->dev_private; 652 if (sd->primary_priv == NULL) { 653 ERROR("no private data for port %u", 654 eth_dev->data->port_id); 655 err = EINVAL; 656 goto port_error; 657 } 658 sd->shared_dev_data = eth_dev->data; 659 rte_spinlock_init(&sd->lock); 660 memcpy(sd->data.name, sd->shared_dev_data->name, 661 sizeof(sd->data.name)); 662 sd->data.dev_private = priv; 663 sd->data.rx_mbuf_alloc_failed = 0; 664 sd->data.mtu = ETHER_MTU; 665 sd->data.port_id = sd->shared_dev_data->port_id; 666 sd->data.mac_addrs = priv->mac; 667 eth_dev->tx_pkt_burst = mlx5_tx_burst_secondary_setup; 668 eth_dev->rx_pkt_burst = mlx5_rx_burst_secondary_setup; 669 } else { 670 eth_dev->data->dev_private = priv; 671 eth_dev->data->mac_addrs = priv->mac; 672 } 673 674 eth_dev->device = &pci_dev->device; 675 rte_eth_copy_pci_info(eth_dev, pci_dev); 676 eth_dev->driver = &mlx5_driver; 677 priv->dev = eth_dev; 678 eth_dev->dev_ops = &mlx5_dev_ops; 679 680 /* Bring Ethernet device up. */ 681 DEBUG("forcing Ethernet interface up"); 682 priv_set_flags(priv, ~IFF_UP, IFF_UP); 683 mlx5_link_update(priv->dev, 1); 684 continue; 685 686 port_error: 687 if (priv) { 688 rte_free(priv->rss_conf); 689 rte_free(priv); 690 } 691 if (pd) 692 claim_zero(ibv_dealloc_pd(pd)); 693 if (ctx) 694 claim_zero(ibv_close_device(ctx)); 695 break; 696 } 697 698 /* 699 * XXX if something went wrong in the loop above, there is a resource 700 * leak (ctx, pd, priv, dpdk ethdev) but we can do nothing about it as 701 * long as the dpdk does not provide a way to deallocate a ethdev and a 702 * way to enumerate the registered ethdevs to free the previous ones. 703 */ 704 705 /* no port found, complain */ 706 if (!mlx5_dev[idx].ports) { 707 err = ENODEV; 708 goto error; 709 } 710 711 error: 712 if (attr_ctx) 713 claim_zero(ibv_close_device(attr_ctx)); 714 if (list) 715 ibv_free_device_list(list); 716 assert(err >= 0); 717 return -err; 718 } 719 720 static const struct rte_pci_id mlx5_pci_id_map[] = { 721 { 722 RTE_PCI_DEVICE(PCI_VENDOR_ID_MELLANOX, 723 PCI_DEVICE_ID_MELLANOX_CONNECTX4) 724 }, 725 { 726 RTE_PCI_DEVICE(PCI_VENDOR_ID_MELLANOX, 727 PCI_DEVICE_ID_MELLANOX_CONNECTX4VF) 728 }, 729 { 730 RTE_PCI_DEVICE(PCI_VENDOR_ID_MELLANOX, 731 PCI_DEVICE_ID_MELLANOX_CONNECTX4LX) 732 }, 733 { 734 RTE_PCI_DEVICE(PCI_VENDOR_ID_MELLANOX, 735 PCI_DEVICE_ID_MELLANOX_CONNECTX4LXVF) 736 }, 737 { 738 RTE_PCI_DEVICE(PCI_VENDOR_ID_MELLANOX, 739 PCI_DEVICE_ID_MELLANOX_CONNECTX5) 740 }, 741 { 742 RTE_PCI_DEVICE(PCI_VENDOR_ID_MELLANOX, 743 PCI_DEVICE_ID_MELLANOX_CONNECTX5VF) 744 }, 745 { 746 RTE_PCI_DEVICE(PCI_VENDOR_ID_MELLANOX, 747 PCI_DEVICE_ID_MELLANOX_CONNECTX5EX) 748 }, 749 { 750 RTE_PCI_DEVICE(PCI_VENDOR_ID_MELLANOX, 751 PCI_DEVICE_ID_MELLANOX_CONNECTX5EXVF) 752 }, 753 { 754 .vendor_id = 0 755 } 756 }; 757 758 static struct eth_driver mlx5_driver = { 759 .pci_drv = { 760 .driver = { 761 .name = MLX5_DRIVER_NAME 762 }, 763 .id_table = mlx5_pci_id_map, 764 .probe = mlx5_pci_probe, 765 .drv_flags = RTE_PCI_DRV_INTR_LSC, 766 }, 767 .dev_private_size = sizeof(struct priv) 768 }; 769 770 /** 771 * Driver initialization routine. 772 */ 773 RTE_INIT(rte_mlx5_pmd_init); 774 static void 775 rte_mlx5_pmd_init(void) 776 { 777 /* 778 * RDMAV_HUGEPAGES_SAFE tells ibv_fork_init() we intend to use 779 * huge pages. Calling ibv_fork_init() during init allows 780 * applications to use fork() safely for purposes other than 781 * using this PMD, which is not supported in forked processes. 782 */ 783 setenv("RDMAV_HUGEPAGES_SAFE", "1", 1); 784 ibv_fork_init(); 785 rte_eal_pci_register(&mlx5_driver.pci_drv); 786 } 787 788 RTE_PMD_EXPORT_NAME(net_mlx5, __COUNTER__); 789 RTE_PMD_REGISTER_PCI_TABLE(net_mlx5, mlx5_pci_id_map); 790 RTE_PMD_REGISTER_KMOD_DEP(net_mlx5, "* ib_uverbs & mlx5_core & mlx5_ib"); 791