1 /*- 2 * BSD LICENSE 3 * 4 * Copyright 2015 6WIND S.A. 5 * Copyright 2015 Mellanox. 6 * 7 * Redistribution and use in source and binary forms, with or without 8 * modification, are permitted provided that the following conditions 9 * are met: 10 * 11 * * Redistributions of source code must retain the above copyright 12 * notice, this list of conditions and the following disclaimer. 13 * * Redistributions in binary form must reproduce the above copyright 14 * notice, this list of conditions and the following disclaimer in 15 * the documentation and/or other materials provided with the 16 * distribution. 17 * * Neither the name of 6WIND S.A. nor the names of its 18 * contributors may be used to endorse or promote products derived 19 * from this software without specific prior written permission. 20 * 21 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 22 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 23 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 24 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 25 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 26 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 27 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 28 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 29 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 30 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 31 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 32 */ 33 34 #include <stddef.h> 35 #include <unistd.h> 36 #include <string.h> 37 #include <assert.h> 38 #include <stdint.h> 39 #include <stdlib.h> 40 #include <errno.h> 41 #include <net/if.h> 42 43 /* Verbs header. */ 44 /* ISO C doesn't support unnamed structs/unions, disabling -pedantic. */ 45 #ifdef PEDANTIC 46 #pragma GCC diagnostic ignored "-Wpedantic" 47 #endif 48 #include <infiniband/verbs.h> 49 #ifdef PEDANTIC 50 #pragma GCC diagnostic error "-Wpedantic" 51 #endif 52 53 /* DPDK headers don't like -pedantic. */ 54 #ifdef PEDANTIC 55 #pragma GCC diagnostic ignored "-Wpedantic" 56 #endif 57 #include <rte_malloc.h> 58 #include <rte_ethdev.h> 59 #include <rte_pci.h> 60 #include <rte_common.h> 61 #include <rte_kvargs.h> 62 #ifdef PEDANTIC 63 #pragma GCC diagnostic error "-Wpedantic" 64 #endif 65 66 #include "mlx5.h" 67 #include "mlx5_utils.h" 68 #include "mlx5_rxtx.h" 69 #include "mlx5_autoconf.h" 70 #include "mlx5_defs.h" 71 72 /* Device parameter to enable RX completion queue compression. */ 73 #define MLX5_RXQ_CQE_COMP_EN "rxq_cqe_comp_en" 74 75 /* Device parameter to configure inline send. */ 76 #define MLX5_TXQ_INLINE "txq_inline" 77 78 /* 79 * Device parameter to configure the number of TX queues threshold for 80 * enabling inline send. 81 */ 82 #define MLX5_TXQS_MIN_INLINE "txqs_min_inline" 83 84 /* Device parameter to enable multi-packet send WQEs. */ 85 #define MLX5_TXQ_MPW_EN "txq_mpw_en" 86 87 /* Device parameter to include 2 dsegs in the title WQEBB. */ 88 #define MLX5_TXQ_MPW_HDR_DSEG_EN "txq_mpw_hdr_dseg_en" 89 90 /* Device parameter to limit the size of inlining packet. */ 91 #define MLX5_TXQ_MAX_INLINE_LEN "txq_max_inline_len" 92 93 /* Device parameter to enable hardware TSO offload. */ 94 #define MLX5_TSO "tso" 95 96 /** 97 * Retrieve integer value from environment variable. 98 * 99 * @param[in] name 100 * Environment variable name. 101 * 102 * @return 103 * Integer value, 0 if the variable is not set. 104 */ 105 int 106 mlx5_getenv_int(const char *name) 107 { 108 const char *val = getenv(name); 109 110 if (val == NULL) 111 return 0; 112 return atoi(val); 113 } 114 115 /** 116 * DPDK callback to close the device. 117 * 118 * Destroy all queues and objects, free memory. 119 * 120 * @param dev 121 * Pointer to Ethernet device structure. 122 */ 123 static void 124 mlx5_dev_close(struct rte_eth_dev *dev) 125 { 126 struct priv *priv = mlx5_get_priv(dev); 127 unsigned int i; 128 129 priv_lock(priv); 130 DEBUG("%p: closing device \"%s\"", 131 (void *)dev, 132 ((priv->ctx != NULL) ? priv->ctx->device->name : "")); 133 /* In case mlx5_dev_stop() has not been called. */ 134 priv_dev_interrupt_handler_uninstall(priv, dev); 135 priv_special_flow_disable_all(priv); 136 priv_mac_addrs_disable(priv); 137 priv_destroy_hash_rxqs(priv); 138 139 /* Remove flow director elements. */ 140 priv_fdir_disable(priv); 141 priv_fdir_delete_filters_list(priv); 142 143 /* Prevent crashes when queues are still in use. */ 144 dev->rx_pkt_burst = removed_rx_burst; 145 dev->tx_pkt_burst = removed_tx_burst; 146 if (priv->rxqs != NULL) { 147 /* XXX race condition if mlx5_rx_burst() is still running. */ 148 usleep(1000); 149 for (i = 0; (i != priv->rxqs_n); ++i) { 150 struct rxq *rxq = (*priv->rxqs)[i]; 151 struct rxq_ctrl *rxq_ctrl; 152 153 if (rxq == NULL) 154 continue; 155 rxq_ctrl = container_of(rxq, struct rxq_ctrl, rxq); 156 (*priv->rxqs)[i] = NULL; 157 rxq_cleanup(rxq_ctrl); 158 rte_free(rxq_ctrl); 159 } 160 priv->rxqs_n = 0; 161 priv->rxqs = NULL; 162 } 163 if (priv->txqs != NULL) { 164 /* XXX race condition if mlx5_tx_burst() is still running. */ 165 usleep(1000); 166 for (i = 0; (i != priv->txqs_n); ++i) { 167 struct txq *txq = (*priv->txqs)[i]; 168 struct txq_ctrl *txq_ctrl; 169 170 if (txq == NULL) 171 continue; 172 txq_ctrl = container_of(txq, struct txq_ctrl, txq); 173 (*priv->txqs)[i] = NULL; 174 txq_cleanup(txq_ctrl); 175 rte_free(txq_ctrl); 176 } 177 priv->txqs_n = 0; 178 priv->txqs = NULL; 179 } 180 if (priv->pd != NULL) { 181 assert(priv->ctx != NULL); 182 claim_zero(ibv_dealloc_pd(priv->pd)); 183 claim_zero(ibv_close_device(priv->ctx)); 184 } else 185 assert(priv->ctx == NULL); 186 if (priv->rss_conf != NULL) { 187 for (i = 0; (i != hash_rxq_init_n); ++i) 188 rte_free((*priv->rss_conf)[i]); 189 rte_free(priv->rss_conf); 190 } 191 if (priv->reta_idx != NULL) 192 rte_free(priv->reta_idx); 193 priv_unlock(priv); 194 memset(priv, 0, sizeof(*priv)); 195 } 196 197 static const struct eth_dev_ops mlx5_dev_ops = { 198 .dev_configure = mlx5_dev_configure, 199 .dev_start = mlx5_dev_start, 200 .dev_stop = mlx5_dev_stop, 201 .dev_set_link_down = mlx5_set_link_down, 202 .dev_set_link_up = mlx5_set_link_up, 203 .dev_close = mlx5_dev_close, 204 .promiscuous_enable = mlx5_promiscuous_enable, 205 .promiscuous_disable = mlx5_promiscuous_disable, 206 .allmulticast_enable = mlx5_allmulticast_enable, 207 .allmulticast_disable = mlx5_allmulticast_disable, 208 .link_update = mlx5_link_update, 209 .stats_get = mlx5_stats_get, 210 .stats_reset = mlx5_stats_reset, 211 .xstats_get = mlx5_xstats_get, 212 .xstats_reset = mlx5_xstats_reset, 213 .xstats_get_names = mlx5_xstats_get_names, 214 .dev_infos_get = mlx5_dev_infos_get, 215 .dev_supported_ptypes_get = mlx5_dev_supported_ptypes_get, 216 .vlan_filter_set = mlx5_vlan_filter_set, 217 .rx_queue_setup = mlx5_rx_queue_setup, 218 .tx_queue_setup = mlx5_tx_queue_setup, 219 .rx_queue_release = mlx5_rx_queue_release, 220 .tx_queue_release = mlx5_tx_queue_release, 221 .flow_ctrl_get = mlx5_dev_get_flow_ctrl, 222 .flow_ctrl_set = mlx5_dev_set_flow_ctrl, 223 .mac_addr_remove = mlx5_mac_addr_remove, 224 .mac_addr_add = mlx5_mac_addr_add, 225 .mac_addr_set = mlx5_mac_addr_set, 226 .mtu_set = mlx5_dev_set_mtu, 227 .vlan_strip_queue_set = mlx5_vlan_strip_queue_set, 228 .vlan_offload_set = mlx5_vlan_offload_set, 229 .reta_update = mlx5_dev_rss_reta_update, 230 .reta_query = mlx5_dev_rss_reta_query, 231 .rss_hash_update = mlx5_rss_hash_update, 232 .rss_hash_conf_get = mlx5_rss_hash_conf_get, 233 .filter_ctrl = mlx5_dev_filter_ctrl, 234 .rx_descriptor_status = mlx5_rx_descriptor_status, 235 .tx_descriptor_status = mlx5_tx_descriptor_status, 236 .rx_queue_intr_enable = mlx5_rx_intr_enable, 237 .rx_queue_intr_disable = mlx5_rx_intr_disable, 238 }; 239 240 static struct { 241 struct rte_pci_addr pci_addr; /* associated PCI address */ 242 uint32_t ports; /* physical ports bitfield. */ 243 } mlx5_dev[32]; 244 245 /** 246 * Get device index in mlx5_dev[] from PCI bus address. 247 * 248 * @param[in] pci_addr 249 * PCI bus address to look for. 250 * 251 * @return 252 * mlx5_dev[] index on success, -1 on failure. 253 */ 254 static int 255 mlx5_dev_idx(struct rte_pci_addr *pci_addr) 256 { 257 unsigned int i; 258 int ret = -1; 259 260 assert(pci_addr != NULL); 261 for (i = 0; (i != RTE_DIM(mlx5_dev)); ++i) { 262 if ((mlx5_dev[i].pci_addr.domain == pci_addr->domain) && 263 (mlx5_dev[i].pci_addr.bus == pci_addr->bus) && 264 (mlx5_dev[i].pci_addr.devid == pci_addr->devid) && 265 (mlx5_dev[i].pci_addr.function == pci_addr->function)) 266 return i; 267 if ((mlx5_dev[i].ports == 0) && (ret == -1)) 268 ret = i; 269 } 270 return ret; 271 } 272 273 /** 274 * Verify and store value for device argument. 275 * 276 * @param[in] key 277 * Key argument to verify. 278 * @param[in] val 279 * Value associated with key. 280 * @param opaque 281 * User data. 282 * 283 * @return 284 * 0 on success, negative errno value on failure. 285 */ 286 static int 287 mlx5_args_check(const char *key, const char *val, void *opaque) 288 { 289 struct priv *priv = opaque; 290 unsigned long tmp; 291 292 errno = 0; 293 tmp = strtoul(val, NULL, 0); 294 if (errno) { 295 WARN("%s: \"%s\" is not a valid integer", key, val); 296 return errno; 297 } 298 if (strcmp(MLX5_RXQ_CQE_COMP_EN, key) == 0) { 299 priv->cqe_comp = !!tmp; 300 } else if (strcmp(MLX5_TXQ_INLINE, key) == 0) { 301 priv->txq_inline = tmp; 302 } else if (strcmp(MLX5_TXQS_MIN_INLINE, key) == 0) { 303 priv->txqs_inline = tmp; 304 } else if (strcmp(MLX5_TXQ_MPW_EN, key) == 0) { 305 priv->mps = !!tmp ? priv->mps : MLX5_MPW_DISABLED; 306 } else if (strcmp(MLX5_TXQ_MPW_HDR_DSEG_EN, key) == 0) { 307 priv->mpw_hdr_dseg = !!tmp; 308 } else if (strcmp(MLX5_TXQ_MAX_INLINE_LEN, key) == 0) { 309 priv->inline_max_packet_sz = tmp; 310 } else if (strcmp(MLX5_TSO, key) == 0) { 311 priv->tso = !!tmp; 312 } else { 313 WARN("%s: unknown parameter", key); 314 return -EINVAL; 315 } 316 return 0; 317 } 318 319 /** 320 * Parse device parameters. 321 * 322 * @param priv 323 * Pointer to private structure. 324 * @param devargs 325 * Device arguments structure. 326 * 327 * @return 328 * 0 on success, errno value on failure. 329 */ 330 static int 331 mlx5_args(struct priv *priv, struct rte_devargs *devargs) 332 { 333 const char **params = (const char *[]){ 334 MLX5_RXQ_CQE_COMP_EN, 335 MLX5_TXQ_INLINE, 336 MLX5_TXQS_MIN_INLINE, 337 MLX5_TXQ_MPW_EN, 338 MLX5_TXQ_MPW_HDR_DSEG_EN, 339 MLX5_TXQ_MAX_INLINE_LEN, 340 MLX5_TSO, 341 NULL, 342 }; 343 struct rte_kvargs *kvlist; 344 int ret = 0; 345 int i; 346 347 if (devargs == NULL) 348 return 0; 349 /* Following UGLY cast is done to pass checkpatch. */ 350 kvlist = rte_kvargs_parse(devargs->args, params); 351 if (kvlist == NULL) 352 return 0; 353 /* Process parameters. */ 354 for (i = 0; (params[i] != NULL); ++i) { 355 if (rte_kvargs_count(kvlist, params[i])) { 356 ret = rte_kvargs_process(kvlist, params[i], 357 mlx5_args_check, priv); 358 if (ret != 0) { 359 rte_kvargs_free(kvlist); 360 return ret; 361 } 362 } 363 } 364 rte_kvargs_free(kvlist); 365 return 0; 366 } 367 368 static struct eth_driver mlx5_driver; 369 370 /** 371 * DPDK callback to register a PCI device. 372 * 373 * This function creates an Ethernet device for each port of a given 374 * PCI device. 375 * 376 * @param[in] pci_drv 377 * PCI driver structure (mlx5_driver). 378 * @param[in] pci_dev 379 * PCI device information. 380 * 381 * @return 382 * 0 on success, negative errno value on failure. 383 */ 384 static int 385 mlx5_pci_probe(struct rte_pci_driver *pci_drv, struct rte_pci_device *pci_dev) 386 { 387 struct ibv_device **list; 388 struct ibv_device *ibv_dev; 389 int err = 0; 390 struct ibv_context *attr_ctx = NULL; 391 struct ibv_device_attr device_attr; 392 unsigned int sriov; 393 unsigned int mps; 394 unsigned int tunnel_en; 395 int idx; 396 int i; 397 398 (void)pci_drv; 399 assert(pci_drv == &mlx5_driver.pci_drv); 400 /* Get mlx5_dev[] index. */ 401 idx = mlx5_dev_idx(&pci_dev->addr); 402 if (idx == -1) { 403 ERROR("this driver cannot support any more adapters"); 404 return -ENOMEM; 405 } 406 DEBUG("using driver device index %d", idx); 407 408 /* Save PCI address. */ 409 mlx5_dev[idx].pci_addr = pci_dev->addr; 410 list = ibv_get_device_list(&i); 411 if (list == NULL) { 412 assert(errno); 413 if (errno == ENOSYS) 414 ERROR("cannot list devices, is ib_uverbs loaded?"); 415 return -errno; 416 } 417 assert(i >= 0); 418 /* 419 * For each listed device, check related sysfs entry against 420 * the provided PCI ID. 421 */ 422 while (i != 0) { 423 struct rte_pci_addr pci_addr; 424 425 --i; 426 DEBUG("checking device \"%s\"", list[i]->name); 427 if (mlx5_ibv_device_to_pci_addr(list[i], &pci_addr)) 428 continue; 429 if ((pci_dev->addr.domain != pci_addr.domain) || 430 (pci_dev->addr.bus != pci_addr.bus) || 431 (pci_dev->addr.devid != pci_addr.devid) || 432 (pci_dev->addr.function != pci_addr.function)) 433 continue; 434 sriov = ((pci_dev->id.device_id == 435 PCI_DEVICE_ID_MELLANOX_CONNECTX4VF) || 436 (pci_dev->id.device_id == 437 PCI_DEVICE_ID_MELLANOX_CONNECTX4LXVF) || 438 (pci_dev->id.device_id == 439 PCI_DEVICE_ID_MELLANOX_CONNECTX5VF) || 440 (pci_dev->id.device_id == 441 PCI_DEVICE_ID_MELLANOX_CONNECTX5EXVF)); 442 /* 443 * Multi-packet send is supported by ConnectX-4 Lx PF as well 444 * as all ConnectX-5 devices. 445 */ 446 switch (pci_dev->id.device_id) { 447 case PCI_DEVICE_ID_MELLANOX_CONNECTX4: 448 tunnel_en = 1; 449 mps = MLX5_MPW_DISABLED; 450 break; 451 case PCI_DEVICE_ID_MELLANOX_CONNECTX4LX: 452 mps = MLX5_MPW; 453 break; 454 case PCI_DEVICE_ID_MELLANOX_CONNECTX5: 455 case PCI_DEVICE_ID_MELLANOX_CONNECTX5VF: 456 case PCI_DEVICE_ID_MELLANOX_CONNECTX5EX: 457 case PCI_DEVICE_ID_MELLANOX_CONNECTX5EXVF: 458 tunnel_en = 1; 459 mps = MLX5_MPW_ENHANCED; 460 break; 461 default: 462 mps = MLX5_MPW_DISABLED; 463 } 464 INFO("PCI information matches, using device \"%s\"" 465 " (SR-IOV: %s, %sMPS: %s)", 466 list[i]->name, 467 sriov ? "true" : "false", 468 mps == MLX5_MPW_ENHANCED ? "Enhanced " : "", 469 mps != MLX5_MPW_DISABLED ? "true" : "false"); 470 attr_ctx = ibv_open_device(list[i]); 471 err = errno; 472 break; 473 } 474 if (attr_ctx == NULL) { 475 ibv_free_device_list(list); 476 switch (err) { 477 case 0: 478 ERROR("cannot access device, is mlx5_ib loaded?"); 479 return -ENODEV; 480 case EINVAL: 481 ERROR("cannot use device, are drivers up to date?"); 482 return -EINVAL; 483 } 484 assert(err > 0); 485 return -err; 486 } 487 ibv_dev = list[i]; 488 489 DEBUG("device opened"); 490 if (ibv_query_device(attr_ctx, &device_attr)) 491 goto error; 492 INFO("%u port(s) detected", device_attr.phys_port_cnt); 493 494 for (i = 0; i < device_attr.phys_port_cnt; i++) { 495 uint32_t port = i + 1; /* ports are indexed from one */ 496 uint32_t test = (1 << i); 497 struct ibv_context *ctx = NULL; 498 struct ibv_port_attr port_attr; 499 struct ibv_pd *pd = NULL; 500 struct priv *priv = NULL; 501 struct rte_eth_dev *eth_dev; 502 struct ibv_exp_device_attr exp_device_attr; 503 struct ether_addr mac; 504 uint16_t num_vfs = 0; 505 506 exp_device_attr.comp_mask = 507 IBV_EXP_DEVICE_ATTR_EXP_CAP_FLAGS | 508 IBV_EXP_DEVICE_ATTR_RX_HASH | 509 IBV_EXP_DEVICE_ATTR_VLAN_OFFLOADS | 510 IBV_EXP_DEVICE_ATTR_RX_PAD_END_ALIGN | 511 IBV_EXP_DEVICE_ATTR_TSO_CAPS | 512 0; 513 514 DEBUG("using port %u (%08" PRIx32 ")", port, test); 515 516 ctx = ibv_open_device(ibv_dev); 517 if (ctx == NULL) 518 goto port_error; 519 520 /* Check port status. */ 521 err = ibv_query_port(ctx, port, &port_attr); 522 if (err) { 523 ERROR("port query failed: %s", strerror(err)); 524 goto port_error; 525 } 526 527 if (port_attr.link_layer != IBV_LINK_LAYER_ETHERNET) { 528 ERROR("port %d is not configured in Ethernet mode", 529 port); 530 goto port_error; 531 } 532 533 if (port_attr.state != IBV_PORT_ACTIVE) 534 DEBUG("port %d is not active: \"%s\" (%d)", 535 port, ibv_port_state_str(port_attr.state), 536 port_attr.state); 537 538 /* Allocate protection domain. */ 539 pd = ibv_alloc_pd(ctx); 540 if (pd == NULL) { 541 ERROR("PD allocation failure"); 542 err = ENOMEM; 543 goto port_error; 544 } 545 546 mlx5_dev[idx].ports |= test; 547 548 /* from rte_ethdev.c */ 549 priv = rte_zmalloc("ethdev private structure", 550 sizeof(*priv), 551 RTE_CACHE_LINE_SIZE); 552 if (priv == NULL) { 553 ERROR("priv allocation failure"); 554 err = ENOMEM; 555 goto port_error; 556 } 557 558 priv->ctx = ctx; 559 priv->device_attr = device_attr; 560 priv->port = port; 561 priv->pd = pd; 562 priv->mtu = ETHER_MTU; 563 priv->mps = mps; /* Enable MPW by default if supported. */ 564 /* Set default values for Enhanced MPW, a.k.a MPWv2. */ 565 if (mps == MLX5_MPW_ENHANCED) { 566 priv->mpw_hdr_dseg = 0; 567 priv->txqs_inline = MLX5_EMPW_MIN_TXQS; 568 priv->inline_max_packet_sz = MLX5_EMPW_MAX_INLINE_LEN; 569 priv->txq_inline = MLX5_WQE_SIZE_MAX - MLX5_WQE_SIZE; 570 } 571 priv->cqe_comp = 1; /* Enable compression by default. */ 572 priv->tunnel_en = tunnel_en; 573 err = mlx5_args(priv, pci_dev->device.devargs); 574 if (err) { 575 ERROR("failed to process device arguments: %s", 576 strerror(err)); 577 goto port_error; 578 } 579 if (ibv_exp_query_device(ctx, &exp_device_attr)) { 580 ERROR("ibv_exp_query_device() failed"); 581 goto port_error; 582 } 583 584 priv->hw_csum = 585 ((exp_device_attr.exp_device_cap_flags & 586 IBV_EXP_DEVICE_RX_CSUM_TCP_UDP_PKT) && 587 (exp_device_attr.exp_device_cap_flags & 588 IBV_EXP_DEVICE_RX_CSUM_IP_PKT)); 589 DEBUG("checksum offloading is %ssupported", 590 (priv->hw_csum ? "" : "not ")); 591 592 priv->hw_csum_l2tun = !!(exp_device_attr.exp_device_cap_flags & 593 IBV_EXP_DEVICE_VXLAN_SUPPORT); 594 DEBUG("L2 tunnel checksum offloads are %ssupported", 595 (priv->hw_csum_l2tun ? "" : "not ")); 596 597 priv->ind_table_max_size = exp_device_attr.rx_hash_caps.max_rwq_indirection_table_size; 598 /* Remove this check once DPDK supports larger/variable 599 * indirection tables. */ 600 if (priv->ind_table_max_size > 601 (unsigned int)ETH_RSS_RETA_SIZE_512) 602 priv->ind_table_max_size = ETH_RSS_RETA_SIZE_512; 603 DEBUG("maximum RX indirection table size is %u", 604 priv->ind_table_max_size); 605 priv->hw_vlan_strip = !!(exp_device_attr.wq_vlan_offloads_cap & 606 IBV_EXP_RECEIVE_WQ_CVLAN_STRIP); 607 DEBUG("VLAN stripping is %ssupported", 608 (priv->hw_vlan_strip ? "" : "not ")); 609 610 priv->hw_fcs_strip = !!(exp_device_attr.exp_device_cap_flags & 611 IBV_EXP_DEVICE_SCATTER_FCS); 612 DEBUG("FCS stripping configuration is %ssupported", 613 (priv->hw_fcs_strip ? "" : "not ")); 614 615 priv->hw_padding = !!exp_device_attr.rx_pad_end_addr_align; 616 DEBUG("hardware RX end alignment padding is %ssupported", 617 (priv->hw_padding ? "" : "not ")); 618 619 priv_get_num_vfs(priv, &num_vfs); 620 priv->sriov = (num_vfs || sriov); 621 priv->tso = ((priv->tso) && 622 (exp_device_attr.tso_caps.max_tso > 0) && 623 (exp_device_attr.tso_caps.supported_qpts & 624 (1 << IBV_QPT_RAW_ETH))); 625 if (priv->tso) 626 priv->max_tso_payload_sz = 627 exp_device_attr.tso_caps.max_tso; 628 if (priv->mps && !mps) { 629 ERROR("multi-packet send not supported on this device" 630 " (" MLX5_TXQ_MPW_EN ")"); 631 err = ENOTSUP; 632 goto port_error; 633 } else if (priv->mps && priv->tso) { 634 WARN("multi-packet send not supported in conjunction " 635 "with TSO. MPS disabled"); 636 priv->mps = 0; 637 } 638 INFO("%sMPS is %s", 639 priv->mps == MLX5_MPW_ENHANCED ? "Enhanced " : "", 640 priv->mps != MLX5_MPW_DISABLED ? "enabled" : "disabled"); 641 /* Allocate and register default RSS hash keys. */ 642 priv->rss_conf = rte_calloc(__func__, hash_rxq_init_n, 643 sizeof((*priv->rss_conf)[0]), 0); 644 if (priv->rss_conf == NULL) { 645 err = ENOMEM; 646 goto port_error; 647 } 648 err = rss_hash_rss_conf_new_key(priv, 649 rss_hash_default_key, 650 rss_hash_default_key_len, 651 ETH_RSS_PROTO_MASK); 652 if (err) 653 goto port_error; 654 /* Configure the first MAC address by default. */ 655 if (priv_get_mac(priv, &mac.addr_bytes)) { 656 ERROR("cannot get MAC address, is mlx5_en loaded?" 657 " (errno: %s)", strerror(errno)); 658 goto port_error; 659 } 660 INFO("port %u MAC address is %02x:%02x:%02x:%02x:%02x:%02x", 661 priv->port, 662 mac.addr_bytes[0], mac.addr_bytes[1], 663 mac.addr_bytes[2], mac.addr_bytes[3], 664 mac.addr_bytes[4], mac.addr_bytes[5]); 665 /* Register MAC address. */ 666 claim_zero(priv_mac_addr_add(priv, 0, 667 (const uint8_t (*)[ETHER_ADDR_LEN]) 668 mac.addr_bytes)); 669 /* Initialize FD filters list. */ 670 err = fdir_init_filters_list(priv); 671 if (err) 672 goto port_error; 673 #ifndef NDEBUG 674 { 675 char ifname[IF_NAMESIZE]; 676 677 if (priv_get_ifname(priv, &ifname) == 0) 678 DEBUG("port %u ifname is \"%s\"", 679 priv->port, ifname); 680 else 681 DEBUG("port %u ifname is unknown", priv->port); 682 } 683 #endif 684 /* Get actual MTU if possible. */ 685 priv_get_mtu(priv, &priv->mtu); 686 DEBUG("port %u MTU is %u", priv->port, priv->mtu); 687 688 /* from rte_ethdev.c */ 689 { 690 char name[RTE_ETH_NAME_MAX_LEN]; 691 692 snprintf(name, sizeof(name), "%s port %u", 693 ibv_get_device_name(ibv_dev), port); 694 eth_dev = rte_eth_dev_allocate(name); 695 } 696 if (eth_dev == NULL) { 697 ERROR("can not allocate rte ethdev"); 698 err = ENOMEM; 699 goto port_error; 700 } 701 702 /* Secondary processes have to use local storage for their 703 * private data as well as a copy of eth_dev->data, but this 704 * pointer must not be modified before burst functions are 705 * actually called. */ 706 if (mlx5_is_secondary()) { 707 struct mlx5_secondary_data *sd = 708 &mlx5_secondary_data[eth_dev->data->port_id]; 709 sd->primary_priv = eth_dev->data->dev_private; 710 if (sd->primary_priv == NULL) { 711 ERROR("no private data for port %u", 712 eth_dev->data->port_id); 713 err = EINVAL; 714 goto port_error; 715 } 716 sd->shared_dev_data = eth_dev->data; 717 rte_spinlock_init(&sd->lock); 718 memcpy(sd->data.name, sd->shared_dev_data->name, 719 sizeof(sd->data.name)); 720 sd->data.dev_private = priv; 721 sd->data.rx_mbuf_alloc_failed = 0; 722 sd->data.mtu = ETHER_MTU; 723 sd->data.port_id = sd->shared_dev_data->port_id; 724 sd->data.mac_addrs = priv->mac; 725 eth_dev->tx_pkt_burst = mlx5_tx_burst_secondary_setup; 726 eth_dev->rx_pkt_burst = mlx5_rx_burst_secondary_setup; 727 } else { 728 eth_dev->data->dev_private = priv; 729 eth_dev->data->mac_addrs = priv->mac; 730 } 731 732 eth_dev->device = &pci_dev->device; 733 rte_eth_copy_pci_info(eth_dev, pci_dev); 734 eth_dev->driver = &mlx5_driver; 735 priv->dev = eth_dev; 736 eth_dev->dev_ops = &mlx5_dev_ops; 737 738 /* Bring Ethernet device up. */ 739 DEBUG("forcing Ethernet interface up"); 740 priv_set_flags(priv, ~IFF_UP, IFF_UP); 741 mlx5_link_update(priv->dev, 1); 742 continue; 743 744 port_error: 745 if (priv) { 746 rte_free(priv->rss_conf); 747 rte_free(priv); 748 } 749 if (pd) 750 claim_zero(ibv_dealloc_pd(pd)); 751 if (ctx) 752 claim_zero(ibv_close_device(ctx)); 753 break; 754 } 755 756 /* 757 * XXX if something went wrong in the loop above, there is a resource 758 * leak (ctx, pd, priv, dpdk ethdev) but we can do nothing about it as 759 * long as the dpdk does not provide a way to deallocate a ethdev and a 760 * way to enumerate the registered ethdevs to free the previous ones. 761 */ 762 763 /* no port found, complain */ 764 if (!mlx5_dev[idx].ports) { 765 err = ENODEV; 766 goto error; 767 } 768 769 error: 770 if (attr_ctx) 771 claim_zero(ibv_close_device(attr_ctx)); 772 if (list) 773 ibv_free_device_list(list); 774 assert(err >= 0); 775 return -err; 776 } 777 778 static const struct rte_pci_id mlx5_pci_id_map[] = { 779 { 780 RTE_PCI_DEVICE(PCI_VENDOR_ID_MELLANOX, 781 PCI_DEVICE_ID_MELLANOX_CONNECTX4) 782 }, 783 { 784 RTE_PCI_DEVICE(PCI_VENDOR_ID_MELLANOX, 785 PCI_DEVICE_ID_MELLANOX_CONNECTX4VF) 786 }, 787 { 788 RTE_PCI_DEVICE(PCI_VENDOR_ID_MELLANOX, 789 PCI_DEVICE_ID_MELLANOX_CONNECTX4LX) 790 }, 791 { 792 RTE_PCI_DEVICE(PCI_VENDOR_ID_MELLANOX, 793 PCI_DEVICE_ID_MELLANOX_CONNECTX4LXVF) 794 }, 795 { 796 RTE_PCI_DEVICE(PCI_VENDOR_ID_MELLANOX, 797 PCI_DEVICE_ID_MELLANOX_CONNECTX5) 798 }, 799 { 800 RTE_PCI_DEVICE(PCI_VENDOR_ID_MELLANOX, 801 PCI_DEVICE_ID_MELLANOX_CONNECTX5VF) 802 }, 803 { 804 RTE_PCI_DEVICE(PCI_VENDOR_ID_MELLANOX, 805 PCI_DEVICE_ID_MELLANOX_CONNECTX5EX) 806 }, 807 { 808 RTE_PCI_DEVICE(PCI_VENDOR_ID_MELLANOX, 809 PCI_DEVICE_ID_MELLANOX_CONNECTX5EXVF) 810 }, 811 { 812 .vendor_id = 0 813 } 814 }; 815 816 static struct eth_driver mlx5_driver = { 817 .pci_drv = { 818 .driver = { 819 .name = MLX5_DRIVER_NAME 820 }, 821 .id_table = mlx5_pci_id_map, 822 .probe = mlx5_pci_probe, 823 .drv_flags = RTE_PCI_DRV_INTR_LSC, 824 }, 825 .dev_private_size = sizeof(struct priv) 826 }; 827 828 /** 829 * Driver initialization routine. 830 */ 831 RTE_INIT(rte_mlx5_pmd_init); 832 static void 833 rte_mlx5_pmd_init(void) 834 { 835 /* 836 * RDMAV_HUGEPAGES_SAFE tells ibv_fork_init() we intend to use 837 * huge pages. Calling ibv_fork_init() during init allows 838 * applications to use fork() safely for purposes other than 839 * using this PMD, which is not supported in forked processes. 840 */ 841 setenv("RDMAV_HUGEPAGES_SAFE", "1", 1); 842 ibv_fork_init(); 843 rte_eal_pci_register(&mlx5_driver.pci_drv); 844 } 845 846 RTE_PMD_EXPORT_NAME(net_mlx5, __COUNTER__); 847 RTE_PMD_REGISTER_PCI_TABLE(net_mlx5, mlx5_pci_id_map); 848 RTE_PMD_REGISTER_KMOD_DEP(net_mlx5, "* ib_uverbs & mlx5_core & mlx5_ib"); 849