xref: /dpdk/drivers/net/mlx5/mlx5.c (revision d1e64fbf6345cc74cd016f8fe152393ed72c39e2)
18fd92a66SOlivier Matz /* SPDX-License-Identifier: BSD-3-Clause
2771fa900SAdrien Mazarguil  * Copyright 2015 6WIND S.A.
35feecc57SShahaf Shuler  * Copyright 2015 Mellanox Technologies, Ltd
4771fa900SAdrien Mazarguil  */
5771fa900SAdrien Mazarguil 
6771fa900SAdrien Mazarguil #include <stddef.h>
7771fa900SAdrien Mazarguil #include <unistd.h>
8771fa900SAdrien Mazarguil #include <string.h>
9771fa900SAdrien Mazarguil #include <assert.h>
1059b91becSAdrien Mazarguil #include <dlfcn.h>
11771fa900SAdrien Mazarguil #include <stdint.h>
12771fa900SAdrien Mazarguil #include <stdlib.h>
13e72dd09bSNélio Laranjeiro #include <errno.h>
14771fa900SAdrien Mazarguil #include <net/if.h>
154a984153SXueming Li #include <sys/mman.h>
16ccdcba53SNélio Laranjeiro #include <linux/rtnetlink.h>
17771fa900SAdrien Mazarguil 
18771fa900SAdrien Mazarguil /* Verbs header. */
19771fa900SAdrien Mazarguil /* ISO C doesn't support unnamed structs/unions, disabling -pedantic. */
20771fa900SAdrien Mazarguil #ifdef PEDANTIC
21fc5b160fSBruce Richardson #pragma GCC diagnostic ignored "-Wpedantic"
22771fa900SAdrien Mazarguil #endif
23771fa900SAdrien Mazarguil #include <infiniband/verbs.h>
24771fa900SAdrien Mazarguil #ifdef PEDANTIC
25fc5b160fSBruce Richardson #pragma GCC diagnostic error "-Wpedantic"
26771fa900SAdrien Mazarguil #endif
27771fa900SAdrien Mazarguil 
28771fa900SAdrien Mazarguil #include <rte_malloc.h>
29ffc905f3SFerruh Yigit #include <rte_ethdev_driver.h>
30fdf91e0fSJan Blunck #include <rte_ethdev_pci.h>
31771fa900SAdrien Mazarguil #include <rte_pci.h>
32c752998bSGaetan Rivet #include <rte_bus_pci.h>
33771fa900SAdrien Mazarguil #include <rte_common.h>
3459b91becSAdrien Mazarguil #include <rte_config.h>
354a984153SXueming Li #include <rte_eal_memconfig.h>
36e72dd09bSNélio Laranjeiro #include <rte_kvargs.h>
37e89c15b6SAdrien Mazarguil #include <rte_rwlock.h>
38e89c15b6SAdrien Mazarguil #include <rte_spinlock.h>
39f38c5457SAdrien Mazarguil #include <rte_string_fns.h>
40771fa900SAdrien Mazarguil 
41771fa900SAdrien Mazarguil #include "mlx5.h"
42771fa900SAdrien Mazarguil #include "mlx5_utils.h"
432e22920bSAdrien Mazarguil #include "mlx5_rxtx.h"
44771fa900SAdrien Mazarguil #include "mlx5_autoconf.h"
4513d57bd5SAdrien Mazarguil #include "mlx5_defs.h"
460e83b8e5SNelio Laranjeiro #include "mlx5_glue.h"
47974f1e7eSYongseok Koh #include "mlx5_mr.h"
4884c406e7SOri Kam #include "mlx5_flow.h"
49771fa900SAdrien Mazarguil 
5099c12dccSNélio Laranjeiro /* Device parameter to enable RX completion queue compression. */
5199c12dccSNélio Laranjeiro #define MLX5_RXQ_CQE_COMP_EN "rxq_cqe_comp_en"
5299c12dccSNélio Laranjeiro 
53bc91e8dbSYongseok Koh /* Device parameter to enable RX completion entry padding to 128B. */
54bc91e8dbSYongseok Koh #define MLX5_RXQ_CQE_PAD_EN "rxq_cqe_pad_en"
55bc91e8dbSYongseok Koh 
5678c7a16dSYongseok Koh /* Device parameter to enable padding Rx packet to cacheline size. */
5778c7a16dSYongseok Koh #define MLX5_RXQ_PKT_PAD_EN "rxq_pkt_pad_en"
5878c7a16dSYongseok Koh 
597d6bf6b8SYongseok Koh /* Device parameter to enable Multi-Packet Rx queue. */
607d6bf6b8SYongseok Koh #define MLX5_RX_MPRQ_EN "mprq_en"
617d6bf6b8SYongseok Koh 
627d6bf6b8SYongseok Koh /* Device parameter to configure log 2 of the number of strides for MPRQ. */
637d6bf6b8SYongseok Koh #define MLX5_RX_MPRQ_LOG_STRIDE_NUM "mprq_log_stride_num"
647d6bf6b8SYongseok Koh 
657d6bf6b8SYongseok Koh /* Device parameter to limit the size of memcpy'd packet for MPRQ. */
667d6bf6b8SYongseok Koh #define MLX5_RX_MPRQ_MAX_MEMCPY_LEN "mprq_max_memcpy_len"
677d6bf6b8SYongseok Koh 
687d6bf6b8SYongseok Koh /* Device parameter to set the minimum number of Rx queues to enable MPRQ. */
697d6bf6b8SYongseok Koh #define MLX5_RXQS_MIN_MPRQ "rxqs_min_mprq"
707d6bf6b8SYongseok Koh 
712a66cf37SYaacov Hazan /* Device parameter to configure inline send. */
722a66cf37SYaacov Hazan #define MLX5_TXQ_INLINE "txq_inline"
732a66cf37SYaacov Hazan 
742a66cf37SYaacov Hazan /*
752a66cf37SYaacov Hazan  * Device parameter to configure the number of TX queues threshold for
762a66cf37SYaacov Hazan  * enabling inline send.
772a66cf37SYaacov Hazan  */
782a66cf37SYaacov Hazan #define MLX5_TXQS_MIN_INLINE "txqs_min_inline"
792a66cf37SYaacov Hazan 
8009d8b416SYongseok Koh /*
8109d8b416SYongseok Koh  * Device parameter to configure the number of TX queues threshold for
8209d8b416SYongseok Koh  * enabling vectorized Tx.
8309d8b416SYongseok Koh  */
8409d8b416SYongseok Koh #define MLX5_TXQS_MAX_VEC "txqs_max_vec"
8509d8b416SYongseok Koh 
86230189d9SNélio Laranjeiro /* Device parameter to enable multi-packet send WQEs. */
87230189d9SNélio Laranjeiro #define MLX5_TXQ_MPW_EN "txq_mpw_en"
88230189d9SNélio Laranjeiro 
896ce84bd8SYongseok Koh /* Device parameter to include 2 dsegs in the title WQEBB. */
906ce84bd8SYongseok Koh #define MLX5_TXQ_MPW_HDR_DSEG_EN "txq_mpw_hdr_dseg_en"
916ce84bd8SYongseok Koh 
926ce84bd8SYongseok Koh /* Device parameter to limit the size of inlining packet. */
936ce84bd8SYongseok Koh #define MLX5_TXQ_MAX_INLINE_LEN "txq_max_inline_len"
946ce84bd8SYongseok Koh 
955644d5b9SNelio Laranjeiro /* Device parameter to enable hardware Tx vector. */
965644d5b9SNelio Laranjeiro #define MLX5_TX_VEC_EN "tx_vec_en"
975644d5b9SNelio Laranjeiro 
985644d5b9SNelio Laranjeiro /* Device parameter to enable hardware Rx vector. */
995644d5b9SNelio Laranjeiro #define MLX5_RX_VEC_EN "rx_vec_en"
1005644d5b9SNelio Laranjeiro 
10178a54648SXueming Li /* Allow L3 VXLAN flow creation. */
10278a54648SXueming Li #define MLX5_L3_VXLAN_EN "l3_vxlan_en"
10378a54648SXueming Li 
104e2b4925eSOri Kam /* Activate DV E-Switch flow steering. */
105e2b4925eSOri Kam #define MLX5_DV_ESW_EN "dv_esw_en"
106e2b4925eSOri Kam 
10751e72d38SOri Kam /* Activate DV flow steering. */
10851e72d38SOri Kam #define MLX5_DV_FLOW_EN "dv_flow_en"
10951e72d38SOri Kam 
110db209cc3SNélio Laranjeiro /* Activate Netlink support in VF mode. */
111db209cc3SNélio Laranjeiro #define MLX5_VF_NL_EN "vf_nl_en"
112db209cc3SNélio Laranjeiro 
113dceb5029SYongseok Koh /* Enable extending memsegs when creating a MR. */
114dceb5029SYongseok Koh #define MLX5_MR_EXT_MEMSEG_EN "mr_ext_memseg_en"
115dceb5029SYongseok Koh 
1166de569f5SAdrien Mazarguil /* Select port representors to instantiate. */
1176de569f5SAdrien Mazarguil #define MLX5_REPRESENTOR "representor"
1186de569f5SAdrien Mazarguil 
11943e9d979SShachar Beiser #ifndef HAVE_IBV_MLX5_MOD_MPW
12043e9d979SShachar Beiser #define MLX5DV_CONTEXT_FLAGS_MPW_ALLOWED (1 << 2)
12143e9d979SShachar Beiser #define MLX5DV_CONTEXT_FLAGS_ENHANCED_MPW (1 << 3)
12243e9d979SShachar Beiser #endif
12343e9d979SShachar Beiser 
124523f5a74SYongseok Koh #ifndef HAVE_IBV_MLX5_MOD_CQE_128B_COMP
125523f5a74SYongseok Koh #define MLX5DV_CONTEXT_FLAGS_CQE_128B_COMP (1 << 4)
126523f5a74SYongseok Koh #endif
127523f5a74SYongseok Koh 
128974f1e7eSYongseok Koh static const char *MZ_MLX5_PMD_SHARED_DATA = "mlx5_pmd_shared_data";
129974f1e7eSYongseok Koh 
130974f1e7eSYongseok Koh /* Shared memory between primary and secondary processes. */
131974f1e7eSYongseok Koh struct mlx5_shared_data *mlx5_shared_data;
132974f1e7eSYongseok Koh 
133974f1e7eSYongseok Koh /* Spinlock for mlx5_shared_data allocation. */
134974f1e7eSYongseok Koh static rte_spinlock_t mlx5_shared_data_lock = RTE_SPINLOCK_INITIALIZER;
135974f1e7eSYongseok Koh 
1367be600c8SYongseok Koh /* Process local data for secondary processes. */
1377be600c8SYongseok Koh static struct mlx5_local_data mlx5_local_data;
1387be600c8SYongseok Koh 
139a170a30dSNélio Laranjeiro /** Driver-specific log messages type. */
140a170a30dSNélio Laranjeiro int mlx5_logtype;
141a170a30dSNélio Laranjeiro 
142ad74bc61SViacheslav Ovsiienko /** Data associated with devices to spawn. */
143ad74bc61SViacheslav Ovsiienko struct mlx5_dev_spawn_data {
144ad74bc61SViacheslav Ovsiienko 	uint32_t ifindex; /**< Network interface index. */
145ad74bc61SViacheslav Ovsiienko 	uint32_t max_port; /**< IB device maximal port index. */
146ad74bc61SViacheslav Ovsiienko 	uint32_t ibv_port; /**< IB device physical port index. */
147ad74bc61SViacheslav Ovsiienko 	struct mlx5_switch_info info; /**< Switch information. */
148ad74bc61SViacheslav Ovsiienko 	struct ibv_device *ibv_dev; /**< Associated IB device. */
149ad74bc61SViacheslav Ovsiienko 	struct rte_eth_dev *eth_dev; /**< Associated Ethernet device. */
150ab3cffcfSViacheslav Ovsiienko 	struct rte_pci_device *pci_dev; /**< Backend PCI device. */
151ad74bc61SViacheslav Ovsiienko };
152ad74bc61SViacheslav Ovsiienko 
15317e19bc4SViacheslav Ovsiienko static LIST_HEAD(, mlx5_ibv_shared) mlx5_ibv_list = LIST_HEAD_INITIALIZER();
15417e19bc4SViacheslav Ovsiienko static pthread_mutex_t mlx5_ibv_list_mutex = PTHREAD_MUTEX_INITIALIZER;
15517e19bc4SViacheslav Ovsiienko 
15617e19bc4SViacheslav Ovsiienko /**
15717e19bc4SViacheslav Ovsiienko  * Allocate shared IB device context. If there is multiport device the
15817e19bc4SViacheslav Ovsiienko  * master and representors will share this context, if there is single
15917e19bc4SViacheslav Ovsiienko  * port dedicated IB device, the context will be used by only given
16017e19bc4SViacheslav Ovsiienko  * port due to unification.
16117e19bc4SViacheslav Ovsiienko  *
162ae4eb7dcSViacheslav Ovsiienko  * Routine first searches the context for the specified IB device name,
16317e19bc4SViacheslav Ovsiienko  * if found the shared context assumed and reference counter is incremented.
16417e19bc4SViacheslav Ovsiienko  * If no context found the new one is created and initialized with specified
16517e19bc4SViacheslav Ovsiienko  * IB device context and parameters.
16617e19bc4SViacheslav Ovsiienko  *
16717e19bc4SViacheslav Ovsiienko  * @param[in] spawn
16817e19bc4SViacheslav Ovsiienko  *   Pointer to the IB device attributes (name, port, etc).
16917e19bc4SViacheslav Ovsiienko  *
17017e19bc4SViacheslav Ovsiienko  * @return
17117e19bc4SViacheslav Ovsiienko  *   Pointer to mlx5_ibv_shared object on success,
17217e19bc4SViacheslav Ovsiienko  *   otherwise NULL and rte_errno is set.
17317e19bc4SViacheslav Ovsiienko  */
17417e19bc4SViacheslav Ovsiienko static struct mlx5_ibv_shared *
17517e19bc4SViacheslav Ovsiienko mlx5_alloc_shared_ibctx(const struct mlx5_dev_spawn_data *spawn)
17617e19bc4SViacheslav Ovsiienko {
17717e19bc4SViacheslav Ovsiienko 	struct mlx5_ibv_shared *sh;
17817e19bc4SViacheslav Ovsiienko 	int err = 0;
17953e5a82fSViacheslav Ovsiienko 	uint32_t i;
18017e19bc4SViacheslav Ovsiienko 
18117e19bc4SViacheslav Ovsiienko 	assert(spawn);
18217e19bc4SViacheslav Ovsiienko 	/* Secondary process should not create the shared context. */
18317e19bc4SViacheslav Ovsiienko 	assert(rte_eal_process_type() == RTE_PROC_PRIMARY);
18417e19bc4SViacheslav Ovsiienko 	pthread_mutex_lock(&mlx5_ibv_list_mutex);
18517e19bc4SViacheslav Ovsiienko 	/* Search for IB context by device name. */
18617e19bc4SViacheslav Ovsiienko 	LIST_FOREACH(sh, &mlx5_ibv_list, next) {
18717e19bc4SViacheslav Ovsiienko 		if (!strcmp(sh->ibdev_name, spawn->ibv_dev->name)) {
18817e19bc4SViacheslav Ovsiienko 			sh->refcnt++;
18917e19bc4SViacheslav Ovsiienko 			goto exit;
19017e19bc4SViacheslav Ovsiienko 		}
19117e19bc4SViacheslav Ovsiienko 	}
192ae4eb7dcSViacheslav Ovsiienko 	/* No device found, we have to create new shared context. */
19317e19bc4SViacheslav Ovsiienko 	assert(spawn->max_port);
19417e19bc4SViacheslav Ovsiienko 	sh = rte_zmalloc("ethdev shared ib context",
19517e19bc4SViacheslav Ovsiienko 			 sizeof(struct mlx5_ibv_shared) +
19617e19bc4SViacheslav Ovsiienko 			 spawn->max_port *
19717e19bc4SViacheslav Ovsiienko 			 sizeof(struct mlx5_ibv_shared_port),
19817e19bc4SViacheslav Ovsiienko 			 RTE_CACHE_LINE_SIZE);
19917e19bc4SViacheslav Ovsiienko 	if (!sh) {
20017e19bc4SViacheslav Ovsiienko 		DRV_LOG(ERR, "shared context allocation failure");
20117e19bc4SViacheslav Ovsiienko 		rte_errno  = ENOMEM;
20217e19bc4SViacheslav Ovsiienko 		goto exit;
20317e19bc4SViacheslav Ovsiienko 	}
20417e19bc4SViacheslav Ovsiienko 	/* Try to open IB device with DV first, then usual Verbs. */
20517e19bc4SViacheslav Ovsiienko 	errno = 0;
20617e19bc4SViacheslav Ovsiienko 	sh->ctx = mlx5_glue->dv_open_device(spawn->ibv_dev);
20717e19bc4SViacheslav Ovsiienko 	if (sh->ctx) {
20817e19bc4SViacheslav Ovsiienko 		sh->devx = 1;
20917e19bc4SViacheslav Ovsiienko 		DRV_LOG(DEBUG, "DevX is supported");
21017e19bc4SViacheslav Ovsiienko 	} else {
21117e19bc4SViacheslav Ovsiienko 		sh->ctx = mlx5_glue->open_device(spawn->ibv_dev);
21217e19bc4SViacheslav Ovsiienko 		if (!sh->ctx) {
21317e19bc4SViacheslav Ovsiienko 			err = errno ? errno : ENODEV;
21417e19bc4SViacheslav Ovsiienko 			goto error;
21517e19bc4SViacheslav Ovsiienko 		}
21617e19bc4SViacheslav Ovsiienko 		DRV_LOG(DEBUG, "DevX is NOT supported");
21717e19bc4SViacheslav Ovsiienko 	}
21817e19bc4SViacheslav Ovsiienko 	err = mlx5_glue->query_device_ex(sh->ctx, NULL, &sh->device_attr);
21917e19bc4SViacheslav Ovsiienko 	if (err) {
22017e19bc4SViacheslav Ovsiienko 		DRV_LOG(DEBUG, "ibv_query_device_ex() failed");
22117e19bc4SViacheslav Ovsiienko 		goto error;
22217e19bc4SViacheslav Ovsiienko 	}
22317e19bc4SViacheslav Ovsiienko 	sh->refcnt = 1;
22417e19bc4SViacheslav Ovsiienko 	sh->max_port = spawn->max_port;
22517e19bc4SViacheslav Ovsiienko 	strncpy(sh->ibdev_name, sh->ctx->device->name,
22617e19bc4SViacheslav Ovsiienko 		sizeof(sh->ibdev_name));
22717e19bc4SViacheslav Ovsiienko 	strncpy(sh->ibdev_path, sh->ctx->device->ibdev_path,
22817e19bc4SViacheslav Ovsiienko 		sizeof(sh->ibdev_path));
229ab3cffcfSViacheslav Ovsiienko 	sh->pci_dev = spawn->pci_dev;
23053e5a82fSViacheslav Ovsiienko 	pthread_mutex_init(&sh->intr_mutex, NULL);
23153e5a82fSViacheslav Ovsiienko 	/*
23253e5a82fSViacheslav Ovsiienko 	 * Setting port_id to max unallowed value means
23353e5a82fSViacheslav Ovsiienko 	 * there is no interrupt subhandler installed for
23453e5a82fSViacheslav Ovsiienko 	 * the given port index i.
23553e5a82fSViacheslav Ovsiienko 	 */
23653e5a82fSViacheslav Ovsiienko 	for (i = 0; i < sh->max_port; i++)
23753e5a82fSViacheslav Ovsiienko 		sh->port[i].ih_port_id = RTE_MAX_ETHPORTS;
23817e19bc4SViacheslav Ovsiienko 	sh->pd = mlx5_glue->alloc_pd(sh->ctx);
23917e19bc4SViacheslav Ovsiienko 	if (sh->pd == NULL) {
24017e19bc4SViacheslav Ovsiienko 		DRV_LOG(ERR, "PD allocation failure");
24117e19bc4SViacheslav Ovsiienko 		err = ENOMEM;
24217e19bc4SViacheslav Ovsiienko 		goto error;
24317e19bc4SViacheslav Ovsiienko 	}
244ab3cffcfSViacheslav Ovsiienko 	/*
245ab3cffcfSViacheslav Ovsiienko 	 * Once the device is added to the list of memory event
246ab3cffcfSViacheslav Ovsiienko 	 * callback, its global MR cache table cannot be expanded
247ab3cffcfSViacheslav Ovsiienko 	 * on the fly because of deadlock. If it overflows, lookup
248ab3cffcfSViacheslav Ovsiienko 	 * should be done by searching MR list linearly, which is slow.
249ab3cffcfSViacheslav Ovsiienko 	 *
250ab3cffcfSViacheslav Ovsiienko 	 * At this point the device is not added to the memory
251ab3cffcfSViacheslav Ovsiienko 	 * event list yet, context is just being created.
252ab3cffcfSViacheslav Ovsiienko 	 */
253ab3cffcfSViacheslav Ovsiienko 	err = mlx5_mr_btree_init(&sh->mr.cache,
254ab3cffcfSViacheslav Ovsiienko 				 MLX5_MR_BTREE_CACHE_N * 2,
255ab3cffcfSViacheslav Ovsiienko 				 sh->pci_dev->device.numa_node);
256ab3cffcfSViacheslav Ovsiienko 	if (err) {
257ab3cffcfSViacheslav Ovsiienko 		err = rte_errno;
258ab3cffcfSViacheslav Ovsiienko 		goto error;
259ab3cffcfSViacheslav Ovsiienko 	}
26017e19bc4SViacheslav Ovsiienko 	LIST_INSERT_HEAD(&mlx5_ibv_list, sh, next);
26117e19bc4SViacheslav Ovsiienko exit:
26217e19bc4SViacheslav Ovsiienko 	pthread_mutex_unlock(&mlx5_ibv_list_mutex);
26317e19bc4SViacheslav Ovsiienko 	return sh;
26417e19bc4SViacheslav Ovsiienko error:
26517e19bc4SViacheslav Ovsiienko 	pthread_mutex_unlock(&mlx5_ibv_list_mutex);
26617e19bc4SViacheslav Ovsiienko 	assert(sh);
26717e19bc4SViacheslav Ovsiienko 	if (sh->pd)
26817e19bc4SViacheslav Ovsiienko 		claim_zero(mlx5_glue->dealloc_pd(sh->pd));
26917e19bc4SViacheslav Ovsiienko 	if (sh->ctx)
27017e19bc4SViacheslav Ovsiienko 		claim_zero(mlx5_glue->close_device(sh->ctx));
27117e19bc4SViacheslav Ovsiienko 	rte_free(sh);
27217e19bc4SViacheslav Ovsiienko 	assert(err > 0);
27317e19bc4SViacheslav Ovsiienko 	rte_errno = err;
27417e19bc4SViacheslav Ovsiienko 	return NULL;
27517e19bc4SViacheslav Ovsiienko }
27617e19bc4SViacheslav Ovsiienko 
27717e19bc4SViacheslav Ovsiienko /**
27817e19bc4SViacheslav Ovsiienko  * Free shared IB device context. Decrement counter and if zero free
27917e19bc4SViacheslav Ovsiienko  * all allocated resources and close handles.
28017e19bc4SViacheslav Ovsiienko  *
28117e19bc4SViacheslav Ovsiienko  * @param[in] sh
28217e19bc4SViacheslav Ovsiienko  *   Pointer to mlx5_ibv_shared object to free
28317e19bc4SViacheslav Ovsiienko  */
28417e19bc4SViacheslav Ovsiienko static void
28517e19bc4SViacheslav Ovsiienko mlx5_free_shared_ibctx(struct mlx5_ibv_shared *sh)
28617e19bc4SViacheslav Ovsiienko {
28717e19bc4SViacheslav Ovsiienko 	pthread_mutex_lock(&mlx5_ibv_list_mutex);
28817e19bc4SViacheslav Ovsiienko #ifndef NDEBUG
28917e19bc4SViacheslav Ovsiienko 	/* Check the object presence in the list. */
29017e19bc4SViacheslav Ovsiienko 	struct mlx5_ibv_shared *lctx;
29117e19bc4SViacheslav Ovsiienko 
29217e19bc4SViacheslav Ovsiienko 	LIST_FOREACH(lctx, &mlx5_ibv_list, next)
29317e19bc4SViacheslav Ovsiienko 		if (lctx == sh)
29417e19bc4SViacheslav Ovsiienko 			break;
29517e19bc4SViacheslav Ovsiienko 	assert(lctx);
29617e19bc4SViacheslav Ovsiienko 	if (lctx != sh) {
29717e19bc4SViacheslav Ovsiienko 		DRV_LOG(ERR, "Freeing non-existing shared IB context");
29817e19bc4SViacheslav Ovsiienko 		goto exit;
29917e19bc4SViacheslav Ovsiienko 	}
30017e19bc4SViacheslav Ovsiienko #endif
30117e19bc4SViacheslav Ovsiienko 	assert(sh);
30217e19bc4SViacheslav Ovsiienko 	assert(sh->refcnt);
30317e19bc4SViacheslav Ovsiienko 	/* Secondary process should not free the shared context. */
30417e19bc4SViacheslav Ovsiienko 	assert(rte_eal_process_type() == RTE_PROC_PRIMARY);
30517e19bc4SViacheslav Ovsiienko 	if (--sh->refcnt)
30617e19bc4SViacheslav Ovsiienko 		goto exit;
307ab3cffcfSViacheslav Ovsiienko 	/* Release created Memory Regions. */
308ab3cffcfSViacheslav Ovsiienko 	mlx5_mr_release(sh);
30917e19bc4SViacheslav Ovsiienko 	LIST_REMOVE(sh, next);
31053e5a82fSViacheslav Ovsiienko 	/*
31153e5a82fSViacheslav Ovsiienko 	 *  Ensure there is no async event handler installed.
31253e5a82fSViacheslav Ovsiienko 	 *  Only primary process handles async device events.
31353e5a82fSViacheslav Ovsiienko 	 **/
31453e5a82fSViacheslav Ovsiienko 	assert(!sh->intr_cnt);
31553e5a82fSViacheslav Ovsiienko 	if (sh->intr_cnt)
31653e5a82fSViacheslav Ovsiienko 		rte_intr_callback_unregister
31753e5a82fSViacheslav Ovsiienko 			(&sh->intr_handle, mlx5_dev_interrupt_handler, sh);
31853e5a82fSViacheslav Ovsiienko 	pthread_mutex_destroy(&sh->intr_mutex);
31917e19bc4SViacheslav Ovsiienko 	if (sh->pd)
32017e19bc4SViacheslav Ovsiienko 		claim_zero(mlx5_glue->dealloc_pd(sh->pd));
32117e19bc4SViacheslav Ovsiienko 	if (sh->ctx)
32217e19bc4SViacheslav Ovsiienko 		claim_zero(mlx5_glue->close_device(sh->ctx));
32317e19bc4SViacheslav Ovsiienko 	rte_free(sh);
32417e19bc4SViacheslav Ovsiienko exit:
32517e19bc4SViacheslav Ovsiienko 	pthread_mutex_unlock(&mlx5_ibv_list_mutex);
32617e19bc4SViacheslav Ovsiienko }
32717e19bc4SViacheslav Ovsiienko 
328771fa900SAdrien Mazarguil /**
329b2177648SViacheslav Ovsiienko  * Initialize DR related data within private structure.
330b2177648SViacheslav Ovsiienko  * Routine checks the reference counter and does actual
331ae4eb7dcSViacheslav Ovsiienko  * resources creation/initialization only if counter is zero.
332b2177648SViacheslav Ovsiienko  *
333b2177648SViacheslav Ovsiienko  * @param[in] priv
334b2177648SViacheslav Ovsiienko  *   Pointer to the private device data structure.
335b2177648SViacheslav Ovsiienko  *
336b2177648SViacheslav Ovsiienko  * @return
337b2177648SViacheslav Ovsiienko  *   Zero on success, positive error code otherwise.
338b2177648SViacheslav Ovsiienko  */
339b2177648SViacheslav Ovsiienko static int
340b2177648SViacheslav Ovsiienko mlx5_alloc_shared_dr(struct mlx5_priv *priv)
341b2177648SViacheslav Ovsiienko {
342b2177648SViacheslav Ovsiienko #ifdef HAVE_MLX5DV_DR
343b2177648SViacheslav Ovsiienko 	struct mlx5_ibv_shared *sh = priv->sh;
344b2177648SViacheslav Ovsiienko 	int err = 0;
345*d1e64fbfSOri Kam 	void *domain;
346b2177648SViacheslav Ovsiienko 
347b2177648SViacheslav Ovsiienko 	assert(sh);
348b2177648SViacheslav Ovsiienko 	if (sh->dv_refcnt) {
349b2177648SViacheslav Ovsiienko 		/* Shared DV/DR structures is already initialized. */
350b2177648SViacheslav Ovsiienko 		sh->dv_refcnt++;
351b2177648SViacheslav Ovsiienko 		priv->dr_shared = 1;
352b2177648SViacheslav Ovsiienko 		return 0;
353b2177648SViacheslav Ovsiienko 	}
354b2177648SViacheslav Ovsiienko 	/* Reference counter is zero, we should initialize structures. */
355*d1e64fbfSOri Kam 	domain = mlx5_glue->dr_create_domain(sh->ctx,
356*d1e64fbfSOri Kam 					     MLX5DV_DR_DOMAIN_TYPE_NIC_RX);
357*d1e64fbfSOri Kam 	if (!domain) {
358*d1e64fbfSOri Kam 		DRV_LOG(ERR, "ingress mlx5dv_dr_create_domain failed");
359b2177648SViacheslav Ovsiienko 		err = errno;
360b2177648SViacheslav Ovsiienko 		goto error;
361b2177648SViacheslav Ovsiienko 	}
362*d1e64fbfSOri Kam 	sh->rx_domain = domain;
363*d1e64fbfSOri Kam 	domain = mlx5_glue->dr_create_domain(sh->ctx,
364*d1e64fbfSOri Kam 					     MLX5DV_DR_DOMAIN_TYPE_NIC_TX);
365*d1e64fbfSOri Kam 	if (!domain) {
366*d1e64fbfSOri Kam 		DRV_LOG(ERR, "egress mlx5dv_dr_create_domain failed");
367b2177648SViacheslav Ovsiienko 		err = errno;
368b2177648SViacheslav Ovsiienko 		goto error;
369b2177648SViacheslav Ovsiienko 	}
37079e35d0dSViacheslav Ovsiienko 	pthread_mutex_init(&sh->dv_mutex, NULL);
371*d1e64fbfSOri Kam 	sh->tx_domain = domain;
372e2b4925eSOri Kam #ifdef HAVE_MLX5DV_DR_ESWITCH
373e2b4925eSOri Kam 	if (priv->config.dv_esw_en) {
374*d1e64fbfSOri Kam 		domain  = mlx5_glue->dr_create_domain
375*d1e64fbfSOri Kam 			(sh->ctx, MLX5DV_DR_DOMAIN_TYPE_FDB);
376*d1e64fbfSOri Kam 		if (!domain) {
377*d1e64fbfSOri Kam 			DRV_LOG(ERR, "FDB mlx5dv_dr_create_domain failed");
378e2b4925eSOri Kam 			err = errno;
379e2b4925eSOri Kam 			goto error;
380e2b4925eSOri Kam 		}
381*d1e64fbfSOri Kam 		sh->fdb_domain = domain;
38234fa7c02SOri Kam 		sh->esw_drop_action = mlx5_glue->dr_create_flow_action_drop();
383e2b4925eSOri Kam 	}
384e2b4925eSOri Kam #endif
385b2177648SViacheslav Ovsiienko 	sh->dv_refcnt++;
386b2177648SViacheslav Ovsiienko 	priv->dr_shared = 1;
387b2177648SViacheslav Ovsiienko 	return 0;
388b2177648SViacheslav Ovsiienko 
389b2177648SViacheslav Ovsiienko error:
390b2177648SViacheslav Ovsiienko        /* Rollback the created objects. */
391*d1e64fbfSOri Kam 	if (sh->rx_domain) {
392*d1e64fbfSOri Kam 		mlx5_glue->dr_destroy_domain(sh->rx_domain);
393*d1e64fbfSOri Kam 		sh->rx_domain = NULL;
394b2177648SViacheslav Ovsiienko 	}
395*d1e64fbfSOri Kam 	if (sh->tx_domain) {
396*d1e64fbfSOri Kam 		mlx5_glue->dr_destroy_domain(sh->tx_domain);
397*d1e64fbfSOri Kam 		sh->tx_domain = NULL;
398b2177648SViacheslav Ovsiienko 	}
399*d1e64fbfSOri Kam 	if (sh->fdb_domain) {
400*d1e64fbfSOri Kam 		mlx5_glue->dr_destroy_domain(sh->fdb_domain);
401*d1e64fbfSOri Kam 		sh->fdb_domain = NULL;
402e2b4925eSOri Kam 	}
40334fa7c02SOri Kam 	if (sh->esw_drop_action) {
40434fa7c02SOri Kam 		mlx5_glue->destroy_flow_action(sh->esw_drop_action);
40534fa7c02SOri Kam 		sh->esw_drop_action = NULL;
40634fa7c02SOri Kam 	}
407b2177648SViacheslav Ovsiienko 	return err;
408b2177648SViacheslav Ovsiienko #else
409b2177648SViacheslav Ovsiienko 	(void)priv;
410b2177648SViacheslav Ovsiienko 	return 0;
411b2177648SViacheslav Ovsiienko #endif
412b2177648SViacheslav Ovsiienko }
413b2177648SViacheslav Ovsiienko 
414b2177648SViacheslav Ovsiienko /**
415b2177648SViacheslav Ovsiienko  * Destroy DR related data within private structure.
416b2177648SViacheslav Ovsiienko  *
417b2177648SViacheslav Ovsiienko  * @param[in] priv
418b2177648SViacheslav Ovsiienko  *   Pointer to the private device data structure.
419b2177648SViacheslav Ovsiienko  */
420b2177648SViacheslav Ovsiienko static void
421b2177648SViacheslav Ovsiienko mlx5_free_shared_dr(struct mlx5_priv *priv)
422b2177648SViacheslav Ovsiienko {
423b2177648SViacheslav Ovsiienko #ifdef HAVE_MLX5DV_DR
424b2177648SViacheslav Ovsiienko 	struct mlx5_ibv_shared *sh;
425b2177648SViacheslav Ovsiienko 
426b2177648SViacheslav Ovsiienko 	if (!priv->dr_shared)
427b2177648SViacheslav Ovsiienko 		return;
428b2177648SViacheslav Ovsiienko 	priv->dr_shared = 0;
429b2177648SViacheslav Ovsiienko 	sh = priv->sh;
430b2177648SViacheslav Ovsiienko 	assert(sh);
431b2177648SViacheslav Ovsiienko 	assert(sh->dv_refcnt);
432b2177648SViacheslav Ovsiienko 	if (sh->dv_refcnt && --sh->dv_refcnt)
433b2177648SViacheslav Ovsiienko 		return;
434*d1e64fbfSOri Kam 	if (sh->rx_domain) {
435*d1e64fbfSOri Kam 		mlx5_glue->dr_destroy_domain(sh->rx_domain);
436*d1e64fbfSOri Kam 		sh->rx_domain = NULL;
437b2177648SViacheslav Ovsiienko 	}
438*d1e64fbfSOri Kam 	if (sh->tx_domain) {
439*d1e64fbfSOri Kam 		mlx5_glue->dr_destroy_domain(sh->tx_domain);
440*d1e64fbfSOri Kam 		sh->tx_domain = NULL;
441b2177648SViacheslav Ovsiienko 	}
442e2b4925eSOri Kam #ifdef HAVE_MLX5DV_DR_ESWITCH
443*d1e64fbfSOri Kam 	if (sh->fdb_domain) {
444*d1e64fbfSOri Kam 		mlx5_glue->dr_destroy_domain(sh->fdb_domain);
445*d1e64fbfSOri Kam 		sh->fdb_domain = NULL;
446e2b4925eSOri Kam 	}
44734fa7c02SOri Kam 	if (sh->esw_drop_action) {
44834fa7c02SOri Kam 		mlx5_glue->destroy_flow_action(sh->esw_drop_action);
44934fa7c02SOri Kam 		sh->esw_drop_action = NULL;
45034fa7c02SOri Kam 	}
451e2b4925eSOri Kam #endif
45279e35d0dSViacheslav Ovsiienko 	pthread_mutex_destroy(&sh->dv_mutex);
453b2177648SViacheslav Ovsiienko #else
454b2177648SViacheslav Ovsiienko 	(void)priv;
455b2177648SViacheslav Ovsiienko #endif
456b2177648SViacheslav Ovsiienko }
457b2177648SViacheslav Ovsiienko 
458b2177648SViacheslav Ovsiienko /**
4597be600c8SYongseok Koh  * Initialize shared data between primary and secondary process.
4607be600c8SYongseok Koh  *
4617be600c8SYongseok Koh  * A memzone is reserved by primary process and secondary processes attach to
4627be600c8SYongseok Koh  * the memzone.
4637be600c8SYongseok Koh  *
4647be600c8SYongseok Koh  * @return
4657be600c8SYongseok Koh  *   0 on success, a negative errno value otherwise and rte_errno is set.
466974f1e7eSYongseok Koh  */
4677be600c8SYongseok Koh static int
4687be600c8SYongseok Koh mlx5_init_shared_data(void)
469974f1e7eSYongseok Koh {
470974f1e7eSYongseok Koh 	const struct rte_memzone *mz;
4717be600c8SYongseok Koh 	int ret = 0;
472974f1e7eSYongseok Koh 
473974f1e7eSYongseok Koh 	rte_spinlock_lock(&mlx5_shared_data_lock);
474974f1e7eSYongseok Koh 	if (mlx5_shared_data == NULL) {
475974f1e7eSYongseok Koh 		if (rte_eal_process_type() == RTE_PROC_PRIMARY) {
476974f1e7eSYongseok Koh 			/* Allocate shared memory. */
477974f1e7eSYongseok Koh 			mz = rte_memzone_reserve(MZ_MLX5_PMD_SHARED_DATA,
478974f1e7eSYongseok Koh 						 sizeof(*mlx5_shared_data),
479974f1e7eSYongseok Koh 						 SOCKET_ID_ANY, 0);
4807be600c8SYongseok Koh 			if (mz == NULL) {
4817be600c8SYongseok Koh 				DRV_LOG(ERR,
4827be600c8SYongseok Koh 					"Cannot allocate mlx5 shared data\n");
4837be600c8SYongseok Koh 				ret = -rte_errno;
4847be600c8SYongseok Koh 				goto error;
4857be600c8SYongseok Koh 			}
4867be600c8SYongseok Koh 			mlx5_shared_data = mz->addr;
4877be600c8SYongseok Koh 			memset(mlx5_shared_data, 0, sizeof(*mlx5_shared_data));
4887be600c8SYongseok Koh 			rte_spinlock_init(&mlx5_shared_data->lock);
489974f1e7eSYongseok Koh 		} else {
490974f1e7eSYongseok Koh 			/* Lookup allocated shared memory. */
491974f1e7eSYongseok Koh 			mz = rte_memzone_lookup(MZ_MLX5_PMD_SHARED_DATA);
4927be600c8SYongseok Koh 			if (mz == NULL) {
4937be600c8SYongseok Koh 				DRV_LOG(ERR,
4947be600c8SYongseok Koh 					"Cannot attach mlx5 shared data\n");
4957be600c8SYongseok Koh 				ret = -rte_errno;
4967be600c8SYongseok Koh 				goto error;
497974f1e7eSYongseok Koh 			}
498974f1e7eSYongseok Koh 			mlx5_shared_data = mz->addr;
4997be600c8SYongseok Koh 			memset(&mlx5_local_data, 0, sizeof(mlx5_local_data));
5003ebe6580SYongseok Koh 		}
501974f1e7eSYongseok Koh 	}
5027be600c8SYongseok Koh error:
5037be600c8SYongseok Koh 	rte_spinlock_unlock(&mlx5_shared_data_lock);
5047be600c8SYongseok Koh 	return ret;
5057be600c8SYongseok Koh }
5067be600c8SYongseok Koh 
5077be600c8SYongseok Koh /**
5084d803a72SOlga Shern  * Retrieve integer value from environment variable.
5094d803a72SOlga Shern  *
5104d803a72SOlga Shern  * @param[in] name
5114d803a72SOlga Shern  *   Environment variable name.
5124d803a72SOlga Shern  *
5134d803a72SOlga Shern  * @return
5144d803a72SOlga Shern  *   Integer value, 0 if the variable is not set.
5154d803a72SOlga Shern  */
5164d803a72SOlga Shern int
5174d803a72SOlga Shern mlx5_getenv_int(const char *name)
5184d803a72SOlga Shern {
5194d803a72SOlga Shern 	const char *val = getenv(name);
5204d803a72SOlga Shern 
5214d803a72SOlga Shern 	if (val == NULL)
5224d803a72SOlga Shern 		return 0;
5234d803a72SOlga Shern 	return atoi(val);
5244d803a72SOlga Shern }
5254d803a72SOlga Shern 
5264d803a72SOlga Shern /**
5271e3a39f7SXueming Li  * Verbs callback to allocate a memory. This function should allocate the space
5281e3a39f7SXueming Li  * according to the size provided residing inside a huge page.
5291e3a39f7SXueming Li  * Please note that all allocation must respect the alignment from libmlx5
5301e3a39f7SXueming Li  * (i.e. currently sysconf(_SC_PAGESIZE)).
5311e3a39f7SXueming Li  *
5321e3a39f7SXueming Li  * @param[in] size
5331e3a39f7SXueming Li  *   The size in bytes of the memory to allocate.
5341e3a39f7SXueming Li  * @param[in] data
5351e3a39f7SXueming Li  *   A pointer to the callback data.
5361e3a39f7SXueming Li  *
5371e3a39f7SXueming Li  * @return
538a6d83b6aSNélio Laranjeiro  *   Allocated buffer, NULL otherwise and rte_errno is set.
5391e3a39f7SXueming Li  */
5401e3a39f7SXueming Li static void *
5411e3a39f7SXueming Li mlx5_alloc_verbs_buf(size_t size, void *data)
5421e3a39f7SXueming Li {
543dbeba4cfSThomas Monjalon 	struct mlx5_priv *priv = data;
5441e3a39f7SXueming Li 	void *ret;
5451e3a39f7SXueming Li 	size_t alignment = sysconf(_SC_PAGESIZE);
546d10b09dbSOlivier Matz 	unsigned int socket = SOCKET_ID_ANY;
5471e3a39f7SXueming Li 
548d10b09dbSOlivier Matz 	if (priv->verbs_alloc_ctx.type == MLX5_VERBS_ALLOC_TYPE_TX_QUEUE) {
549d10b09dbSOlivier Matz 		const struct mlx5_txq_ctrl *ctrl = priv->verbs_alloc_ctx.obj;
550d10b09dbSOlivier Matz 
551d10b09dbSOlivier Matz 		socket = ctrl->socket;
552d10b09dbSOlivier Matz 	} else if (priv->verbs_alloc_ctx.type ==
553d10b09dbSOlivier Matz 		   MLX5_VERBS_ALLOC_TYPE_RX_QUEUE) {
554d10b09dbSOlivier Matz 		const struct mlx5_rxq_ctrl *ctrl = priv->verbs_alloc_ctx.obj;
555d10b09dbSOlivier Matz 
556d10b09dbSOlivier Matz 		socket = ctrl->socket;
557d10b09dbSOlivier Matz 	}
5581e3a39f7SXueming Li 	assert(data != NULL);
559d10b09dbSOlivier Matz 	ret = rte_malloc_socket(__func__, size, alignment, socket);
560a6d83b6aSNélio Laranjeiro 	if (!ret && size)
561a6d83b6aSNélio Laranjeiro 		rte_errno = ENOMEM;
5621e3a39f7SXueming Li 	return ret;
5631e3a39f7SXueming Li }
5641e3a39f7SXueming Li 
5651e3a39f7SXueming Li /**
5661e3a39f7SXueming Li  * Verbs callback to free a memory.
5671e3a39f7SXueming Li  *
5681e3a39f7SXueming Li  * @param[in] ptr
5691e3a39f7SXueming Li  *   A pointer to the memory to free.
5701e3a39f7SXueming Li  * @param[in] data
5711e3a39f7SXueming Li  *   A pointer to the callback data.
5721e3a39f7SXueming Li  */
5731e3a39f7SXueming Li static void
5741e3a39f7SXueming Li mlx5_free_verbs_buf(void *ptr, void *data __rte_unused)
5751e3a39f7SXueming Li {
5761e3a39f7SXueming Li 	assert(data != NULL);
5771e3a39f7SXueming Li 	rte_free(ptr);
5781e3a39f7SXueming Li }
5791e3a39f7SXueming Li 
5801e3a39f7SXueming Li /**
581120dc4a7SYongseok Koh  * Initialize process private data structure.
582120dc4a7SYongseok Koh  *
583120dc4a7SYongseok Koh  * @param dev
584120dc4a7SYongseok Koh  *   Pointer to Ethernet device structure.
585120dc4a7SYongseok Koh  *
586120dc4a7SYongseok Koh  * @return
587120dc4a7SYongseok Koh  *   0 on success, a negative errno value otherwise and rte_errno is set.
588120dc4a7SYongseok Koh  */
589120dc4a7SYongseok Koh int
590120dc4a7SYongseok Koh mlx5_proc_priv_init(struct rte_eth_dev *dev)
591120dc4a7SYongseok Koh {
592120dc4a7SYongseok Koh 	struct mlx5_priv *priv = dev->data->dev_private;
593120dc4a7SYongseok Koh 	struct mlx5_proc_priv *ppriv;
594120dc4a7SYongseok Koh 	size_t ppriv_size;
595120dc4a7SYongseok Koh 
596120dc4a7SYongseok Koh 	/*
597120dc4a7SYongseok Koh 	 * UAR register table follows the process private structure. BlueFlame
598120dc4a7SYongseok Koh 	 * registers for Tx queues are stored in the table.
599120dc4a7SYongseok Koh 	 */
600120dc4a7SYongseok Koh 	ppriv_size =
601120dc4a7SYongseok Koh 		sizeof(struct mlx5_proc_priv) + priv->txqs_n * sizeof(void *);
602120dc4a7SYongseok Koh 	ppriv = rte_malloc_socket("mlx5_proc_priv", ppriv_size,
603120dc4a7SYongseok Koh 				  RTE_CACHE_LINE_SIZE, dev->device->numa_node);
604120dc4a7SYongseok Koh 	if (!ppriv) {
605120dc4a7SYongseok Koh 		rte_errno = ENOMEM;
606120dc4a7SYongseok Koh 		return -rte_errno;
607120dc4a7SYongseok Koh 	}
608120dc4a7SYongseok Koh 	ppriv->uar_table_sz = ppriv_size;
609120dc4a7SYongseok Koh 	dev->process_private = ppriv;
610120dc4a7SYongseok Koh 	return 0;
611120dc4a7SYongseok Koh }
612120dc4a7SYongseok Koh 
613120dc4a7SYongseok Koh /**
614120dc4a7SYongseok Koh  * Un-initialize process private data structure.
615120dc4a7SYongseok Koh  *
616120dc4a7SYongseok Koh  * @param dev
617120dc4a7SYongseok Koh  *   Pointer to Ethernet device structure.
618120dc4a7SYongseok Koh  */
619120dc4a7SYongseok Koh static void
620120dc4a7SYongseok Koh mlx5_proc_priv_uninit(struct rte_eth_dev *dev)
621120dc4a7SYongseok Koh {
622120dc4a7SYongseok Koh 	if (!dev->process_private)
623120dc4a7SYongseok Koh 		return;
624120dc4a7SYongseok Koh 	rte_free(dev->process_private);
625120dc4a7SYongseok Koh 	dev->process_private = NULL;
626120dc4a7SYongseok Koh }
627120dc4a7SYongseok Koh 
628120dc4a7SYongseok Koh /**
629771fa900SAdrien Mazarguil  * DPDK callback to close the device.
630771fa900SAdrien Mazarguil  *
631771fa900SAdrien Mazarguil  * Destroy all queues and objects, free memory.
632771fa900SAdrien Mazarguil  *
633771fa900SAdrien Mazarguil  * @param dev
634771fa900SAdrien Mazarguil  *   Pointer to Ethernet device structure.
635771fa900SAdrien Mazarguil  */
636771fa900SAdrien Mazarguil static void
637771fa900SAdrien Mazarguil mlx5_dev_close(struct rte_eth_dev *dev)
638771fa900SAdrien Mazarguil {
639dbeba4cfSThomas Monjalon 	struct mlx5_priv *priv = dev->data->dev_private;
6402e22920bSAdrien Mazarguil 	unsigned int i;
6416af6b973SNélio Laranjeiro 	int ret;
642771fa900SAdrien Mazarguil 
643a170a30dSNélio Laranjeiro 	DRV_LOG(DEBUG, "port %u closing device \"%s\"",
6440f99970bSNélio Laranjeiro 		dev->data->port_id,
645f048f3d4SViacheslav Ovsiienko 		((priv->sh->ctx != NULL) ? priv->sh->ctx->device->name : ""));
646ecc1c29dSAdrien Mazarguil 	/* In case mlx5_dev_stop() has not been called. */
647af4f09f2SNélio Laranjeiro 	mlx5_dev_interrupt_handler_uninstall(dev);
648af4f09f2SNélio Laranjeiro 	mlx5_traffic_disable(dev);
649af689f1fSNelio Laranjeiro 	mlx5_flow_flush(dev, NULL);
6502e22920bSAdrien Mazarguil 	/* Prevent crashes when queues are still in use. */
6512e22920bSAdrien Mazarguil 	dev->rx_pkt_burst = removed_rx_burst;
6522e22920bSAdrien Mazarguil 	dev->tx_pkt_burst = removed_tx_burst;
6532aac5b5dSYongseok Koh 	rte_wmb();
6542aac5b5dSYongseok Koh 	/* Disable datapath on secondary process. */
6552aac5b5dSYongseok Koh 	mlx5_mp_req_stop_rxtx(dev);
6562e22920bSAdrien Mazarguil 	if (priv->rxqs != NULL) {
6572e22920bSAdrien Mazarguil 		/* XXX race condition if mlx5_rx_burst() is still running. */
6582e22920bSAdrien Mazarguil 		usleep(1000);
659a1366b1aSNélio Laranjeiro 		for (i = 0; (i != priv->rxqs_n); ++i)
660af4f09f2SNélio Laranjeiro 			mlx5_rxq_release(dev, i);
6612e22920bSAdrien Mazarguil 		priv->rxqs_n = 0;
6622e22920bSAdrien Mazarguil 		priv->rxqs = NULL;
6632e22920bSAdrien Mazarguil 	}
6642e22920bSAdrien Mazarguil 	if (priv->txqs != NULL) {
6652e22920bSAdrien Mazarguil 		/* XXX race condition if mlx5_tx_burst() is still running. */
6662e22920bSAdrien Mazarguil 		usleep(1000);
6676e78005aSNélio Laranjeiro 		for (i = 0; (i != priv->txqs_n); ++i)
668af4f09f2SNélio Laranjeiro 			mlx5_txq_release(dev, i);
6692e22920bSAdrien Mazarguil 		priv->txqs_n = 0;
6702e22920bSAdrien Mazarguil 		priv->txqs = NULL;
6712e22920bSAdrien Mazarguil 	}
672120dc4a7SYongseok Koh 	mlx5_proc_priv_uninit(dev);
6737d6bf6b8SYongseok Koh 	mlx5_mprq_free_mp(dev);
674ab3cffcfSViacheslav Ovsiienko 	/* Remove from memory callback device list. */
675ab3cffcfSViacheslav Ovsiienko 	rte_rwlock_write_lock(&mlx5_shared_data->mem_event_rwlock);
67617e19bc4SViacheslav Ovsiienko 	assert(priv->sh);
677ccb38153SViacheslav Ovsiienko 	LIST_REMOVE(priv->sh, mem_event_cb);
678ccb38153SViacheslav Ovsiienko 	rte_rwlock_write_unlock(&mlx5_shared_data->mem_event_rwlock);
679b2177648SViacheslav Ovsiienko 	mlx5_free_shared_dr(priv);
68029c1d8bbSNélio Laranjeiro 	if (priv->rss_conf.rss_key != NULL)
68129c1d8bbSNélio Laranjeiro 		rte_free(priv->rss_conf.rss_key);
682634efbc2SNelio Laranjeiro 	if (priv->reta_idx != NULL)
683634efbc2SNelio Laranjeiro 		rte_free(priv->reta_idx);
684ccdcba53SNélio Laranjeiro 	if (priv->config.vf)
685ccdcba53SNélio Laranjeiro 		mlx5_nl_mac_addr_flush(dev);
68626c08b97SAdrien Mazarguil 	if (priv->nl_socket_route >= 0)
68726c08b97SAdrien Mazarguil 		close(priv->nl_socket_route);
68826c08b97SAdrien Mazarguil 	if (priv->nl_socket_rdma >= 0)
68926c08b97SAdrien Mazarguil 		close(priv->nl_socket_rdma);
690d53180afSMoti Haimovsky 	if (priv->tcf_context)
691d53180afSMoti Haimovsky 		mlx5_flow_tcf_context_destroy(priv->tcf_context);
692942d13e6SViacheslav Ovsiienko 	if (priv->sh) {
693942d13e6SViacheslav Ovsiienko 		/*
694942d13e6SViacheslav Ovsiienko 		 * Free the shared context in last turn, because the cleanup
695942d13e6SViacheslav Ovsiienko 		 * routines above may use some shared fields, like
696942d13e6SViacheslav Ovsiienko 		 * mlx5_nl_mac_addr_flush() uses ibdev_path for retrieveing
697942d13e6SViacheslav Ovsiienko 		 * ifindex if Netlink fails.
698942d13e6SViacheslav Ovsiienko 		 */
699942d13e6SViacheslav Ovsiienko 		mlx5_free_shared_ibctx(priv->sh);
700942d13e6SViacheslav Ovsiienko 		priv->sh = NULL;
701942d13e6SViacheslav Ovsiienko 	}
702af4f09f2SNélio Laranjeiro 	ret = mlx5_hrxq_ibv_verify(dev);
703f5479b68SNélio Laranjeiro 	if (ret)
704a170a30dSNélio Laranjeiro 		DRV_LOG(WARNING, "port %u some hash Rx queue still remain",
7050f99970bSNélio Laranjeiro 			dev->data->port_id);
706af4f09f2SNélio Laranjeiro 	ret = mlx5_ind_table_ibv_verify(dev);
7074c7a0f5fSNélio Laranjeiro 	if (ret)
708a170a30dSNélio Laranjeiro 		DRV_LOG(WARNING, "port %u some indirection table still remain",
7090f99970bSNélio Laranjeiro 			dev->data->port_id);
710af4f09f2SNélio Laranjeiro 	ret = mlx5_rxq_ibv_verify(dev);
71109cb5b58SNélio Laranjeiro 	if (ret)
712a170a30dSNélio Laranjeiro 		DRV_LOG(WARNING, "port %u some Verbs Rx queue still remain",
7130f99970bSNélio Laranjeiro 			dev->data->port_id);
714af4f09f2SNélio Laranjeiro 	ret = mlx5_rxq_verify(dev);
715a1366b1aSNélio Laranjeiro 	if (ret)
716a170a30dSNélio Laranjeiro 		DRV_LOG(WARNING, "port %u some Rx queues still remain",
7170f99970bSNélio Laranjeiro 			dev->data->port_id);
718af4f09f2SNélio Laranjeiro 	ret = mlx5_txq_ibv_verify(dev);
719faf2667fSNélio Laranjeiro 	if (ret)
720a170a30dSNélio Laranjeiro 		DRV_LOG(WARNING, "port %u some Verbs Tx queue still remain",
7210f99970bSNélio Laranjeiro 			dev->data->port_id);
722af4f09f2SNélio Laranjeiro 	ret = mlx5_txq_verify(dev);
7236e78005aSNélio Laranjeiro 	if (ret)
724a170a30dSNélio Laranjeiro 		DRV_LOG(WARNING, "port %u some Tx queues still remain",
7250f99970bSNélio Laranjeiro 			dev->data->port_id);
726af4f09f2SNélio Laranjeiro 	ret = mlx5_flow_verify(dev);
7276af6b973SNélio Laranjeiro 	if (ret)
728a170a30dSNélio Laranjeiro 		DRV_LOG(WARNING, "port %u some flows still remain",
729a170a30dSNélio Laranjeiro 			dev->data->port_id);
7302b730263SAdrien Mazarguil 	if (priv->domain_id != RTE_ETH_DEV_SWITCH_DOMAIN_ID_INVALID) {
7312b730263SAdrien Mazarguil 		unsigned int c = 0;
732d874a4eeSThomas Monjalon 		uint16_t port_id;
7332b730263SAdrien Mazarguil 
734d874a4eeSThomas Monjalon 		RTE_ETH_FOREACH_DEV_OF(port_id, dev->device) {
735dbeba4cfSThomas Monjalon 			struct mlx5_priv *opriv =
736d874a4eeSThomas Monjalon 				rte_eth_devices[port_id].data->dev_private;
7372b730263SAdrien Mazarguil 
7382b730263SAdrien Mazarguil 			if (!opriv ||
7392b730263SAdrien Mazarguil 			    opriv->domain_id != priv->domain_id ||
740d874a4eeSThomas Monjalon 			    &rte_eth_devices[port_id] == dev)
7412b730263SAdrien Mazarguil 				continue;
7422b730263SAdrien Mazarguil 			++c;
7432b730263SAdrien Mazarguil 		}
7442b730263SAdrien Mazarguil 		if (!c)
7452b730263SAdrien Mazarguil 			claim_zero(rte_eth_switch_domain_free(priv->domain_id));
7462b730263SAdrien Mazarguil 	}
747771fa900SAdrien Mazarguil 	memset(priv, 0, sizeof(*priv));
7482b730263SAdrien Mazarguil 	priv->domain_id = RTE_ETH_DEV_SWITCH_DOMAIN_ID_INVALID;
74942603bbdSOphir Munk 	/*
75042603bbdSOphir Munk 	 * Reset mac_addrs to NULL such that it is not freed as part of
75142603bbdSOphir Munk 	 * rte_eth_dev_release_port(). mac_addrs is part of dev_private so
75242603bbdSOphir Munk 	 * it is freed when dev_private is freed.
75342603bbdSOphir Munk 	 */
75442603bbdSOphir Munk 	dev->data->mac_addrs = NULL;
755771fa900SAdrien Mazarguil }
756771fa900SAdrien Mazarguil 
7570887aa7fSNélio Laranjeiro const struct eth_dev_ops mlx5_dev_ops = {
758e60fbd5bSAdrien Mazarguil 	.dev_configure = mlx5_dev_configure,
759e60fbd5bSAdrien Mazarguil 	.dev_start = mlx5_dev_start,
760e60fbd5bSAdrien Mazarguil 	.dev_stop = mlx5_dev_stop,
76162072098SOr Ami 	.dev_set_link_down = mlx5_set_link_down,
76262072098SOr Ami 	.dev_set_link_up = mlx5_set_link_up,
763771fa900SAdrien Mazarguil 	.dev_close = mlx5_dev_close,
7641bdbe1afSAdrien Mazarguil 	.promiscuous_enable = mlx5_promiscuous_enable,
7651bdbe1afSAdrien Mazarguil 	.promiscuous_disable = mlx5_promiscuous_disable,
7661bdbe1afSAdrien Mazarguil 	.allmulticast_enable = mlx5_allmulticast_enable,
7671bdbe1afSAdrien Mazarguil 	.allmulticast_disable = mlx5_allmulticast_disable,
768cb8faed7SAdrien Mazarguil 	.link_update = mlx5_link_update,
76987011737SAdrien Mazarguil 	.stats_get = mlx5_stats_get,
77087011737SAdrien Mazarguil 	.stats_reset = mlx5_stats_reset,
771a4193ae3SShahaf Shuler 	.xstats_get = mlx5_xstats_get,
772a4193ae3SShahaf Shuler 	.xstats_reset = mlx5_xstats_reset,
773a4193ae3SShahaf Shuler 	.xstats_get_names = mlx5_xstats_get_names,
774714bf46eSThomas Monjalon 	.fw_version_get = mlx5_fw_version_get,
775e60fbd5bSAdrien Mazarguil 	.dev_infos_get = mlx5_dev_infos_get,
77678a38edfSJianfeng Tan 	.dev_supported_ptypes_get = mlx5_dev_supported_ptypes_get,
777e9086978SAdrien Mazarguil 	.vlan_filter_set = mlx5_vlan_filter_set,
7782e22920bSAdrien Mazarguil 	.rx_queue_setup = mlx5_rx_queue_setup,
7792e22920bSAdrien Mazarguil 	.tx_queue_setup = mlx5_tx_queue_setup,
7802e22920bSAdrien Mazarguil 	.rx_queue_release = mlx5_rx_queue_release,
7812e22920bSAdrien Mazarguil 	.tx_queue_release = mlx5_tx_queue_release,
78202d75430SAdrien Mazarguil 	.flow_ctrl_get = mlx5_dev_get_flow_ctrl,
78302d75430SAdrien Mazarguil 	.flow_ctrl_set = mlx5_dev_set_flow_ctrl,
7843318aef7SAdrien Mazarguil 	.mac_addr_remove = mlx5_mac_addr_remove,
7853318aef7SAdrien Mazarguil 	.mac_addr_add = mlx5_mac_addr_add,
78686977fccSDavid Marchand 	.mac_addr_set = mlx5_mac_addr_set,
787e0586a8dSNélio Laranjeiro 	.set_mc_addr_list = mlx5_set_mc_addr_list,
788cf37ca95SAdrien Mazarguil 	.mtu_set = mlx5_dev_set_mtu,
789f3db9489SYaacov Hazan 	.vlan_strip_queue_set = mlx5_vlan_strip_queue_set,
790f3db9489SYaacov Hazan 	.vlan_offload_set = mlx5_vlan_offload_set,
791634efbc2SNelio Laranjeiro 	.reta_update = mlx5_dev_rss_reta_update,
792634efbc2SNelio Laranjeiro 	.reta_query = mlx5_dev_rss_reta_query,
7932f97422eSNelio Laranjeiro 	.rss_hash_update = mlx5_rss_hash_update,
7942f97422eSNelio Laranjeiro 	.rss_hash_conf_get = mlx5_rss_hash_conf_get,
79576f5c99eSYaacov Hazan 	.filter_ctrl = mlx5_dev_filter_ctrl,
7968788fec1SOlivier Matz 	.rx_descriptor_status = mlx5_rx_descriptor_status,
7978788fec1SOlivier Matz 	.tx_descriptor_status = mlx5_tx_descriptor_status,
79826f04883STom Barbette 	.rx_queue_count = mlx5_rx_queue_count,
7993c7d44afSShahaf Shuler 	.rx_queue_intr_enable = mlx5_rx_intr_enable,
8003c7d44afSShahaf Shuler 	.rx_queue_intr_disable = mlx5_rx_intr_disable,
801d3e0f392SMatan Azrad 	.is_removed = mlx5_is_removed,
802771fa900SAdrien Mazarguil };
803771fa900SAdrien Mazarguil 
804714bf46eSThomas Monjalon /* Available operations from secondary process. */
80587ec44ceSXueming Li static const struct eth_dev_ops mlx5_dev_sec_ops = {
80687ec44ceSXueming Li 	.stats_get = mlx5_stats_get,
80787ec44ceSXueming Li 	.stats_reset = mlx5_stats_reset,
80887ec44ceSXueming Li 	.xstats_get = mlx5_xstats_get,
80987ec44ceSXueming Li 	.xstats_reset = mlx5_xstats_reset,
81087ec44ceSXueming Li 	.xstats_get_names = mlx5_xstats_get_names,
811714bf46eSThomas Monjalon 	.fw_version_get = mlx5_fw_version_get,
81287ec44ceSXueming Li 	.dev_infos_get = mlx5_dev_infos_get,
81387ec44ceSXueming Li 	.rx_descriptor_status = mlx5_rx_descriptor_status,
81487ec44ceSXueming Li 	.tx_descriptor_status = mlx5_tx_descriptor_status,
81587ec44ceSXueming Li };
81687ec44ceSXueming Li 
817714bf46eSThomas Monjalon /* Available operations in flow isolated mode. */
8180887aa7fSNélio Laranjeiro const struct eth_dev_ops mlx5_dev_ops_isolate = {
8190887aa7fSNélio Laranjeiro 	.dev_configure = mlx5_dev_configure,
8200887aa7fSNélio Laranjeiro 	.dev_start = mlx5_dev_start,
8210887aa7fSNélio Laranjeiro 	.dev_stop = mlx5_dev_stop,
8220887aa7fSNélio Laranjeiro 	.dev_set_link_down = mlx5_set_link_down,
8230887aa7fSNélio Laranjeiro 	.dev_set_link_up = mlx5_set_link_up,
8240887aa7fSNélio Laranjeiro 	.dev_close = mlx5_dev_close,
82524b068adSYongseok Koh 	.promiscuous_enable = mlx5_promiscuous_enable,
82624b068adSYongseok Koh 	.promiscuous_disable = mlx5_promiscuous_disable,
8272547ee74SYongseok Koh 	.allmulticast_enable = mlx5_allmulticast_enable,
8282547ee74SYongseok Koh 	.allmulticast_disable = mlx5_allmulticast_disable,
8290887aa7fSNélio Laranjeiro 	.link_update = mlx5_link_update,
8300887aa7fSNélio Laranjeiro 	.stats_get = mlx5_stats_get,
8310887aa7fSNélio Laranjeiro 	.stats_reset = mlx5_stats_reset,
8320887aa7fSNélio Laranjeiro 	.xstats_get = mlx5_xstats_get,
8330887aa7fSNélio Laranjeiro 	.xstats_reset = mlx5_xstats_reset,
8340887aa7fSNélio Laranjeiro 	.xstats_get_names = mlx5_xstats_get_names,
835714bf46eSThomas Monjalon 	.fw_version_get = mlx5_fw_version_get,
8360887aa7fSNélio Laranjeiro 	.dev_infos_get = mlx5_dev_infos_get,
8370887aa7fSNélio Laranjeiro 	.dev_supported_ptypes_get = mlx5_dev_supported_ptypes_get,
8380887aa7fSNélio Laranjeiro 	.vlan_filter_set = mlx5_vlan_filter_set,
8390887aa7fSNélio Laranjeiro 	.rx_queue_setup = mlx5_rx_queue_setup,
8400887aa7fSNélio Laranjeiro 	.tx_queue_setup = mlx5_tx_queue_setup,
8410887aa7fSNélio Laranjeiro 	.rx_queue_release = mlx5_rx_queue_release,
8420887aa7fSNélio Laranjeiro 	.tx_queue_release = mlx5_tx_queue_release,
8430887aa7fSNélio Laranjeiro 	.flow_ctrl_get = mlx5_dev_get_flow_ctrl,
8440887aa7fSNélio Laranjeiro 	.flow_ctrl_set = mlx5_dev_set_flow_ctrl,
8450887aa7fSNélio Laranjeiro 	.mac_addr_remove = mlx5_mac_addr_remove,
8460887aa7fSNélio Laranjeiro 	.mac_addr_add = mlx5_mac_addr_add,
8470887aa7fSNélio Laranjeiro 	.mac_addr_set = mlx5_mac_addr_set,
848e0586a8dSNélio Laranjeiro 	.set_mc_addr_list = mlx5_set_mc_addr_list,
8490887aa7fSNélio Laranjeiro 	.mtu_set = mlx5_dev_set_mtu,
8500887aa7fSNélio Laranjeiro 	.vlan_strip_queue_set = mlx5_vlan_strip_queue_set,
8510887aa7fSNélio Laranjeiro 	.vlan_offload_set = mlx5_vlan_offload_set,
8520887aa7fSNélio Laranjeiro 	.filter_ctrl = mlx5_dev_filter_ctrl,
8530887aa7fSNélio Laranjeiro 	.rx_descriptor_status = mlx5_rx_descriptor_status,
8540887aa7fSNélio Laranjeiro 	.tx_descriptor_status = mlx5_tx_descriptor_status,
8550887aa7fSNélio Laranjeiro 	.rx_queue_intr_enable = mlx5_rx_intr_enable,
8560887aa7fSNélio Laranjeiro 	.rx_queue_intr_disable = mlx5_rx_intr_disable,
857d3e0f392SMatan Azrad 	.is_removed = mlx5_is_removed,
8580887aa7fSNélio Laranjeiro };
8590887aa7fSNélio Laranjeiro 
860e72dd09bSNélio Laranjeiro /**
861e72dd09bSNélio Laranjeiro  * Verify and store value for device argument.
862e72dd09bSNélio Laranjeiro  *
863e72dd09bSNélio Laranjeiro  * @param[in] key
864e72dd09bSNélio Laranjeiro  *   Key argument to verify.
865e72dd09bSNélio Laranjeiro  * @param[in] val
866e72dd09bSNélio Laranjeiro  *   Value associated with key.
867e72dd09bSNélio Laranjeiro  * @param opaque
868e72dd09bSNélio Laranjeiro  *   User data.
869e72dd09bSNélio Laranjeiro  *
870e72dd09bSNélio Laranjeiro  * @return
871a6d83b6aSNélio Laranjeiro  *   0 on success, a negative errno value otherwise and rte_errno is set.
872e72dd09bSNélio Laranjeiro  */
873e72dd09bSNélio Laranjeiro static int
874e72dd09bSNélio Laranjeiro mlx5_args_check(const char *key, const char *val, void *opaque)
875e72dd09bSNélio Laranjeiro {
8767fe24446SShahaf Shuler 	struct mlx5_dev_config *config = opaque;
87799c12dccSNélio Laranjeiro 	unsigned long tmp;
878e72dd09bSNélio Laranjeiro 
8796de569f5SAdrien Mazarguil 	/* No-op, port representors are processed in mlx5_dev_spawn(). */
8806de569f5SAdrien Mazarguil 	if (!strcmp(MLX5_REPRESENTOR, key))
8816de569f5SAdrien Mazarguil 		return 0;
88299c12dccSNélio Laranjeiro 	errno = 0;
88399c12dccSNélio Laranjeiro 	tmp = strtoul(val, NULL, 0);
88499c12dccSNélio Laranjeiro 	if (errno) {
885a6d83b6aSNélio Laranjeiro 		rte_errno = errno;
886a170a30dSNélio Laranjeiro 		DRV_LOG(WARNING, "%s: \"%s\" is not a valid integer", key, val);
887a6d83b6aSNélio Laranjeiro 		return -rte_errno;
88899c12dccSNélio Laranjeiro 	}
88999c12dccSNélio Laranjeiro 	if (strcmp(MLX5_RXQ_CQE_COMP_EN, key) == 0) {
8907fe24446SShahaf Shuler 		config->cqe_comp = !!tmp;
891bc91e8dbSYongseok Koh 	} else if (strcmp(MLX5_RXQ_CQE_PAD_EN, key) == 0) {
892bc91e8dbSYongseok Koh 		config->cqe_pad = !!tmp;
89378c7a16dSYongseok Koh 	} else if (strcmp(MLX5_RXQ_PKT_PAD_EN, key) == 0) {
89478c7a16dSYongseok Koh 		config->hw_padding = !!tmp;
8957d6bf6b8SYongseok Koh 	} else if (strcmp(MLX5_RX_MPRQ_EN, key) == 0) {
8967d6bf6b8SYongseok Koh 		config->mprq.enabled = !!tmp;
8977d6bf6b8SYongseok Koh 	} else if (strcmp(MLX5_RX_MPRQ_LOG_STRIDE_NUM, key) == 0) {
8987d6bf6b8SYongseok Koh 		config->mprq.stride_num_n = tmp;
8997d6bf6b8SYongseok Koh 	} else if (strcmp(MLX5_RX_MPRQ_MAX_MEMCPY_LEN, key) == 0) {
9007d6bf6b8SYongseok Koh 		config->mprq.max_memcpy_len = tmp;
9017d6bf6b8SYongseok Koh 	} else if (strcmp(MLX5_RXQS_MIN_MPRQ, key) == 0) {
9027d6bf6b8SYongseok Koh 		config->mprq.min_rxqs_num = tmp;
9032a66cf37SYaacov Hazan 	} else if (strcmp(MLX5_TXQ_INLINE, key) == 0) {
9047fe24446SShahaf Shuler 		config->txq_inline = tmp;
9052a66cf37SYaacov Hazan 	} else if (strcmp(MLX5_TXQS_MIN_INLINE, key) == 0) {
9067fe24446SShahaf Shuler 		config->txqs_inline = tmp;
90709d8b416SYongseok Koh 	} else if (strcmp(MLX5_TXQS_MAX_VEC, key) == 0) {
90809d8b416SYongseok Koh 		config->txqs_vec = tmp;
909230189d9SNélio Laranjeiro 	} else if (strcmp(MLX5_TXQ_MPW_EN, key) == 0) {
910f9de8718SShahaf Shuler 		config->mps = !!tmp;
9116ce84bd8SYongseok Koh 	} else if (strcmp(MLX5_TXQ_MPW_HDR_DSEG_EN, key) == 0) {
9127fe24446SShahaf Shuler 		config->mpw_hdr_dseg = !!tmp;
9136ce84bd8SYongseok Koh 	} else if (strcmp(MLX5_TXQ_MAX_INLINE_LEN, key) == 0) {
9147fe24446SShahaf Shuler 		config->inline_max_packet_sz = tmp;
9155644d5b9SNelio Laranjeiro 	} else if (strcmp(MLX5_TX_VEC_EN, key) == 0) {
9167fe24446SShahaf Shuler 		config->tx_vec_en = !!tmp;
9175644d5b9SNelio Laranjeiro 	} else if (strcmp(MLX5_RX_VEC_EN, key) == 0) {
9187fe24446SShahaf Shuler 		config->rx_vec_en = !!tmp;
91978a54648SXueming Li 	} else if (strcmp(MLX5_L3_VXLAN_EN, key) == 0) {
92078a54648SXueming Li 		config->l3_vxlan_en = !!tmp;
921db209cc3SNélio Laranjeiro 	} else if (strcmp(MLX5_VF_NL_EN, key) == 0) {
922db209cc3SNélio Laranjeiro 		config->vf_nl_en = !!tmp;
923e2b4925eSOri Kam 	} else if (strcmp(MLX5_DV_ESW_EN, key) == 0) {
924e2b4925eSOri Kam 		config->dv_esw_en = !!tmp;
92551e72d38SOri Kam 	} else if (strcmp(MLX5_DV_FLOW_EN, key) == 0) {
92651e72d38SOri Kam 		config->dv_flow_en = !!tmp;
927dceb5029SYongseok Koh 	} else if (strcmp(MLX5_MR_EXT_MEMSEG_EN, key) == 0) {
928dceb5029SYongseok Koh 		config->mr_ext_memseg_en = !!tmp;
92999c12dccSNélio Laranjeiro 	} else {
930a170a30dSNélio Laranjeiro 		DRV_LOG(WARNING, "%s: unknown parameter", key);
931a6d83b6aSNélio Laranjeiro 		rte_errno = EINVAL;
932a6d83b6aSNélio Laranjeiro 		return -rte_errno;
933e72dd09bSNélio Laranjeiro 	}
93499c12dccSNélio Laranjeiro 	return 0;
93599c12dccSNélio Laranjeiro }
936e72dd09bSNélio Laranjeiro 
937e72dd09bSNélio Laranjeiro /**
938e72dd09bSNélio Laranjeiro  * Parse device parameters.
939e72dd09bSNélio Laranjeiro  *
9407fe24446SShahaf Shuler  * @param config
9417fe24446SShahaf Shuler  *   Pointer to device configuration structure.
942e72dd09bSNélio Laranjeiro  * @param devargs
943e72dd09bSNélio Laranjeiro  *   Device arguments structure.
944e72dd09bSNélio Laranjeiro  *
945e72dd09bSNélio Laranjeiro  * @return
946a6d83b6aSNélio Laranjeiro  *   0 on success, a negative errno value otherwise and rte_errno is set.
947e72dd09bSNélio Laranjeiro  */
948e72dd09bSNélio Laranjeiro static int
9497fe24446SShahaf Shuler mlx5_args(struct mlx5_dev_config *config, struct rte_devargs *devargs)
950e72dd09bSNélio Laranjeiro {
951e72dd09bSNélio Laranjeiro 	const char **params = (const char *[]){
95299c12dccSNélio Laranjeiro 		MLX5_RXQ_CQE_COMP_EN,
953bc91e8dbSYongseok Koh 		MLX5_RXQ_CQE_PAD_EN,
95478c7a16dSYongseok Koh 		MLX5_RXQ_PKT_PAD_EN,
9557d6bf6b8SYongseok Koh 		MLX5_RX_MPRQ_EN,
9567d6bf6b8SYongseok Koh 		MLX5_RX_MPRQ_LOG_STRIDE_NUM,
9577d6bf6b8SYongseok Koh 		MLX5_RX_MPRQ_MAX_MEMCPY_LEN,
9587d6bf6b8SYongseok Koh 		MLX5_RXQS_MIN_MPRQ,
9592a66cf37SYaacov Hazan 		MLX5_TXQ_INLINE,
9602a66cf37SYaacov Hazan 		MLX5_TXQS_MIN_INLINE,
96109d8b416SYongseok Koh 		MLX5_TXQS_MAX_VEC,
962230189d9SNélio Laranjeiro 		MLX5_TXQ_MPW_EN,
9636ce84bd8SYongseok Koh 		MLX5_TXQ_MPW_HDR_DSEG_EN,
9646ce84bd8SYongseok Koh 		MLX5_TXQ_MAX_INLINE_LEN,
9655644d5b9SNelio Laranjeiro 		MLX5_TX_VEC_EN,
9665644d5b9SNelio Laranjeiro 		MLX5_RX_VEC_EN,
96778a54648SXueming Li 		MLX5_L3_VXLAN_EN,
968db209cc3SNélio Laranjeiro 		MLX5_VF_NL_EN,
969e2b4925eSOri Kam 		MLX5_DV_ESW_EN,
97051e72d38SOri Kam 		MLX5_DV_FLOW_EN,
971dceb5029SYongseok Koh 		MLX5_MR_EXT_MEMSEG_EN,
9726de569f5SAdrien Mazarguil 		MLX5_REPRESENTOR,
973e72dd09bSNélio Laranjeiro 		NULL,
974e72dd09bSNélio Laranjeiro 	};
975e72dd09bSNélio Laranjeiro 	struct rte_kvargs *kvlist;
976e72dd09bSNélio Laranjeiro 	int ret = 0;
977e72dd09bSNélio Laranjeiro 	int i;
978e72dd09bSNélio Laranjeiro 
979e72dd09bSNélio Laranjeiro 	if (devargs == NULL)
980e72dd09bSNélio Laranjeiro 		return 0;
981e72dd09bSNélio Laranjeiro 	/* Following UGLY cast is done to pass checkpatch. */
982e72dd09bSNélio Laranjeiro 	kvlist = rte_kvargs_parse(devargs->args, params);
983e72dd09bSNélio Laranjeiro 	if (kvlist == NULL)
984e72dd09bSNélio Laranjeiro 		return 0;
985e72dd09bSNélio Laranjeiro 	/* Process parameters. */
986e72dd09bSNélio Laranjeiro 	for (i = 0; (params[i] != NULL); ++i) {
987e72dd09bSNélio Laranjeiro 		if (rte_kvargs_count(kvlist, params[i])) {
988e72dd09bSNélio Laranjeiro 			ret = rte_kvargs_process(kvlist, params[i],
9897fe24446SShahaf Shuler 						 mlx5_args_check, config);
990a6d83b6aSNélio Laranjeiro 			if (ret) {
991a6d83b6aSNélio Laranjeiro 				rte_errno = EINVAL;
992a67323e4SShahaf Shuler 				rte_kvargs_free(kvlist);
993a6d83b6aSNélio Laranjeiro 				return -rte_errno;
994e72dd09bSNélio Laranjeiro 			}
995e72dd09bSNélio Laranjeiro 		}
996a67323e4SShahaf Shuler 	}
997e72dd09bSNélio Laranjeiro 	rte_kvargs_free(kvlist);
998e72dd09bSNélio Laranjeiro 	return 0;
999e72dd09bSNélio Laranjeiro }
1000e72dd09bSNélio Laranjeiro 
1001fdf91e0fSJan Blunck static struct rte_pci_driver mlx5_driver;
1002771fa900SAdrien Mazarguil 
10037be600c8SYongseok Koh /**
10047be600c8SYongseok Koh  * PMD global initialization.
10057be600c8SYongseok Koh  *
10067be600c8SYongseok Koh  * Independent from individual device, this function initializes global
10077be600c8SYongseok Koh  * per-PMD data structures distinguishing primary and secondary processes.
10087be600c8SYongseok Koh  * Hence, each initialization is called once per a process.
10097be600c8SYongseok Koh  *
10107be600c8SYongseok Koh  * @return
10117be600c8SYongseok Koh  *   0 on success, a negative errno value otherwise and rte_errno is set.
10127be600c8SYongseok Koh  */
10137be600c8SYongseok Koh static int
10147be600c8SYongseok Koh mlx5_init_once(void)
10157be600c8SYongseok Koh {
10167be600c8SYongseok Koh 	struct mlx5_shared_data *sd;
10177be600c8SYongseok Koh 	struct mlx5_local_data *ld = &mlx5_local_data;
10187be600c8SYongseok Koh 
10197be600c8SYongseok Koh 	if (mlx5_init_shared_data())
10207be600c8SYongseok Koh 		return -rte_errno;
10217be600c8SYongseok Koh 	sd = mlx5_shared_data;
10227be600c8SYongseok Koh 	assert(sd);
10237be600c8SYongseok Koh 	rte_spinlock_lock(&sd->lock);
10247be600c8SYongseok Koh 	switch (rte_eal_process_type()) {
10257be600c8SYongseok Koh 	case RTE_PROC_PRIMARY:
10267be600c8SYongseok Koh 		if (sd->init_done)
10277be600c8SYongseok Koh 			break;
10287be600c8SYongseok Koh 		LIST_INIT(&sd->mem_event_cb_list);
10297be600c8SYongseok Koh 		rte_rwlock_init(&sd->mem_event_rwlock);
10307be600c8SYongseok Koh 		rte_mem_event_callback_register("MLX5_MEM_EVENT_CB",
10317be600c8SYongseok Koh 						mlx5_mr_mem_event_cb, NULL);
10327be600c8SYongseok Koh 		mlx5_mp_init_primary();
10337be600c8SYongseok Koh 		sd->init_done = true;
10347be600c8SYongseok Koh 		break;
10357be600c8SYongseok Koh 	case RTE_PROC_SECONDARY:
10367be600c8SYongseok Koh 		if (ld->init_done)
10377be600c8SYongseok Koh 			break;
10382aac5b5dSYongseok Koh 		mlx5_mp_init_secondary();
10397be600c8SYongseok Koh 		++sd->secondary_cnt;
10407be600c8SYongseok Koh 		ld->init_done = true;
10417be600c8SYongseok Koh 		break;
10427be600c8SYongseok Koh 	default:
10437be600c8SYongseok Koh 		break;
10447be600c8SYongseok Koh 	}
10457be600c8SYongseok Koh 	rte_spinlock_unlock(&sd->lock);
10467be600c8SYongseok Koh 	return 0;
10477be600c8SYongseok Koh }
10487be600c8SYongseok Koh 
10497be600c8SYongseok Koh /**
1050f38c5457SAdrien Mazarguil  * Spawn an Ethernet device from Verbs information.
1051771fa900SAdrien Mazarguil  *
1052f38c5457SAdrien Mazarguil  * @param dpdk_dev
1053f38c5457SAdrien Mazarguil  *   Backing DPDK device.
1054ad74bc61SViacheslav Ovsiienko  * @param spawn
1055ad74bc61SViacheslav Ovsiienko  *   Verbs device parameters (name, port, switch_info) to spawn.
1056f87bfa8eSYongseok Koh  * @param config
1057f87bfa8eSYongseok Koh  *   Device configuration parameters.
1058771fa900SAdrien Mazarguil  *
1059771fa900SAdrien Mazarguil  * @return
1060f38c5457SAdrien Mazarguil  *   A valid Ethernet device object on success, NULL otherwise and rte_errno
1061206254b7SOphir Munk  *   is set. The following errors are defined:
10626de569f5SAdrien Mazarguil  *
10636de569f5SAdrien Mazarguil  *   EBUSY: device is not supposed to be spawned.
1064206254b7SOphir Munk  *   EEXIST: device is already spawned
1065771fa900SAdrien Mazarguil  */
1066f38c5457SAdrien Mazarguil static struct rte_eth_dev *
1067f38c5457SAdrien Mazarguil mlx5_dev_spawn(struct rte_device *dpdk_dev,
1068ad74bc61SViacheslav Ovsiienko 	       struct mlx5_dev_spawn_data *spawn,
1069ad74bc61SViacheslav Ovsiienko 	       struct mlx5_dev_config config)
1070771fa900SAdrien Mazarguil {
1071ad74bc61SViacheslav Ovsiienko 	const struct mlx5_switch_info *switch_info = &spawn->info;
107217e19bc4SViacheslav Ovsiienko 	struct mlx5_ibv_shared *sh = NULL;
107368128934SAdrien Mazarguil 	struct ibv_port_attr port_attr;
10746057a10bSAdrien Mazarguil 	struct mlx5dv_context dv_attr = { .comp_mask = 0 };
10759083982cSAdrien Mazarguil 	struct rte_eth_dev *eth_dev = NULL;
1076dbeba4cfSThomas Monjalon 	struct mlx5_priv *priv = NULL;
1077771fa900SAdrien Mazarguil 	int err = 0;
107878c7a16dSYongseok Koh 	unsigned int hw_padding = 0;
1079e192ef80SYaacov Hazan 	unsigned int mps;
1080523f5a74SYongseok Koh 	unsigned int cqe_comp;
1081bc91e8dbSYongseok Koh 	unsigned int cqe_pad = 0;
1082772d3435SXueming Li 	unsigned int tunnel_en = 0;
10831f106da2SMatan Azrad 	unsigned int mpls_en = 0;
10845f8ba81cSXueming Li 	unsigned int swp = 0;
10857d6bf6b8SYongseok Koh 	unsigned int mprq = 0;
10867d6bf6b8SYongseok Koh 	unsigned int mprq_min_stride_size_n = 0;
10877d6bf6b8SYongseok Koh 	unsigned int mprq_max_stride_size_n = 0;
10887d6bf6b8SYongseok Koh 	unsigned int mprq_min_stride_num_n = 0;
10897d6bf6b8SYongseok Koh 	unsigned int mprq_max_stride_num_n = 0;
109068128934SAdrien Mazarguil 	struct ether_addr mac;
109168128934SAdrien Mazarguil 	char name[RTE_ETH_NAME_MAX_LEN];
10922b730263SAdrien Mazarguil 	int own_domain_id = 0;
1093206254b7SOphir Munk 	uint16_t port_id;
10942b730263SAdrien Mazarguil 	unsigned int i;
1095771fa900SAdrien Mazarguil 
10966de569f5SAdrien Mazarguil 	/* Determine if this port representor is supposed to be spawned. */
10976de569f5SAdrien Mazarguil 	if (switch_info->representor && dpdk_dev->devargs) {
10986de569f5SAdrien Mazarguil 		struct rte_eth_devargs eth_da;
10996de569f5SAdrien Mazarguil 
11006de569f5SAdrien Mazarguil 		err = rte_eth_devargs_parse(dpdk_dev->devargs->args, &eth_da);
11016de569f5SAdrien Mazarguil 		if (err) {
11026de569f5SAdrien Mazarguil 			rte_errno = -err;
11036de569f5SAdrien Mazarguil 			DRV_LOG(ERR, "failed to process device arguments: %s",
11046de569f5SAdrien Mazarguil 				strerror(rte_errno));
11056de569f5SAdrien Mazarguil 			return NULL;
11066de569f5SAdrien Mazarguil 		}
11076de569f5SAdrien Mazarguil 		for (i = 0; i < eth_da.nb_representor_ports; ++i)
11086de569f5SAdrien Mazarguil 			if (eth_da.representor_ports[i] ==
11096de569f5SAdrien Mazarguil 			    (uint16_t)switch_info->port_name)
11106de569f5SAdrien Mazarguil 				break;
11116de569f5SAdrien Mazarguil 		if (i == eth_da.nb_representor_ports) {
11126de569f5SAdrien Mazarguil 			rte_errno = EBUSY;
11136de569f5SAdrien Mazarguil 			return NULL;
11146de569f5SAdrien Mazarguil 		}
11156de569f5SAdrien Mazarguil 	}
1116206254b7SOphir Munk 	/* Build device name. */
1117206254b7SOphir Munk 	if (!switch_info->representor)
111809c9c4d2SThomas Monjalon 		strlcpy(name, dpdk_dev->name, sizeof(name));
1119206254b7SOphir Munk 	else
1120206254b7SOphir Munk 		snprintf(name, sizeof(name), "%s_representor_%u",
1121206254b7SOphir Munk 			 dpdk_dev->name, switch_info->port_name);
1122206254b7SOphir Munk 	/* check if the device is already spawned */
1123206254b7SOphir Munk 	if (rte_eth_dev_get_port_by_name(name, &port_id) == 0) {
1124206254b7SOphir Munk 		rte_errno = EEXIST;
1125206254b7SOphir Munk 		return NULL;
1126206254b7SOphir Munk 	}
112717e19bc4SViacheslav Ovsiienko 	DRV_LOG(DEBUG, "naming Ethernet device \"%s\"", name);
112817e19bc4SViacheslav Ovsiienko 	if (rte_eal_process_type() == RTE_PROC_SECONDARY) {
112917e19bc4SViacheslav Ovsiienko 		eth_dev = rte_eth_dev_attach_secondary(name);
113017e19bc4SViacheslav Ovsiienko 		if (eth_dev == NULL) {
113117e19bc4SViacheslav Ovsiienko 			DRV_LOG(ERR, "can not attach rte ethdev");
113217e19bc4SViacheslav Ovsiienko 			rte_errno = ENOMEM;
1133f38c5457SAdrien Mazarguil 			return NULL;
1134771fa900SAdrien Mazarguil 		}
113517e19bc4SViacheslav Ovsiienko 		eth_dev->device = dpdk_dev;
113617e19bc4SViacheslav Ovsiienko 		eth_dev->dev_ops = &mlx5_dev_sec_ops;
1137120dc4a7SYongseok Koh 		err = mlx5_proc_priv_init(eth_dev);
1138120dc4a7SYongseok Koh 		if (err)
1139120dc4a7SYongseok Koh 			return NULL;
114017e19bc4SViacheslav Ovsiienko 		/* Receive command fd from primary process */
11419a8ab29bSYongseok Koh 		err = mlx5_mp_req_verbs_cmd_fd(eth_dev);
114217e19bc4SViacheslav Ovsiienko 		if (err < 0)
114317e19bc4SViacheslav Ovsiienko 			return NULL;
114417e19bc4SViacheslav Ovsiienko 		/* Remap UAR for Tx queues. */
1145120dc4a7SYongseok Koh 		err = mlx5_tx_uar_init_secondary(eth_dev, err);
114617e19bc4SViacheslav Ovsiienko 		if (err)
114717e19bc4SViacheslav Ovsiienko 			return NULL;
114817e19bc4SViacheslav Ovsiienko 		/*
114917e19bc4SViacheslav Ovsiienko 		 * Ethdev pointer is still required as input since
115017e19bc4SViacheslav Ovsiienko 		 * the primary device is not accessible from the
115117e19bc4SViacheslav Ovsiienko 		 * secondary process.
115217e19bc4SViacheslav Ovsiienko 		 */
115317e19bc4SViacheslav Ovsiienko 		eth_dev->rx_pkt_burst = mlx5_select_rx_function(eth_dev);
115417e19bc4SViacheslav Ovsiienko 		eth_dev->tx_pkt_burst = mlx5_select_tx_function(eth_dev);
115517e19bc4SViacheslav Ovsiienko 		return eth_dev;
1156f5bf91deSMoti Haimovsky 	}
115717e19bc4SViacheslav Ovsiienko 	sh = mlx5_alloc_shared_ibctx(spawn);
115817e19bc4SViacheslav Ovsiienko 	if (!sh)
115917e19bc4SViacheslav Ovsiienko 		return NULL;
116017e19bc4SViacheslav Ovsiienko 	config.devx = sh->devx;
11615f8ba81cSXueming Li #ifdef HAVE_IBV_MLX5_MOD_SWP
11626057a10bSAdrien Mazarguil 	dv_attr.comp_mask |= MLX5DV_CONTEXT_MASK_SWP;
11635f8ba81cSXueming Li #endif
116443e9d979SShachar Beiser 	/*
116543e9d979SShachar Beiser 	 * Multi-packet send is supported by ConnectX-4 Lx PF as well
116643e9d979SShachar Beiser 	 * as all ConnectX-5 devices.
116743e9d979SShachar Beiser 	 */
1168038e7251SShahaf Shuler #ifdef HAVE_IBV_DEVICE_TUNNEL_SUPPORT
11696057a10bSAdrien Mazarguil 	dv_attr.comp_mask |= MLX5DV_CONTEXT_MASK_TUNNEL_OFFLOADS;
1170038e7251SShahaf Shuler #endif
11717d6bf6b8SYongseok Koh #ifdef HAVE_IBV_DEVICE_STRIDING_RQ_SUPPORT
11726057a10bSAdrien Mazarguil 	dv_attr.comp_mask |= MLX5DV_CONTEXT_MASK_STRIDING_RQ;
11737d6bf6b8SYongseok Koh #endif
117417e19bc4SViacheslav Ovsiienko 	mlx5_glue->dv_query_device(sh->ctx, &dv_attr);
11756057a10bSAdrien Mazarguil 	if (dv_attr.flags & MLX5DV_CONTEXT_FLAGS_MPW_ALLOWED) {
11766057a10bSAdrien Mazarguil 		if (dv_attr.flags & MLX5DV_CONTEXT_FLAGS_ENHANCED_MPW) {
1177a170a30dSNélio Laranjeiro 			DRV_LOG(DEBUG, "enhanced MPW is supported");
117843e9d979SShachar Beiser 			mps = MLX5_MPW_ENHANCED;
117943e9d979SShachar Beiser 		} else {
1180a170a30dSNélio Laranjeiro 			DRV_LOG(DEBUG, "MPW is supported");
1181e589960cSYongseok Koh 			mps = MLX5_MPW;
1182e589960cSYongseok Koh 		}
1183e589960cSYongseok Koh 	} else {
1184a170a30dSNélio Laranjeiro 		DRV_LOG(DEBUG, "MPW isn't supported");
118543e9d979SShachar Beiser 		mps = MLX5_MPW_DISABLED;
118643e9d979SShachar Beiser 	}
11875f8ba81cSXueming Li #ifdef HAVE_IBV_MLX5_MOD_SWP
11886057a10bSAdrien Mazarguil 	if (dv_attr.comp_mask & MLX5DV_CONTEXT_MASK_SWP)
11896057a10bSAdrien Mazarguil 		swp = dv_attr.sw_parsing_caps.sw_parsing_offloads;
11905f8ba81cSXueming Li 	DRV_LOG(DEBUG, "SWP support: %u", swp);
11915f8ba81cSXueming Li #endif
119268128934SAdrien Mazarguil 	config.swp = !!swp;
11937d6bf6b8SYongseok Koh #ifdef HAVE_IBV_DEVICE_STRIDING_RQ_SUPPORT
11946057a10bSAdrien Mazarguil 	if (dv_attr.comp_mask & MLX5DV_CONTEXT_MASK_STRIDING_RQ) {
11957d6bf6b8SYongseok Koh 		struct mlx5dv_striding_rq_caps mprq_caps =
11966057a10bSAdrien Mazarguil 			dv_attr.striding_rq_caps;
11977d6bf6b8SYongseok Koh 
11987d6bf6b8SYongseok Koh 		DRV_LOG(DEBUG, "\tmin_single_stride_log_num_of_bytes: %d",
11997d6bf6b8SYongseok Koh 			mprq_caps.min_single_stride_log_num_of_bytes);
12007d6bf6b8SYongseok Koh 		DRV_LOG(DEBUG, "\tmax_single_stride_log_num_of_bytes: %d",
12017d6bf6b8SYongseok Koh 			mprq_caps.max_single_stride_log_num_of_bytes);
12027d6bf6b8SYongseok Koh 		DRV_LOG(DEBUG, "\tmin_single_wqe_log_num_of_strides: %d",
12037d6bf6b8SYongseok Koh 			mprq_caps.min_single_wqe_log_num_of_strides);
12047d6bf6b8SYongseok Koh 		DRV_LOG(DEBUG, "\tmax_single_wqe_log_num_of_strides: %d",
12057d6bf6b8SYongseok Koh 			mprq_caps.max_single_wqe_log_num_of_strides);
12067d6bf6b8SYongseok Koh 		DRV_LOG(DEBUG, "\tsupported_qpts: %d",
12077d6bf6b8SYongseok Koh 			mprq_caps.supported_qpts);
12087d6bf6b8SYongseok Koh 		DRV_LOG(DEBUG, "device supports Multi-Packet RQ");
12097d6bf6b8SYongseok Koh 		mprq = 1;
12107d6bf6b8SYongseok Koh 		mprq_min_stride_size_n =
12117d6bf6b8SYongseok Koh 			mprq_caps.min_single_stride_log_num_of_bytes;
12127d6bf6b8SYongseok Koh 		mprq_max_stride_size_n =
12137d6bf6b8SYongseok Koh 			mprq_caps.max_single_stride_log_num_of_bytes;
12147d6bf6b8SYongseok Koh 		mprq_min_stride_num_n =
12157d6bf6b8SYongseok Koh 			mprq_caps.min_single_wqe_log_num_of_strides;
12167d6bf6b8SYongseok Koh 		mprq_max_stride_num_n =
12177d6bf6b8SYongseok Koh 			mprq_caps.max_single_wqe_log_num_of_strides;
121868128934SAdrien Mazarguil 		config.mprq.stride_num_n = RTE_MAX(MLX5_MPRQ_STRIDE_NUM_N,
121968128934SAdrien Mazarguil 						   mprq_min_stride_num_n);
12207d6bf6b8SYongseok Koh 	}
12217d6bf6b8SYongseok Koh #endif
1222523f5a74SYongseok Koh 	if (RTE_CACHE_LINE_SIZE == 128 &&
12236057a10bSAdrien Mazarguil 	    !(dv_attr.flags & MLX5DV_CONTEXT_FLAGS_CQE_128B_COMP))
1224523f5a74SYongseok Koh 		cqe_comp = 0;
1225523f5a74SYongseok Koh 	else
1226523f5a74SYongseok Koh 		cqe_comp = 1;
122768128934SAdrien Mazarguil 	config.cqe_comp = cqe_comp;
1228bc91e8dbSYongseok Koh #ifdef HAVE_IBV_MLX5_MOD_CQE_128B_PAD
1229bc91e8dbSYongseok Koh 	/* Whether device supports 128B Rx CQE padding. */
1230bc91e8dbSYongseok Koh 	cqe_pad = RTE_CACHE_LINE_SIZE == 128 &&
1231bc91e8dbSYongseok Koh 		  (dv_attr.flags & MLX5DV_CONTEXT_FLAGS_CQE_128B_PAD);
1232bc91e8dbSYongseok Koh #endif
1233038e7251SShahaf Shuler #ifdef HAVE_IBV_DEVICE_TUNNEL_SUPPORT
12346057a10bSAdrien Mazarguil 	if (dv_attr.comp_mask & MLX5DV_CONTEXT_MASK_TUNNEL_OFFLOADS) {
12356057a10bSAdrien Mazarguil 		tunnel_en = ((dv_attr.tunnel_offloads_caps &
1236038e7251SShahaf Shuler 			      MLX5DV_RAW_PACKET_CAP_TUNNELED_OFFLOAD_VXLAN) &&
12376057a10bSAdrien Mazarguil 			     (dv_attr.tunnel_offloads_caps &
1238038e7251SShahaf Shuler 			      MLX5DV_RAW_PACKET_CAP_TUNNELED_OFFLOAD_GRE));
1239038e7251SShahaf Shuler 	}
1240a170a30dSNélio Laranjeiro 	DRV_LOG(DEBUG, "tunnel offloading is %ssupported",
1241a170a30dSNélio Laranjeiro 		tunnel_en ? "" : "not ");
1242038e7251SShahaf Shuler #else
1243a170a30dSNélio Laranjeiro 	DRV_LOG(WARNING,
1244a170a30dSNélio Laranjeiro 		"tunnel offloading disabled due to old OFED/rdma-core version");
1245038e7251SShahaf Shuler #endif
124668128934SAdrien Mazarguil 	config.tunnel_en = tunnel_en;
12471f106da2SMatan Azrad #ifdef HAVE_IBV_DEVICE_MPLS_SUPPORT
12486057a10bSAdrien Mazarguil 	mpls_en = ((dv_attr.tunnel_offloads_caps &
12491f106da2SMatan Azrad 		    MLX5DV_RAW_PACKET_CAP_TUNNELED_OFFLOAD_CW_MPLS_OVER_GRE) &&
12506057a10bSAdrien Mazarguil 		   (dv_attr.tunnel_offloads_caps &
12511f106da2SMatan Azrad 		    MLX5DV_RAW_PACKET_CAP_TUNNELED_OFFLOAD_CW_MPLS_OVER_UDP));
12521f106da2SMatan Azrad 	DRV_LOG(DEBUG, "MPLS over GRE/UDP tunnel offloading is %ssupported",
12531f106da2SMatan Azrad 		mpls_en ? "" : "not ");
12541f106da2SMatan Azrad #else
12551f106da2SMatan Azrad 	DRV_LOG(WARNING, "MPLS over GRE/UDP tunnel offloading disabled due to"
12561f106da2SMatan Azrad 		" old OFED/rdma-core version or firmware configuration");
12571f106da2SMatan Azrad #endif
125868128934SAdrien Mazarguil 	config.mpls_en = mpls_en;
1259771fa900SAdrien Mazarguil 	/* Check port status. */
126017e19bc4SViacheslav Ovsiienko 	err = mlx5_glue->query_port(sh->ctx, spawn->ibv_port, &port_attr);
1261771fa900SAdrien Mazarguil 	if (err) {
1262a170a30dSNélio Laranjeiro 		DRV_LOG(ERR, "port query failed: %s", strerror(err));
12639083982cSAdrien Mazarguil 		goto error;
1264771fa900SAdrien Mazarguil 	}
12651371f4dfSOr Ami 	if (port_attr.link_layer != IBV_LINK_LAYER_ETHERNET) {
12669083982cSAdrien Mazarguil 		DRV_LOG(ERR, "port is not configured in Ethernet mode");
1267e1c3e305SMatan Azrad 		err = EINVAL;
12689083982cSAdrien Mazarguil 		goto error;
12691371f4dfSOr Ami 	}
1270771fa900SAdrien Mazarguil 	if (port_attr.state != IBV_PORT_ACTIVE)
12719083982cSAdrien Mazarguil 		DRV_LOG(DEBUG, "port is not active: \"%s\" (%d)",
1272a170a30dSNélio Laranjeiro 			mlx5_glue->port_state_str(port_attr.state),
1273771fa900SAdrien Mazarguil 			port_attr.state);
127417e19bc4SViacheslav Ovsiienko 	/* Allocate private eth device data. */
1275771fa900SAdrien Mazarguil 	priv = rte_zmalloc("ethdev private structure",
1276771fa900SAdrien Mazarguil 			   sizeof(*priv),
1277771fa900SAdrien Mazarguil 			   RTE_CACHE_LINE_SIZE);
1278771fa900SAdrien Mazarguil 	if (priv == NULL) {
1279a170a30dSNélio Laranjeiro 		DRV_LOG(ERR, "priv allocation failure");
1280771fa900SAdrien Mazarguil 		err = ENOMEM;
12819083982cSAdrien Mazarguil 		goto error;
1282771fa900SAdrien Mazarguil 	}
128317e19bc4SViacheslav Ovsiienko 	priv->sh = sh;
128417e19bc4SViacheslav Ovsiienko 	priv->ibv_port = spawn->ibv_port;
1285771fa900SAdrien Mazarguil 	priv->mtu = ETHER_MTU;
12866bf10ab6SMoti Haimovsky #ifndef RTE_ARCH_64
12876bf10ab6SMoti Haimovsky 	/* Initialize UAR access locks for 32bit implementations. */
12886bf10ab6SMoti Haimovsky 	rte_spinlock_init(&priv->uar_lock_cq);
12896bf10ab6SMoti Haimovsky 	for (i = 0; i < MLX5_UAR_PAGE_NUM_MAX; i++)
12906bf10ab6SMoti Haimovsky 		rte_spinlock_init(&priv->uar_lock[i]);
12916bf10ab6SMoti Haimovsky #endif
129226c08b97SAdrien Mazarguil 	/* Some internal functions rely on Netlink sockets, open them now. */
12935366074bSNelio Laranjeiro 	priv->nl_socket_rdma = mlx5_nl_init(NETLINK_RDMA);
12945366074bSNelio Laranjeiro 	priv->nl_socket_route =	mlx5_nl_init(NETLINK_ROUTE);
129526c08b97SAdrien Mazarguil 	priv->nl_sn = 0;
12962b730263SAdrien Mazarguil 	priv->representor = !!switch_info->representor;
1297299d7dc2SViacheslav Ovsiienko 	priv->master = !!switch_info->master;
12982b730263SAdrien Mazarguil 	priv->domain_id = RTE_ETH_DEV_SWITCH_DOMAIN_ID_INVALID;
1299299d7dc2SViacheslav Ovsiienko 	/*
1300299d7dc2SViacheslav Ovsiienko 	 * Currently we support single E-Switch per PF configurations
1301299d7dc2SViacheslav Ovsiienko 	 * only and vport_id field contains the vport index for
1302299d7dc2SViacheslav Ovsiienko 	 * associated VF, which is deduced from representor port name.
1303ae4eb7dcSViacheslav Ovsiienko 	 * For example, let's have the IB device port 10, it has
1304299d7dc2SViacheslav Ovsiienko 	 * attached network device eth0, which has port name attribute
1305299d7dc2SViacheslav Ovsiienko 	 * pf0vf2, we can deduce the VF number as 2, and set vport index
1306299d7dc2SViacheslav Ovsiienko 	 * as 3 (2+1). This assigning schema should be changed if the
1307299d7dc2SViacheslav Ovsiienko 	 * multiple E-Switch instances per PF configurations or/and PCI
1308299d7dc2SViacheslav Ovsiienko 	 * subfunctions are added.
1309299d7dc2SViacheslav Ovsiienko 	 */
1310299d7dc2SViacheslav Ovsiienko 	priv->vport_id = switch_info->representor ?
1311299d7dc2SViacheslav Ovsiienko 			 switch_info->port_name + 1 : -1;
1312299d7dc2SViacheslav Ovsiienko 	/* representor_id field keeps the unmodified port/VF index. */
1313299d7dc2SViacheslav Ovsiienko 	priv->representor_id = switch_info->representor ?
1314299d7dc2SViacheslav Ovsiienko 			       switch_info->port_name : -1;
13152b730263SAdrien Mazarguil 	/*
13162b730263SAdrien Mazarguil 	 * Look for sibling devices in order to reuse their switch domain
13172b730263SAdrien Mazarguil 	 * if any, otherwise allocate one.
13182b730263SAdrien Mazarguil 	 */
1319d874a4eeSThomas Monjalon 	RTE_ETH_FOREACH_DEV_OF(port_id, dpdk_dev) {
1320dbeba4cfSThomas Monjalon 		const struct mlx5_priv *opriv =
1321d874a4eeSThomas Monjalon 			rte_eth_devices[port_id].data->dev_private;
13222b730263SAdrien Mazarguil 
13232b730263SAdrien Mazarguil 		if (!opriv ||
13242b730263SAdrien Mazarguil 			opriv->domain_id ==
13252b730263SAdrien Mazarguil 			RTE_ETH_DEV_SWITCH_DOMAIN_ID_INVALID)
13262b730263SAdrien Mazarguil 			continue;
13272b730263SAdrien Mazarguil 		priv->domain_id = opriv->domain_id;
13282b730263SAdrien Mazarguil 		break;
13292b730263SAdrien Mazarguil 	}
13302b730263SAdrien Mazarguil 	if (priv->domain_id == RTE_ETH_DEV_SWITCH_DOMAIN_ID_INVALID) {
13312b730263SAdrien Mazarguil 		err = rte_eth_switch_domain_alloc(&priv->domain_id);
13322b730263SAdrien Mazarguil 		if (err) {
13332b730263SAdrien Mazarguil 			err = rte_errno;
13342b730263SAdrien Mazarguil 			DRV_LOG(ERR, "unable to allocate switch domain: %s",
13352b730263SAdrien Mazarguil 				strerror(rte_errno));
13362b730263SAdrien Mazarguil 			goto error;
13372b730263SAdrien Mazarguil 		}
13382b730263SAdrien Mazarguil 		own_domain_id = 1;
13392b730263SAdrien Mazarguil 	}
1340f38c5457SAdrien Mazarguil 	err = mlx5_args(&config, dpdk_dev->devargs);
1341e72dd09bSNélio Laranjeiro 	if (err) {
1342012ad994SShahaf Shuler 		err = rte_errno;
134393068a9dSAdrien Mazarguil 		DRV_LOG(ERR, "failed to process device arguments: %s",
134493068a9dSAdrien Mazarguil 			strerror(rte_errno));
13459083982cSAdrien Mazarguil 		goto error;
1346e72dd09bSNélio Laranjeiro 	}
134717e19bc4SViacheslav Ovsiienko 	config.hw_csum = !!(sh->device_attr.device_cap_flags_ex &
134817e19bc4SViacheslav Ovsiienko 			    IBV_DEVICE_RAW_IP_CSUM);
1349a170a30dSNélio Laranjeiro 	DRV_LOG(DEBUG, "checksum offloading is %ssupported",
13507fe24446SShahaf Shuler 		(config.hw_csum ? "" : "not "));
13512dd8b721SViacheslav Ovsiienko #if !defined(HAVE_IBV_DEVICE_COUNTERS_SET_V42) && \
13522dd8b721SViacheslav Ovsiienko 	!defined(HAVE_IBV_DEVICE_COUNTERS_SET_V45)
13532dd8b721SViacheslav Ovsiienko 	DRV_LOG(DEBUG, "counters are not supported");
13549a761de8SOri Kam #endif
135558b1312eSYongseok Koh #ifndef HAVE_IBV_FLOW_DV_SUPPORT
135658b1312eSYongseok Koh 	if (config.dv_flow_en) {
135758b1312eSYongseok Koh 		DRV_LOG(WARNING, "DV flow is not supported");
135858b1312eSYongseok Koh 		config.dv_flow_en = 0;
135958b1312eSYongseok Koh 	}
136058b1312eSYongseok Koh #endif
13617fe24446SShahaf Shuler 	config.ind_table_max_size =
136217e19bc4SViacheslav Ovsiienko 		sh->device_attr.rss_caps.max_rwq_indirection_table_size;
136368128934SAdrien Mazarguil 	/*
136468128934SAdrien Mazarguil 	 * Remove this check once DPDK supports larger/variable
136568128934SAdrien Mazarguil 	 * indirection tables.
136668128934SAdrien Mazarguil 	 */
136768128934SAdrien Mazarguil 	if (config.ind_table_max_size > (unsigned int)ETH_RSS_RETA_SIZE_512)
13687fe24446SShahaf Shuler 		config.ind_table_max_size = ETH_RSS_RETA_SIZE_512;
1369a170a30dSNélio Laranjeiro 	DRV_LOG(DEBUG, "maximum Rx indirection table size is %u",
13707fe24446SShahaf Shuler 		config.ind_table_max_size);
137117e19bc4SViacheslav Ovsiienko 	config.hw_vlan_strip = !!(sh->device_attr.raw_packet_caps &
137243e9d979SShachar Beiser 				  IBV_RAW_PACKET_CAP_CVLAN_STRIPPING);
1373a170a30dSNélio Laranjeiro 	DRV_LOG(DEBUG, "VLAN stripping is %ssupported",
13747fe24446SShahaf Shuler 		(config.hw_vlan_strip ? "" : "not "));
137517e19bc4SViacheslav Ovsiienko 	config.hw_fcs_strip = !!(sh->device_attr.raw_packet_caps &
1376cd230a3eSShahaf Shuler 				 IBV_RAW_PACKET_CAP_SCATTER_FCS);
1377a170a30dSNélio Laranjeiro 	DRV_LOG(DEBUG, "FCS stripping configuration is %ssupported",
13787fe24446SShahaf Shuler 		(config.hw_fcs_strip ? "" : "not "));
13792014a7fbSYongseok Koh #if defined(HAVE_IBV_WQ_FLAG_RX_END_PADDING)
138017e19bc4SViacheslav Ovsiienko 	hw_padding = !!sh->device_attr.rx_pad_end_addr_align;
13812014a7fbSYongseok Koh #elif defined(HAVE_IBV_WQ_FLAGS_PCI_WRITE_END_PADDING)
138217e19bc4SViacheslav Ovsiienko 	hw_padding = !!(sh->device_attr.device_cap_flags_ex &
13832014a7fbSYongseok Koh 			IBV_DEVICE_PCI_WRITE_END_PADDING);
138443e9d979SShachar Beiser #endif
138578c7a16dSYongseok Koh 	if (config.hw_padding && !hw_padding) {
138678c7a16dSYongseok Koh 		DRV_LOG(DEBUG, "Rx end alignment padding isn't supported");
138778c7a16dSYongseok Koh 		config.hw_padding = 0;
138878c7a16dSYongseok Koh 	} else if (config.hw_padding) {
138978c7a16dSYongseok Koh 		DRV_LOG(DEBUG, "Rx end alignment padding is enabled");
139078c7a16dSYongseok Koh 	}
139117e19bc4SViacheslav Ovsiienko 	config.tso = (sh->device_attr.tso_caps.max_tso > 0 &&
139217e19bc4SViacheslav Ovsiienko 		      (sh->device_attr.tso_caps.supported_qpts &
139343e9d979SShachar Beiser 		       (1 << IBV_QPT_RAW_PACKET)));
13947fe24446SShahaf Shuler 	if (config.tso)
139517e19bc4SViacheslav Ovsiienko 		config.tso_max_payload_sz = sh->device_attr.tso_caps.max_tso;
1396f9de8718SShahaf Shuler 	/*
1397f9de8718SShahaf Shuler 	 * MPW is disabled by default, while the Enhanced MPW is enabled
1398f9de8718SShahaf Shuler 	 * by default.
1399f9de8718SShahaf Shuler 	 */
1400f9de8718SShahaf Shuler 	if (config.mps == MLX5_ARG_UNSET)
1401f9de8718SShahaf Shuler 		config.mps = (mps == MLX5_MPW_ENHANCED) ? MLX5_MPW_ENHANCED :
1402f9de8718SShahaf Shuler 							  MLX5_MPW_DISABLED;
1403f9de8718SShahaf Shuler 	else
1404f9de8718SShahaf Shuler 		config.mps = config.mps ? mps : MLX5_MPW_DISABLED;
1405a170a30dSNélio Laranjeiro 	DRV_LOG(INFO, "%sMPS is %s",
14060f99970bSNélio Laranjeiro 		config.mps == MLX5_MPW_ENHANCED ? "enhanced " : "",
140768128934SAdrien Mazarguil 		config.mps != MLX5_MPW_DISABLED ? "enabled" : "disabled");
14087fe24446SShahaf Shuler 	if (config.cqe_comp && !cqe_comp) {
1409a170a30dSNélio Laranjeiro 		DRV_LOG(WARNING, "Rx CQE compression isn't supported");
14107fe24446SShahaf Shuler 		config.cqe_comp = 0;
1411523f5a74SYongseok Koh 	}
1412bc91e8dbSYongseok Koh 	if (config.cqe_pad && !cqe_pad) {
1413bc91e8dbSYongseok Koh 		DRV_LOG(WARNING, "Rx CQE padding isn't supported");
1414bc91e8dbSYongseok Koh 		config.cqe_pad = 0;
1415bc91e8dbSYongseok Koh 	} else if (config.cqe_pad) {
1416bc91e8dbSYongseok Koh 		DRV_LOG(INFO, "Rx CQE padding is enabled");
1417bc91e8dbSYongseok Koh 	}
14185c0e2db6SYongseok Koh 	if (config.mprq.enabled && mprq) {
14197d6bf6b8SYongseok Koh 		if (config.mprq.stride_num_n > mprq_max_stride_num_n ||
14207d6bf6b8SYongseok Koh 		    config.mprq.stride_num_n < mprq_min_stride_num_n) {
14217d6bf6b8SYongseok Koh 			config.mprq.stride_num_n =
14227d6bf6b8SYongseok Koh 				RTE_MAX(MLX5_MPRQ_STRIDE_NUM_N,
14237d6bf6b8SYongseok Koh 					mprq_min_stride_num_n);
14247d6bf6b8SYongseok Koh 			DRV_LOG(WARNING,
14257d6bf6b8SYongseok Koh 				"the number of strides"
14267d6bf6b8SYongseok Koh 				" for Multi-Packet RQ is out of range,"
14277d6bf6b8SYongseok Koh 				" setting default value (%u)",
14287d6bf6b8SYongseok Koh 				1 << config.mprq.stride_num_n);
14297d6bf6b8SYongseok Koh 		}
14307d6bf6b8SYongseok Koh 		config.mprq.min_stride_size_n = mprq_min_stride_size_n;
14317d6bf6b8SYongseok Koh 		config.mprq.max_stride_size_n = mprq_max_stride_size_n;
14325c0e2db6SYongseok Koh 	} else if (config.mprq.enabled && !mprq) {
14335c0e2db6SYongseok Koh 		DRV_LOG(WARNING, "Multi-Packet RQ isn't supported");
14345c0e2db6SYongseok Koh 		config.mprq.enabled = 0;
14357d6bf6b8SYongseok Koh 	}
1436af4f09f2SNélio Laranjeiro 	eth_dev = rte_eth_dev_allocate(name);
1437af4f09f2SNélio Laranjeiro 	if (eth_dev == NULL) {
1438a170a30dSNélio Laranjeiro 		DRV_LOG(ERR, "can not allocate rte ethdev");
1439af4f09f2SNélio Laranjeiro 		err = ENOMEM;
14409083982cSAdrien Mazarguil 		goto error;
1441af4f09f2SNélio Laranjeiro 	}
144215febafdSThomas Monjalon 	/* Flag to call rte_eth_dev_release_port() in rte_eth_dev_close(). */
144315febafdSThomas Monjalon 	eth_dev->data->dev_flags |= RTE_ETH_DEV_CLOSE_REMOVE;
1444a7d3c627SThomas Monjalon 	if (priv->representor) {
14452b730263SAdrien Mazarguil 		eth_dev->data->dev_flags |= RTE_ETH_DEV_REPRESENTOR;
1446a7d3c627SThomas Monjalon 		eth_dev->data->representor_id = priv->representor_id;
1447a7d3c627SThomas Monjalon 	}
1448af4f09f2SNélio Laranjeiro 	eth_dev->data->dev_private = priv;
1449df428ceeSYongseok Koh 	priv->dev_data = eth_dev->data;
1450af4f09f2SNélio Laranjeiro 	eth_dev->data->mac_addrs = priv->mac;
1451f38c5457SAdrien Mazarguil 	eth_dev->device = dpdk_dev;
1452771fa900SAdrien Mazarguil 	/* Configure the first MAC address by default. */
1453af4f09f2SNélio Laranjeiro 	if (mlx5_get_mac(eth_dev, &mac.addr_bytes)) {
1454a170a30dSNélio Laranjeiro 		DRV_LOG(ERR,
1455a170a30dSNélio Laranjeiro 			"port %u cannot get MAC address, is mlx5_en"
1456a170a30dSNélio Laranjeiro 			" loaded? (errno: %s)",
14578c3c2372SAdrien Mazarguil 			eth_dev->data->port_id, strerror(rte_errno));
1458e1c3e305SMatan Azrad 		err = ENODEV;
14599083982cSAdrien Mazarguil 		goto error;
1460771fa900SAdrien Mazarguil 	}
1461a170a30dSNélio Laranjeiro 	DRV_LOG(INFO,
1462a170a30dSNélio Laranjeiro 		"port %u MAC address is %02x:%02x:%02x:%02x:%02x:%02x",
14630f99970bSNélio Laranjeiro 		eth_dev->data->port_id,
1464771fa900SAdrien Mazarguil 		mac.addr_bytes[0], mac.addr_bytes[1],
1465771fa900SAdrien Mazarguil 		mac.addr_bytes[2], mac.addr_bytes[3],
1466771fa900SAdrien Mazarguil 		mac.addr_bytes[4], mac.addr_bytes[5]);
1467771fa900SAdrien Mazarguil #ifndef NDEBUG
1468771fa900SAdrien Mazarguil 	{
1469771fa900SAdrien Mazarguil 		char ifname[IF_NAMESIZE];
1470771fa900SAdrien Mazarguil 
1471af4f09f2SNélio Laranjeiro 		if (mlx5_get_ifname(eth_dev, &ifname) == 0)
1472a170a30dSNélio Laranjeiro 			DRV_LOG(DEBUG, "port %u ifname is \"%s\"",
14730f99970bSNélio Laranjeiro 				eth_dev->data->port_id, ifname);
1474771fa900SAdrien Mazarguil 		else
1475a170a30dSNélio Laranjeiro 			DRV_LOG(DEBUG, "port %u ifname is unknown",
14760f99970bSNélio Laranjeiro 				eth_dev->data->port_id);
1477771fa900SAdrien Mazarguil 	}
1478771fa900SAdrien Mazarguil #endif
1479771fa900SAdrien Mazarguil 	/* Get actual MTU if possible. */
1480a6d83b6aSNélio Laranjeiro 	err = mlx5_get_mtu(eth_dev, &priv->mtu);
1481012ad994SShahaf Shuler 	if (err) {
1482012ad994SShahaf Shuler 		err = rte_errno;
14839083982cSAdrien Mazarguil 		goto error;
1484012ad994SShahaf Shuler 	}
1485a170a30dSNélio Laranjeiro 	DRV_LOG(DEBUG, "port %u MTU is %u", eth_dev->data->port_id,
1486a170a30dSNélio Laranjeiro 		priv->mtu);
148768128934SAdrien Mazarguil 	/* Initialize burst functions to prevent crashes before link-up. */
1488e313ef4cSShahaf Shuler 	eth_dev->rx_pkt_burst = removed_rx_burst;
1489e313ef4cSShahaf Shuler 	eth_dev->tx_pkt_burst = removed_tx_burst;
1490771fa900SAdrien Mazarguil 	eth_dev->dev_ops = &mlx5_dev_ops;
1491272733b5SNélio Laranjeiro 	/* Register MAC address. */
1492272733b5SNélio Laranjeiro 	claim_zero(mlx5_mac_addr_add(eth_dev, &mac, 0, 0));
1493f87bfa8eSYongseok Koh 	if (config.vf && config.vf_nl_en)
1494ccdcba53SNélio Laranjeiro 		mlx5_nl_mac_addr_sync(eth_dev);
1495d53180afSMoti Haimovsky 	priv->tcf_context = mlx5_flow_tcf_context_create();
1496d53180afSMoti Haimovsky 	if (!priv->tcf_context) {
149757123c00SYongseok Koh 		err = -rte_errno;
149857123c00SYongseok Koh 		DRV_LOG(WARNING,
149957123c00SYongseok Koh 			"flow rules relying on switch offloads will not be"
150057123c00SYongseok Koh 			" supported: cannot open libmnl socket: %s",
150157123c00SYongseok Koh 			strerror(rte_errno));
150257123c00SYongseok Koh 	} else {
150357123c00SYongseok Koh 		struct rte_flow_error error;
150457123c00SYongseok Koh 		unsigned int ifindex = mlx5_ifindex(eth_dev);
150557123c00SYongseok Koh 
150657123c00SYongseok Koh 		if (!ifindex) {
150757123c00SYongseok Koh 			err = -rte_errno;
150857123c00SYongseok Koh 			error.message =
150957123c00SYongseok Koh 				"cannot retrieve network interface index";
151057123c00SYongseok Koh 		} else {
1511d53180afSMoti Haimovsky 			err = mlx5_flow_tcf_init(priv->tcf_context,
1512d53180afSMoti Haimovsky 						 ifindex, &error);
151357123c00SYongseok Koh 		}
151457123c00SYongseok Koh 		if (err) {
151557123c00SYongseok Koh 			DRV_LOG(WARNING,
151657123c00SYongseok Koh 				"flow rules relying on switch offloads will"
151757123c00SYongseok Koh 				" not be supported: %s: %s",
151857123c00SYongseok Koh 				error.message, strerror(rte_errno));
1519d53180afSMoti Haimovsky 			mlx5_flow_tcf_context_destroy(priv->tcf_context);
1520d53180afSMoti Haimovsky 			priv->tcf_context = NULL;
152157123c00SYongseok Koh 		}
152257123c00SYongseok Koh 	}
1523c8ffb8a9SNélio Laranjeiro 	TAILQ_INIT(&priv->flows);
15241b37f5d8SNélio Laranjeiro 	TAILQ_INIT(&priv->ctrl_flows);
15251e3a39f7SXueming Li 	/* Hint libmlx5 to use PMD allocator for data plane resources */
15261e3a39f7SXueming Li 	struct mlx5dv_ctx_allocators alctr = {
15271e3a39f7SXueming Li 		.alloc = &mlx5_alloc_verbs_buf,
15281e3a39f7SXueming Li 		.free = &mlx5_free_verbs_buf,
15291e3a39f7SXueming Li 		.data = priv,
15301e3a39f7SXueming Li 	};
153117e19bc4SViacheslav Ovsiienko 	mlx5_glue->dv_set_context_attr(sh->ctx,
153217e19bc4SViacheslav Ovsiienko 				       MLX5DV_CTX_ATTR_BUF_ALLOCATORS,
15331e3a39f7SXueming Li 				       (void *)((uintptr_t)&alctr));
1534771fa900SAdrien Mazarguil 	/* Bring Ethernet device up. */
1535a170a30dSNélio Laranjeiro 	DRV_LOG(DEBUG, "port %u forcing Ethernet interface up",
15360f99970bSNélio Laranjeiro 		eth_dev->data->port_id);
15377ba5320bSNélio Laranjeiro 	mlx5_set_link_up(eth_dev);
1538a85a606cSShahaf Shuler 	/*
1539a85a606cSShahaf Shuler 	 * Even though the interrupt handler is not installed yet,
1540ae4eb7dcSViacheslav Ovsiienko 	 * interrupts will still trigger on the async_fd from
1541a85a606cSShahaf Shuler 	 * Verbs context returned by ibv_open_device().
1542a85a606cSShahaf Shuler 	 */
1543a85a606cSShahaf Shuler 	mlx5_link_update(eth_dev, 0);
1544e2b4925eSOri Kam #ifdef HAVE_IBV_DEVX_OBJ
1545f4a9349dSViacheslav Ovsiienko 	if (config.devx) {
1546e2b4925eSOri Kam 		err = mlx5_devx_cmd_query_hca_attr(sh->ctx, &config.hca_attr);
1547e2b4925eSOri Kam 		if (err) {
1548e2b4925eSOri Kam 			err = -err;
1549e2b4925eSOri Kam 			goto error;
1550e2b4925eSOri Kam 		}
1551f4a9349dSViacheslav Ovsiienko 	}
1552e2b4925eSOri Kam #endif
1553e2b4925eSOri Kam #ifdef HAVE_MLX5DV_DR_ESWITCH
1554e2b4925eSOri Kam 	if (!(config.hca_attr.eswitch_manager && config.dv_flow_en &&
1555e2b4925eSOri Kam 	      (switch_info->representor || switch_info->master)))
1556e2b4925eSOri Kam 		config.dv_esw_en = 0;
1557e2b4925eSOri Kam #else
1558e2b4925eSOri Kam 	config.dv_esw_en = 0;
1559e2b4925eSOri Kam #endif
15607fe24446SShahaf Shuler 	/* Store device configuration on private structure. */
15617fe24446SShahaf Shuler 	priv->config = config;
1562e2b4925eSOri Kam 	if (config.dv_flow_en) {
1563e2b4925eSOri Kam 		err = mlx5_alloc_shared_dr(priv);
1564e2b4925eSOri Kam 		if (err)
1565e2b4925eSOri Kam 			goto error;
1566e2b4925eSOri Kam 	}
156778be8852SNelio Laranjeiro 	/* Supported Verbs flow priority number detection. */
15682815702bSNelio Laranjeiro 	err = mlx5_flow_discover_priorities(eth_dev);
15694fb27c1dSViacheslav Ovsiienko 	if (err < 0) {
15704fb27c1dSViacheslav Ovsiienko 		err = -err;
15719083982cSAdrien Mazarguil 		goto error;
15724fb27c1dSViacheslav Ovsiienko 	}
15732815702bSNelio Laranjeiro 	priv->config.flow_prio = err;
1574e89c15b6SAdrien Mazarguil 	/* Add device to memory callback list. */
1575e89c15b6SAdrien Mazarguil 	rte_rwlock_write_lock(&mlx5_shared_data->mem_event_rwlock);
1576e89c15b6SAdrien Mazarguil 	LIST_INSERT_HEAD(&mlx5_shared_data->mem_event_cb_list,
1577ccb38153SViacheslav Ovsiienko 			 sh, mem_event_cb);
1578e89c15b6SAdrien Mazarguil 	rte_rwlock_write_unlock(&mlx5_shared_data->mem_event_rwlock);
1579f38c5457SAdrien Mazarguil 	return eth_dev;
15809083982cSAdrien Mazarguil error:
158126c08b97SAdrien Mazarguil 	if (priv) {
1582b2177648SViacheslav Ovsiienko 		if (priv->sh)
1583b2177648SViacheslav Ovsiienko 			mlx5_free_shared_dr(priv);
158426c08b97SAdrien Mazarguil 		if (priv->nl_socket_route >= 0)
158526c08b97SAdrien Mazarguil 			close(priv->nl_socket_route);
158626c08b97SAdrien Mazarguil 		if (priv->nl_socket_rdma >= 0)
158726c08b97SAdrien Mazarguil 			close(priv->nl_socket_rdma);
1588d53180afSMoti Haimovsky 		if (priv->tcf_context)
1589d53180afSMoti Haimovsky 			mlx5_flow_tcf_context_destroy(priv->tcf_context);
15902b730263SAdrien Mazarguil 		if (own_domain_id)
15912b730263SAdrien Mazarguil 			claim_zero(rte_eth_switch_domain_free(priv->domain_id));
1592771fa900SAdrien Mazarguil 		rte_free(priv);
1593e16adf08SThomas Monjalon 		if (eth_dev != NULL)
1594e16adf08SThomas Monjalon 			eth_dev->data->dev_private = NULL;
159526c08b97SAdrien Mazarguil 	}
1596e16adf08SThomas Monjalon 	if (eth_dev != NULL) {
1597e16adf08SThomas Monjalon 		/* mac_addrs must not be freed alone because part of dev_private */
1598e16adf08SThomas Monjalon 		eth_dev->data->mac_addrs = NULL;
1599690de285SRaslan Darawsheh 		rte_eth_dev_release_port(eth_dev);
1600e16adf08SThomas Monjalon 	}
160117e19bc4SViacheslav Ovsiienko 	if (sh)
160217e19bc4SViacheslav Ovsiienko 		mlx5_free_shared_ibctx(sh);
1603f38c5457SAdrien Mazarguil 	assert(err > 0);
1604a6d83b6aSNélio Laranjeiro 	rte_errno = err;
1605f38c5457SAdrien Mazarguil 	return NULL;
1606f38c5457SAdrien Mazarguil }
1607f38c5457SAdrien Mazarguil 
1608116f90adSAdrien Mazarguil /**
1609116f90adSAdrien Mazarguil  * Comparison callback to sort device data.
1610116f90adSAdrien Mazarguil  *
1611116f90adSAdrien Mazarguil  * This is meant to be used with qsort().
1612116f90adSAdrien Mazarguil  *
1613116f90adSAdrien Mazarguil  * @param a[in]
1614116f90adSAdrien Mazarguil  *   Pointer to pointer to first data object.
1615116f90adSAdrien Mazarguil  * @param b[in]
1616116f90adSAdrien Mazarguil  *   Pointer to pointer to second data object.
1617116f90adSAdrien Mazarguil  *
1618116f90adSAdrien Mazarguil  * @return
1619116f90adSAdrien Mazarguil  *   0 if both objects are equal, less than 0 if the first argument is less
1620116f90adSAdrien Mazarguil  *   than the second, greater than 0 otherwise.
1621116f90adSAdrien Mazarguil  */
1622116f90adSAdrien Mazarguil static int
1623116f90adSAdrien Mazarguil mlx5_dev_spawn_data_cmp(const void *a, const void *b)
1624116f90adSAdrien Mazarguil {
1625116f90adSAdrien Mazarguil 	const struct mlx5_switch_info *si_a =
1626116f90adSAdrien Mazarguil 		&((const struct mlx5_dev_spawn_data *)a)->info;
1627116f90adSAdrien Mazarguil 	const struct mlx5_switch_info *si_b =
1628116f90adSAdrien Mazarguil 		&((const struct mlx5_dev_spawn_data *)b)->info;
1629116f90adSAdrien Mazarguil 	int ret;
1630116f90adSAdrien Mazarguil 
1631116f90adSAdrien Mazarguil 	/* Master device first. */
1632116f90adSAdrien Mazarguil 	ret = si_b->master - si_a->master;
1633116f90adSAdrien Mazarguil 	if (ret)
1634116f90adSAdrien Mazarguil 		return ret;
1635116f90adSAdrien Mazarguil 	/* Then representor devices. */
1636116f90adSAdrien Mazarguil 	ret = si_b->representor - si_a->representor;
1637116f90adSAdrien Mazarguil 	if (ret)
1638116f90adSAdrien Mazarguil 		return ret;
1639116f90adSAdrien Mazarguil 	/* Unidentified devices come last in no specific order. */
1640116f90adSAdrien Mazarguil 	if (!si_a->representor)
1641116f90adSAdrien Mazarguil 		return 0;
1642116f90adSAdrien Mazarguil 	/* Order representors by name. */
1643116f90adSAdrien Mazarguil 	return si_a->port_name - si_b->port_name;
1644116f90adSAdrien Mazarguil }
1645116f90adSAdrien Mazarguil 
1646f38c5457SAdrien Mazarguil /**
1647f38c5457SAdrien Mazarguil  * DPDK callback to register a PCI device.
1648f38c5457SAdrien Mazarguil  *
16492b730263SAdrien Mazarguil  * This function spawns Ethernet devices out of a given PCI device.
1650f38c5457SAdrien Mazarguil  *
1651f38c5457SAdrien Mazarguil  * @param[in] pci_drv
1652f38c5457SAdrien Mazarguil  *   PCI driver structure (mlx5_driver).
1653f38c5457SAdrien Mazarguil  * @param[in] pci_dev
1654f38c5457SAdrien Mazarguil  *   PCI device information.
1655f38c5457SAdrien Mazarguil  *
1656f38c5457SAdrien Mazarguil  * @return
1657f38c5457SAdrien Mazarguil  *   0 on success, a negative errno value otherwise and rte_errno is set.
1658f38c5457SAdrien Mazarguil  */
1659f38c5457SAdrien Mazarguil static int
1660f38c5457SAdrien Mazarguil mlx5_pci_probe(struct rte_pci_driver *pci_drv __rte_unused,
1661f38c5457SAdrien Mazarguil 	       struct rte_pci_device *pci_dev)
1662f38c5457SAdrien Mazarguil {
1663f38c5457SAdrien Mazarguil 	struct ibv_device **ibv_list;
1664ad74bc61SViacheslav Ovsiienko 	/*
1665ad74bc61SViacheslav Ovsiienko 	 * Number of found IB Devices matching with requested PCI BDF.
1666ad74bc61SViacheslav Ovsiienko 	 * nd != 1 means there are multiple IB devices over the same
1667ad74bc61SViacheslav Ovsiienko 	 * PCI device and we have representors and master.
1668ad74bc61SViacheslav Ovsiienko 	 */
1669ad74bc61SViacheslav Ovsiienko 	unsigned int nd = 0;
1670ad74bc61SViacheslav Ovsiienko 	/*
1671ad74bc61SViacheslav Ovsiienko 	 * Number of found IB device Ports. nd = 1 and np = 1..n means
1672ad74bc61SViacheslav Ovsiienko 	 * we have the single multiport IB device, and there may be
1673ad74bc61SViacheslav Ovsiienko 	 * representors attached to some of found ports.
1674ad74bc61SViacheslav Ovsiienko 	 */
1675ad74bc61SViacheslav Ovsiienko 	unsigned int np = 0;
1676ad74bc61SViacheslav Ovsiienko 	/*
1677ad74bc61SViacheslav Ovsiienko 	 * Number of DPDK ethernet devices to Spawn - either over
1678ad74bc61SViacheslav Ovsiienko 	 * multiple IB devices or multiple ports of single IB device.
1679ad74bc61SViacheslav Ovsiienko 	 * Actually this is the number of iterations to spawn.
1680ad74bc61SViacheslav Ovsiienko 	 */
1681ad74bc61SViacheslav Ovsiienko 	unsigned int ns = 0;
1682f87bfa8eSYongseok Koh 	struct mlx5_dev_config dev_config;
1683f38c5457SAdrien Mazarguil 	int ret;
1684f38c5457SAdrien Mazarguil 
16857be600c8SYongseok Koh 	ret = mlx5_init_once();
16867be600c8SYongseok Koh 	if (ret) {
16877be600c8SYongseok Koh 		DRV_LOG(ERR, "unable to init PMD global data: %s",
16887be600c8SYongseok Koh 			strerror(rte_errno));
16897be600c8SYongseok Koh 		return -rte_errno;
16907be600c8SYongseok Koh 	}
1691f38c5457SAdrien Mazarguil 	assert(pci_drv == &mlx5_driver);
1692f38c5457SAdrien Mazarguil 	errno = 0;
1693f38c5457SAdrien Mazarguil 	ibv_list = mlx5_glue->get_device_list(&ret);
1694f38c5457SAdrien Mazarguil 	if (!ibv_list) {
1695f38c5457SAdrien Mazarguil 		rte_errno = errno ? errno : ENOSYS;
1696f38c5457SAdrien Mazarguil 		DRV_LOG(ERR, "cannot list devices, is ib_uverbs loaded?");
1697a6d83b6aSNélio Laranjeiro 		return -rte_errno;
1698a6d83b6aSNélio Laranjeiro 	}
1699ad74bc61SViacheslav Ovsiienko 	/*
1700ad74bc61SViacheslav Ovsiienko 	 * First scan the list of all Infiniband devices to find
1701ad74bc61SViacheslav Ovsiienko 	 * matching ones, gathering into the list.
1702ad74bc61SViacheslav Ovsiienko 	 */
170326c08b97SAdrien Mazarguil 	struct ibv_device *ibv_match[ret + 1];
1704ad74bc61SViacheslav Ovsiienko 	int nl_route = -1;
1705ad74bc61SViacheslav Ovsiienko 	int nl_rdma = -1;
1706ad74bc61SViacheslav Ovsiienko 	unsigned int i;
170726c08b97SAdrien Mazarguil 
1708f38c5457SAdrien Mazarguil 	while (ret-- > 0) {
1709f38c5457SAdrien Mazarguil 		struct rte_pci_addr pci_addr;
1710f38c5457SAdrien Mazarguil 
1711f38c5457SAdrien Mazarguil 		DRV_LOG(DEBUG, "checking device \"%s\"", ibv_list[ret]->name);
1712f38c5457SAdrien Mazarguil 		if (mlx5_ibv_device_to_pci_addr(ibv_list[ret], &pci_addr))
1713f38c5457SAdrien Mazarguil 			continue;
1714f38c5457SAdrien Mazarguil 		if (pci_dev->addr.domain != pci_addr.domain ||
1715f38c5457SAdrien Mazarguil 		    pci_dev->addr.bus != pci_addr.bus ||
1716f38c5457SAdrien Mazarguil 		    pci_dev->addr.devid != pci_addr.devid ||
1717f38c5457SAdrien Mazarguil 		    pci_dev->addr.function != pci_addr.function)
1718f38c5457SAdrien Mazarguil 			continue;
171926c08b97SAdrien Mazarguil 		DRV_LOG(INFO, "PCI information matches for device \"%s\"",
1720f38c5457SAdrien Mazarguil 			ibv_list[ret]->name);
1721ad74bc61SViacheslav Ovsiienko 		ibv_match[nd++] = ibv_list[ret];
172226c08b97SAdrien Mazarguil 	}
1723ad74bc61SViacheslav Ovsiienko 	ibv_match[nd] = NULL;
1724ad74bc61SViacheslav Ovsiienko 	if (!nd) {
1725ae4eb7dcSViacheslav Ovsiienko 		/* No device matches, just complain and bail out. */
1726ad74bc61SViacheslav Ovsiienko 		mlx5_glue->free_device_list(ibv_list);
1727ad74bc61SViacheslav Ovsiienko 		DRV_LOG(WARNING,
1728ad74bc61SViacheslav Ovsiienko 			"no Verbs device matches PCI device " PCI_PRI_FMT ","
1729ad74bc61SViacheslav Ovsiienko 			" are kernel drivers loaded?",
1730ad74bc61SViacheslav Ovsiienko 			pci_dev->addr.domain, pci_dev->addr.bus,
1731ad74bc61SViacheslav Ovsiienko 			pci_dev->addr.devid, pci_dev->addr.function);
1732ad74bc61SViacheslav Ovsiienko 		rte_errno = ENOENT;
1733ad74bc61SViacheslav Ovsiienko 		ret = -rte_errno;
1734ad74bc61SViacheslav Ovsiienko 		return ret;
1735ad74bc61SViacheslav Ovsiienko 	}
1736ad74bc61SViacheslav Ovsiienko 	nl_route = mlx5_nl_init(NETLINK_ROUTE);
1737ad74bc61SViacheslav Ovsiienko 	nl_rdma = mlx5_nl_init(NETLINK_RDMA);
1738ad74bc61SViacheslav Ovsiienko 	if (nd == 1) {
173926c08b97SAdrien Mazarguil 		/*
1740ad74bc61SViacheslav Ovsiienko 		 * Found single matching device may have multiple ports.
1741ad74bc61SViacheslav Ovsiienko 		 * Each port may be representor, we have to check the port
1742ad74bc61SViacheslav Ovsiienko 		 * number and check the representors existence.
174326c08b97SAdrien Mazarguil 		 */
1744ad74bc61SViacheslav Ovsiienko 		if (nl_rdma >= 0)
1745ad74bc61SViacheslav Ovsiienko 			np = mlx5_nl_portnum(nl_rdma, ibv_match[0]->name);
1746ad74bc61SViacheslav Ovsiienko 		if (!np)
1747ad74bc61SViacheslav Ovsiienko 			DRV_LOG(WARNING, "can not get IB device \"%s\""
1748ad74bc61SViacheslav Ovsiienko 					 " ports number", ibv_match[0]->name);
1749ad74bc61SViacheslav Ovsiienko 	}
1750ad74bc61SViacheslav Ovsiienko 	/*
1751ad74bc61SViacheslav Ovsiienko 	 * Now we can determine the maximal
1752ad74bc61SViacheslav Ovsiienko 	 * amount of devices to be spawned.
1753ad74bc61SViacheslav Ovsiienko 	 */
1754ad74bc61SViacheslav Ovsiienko 	struct mlx5_dev_spawn_data list[np ? np : nd];
1755ad74bc61SViacheslav Ovsiienko 
1756ad74bc61SViacheslav Ovsiienko 	if (np > 1) {
1757ad74bc61SViacheslav Ovsiienko 		/*
1758ae4eb7dcSViacheslav Ovsiienko 		 * Single IB device with multiple ports found,
1759ad74bc61SViacheslav Ovsiienko 		 * it may be E-Switch master device and representors.
1760ad74bc61SViacheslav Ovsiienko 		 * We have to perform identification trough the ports.
1761ad74bc61SViacheslav Ovsiienko 		 */
1762ad74bc61SViacheslav Ovsiienko 		assert(nl_rdma >= 0);
1763ad74bc61SViacheslav Ovsiienko 		assert(ns == 0);
1764ad74bc61SViacheslav Ovsiienko 		assert(nd == 1);
1765ad74bc61SViacheslav Ovsiienko 		for (i = 1; i <= np; ++i) {
1766ad74bc61SViacheslav Ovsiienko 			list[ns].max_port = np;
1767ad74bc61SViacheslav Ovsiienko 			list[ns].ibv_port = i;
1768ad74bc61SViacheslav Ovsiienko 			list[ns].ibv_dev = ibv_match[0];
1769ad74bc61SViacheslav Ovsiienko 			list[ns].eth_dev = NULL;
1770ab3cffcfSViacheslav Ovsiienko 			list[ns].pci_dev = pci_dev;
1771ad74bc61SViacheslav Ovsiienko 			list[ns].ifindex = mlx5_nl_ifindex
1772ad74bc61SViacheslav Ovsiienko 					(nl_rdma, list[ns].ibv_dev->name, i);
1773ad74bc61SViacheslav Ovsiienko 			if (!list[ns].ifindex) {
1774ad74bc61SViacheslav Ovsiienko 				/*
1775ad74bc61SViacheslav Ovsiienko 				 * No network interface index found for the
1776ad74bc61SViacheslav Ovsiienko 				 * specified port, it means there is no
1777ad74bc61SViacheslav Ovsiienko 				 * representor on this port. It's OK,
1778ad74bc61SViacheslav Ovsiienko 				 * there can be disabled ports, for example
1779ad74bc61SViacheslav Ovsiienko 				 * if sriov_numvfs < sriov_totalvfs.
1780ad74bc61SViacheslav Ovsiienko 				 */
178126c08b97SAdrien Mazarguil 				continue;
178226c08b97SAdrien Mazarguil 			}
1783ad74bc61SViacheslav Ovsiienko 			ret = -1;
178426c08b97SAdrien Mazarguil 			if (nl_route >= 0)
1785ad74bc61SViacheslav Ovsiienko 				ret = mlx5_nl_switch_info
1786ad74bc61SViacheslav Ovsiienko 					       (nl_route,
1787ad74bc61SViacheslav Ovsiienko 						list[ns].ifindex,
1788ad74bc61SViacheslav Ovsiienko 						&list[ns].info);
1789ad74bc61SViacheslav Ovsiienko 			if (ret || (!list[ns].info.representor &&
1790ad74bc61SViacheslav Ovsiienko 				    !list[ns].info.master)) {
1791ad74bc61SViacheslav Ovsiienko 				/*
1792ad74bc61SViacheslav Ovsiienko 				 * We failed to recognize representors with
1793ad74bc61SViacheslav Ovsiienko 				 * Netlink, let's try to perform the task
1794ad74bc61SViacheslav Ovsiienko 				 * with sysfs.
1795ad74bc61SViacheslav Ovsiienko 				 */
1796ad74bc61SViacheslav Ovsiienko 				ret =  mlx5_sysfs_switch_info
1797ad74bc61SViacheslav Ovsiienko 						(list[ns].ifindex,
1798ad74bc61SViacheslav Ovsiienko 						 &list[ns].info);
1799ad74bc61SViacheslav Ovsiienko 			}
1800ad74bc61SViacheslav Ovsiienko 			if (!ret && (list[ns].info.representor ^
1801ad74bc61SViacheslav Ovsiienko 				     list[ns].info.master))
1802ad74bc61SViacheslav Ovsiienko 				ns++;
1803ad74bc61SViacheslav Ovsiienko 		}
1804ad74bc61SViacheslav Ovsiienko 		if (!ns) {
180526c08b97SAdrien Mazarguil 			DRV_LOG(ERR,
1806ad74bc61SViacheslav Ovsiienko 				"unable to recognize master/representors"
1807ad74bc61SViacheslav Ovsiienko 				" on the IB device with multiple ports");
1808ad74bc61SViacheslav Ovsiienko 			rte_errno = ENOENT;
1809ad74bc61SViacheslav Ovsiienko 			ret = -rte_errno;
1810ad74bc61SViacheslav Ovsiienko 			goto exit;
1811ad74bc61SViacheslav Ovsiienko 		}
1812ad74bc61SViacheslav Ovsiienko 	} else {
1813ad74bc61SViacheslav Ovsiienko 		/*
1814ad74bc61SViacheslav Ovsiienko 		 * The existence of several matching entries (nd > 1) means
1815ad74bc61SViacheslav Ovsiienko 		 * port representors have been instantiated. No existing Verbs
1816ad74bc61SViacheslav Ovsiienko 		 * call nor sysfs entries can tell them apart, this can only
1817ad74bc61SViacheslav Ovsiienko 		 * be done through Netlink calls assuming kernel drivers are
1818ad74bc61SViacheslav Ovsiienko 		 * recent enough to support them.
1819ad74bc61SViacheslav Ovsiienko 		 *
1820ad74bc61SViacheslav Ovsiienko 		 * In the event of identification failure through Netlink,
1821ad74bc61SViacheslav Ovsiienko 		 * try again through sysfs, then:
1822ad74bc61SViacheslav Ovsiienko 		 *
1823ad74bc61SViacheslav Ovsiienko 		 * 1. A single IB device matches (nd == 1) with single
1824ad74bc61SViacheslav Ovsiienko 		 *    port (np=0/1) and is not a representor, assume
1825ad74bc61SViacheslav Ovsiienko 		 *    no switch support.
1826ad74bc61SViacheslav Ovsiienko 		 *
1827ad74bc61SViacheslav Ovsiienko 		 * 2. Otherwise no safe assumptions can be made;
1828ad74bc61SViacheslav Ovsiienko 		 *    complain louder and bail out.
1829ad74bc61SViacheslav Ovsiienko 		 */
1830ad74bc61SViacheslav Ovsiienko 		np = 1;
1831ad74bc61SViacheslav Ovsiienko 		for (i = 0; i != nd; ++i) {
1832ad74bc61SViacheslav Ovsiienko 			memset(&list[ns].info, 0, sizeof(list[ns].info));
1833ad74bc61SViacheslav Ovsiienko 			list[ns].max_port = 1;
1834ad74bc61SViacheslav Ovsiienko 			list[ns].ibv_port = 1;
1835ad74bc61SViacheslav Ovsiienko 			list[ns].ibv_dev = ibv_match[i];
1836ad74bc61SViacheslav Ovsiienko 			list[ns].eth_dev = NULL;
1837ab3cffcfSViacheslav Ovsiienko 			list[ns].pci_dev = pci_dev;
1838ad74bc61SViacheslav Ovsiienko 			list[ns].ifindex = 0;
1839ad74bc61SViacheslav Ovsiienko 			if (nl_rdma >= 0)
1840ad74bc61SViacheslav Ovsiienko 				list[ns].ifindex = mlx5_nl_ifindex
1841ad74bc61SViacheslav Ovsiienko 					(nl_rdma, list[ns].ibv_dev->name, 1);
1842ad74bc61SViacheslav Ovsiienko 			if (!list[ns].ifindex) {
18439c2bbd04SViacheslav Ovsiienko 				char ifname[IF_NAMESIZE];
18449c2bbd04SViacheslav Ovsiienko 
1845ad74bc61SViacheslav Ovsiienko 				/*
18469c2bbd04SViacheslav Ovsiienko 				 * Netlink failed, it may happen with old
18479c2bbd04SViacheslav Ovsiienko 				 * ib_core kernel driver (before 4.16).
18489c2bbd04SViacheslav Ovsiienko 				 * We can assume there is old driver because
18499c2bbd04SViacheslav Ovsiienko 				 * here we are processing single ports IB
18509c2bbd04SViacheslav Ovsiienko 				 * devices. Let's try sysfs to retrieve
18519c2bbd04SViacheslav Ovsiienko 				 * the ifindex. The method works for
18529c2bbd04SViacheslav Ovsiienko 				 * master device only.
18539c2bbd04SViacheslav Ovsiienko 				 */
18549c2bbd04SViacheslav Ovsiienko 				if (nd > 1) {
18559c2bbd04SViacheslav Ovsiienko 					/*
18569c2bbd04SViacheslav Ovsiienko 					 * Multiple devices found, assume
18579c2bbd04SViacheslav Ovsiienko 					 * representors, can not distinguish
18589c2bbd04SViacheslav Ovsiienko 					 * master/representor and retrieve
18599c2bbd04SViacheslav Ovsiienko 					 * ifindex via sysfs.
1860ad74bc61SViacheslav Ovsiienko 					 */
1861ad74bc61SViacheslav Ovsiienko 					continue;
1862ad74bc61SViacheslav Ovsiienko 				}
18639c2bbd04SViacheslav Ovsiienko 				ret = mlx5_get_master_ifname
18649c2bbd04SViacheslav Ovsiienko 					(ibv_match[i]->ibdev_path, &ifname);
18659c2bbd04SViacheslav Ovsiienko 				if (!ret)
18669c2bbd04SViacheslav Ovsiienko 					list[ns].ifindex =
18679c2bbd04SViacheslav Ovsiienko 						if_nametoindex(ifname);
18689c2bbd04SViacheslav Ovsiienko 				if (!list[ns].ifindex) {
18699c2bbd04SViacheslav Ovsiienko 					/*
18709c2bbd04SViacheslav Ovsiienko 					 * No network interface index found
18719c2bbd04SViacheslav Ovsiienko 					 * for the specified device, it means
18729c2bbd04SViacheslav Ovsiienko 					 * there it is neither representor
18739c2bbd04SViacheslav Ovsiienko 					 * nor master.
18749c2bbd04SViacheslav Ovsiienko 					 */
18759c2bbd04SViacheslav Ovsiienko 					continue;
18769c2bbd04SViacheslav Ovsiienko 				}
18779c2bbd04SViacheslav Ovsiienko 			}
1878ad74bc61SViacheslav Ovsiienko 			ret = -1;
1879ad74bc61SViacheslav Ovsiienko 			if (nl_route >= 0)
1880ad74bc61SViacheslav Ovsiienko 				ret = mlx5_nl_switch_info
1881ad74bc61SViacheslav Ovsiienko 					       (nl_route,
1882ad74bc61SViacheslav Ovsiienko 						list[ns].ifindex,
1883ad74bc61SViacheslav Ovsiienko 						&list[ns].info);
1884ad74bc61SViacheslav Ovsiienko 			if (ret || (!list[ns].info.representor &&
1885ad74bc61SViacheslav Ovsiienko 				    !list[ns].info.master)) {
1886ad74bc61SViacheslav Ovsiienko 				/*
1887ad74bc61SViacheslav Ovsiienko 				 * We failed to recognize representors with
1888ad74bc61SViacheslav Ovsiienko 				 * Netlink, let's try to perform the task
1889ad74bc61SViacheslav Ovsiienko 				 * with sysfs.
1890ad74bc61SViacheslav Ovsiienko 				 */
1891ad74bc61SViacheslav Ovsiienko 				ret =  mlx5_sysfs_switch_info
1892ad74bc61SViacheslav Ovsiienko 						(list[ns].ifindex,
1893ad74bc61SViacheslav Ovsiienko 						 &list[ns].info);
1894ad74bc61SViacheslav Ovsiienko 			}
1895ad74bc61SViacheslav Ovsiienko 			if (!ret && (list[ns].info.representor ^
1896ad74bc61SViacheslav Ovsiienko 				     list[ns].info.master)) {
1897ad74bc61SViacheslav Ovsiienko 				ns++;
1898ad74bc61SViacheslav Ovsiienko 			} else if ((nd == 1) &&
1899ad74bc61SViacheslav Ovsiienko 				   !list[ns].info.representor &&
1900ad74bc61SViacheslav Ovsiienko 				   !list[ns].info.master) {
1901ad74bc61SViacheslav Ovsiienko 				/*
1902ad74bc61SViacheslav Ovsiienko 				 * Single IB device with
1903ad74bc61SViacheslav Ovsiienko 				 * one physical port and
1904ad74bc61SViacheslav Ovsiienko 				 * attached network device.
1905ad74bc61SViacheslav Ovsiienko 				 * May be SRIOV is not enabled
1906ad74bc61SViacheslav Ovsiienko 				 * or there is no representors.
1907ad74bc61SViacheslav Ovsiienko 				 */
1908ad74bc61SViacheslav Ovsiienko 				DRV_LOG(INFO, "no E-Switch support detected");
1909ad74bc61SViacheslav Ovsiienko 				ns++;
1910ad74bc61SViacheslav Ovsiienko 				break;
191126c08b97SAdrien Mazarguil 			}
1912f38c5457SAdrien Mazarguil 		}
1913ad74bc61SViacheslav Ovsiienko 		if (!ns) {
1914ad74bc61SViacheslav Ovsiienko 			DRV_LOG(ERR,
1915ad74bc61SViacheslav Ovsiienko 				"unable to recognize master/representors"
1916ad74bc61SViacheslav Ovsiienko 				" on the multiple IB devices");
1917ad74bc61SViacheslav Ovsiienko 			rte_errno = ENOENT;
1918ad74bc61SViacheslav Ovsiienko 			ret = -rte_errno;
1919ad74bc61SViacheslav Ovsiienko 			goto exit;
1920ad74bc61SViacheslav Ovsiienko 		}
1921ad74bc61SViacheslav Ovsiienko 	}
1922ad74bc61SViacheslav Ovsiienko 	assert(ns);
1923116f90adSAdrien Mazarguil 	/*
1924116f90adSAdrien Mazarguil 	 * Sort list to probe devices in natural order for users convenience
1925116f90adSAdrien Mazarguil 	 * (i.e. master first, then representors from lowest to highest ID).
1926116f90adSAdrien Mazarguil 	 */
1927ad74bc61SViacheslav Ovsiienko 	qsort(list, ns, sizeof(*list), mlx5_dev_spawn_data_cmp);
1928f87bfa8eSYongseok Koh 	/* Default configuration. */
1929f87bfa8eSYongseok Koh 	dev_config = (struct mlx5_dev_config){
193078c7a16dSYongseok Koh 		.hw_padding = 0,
1931f87bfa8eSYongseok Koh 		.mps = MLX5_ARG_UNSET,
1932f87bfa8eSYongseok Koh 		.tx_vec_en = 1,
1933f87bfa8eSYongseok Koh 		.rx_vec_en = 1,
1934f87bfa8eSYongseok Koh 		.txq_inline = MLX5_ARG_UNSET,
1935f87bfa8eSYongseok Koh 		.txqs_inline = MLX5_ARG_UNSET,
193609d8b416SYongseok Koh 		.txqs_vec = MLX5_ARG_UNSET,
1937f87bfa8eSYongseok Koh 		.inline_max_packet_sz = MLX5_ARG_UNSET,
1938f87bfa8eSYongseok Koh 		.vf_nl_en = 1,
1939dceb5029SYongseok Koh 		.mr_ext_memseg_en = 1,
1940f87bfa8eSYongseok Koh 		.mprq = {
1941f87bfa8eSYongseok Koh 			.enabled = 0, /* Disabled by default. */
1942f87bfa8eSYongseok Koh 			.stride_num_n = MLX5_MPRQ_STRIDE_NUM_N,
1943f87bfa8eSYongseok Koh 			.max_memcpy_len = MLX5_MPRQ_MEMCPY_DEFAULT_LEN,
1944f87bfa8eSYongseok Koh 			.min_rxqs_num = MLX5_MPRQ_MIN_RXQS,
1945f87bfa8eSYongseok Koh 		},
1946e2b4925eSOri Kam 		.dv_esw_en = 1,
1947f87bfa8eSYongseok Koh 	};
1948ad74bc61SViacheslav Ovsiienko 	/* Device specific configuration. */
1949f38c5457SAdrien Mazarguil 	switch (pci_dev->id.device_id) {
195009d8b416SYongseok Koh 	case PCI_DEVICE_ID_MELLANOX_CONNECTX5BF:
195109d8b416SYongseok Koh 		dev_config.txqs_vec = MLX5_VPMD_MAX_TXQS_BLUEFIELD;
195209d8b416SYongseok Koh 		break;
1953f38c5457SAdrien Mazarguil 	case PCI_DEVICE_ID_MELLANOX_CONNECTX4VF:
1954f38c5457SAdrien Mazarguil 	case PCI_DEVICE_ID_MELLANOX_CONNECTX4LXVF:
1955f38c5457SAdrien Mazarguil 	case PCI_DEVICE_ID_MELLANOX_CONNECTX5VF:
1956f38c5457SAdrien Mazarguil 	case PCI_DEVICE_ID_MELLANOX_CONNECTX5EXVF:
1957f87bfa8eSYongseok Koh 		dev_config.vf = 1;
1958f38c5457SAdrien Mazarguil 		break;
1959f38c5457SAdrien Mazarguil 	default:
1960f87bfa8eSYongseok Koh 		break;
1961f38c5457SAdrien Mazarguil 	}
196209d8b416SYongseok Koh 	/* Set architecture-dependent default value if unset. */
196309d8b416SYongseok Koh 	if (dev_config.txqs_vec == MLX5_ARG_UNSET)
196409d8b416SYongseok Koh 		dev_config.txqs_vec = MLX5_VPMD_MAX_TXQS;
1965ad74bc61SViacheslav Ovsiienko 	for (i = 0; i != ns; ++i) {
19662b730263SAdrien Mazarguil 		uint32_t restore;
19672b730263SAdrien Mazarguil 
1968f87bfa8eSYongseok Koh 		list[i].eth_dev = mlx5_dev_spawn(&pci_dev->device,
1969ad74bc61SViacheslav Ovsiienko 						 &list[i],
1970ad74bc61SViacheslav Ovsiienko 						 dev_config);
19716de569f5SAdrien Mazarguil 		if (!list[i].eth_dev) {
1972206254b7SOphir Munk 			if (rte_errno != EBUSY && rte_errno != EEXIST)
19732b730263SAdrien Mazarguil 				break;
1974206254b7SOphir Munk 			/* Device is disabled or already spawned. Ignore it. */
19756de569f5SAdrien Mazarguil 			continue;
19766de569f5SAdrien Mazarguil 		}
1977116f90adSAdrien Mazarguil 		restore = list[i].eth_dev->data->dev_flags;
1978116f90adSAdrien Mazarguil 		rte_eth_copy_pci_info(list[i].eth_dev, pci_dev);
19792b730263SAdrien Mazarguil 		/* Restore non-PCI flags cleared by the above call. */
1980116f90adSAdrien Mazarguil 		list[i].eth_dev->data->dev_flags |= restore;
1981116f90adSAdrien Mazarguil 		rte_eth_dev_probing_finish(list[i].eth_dev);
19822b730263SAdrien Mazarguil 	}
1983ad74bc61SViacheslav Ovsiienko 	if (i != ns) {
1984f38c5457SAdrien Mazarguil 		DRV_LOG(ERR,
1985f38c5457SAdrien Mazarguil 			"probe of PCI device " PCI_PRI_FMT " aborted after"
1986f38c5457SAdrien Mazarguil 			" encountering an error: %s",
1987f38c5457SAdrien Mazarguil 			pci_dev->addr.domain, pci_dev->addr.bus,
1988f38c5457SAdrien Mazarguil 			pci_dev->addr.devid, pci_dev->addr.function,
1989f38c5457SAdrien Mazarguil 			strerror(rte_errno));
1990f38c5457SAdrien Mazarguil 		ret = -rte_errno;
19912b730263SAdrien Mazarguil 		/* Roll back. */
19922b730263SAdrien Mazarguil 		while (i--) {
19936de569f5SAdrien Mazarguil 			if (!list[i].eth_dev)
19946de569f5SAdrien Mazarguil 				continue;
1995116f90adSAdrien Mazarguil 			mlx5_dev_close(list[i].eth_dev);
1996e16adf08SThomas Monjalon 			/* mac_addrs must not be freed because in dev_private */
1997e16adf08SThomas Monjalon 			list[i].eth_dev->data->mac_addrs = NULL;
1998116f90adSAdrien Mazarguil 			claim_zero(rte_eth_dev_release_port(list[i].eth_dev));
19992b730263SAdrien Mazarguil 		}
20002b730263SAdrien Mazarguil 		/* Restore original error. */
20012b730263SAdrien Mazarguil 		rte_errno = -ret;
2002f38c5457SAdrien Mazarguil 	} else {
2003f38c5457SAdrien Mazarguil 		ret = 0;
2004f38c5457SAdrien Mazarguil 	}
2005ad74bc61SViacheslav Ovsiienko exit:
2006ad74bc61SViacheslav Ovsiienko 	/*
2007ad74bc61SViacheslav Ovsiienko 	 * Do the routine cleanup:
2008ad74bc61SViacheslav Ovsiienko 	 * - close opened Netlink sockets
2009ad74bc61SViacheslav Ovsiienko 	 * - free the Infiniband device list
2010ad74bc61SViacheslav Ovsiienko 	 */
2011ad74bc61SViacheslav Ovsiienko 	if (nl_rdma >= 0)
2012ad74bc61SViacheslav Ovsiienko 		close(nl_rdma);
2013ad74bc61SViacheslav Ovsiienko 	if (nl_route >= 0)
2014ad74bc61SViacheslav Ovsiienko 		close(nl_route);
2015ad74bc61SViacheslav Ovsiienko 	assert(ibv_list);
2016ad74bc61SViacheslav Ovsiienko 	mlx5_glue->free_device_list(ibv_list);
2017f38c5457SAdrien Mazarguil 	return ret;
2018771fa900SAdrien Mazarguil }
2019771fa900SAdrien Mazarguil 
20203a820742SOphir Munk /**
20213a820742SOphir Munk  * DPDK callback to remove a PCI device.
20223a820742SOphir Munk  *
20233a820742SOphir Munk  * This function removes all Ethernet devices belong to a given PCI device.
20243a820742SOphir Munk  *
20253a820742SOphir Munk  * @param[in] pci_dev
20263a820742SOphir Munk  *   Pointer to the PCI device.
20273a820742SOphir Munk  *
20283a820742SOphir Munk  * @return
20293a820742SOphir Munk  *   0 on success, the function cannot fail.
20303a820742SOphir Munk  */
20313a820742SOphir Munk static int
20323a820742SOphir Munk mlx5_pci_remove(struct rte_pci_device *pci_dev)
20333a820742SOphir Munk {
20343a820742SOphir Munk 	uint16_t port_id;
20353a820742SOphir Munk 
20365294b800SThomas Monjalon 	RTE_ETH_FOREACH_DEV_OF(port_id, &pci_dev->device)
20373a820742SOphir Munk 		rte_eth_dev_close(port_id);
20383a820742SOphir Munk 	return 0;
20393a820742SOphir Munk }
20403a820742SOphir Munk 
2041771fa900SAdrien Mazarguil static const struct rte_pci_id mlx5_pci_id_map[] = {
2042771fa900SAdrien Mazarguil 	{
20431d1bc870SNélio Laranjeiro 		RTE_PCI_DEVICE(PCI_VENDOR_ID_MELLANOX,
20441d1bc870SNélio Laranjeiro 			       PCI_DEVICE_ID_MELLANOX_CONNECTX4)
2045771fa900SAdrien Mazarguil 	},
2046771fa900SAdrien Mazarguil 	{
20471d1bc870SNélio Laranjeiro 		RTE_PCI_DEVICE(PCI_VENDOR_ID_MELLANOX,
20481d1bc870SNélio Laranjeiro 			       PCI_DEVICE_ID_MELLANOX_CONNECTX4VF)
2049771fa900SAdrien Mazarguil 	},
2050771fa900SAdrien Mazarguil 	{
20511d1bc870SNélio Laranjeiro 		RTE_PCI_DEVICE(PCI_VENDOR_ID_MELLANOX,
20521d1bc870SNélio Laranjeiro 			       PCI_DEVICE_ID_MELLANOX_CONNECTX4LX)
2053771fa900SAdrien Mazarguil 	},
2054771fa900SAdrien Mazarguil 	{
20551d1bc870SNélio Laranjeiro 		RTE_PCI_DEVICE(PCI_VENDOR_ID_MELLANOX,
20561d1bc870SNélio Laranjeiro 			       PCI_DEVICE_ID_MELLANOX_CONNECTX4LXVF)
2057771fa900SAdrien Mazarguil 	},
2058771fa900SAdrien Mazarguil 	{
2059528a9fbeSYongseok Koh 		RTE_PCI_DEVICE(PCI_VENDOR_ID_MELLANOX,
2060528a9fbeSYongseok Koh 			       PCI_DEVICE_ID_MELLANOX_CONNECTX5)
2061528a9fbeSYongseok Koh 	},
2062528a9fbeSYongseok Koh 	{
2063528a9fbeSYongseok Koh 		RTE_PCI_DEVICE(PCI_VENDOR_ID_MELLANOX,
2064528a9fbeSYongseok Koh 			       PCI_DEVICE_ID_MELLANOX_CONNECTX5VF)
2065528a9fbeSYongseok Koh 	},
2066528a9fbeSYongseok Koh 	{
2067528a9fbeSYongseok Koh 		RTE_PCI_DEVICE(PCI_VENDOR_ID_MELLANOX,
2068528a9fbeSYongseok Koh 			       PCI_DEVICE_ID_MELLANOX_CONNECTX5EX)
2069528a9fbeSYongseok Koh 	},
2070528a9fbeSYongseok Koh 	{
2071528a9fbeSYongseok Koh 		RTE_PCI_DEVICE(PCI_VENDOR_ID_MELLANOX,
2072528a9fbeSYongseok Koh 			       PCI_DEVICE_ID_MELLANOX_CONNECTX5EXVF)
2073528a9fbeSYongseok Koh 	},
2074528a9fbeSYongseok Koh 	{
2075dd3331c6SShahaf Shuler 		RTE_PCI_DEVICE(PCI_VENDOR_ID_MELLANOX,
2076dd3331c6SShahaf Shuler 			       PCI_DEVICE_ID_MELLANOX_CONNECTX5BF)
2077dd3331c6SShahaf Shuler 	},
2078dd3331c6SShahaf Shuler 	{
2079c322c0e5SOri Kam 		RTE_PCI_DEVICE(PCI_VENDOR_ID_MELLANOX,
2080c322c0e5SOri Kam 			       PCI_DEVICE_ID_MELLANOX_CONNECTX5BFVF)
2081c322c0e5SOri Kam 	},
2082c322c0e5SOri Kam 	{
2083f0354d84SWisam Jaddo 		RTE_PCI_DEVICE(PCI_VENDOR_ID_MELLANOX,
2084f0354d84SWisam Jaddo 				PCI_DEVICE_ID_MELLANOX_CONNECTX6)
2085f0354d84SWisam Jaddo 	},
2086f0354d84SWisam Jaddo 	{
2087f0354d84SWisam Jaddo 		RTE_PCI_DEVICE(PCI_VENDOR_ID_MELLANOX,
2088f0354d84SWisam Jaddo 				PCI_DEVICE_ID_MELLANOX_CONNECTX6VF)
2089f0354d84SWisam Jaddo 	},
2090f0354d84SWisam Jaddo 	{
2091771fa900SAdrien Mazarguil 		.vendor_id = 0
2092771fa900SAdrien Mazarguil 	}
2093771fa900SAdrien Mazarguil };
2094771fa900SAdrien Mazarguil 
2095fdf91e0fSJan Blunck static struct rte_pci_driver mlx5_driver = {
20962f3193cfSJan Viktorin 	.driver = {
20972f3193cfSJan Viktorin 		.name = MLX5_DRIVER_NAME
20982f3193cfSJan Viktorin 	},
2099771fa900SAdrien Mazarguil 	.id_table = mlx5_pci_id_map,
2100af424af8SShreyansh Jain 	.probe = mlx5_pci_probe,
21013a820742SOphir Munk 	.remove = mlx5_pci_remove,
2102989e999dSShahaf Shuler 	.dma_map = mlx5_dma_map,
2103989e999dSShahaf Shuler 	.dma_unmap = mlx5_dma_unmap,
2104206254b7SOphir Munk 	.drv_flags = (RTE_PCI_DRV_INTR_LSC | RTE_PCI_DRV_INTR_RMV |
2105206254b7SOphir Munk 		      RTE_PCI_DRV_PROBE_AGAIN),
2106771fa900SAdrien Mazarguil };
2107771fa900SAdrien Mazarguil 
210872b934adSThomas Monjalon #ifdef RTE_IBVERBS_LINK_DLOPEN
210959b91becSAdrien Mazarguil 
211059b91becSAdrien Mazarguil /**
211108c028d0SAdrien Mazarguil  * Suffix RTE_EAL_PMD_PATH with "-glue".
211208c028d0SAdrien Mazarguil  *
211308c028d0SAdrien Mazarguil  * This function performs a sanity check on RTE_EAL_PMD_PATH before
211408c028d0SAdrien Mazarguil  * suffixing its last component.
211508c028d0SAdrien Mazarguil  *
211608c028d0SAdrien Mazarguil  * @param buf[out]
211708c028d0SAdrien Mazarguil  *   Output buffer, should be large enough otherwise NULL is returned.
211808c028d0SAdrien Mazarguil  * @param size
211908c028d0SAdrien Mazarguil  *   Size of @p out.
212008c028d0SAdrien Mazarguil  *
212108c028d0SAdrien Mazarguil  * @return
212208c028d0SAdrien Mazarguil  *   Pointer to @p buf or @p NULL in case suffix cannot be appended.
212308c028d0SAdrien Mazarguil  */
212408c028d0SAdrien Mazarguil static char *
212508c028d0SAdrien Mazarguil mlx5_glue_path(char *buf, size_t size)
212608c028d0SAdrien Mazarguil {
212708c028d0SAdrien Mazarguil 	static const char *const bad[] = { "/", ".", "..", NULL };
212808c028d0SAdrien Mazarguil 	const char *path = RTE_EAL_PMD_PATH;
212908c028d0SAdrien Mazarguil 	size_t len = strlen(path);
213008c028d0SAdrien Mazarguil 	size_t off;
213108c028d0SAdrien Mazarguil 	int i;
213208c028d0SAdrien Mazarguil 
213308c028d0SAdrien Mazarguil 	while (len && path[len - 1] == '/')
213408c028d0SAdrien Mazarguil 		--len;
213508c028d0SAdrien Mazarguil 	for (off = len; off && path[off - 1] != '/'; --off)
213608c028d0SAdrien Mazarguil 		;
213708c028d0SAdrien Mazarguil 	for (i = 0; bad[i]; ++i)
213808c028d0SAdrien Mazarguil 		if (!strncmp(path + off, bad[i], (int)(len - off)))
213908c028d0SAdrien Mazarguil 			goto error;
214008c028d0SAdrien Mazarguil 	i = snprintf(buf, size, "%.*s-glue", (int)len, path);
214108c028d0SAdrien Mazarguil 	if (i == -1 || (size_t)i >= size)
214208c028d0SAdrien Mazarguil 		goto error;
214308c028d0SAdrien Mazarguil 	return buf;
214408c028d0SAdrien Mazarguil error:
2145a170a30dSNélio Laranjeiro 	DRV_LOG(ERR,
2146a170a30dSNélio Laranjeiro 		"unable to append \"-glue\" to last component of"
214708c028d0SAdrien Mazarguil 		" RTE_EAL_PMD_PATH (\"" RTE_EAL_PMD_PATH "\"),"
214808c028d0SAdrien Mazarguil 		" please re-configure DPDK");
214908c028d0SAdrien Mazarguil 	return NULL;
215008c028d0SAdrien Mazarguil }
215108c028d0SAdrien Mazarguil 
215208c028d0SAdrien Mazarguil /**
215359b91becSAdrien Mazarguil  * Initialization routine for run-time dependency on rdma-core.
215459b91becSAdrien Mazarguil  */
215559b91becSAdrien Mazarguil static int
215659b91becSAdrien Mazarguil mlx5_glue_init(void)
215759b91becSAdrien Mazarguil {
215808c028d0SAdrien Mazarguil 	char glue_path[sizeof(RTE_EAL_PMD_PATH) - 1 + sizeof("-glue")];
2159f6242d06SAdrien Mazarguil 	const char *path[] = {
2160f6242d06SAdrien Mazarguil 		/*
2161f6242d06SAdrien Mazarguil 		 * A basic security check is necessary before trusting
2162f6242d06SAdrien Mazarguil 		 * MLX5_GLUE_PATH, which may override RTE_EAL_PMD_PATH.
2163f6242d06SAdrien Mazarguil 		 */
2164f6242d06SAdrien Mazarguil 		(geteuid() == getuid() && getegid() == getgid() ?
2165f6242d06SAdrien Mazarguil 		 getenv("MLX5_GLUE_PATH") : NULL),
216608c028d0SAdrien Mazarguil 		/*
216708c028d0SAdrien Mazarguil 		 * When RTE_EAL_PMD_PATH is set, use its glue-suffixed
216808c028d0SAdrien Mazarguil 		 * variant, otherwise let dlopen() look up libraries on its
216908c028d0SAdrien Mazarguil 		 * own.
217008c028d0SAdrien Mazarguil 		 */
217108c028d0SAdrien Mazarguil 		(*RTE_EAL_PMD_PATH ?
217208c028d0SAdrien Mazarguil 		 mlx5_glue_path(glue_path, sizeof(glue_path)) : ""),
2173f6242d06SAdrien Mazarguil 	};
2174f6242d06SAdrien Mazarguil 	unsigned int i = 0;
217559b91becSAdrien Mazarguil 	void *handle = NULL;
217659b91becSAdrien Mazarguil 	void **sym;
217759b91becSAdrien Mazarguil 	const char *dlmsg;
217859b91becSAdrien Mazarguil 
2179f6242d06SAdrien Mazarguil 	while (!handle && i != RTE_DIM(path)) {
2180f6242d06SAdrien Mazarguil 		const char *end;
2181f6242d06SAdrien Mazarguil 		size_t len;
2182f6242d06SAdrien Mazarguil 		int ret;
2183f6242d06SAdrien Mazarguil 
2184f6242d06SAdrien Mazarguil 		if (!path[i]) {
2185f6242d06SAdrien Mazarguil 			++i;
2186f6242d06SAdrien Mazarguil 			continue;
2187f6242d06SAdrien Mazarguil 		}
2188f6242d06SAdrien Mazarguil 		end = strpbrk(path[i], ":;");
2189f6242d06SAdrien Mazarguil 		if (!end)
2190f6242d06SAdrien Mazarguil 			end = path[i] + strlen(path[i]);
2191f6242d06SAdrien Mazarguil 		len = end - path[i];
2192f6242d06SAdrien Mazarguil 		ret = 0;
2193f6242d06SAdrien Mazarguil 		do {
2194f6242d06SAdrien Mazarguil 			char name[ret + 1];
2195f6242d06SAdrien Mazarguil 
2196f6242d06SAdrien Mazarguil 			ret = snprintf(name, sizeof(name), "%.*s%s" MLX5_GLUE,
2197f6242d06SAdrien Mazarguil 				       (int)len, path[i],
2198f6242d06SAdrien Mazarguil 				       (!len || *(end - 1) == '/') ? "" : "/");
2199f6242d06SAdrien Mazarguil 			if (ret == -1)
2200f6242d06SAdrien Mazarguil 				break;
2201f6242d06SAdrien Mazarguil 			if (sizeof(name) != (size_t)ret + 1)
2202f6242d06SAdrien Mazarguil 				continue;
2203a170a30dSNélio Laranjeiro 			DRV_LOG(DEBUG, "looking for rdma-core glue as \"%s\"",
2204a170a30dSNélio Laranjeiro 				name);
2205f6242d06SAdrien Mazarguil 			handle = dlopen(name, RTLD_LAZY);
2206f6242d06SAdrien Mazarguil 			break;
2207f6242d06SAdrien Mazarguil 		} while (1);
2208f6242d06SAdrien Mazarguil 		path[i] = end + 1;
2209f6242d06SAdrien Mazarguil 		if (!*end)
2210f6242d06SAdrien Mazarguil 			++i;
2211f6242d06SAdrien Mazarguil 	}
221259b91becSAdrien Mazarguil 	if (!handle) {
221359b91becSAdrien Mazarguil 		rte_errno = EINVAL;
221459b91becSAdrien Mazarguil 		dlmsg = dlerror();
221559b91becSAdrien Mazarguil 		if (dlmsg)
2216a170a30dSNélio Laranjeiro 			DRV_LOG(WARNING, "cannot load glue library: %s", dlmsg);
221759b91becSAdrien Mazarguil 		goto glue_error;
221859b91becSAdrien Mazarguil 	}
221959b91becSAdrien Mazarguil 	sym = dlsym(handle, "mlx5_glue");
222059b91becSAdrien Mazarguil 	if (!sym || !*sym) {
222159b91becSAdrien Mazarguil 		rte_errno = EINVAL;
222259b91becSAdrien Mazarguil 		dlmsg = dlerror();
222359b91becSAdrien Mazarguil 		if (dlmsg)
2224a170a30dSNélio Laranjeiro 			DRV_LOG(ERR, "cannot resolve glue symbol: %s", dlmsg);
222559b91becSAdrien Mazarguil 		goto glue_error;
222659b91becSAdrien Mazarguil 	}
222759b91becSAdrien Mazarguil 	mlx5_glue = *sym;
222859b91becSAdrien Mazarguil 	return 0;
222959b91becSAdrien Mazarguil glue_error:
223059b91becSAdrien Mazarguil 	if (handle)
223159b91becSAdrien Mazarguil 		dlclose(handle);
2232a170a30dSNélio Laranjeiro 	DRV_LOG(WARNING,
2233a170a30dSNélio Laranjeiro 		"cannot initialize PMD due to missing run-time dependency on"
2234a170a30dSNélio Laranjeiro 		" rdma-core libraries (libibverbs, libmlx5)");
223559b91becSAdrien Mazarguil 	return -rte_errno;
223659b91becSAdrien Mazarguil }
223759b91becSAdrien Mazarguil 
223859b91becSAdrien Mazarguil #endif
223959b91becSAdrien Mazarguil 
2240771fa900SAdrien Mazarguil /**
2241771fa900SAdrien Mazarguil  * Driver initialization routine.
2242771fa900SAdrien Mazarguil  */
2243f8e99896SThomas Monjalon RTE_INIT(rte_mlx5_pmd_init)
2244771fa900SAdrien Mazarguil {
22453d96644aSStephen Hemminger 	/* Initialize driver log type. */
22463d96644aSStephen Hemminger 	mlx5_logtype = rte_log_register("pmd.net.mlx5");
22473d96644aSStephen Hemminger 	if (mlx5_logtype >= 0)
22483d96644aSStephen Hemminger 		rte_log_set_level(mlx5_logtype, RTE_LOG_NOTICE);
22493d96644aSStephen Hemminger 
22505f8ba81cSXueming Li 	/* Build the static tables for Verbs conversion. */
2251ea16068cSYongseok Koh 	mlx5_set_ptype_table();
22525f8ba81cSXueming Li 	mlx5_set_cksum_table();
22535f8ba81cSXueming Li 	mlx5_set_swp_types_table();
2254771fa900SAdrien Mazarguil 	/*
2255771fa900SAdrien Mazarguil 	 * RDMAV_HUGEPAGES_SAFE tells ibv_fork_init() we intend to use
2256771fa900SAdrien Mazarguil 	 * huge pages. Calling ibv_fork_init() during init allows
2257771fa900SAdrien Mazarguil 	 * applications to use fork() safely for purposes other than
2258771fa900SAdrien Mazarguil 	 * using this PMD, which is not supported in forked processes.
2259771fa900SAdrien Mazarguil 	 */
2260771fa900SAdrien Mazarguil 	setenv("RDMAV_HUGEPAGES_SAFE", "1", 1);
2261161b93e5SYongseok Koh 	/* Match the size of Rx completion entry to the size of a cacheline. */
2262161b93e5SYongseok Koh 	if (RTE_CACHE_LINE_SIZE == 128)
2263161b93e5SYongseok Koh 		setenv("MLX5_CQE_SIZE", "128", 0);
22641ff30d18SMatan Azrad 	/*
22651ff30d18SMatan Azrad 	 * MLX5_DEVICE_FATAL_CLEANUP tells ibv_destroy functions to
22661ff30d18SMatan Azrad 	 * cleanup all the Verbs resources even when the device was removed.
22671ff30d18SMatan Azrad 	 */
22681ff30d18SMatan Azrad 	setenv("MLX5_DEVICE_FATAL_CLEANUP", "1", 1);
226972b934adSThomas Monjalon #ifdef RTE_IBVERBS_LINK_DLOPEN
227059b91becSAdrien Mazarguil 	if (mlx5_glue_init())
227159b91becSAdrien Mazarguil 		return;
227259b91becSAdrien Mazarguil 	assert(mlx5_glue);
227359b91becSAdrien Mazarguil #endif
22742a3b0097SAdrien Mazarguil #ifndef NDEBUG
22752a3b0097SAdrien Mazarguil 	/* Glue structure must not contain any NULL pointers. */
22762a3b0097SAdrien Mazarguil 	{
22772a3b0097SAdrien Mazarguil 		unsigned int i;
22782a3b0097SAdrien Mazarguil 
22792a3b0097SAdrien Mazarguil 		for (i = 0; i != sizeof(*mlx5_glue) / sizeof(void *); ++i)
22802a3b0097SAdrien Mazarguil 			assert(((const void *const *)mlx5_glue)[i]);
22812a3b0097SAdrien Mazarguil 	}
22822a3b0097SAdrien Mazarguil #endif
22836d5df2eaSAdrien Mazarguil 	if (strcmp(mlx5_glue->version, MLX5_GLUE_VERSION)) {
2284a170a30dSNélio Laranjeiro 		DRV_LOG(ERR,
2285a170a30dSNélio Laranjeiro 			"rdma-core glue \"%s\" mismatch: \"%s\" is required",
22866d5df2eaSAdrien Mazarguil 			mlx5_glue->version, MLX5_GLUE_VERSION);
22876d5df2eaSAdrien Mazarguil 		return;
22886d5df2eaSAdrien Mazarguil 	}
22890e83b8e5SNelio Laranjeiro 	mlx5_glue->fork_init();
22903dcfe039SThomas Monjalon 	rte_pci_register(&mlx5_driver);
2291771fa900SAdrien Mazarguil }
2292771fa900SAdrien Mazarguil 
229301f19227SShreyansh Jain RTE_PMD_EXPORT_NAME(net_mlx5, __COUNTER__);
229401f19227SShreyansh Jain RTE_PMD_REGISTER_PCI_TABLE(net_mlx5, mlx5_pci_id_map);
22950880c401SOlivier Matz RTE_PMD_REGISTER_KMOD_DEP(net_mlx5, "* ib_uverbs & mlx5_core & mlx5_ib");
2296