1771fa900SAdrien Mazarguil /*- 2771fa900SAdrien Mazarguil * BSD LICENSE 3771fa900SAdrien Mazarguil * 4771fa900SAdrien Mazarguil * Copyright 2015 6WIND S.A. 5771fa900SAdrien Mazarguil * Copyright 2015 Mellanox. 6771fa900SAdrien Mazarguil * 7771fa900SAdrien Mazarguil * Redistribution and use in source and binary forms, with or without 8771fa900SAdrien Mazarguil * modification, are permitted provided that the following conditions 9771fa900SAdrien Mazarguil * are met: 10771fa900SAdrien Mazarguil * 11771fa900SAdrien Mazarguil * * Redistributions of source code must retain the above copyright 12771fa900SAdrien Mazarguil * notice, this list of conditions and the following disclaimer. 13771fa900SAdrien Mazarguil * * Redistributions in binary form must reproduce the above copyright 14771fa900SAdrien Mazarguil * notice, this list of conditions and the following disclaimer in 15771fa900SAdrien Mazarguil * the documentation and/or other materials provided with the 16771fa900SAdrien Mazarguil * distribution. 17771fa900SAdrien Mazarguil * * Neither the name of 6WIND S.A. nor the names of its 18771fa900SAdrien Mazarguil * contributors may be used to endorse or promote products derived 19771fa900SAdrien Mazarguil * from this software without specific prior written permission. 20771fa900SAdrien Mazarguil * 21771fa900SAdrien Mazarguil * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 22771fa900SAdrien Mazarguil * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 23771fa900SAdrien Mazarguil * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 24771fa900SAdrien Mazarguil * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 25771fa900SAdrien Mazarguil * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 26771fa900SAdrien Mazarguil * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 27771fa900SAdrien Mazarguil * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 28771fa900SAdrien Mazarguil * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 29771fa900SAdrien Mazarguil * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 30771fa900SAdrien Mazarguil * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 31771fa900SAdrien Mazarguil * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 32771fa900SAdrien Mazarguil */ 33771fa900SAdrien Mazarguil 34771fa900SAdrien Mazarguil #include <stddef.h> 35771fa900SAdrien Mazarguil #include <unistd.h> 36771fa900SAdrien Mazarguil #include <string.h> 37771fa900SAdrien Mazarguil #include <assert.h> 38771fa900SAdrien Mazarguil #include <stdint.h> 39771fa900SAdrien Mazarguil #include <stdlib.h> 40e72dd09bSNélio Laranjeiro #include <errno.h> 41771fa900SAdrien Mazarguil #include <net/if.h> 42771fa900SAdrien Mazarguil 43771fa900SAdrien Mazarguil /* Verbs header. */ 44771fa900SAdrien Mazarguil /* ISO C doesn't support unnamed structs/unions, disabling -pedantic. */ 45771fa900SAdrien Mazarguil #ifdef PEDANTIC 46fc5b160fSBruce Richardson #pragma GCC diagnostic ignored "-Wpedantic" 47771fa900SAdrien Mazarguil #endif 48771fa900SAdrien Mazarguil #include <infiniband/verbs.h> 49771fa900SAdrien Mazarguil #ifdef PEDANTIC 50fc5b160fSBruce Richardson #pragma GCC diagnostic error "-Wpedantic" 51771fa900SAdrien Mazarguil #endif 52771fa900SAdrien Mazarguil 53771fa900SAdrien Mazarguil /* DPDK headers don't like -pedantic. */ 54771fa900SAdrien Mazarguil #ifdef PEDANTIC 55fc5b160fSBruce Richardson #pragma GCC diagnostic ignored "-Wpedantic" 56771fa900SAdrien Mazarguil #endif 57771fa900SAdrien Mazarguil #include <rte_malloc.h> 58771fa900SAdrien Mazarguil #include <rte_ethdev.h> 59771fa900SAdrien Mazarguil #include <rte_pci.h> 60771fa900SAdrien Mazarguil #include <rte_common.h> 61e72dd09bSNélio Laranjeiro #include <rte_kvargs.h> 62771fa900SAdrien Mazarguil #ifdef PEDANTIC 63fc5b160fSBruce Richardson #pragma GCC diagnostic error "-Wpedantic" 64771fa900SAdrien Mazarguil #endif 65771fa900SAdrien Mazarguil 66771fa900SAdrien Mazarguil #include "mlx5.h" 67771fa900SAdrien Mazarguil #include "mlx5_utils.h" 682e22920bSAdrien Mazarguil #include "mlx5_rxtx.h" 69771fa900SAdrien Mazarguil #include "mlx5_autoconf.h" 7013d57bd5SAdrien Mazarguil #include "mlx5_defs.h" 71771fa900SAdrien Mazarguil 7299c12dccSNélio Laranjeiro /* Device parameter to enable RX completion queue compression. */ 7399c12dccSNélio Laranjeiro #define MLX5_RXQ_CQE_COMP_EN "rxq_cqe_comp_en" 7499c12dccSNélio Laranjeiro 752a66cf37SYaacov Hazan /* Device parameter to configure inline send. */ 762a66cf37SYaacov Hazan #define MLX5_TXQ_INLINE "txq_inline" 772a66cf37SYaacov Hazan 782a66cf37SYaacov Hazan /* 792a66cf37SYaacov Hazan * Device parameter to configure the number of TX queues threshold for 802a66cf37SYaacov Hazan * enabling inline send. 812a66cf37SYaacov Hazan */ 822a66cf37SYaacov Hazan #define MLX5_TXQS_MIN_INLINE "txqs_min_inline" 832a66cf37SYaacov Hazan 84230189d9SNélio Laranjeiro /* Device parameter to enable multi-packet send WQEs. */ 85230189d9SNélio Laranjeiro #define MLX5_TXQ_MPW_EN "txq_mpw_en" 86230189d9SNélio Laranjeiro 87771fa900SAdrien Mazarguil /** 884d803a72SOlga Shern * Retrieve integer value from environment variable. 894d803a72SOlga Shern * 904d803a72SOlga Shern * @param[in] name 914d803a72SOlga Shern * Environment variable name. 924d803a72SOlga Shern * 934d803a72SOlga Shern * @return 944d803a72SOlga Shern * Integer value, 0 if the variable is not set. 954d803a72SOlga Shern */ 964d803a72SOlga Shern int 974d803a72SOlga Shern mlx5_getenv_int(const char *name) 984d803a72SOlga Shern { 994d803a72SOlga Shern const char *val = getenv(name); 1004d803a72SOlga Shern 1014d803a72SOlga Shern if (val == NULL) 1024d803a72SOlga Shern return 0; 1034d803a72SOlga Shern return atoi(val); 1044d803a72SOlga Shern } 1054d803a72SOlga Shern 1064d803a72SOlga Shern /** 107771fa900SAdrien Mazarguil * DPDK callback to close the device. 108771fa900SAdrien Mazarguil * 109771fa900SAdrien Mazarguil * Destroy all queues and objects, free memory. 110771fa900SAdrien Mazarguil * 111771fa900SAdrien Mazarguil * @param dev 112771fa900SAdrien Mazarguil * Pointer to Ethernet device structure. 113771fa900SAdrien Mazarguil */ 114771fa900SAdrien Mazarguil static void 115771fa900SAdrien Mazarguil mlx5_dev_close(struct rte_eth_dev *dev) 116771fa900SAdrien Mazarguil { 117a48deadaSOr Ami struct priv *priv = mlx5_get_priv(dev); 1182e22920bSAdrien Mazarguil unsigned int i; 119771fa900SAdrien Mazarguil 120771fa900SAdrien Mazarguil priv_lock(priv); 121771fa900SAdrien Mazarguil DEBUG("%p: closing device \"%s\"", 122771fa900SAdrien Mazarguil (void *)dev, 123771fa900SAdrien Mazarguil ((priv->ctx != NULL) ? priv->ctx->device->name : "")); 124ecc1c29dSAdrien Mazarguil /* In case mlx5_dev_stop() has not been called. */ 125198a3c33SNelio Laranjeiro priv_dev_interrupt_handler_uninstall(priv, dev); 1260d218674SAdrien Mazarguil priv_special_flow_disable_all(priv); 127ecc1c29dSAdrien Mazarguil priv_mac_addrs_disable(priv); 128ecc1c29dSAdrien Mazarguil priv_destroy_hash_rxqs(priv); 12976f5c99eSYaacov Hazan 13076f5c99eSYaacov Hazan /* Remove flow director elements. */ 13176f5c99eSYaacov Hazan priv_fdir_disable(priv); 13276f5c99eSYaacov Hazan priv_fdir_delete_filters_list(priv); 13376f5c99eSYaacov Hazan 1342e22920bSAdrien Mazarguil /* Prevent crashes when queues are still in use. */ 1352e22920bSAdrien Mazarguil dev->rx_pkt_burst = removed_rx_burst; 1362e22920bSAdrien Mazarguil dev->tx_pkt_burst = removed_tx_burst; 1372e22920bSAdrien Mazarguil if (priv->rxqs != NULL) { 1382e22920bSAdrien Mazarguil /* XXX race condition if mlx5_rx_burst() is still running. */ 1392e22920bSAdrien Mazarguil usleep(1000); 1402e22920bSAdrien Mazarguil for (i = 0; (i != priv->rxqs_n); ++i) { 14121c8bb49SNélio Laranjeiro struct rxq *rxq = (*priv->rxqs)[i]; 1420cdddf4dSNélio Laranjeiro struct rxq_ctrl *rxq_ctrl; 14321c8bb49SNélio Laranjeiro 14421c8bb49SNélio Laranjeiro if (rxq == NULL) 1452e22920bSAdrien Mazarguil continue; 1460cdddf4dSNélio Laranjeiro rxq_ctrl = container_of(rxq, struct rxq_ctrl, rxq); 1472e22920bSAdrien Mazarguil (*priv->rxqs)[i] = NULL; 1480cdddf4dSNélio Laranjeiro rxq_cleanup(rxq_ctrl); 1490cdddf4dSNélio Laranjeiro rte_free(rxq_ctrl); 1502e22920bSAdrien Mazarguil } 1512e22920bSAdrien Mazarguil priv->rxqs_n = 0; 1522e22920bSAdrien Mazarguil priv->rxqs = NULL; 1532e22920bSAdrien Mazarguil } 1542e22920bSAdrien Mazarguil if (priv->txqs != NULL) { 1552e22920bSAdrien Mazarguil /* XXX race condition if mlx5_tx_burst() is still running. */ 1562e22920bSAdrien Mazarguil usleep(1000); 1572e22920bSAdrien Mazarguil for (i = 0; (i != priv->txqs_n); ++i) { 15821c8bb49SNélio Laranjeiro struct txq *txq = (*priv->txqs)[i]; 15921c8bb49SNélio Laranjeiro struct txq_ctrl *txq_ctrl; 16021c8bb49SNélio Laranjeiro 16121c8bb49SNélio Laranjeiro if (txq == NULL) 1622e22920bSAdrien Mazarguil continue; 16321c8bb49SNélio Laranjeiro txq_ctrl = container_of(txq, struct txq_ctrl, txq); 1642e22920bSAdrien Mazarguil (*priv->txqs)[i] = NULL; 16521c8bb49SNélio Laranjeiro txq_cleanup(txq_ctrl); 16621c8bb49SNélio Laranjeiro rte_free(txq_ctrl); 1672e22920bSAdrien Mazarguil } 1682e22920bSAdrien Mazarguil priv->txqs_n = 0; 1692e22920bSAdrien Mazarguil priv->txqs = NULL; 1702e22920bSAdrien Mazarguil } 171771fa900SAdrien Mazarguil if (priv->pd != NULL) { 172771fa900SAdrien Mazarguil assert(priv->ctx != NULL); 173771fa900SAdrien Mazarguil claim_zero(ibv_dealloc_pd(priv->pd)); 174771fa900SAdrien Mazarguil claim_zero(ibv_close_device(priv->ctx)); 175771fa900SAdrien Mazarguil } else 176771fa900SAdrien Mazarguil assert(priv->ctx == NULL); 1770573873dSNelio Laranjeiro if (priv->rss_conf != NULL) { 1780573873dSNelio Laranjeiro for (i = 0; (i != hash_rxq_init_n); ++i) 1790573873dSNelio Laranjeiro rte_free((*priv->rss_conf)[i]); 1802f97422eSNelio Laranjeiro rte_free(priv->rss_conf); 1810573873dSNelio Laranjeiro } 182634efbc2SNelio Laranjeiro if (priv->reta_idx != NULL) 183634efbc2SNelio Laranjeiro rte_free(priv->reta_idx); 184771fa900SAdrien Mazarguil priv_unlock(priv); 185771fa900SAdrien Mazarguil memset(priv, 0, sizeof(*priv)); 186771fa900SAdrien Mazarguil } 187771fa900SAdrien Mazarguil 188771fa900SAdrien Mazarguil static const struct eth_dev_ops mlx5_dev_ops = { 189e60fbd5bSAdrien Mazarguil .dev_configure = mlx5_dev_configure, 190e60fbd5bSAdrien Mazarguil .dev_start = mlx5_dev_start, 191e60fbd5bSAdrien Mazarguil .dev_stop = mlx5_dev_stop, 19262072098SOr Ami .dev_set_link_down = mlx5_set_link_down, 19362072098SOr Ami .dev_set_link_up = mlx5_set_link_up, 194771fa900SAdrien Mazarguil .dev_close = mlx5_dev_close, 1951bdbe1afSAdrien Mazarguil .promiscuous_enable = mlx5_promiscuous_enable, 1961bdbe1afSAdrien Mazarguil .promiscuous_disable = mlx5_promiscuous_disable, 1971bdbe1afSAdrien Mazarguil .allmulticast_enable = mlx5_allmulticast_enable, 1981bdbe1afSAdrien Mazarguil .allmulticast_disable = mlx5_allmulticast_disable, 199cb8faed7SAdrien Mazarguil .link_update = mlx5_link_update, 20087011737SAdrien Mazarguil .stats_get = mlx5_stats_get, 20187011737SAdrien Mazarguil .stats_reset = mlx5_stats_reset, 202e60fbd5bSAdrien Mazarguil .dev_infos_get = mlx5_dev_infos_get, 20378a38edfSJianfeng Tan .dev_supported_ptypes_get = mlx5_dev_supported_ptypes_get, 204e9086978SAdrien Mazarguil .vlan_filter_set = mlx5_vlan_filter_set, 2052e22920bSAdrien Mazarguil .rx_queue_setup = mlx5_rx_queue_setup, 2062e22920bSAdrien Mazarguil .tx_queue_setup = mlx5_tx_queue_setup, 2072e22920bSAdrien Mazarguil .rx_queue_release = mlx5_rx_queue_release, 2082e22920bSAdrien Mazarguil .tx_queue_release = mlx5_tx_queue_release, 20902d75430SAdrien Mazarguil .flow_ctrl_get = mlx5_dev_get_flow_ctrl, 21002d75430SAdrien Mazarguil .flow_ctrl_set = mlx5_dev_set_flow_ctrl, 2113318aef7SAdrien Mazarguil .mac_addr_remove = mlx5_mac_addr_remove, 2123318aef7SAdrien Mazarguil .mac_addr_add = mlx5_mac_addr_add, 21386977fccSDavid Marchand .mac_addr_set = mlx5_mac_addr_set, 214cf37ca95SAdrien Mazarguil .mtu_set = mlx5_dev_set_mtu, 215f3db9489SYaacov Hazan .vlan_strip_queue_set = mlx5_vlan_strip_queue_set, 216f3db9489SYaacov Hazan .vlan_offload_set = mlx5_vlan_offload_set, 217634efbc2SNelio Laranjeiro .reta_update = mlx5_dev_rss_reta_update, 218634efbc2SNelio Laranjeiro .reta_query = mlx5_dev_rss_reta_query, 2192f97422eSNelio Laranjeiro .rss_hash_update = mlx5_rss_hash_update, 2202f97422eSNelio Laranjeiro .rss_hash_conf_get = mlx5_rss_hash_conf_get, 22176f5c99eSYaacov Hazan .filter_ctrl = mlx5_dev_filter_ctrl, 222771fa900SAdrien Mazarguil }; 223771fa900SAdrien Mazarguil 224771fa900SAdrien Mazarguil static struct { 225771fa900SAdrien Mazarguil struct rte_pci_addr pci_addr; /* associated PCI address */ 226771fa900SAdrien Mazarguil uint32_t ports; /* physical ports bitfield. */ 227771fa900SAdrien Mazarguil } mlx5_dev[32]; 228771fa900SAdrien Mazarguil 229771fa900SAdrien Mazarguil /** 230771fa900SAdrien Mazarguil * Get device index in mlx5_dev[] from PCI bus address. 231771fa900SAdrien Mazarguil * 232771fa900SAdrien Mazarguil * @param[in] pci_addr 233771fa900SAdrien Mazarguil * PCI bus address to look for. 234771fa900SAdrien Mazarguil * 235771fa900SAdrien Mazarguil * @return 236771fa900SAdrien Mazarguil * mlx5_dev[] index on success, -1 on failure. 237771fa900SAdrien Mazarguil */ 238771fa900SAdrien Mazarguil static int 239771fa900SAdrien Mazarguil mlx5_dev_idx(struct rte_pci_addr *pci_addr) 240771fa900SAdrien Mazarguil { 241771fa900SAdrien Mazarguil unsigned int i; 242771fa900SAdrien Mazarguil int ret = -1; 243771fa900SAdrien Mazarguil 244771fa900SAdrien Mazarguil assert(pci_addr != NULL); 245771fa900SAdrien Mazarguil for (i = 0; (i != RTE_DIM(mlx5_dev)); ++i) { 246771fa900SAdrien Mazarguil if ((mlx5_dev[i].pci_addr.domain == pci_addr->domain) && 247771fa900SAdrien Mazarguil (mlx5_dev[i].pci_addr.bus == pci_addr->bus) && 248771fa900SAdrien Mazarguil (mlx5_dev[i].pci_addr.devid == pci_addr->devid) && 249771fa900SAdrien Mazarguil (mlx5_dev[i].pci_addr.function == pci_addr->function)) 250771fa900SAdrien Mazarguil return i; 251771fa900SAdrien Mazarguil if ((mlx5_dev[i].ports == 0) && (ret == -1)) 252771fa900SAdrien Mazarguil ret = i; 253771fa900SAdrien Mazarguil } 254771fa900SAdrien Mazarguil return ret; 255771fa900SAdrien Mazarguil } 256771fa900SAdrien Mazarguil 257e72dd09bSNélio Laranjeiro /** 258e72dd09bSNélio Laranjeiro * Verify and store value for device argument. 259e72dd09bSNélio Laranjeiro * 260e72dd09bSNélio Laranjeiro * @param[in] key 261e72dd09bSNélio Laranjeiro * Key argument to verify. 262e72dd09bSNélio Laranjeiro * @param[in] val 263e72dd09bSNélio Laranjeiro * Value associated with key. 264e72dd09bSNélio Laranjeiro * @param opaque 265e72dd09bSNélio Laranjeiro * User data. 266e72dd09bSNélio Laranjeiro * 267e72dd09bSNélio Laranjeiro * @return 268e72dd09bSNélio Laranjeiro * 0 on success, negative errno value on failure. 269e72dd09bSNélio Laranjeiro */ 270e72dd09bSNélio Laranjeiro static int 271e72dd09bSNélio Laranjeiro mlx5_args_check(const char *key, const char *val, void *opaque) 272e72dd09bSNélio Laranjeiro { 273e72dd09bSNélio Laranjeiro struct priv *priv = opaque; 27499c12dccSNélio Laranjeiro unsigned long tmp; 275e72dd09bSNélio Laranjeiro 27699c12dccSNélio Laranjeiro errno = 0; 27799c12dccSNélio Laranjeiro tmp = strtoul(val, NULL, 0); 27899c12dccSNélio Laranjeiro if (errno) { 27999c12dccSNélio Laranjeiro WARN("%s: \"%s\" is not a valid integer", key, val); 28099c12dccSNélio Laranjeiro return errno; 28199c12dccSNélio Laranjeiro } 28299c12dccSNélio Laranjeiro if (strcmp(MLX5_RXQ_CQE_COMP_EN, key) == 0) { 28399c12dccSNélio Laranjeiro priv->cqe_comp = !!tmp; 2842a66cf37SYaacov Hazan } else if (strcmp(MLX5_TXQ_INLINE, key) == 0) { 2852a66cf37SYaacov Hazan priv->txq_inline = tmp; 2862a66cf37SYaacov Hazan } else if (strcmp(MLX5_TXQS_MIN_INLINE, key) == 0) { 2872a66cf37SYaacov Hazan priv->txqs_inline = tmp; 288230189d9SNélio Laranjeiro } else if (strcmp(MLX5_TXQ_MPW_EN, key) == 0) { 289230189d9SNélio Laranjeiro priv->mps = !!tmp; 29099c12dccSNélio Laranjeiro } else { 291e72dd09bSNélio Laranjeiro WARN("%s: unknown parameter", key); 292e72dd09bSNélio Laranjeiro return -EINVAL; 293e72dd09bSNélio Laranjeiro } 29499c12dccSNélio Laranjeiro return 0; 29599c12dccSNélio Laranjeiro } 296e72dd09bSNélio Laranjeiro 297e72dd09bSNélio Laranjeiro /** 298e72dd09bSNélio Laranjeiro * Parse device parameters. 299e72dd09bSNélio Laranjeiro * 300e72dd09bSNélio Laranjeiro * @param priv 301e72dd09bSNélio Laranjeiro * Pointer to private structure. 302e72dd09bSNélio Laranjeiro * @param devargs 303e72dd09bSNélio Laranjeiro * Device arguments structure. 304e72dd09bSNélio Laranjeiro * 305e72dd09bSNélio Laranjeiro * @return 306e72dd09bSNélio Laranjeiro * 0 on success, errno value on failure. 307e72dd09bSNélio Laranjeiro */ 308e72dd09bSNélio Laranjeiro static int 309e72dd09bSNélio Laranjeiro mlx5_args(struct priv *priv, struct rte_devargs *devargs) 310e72dd09bSNélio Laranjeiro { 311e72dd09bSNélio Laranjeiro const char **params = (const char *[]){ 31299c12dccSNélio Laranjeiro MLX5_RXQ_CQE_COMP_EN, 3132a66cf37SYaacov Hazan MLX5_TXQ_INLINE, 3142a66cf37SYaacov Hazan MLX5_TXQS_MIN_INLINE, 315230189d9SNélio Laranjeiro MLX5_TXQ_MPW_EN, 316e72dd09bSNélio Laranjeiro NULL, 317e72dd09bSNélio Laranjeiro }; 318e72dd09bSNélio Laranjeiro struct rte_kvargs *kvlist; 319e72dd09bSNélio Laranjeiro int ret = 0; 320e72dd09bSNélio Laranjeiro int i; 321e72dd09bSNélio Laranjeiro 322e72dd09bSNélio Laranjeiro if (devargs == NULL) 323e72dd09bSNélio Laranjeiro return 0; 324e72dd09bSNélio Laranjeiro /* Following UGLY cast is done to pass checkpatch. */ 325e72dd09bSNélio Laranjeiro kvlist = rte_kvargs_parse(devargs->args, params); 326e72dd09bSNélio Laranjeiro if (kvlist == NULL) 327e72dd09bSNélio Laranjeiro return 0; 328e72dd09bSNélio Laranjeiro /* Process parameters. */ 329e72dd09bSNélio Laranjeiro for (i = 0; (params[i] != NULL); ++i) { 330e72dd09bSNélio Laranjeiro if (rte_kvargs_count(kvlist, params[i])) { 331e72dd09bSNélio Laranjeiro ret = rte_kvargs_process(kvlist, params[i], 332e72dd09bSNélio Laranjeiro mlx5_args_check, priv); 333e72dd09bSNélio Laranjeiro if (ret != 0) 334e72dd09bSNélio Laranjeiro return ret; 335e72dd09bSNélio Laranjeiro } 336e72dd09bSNélio Laranjeiro } 337e72dd09bSNélio Laranjeiro rte_kvargs_free(kvlist); 338e72dd09bSNélio Laranjeiro return 0; 339e72dd09bSNélio Laranjeiro } 340e72dd09bSNélio Laranjeiro 341771fa900SAdrien Mazarguil static struct eth_driver mlx5_driver; 342771fa900SAdrien Mazarguil 343771fa900SAdrien Mazarguil /** 344771fa900SAdrien Mazarguil * DPDK callback to register a PCI device. 345771fa900SAdrien Mazarguil * 346771fa900SAdrien Mazarguil * This function creates an Ethernet device for each port of a given 347771fa900SAdrien Mazarguil * PCI device. 348771fa900SAdrien Mazarguil * 349771fa900SAdrien Mazarguil * @param[in] pci_drv 350771fa900SAdrien Mazarguil * PCI driver structure (mlx5_driver). 351771fa900SAdrien Mazarguil * @param[in] pci_dev 352771fa900SAdrien Mazarguil * PCI device information. 353771fa900SAdrien Mazarguil * 354771fa900SAdrien Mazarguil * @return 355771fa900SAdrien Mazarguil * 0 on success, negative errno value on failure. 356771fa900SAdrien Mazarguil */ 357771fa900SAdrien Mazarguil static int 358af424af8SShreyansh Jain mlx5_pci_probe(struct rte_pci_driver *pci_drv, struct rte_pci_device *pci_dev) 359771fa900SAdrien Mazarguil { 360771fa900SAdrien Mazarguil struct ibv_device **list; 361771fa900SAdrien Mazarguil struct ibv_device *ibv_dev; 362771fa900SAdrien Mazarguil int err = 0; 363771fa900SAdrien Mazarguil struct ibv_context *attr_ctx = NULL; 364771fa900SAdrien Mazarguil struct ibv_device_attr device_attr; 36585e347dbSNélio Laranjeiro unsigned int sriov; 366e192ef80SYaacov Hazan unsigned int mps; 367771fa900SAdrien Mazarguil int idx; 368771fa900SAdrien Mazarguil int i; 369771fa900SAdrien Mazarguil 370771fa900SAdrien Mazarguil (void)pci_drv; 371771fa900SAdrien Mazarguil assert(pci_drv == &mlx5_driver.pci_drv); 372771fa900SAdrien Mazarguil /* Get mlx5_dev[] index. */ 373771fa900SAdrien Mazarguil idx = mlx5_dev_idx(&pci_dev->addr); 374771fa900SAdrien Mazarguil if (idx == -1) { 375771fa900SAdrien Mazarguil ERROR("this driver cannot support any more adapters"); 376771fa900SAdrien Mazarguil return -ENOMEM; 377771fa900SAdrien Mazarguil } 378771fa900SAdrien Mazarguil DEBUG("using driver device index %d", idx); 379771fa900SAdrien Mazarguil 380771fa900SAdrien Mazarguil /* Save PCI address. */ 381771fa900SAdrien Mazarguil mlx5_dev[idx].pci_addr = pci_dev->addr; 382771fa900SAdrien Mazarguil list = ibv_get_device_list(&i); 383771fa900SAdrien Mazarguil if (list == NULL) { 384771fa900SAdrien Mazarguil assert(errno); 385771fa900SAdrien Mazarguil if (errno == ENOSYS) { 386771fa900SAdrien Mazarguil WARN("cannot list devices, is ib_uverbs loaded?"); 387771fa900SAdrien Mazarguil return 0; 388771fa900SAdrien Mazarguil } 389771fa900SAdrien Mazarguil return -errno; 390771fa900SAdrien Mazarguil } 391771fa900SAdrien Mazarguil assert(i >= 0); 392771fa900SAdrien Mazarguil /* 393771fa900SAdrien Mazarguil * For each listed device, check related sysfs entry against 394771fa900SAdrien Mazarguil * the provided PCI ID. 395771fa900SAdrien Mazarguil */ 396771fa900SAdrien Mazarguil while (i != 0) { 397771fa900SAdrien Mazarguil struct rte_pci_addr pci_addr; 398771fa900SAdrien Mazarguil 399771fa900SAdrien Mazarguil --i; 400771fa900SAdrien Mazarguil DEBUG("checking device \"%s\"", list[i]->name); 401771fa900SAdrien Mazarguil if (mlx5_ibv_device_to_pci_addr(list[i], &pci_addr)) 402771fa900SAdrien Mazarguil continue; 403771fa900SAdrien Mazarguil if ((pci_dev->addr.domain != pci_addr.domain) || 404771fa900SAdrien Mazarguil (pci_dev->addr.bus != pci_addr.bus) || 405771fa900SAdrien Mazarguil (pci_dev->addr.devid != pci_addr.devid) || 406771fa900SAdrien Mazarguil (pci_dev->addr.function != pci_addr.function)) 407771fa900SAdrien Mazarguil continue; 40885e347dbSNélio Laranjeiro sriov = ((pci_dev->id.device_id == 409771fa900SAdrien Mazarguil PCI_DEVICE_ID_MELLANOX_CONNECTX4VF) || 410771fa900SAdrien Mazarguil (pci_dev->id.device_id == 411771fa900SAdrien Mazarguil PCI_DEVICE_ID_MELLANOX_CONNECTX4LXVF)); 412e192ef80SYaacov Hazan /* Multi-packet send is only supported by ConnectX-4 Lx PF. */ 413e192ef80SYaacov Hazan mps = (pci_dev->id.device_id == 414e192ef80SYaacov Hazan PCI_DEVICE_ID_MELLANOX_CONNECTX4LX); 41585e347dbSNélio Laranjeiro INFO("PCI information matches, using device \"%s\"" 41685e347dbSNélio Laranjeiro " (SR-IOV: %s, MPS: %s)", 417e192ef80SYaacov Hazan list[i]->name, 41885e347dbSNélio Laranjeiro sriov ? "true" : "false", 419e192ef80SYaacov Hazan mps ? "true" : "false"); 420771fa900SAdrien Mazarguil attr_ctx = ibv_open_device(list[i]); 421771fa900SAdrien Mazarguil err = errno; 422771fa900SAdrien Mazarguil break; 423771fa900SAdrien Mazarguil } 424771fa900SAdrien Mazarguil if (attr_ctx == NULL) { 425771fa900SAdrien Mazarguil ibv_free_device_list(list); 426771fa900SAdrien Mazarguil switch (err) { 427771fa900SAdrien Mazarguil case 0: 428771fa900SAdrien Mazarguil WARN("cannot access device, is mlx5_ib loaded?"); 429771fa900SAdrien Mazarguil return 0; 430771fa900SAdrien Mazarguil case EINVAL: 431771fa900SAdrien Mazarguil WARN("cannot use device, are drivers up to date?"); 432771fa900SAdrien Mazarguil return 0; 433771fa900SAdrien Mazarguil } 434771fa900SAdrien Mazarguil assert(err > 0); 435771fa900SAdrien Mazarguil return -err; 436771fa900SAdrien Mazarguil } 437771fa900SAdrien Mazarguil ibv_dev = list[i]; 438771fa900SAdrien Mazarguil 439771fa900SAdrien Mazarguil DEBUG("device opened"); 440771fa900SAdrien Mazarguil if (ibv_query_device(attr_ctx, &device_attr)) 441771fa900SAdrien Mazarguil goto error; 442771fa900SAdrien Mazarguil INFO("%u port(s) detected", device_attr.phys_port_cnt); 443771fa900SAdrien Mazarguil 444771fa900SAdrien Mazarguil for (i = 0; i < device_attr.phys_port_cnt; i++) { 445771fa900SAdrien Mazarguil uint32_t port = i + 1; /* ports are indexed from one */ 446771fa900SAdrien Mazarguil uint32_t test = (1 << i); 447771fa900SAdrien Mazarguil struct ibv_context *ctx = NULL; 448771fa900SAdrien Mazarguil struct ibv_port_attr port_attr; 449771fa900SAdrien Mazarguil struct ibv_pd *pd = NULL; 450771fa900SAdrien Mazarguil struct priv *priv = NULL; 451771fa900SAdrien Mazarguil struct rte_eth_dev *eth_dev; 452771fa900SAdrien Mazarguil struct ibv_exp_device_attr exp_device_attr; 453771fa900SAdrien Mazarguil struct ether_addr mac; 45485e347dbSNélio Laranjeiro uint16_t num_vfs = 0; 455771fa900SAdrien Mazarguil 45695e16ef3SNelio Laranjeiro exp_device_attr.comp_mask = 45795e16ef3SNelio Laranjeiro IBV_EXP_DEVICE_ATTR_EXP_CAP_FLAGS | 458f3db9489SYaacov Hazan IBV_EXP_DEVICE_ATTR_RX_HASH | 459f3db9489SYaacov Hazan IBV_EXP_DEVICE_ATTR_VLAN_OFFLOADS | 4604d803a72SOlga Shern IBV_EXP_DEVICE_ATTR_RX_PAD_END_ALIGN | 461f3db9489SYaacov Hazan 0; 462771fa900SAdrien Mazarguil 463771fa900SAdrien Mazarguil DEBUG("using port %u (%08" PRIx32 ")", port, test); 464771fa900SAdrien Mazarguil 465771fa900SAdrien Mazarguil ctx = ibv_open_device(ibv_dev); 466771fa900SAdrien Mazarguil if (ctx == NULL) 467771fa900SAdrien Mazarguil goto port_error; 468771fa900SAdrien Mazarguil 469771fa900SAdrien Mazarguil /* Check port status. */ 470771fa900SAdrien Mazarguil err = ibv_query_port(ctx, port, &port_attr); 471771fa900SAdrien Mazarguil if (err) { 472771fa900SAdrien Mazarguil ERROR("port query failed: %s", strerror(err)); 473771fa900SAdrien Mazarguil goto port_error; 474771fa900SAdrien Mazarguil } 4751371f4dfSOr Ami 4761371f4dfSOr Ami if (port_attr.link_layer != IBV_LINK_LAYER_ETHERNET) { 4771371f4dfSOr Ami ERROR("port %d is not configured in Ethernet mode", 4781371f4dfSOr Ami port); 4791371f4dfSOr Ami goto port_error; 4801371f4dfSOr Ami } 4811371f4dfSOr Ami 482771fa900SAdrien Mazarguil if (port_attr.state != IBV_PORT_ACTIVE) 483771fa900SAdrien Mazarguil DEBUG("port %d is not active: \"%s\" (%d)", 484771fa900SAdrien Mazarguil port, ibv_port_state_str(port_attr.state), 485771fa900SAdrien Mazarguil port_attr.state); 486771fa900SAdrien Mazarguil 487771fa900SAdrien Mazarguil /* Allocate protection domain. */ 488771fa900SAdrien Mazarguil pd = ibv_alloc_pd(ctx); 489771fa900SAdrien Mazarguil if (pd == NULL) { 490771fa900SAdrien Mazarguil ERROR("PD allocation failure"); 491771fa900SAdrien Mazarguil err = ENOMEM; 492771fa900SAdrien Mazarguil goto port_error; 493771fa900SAdrien Mazarguil } 494771fa900SAdrien Mazarguil 495771fa900SAdrien Mazarguil mlx5_dev[idx].ports |= test; 496771fa900SAdrien Mazarguil 497771fa900SAdrien Mazarguil /* from rte_ethdev.c */ 498771fa900SAdrien Mazarguil priv = rte_zmalloc("ethdev private structure", 499771fa900SAdrien Mazarguil sizeof(*priv), 500771fa900SAdrien Mazarguil RTE_CACHE_LINE_SIZE); 501771fa900SAdrien Mazarguil if (priv == NULL) { 502771fa900SAdrien Mazarguil ERROR("priv allocation failure"); 503771fa900SAdrien Mazarguil err = ENOMEM; 504771fa900SAdrien Mazarguil goto port_error; 505771fa900SAdrien Mazarguil } 506771fa900SAdrien Mazarguil 507771fa900SAdrien Mazarguil priv->ctx = ctx; 508771fa900SAdrien Mazarguil priv->device_attr = device_attr; 509771fa900SAdrien Mazarguil priv->port = port; 510771fa900SAdrien Mazarguil priv->pd = pd; 511771fa900SAdrien Mazarguil priv->mtu = ETHER_MTU; 512230189d9SNélio Laranjeiro priv->mps = mps; /* Enable MPW by default if supported. */ 51399c12dccSNélio Laranjeiro priv->cqe_comp = 1; /* Enable compression by default. */ 51413a1317dSJan Viktorin err = mlx5_args(priv, pci_dev->device.devargs); 515e72dd09bSNélio Laranjeiro if (err) { 516e72dd09bSNélio Laranjeiro ERROR("failed to process device arguments: %s", 517e72dd09bSNélio Laranjeiro strerror(err)); 518e72dd09bSNélio Laranjeiro goto port_error; 519e72dd09bSNélio Laranjeiro } 520771fa900SAdrien Mazarguil if (ibv_exp_query_device(ctx, &exp_device_attr)) { 521771fa900SAdrien Mazarguil ERROR("ibv_exp_query_device() failed"); 522771fa900SAdrien Mazarguil goto port_error; 523771fa900SAdrien Mazarguil } 524771fa900SAdrien Mazarguil 525771fa900SAdrien Mazarguil priv->hw_csum = 526771fa900SAdrien Mazarguil ((exp_device_attr.exp_device_cap_flags & 527771fa900SAdrien Mazarguil IBV_EXP_DEVICE_RX_CSUM_TCP_UDP_PKT) && 528771fa900SAdrien Mazarguil (exp_device_attr.exp_device_cap_flags & 529771fa900SAdrien Mazarguil IBV_EXP_DEVICE_RX_CSUM_IP_PKT)); 530771fa900SAdrien Mazarguil DEBUG("checksum offloading is %ssupported", 531771fa900SAdrien Mazarguil (priv->hw_csum ? "" : "not ")); 532771fa900SAdrien Mazarguil 533771fa900SAdrien Mazarguil priv->hw_csum_l2tun = !!(exp_device_attr.exp_device_cap_flags & 534771fa900SAdrien Mazarguil IBV_EXP_DEVICE_VXLAN_SUPPORT); 535771fa900SAdrien Mazarguil DEBUG("L2 tunnel checksum offloads are %ssupported", 536771fa900SAdrien Mazarguil (priv->hw_csum_l2tun ? "" : "not ")); 537771fa900SAdrien Mazarguil 53813d57bd5SAdrien Mazarguil priv->ind_table_max_size = exp_device_attr.rx_hash_caps.max_rwq_indirection_table_size; 53913d57bd5SAdrien Mazarguil /* Remove this check once DPDK supports larger/variable 54013d57bd5SAdrien Mazarguil * indirection tables. */ 54113d57bd5SAdrien Mazarguil if (priv->ind_table_max_size > (unsigned int)RSS_INDIRECTION_TABLE_SIZE) 54213d57bd5SAdrien Mazarguil priv->ind_table_max_size = RSS_INDIRECTION_TABLE_SIZE; 54395e16ef3SNelio Laranjeiro DEBUG("maximum RX indirection table size is %u", 54495e16ef3SNelio Laranjeiro priv->ind_table_max_size); 545f3db9489SYaacov Hazan priv->hw_vlan_strip = !!(exp_device_attr.wq_vlan_offloads_cap & 546f3db9489SYaacov Hazan IBV_EXP_RECEIVE_WQ_CVLAN_STRIP); 547f3db9489SYaacov Hazan DEBUG("VLAN stripping is %ssupported", 548f3db9489SYaacov Hazan (priv->hw_vlan_strip ? "" : "not ")); 54995e16ef3SNelio Laranjeiro 5504d326709SOlga Shern priv->hw_fcs_strip = !!(exp_device_attr.exp_device_cap_flags & 5514d326709SOlga Shern IBV_EXP_DEVICE_SCATTER_FCS); 5524d326709SOlga Shern DEBUG("FCS stripping configuration is %ssupported", 5534d326709SOlga Shern (priv->hw_fcs_strip ? "" : "not ")); 5544d326709SOlga Shern 5554d803a72SOlga Shern priv->hw_padding = !!exp_device_attr.rx_pad_end_addr_align; 5564d803a72SOlga Shern DEBUG("hardware RX end alignment padding is %ssupported", 5574d803a72SOlga Shern (priv->hw_padding ? "" : "not ")); 5584d803a72SOlga Shern 55985e347dbSNélio Laranjeiro priv_get_num_vfs(priv, &num_vfs); 56085e347dbSNélio Laranjeiro priv->sriov = (num_vfs || sriov); 561230189d9SNélio Laranjeiro if (priv->mps && !mps) { 562230189d9SNélio Laranjeiro ERROR("multi-packet send not supported on this device" 563230189d9SNélio Laranjeiro " (" MLX5_TXQ_MPW_EN ")"); 564230189d9SNélio Laranjeiro err = ENOTSUP; 565230189d9SNélio Laranjeiro goto port_error; 566230189d9SNélio Laranjeiro } 5670573873dSNelio Laranjeiro /* Allocate and register default RSS hash keys. */ 5680573873dSNelio Laranjeiro priv->rss_conf = rte_calloc(__func__, hash_rxq_init_n, 5690573873dSNelio Laranjeiro sizeof((*priv->rss_conf)[0]), 0); 5700573873dSNelio Laranjeiro if (priv->rss_conf == NULL) { 5710573873dSNelio Laranjeiro err = ENOMEM; 5720573873dSNelio Laranjeiro goto port_error; 5730573873dSNelio Laranjeiro } 5742f97422eSNelio Laranjeiro err = rss_hash_rss_conf_new_key(priv, 5752f97422eSNelio Laranjeiro rss_hash_default_key, 5760573873dSNelio Laranjeiro rss_hash_default_key_len, 5770573873dSNelio Laranjeiro ETH_RSS_PROTO_MASK); 5782f97422eSNelio Laranjeiro if (err) 5792f97422eSNelio Laranjeiro goto port_error; 580771fa900SAdrien Mazarguil /* Configure the first MAC address by default. */ 581771fa900SAdrien Mazarguil if (priv_get_mac(priv, &mac.addr_bytes)) { 582771fa900SAdrien Mazarguil ERROR("cannot get MAC address, is mlx5_en loaded?" 583771fa900SAdrien Mazarguil " (errno: %s)", strerror(errno)); 584771fa900SAdrien Mazarguil goto port_error; 585771fa900SAdrien Mazarguil } 586771fa900SAdrien Mazarguil INFO("port %u MAC address is %02x:%02x:%02x:%02x:%02x:%02x", 587771fa900SAdrien Mazarguil priv->port, 588771fa900SAdrien Mazarguil mac.addr_bytes[0], mac.addr_bytes[1], 589771fa900SAdrien Mazarguil mac.addr_bytes[2], mac.addr_bytes[3], 590771fa900SAdrien Mazarguil mac.addr_bytes[4], mac.addr_bytes[5]); 5910497ddaaSYaacov Hazan /* Register MAC address. */ 592771fa900SAdrien Mazarguil claim_zero(priv_mac_addr_add(priv, 0, 593771fa900SAdrien Mazarguil (const uint8_t (*)[ETHER_ADDR_LEN]) 594771fa900SAdrien Mazarguil mac.addr_bytes)); 59576f5c99eSYaacov Hazan /* Initialize FD filters list. */ 59676f5c99eSYaacov Hazan err = fdir_init_filters_list(priv); 59776f5c99eSYaacov Hazan if (err) 59876f5c99eSYaacov Hazan goto port_error; 599771fa900SAdrien Mazarguil #ifndef NDEBUG 600771fa900SAdrien Mazarguil { 601771fa900SAdrien Mazarguil char ifname[IF_NAMESIZE]; 602771fa900SAdrien Mazarguil 603771fa900SAdrien Mazarguil if (priv_get_ifname(priv, &ifname) == 0) 604771fa900SAdrien Mazarguil DEBUG("port %u ifname is \"%s\"", 605771fa900SAdrien Mazarguil priv->port, ifname); 606771fa900SAdrien Mazarguil else 607771fa900SAdrien Mazarguil DEBUG("port %u ifname is unknown", priv->port); 608771fa900SAdrien Mazarguil } 609771fa900SAdrien Mazarguil #endif 610771fa900SAdrien Mazarguil /* Get actual MTU if possible. */ 611771fa900SAdrien Mazarguil priv_get_mtu(priv, &priv->mtu); 612771fa900SAdrien Mazarguil DEBUG("port %u MTU is %u", priv->port, priv->mtu); 613771fa900SAdrien Mazarguil 614771fa900SAdrien Mazarguil /* from rte_ethdev.c */ 615771fa900SAdrien Mazarguil { 616771fa900SAdrien Mazarguil char name[RTE_ETH_NAME_MAX_LEN]; 617771fa900SAdrien Mazarguil 618771fa900SAdrien Mazarguil snprintf(name, sizeof(name), "%s port %u", 619771fa900SAdrien Mazarguil ibv_get_device_name(ibv_dev), port); 6206751f6deSDavid Marchand eth_dev = rte_eth_dev_allocate(name); 621771fa900SAdrien Mazarguil } 622771fa900SAdrien Mazarguil if (eth_dev == NULL) { 623771fa900SAdrien Mazarguil ERROR("can not allocate rte ethdev"); 624771fa900SAdrien Mazarguil err = ENOMEM; 625771fa900SAdrien Mazarguil goto port_error; 626771fa900SAdrien Mazarguil } 627771fa900SAdrien Mazarguil 628a48deadaSOr Ami /* Secondary processes have to use local storage for their 629a48deadaSOr Ami * private data as well as a copy of eth_dev->data, but this 630a48deadaSOr Ami * pointer must not be modified before burst functions are 631a48deadaSOr Ami * actually called. */ 632a48deadaSOr Ami if (mlx5_is_secondary()) { 633a48deadaSOr Ami struct mlx5_secondary_data *sd = 634a48deadaSOr Ami &mlx5_secondary_data[eth_dev->data->port_id]; 635a48deadaSOr Ami sd->primary_priv = eth_dev->data->dev_private; 636a48deadaSOr Ami if (sd->primary_priv == NULL) { 637a48deadaSOr Ami ERROR("no private data for port %u", 638a48deadaSOr Ami eth_dev->data->port_id); 639a48deadaSOr Ami err = EINVAL; 640a48deadaSOr Ami goto port_error; 641a48deadaSOr Ami } 642a48deadaSOr Ami sd->shared_dev_data = eth_dev->data; 643a48deadaSOr Ami rte_spinlock_init(&sd->lock); 644a48deadaSOr Ami memcpy(sd->data.name, sd->shared_dev_data->name, 645a48deadaSOr Ami sizeof(sd->data.name)); 646a48deadaSOr Ami sd->data.dev_private = priv; 647a48deadaSOr Ami sd->data.rx_mbuf_alloc_failed = 0; 648a48deadaSOr Ami sd->data.mtu = ETHER_MTU; 649a48deadaSOr Ami sd->data.port_id = sd->shared_dev_data->port_id; 650a48deadaSOr Ami sd->data.mac_addrs = priv->mac; 651a48deadaSOr Ami eth_dev->tx_pkt_burst = mlx5_tx_burst_secondary_setup; 652a48deadaSOr Ami eth_dev->rx_pkt_burst = mlx5_rx_burst_secondary_setup; 653a48deadaSOr Ami } else { 654771fa900SAdrien Mazarguil eth_dev->data->dev_private = priv; 655771fa900SAdrien Mazarguil eth_dev->data->rx_mbuf_alloc_failed = 0; 656771fa900SAdrien Mazarguil eth_dev->data->mtu = ETHER_MTU; 657a48deadaSOr Ami eth_dev->data->mac_addrs = priv->mac; 658a48deadaSOr Ami } 659771fa900SAdrien Mazarguil 660a48deadaSOr Ami eth_dev->pci_dev = pci_dev; 661a48deadaSOr Ami rte_eth_copy_pci_info(eth_dev, pci_dev); 662a48deadaSOr Ami eth_dev->driver = &mlx5_driver; 663771fa900SAdrien Mazarguil priv->dev = eth_dev; 664771fa900SAdrien Mazarguil eth_dev->dev_ops = &mlx5_dev_ops; 665a48deadaSOr Ami 666198a3c33SNelio Laranjeiro TAILQ_INIT(ð_dev->link_intr_cbs); 667771fa900SAdrien Mazarguil 668771fa900SAdrien Mazarguil /* Bring Ethernet device up. */ 669771fa900SAdrien Mazarguil DEBUG("forcing Ethernet interface up"); 670771fa900SAdrien Mazarguil priv_set_flags(priv, ~IFF_UP, IFF_UP); 6710d1e2f8dSOlga Shern mlx5_link_update_unlocked(priv->dev, 1); 672771fa900SAdrien Mazarguil continue; 673771fa900SAdrien Mazarguil 674771fa900SAdrien Mazarguil port_error: 6752f636ae5SOr Ami if (priv) { 6762f97422eSNelio Laranjeiro rte_free(priv->rss_conf); 677771fa900SAdrien Mazarguil rte_free(priv); 6782f636ae5SOr Ami } 679771fa900SAdrien Mazarguil if (pd) 680771fa900SAdrien Mazarguil claim_zero(ibv_dealloc_pd(pd)); 681771fa900SAdrien Mazarguil if (ctx) 682771fa900SAdrien Mazarguil claim_zero(ibv_close_device(ctx)); 683771fa900SAdrien Mazarguil break; 684771fa900SAdrien Mazarguil } 685771fa900SAdrien Mazarguil 686771fa900SAdrien Mazarguil /* 687771fa900SAdrien Mazarguil * XXX if something went wrong in the loop above, there is a resource 688771fa900SAdrien Mazarguil * leak (ctx, pd, priv, dpdk ethdev) but we can do nothing about it as 689771fa900SAdrien Mazarguil * long as the dpdk does not provide a way to deallocate a ethdev and a 690771fa900SAdrien Mazarguil * way to enumerate the registered ethdevs to free the previous ones. 691771fa900SAdrien Mazarguil */ 692771fa900SAdrien Mazarguil 693771fa900SAdrien Mazarguil /* no port found, complain */ 694771fa900SAdrien Mazarguil if (!mlx5_dev[idx].ports) { 695771fa900SAdrien Mazarguil err = ENODEV; 696771fa900SAdrien Mazarguil goto error; 697771fa900SAdrien Mazarguil } 698771fa900SAdrien Mazarguil 699771fa900SAdrien Mazarguil error: 700771fa900SAdrien Mazarguil if (attr_ctx) 701771fa900SAdrien Mazarguil claim_zero(ibv_close_device(attr_ctx)); 702771fa900SAdrien Mazarguil if (list) 703771fa900SAdrien Mazarguil ibv_free_device_list(list); 704771fa900SAdrien Mazarguil assert(err >= 0); 705771fa900SAdrien Mazarguil return -err; 706771fa900SAdrien Mazarguil } 707771fa900SAdrien Mazarguil 708771fa900SAdrien Mazarguil static const struct rte_pci_id mlx5_pci_id_map[] = { 709771fa900SAdrien Mazarguil { 7101d1bc870SNélio Laranjeiro RTE_PCI_DEVICE(PCI_VENDOR_ID_MELLANOX, 7111d1bc870SNélio Laranjeiro PCI_DEVICE_ID_MELLANOX_CONNECTX4) 712771fa900SAdrien Mazarguil }, 713771fa900SAdrien Mazarguil { 7141d1bc870SNélio Laranjeiro RTE_PCI_DEVICE(PCI_VENDOR_ID_MELLANOX, 7151d1bc870SNélio Laranjeiro PCI_DEVICE_ID_MELLANOX_CONNECTX4VF) 716771fa900SAdrien Mazarguil }, 717771fa900SAdrien Mazarguil { 7181d1bc870SNélio Laranjeiro RTE_PCI_DEVICE(PCI_VENDOR_ID_MELLANOX, 7191d1bc870SNélio Laranjeiro PCI_DEVICE_ID_MELLANOX_CONNECTX4LX) 720771fa900SAdrien Mazarguil }, 721771fa900SAdrien Mazarguil { 7221d1bc870SNélio Laranjeiro RTE_PCI_DEVICE(PCI_VENDOR_ID_MELLANOX, 7231d1bc870SNélio Laranjeiro PCI_DEVICE_ID_MELLANOX_CONNECTX4LXVF) 724771fa900SAdrien Mazarguil }, 725771fa900SAdrien Mazarguil { 726771fa900SAdrien Mazarguil .vendor_id = 0 727771fa900SAdrien Mazarguil } 728771fa900SAdrien Mazarguil }; 729771fa900SAdrien Mazarguil 730771fa900SAdrien Mazarguil static struct eth_driver mlx5_driver = { 731771fa900SAdrien Mazarguil .pci_drv = { 7322f3193cfSJan Viktorin .driver = { 7332f3193cfSJan Viktorin .name = MLX5_DRIVER_NAME 7342f3193cfSJan Viktorin }, 735771fa900SAdrien Mazarguil .id_table = mlx5_pci_id_map, 736af424af8SShreyansh Jain .probe = mlx5_pci_probe, 737198a3c33SNelio Laranjeiro .drv_flags = RTE_PCI_DRV_INTR_LSC, 738771fa900SAdrien Mazarguil }, 739771fa900SAdrien Mazarguil .dev_private_size = sizeof(struct priv) 740771fa900SAdrien Mazarguil }; 741771fa900SAdrien Mazarguil 742771fa900SAdrien Mazarguil /** 743771fa900SAdrien Mazarguil * Driver initialization routine. 744771fa900SAdrien Mazarguil */ 745c830cb29SDavid Marchand RTE_INIT(rte_mlx5_pmd_init); 746c830cb29SDavid Marchand static void 747c830cb29SDavid Marchand rte_mlx5_pmd_init(void) 748771fa900SAdrien Mazarguil { 749771fa900SAdrien Mazarguil /* 750771fa900SAdrien Mazarguil * RDMAV_HUGEPAGES_SAFE tells ibv_fork_init() we intend to use 751771fa900SAdrien Mazarguil * huge pages. Calling ibv_fork_init() during init allows 752771fa900SAdrien Mazarguil * applications to use fork() safely for purposes other than 753771fa900SAdrien Mazarguil * using this PMD, which is not supported in forked processes. 754771fa900SAdrien Mazarguil */ 755771fa900SAdrien Mazarguil setenv("RDMAV_HUGEPAGES_SAFE", "1", 1); 756771fa900SAdrien Mazarguil ibv_fork_init(); 757771fa900SAdrien Mazarguil rte_eal_pci_register(&mlx5_driver.pci_drv); 758771fa900SAdrien Mazarguil } 759771fa900SAdrien Mazarguil 76001f19227SShreyansh Jain RTE_PMD_EXPORT_NAME(net_mlx5, __COUNTER__); 76101f19227SShreyansh Jain RTE_PMD_REGISTER_PCI_TABLE(net_mlx5, mlx5_pci_id_map); 762*0880c401SOlivier Matz RTE_PMD_REGISTER_KMOD_DEP(net_mlx5, "* ib_uverbs & mlx5_core & mlx5_ib"); 763